February 2022 - Alsa-devel - mailman.alsa-project.org

jack: implement pcm operation sw_params
by GitHub pull_request - opened 21 Feb '22

21 Feb '22

alsa-project/alsa-plugins pull request #43 was opened from aditpape: to reflect an updated avail_min value during runtime Signed-off-by: Andreas Pape <apape(a)de.adit-jv.com> Request URL : https://github.com/alsa-project/alsa-plugins/pull/43 Patch URL : https://github.com/alsa-project/alsa-plugins/pull/43.patch Repository URL: https://github.com/alsa-project/alsa-plugins

1 0

[PATCH] ASoC: mediatek: mt8195: enable apll tuner
by Trevor Wu 21 Feb '22

21 Feb '22

Normally, the clock source of audio module is either 26M or APLL1/APLL2, but APLL1/APLL2 are not the multiple of 26M. In the patch, APLL1 and APLL2 tuners are enabled to handle sample rate mismatch when the data path crosses two different clock domains. Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> --- sound/soc/mediatek/mt8195/mt8195-afe-clk.c | 282 ++++++++++++++++++++- sound/soc/mediatek/mt8195/mt8195-afe-clk.h | 11 + sound/soc/mediatek/mt8195/mt8195-afe-pcm.c | 3 - 3 files changed, 292 insertions(+), 4 deletions(-) diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c index c2543f4cffb7..efd5cc364a35 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c @@ -40,6 +40,8 @@ static const char *aud_clks[MT8195_CLK_NUM] = { [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp", /* afe clock gate */ [MT8195_CLK_AUD_AFE] = "aud_afe", + [MT8195_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner", + [MT8195_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner", [MT8195_CLK_AUD_APLL] = "aud_apll", [MT8195_CLK_AUD_APLL2] = "aud_apll2", [MT8195_CLK_AUD_DAC] = "aud_dac", @@ -77,6 +79,268 @@ static const char *aud_clks[MT8195_CLK_NUM] = { [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", }; +struct mt8195_afe_tuner_cfg { + unsigned int id; + int apll_div_reg; + unsigned int apll_div_shift; + unsigned int apll_div_maskbit; + unsigned int apll_div_default; + int ref_ck_sel_reg; + unsigned int ref_ck_sel_shift; + unsigned int ref_ck_sel_maskbit; + unsigned int ref_ck_sel_default; + int tuner_en_reg; + unsigned int tuner_en_shift; + unsigned int tuner_en_maskbit; + int upper_bound_reg; + unsigned int upper_bound_shift; + unsigned int upper_bound_maskbit; + unsigned int upper_bound_default; + spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/ + int ref_cnt; +}; + +static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = { + [MT8195_AUD_PLL1] = { + .id = MT8195_AUD_PLL1, + .apll_div_reg = AFE_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0xf, + .apll_div_default = 0x7, + .ref_ck_sel_reg = AFE_APLL_TUNER_CFG, + .ref_ck_sel_shift = 1, + .ref_ck_sel_maskbit = 0x3, + .ref_ck_sel_default = 0x2, + .tuner_en_reg = AFE_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_APLL_TUNER_CFG, + .upper_bound_shift = 8, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x2, + }, + [MT8195_AUD_PLL2] = { + .id = MT8195_AUD_PLL2, + .apll_div_reg = AFE_APLL_TUNER_CFG1, + .apll_div_shift = 4, + .apll_div_maskbit = 0xf, + .apll_div_default = 0x7, + .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1, + .ref_ck_sel_shift = 1, + .ref_ck_sel_maskbit = 0x3, + .ref_ck_sel_default = 0x1, + .tuner_en_reg = AFE_APLL_TUNER_CFG1, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_APLL_TUNER_CFG1, + .upper_bound_shift = 8, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x2, + }, + [MT8195_AUD_PLL3] = { + .id = MT8195_AUD_PLL3, + .apll_div_reg = AFE_EARC_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0x3f, + .apll_div_default = 0x3, + .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG, + .ref_ck_sel_shift = 24, + .ref_ck_sel_maskbit = 0x3, + .ref_ck_sel_default = 0x0, + .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG, + .upper_bound_shift = 12, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x4, + }, + [MT8195_AUD_PLL4] = { + .id = MT8195_AUD_PLL4, + .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0x3f, + .apll_div_default = 0x7, + .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1, + .ref_ck_sel_shift = 8, + .ref_ck_sel_maskbit = 0x1, + .ref_ck_sel_default = 0, + .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG, + .upper_bound_shift = 12, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x4, + }, + [MT8195_AUD_PLL5] = { + .id = MT8195_AUD_PLL5, + .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0x3f, + .apll_div_default = 0x3, + .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG, + .ref_ck_sel_shift = 24, + .ref_ck_sel_maskbit = 0x1, + .ref_ck_sel_default = 0, + .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG, + .upper_bound_shift = 12, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x4, + }, +}; + +static struct mt8195_afe_tuner_cfg *mt8195_afe_found_apll_tuner(unsigned int id) +{ + if (id >= MT8195_AUD_PLL_NUM) + return NULL; + + return &mt8195_afe_tuner_cfgs[id]; +} + +static int mt8195_afe_init_apll_tuner(unsigned int id) +{ + struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + + if (!cfg) + return -EINVAL; + + cfg->ref_cnt = 0; + spin_lock_init(&cfg->ctrl_lock); + + return 0; +} + +static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe, + unsigned int id) +{ + const struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + + if (!cfg) + return -EINVAL; + + regmap_update_bits(afe->regmap, cfg->apll_div_reg, + cfg->apll_div_maskbit << cfg->apll_div_shift, + cfg->apll_div_default << cfg->apll_div_shift); + + regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg, + cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift, + cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift); + + regmap_update_bits(afe->regmap, cfg->upper_bound_reg, + cfg->upper_bound_maskbit << cfg->upper_bound_shift, + cfg->upper_bound_default << cfg->upper_bound_shift); + + return 0; +} + +static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_private *afe_priv = afe->platform_priv; + + switch (id) { + case MT8195_AUD_PLL1: + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); + break; + case MT8195_AUD_PLL2: + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); + break; + default: + break; + } + + return 0; +} + +static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_private *afe_priv = afe->platform_priv; + + switch (id) { + case MT8195_AUD_PLL1: + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); + break; + case MT8195_AUD_PLL2: + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); + break; + default: + break; + } + + return 0; +} + +static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + unsigned long flags; + int ret = 0; + + if (!cfg) + return -EINVAL; + + ret = mt8195_afe_setup_apll_tuner(afe, id); + if (ret) + return ret; + + ret = mt8195_afe_enable_tuner_clk(afe, id); + if (ret) + return ret; + + spin_lock_irqsave(&cfg->ctrl_lock, flags); + + cfg->ref_cnt++; + if (cfg->ref_cnt == 1) + regmap_update_bits(afe->regmap, + cfg->tuner_en_reg, + cfg->tuner_en_maskbit << cfg->tuner_en_shift, + 1 << cfg->tuner_en_shift); + + spin_unlock_irqrestore(&cfg->ctrl_lock, flags); + + return ret; +} + +static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + unsigned long flags; + int ret = 0; + + if (!cfg) + return -EINVAL; + + spin_lock_irqsave(&cfg->ctrl_lock, flags); + + cfg->ref_cnt--; + if (cfg->ref_cnt == 0) + regmap_update_bits(afe->regmap, + cfg->tuner_en_reg, + cfg->tuner_en_maskbit << cfg->tuner_en_shift, + 0 << cfg->tuner_en_shift); + else if (cfg->ref_cnt < 0) + cfg->ref_cnt = 0; + + spin_unlock_irqrestore(&cfg->ctrl_lock, flags); + + ret = mt8195_afe_disable_tuner_clk(afe, id); + if (ret) + return ret; + + return ret; +} + int mt8195_afe_get_mclk_source_clk_id(int sel) { switch (sel) { @@ -113,7 +377,7 @@ int mt8195_afe_get_default_mclk_source_by_rate(int rate) int mt8195_afe_init_clock(struct mtk_base_afe *afe) { struct mt8195_afe_private *afe_priv = afe->platform_priv; - int i; + int i, ret; mt8195_audsys_clk_register(afe); @@ -133,6 +397,16 @@ int mt8195_afe_init_clock(struct mtk_base_afe *afe) } } + /* initial tuner */ + for (i = 0; i < MT8195_AUD_PLL_NUM; i++) { + ret = mt8195_afe_init_apll_tuner(i); + if (ret) { + dev_dbg(afe->dev, "%s(), init apll_tuner%d failed", + __func__, (i + 1)); + return -EINVAL; + } + } + return 0; } @@ -428,11 +702,17 @@ int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe) mt8195_afe_enable_afe_on(afe); + mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1); + mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2); + return 0; } int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe) { + mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2); + mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1); + mt8195_afe_disable_afe_on(afe); mt8195_afe_disable_timing_sys(afe); diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.h b/sound/soc/mediatek/mt8195/mt8195-afe-clk.h index f8e6eeb29a89..40663e31becd 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.h +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.h @@ -35,6 +35,8 @@ enum { MT8195_CLK_INFRA_AO_AUDIO_26M_B, MT8195_CLK_SCP_ADSP_AUDIODSP, MT8195_CLK_AUD_AFE, + MT8195_CLK_AUD_APLL1_TUNER, + MT8195_CLK_AUD_APLL2_TUNER, MT8195_CLK_AUD_APLL, MT8195_CLK_AUD_APLL2, MT8195_CLK_AUD_DAC, @@ -84,6 +86,15 @@ enum { MT8195_MCK_SEL_NUM, }; +enum { + MT8195_AUD_PLL1, + MT8195_AUD_PLL2, + MT8195_AUD_PLL3, + MT8195_AUD_PLL4, + MT8195_AUD_PLL5, + MT8195_AUD_PLL_NUM, +}; + struct mtk_base_afe; int mt8195_afe_get_mclk_source_clk_id(int sel); diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c b/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c index e425f868476a..b77c2ba5a629 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c @@ -2583,8 +2583,6 @@ static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg) case AFE_IRQ3_CON_MON: case AFE_IRQ_MCU_MON2: case ADSP_IRQ_STATUS: - case AFE_APLL_TUNER_CFG: - case AFE_APLL_TUNER_CFG1: case AUDIO_TOP_STA0: case AUDIO_TOP_STA1: case AFE_GAIN1_CUR: @@ -2623,7 +2621,6 @@ static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg) case SPDIFIN_USERCODE10: case SPDIFIN_USERCODE11: case SPDIFIN_USERCODE12: - case AFE_SPDIFIN_APLL_TUNER_CFG: case AFE_LINEIN_APLL_TUNER_MON: case AFE_EARC_APLL_TUNER_MON: case AFE_CM0_MON: -- 2.18.0

2 1

[PATCH v2] ASoC: SOF: Intel: Add topology overwrite for Felwinter
by Brent Lu 21 Feb '22

21 Feb '22

From: Ajye Huang <ajye_huang(a)compal.corp-partner.google.com> The Felwinter uses four max98360a amplifiers on corresponding CH0~CH3. There are four amps on the board connecting to headphone to SSP0 port, amp to SSP1,and the DAI format would be DSP_A,8-slots, 32 bit slot-width. CH0: L(Woofer), CH1:R(Woofer), CH2:L(Tweeter), CH3:R(Tweeter) Signed-off-by: Ajye Huang <ajye_huang(a)compal.corp-partner.google.com> Signed-off-by: Brent Lu <brent.lu(a)intel.com> Reviewed-by: Curtis Malainey <cujomalainey(a)chromium.org> Reviewed-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> --- sound/soc/sof/sof-pci-dev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/soc/sof/sof-pci-dev.c b/sound/soc/sof/sof-pci-dev.c index 20c6ca37dbc4..61f2afd54c3e 100644 --- a/sound/soc/sof/sof-pci-dev.c +++ b/sound/soc/sof/sof-pci-dev.c @@ -67,6 +67,14 @@ static const struct dmi_system_id sof_tplg_table[] = { }, .driver_data = "sof-adl-max98390-ssp2-rt5682-ssp0.tplg", }, + { + .callback = sof_tplg_cb, + .matches = { + DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"), + DMI_MATCH(DMI_OEM_STRING, "AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY"), + }, + .driver_data = "sof-adl-max98360a-rt5682-2way.tplg", + }, {} }; -- 2.25.1

2 1

[PATCH] ASoC: SOF: Intel: Add topology overwrite for Felwinter
by Brent Lu 21 Feb '22

21 Feb '22

From: Ajye Huang <ajye_huang(a)compal.corp-partner.google.com> The Felwinter uses four max98360a amplifiers on corresponding CH0~CH3. There are four amps on the board connecting to headphone to SSP0 port, amp to SSP1,and the DAI format would be DSP_A,8-slots, 32 bit slot-width. CH0: L(Woofer), CH1:R(Woofer), CH2:L(Tweeter), CH3:R(Tweeter) Signed-off-by: Ajye Huang <ajye_huang(a)compal.corp-partner.google.com> Signed-off-by: Brent Lu <brent.lu(a)intel.com> --- sound/soc/sof/sof-pci-dev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/soc/sof/sof-pci-dev.c b/sound/soc/sof/sof-pci-dev.c index 20c6ca37dbc4..61f2afd54c3e 100644 --- a/sound/soc/sof/sof-pci-dev.c +++ b/sound/soc/sof/sof-pci-dev.c @@ -67,6 +67,14 @@ static const struct dmi_system_id sof_tplg_table[] = { }, .driver_data = "sof-adl-max98390-ssp2-rt5682-ssp0.tplg", }, + { + .callback = sof_tplg_cb, + .matches = { + DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"), + DMI_MATCH(DMI_OEM_STRING, "AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY"), + }, + .driver_data = "sof-adl-max98360a-rt5682-2way.tplg", + }, {} }; -- 2.25.1

4 4

Codec without controls in device tree
by Sascha Hauer 21 Feb '22

21 Feb '22

Hi, I have several i.MX8 boards here which have codecs connected to them which are really just plane D/A converters without any control interface like a pcm1754 or a pcm4104 in hardware mode. Currently we use the simple-audio-card OF driver with custom codec code in sound/soc/codecs/. The codec does nothing except specifying desired rates, channels and formats. Is this the way to go or is there some device tree solution to get rid of the codec? Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2 1

Asking for information about ALSA's kselftest
by Giacomo Guiduzzi 21 Feb '22

21 Feb '22

Good morning Mr. Broonie and users of the alsa-devel mailing list, I’m a student at the University of Modena and Reggio Emilia. I am working at the Kernel Hacking course’s exam, a course kept by Paolo Valente which introduces students to the world of the Linux kernel and its magic. I was taking a look at the kernel’s kselftests from Linus Torvald’s repository to find some test to fix for the exam and I stumbled upon the ALSA’s selftest, which I’ve passed the last few days on, debugging and exploring. During the execution the test goes as it should except for two or three tests. Until now I’ve tried understanding test 71, which sometimes succeeds and sometimes fails, and test 72. I have no previous knowledge of how ALSA works as I’m completely new to the kselftests and the kernel in general. Test 71 gives the following output: # Surround Playback Volume.0 expected 0 but read 1, is_volatile 0 # Surround Playback Volume.1 expected 1 but read 0, is_volatile 0 not ok 71 write_default.0.22 I wanted to ask you if it is normal or not that this test fails on my hardware, and if not, what I could do to debug the problem and give you useful information to help understand what the issue is. I am currently testing on an Ubuntu Desktop VirtualBox VM which audio hardware (as the output of the lshw command, multimedia section) is: description: Multimedia audio controller product: 82801AA AC'97 Audio Controller vendor: Intel Corporation physical id: 5 bus info: pci@0000:00:05.0 version: 01 width: 32 bits clock: 33MHz capabilities: bus_master configuration: driver=snd_intel8x0 latency=64 resources: irq:21 ioport:d100(size=256) ioport:d200(size=64) From what I have seen until now it doesn’t look like a bug from the test nor an issue from the kernel, so I’m not really sure where to look at: I have compiled alsalib’s source code from the Git repo with debug symbols and I’ve followed the execution of the test until I reached a call to the ioctl syscall, which doesn’t return an error code so it doesn’t look like the problem relies in the kernel; I’m no expert though, I’ll let you confirm this or not. I am at your complete disposal to give you any further useful information as I can’t do much more from my side alone. Thank you in advance, looking forward to your kind response. Best Regards, Giacomo Guiduzzi

1 0

[PATCH v2 0/4] ALSA: hda: Expose codec organization functions
by Cezary Rojewski 21 Feb '22

21 Feb '22

Changes expose several function that are currently unavailable for HDA-DSP drivers for use. Those functions are: snd_hda_codec_cleanup_for_unbind() snd_hda_codec_set_power_save() snd_hda_codec_register() snd_hda_codec_unregister() snd_hda_codec_device_init() This allows upcoming AVS driver [1] to re-use even mode of HDA related code that is currently available in sound/pci/hda and sound/hda and prevent any code duplication within avs-driver that would otherwise had to happen. Last patch in the series provides snd_hdac_ext_bus_link_at() - a helper function which allows for retrieval of HDA segment (link) based on codec address directly. This is simpler than parsing codec-name first to extract the address what is the case for snd_hdac_ext_bus_get_link(). The latter function is updated to re-use newly added one so core logic is not duplicated after the addition. Changes v1 -> v2: - snd_hda_codec_new() now calls snd_hda_codec_device_new() with 'snddev_managed' param set to 'true', reported by Kai [1]: https://lore.kernel.org/all/20211208111301.1817725-1-cezary.rojewski@intel.… Cezary Rojewski (4): ALSA: hda: Add snd_hdac_ext_bus_link_at() helper ALSA: hda: Update and expose snd_hda_codec_device_init() ALSA: hda: Update and expose codec register procedures ALSA: hda: Expose codec cleanup and power-save functions include/sound/hda_codec.h | 11 +++- include/sound/hdaudio_ext.h | 1 + sound/hda/ext/hdac_ext_controller.c | 31 +++++++--- sound/pci/hda/hda_codec.c | 94 ++++++++++++++++++++--------- sound/pci/hda/hda_local.h | 2 - sound/soc/codecs/hdac_hda.c | 2 +- 6 files changed, 100 insertions(+), 41 deletions(-) -- 2.25.1

2 6

[RFC PATCH 1/3] ASoC: simple-card-utils: add support for componants provideing jack events via set_jack
by Carl Philipp Klemm 20 Feb '22

20 Feb '22

This allows componants that want a jack to report state on to do so by calling set_jack on components implementing this function. Im not entirely sure this is the right way to do this so RFC Signed-off-by: Carl Philipp Klemm <philipp(a)uvos.xyz> --- include/sound/simple_card_utils.h | 6 ++-- sound/soc/generic/simple-card-utils.c | 47 +++++++++++++++++++-------- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/include/sound/simple_card_utils.h b/include/sound/simple_card_utils.h index 51b3b485a92e..547ad537613d 100644 --- a/include/sound/simple_card_utils.h +++ b/include/sound/simple_card_utils.h @@ -57,8 +57,8 @@ struct asoc_simple_priv { struct prop_nums num; unsigned int mclk_fs; } *dai_props; - struct asoc_simple_jack hp_jack; - struct asoc_simple_jack mic_jack; + struct asoc_simple_jack *hp_jack; + struct asoc_simple_jack *mic_jack; struct snd_soc_dai_link *dai_link; struct asoc_simple_dai *dais; struct snd_soc_dai_link_component *dlcs; @@ -173,7 +173,7 @@ int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix); int asoc_simple_init_jack(struct snd_soc_card *card, - struct asoc_simple_jack *sjack, + struct asoc_simple_jack **sjack, int is_hp, char *prefix, char *pin); int asoc_simple_init_priv(struct asoc_simple_priv *priv, struct link_info *li); diff --git a/sound/soc/generic/simple-card-utils.c b/sound/soc/generic/simple-card-utils.c index 10c63b73900c..1899feba16cc 100644 --- a/sound/soc/generic/simple-card-utils.c +++ b/sound/soc/generic/simple-card-utils.c @@ -395,6 +395,7 @@ int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd) struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card); struct simple_dai_props *props = simple_priv_to_props(priv, rtd->num); struct asoc_simple_dai *dai; + struct snd_soc_component *component; int i, ret; for_each_prop_dai_codec(props, i, dai) { @@ -412,6 +413,21 @@ int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd) if (ret < 0) return ret; + for_each_rtd_components(rtd, i, component) { + if (component->driver->set_jack) { + if (!priv->hp_jack) { + priv->hp_jack = devm_kzalloc(priv->snd_card.dev, + sizeof(*priv->hp_jack), GFP_KERNEL); + snd_soc_card_jack_new(&priv->snd_card, + "Headphones", + SND_JACK_HEADPHONE, + &priv->hp_jack->jack, + NULL, 0); + } + snd_soc_component_set_jack(component, &priv->hp_jack->jack, NULL); + } + } + return 0; } EXPORT_SYMBOL_GPL(asoc_simple_dai_init); @@ -554,7 +570,7 @@ int asoc_simple_parse_pin_switches(struct snd_soc_card *card, EXPORT_SYMBOL_GPL(asoc_simple_parse_pin_switches); int asoc_simple_init_jack(struct snd_soc_card *card, - struct asoc_simple_jack *sjack, + struct asoc_simple_jack **sjack, int is_hp, char *prefix, char *pin) { @@ -569,8 +585,6 @@ int asoc_simple_init_jack(struct snd_soc_card *card, if (!prefix) prefix = ""; - sjack->gpio.gpio = -ENOENT; - if (is_hp) { snprintf(prop, sizeof(prop), "%shp-det-gpio", prefix); pin_name = pin ? pin : "Headphones"; @@ -588,21 +602,26 @@ int asoc_simple_init_jack(struct snd_soc_card *card, return -EPROBE_DEFER; if (gpio_is_valid(det)) { - sjack->pin.pin = pin_name; - sjack->pin.mask = mask; + struct asoc_simple_jack *sjack_d; + + sjack = devm_kzalloc(dev, sizeof(*(*sjack)), GFP_KERNEL); + sjack_d = *sjack; + + sjack_d->pin.pin = pin_name; + sjack_d->pin.mask = mask; - sjack->gpio.name = gpio_name; - sjack->gpio.report = mask; - sjack->gpio.gpio = det; - sjack->gpio.invert = !!(flags & OF_GPIO_ACTIVE_LOW); - sjack->gpio.debounce_time = 150; + sjack_d->gpio.name = gpio_name; + sjack_d->gpio.report = mask; + sjack_d->gpio.gpio = det; + sjack_d->gpio.invert = !!(flags & OF_GPIO_ACTIVE_LOW); + sjack_d->gpio.debounce_time = 150; snd_soc_card_jack_new(card, pin_name, mask, - &sjack->jack, - &sjack->pin, 1); + &sjack_d->jack, + &sjack_d->pin, 1); - snd_soc_jack_add_gpios(&sjack->jack, 1, - &sjack->gpio); + snd_soc_jack_add_gpios(&sjack_d->jack, 1, + &sjack_d->gpio); } return 0; -- 2.34.1

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[PATCH 6/6] Documentation: sound: audio-graph-card: update dts
by Carl Philipp Klemm 20 Feb '22

20 Feb '22

bindings to add has-hp-jack Message-Id: <20220220011601.4424ad416d65b836e3165cfa(a)uvos.xyz> In-Reply-To: <OS3PR01MB8426FD3FD1B45BB31C971A56D4509(a)OS3PR01MB8426.jpnprd01.prod.outlook.com> References: <20211228190931.df5d518220080a734532ebfd(a)uvos.xyz> <87a6gawxpe.wl-kuninori.morimoto.gx(a)gmail.com> <20220105101028.620b7f2cb7727eedfccd933e(a)uvos.xyz> <87r19ld48v.wl-kuninori.morimoto.gx(a)gmail.com> <20220108145749.f55500222b049f344415a5c3(a)uvos.xyz> <OS3PR01MB8426FD3FD1B45BB31C971A56D4509(a)OS3PR01MB8426.jpnprd01.prod.outlook.com> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.33; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Signed-off-by: Carl Philipp Klemm <philipp(a)uvos.xyz> --- Documentation/devicetree/bindings/sound/audio-graph.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/audio-graph.yaml b/Documentation/devicetree/bindings/sound/audio-graph.yaml index 4b46794e5153..5844b900789a 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph.yaml +++ b/Documentation/devicetree/bindings/sound/audio-graph.yaml @@ -38,6 +38,8 @@ properties: maxItems: 1 mic-det-gpio: maxItems: 1 + hp-det-gpio: + description: Set this properties if the device has a headphone jack to be reported on by a snd_soc_component required: - dais -- 2.35.1

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[RESEND v13 00/10] Add support for audio on SC7280 based targets
by Srinivasa Rao Mandadapu 19 Feb '22

19 Feb '22

This patch set is to add support for Audio over wcd codec, digital mics, through digital codecs and without ADSP. Changes Since V12: -- Fix arguments type mismatch. Changes Since V11: -- Fix kernel robot issue on arguments type mismatch. Changes Since V10: -- Split bulk clock voting to individual clock voting as per use case in cdc-dma driver. -- Add missing codec dma clocks. -- Update rxtx lpm buffer size. Changes Since V9: -- Change individual clock voting to bulk clock voting of lpass-sc7280 platform driver. -- Remove redundant clocks in lpass variant structure. -- Add mclk for MI2S based headset path. -- Remove unused lpass variant structure members in lpass header. Changes Since V8: -- Fix errors in sc7280 lpass cpu dt-bindings. -- Move to quicinc domain email id's. Changes Since V7: -- Fix indentation errors. -- Bisect patches to avoid interdependency. Changes Since V6: -- Split cdc dma regmap config macros. -- Add write dma reg fields for i2s path. -- Add helper function to distinguish rxtx and va dma ports. -- Optimizing clock and reg name in cpu dt-bindings. -- Update buffer management for cdc dma path. -- Remove Kconfig fields of machine driver. Changes Since V5: -- Include MI2S primary node to snd_soc_dai_driver in lpass-sc7280 platform driver. -- Move dependency patch list to corresponding patch. -- Add support for missing cdc-dma ports. -- Change if/else conditional statements to switch cases. -- Add missing error handlings. -- Typo errors fix. Changes Since V4: -- Remove unused variable in lpass-sc7280 platform driver. Changes Since V3: -- Remove redundant power domain controls. As power domains can be configured from dtsi. Changes Since V2: -- Split lpass sc7280 cpu driver patch and create regmap config patch. -- Create patches based on latest kernel tip. -- Add helper function to get dma control and lpaif handle. -- Remove unused variables. Changes Since V1: -- Typo errors fix -- CPU driver readable/writable apis optimization. -- Add Missing config patch -- Add Common api for repeated dmactl initialization. Srinivasa Rao Mandadapu (10): ASoC: qcom: SC7280: Update config for building codec dma drivers ASoC: qcom: Move lpass_pcm_data structure to lpass header ASoC: qcom: lpass: Add dma fields for codec dma lpass interface ASoC: qcom: Add helper function to get dma control and lpaif handle ASoC: qcom: Add register definition for codec rddma and wrdma ASoC: qcom: Add regmap config support for codec dma driver ASoC: qcom: Add support for codec dma driver ASoC: qcom: Add lpass CPU driver for codec dma control ASoC: dt-bindings: Add SC7280 lpass cpu bindings ASoC: qcom: lpass-sc7280: Add platform driver for lpass audio .../devicetree/bindings/sound/qcom,lpass-cpu.yaml | 75 ++- sound/soc/qcom/Kconfig | 11 + sound/soc/qcom/Makefile | 4 + sound/soc/qcom/lpass-cdc-dma.c | 304 ++++++++++ sound/soc/qcom/lpass-cpu.c | 244 +++++++- sound/soc/qcom/lpass-lpaif-reg.h | 127 ++++- sound/soc/qcom/lpass-platform.c | 617 ++++++++++++++++++--- sound/soc/qcom/lpass-sc7280.c | 447 +++++++++++++++ sound/soc/qcom/lpass.h | 145 +++++ 9 files changed, 1887 insertions(+), 87 deletions(-) create mode 100644 sound/soc/qcom/lpass-cdc-dma.c create mode 100644 sound/soc/qcom/lpass-sc7280.c -- 2.7.4

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