February 2022 - Alsa-devel - mailman.alsa-project.org

[PATCH AUTOSEL 5.16 06/30] ASoC: rt5668: do not block workqueue if card is unbound
by Sasha Levin 23 Feb '22

23 Feb '22

From: Kai Vehmanen <kai.vehmanen(a)linux.intel.com> [ Upstream commit a6d78661dc903d90a327892bbc34268f3a5f4b9c ] The current rt5668_jack_detect_handler() assumes the component and card will always show up and implements an infinite usleep loop waiting for them to show up. This does not hold true if a codec interrupt (or other event) occurs when the card is unbound. The codec driver's remove or shutdown functions cannot cancel the workqueue due to the wait loop. As a result, code can either end up blocking the workqueue, or hit a kernel oops when the card is freed. Fix the issue by rescheduling the jack detect handler in case the card is not ready. In case card never shows up, the shutdown/remove/suspend calls can now cancel the detect task. Signed-off-by: Kai Vehmanen <kai.vehmanen(a)linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi(a)linux.intel.com> Reviewed-by: Shuming Fan <shumingf(a)realtek.com> Link: https://lore.kernel.org/r/20220207153000.3452802-2-kai.vehmanen@linux.intel… Signed-off-by: Mark Brown <broonie(a)kernel.org> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- sound/soc/codecs/rt5668.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/sound/soc/codecs/rt5668.c b/sound/soc/codecs/rt5668.c index fb09715bf9328..5b12cbf2ba215 100644 --- a/sound/soc/codecs/rt5668.c +++ b/sound/soc/codecs/rt5668.c @@ -1022,11 +1022,13 @@ static void rt5668_jack_detect_handler(struct work_struct *work) container_of(work, struct rt5668_priv, jack_detect_work.work); int val, btn_type; - while (!rt5668->component) - usleep_range(10000, 15000); - - while (!rt5668->component->card->instantiated) - usleep_range(10000, 15000); + if (!rt5668->component || !rt5668->component->card || + !rt5668->component->card->instantiated) { + /* card not yet ready, try later */ + mod_delayed_work(system_power_efficient_wq, + &rt5668->jack_detect_work, msecs_to_jiffies(15)); + return; + } mutex_lock(&rt5668->calibrate_mutex); -- 2.34.1

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[PATCH AUTOSEL 5.16 05/30] ASoC: rt5682s: do not block workqueue if card is unbound
by Sasha Levin 23 Feb '22

23 Feb '22

From: Kai Vehmanen <kai.vehmanen(a)linux.intel.com> [ Upstream commit d7b530fdc45e75a54914a194c4becd9672a4e24f ] The current rt5682s_jack_detect_handler() assumes the component and card will always show up and implements an infinite usleep loop waiting for them to show up. This does not hold true if a codec interrupt (or other event) occurs when the card is unbound. The codec driver's remove or shutdown functions cannot cancel the workqueue due to the wait loop. As a result, code can either end up blocking the workqueue, or hit a kernel oops when the card is freed. Fix the issue by rescheduling the jack detect handler in case the card is not ready. In case card never shows up, the shutdown/remove/suspend calls can now cancel the detect task. Signed-off-by: Kai Vehmanen <kai.vehmanen(a)linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi(a)linux.intel.com> Reviewed-by: Shuming Fan <shumingf(a)realtek.com> Link: https://lore.kernel.org/r/20220207153000.3452802-1-kai.vehmanen@linux.intel… Signed-off-by: Mark Brown <broonie(a)kernel.org> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- sound/soc/codecs/rt5682s.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/sound/soc/codecs/rt5682s.c b/sound/soc/codecs/rt5682s.c index d49a4f68566d2..d79b548d23fa4 100644 --- a/sound/soc/codecs/rt5682s.c +++ b/sound/soc/codecs/rt5682s.c @@ -824,11 +824,13 @@ static void rt5682s_jack_detect_handler(struct work_struct *work) container_of(work, struct rt5682s_priv, jack_detect_work.work); int val, btn_type; - while (!rt5682s->component) - usleep_range(10000, 15000); - - while (!rt5682s->component->card->instantiated) - usleep_range(10000, 15000); + if (!rt5682s->component || !rt5682s->component->card || + !rt5682s->component->card->instantiated) { + /* card not yet ready, try later */ + mod_delayed_work(system_power_efficient_wq, + &rt5682s->jack_detect_work, msecs_to_jiffies(15)); + return; + } mutex_lock(&rt5682s->jdet_mutex); mutex_lock(&rt5682s->calibrate_mutex); -- 2.34.1

1 0

[PATCH 00/10] ASoC: codec: add pm runtime support for Qualcomm codecs
by Srinivas Kandagatla 22 Feb '22

22 Feb '22

This patchset adds support for runtime pm on tx/rx/wsa/wcd lpass macro, wsa881x and wcd938x codecs that are wired up on SoundWire bus. During pm testing it was also found that soundwire clks enabled by lpass macros are not enabling all the required clocks correctly, so last 3 patches corrects them. Tested this on SM8250 MTP along SoundWire In band Headset Button wakeup interrupts. Srinivas Kandagatla (10): ASoC: codecs: va-macro: add runtime pm support ASoC: codecs: wsa-macro: add runtime pm support ASoC: codecs: rx-macro: add runtime pm support ASoC: codecs: tx-macro: add runtime pm support ASoC: codecs: wsa881x: add runtime pm support ASoC: codecs: wcd938x: add simple clk stop support ASoC: codecs: wcd-mbhc: add runtime pm support ASoC: codecs: wsa-macro: setup soundwire clks correctly ASoC: codecs: tx-macro: setup soundwire clks correctly ASoC: codecs: rx-macro: setup soundwire clks correctly sound/soc/codecs/lpass-rx-macro.c | 49 +++++++++++++++++++++++++-- sound/soc/codecs/lpass-tx-macro.c | 45 ++++++++++++++++++++++++- sound/soc/codecs/lpass-va-macro.c | 36 ++++++++++++++++++++ sound/soc/codecs/lpass-wsa-macro.c | 43 +++++++++++++++++++++++- sound/soc/codecs/wcd-mbhc-v2.c | 26 ++++++++++++++ sound/soc/codecs/wcd938x-sdw.c | 1 + sound/soc/codecs/wsa881x.c | 54 ++++++++++++++++++++++++++++++ 7 files changed, 250 insertions(+), 4 deletions(-) -- 2.21.0

3 17

[PATCH v8 0/7] Add pin control support for lpass sc7280
by Srinivasa Rao Mandadapu 22 Feb '22

22 Feb '22

This patch series is to split lpass variant common pin control functions and SoC specific functions and to add lpass sc7280 pincontrol support. It also Adds dt-bindings for lpass sc7280 lpass lpi pincontrol. Changes Since V7: -- Update optional clock voting with conditional check. -- Add const to lpi_pinctrl_variant_data structure. -- Update required headers and remove redundant. -- Change EXPORT_SYMBOL to EXPORT_SYMBOL_GPL -- Fix typo errors. Changes Since V6: -- Update conditional clock voting to optional clock voting. -- Update Kconfig depends on field with select. -- Fix typo errors. Changes Since V5: -- Create new patch by updating macro name to lpi specific. -- Create new patch by updating lpi pin group structure with core group_desc structure. -- Fix typo errors. -- Sort macros in the make file and configuration file. Changes Since V4: -- Update commit message and description of the chip specific extraction patch. -- Sort macros in kconfig and makefile. -- Update optional clock voting to conditional clock voting. -- Fix typo errors. -- Move to quicinc domain email id's. Changes Since V3: -- Update separate Kconfig fields for sm8250 and sc7280. -- Update module license and description. -- Move static variables to corresponding .c files from header file. Changes Since V2: -- Add new dt-bindings for sc7280 lpi driver. -- Make clock voting change as separate patch. -- Split existing pincontrol driver and make common functions as part of separate file. -- Rename lpass pincontrol lpi dt-bindings to sm8250 specific dt-bindings Changes Since V1: -- Make lpi pinctrl variant data structure as constant -- Add appropriate commit message -- Change signedoff by sequence. Srinivasa Rao Mandadapu (7): dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings pinctrl: qcom: Update macro name to LPI specific pinctrl: qcom: Update lpi pin group structure pinctrl: qcom: Extract chip specific LPASS LPI code pinctrl: qcom: Add SC7280 lpass pin configuration pinctrl: qcom: Update clock voting as optional Tested this on SM8250 MTP with WSA and WCD codecs. Tested-by: Srinivas Kandagatla <srinivas.kandagatla(a)linaro.org> .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 133 ----------- .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 ++++++++++ .../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 133 +++++++++++ drivers/pinctrl/qcom/Kconfig | 16 ++ drivers/pinctrl/qcom/Makefile | 2 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 255 ++------------------- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 86 +++++++ drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++ drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++ 9 files changed, 705 insertions(+), 370 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c -- 2.7.4

2 8

Asking for information about ALSA's kselftest
by Giacomo Guiduzzi 22 Feb '22

22 Feb '22

[RESENDING BECAUSE BOUNCED BY SPAMASSASSIN] Greetings Mr. Brown and users of the alsa-devel mailing list, I’m a student at the University of Modena and Reggio Emilia. I am working on the Kernel Hacking course’s exam, a course kept by Paolo Valente which introduces students to the world of the Linux kernel and its magics. I was taking a look at the kernel’s kselftests from Linus Torvald’s repository to find some test to fix for the exam and I stumbled upon the ALSA’s selftest, which I’ve passed the last few days on, debugging and exploring. During the execution the test goes as it should except for two or three tests. Until now I’ve tried understanding test 71, which sometimes succeeds and sometimes fails, and test 72. I have no previous knowledge of how ALSA works and I’m completely new to the kselftests and the kernel in general. Test 71 gives the following output: # Surround Playback Volume.0 expected 0 but read 1, is_volatile 0 # Surround Playback Volume.1 expected 1 but read 0, is_volatile 0 not ok 71 write_default.0.22 I wanted to ask you if it is normal or not that this test fails on my hardware, and if not, what I could do to debug the problem and give you useful information to help understand what the issue is. I am currently testing on an Ubuntu Desktop VirtualBox VM on kernel 5.17.0-rc3. The audio hardware (as the output of the lshw command, multimedia section) is: description: Multimedia audio controller product: 82801AA AC'97 Audio Controller vendor: Intel Corporation physical id: 5 bus info: pci@0000:00:05.0 version: 01 width: 32 bits clock: 33MHz capabilities: bus_master configuration: driver=snd_intel8x0 latency=64 resources: irq:21 ioport:d100(size=256) ioport:d200(size=64) From what I have seen until now it doesn’t look like a bug from the test nor an issue from the kernel, so I’m not really sure where to look at: I have compiled alsalib’s source code from the Git repo with debug symbols and I’ve followed the execution of the test until I reached a call to the ioctl syscall, which doesn’t return an error code so it doesn’t look like the problem relies in the kernel; I’m no expert though, I’ll let you confirm this or not. I am at your complete disposal to give you any further useful information as I can’t do much more from my side alone. Thank you in advance, looking forward to your kind response. Best Regards, Giacomo Guiduzzi

2 1

[PATCH] ASoC: samsung: i2s: check the return value of kstrdup()
by xkernel.wang＠foxmail.com 22 Feb '22

22 Feb '22

From: Xiaoke Wang <xkernel.wang(a)foxmail.com> kstrdup() is a memory allocation function which can return NULL when some internal memory errors happen. It is better to check the return value of it to catch the error in time. Signed-off-by: Xiaoke Wang <xkernel.wang(a)foxmail.com> --- sound/soc/samsung/i2s.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c index 309badc..70c8271 100644 --- a/sound/soc/samsung/i2s.c +++ b/sound/soc/samsung/i2s.c @@ -1349,6 +1349,10 @@ static int i2s_create_secondary_device(struct samsung_i2s_priv *priv) return -ENOMEM; pdev_sec->driver_override = kstrdup("samsung-i2s", GFP_KERNEL); + if (!pdev_sec->driver_override) { + platform_device_put(pdev_sec); + return -ENOMEM; + } ret = platform_device_add(pdev_sec); if (ret < 0) { --

2 1

[PATCH 0/3] ASoC: amd: acp: Add new machines and minor tweaks
by Ajit Kumar Pandey 22 Feb '22

22 Feb '22

This patch series will add sound card support for newer machines and done some minor tweaks related to legacy machine driver. Ajit Kumar Pandey (3): ASoC: amd: acp: Change card name for Guybrush Machine ASoC: amd: acp-legacy: Add legacy card support for new machines ASoC: amd: acp: Add DMIC machine driver ops sound/soc/amd/acp/acp-legacy-mach.c | 34 +++++++++++++++++++++++++++-- sound/soc/amd/acp/acp-mach-common.c | 27 +++++++++++++++++++++++ sound/soc/amd/acp/acp-renoir.c | 19 +++++++++++++++- 3 files changed, 77 insertions(+), 3 deletions(-) -- 2.25.1

3 6

jack: implement pcm operation sw_params
by GitHub pull_request - opened 21 Feb '22

21 Feb '22

alsa-project/alsa-plugins pull request #43 was opened from aditpape: to reflect an updated avail_min value during runtime Signed-off-by: Andreas Pape <apape(a)de.adit-jv.com> Request URL : https://github.com/alsa-project/alsa-plugins/pull/43 Patch URL : https://github.com/alsa-project/alsa-plugins/pull/43.patch Repository URL: https://github.com/alsa-project/alsa-plugins

1 0

[PATCH] ASoC: mediatek: mt8195: enable apll tuner
by Trevor Wu 21 Feb '22

21 Feb '22

Normally, the clock source of audio module is either 26M or APLL1/APLL2, but APLL1/APLL2 are not the multiple of 26M. In the patch, APLL1 and APLL2 tuners are enabled to handle sample rate mismatch when the data path crosses two different clock domains. Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> --- sound/soc/mediatek/mt8195/mt8195-afe-clk.c | 282 ++++++++++++++++++++- sound/soc/mediatek/mt8195/mt8195-afe-clk.h | 11 + sound/soc/mediatek/mt8195/mt8195-afe-pcm.c | 3 - 3 files changed, 292 insertions(+), 4 deletions(-) diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c index c2543f4cffb7..efd5cc364a35 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c @@ -40,6 +40,8 @@ static const char *aud_clks[MT8195_CLK_NUM] = { [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp", /* afe clock gate */ [MT8195_CLK_AUD_AFE] = "aud_afe", + [MT8195_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner", + [MT8195_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner", [MT8195_CLK_AUD_APLL] = "aud_apll", [MT8195_CLK_AUD_APLL2] = "aud_apll2", [MT8195_CLK_AUD_DAC] = "aud_dac", @@ -77,6 +79,268 @@ static const char *aud_clks[MT8195_CLK_NUM] = { [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", }; +struct mt8195_afe_tuner_cfg { + unsigned int id; + int apll_div_reg; + unsigned int apll_div_shift; + unsigned int apll_div_maskbit; + unsigned int apll_div_default; + int ref_ck_sel_reg; + unsigned int ref_ck_sel_shift; + unsigned int ref_ck_sel_maskbit; + unsigned int ref_ck_sel_default; + int tuner_en_reg; + unsigned int tuner_en_shift; + unsigned int tuner_en_maskbit; + int upper_bound_reg; + unsigned int upper_bound_shift; + unsigned int upper_bound_maskbit; + unsigned int upper_bound_default; + spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/ + int ref_cnt; +}; + +static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = { + [MT8195_AUD_PLL1] = { + .id = MT8195_AUD_PLL1, + .apll_div_reg = AFE_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0xf, + .apll_div_default = 0x7, + .ref_ck_sel_reg = AFE_APLL_TUNER_CFG, + .ref_ck_sel_shift = 1, + .ref_ck_sel_maskbit = 0x3, + .ref_ck_sel_default = 0x2, + .tuner_en_reg = AFE_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_APLL_TUNER_CFG, + .upper_bound_shift = 8, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x2, + }, + [MT8195_AUD_PLL2] = { + .id = MT8195_AUD_PLL2, + .apll_div_reg = AFE_APLL_TUNER_CFG1, + .apll_div_shift = 4, + .apll_div_maskbit = 0xf, + .apll_div_default = 0x7, + .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1, + .ref_ck_sel_shift = 1, + .ref_ck_sel_maskbit = 0x3, + .ref_ck_sel_default = 0x1, + .tuner_en_reg = AFE_APLL_TUNER_CFG1, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_APLL_TUNER_CFG1, + .upper_bound_shift = 8, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x2, + }, + [MT8195_AUD_PLL3] = { + .id = MT8195_AUD_PLL3, + .apll_div_reg = AFE_EARC_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0x3f, + .apll_div_default = 0x3, + .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG, + .ref_ck_sel_shift = 24, + .ref_ck_sel_maskbit = 0x3, + .ref_ck_sel_default = 0x0, + .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG, + .upper_bound_shift = 12, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x4, + }, + [MT8195_AUD_PLL4] = { + .id = MT8195_AUD_PLL4, + .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0x3f, + .apll_div_default = 0x7, + .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1, + .ref_ck_sel_shift = 8, + .ref_ck_sel_maskbit = 0x1, + .ref_ck_sel_default = 0, + .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG, + .upper_bound_shift = 12, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x4, + }, + [MT8195_AUD_PLL5] = { + .id = MT8195_AUD_PLL5, + .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG, + .apll_div_shift = 4, + .apll_div_maskbit = 0x3f, + .apll_div_default = 0x3, + .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG, + .ref_ck_sel_shift = 24, + .ref_ck_sel_maskbit = 0x1, + .ref_ck_sel_default = 0, + .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG, + .tuner_en_shift = 0, + .tuner_en_maskbit = 0x1, + .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG, + .upper_bound_shift = 12, + .upper_bound_maskbit = 0xff, + .upper_bound_default = 0x4, + }, +}; + +static struct mt8195_afe_tuner_cfg *mt8195_afe_found_apll_tuner(unsigned int id) +{ + if (id >= MT8195_AUD_PLL_NUM) + return NULL; + + return &mt8195_afe_tuner_cfgs[id]; +} + +static int mt8195_afe_init_apll_tuner(unsigned int id) +{ + struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + + if (!cfg) + return -EINVAL; + + cfg->ref_cnt = 0; + spin_lock_init(&cfg->ctrl_lock); + + return 0; +} + +static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe, + unsigned int id) +{ + const struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + + if (!cfg) + return -EINVAL; + + regmap_update_bits(afe->regmap, cfg->apll_div_reg, + cfg->apll_div_maskbit << cfg->apll_div_shift, + cfg->apll_div_default << cfg->apll_div_shift); + + regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg, + cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift, + cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift); + + regmap_update_bits(afe->regmap, cfg->upper_bound_reg, + cfg->upper_bound_maskbit << cfg->upper_bound_shift, + cfg->upper_bound_default << cfg->upper_bound_shift); + + return 0; +} + +static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_private *afe_priv = afe->platform_priv; + + switch (id) { + case MT8195_AUD_PLL1: + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); + break; + case MT8195_AUD_PLL2: + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); + mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); + break; + default: + break; + } + + return 0; +} + +static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_private *afe_priv = afe->platform_priv; + + switch (id) { + case MT8195_AUD_PLL1: + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); + break; + case MT8195_AUD_PLL2: + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); + break; + default: + break; + } + + return 0; +} + +static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + unsigned long flags; + int ret = 0; + + if (!cfg) + return -EINVAL; + + ret = mt8195_afe_setup_apll_tuner(afe, id); + if (ret) + return ret; + + ret = mt8195_afe_enable_tuner_clk(afe, id); + if (ret) + return ret; + + spin_lock_irqsave(&cfg->ctrl_lock, flags); + + cfg->ref_cnt++; + if (cfg->ref_cnt == 1) + regmap_update_bits(afe->regmap, + cfg->tuner_en_reg, + cfg->tuner_en_maskbit << cfg->tuner_en_shift, + 1 << cfg->tuner_en_shift); + + spin_unlock_irqrestore(&cfg->ctrl_lock, flags); + + return ret; +} + +static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe, + unsigned int id) +{ + struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); + unsigned long flags; + int ret = 0; + + if (!cfg) + return -EINVAL; + + spin_lock_irqsave(&cfg->ctrl_lock, flags); + + cfg->ref_cnt--; + if (cfg->ref_cnt == 0) + regmap_update_bits(afe->regmap, + cfg->tuner_en_reg, + cfg->tuner_en_maskbit << cfg->tuner_en_shift, + 0 << cfg->tuner_en_shift); + else if (cfg->ref_cnt < 0) + cfg->ref_cnt = 0; + + spin_unlock_irqrestore(&cfg->ctrl_lock, flags); + + ret = mt8195_afe_disable_tuner_clk(afe, id); + if (ret) + return ret; + + return ret; +} + int mt8195_afe_get_mclk_source_clk_id(int sel) { switch (sel) { @@ -113,7 +377,7 @@ int mt8195_afe_get_default_mclk_source_by_rate(int rate) int mt8195_afe_init_clock(struct mtk_base_afe *afe) { struct mt8195_afe_private *afe_priv = afe->platform_priv; - int i; + int i, ret; mt8195_audsys_clk_register(afe); @@ -133,6 +397,16 @@ int mt8195_afe_init_clock(struct mtk_base_afe *afe) } } + /* initial tuner */ + for (i = 0; i < MT8195_AUD_PLL_NUM; i++) { + ret = mt8195_afe_init_apll_tuner(i); + if (ret) { + dev_dbg(afe->dev, "%s(), init apll_tuner%d failed", + __func__, (i + 1)); + return -EINVAL; + } + } + return 0; } @@ -428,11 +702,17 @@ int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe) mt8195_afe_enable_afe_on(afe); + mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1); + mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2); + return 0; } int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe) { + mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2); + mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1); + mt8195_afe_disable_afe_on(afe); mt8195_afe_disable_timing_sys(afe); diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.h b/sound/soc/mediatek/mt8195/mt8195-afe-clk.h index f8e6eeb29a89..40663e31becd 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.h +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.h @@ -35,6 +35,8 @@ enum { MT8195_CLK_INFRA_AO_AUDIO_26M_B, MT8195_CLK_SCP_ADSP_AUDIODSP, MT8195_CLK_AUD_AFE, + MT8195_CLK_AUD_APLL1_TUNER, + MT8195_CLK_AUD_APLL2_TUNER, MT8195_CLK_AUD_APLL, MT8195_CLK_AUD_APLL2, MT8195_CLK_AUD_DAC, @@ -84,6 +86,15 @@ enum { MT8195_MCK_SEL_NUM, }; +enum { + MT8195_AUD_PLL1, + MT8195_AUD_PLL2, + MT8195_AUD_PLL3, + MT8195_AUD_PLL4, + MT8195_AUD_PLL5, + MT8195_AUD_PLL_NUM, +}; + struct mtk_base_afe; int mt8195_afe_get_mclk_source_clk_id(int sel); diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c b/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c index e425f868476a..b77c2ba5a629 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c @@ -2583,8 +2583,6 @@ static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg) case AFE_IRQ3_CON_MON: case AFE_IRQ_MCU_MON2: case ADSP_IRQ_STATUS: - case AFE_APLL_TUNER_CFG: - case AFE_APLL_TUNER_CFG1: case AUDIO_TOP_STA0: case AUDIO_TOP_STA1: case AFE_GAIN1_CUR: @@ -2623,7 +2621,6 @@ static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg) case SPDIFIN_USERCODE10: case SPDIFIN_USERCODE11: case SPDIFIN_USERCODE12: - case AFE_SPDIFIN_APLL_TUNER_CFG: case AFE_LINEIN_APLL_TUNER_MON: case AFE_EARC_APLL_TUNER_MON: case AFE_CM0_MON: -- 2.18.0

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[PATCH v2] ASoC: SOF: Intel: Add topology overwrite for Felwinter
by Brent Lu 21 Feb '22

21 Feb '22

From: Ajye Huang <ajye_huang(a)compal.corp-partner.google.com> The Felwinter uses four max98360a amplifiers on corresponding CH0~CH3. There are four amps on the board connecting to headphone to SSP0 port, amp to SSP1,and the DAI format would be DSP_A,8-slots, 32 bit slot-width. CH0: L(Woofer), CH1:R(Woofer), CH2:L(Tweeter), CH3:R(Tweeter) Signed-off-by: Ajye Huang <ajye_huang(a)compal.corp-partner.google.com> Signed-off-by: Brent Lu <brent.lu(a)intel.com> Reviewed-by: Curtis Malainey <cujomalainey(a)chromium.org> Reviewed-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> --- sound/soc/sof/sof-pci-dev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/soc/sof/sof-pci-dev.c b/sound/soc/sof/sof-pci-dev.c index 20c6ca37dbc4..61f2afd54c3e 100644 --- a/sound/soc/sof/sof-pci-dev.c +++ b/sound/soc/sof/sof-pci-dev.c @@ -67,6 +67,14 @@ static const struct dmi_system_id sof_tplg_table[] = { }, .driver_data = "sof-adl-max98390-ssp2-rt5682-ssp0.tplg", }, + { + .callback = sof_tplg_cb, + .matches = { + DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"), + DMI_MATCH(DMI_OEM_STRING, "AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY"), + }, + .driver_data = "sof-adl-max98360a-rt5682-2way.tplg", + }, {} }; -- 2.25.1

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