April 2020 - Alsa-devel - mailman.alsa-project.org

[PATCH] ASoC: dt-bindings: ak4642: switch to yaml base Documentation
by Kuninori Morimoto 06 May '20

06 May '20

From: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> This patch switches from .txt base to .yaml base Document. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> --- .../devicetree/bindings/sound/ak4642.txt | 37 ------------ .../devicetree/bindings/sound/ak4642.yaml | 58 +++++++++++++++++++ 2 files changed, 58 insertions(+), 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/ak4642.txt create mode 100644 Documentation/devicetree/bindings/sound/ak4642.yaml diff --git a/Documentation/devicetree/bindings/sound/ak4642.txt b/Documentation/devicetree/bindings/sound/ak4642.txt deleted file mode 100644 index 58e48ee97175..000000000000 --- a/Documentation/devicetree/bindings/sound/ak4642.txt +++ /dev/null @@ -1,37 +0,0 @@ -AK4642 I2C transmitter - -This device supports I2C mode only. - -Required properties: - - - compatible : "asahi-kasei,ak4642" or "asahi-kasei,ak4643" or "asahi-kasei,ak4648" - - reg : The chip select number on the I2C bus - -Optional properties: - - - #clock-cells : common clock binding; shall be set to 0 - - clocks : common clock binding; MCKI clock - - clock-frequency : common clock binding; frequency of MCKO - - clock-output-names : common clock binding; MCKO clock name - -Example 1: - -&i2c { - ak4648: ak4648@12 { - compatible = "asahi-kasei,ak4642"; - reg = <0x12>; - }; -}; - -Example 2: - -&i2c { - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - reg = <0x12>; - #clock-cells = <0>; - clocks = <&audio_clock>; - clock-frequency = <12288000>; - clock-output-names = "ak4643_mcko"; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/ak4642.yaml b/Documentation/devicetree/bindings/sound/ak4642.yaml new file mode 100644 index 000000000000..6cd213be2266 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak4642.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ak4642.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AK4642 I2C transmitter Device Tree Bindings + +maintainers: + - Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> + +properties: + compatible: + enum: + - asahi-kasei,ak4642 + - asahi-kasei,ak4643 + - asahi-kasei,ak4648 + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + "#sound-dai-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-frequency: + description: common clock binding; frequency of MCKO + $ref: /schemas/types.yaml#/definitions/uint32 + + clock-output-names: + description: common clock name + $ref: /schemas/types.yaml#/definitions/string + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + #clock-cells = <0>; + clocks = <&audio_clock>; + clock-frequency = <12288000>; + clock-output-names = "ak4643_mcko"; + }; + }; -- 2.17.1

2 1

[PATCH] [inline assembly] fix pcm_dmix_i386.h assembly chunk interfaces
by frederic.recoules＠univ-grenoble-alpes.fr 06 May '20

06 May '20

From: Frédéric Recoules <frederic.recoules(a)orange.fr> Enabler change: - set HAVE_MMX in configure if the compiler is aware of MMX technology Main changes are: - move 'size' and 'old_ebx' to the output list since they are clobbered - add the "memory" keyword since input pointers are dereferenced - add mmx registers in the clobber list and add an initialization for mm1 - add ebx in clobbers via a set of macro when GCC is newer than 5.0 (it will work for other compilers or non-PIC mode too) Minor changes are: - keep consistent the token numbering in the template - remove the manual save/restore ebx when it is in the clobber list - allows 'dst_step', 'src_step' and 'sum_step' to be given by immediates - allows 'size' to be given by register (e.g. ebp) - add "cc" keyword since the eflag register is clobbered Signed-off-by: Frédéric Recoules <frederic.recoules(a)orange.fr> --- configure.ac | 7 ++ src/pcm/pcm_dmix_i386.h | 174 +++++++++++++++++++++++----------------- 2 files changed, 106 insertions(+), 75 deletions(-) diff --git a/configure.ac b/configure.ac index 4b5ab662..1838e50b 100644 --- a/configure.ac +++ b/configure.ac @@ -516,6 +516,13 @@ if test -z "$gcc_have_atomics"; then fi AC_MSG_RESULT($gcc_have_atomics) +dnl check mmx register for pcm_dmix_i386 + +AC_TRY_LINK([], + [__asm__ volatile ("" : : : "mm0");], + [AC_DEFINE([HAVE_MMX], "1", [MMX technology is enabled])], + []) + PCM_PLUGIN_LIST="copy linear route mulaw alaw adpcm rate plug multi shm file null empty share meter hooks lfloat ladspa dmix dshare dsnoop asym iec958 softvol extplug ioplug mmap_emul" build_pcm_plugin="no" diff --git a/src/pcm/pcm_dmix_i386.h b/src/pcm/pcm_dmix_i386.h index 2778cb1d..aa1717f6 100644 --- a/src/pcm/pcm_dmix_i386.h +++ b/src/pcm/pcm_dmix_i386.h @@ -26,6 +26,13 @@ * */ +#define COMMA , +#if __GNUC__ < 5 && defined(__PIC__) +# define GCC_PIC_SWITCH(before,after) before +#else +# define GCC_PIC_SWITCH(before,after) after +#endif + /* * for plain i386 */ @@ -47,13 +54,14 @@ static void MIX_AREAS_16(unsigned int size, __asm__ __volatile__ ( "\n" - "\tmovl %%ebx, %7\n" /* ebx is GOT pointer (-fPIC) */ + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %%ebx, %1\n",) /* * initialization, load ESI, EDI, EBX registers */ - "\tmovl %1, %%edi\n" - "\tmovl %2, %%esi\n" - "\tmovl %3, %%ebx\n" + "\tmovl %2, %%edi\n" + "\tmovl %3, %%esi\n" + "\tmovl %4, %%ebx\n" "\tcmpl $0, %0\n" "\tjnz 2f\n" "\tjmp 7f\n" @@ -64,9 +72,9 @@ static void MIX_AREAS_16(unsigned int size, */ "\t.p2align 4,,15\n" "1:" - "\tadd %4, %%edi\n" - "\tadd %5, %%esi\n" - "\tadd %6, %%ebx\n" + "\tadd %5, %%edi\n" + "\tadd %6, %%esi\n" + "\tadd %7, %%ebx\n" /* * sample = *src; @@ -138,15 +146,16 @@ static void MIX_AREAS_16(unsigned int size, "\tjnz 4b\n" "\tdecl %0\n" "\tjnz 1b\n" - - "7:" - "\tmovl %7, %%ebx\n" /* ebx is GOT pointer (-fPIC) */ - : /* no output regs */ - : "m" (size), "m" (dst), "m" (src), - "m" (sum), "m" (dst_step), "m" (src_step), - "m" (sum_step), "m" (old_ebx) - : "esi", "edi", "edx", "ecx", "eax" + "7:" + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %1, %%ebx\n",) + + : "+&rm" (size), GCC_PIC_SWITCH("=m","=X") (old_ebx) + : "m" (dst), "m" (src), "m" (sum), + "im" (dst_step), "im" (src_step), "im" (sum_step) + : "esi", "edi", "edx", "ecx", GCC_PIC_SWITCH(,"ebx"COMMA) "eax", + "memory", "cc" ); } @@ -171,22 +180,24 @@ static void MIX_AREAS_16_MMX(unsigned int size, __asm__ __volatile__ ( "\n" - "\tmovl %%ebx, %7\n" /* ebx is GOT pointer (-fPIC) */ + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %%ebx, %1\n",) /* - * initialization, load ESI, EDI, EBX registers + * initialization, load ESI, EDI, EBX registers, clear MM1 */ - "\tmovl %1, %%edi\n" - "\tmovl %2, %%esi\n" - "\tmovl %3, %%ebx\n" + "\tpxor %%mm1, %%mm1\n" + "\tmovl %2, %%edi\n" + "\tmovl %3, %%esi\n" + "\tmovl %4, %%ebx\n" "\tcmpl $0, %0\n" "\tjnz 2f\n" "\tjmp 5f\n" "\t.p2align 4,,15\n" "1:" - "\tadd %4, %%edi\n" - "\tadd %5, %%esi\n" - "\tadd %6, %%ebx\n" + "\tadd %5, %%edi\n" + "\tadd %6, %%esi\n" + "\tadd %7, %%ebx\n" "2:" /* @@ -230,13 +241,20 @@ static void MIX_AREAS_16_MMX(unsigned int size, "\tjnz 1b\n" "\temms\n" "5:" - "\tmovl %7, %%ebx\n" /* ebx is GOT pointer (-fPIC) */ - - : /* no output regs */ - : "m" (size), "m" (dst), "m" (src), - "m" (sum), "m" (dst_step), "m" (src_step), - "m" (sum_step), "m" (old_ebx) - : "esi", "edi", "edx", "ecx", "eax" + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %1, %%ebx\n",) + + : "+&rm" (size), GCC_PIC_SWITCH("=m","=X") (old_ebx) + : "m" (dst), "m" (src), "m" (sum), + "im" (dst_step), "im" (src_step), "im" (sum_step) + : "esi", "edi", "edx", "ecx", GCC_PIC_SWITCH(,"ebx"COMMA) "eax", + "memory", "cc", +# ifdef HAVE_MMX + "mm0", "mm1" +# else + "st", "st(1)", "st(2)", "st(3)", + "st(4)", "st(5)", "st(6)", "st(7)" +# endif ); } @@ -261,13 +279,14 @@ static void MIX_AREAS_32(unsigned int size, __asm__ __volatile__ ( "\n" - "\tmovl %%ebx, %7\n" /* ebx is GOT pointer (-fPIC) */ + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %%ebx, %1\n",) /* * initialization, load ESI, EDI, EBX registers */ - "\tmovl %1, %%edi\n" - "\tmovl %2, %%esi\n" - "\tmovl %3, %%ebx\n" + "\tmovl %2, %%edi\n" + "\tmovl %3, %%esi\n" + "\tmovl %4, %%ebx\n" "\tcmpl $0, %0\n" "\tjnz 1f\n" "\tjmp 6f\n" @@ -337,19 +356,20 @@ static void MIX_AREAS_32(unsigned int size, */ "\tdecl %0\n" "\tjz 6f\n" - "\tadd %4, %%edi\n" - "\tadd %5, %%esi\n" - "\tadd %6, %%ebx\n" + "\tadd %5, %%edi\n" + "\tadd %6, %%esi\n" + "\tadd %7, %%ebx\n" "\tjmp 1b\n" - - "6:" - "\tmovl %7, %%ebx\n" /* ebx is GOT pointer (-fPIC) */ - : /* no output regs */ - : "m" (size), "m" (dst), "m" (src), - "m" (sum), "m" (dst_step), "m" (src_step), - "m" (sum_step), "m" (old_ebx) - : "esi", "edi", "edx", "ecx", "eax" + "6:" + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %1, %%ebx\n",) + + : "+&rm" (size), GCC_PIC_SWITCH("=m","=X") (old_ebx) + : "m" (dst), "m" (src), "m" (sum), + "im" (dst_step), "im" (src_step), "im" (sum_step) + : "esi", "edi", "edx", "ecx", GCC_PIC_SWITCH(,"ebx"COMMA) "eax", + "memory", "cc" ); } @@ -374,13 +394,14 @@ static void MIX_AREAS_24(unsigned int size, __asm__ __volatile__ ( "\n" - "\tmovl %%ebx, %7\n" /* ebx is GOT pointer (-fPIC) */ + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %%ebx, %1\n",) /* * initialization, load ESI, EDI, EBX registers */ - "\tmovl %1, %%edi\n" - "\tmovl %2, %%esi\n" - "\tmovl %3, %%ebx\n" + "\tmovl %2, %%edi\n" + "\tmovl %3, %%esi\n" + "\tmovl %4, %%ebx\n" "\tcmpl $0, %0\n" "\tjnz 1f\n" "\tjmp 6f\n" @@ -443,19 +464,20 @@ static void MIX_AREAS_24(unsigned int size, */ "\tdecl %0\n" "\tjz 6f\n" - "\tadd %4, %%edi\n" - "\tadd %5, %%esi\n" - "\tadd %6, %%ebx\n" + "\tadd %5, %%edi\n" + "\tadd %6, %%esi\n" + "\tadd %7, %%ebx\n" "\tjmp 1b\n" - - "6:" - "\tmovl %7, %%ebx\n" /* ebx is GOT pointer (-fPIC) */ - : /* no output regs */ - : "m" (size), "m" (dst), "m" (src), - "m" (sum), "m" (dst_step), "m" (src_step), - "m" (sum_step), "m" (old_ebx) - : "esi", "edi", "edx", "ecx", "eax" + "6:" + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %1, %%ebx\n",) + + : "+&rm" (size), GCC_PIC_SWITCH("=m","=X") (old_ebx) + : "m" (dst), "m" (src), "m" (sum), + "im" (dst_step), "im" (src_step), "im" (sum_step) + : "esi", "edi", "edx", "ecx", GCC_PIC_SWITCH(,"ebx"COMMA) "eax", + "memory", "cc" ); } @@ -480,13 +502,14 @@ static void MIX_AREAS_24_CMOV(unsigned int size, __asm__ __volatile__ ( "\n" - "\tmovl %%ebx, %7\n" /* ebx is GOT pointer (-fPIC) */ + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %%ebx, %1\n",) /* * initialization, load ESI, EDI, EBX registers */ - "\tmovl %1, %%edi\n" - "\tmovl %2, %%esi\n" - "\tmovl %3, %%ebx\n" + "\tmovl %2, %%edi\n" + "\tmovl %3, %%esi\n" + "\tmovl %4, %%ebx\n" "\tcmpl $0, %0\n" "\tjz 6f\n" @@ -541,19 +564,20 @@ static void MIX_AREAS_24_CMOV(unsigned int size, /* * while (size-- > 0) */ - "\tadd %4, %%edi\n" - "\tadd %5, %%esi\n" - "\tadd %6, %%ebx\n" + "\tadd %5, %%edi\n" + "\tadd %6, %%esi\n" + "\tadd %7, %%ebx\n" "\tdecl %0\n" "\tjnz 1b\n" - - "6:" - "\tmovl %7, %%ebx\n" /* ebx is GOT pointer (-fPIC) */ - : /* no output regs */ - : "m" (size), "m" (dst), "m" (src), - "m" (sum), "m" (dst_step), "m" (src_step), - "m" (sum_step), "m" (old_ebx) - : "esi", "edi", "edx", "ecx", "eax" + "6:" + /* ebx is GOT pointer (-fPIC) */ + GCC_PIC_SWITCH("\tmovl %1, %%ebx\n",) + + : "+&rm" (size), GCC_PIC_SWITCH("=m","=X") (old_ebx) + : "m" (dst), "m" (src), "m" (sum), + "im" (dst_step), "im" (src_step), "im" (sum_step) + : "esi", "edi", "edx", "ecx", GCC_PIC_SWITCH(,"ebx"COMMA) "eax", + "memory", "cc" ); } -- 2.17.1

3 5

[RFC] DPCM for Tegra
by Sameer Pujar 06 May '20

06 May '20

Hi Mark, Earlier I had sent Tegra ASoC series [0] for review and writing back to follow up on the same. Background ========== There were following concerns on [0]: - Usage of mixer control overrides in each driver for PCM parameters. - Exposure of routing controls to the user. The comments are mostly captured in [1] and [2]. There was a suggestion to use DPCM for the Tegra audio requirements. Note: As of now, below does not cover specific solution for propogation of audio configurations or PCM parameters (like sample rate, sample size and channels). DPCM Testing ============ Since then I was looking into internals of DPCM and was trying to get it working with Tegra. I was able to get following things working. - Audio playback/capture over I2S/DMIC/DSPK. - Audio resampling use case. - Mixing of two audio streams with resampler in the path. Objective was to understand and get audio working with DPCM. Please note that I used simple-card DPCM driver for a quick testing on top of the above Tegra Audio series. I had to tweak the simple-card driver a little, but currently keeping it out of the scope of current discussion. At a high level Tegra Audio HW is depicted as below. | Front End PCMs | SoC DSP | Back End DAIs | ************* ADMAIF<0> <------------> * * <----DAI<0>-----> I2S * * ADMAIF<1> <------------> * * <----DAI<1>-----> DMIC * XBAR * ADMAIF<2> <------------> * * <----DAI<2>-----> DSPK * * ADMAIF<N> <------------> * * <----DAI<3>-----> SFC (Resampler) * * * * <----DAI<4>-----> MIXER * * * * <----DAI<N>-----> ... ************* Note: ----- * XBAR is just a cross bar interconnecting one component to another. Specific switch needs to be programmed for audio data to flow from one component to another. * SFC or Mixer are separate HW blocks and separate ASoC drivers are written for these. These drivers were not sent earlier as part of initial upstream series [0]. Follow up queries ================= Based on the above experience I do have few follow up queries and request for your inputs on this. a) Can I use a DAPM Mux control to activate a BE path? This in turn can program required switch in XBAR. This is needed for following reasons: - For an open platform like Jetson, we want to give maximum flexibility for a user to customize their audio paths. Number of connected components and order of these can vary depending on a use case. - Allow re-use of audio components across multiple use cases. For example, number of SFC instances are lesser than PCM playback or capture devices. b) I have modelled SFC and MIXER as backends. Is this allowed? This was done to include SFC or MIXER HW components as part of the sound card and use like below in one of the audio use cases. ADMAIF1(FE) --> SFC(BE1) --> I2S(BE2) ... OR ADMAIF2(FE) --> SFC(BE1) --> I2S(BE2) ... I used following workaround to connect multiple BE components. With this I can see PCM callbacks happen for all BE DAIs along the DAPM path. The obective was to connect multiple components together and (a) was used to connect one component to another. Each "-->" here connects two components and it is a switch in XBAR. --- sound/soc/soc-pcm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c index e256d43..ee7af55 100644 --- a/sound/soc/soc-pcm.c +++ b/sound/soc/soc-pcm.c @@ -1494,7 +1494,7 @@ int dpcm_path_get(struct snd_soc_pcm_runtime *fe, /* get number of valid DAI paths and their widgets */ paths = snd_soc_dapm_dai_get_connected_widgets(cpu_dai, stream, list, - dpcm_end_walk_at_be); + NULL); dev_dbg(fe->dev, "ASoC: found %d audio %s paths\n", paths, stream ? "capture" : "playback"); -- c) Hostless mode did NOT work: - Following audio path was intended to be tested: I2S1 --> SFC --> I2S2 - [3] offers two options: * CODEC<->CODEC: If I were to use a separate DAI link for each BE to BE connection, then it will result in a similar design what we have currently. * Hostless: I did not come across references for this. (Any references in this regard will be helpful) May be the current Tegra ASoC design is more suitable for component model as you had previously mentioned. I wanted to understand if above, especially (a) and (b), are acceptable in this regard or if there are better options to interconnect multiple ASoC components. Looking forward for your feedback. Thanks, Sameer. References ========== [0] http://patchwork.ozlabs.org/project/linux-tegra/list/?series=159664&archive… [1] http://patchwork.ozlabs.org/project/linux-tegra/patch/1582180492-25297-6-gi… [2] http://patchwork.ozlabs.org/project/linux-tegra/patch/1582180492-25297-4-gi… [3] https://www.kernel.org/doc/html/v5.6/sound/soc/dpcm.html

3 6

RE: [PATCH 0/1] Fiji GPU audio register timeout when in BACO state
by Deucher, Alexander 06 May '20

06 May '20

[AMD Public Use] > -----Original Message----- > From: Nicholas Johnson <nicholas.johnson-opensource(a)outlook.com.au> > Sent: Sunday, April 26, 2020 12:02 PM > To: linux-kernel(a)vger.kernel.org > Cc: Deucher, Alexander <Alexander.Deucher(a)amd.com>; Koenig, Christian > <Christian.Koenig(a)amd.com>; Zhou, David(ChunMing) > <David1.Zhou(a)amd.com>; Nicholas Johnson <nicholas.johnson- > opensource(a)outlook.com.au> > Subject: [PATCH 0/1] Fiji GPU audio register timeout when in BACO state > > Hi all, > > Since Linux v5.7-rc1 / commit 4fdda2e66de0 ("drm/amdgpu/runpm: enable > runpm on baco capable VI+ asics"), my AMD R9 Nano has been using runpm / > BACO. You can tell visually when it sleeps, because the fan on the graphics > card is switched off to save power. It did not spin down the fan in v5.6.x. > > This is great (I love it), except that when it is sleeping, the PCIe audio function > of the GPU has issues if anything tries to access it. You get dmesg errors such > as these: > > snd_hda_intel 0000:08:00.1: spurious response 0x0:0x0, last cmd=0x170500 > snd_hda_intel 0000:08:00.1: azx_get_response timeout, switching to polling > mode: last cmd=0x001f0500 snd_hda_intel 0000:08:00.1: No response from > codec, disabling MSI: last cmd=0x001f0500 snd_hda_intel 0000:08:00.1: No > response from codec, resetting bus: last cmd=0x001f0500 > snd_hda_codec_hdmi hdaudioC1D0: Unable to sync register 0x2f0d00. -11 > > The above is with the Fiji XT GPU at 0000:08:00.0 in a Thunderbolt enclosure > (not that Thunderbolt should affect it, but I feel I should mention it just in > case). I dropped a lot of duplicate dmesg lines, as some of them repeated a > lot of times before the driver gave up. > > I offer this patch to disable runpm for Fiji while a fix is found, if you decide > that is the best approach. Regardless, I will gladly test any patches you come > up with instead and confirm that the above issue has been fixed. > > I cannot tell if any other GPUs are affected. The only other cards to which I > have access are a couple of AMD R9 280X (Tahiti XT), which use radeon driver > instead of amdgpu driver. Adding a few more people. Do you know what is accessing the audio? The audio should have a dependency on the GPU device. The GPU won't enter runtime pm until the audio has entered runtime pm and vice versa on resume. Please attach a copy of your dmesg output and lspci output. Alex

5 23

[PATCH v2 1/2] dt-bindings: sound: lpass-cpu: Document DAI subnodes
by Stephan Gerhold 06 May '20

06 May '20

The lpass-cpu driver now allows configuring the MI2S SD lines by defining subnodes for one of the DAIs. Document this in the device tree bindings. Signed-off-by: Stephan Gerhold <stephan(a)gerhold.net> --- Changes in v2: - Clarify number of entries for qcom,playback/capture-sd-lines - Suggest more generic node names (dai@...) for children DAI device nodes v1: https://lore.kernel.org/alsa-devel/20200406135608.126171-1-stephan@gerhold.… --- .../bindings/sound/qcom,lpass-cpu.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt index 21c648328be9..32c2cdb3d32f 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt @@ -30,6 +30,8 @@ Required properties: - reg : Must contain an address for each entry in reg-names. - reg-names : A list which must include the following entries: * "lpass-lpaif" +- #address-cells : Must be 1 +- #size-cells : Must be 0 @@ -37,6 +39,20 @@ Optional properties: - qcom,adsp : Phandle for the audio DSP node +By default, the driver uses up to 4 MI2S SD lines, for a total of 8 channels. +The SD lines to use can be configured by adding subnodes for each of the DAIs. + +Required properties for each DAI (represented by a subnode): +- reg : Must be one of the DAI IDs + (usually part of dt-bindings header) +- qcom,playback-sd-lines: List of serial data lines to use for playback + Each SD line should be represented by a number from 0-3. +- qcom,capture-sd-lines : List of serial data lines to use for capture + Each SD line should be represented by a number from 0-3. + +Note that adding a subnode changes the default to "no lines configured", +so both playback and capture lines should be configured when a subnode is added. + Example: lpass@28100000 { @@ -51,4 +67,13 @@ lpass@28100000 { reg = <0x28100000 0x10000>; reg-names = "lpass-lpaif"; qcom,adsp = <&adsp>; + + #address-cells = <1>; + #size-cells = <0>; + + /* Optional to set different MI2S SD lines */ + dai@3 { + reg = <MI2S_QUATERNARY>; + qcom,playback-sd-lines = <0 1>; + }; }; -- 2.26.2

3 3

[alsa-devel] [RESEND PATCH] ASoC: wm8524: Add support S32_LE
by Shengjiu Wang 05 May '20

05 May '20

Allow 32bit sample with this codec. Signed-off-by: Shengjiu Wang <shengjiu.wang(a)nxp.com> --- sound/soc/codecs/wm8524.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/wm8524.c b/sound/soc/codecs/wm8524.c index 91e3d1570c45..4e9ab542f648 100644 --- a/sound/soc/codecs/wm8524.c +++ b/sound/soc/codecs/wm8524.c @@ -159,7 +159,9 @@ static int wm8524_mute_stream(struct snd_soc_dai *dai, int mute, int stream) #define WM8524_RATES SNDRV_PCM_RATE_8000_192000 -#define WM8524_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) +#define WM8524_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) static const struct snd_soc_dai_ops wm8524_dai_ops = { .startup = wm8524_startup, -- 2.21.0

2 1

[PATCH v4] ucm2: hdadsp: add basic ucm config
by Mateusz Gorski 04 May '20

04 May '20

Basic UCM configuration for Intel Skylake SST with HDA DSP generic machine driver enabling codec playback and capture on both HDA codec and DMIC ports. Signed-off-by: Mateusz Gorski <mateusz.gorski(a)linux.intel.com> --- Changes in v4: - adjusted folder and files names to hda-dsp instead of hdadsp ucm2/hda-dsp/Hdmi1.conf | 24 ++++++++++ ucm2/hda-dsp/Hdmi2.conf | 24 ++++++++++ ucm2/hda-dsp/HiFi.conf | 96 +++++++++++++++++++++++++++++++++++++++ ucm2/hda-dsp/hda-dsp.conf | 16 +++++++ 4 files changed, 160 insertions(+) create mode 100644 ucm2/hda-dsp/Hdmi1.conf create mode 100644 ucm2/hda-dsp/Hdmi2.conf create mode 100644 ucm2/hda-dsp/HiFi.conf create mode 100644 ucm2/hda-dsp/hda-dsp.conf diff --git a/ucm2/hda-dsp/Hdmi1.conf b/ucm2/hda-dsp/Hdmi1.conf new file mode 100644 index 0000000..d402dab --- /dev/null +++ b/ucm2/hda-dsp/Hdmi1.conf @@ -0,0 +1,24 @@ +# Usecase for device HDMI1/Display Port stereo playback on Intel cAVS platforms +# For Audio in HDA mode + +SectionDevice."HDMI1" { + Comment "HDMI/Display Port 1 Stereo" + + Value { + PlaybackPriority 300 + PlaybackPCM "hw:${CardId},10" + If.1 { + Condition { + Type ControlExists + Control "iface=CARD,name='HDMI/DP,pcm=17 Jack'" + } + True { + JackControl "HDMI/DP,pcm=17 Jack" + } + False { + JackControl "HDMI/DP, pcm=17 Jack" + } + } + } +} + diff --git a/ucm2/hda-dsp/Hdmi2.conf b/ucm2/hda-dsp/Hdmi2.conf new file mode 100644 index 0000000..153bbe1 --- /dev/null +++ b/ucm2/hda-dsp/Hdmi2.conf @@ -0,0 +1,24 @@ +# Usecase for device HDMI2/Display Port stereo playback on Intel cAVS platforms +# For Audio in HDA mode + +SectionDevice."HDMI2" { + Comment "HDMI/Display Port 2 Stereo" + + Value { + PlaybackPriority 400 + PlaybackPCM "hw:${CardId},11" + If.1 { + Condition { + Type ControlExists + Control "iface=CARD,name='HDMI/DP,pcm=18 Jack'" + } + True { + JackControl "HDMI/DP,pcm=18 Jack" + } + False { + JackControl "HDMI/DP, pcm=18 Jack" + } + } + } +} + diff --git a/ucm2/hda-dsp/HiFi.conf b/ucm2/hda-dsp/HiFi.conf new file mode 100644 index 0000000..cdeb215 --- /dev/null +++ b/ucm2/hda-dsp/HiFi.conf @@ -0,0 +1,96 @@ +# Usecase for stereo playback Speaker and Headset, Recording on DMIC and Headset MIC. +# For Audio in HDA mode on Intel cAVS platforms + +SectionVerb { + + EnableSequence [ + cset "name='mch_cap_out mo mch_cap_in mi Switch' 1" + ] + + Value { + TQ "HiFi" + } +} + +SectionDevice."Headphones" { + Comment "Headphones" + + ConflictingDevice [ + "Speaker" + ] + + EnableSequence [ + cset "name='Headphone Playback Switch' 1,1" + cset "name='Speaker Playback Switch' 0,0" + ] + + Value { + PlaybackPriority 200 + PlaybackPCM "hw:${CardId},7" + PlaybackMixerElem "Headphone" + PlaybackMasterElem "Master" + PlaybackVolume "Headphone Playback Volume" + PlaybackSwitch "Headphone Playback Switch" + JackControl "Front Headphone Jack" + JackHWMute "Speaker" + } +} + +SectionDevice."Speaker" { + Comment "Speaker" + + ConflictingDevice [ + "Headphones" + ] + + EnableSequence [ + cset "name='Headphone Playback Switch' 0,0" + cset "name='Speaker Playback Switch' 1,1" + ] + + Value { + PlaybackPriority 100 + PlaybackPCM "hw:${CardId},7" + PlaybackMixerElem "Speaker" + PlaybackMasterElem "Master" + PlaybackVolume "Speaker Playback Volume" + PlaybackSwitch "Speaker Playback Switch" + } +} + +SectionDevice."Headset" { + Comment "Headset Microphone" + + ConflictingDevice [ + "Mic" + ] + + EnableSequence [ + cset "name='media0_out mo codec0_in mi Switch' 1" + ] + + Value { + CapturePriority 200 + CapturePCM "hw:${CardId},7" + } +} + +SectionDevice."Mic" { + Comment "Digital Microphone" + + ConflictingDevice [ + "Headset" + ] + + EnableSequence [ + cset "name='mch_cap_out mo mch_cap_in mi Switch' 1" + ] + + Value { + CapturePriority 100 + CapturePCM "hw:${CardId},13" + } +} + +<hda-dsp/Hdmi1.conf> +<hda-dsp/Hdmi2.conf> diff --git a/ucm2/hda-dsp/hda-dsp.conf b/ucm2/hda-dsp/hda-dsp.conf new file mode 100644 index 0000000..48c07c8 --- /dev/null +++ b/ucm2/hda-dsp/hda-dsp.conf @@ -0,0 +1,16 @@ +# UCM for Intel CAVS platforms +# For Audio in HDA and DMIC mode + +Syntax 2 + +SectionUseCase."HiFi" { + File "HiFi.conf" + Comment "Play HiFi quality Music" +} + +SectionDefaults [ + cset "name='Master Playback Switch' 1" + cset "name='codec0_out mo media0_in mi Switch' 1" + cset "name='media0_out mo codec0_in mi Switch' 1" + cset "name='mch_cap_out mo mch_cap_in mi Switch' 1" +] -- 2.17.1

3 2

[PATCH v4] topology: Add topology file for generic HDA DSP machine driver
by Mateusz Gorski 04 May '20

04 May '20

Provide conf file with topology for generic HDA DSP machine driver configuration. This topology is meant to be used with Intel Skylake SST driver. Signed-off-by: Mateusz Gorski <mateusz.gorski(a)linux.intel.com> --- Changes in v4: - changed get and put enum ops for DMIC paths - removed "write" and "read_write" rights for DMIC multi-config enums .../hda-dsp/skl_hda_dsp_generic-tplg.conf | 8265 +++++++++++++++++ 1 file changed, 8265 insertions(+) create mode 100644 topology/hda-dsp/skl_hda_dsp_generic-tplg.conf diff --git a/topology/hda-dsp/skl_hda_dsp_generic-tplg.conf b/topology/hda-dsp/skl_hda_dsp_generic-tplg.conf new file mode 100644 index 0000000..32ba9a7 --- /dev/null +++ b/topology/hda-dsp/skl_hda_dsp_generic-tplg.conf @@ -0,0 +1,8265 @@ + +SectionVendorTokens."skl_tokens" { + SKL_TKN_UUID "1" + SKL_TKN_U8_NUM_BLOCKS "2" + SKL_TKN_U8_BLOCK_TYPE "3" + SKL_TKN_U8_IN_PIN_TYPE "4" + SKL_TKN_U8_OUT_PIN_TYPE "5" + SKL_TKN_U8_DYN_IN_PIN "6" + SKL_TKN_U8_DYN_OUT_PIN "7" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "9" + SKL_TKN_U8_TIME_SLOT "10" + SKL_TKN_U8_CORE_ID "11" + SKL_TKN_U8_MODULE_TYPE "12" + SKL_TKN_U8_CONN_TYPE "13" + SKL_TKN_U8_DEV_TYPE "14" + SKL_TKN_U8_HW_CONN_TYPE "15" + SKL_TKN_U16_MOD_INST_ID "16" + SKL_TKN_U16_BLOCK_SIZE "17" + SKL_TKN_U32_MAX_MCPS "18" + SKL_TKN_U32_MEM_PAGES "19" + SKL_TKN_U32_OBS "20" + SKL_TKN_U32_IBS "21" + SKL_TKN_U32_VBUS_ID "22" + SKL_TKN_U32_PARAMS_FIXUP "23" + SKL_TKN_U32_CONVERTER "24" + SKL_TKN_U32_PIPE_ID "25" + SKL_TKN_U32_PIPE_CONN_TYPE "26" + SKL_TKN_U32_PIPE_PRIORITY "27" + SKL_TKN_U32_PIPE_MEM_PGS "28" + SKL_TKN_U32_DIR_PIN_COUNT "29" + SKL_TKN_U32_FMT_CH "30" + SKL_TKN_U32_FMT_FREQ "31" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "33" + SKL_TKN_U32_FMT_CH_CONFIG "34" + SKL_TKN_U32_FMT_INTERLEAVE "35" + SKL_TKN_U32_FMT_SAMPLE_TYPE "36" + SKL_TKN_U32_FMT_CH_MAP "37" + SKL_TKN_U32_PIN_MOD_ID "38" + SKL_TKN_U32_PIN_INST_ID "39" + SKL_TKN_U32_MOD_SET_PARAMS "40" + SKL_TKN_U32_MOD_PARAM_ID "41" + SKL_TKN_U32_CAPS_SET_PARAMS "42" + SKL_TKN_U32_CAPS_PARAMS_ID "43" + SKL_TKN_U32_CAPS_SIZE "44" + SKL_TKN_U32_PROC_DOMAIN "45" + SKL_TKN_U32_LIB_COUNT "46" + SKL_TKN_STR_LIB_NAME "47" + SKL_TKN_U32_PMODE "48" + SKL_TKN_U32_D0I3_CAPS "49" + SKL_TKN_U32_DMA_BUF_SIZE "50" + SKL_TKN_U32_PIPE_DIRECTION "51" + SKL_TKN_U32_PIPE_CONFIG_ID "52" + SKL_TKN_U32_NUM_CONFIGS "53" + SKL_TKN_U32_PATH_MEM_PGS "54" + SKL_TKN_U32_CFG_FREQ "55" + SKL_TKN_U8_CFG_CHAN "56" + SKL_TKN_U8_CFG_BPS "57" + SKL_TKN_CFG_MOD_RES_ID "58" + SKL_TKN_CFG_MOD_FMT_ID "59" + SKL_TKN_U8_NUM_MOD "60" + SKL_TKN_MM_U8_MOD_IDX "61" + SKL_TKN_MM_U8_NUM_RES "62" + SKL_TKN_MM_U8_NUM_INTF "63" + SKL_TKN_MM_U32_RES_ID "64" + SKL_TKN_MM_U32_CPS "65" + SKL_TKN_MM_U32_DMA_SIZE "66" + SKL_TKN_MM_U32_CPC "67" + SKL_TKN_MM_U32_RES_PIN_ID "68" + SKL_TKN_MM_U32_INTF_PIN_ID "69" + SKL_TKN_MM_U32_PIN_BUF "70" + SKL_TKN_MM_U32_FMT_ID "71" + SKL_TKN_MM_U32_NUM_IN_FMT "72" + SKL_TKN_MM_U32_NUM_OUT_FMT "73" + SKL_TKN_U32_ASTATE_IDX "74" + SKL_TKN_U32_ASTATE_COUNT "75" + SKL_TKN_U32_ASTATE_KCPS "76" + SKL_TKN_U32_ASTATE_CLK_SRC "77" + SKL_TKN_U32_DMACTRL_CFG_IDX "82" + SKL_TKN_U32_DMACTRL_CFG_SIZE "83" + SKL_TKN_U32_DMA_IDX "84" + SKL_TKN_U32_DMA_TYPE "85" + SKL_TKN_U32_DMA_SIZE "86" + SKL_TKN_U32_DMA_MAX_SIZE "87" + SKL_TKN_U32_DMA_MIN_SIZE "88" + SKL_TKN_U32_SCH_TYPE "89" + SKL_TKN_U32_SCH_SIZE "90" + SKL_TKN_U32_SCH_SYS_TICK_MUL "91" + SKL_TKN_U32_SCH_SYS_TICK_DIV "92" + SKL_TKN_U32_SCH_SYS_TICK_LL_SRC "93" + SKL_TKN_U32_SCH_SYS_TICK_CFG_LEN "94" + SKL_TKN_U32_SCH_SYS_TICK_CFG "95" + SKL_TKN_U32_FMT_CFG_IDX "96" +} + +SectionVendorTuples."mod_type_data_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "6436" + } +} + +SectionData."mod_type_data_size_desc" { + tuples "mod_type_data_size_desc" +} + +SectionVendorTuples."mod_type_data" { + tokens "skl_tokens" + + tuples."byte.u8_num_mod" { + SKL_TKN_U8_NUM_MOD "5" + } + + tuples."uuid.mod_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_mod_type_0" { + SKL_TKN_MM_U8_MOD_IDX "0" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "3" + SKL_TKN_MM_U8_NUM_RES "2" + SKL_TKN_MM_U8_NUM_INTF "2" + } + + tuples."word.u32_mod_type_0_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2666000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2666" + } + + tuples."word.u32_mod_type_0_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_0_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_0_res_1" { + SKL_TKN_MM_U32_RES_ID "1" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2666000" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_OBS "768" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2666" + } + + tuples."word.u32_mod_type_0_res_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_0_res_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_0_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_0_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_0_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_0_intf_1" { + SKL_TKN_MM_U32_FMT_ID "1" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_0_intf_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_0_intf_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_1" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_mod_type_1" { + SKL_TKN_MM_U8_MOD_IDX "1" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "2" + SKL_TKN_MM_U8_NUM_INTF "2" + } + + tuples."word.u32_mod_type_1_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1521000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "1521" + } + + tuples."word.u32_mod_type_1_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_1_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_1_res_1" { + SKL_TKN_MM_U32_RES_ID "1" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2666000" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_OBS "768" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2666" + } + + tuples."word.u32_mod_type_1_res_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_1_res_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_1_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_1_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_1_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_1_intf_1" { + SKL_TKN_MM_U32_FMT_ID "1" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_1_intf_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_1_intf_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_2" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_mod_type_2" { + SKL_TKN_MM_U8_MOD_IDX "2" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "4" + SKL_TKN_MM_U8_NUM_RES "15" + SKL_TKN_MM_U8_NUM_INTF "15" + } + + tuples."word.u32_mod_type_2_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2581000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "384" + SKL_TKN_MM_U32_CPC "2581" + } + + tuples."word.u32_mod_type_2_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_1" { + SKL_TKN_MM_U32_RES_ID "1" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_2" { + SKL_TKN_MM_U32_RES_ID "2" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_2_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_2_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_3" { + SKL_TKN_MM_U32_RES_ID "3" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "4473000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "4473" + } + + tuples."word.u32_mod_type_2_res_3_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_3_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_4" { + SKL_TKN_MM_U32_RES_ID "4" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "384" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_4_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_4_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_5" { + SKL_TKN_MM_U32_RES_ID "5" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_5_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_5_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_6" { + SKL_TKN_MM_U32_RES_ID "6" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_OBS "768" + SKL_TKN_MM_U32_DMA_SIZE "1536" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_6_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_6_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_7" { + SKL_TKN_MM_U32_RES_ID "7" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "1536" + SKL_TKN_U32_OBS "1536" + SKL_TKN_MM_U32_DMA_SIZE "3072" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_7_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "1536" + } + + tuples."word.u32_mod_type_2_res_7_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "1536" + } + + tuples."word.u32_mod_type_2_res_8" { + SKL_TKN_MM_U32_RES_ID "8" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "579000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "579" + } + + tuples."word.u32_mod_type_2_res_8_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_8_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_9" { + SKL_TKN_MM_U32_RES_ID "9" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_9_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_9_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_10" { + SKL_TKN_MM_U32_RES_ID "10" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_10_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_10_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_11" { + SKL_TKN_MM_U32_RES_ID "11" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_11_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_11_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_12" { + SKL_TKN_MM_U32_RES_ID "12" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_12_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_12_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_13" { + SKL_TKN_MM_U32_RES_ID "13" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "768" + SKL_TKN_MM_U32_DMA_SIZE "1536" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_13_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_13_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_14" { + SKL_TKN_MM_U32_RES_ID "14" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "1536" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_14_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_14_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_1" { + SKL_TKN_MM_U32_FMT_ID "1" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_2" { + SKL_TKN_MM_U32_FMT_ID "2" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_2_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_2_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_3" { + SKL_TKN_MM_U32_FMT_ID "3" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_3_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_3_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_4" { + SKL_TKN_MM_U32_FMT_ID "4" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_4_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_4_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_5" { + SKL_TKN_MM_U32_FMT_ID "5" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_5_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_5_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_6" { + SKL_TKN_MM_U32_FMT_ID "6" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_6_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "6" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "8" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4283707920" + } + + tuples."word.u32_mod_type_2_intf_6_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "6" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "8" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4283707920" + } + + tuples."word.u32_mod_type_2_intf_7" { + SKL_TKN_MM_U32_FMT_ID "7" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_7_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "8" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "14" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "1985229328" + } + + tuples."word.u32_mod_type_2_intf_7_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "8" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "14" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "1985229328" + } + + tuples."word.u32_mod_type_2_intf_8" { + SKL_TKN_MM_U32_FMT_ID "8" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_8_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_8_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_9" { + SKL_TKN_MM_U32_FMT_ID "9" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_9_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_9_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_10" { + SKL_TKN_MM_U32_FMT_ID "10" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_10_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_10_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_11" { + SKL_TKN_MM_U32_FMT_ID "11" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_11_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_11_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_12" { + SKL_TKN_MM_U32_FMT_ID "12" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_12_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_12_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_13" { + SKL_TKN_MM_U32_FMT_ID "13" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_13_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_13_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_14" { + SKL_TKN_MM_U32_FMT_ID "14" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_14_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_14_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."uuid.mod_3" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."byte.u8_mod_type_3" { + SKL_TKN_MM_U8_MOD_IDX "3" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_3_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "100000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2106" + } + + tuples."word.u32_mod_type_3_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_3_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_3_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_3_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_3_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_4" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."byte.u8_mod_type_4" { + SKL_TKN_MM_U8_MOD_IDX "4" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_4_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "4" + SKL_TKN_MM_U32_CPS "100000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "10157" + } + + tuples."word.u32_mod_type_4_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_4_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_4_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_4_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_4_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } +} + +SectionData."mod_type_data" { + tuples "mod_type_data" +} + +SectionVendorTuples."media0_in cpr 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in cpr 0 num_desc" { + tuples "media0_in cpr 0 num_desc" +} + +SectionVendorTuples."media0_in cpr 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media0_in cpr 0_size_desc" { + tuples "media0_in cpr 0_size_desc" +} + +SectionVendorTuples."media0_in cpr 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "7" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media0_in cpr 0" { + tuples "media0_in cpr 0" +} + +SectionWidget."media0_in cpr 0" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media0_in cpr 0 num_desc" + "media0_in cpr 0_size_desc" + "media0_in cpr 0" + ] +} + +SectionVendorTuples."media0_in updwmix 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in updwmix 0 num_desc" { + tuples "media0_in updwmix 0 num_desc" +} + +SectionVendorTuples."media0_in updwmix 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "388" + } +} + +SectionData."media0_in updwmix 0_size_desc" { + tuples "media0_in updwmix 0_size_desc" +} + +SectionVendorTuples."media0_in updwmix 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "2" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "8" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } +} + +SectionData."media0_in updwmix 0" { + tuples "media0_in updwmix 0" +} + +SectionWidget."media0_in updwmix 0" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_in updwmix 0 num_desc" + "media0_in updwmix 0_size_desc" + "media0_in updwmix 0" + ] +} + +SectionVendorTuples."media0_in srcintc 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in srcintc 0 num_desc" { + tuples "media0_in srcintc 0 num_desc" +} + +SectionVendorTuples."media0_in srcintc 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "388" + } +} + +SectionData."media0_in srcintc 0_size_desc" { + tuples "media0_in srcintc 0_size_desc" +} + +SectionVendorTuples."media0_in srcintc 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "3" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "1" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "7" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } +} + +SectionData."media0_in srcintc 0" { + tuples "media0_in srcintc 0" +} + +SectionWidget."media0_in srcintc 0" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_in srcintc 0 num_desc" + "media0_in srcintc 0_size_desc" + "media0_in srcintc 0" + ] +} + +SectionVendorTuples."media0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in mi num_desc" { + tuples "media0_in mi num_desc" +} + +SectionVendorTuples."media0_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media0_in mi_size_desc" { + tuples "media0_in mi_size_desc" +} + +SectionVendorTuples."media0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "8" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media0_in mi" { + tuples "media0_in mi" +} + +SectionWidget."media0_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media0_in mi num_desc" + "media0_in mi_size_desc" + "media0_in mi" + ] +} + +SectionVendorTuples."codec0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_out mo num_desc" { + tuples "codec0_out mo num_desc" +} + +SectionVendorTuples."codec0_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec0_out mo_size_desc" { + tuples "codec0_out mo_size_desc" +} + +SectionVendorTuples."codec0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec0_out mo" { + tuples "codec0_out mo" +} + +SectionWidget."codec0_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media0_in mi Switch" + ] + + data [ + "codec0_out mo num_desc" + "codec0_out mo_size_desc" + "codec0_out mo" + ] +} + +SectionVendorTuples."codec0_out cpr 1 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_out cpr 1 num_desc" { + tuples "codec0_out cpr 1 num_desc" +} + +SectionVendorTuples."codec0_out cpr 1_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec0_out cpr 1_size_desc" { + tuples "codec0_out cpr 1_size_desc" +} + +SectionVendorTuples."codec0_out cpr 1" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec0_out cpr 1" { + tuples "codec0_out cpr 1" +} + +SectionWidget."codec0_out cpr 1" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec0_out cpr 1 num_desc" + "codec0_out cpr 1_size_desc" + "codec0_out cpr 1" + ] +} + +SectionWidget."codec0_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."media1_in cpr 2 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_in cpr 2 num_desc" { + tuples "media1_in cpr 2 num_desc" +} + +SectionVendorTuples."media1_in cpr 2_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media1_in cpr 2_size_desc" { + tuples "media1_in cpr 2_size_desc" +} + +SectionVendorTuples."media1_in cpr 2" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media1_in cpr 2" { + tuples "media1_in cpr 2" +} + +SectionWidget."media1_in cpr 2" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media1_in cpr 2 num_desc" + "media1_in cpr 2_size_desc" + "media1_in cpr 2" + ] +} + +SectionVendorTuples."media1_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_in mi num_desc" { + tuples "media1_in mi num_desc" +} + +SectionVendorTuples."media1_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media1_in mi_size_desc" { + tuples "media1_in mi_size_desc" +} + +SectionVendorTuples."media1_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media1_in mi" { + tuples "media1_in mi" +} + +SectionWidget."media1_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media1_in mi num_desc" + "media1_in mi_size_desc" + "media1_in mi" + ] +} + +SectionVendorTuples."codec1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_out mo num_desc" { + tuples "codec1_out mo num_desc" +} + +SectionVendorTuples."codec1_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec1_out mo_size_desc" { + tuples "codec1_out mo_size_desc" +} + +SectionVendorTuples."codec1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec1_out mo" { + tuples "codec1_out mo" +} + +SectionWidget."codec1_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media1_in mi Switch" + ] + + data [ + "codec1_out mo num_desc" + "codec1_out mo_size_desc" + "codec1_out mo" + ] +} + +SectionVendorTuples."codec1_out cpr 3 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_out cpr 3 num_desc" { + tuples "codec1_out cpr 3 num_desc" +} + +SectionVendorTuples."codec1_out cpr 3_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec1_out cpr 3_size_desc" { + tuples "codec1_out cpr 3_size_desc" +} + +SectionVendorTuples."codec1_out cpr 3" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec1_out cpr 3" { + tuples "codec1_out cpr 3" +} + +SectionWidget."codec1_out cpr 3" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec1_out cpr 3 num_desc" + "codec1_out cpr 3_size_desc" + "codec1_out cpr 3" + ] +} + +SectionWidget."codec1_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."media2_in cpr 4 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_in cpr 4 num_desc" { + tuples "media2_in cpr 4 num_desc" +} + +SectionVendorTuples."media2_in cpr 4_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media2_in cpr 4_size_desc" { + tuples "media2_in cpr 4_size_desc" +} + +SectionVendorTuples."media2_in cpr 4" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media2_in cpr 4" { + tuples "media2_in cpr 4" +} + +SectionWidget."media2_in cpr 4" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media2_in cpr 4 num_desc" + "media2_in cpr 4_size_desc" + "media2_in cpr 4" + ] +} + +SectionVendorTuples."media2_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_in mi num_desc" { + tuples "media2_in mi num_desc" +} + +SectionVendorTuples."media2_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media2_in mi_size_desc" { + tuples "media2_in mi_size_desc" +} + +SectionVendorTuples."media2_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media2_in mi" { + tuples "media2_in mi" +} + +SectionWidget."media2_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media2_in mi num_desc" + "media2_in mi_size_desc" + "media2_in mi" + ] +} + +SectionVendorTuples."codec2_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_out mo num_desc" { + tuples "codec2_out mo num_desc" +} + +SectionVendorTuples."codec2_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec2_out mo_size_desc" { + tuples "codec2_out mo_size_desc" +} + +SectionVendorTuples."codec2_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec2_out mo" { + tuples "codec2_out mo" +} + +SectionWidget."codec2_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media2_in mi Switch" + ] + + data [ + "codec2_out mo num_desc" + "codec2_out mo_size_desc" + "codec2_out mo" + ] +} + +SectionVendorTuples."codec2_out cpr 5 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_out cpr 5 num_desc" { + tuples "codec2_out cpr 5 num_desc" +} + +SectionVendorTuples."codec2_out cpr 5_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec2_out cpr 5_size_desc" { + tuples "codec2_out cpr 5_size_desc" +} + +SectionVendorTuples."codec2_out cpr 5" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec2_out cpr 5" { + tuples "codec2_out cpr 5" +} + +SectionWidget."codec2_out cpr 5" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec2_out cpr 5 num_desc" + "codec2_out cpr 5_size_desc" + "codec2_out cpr 5" + ] +} + +SectionWidget."codec2_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."codec0_in cpr 6 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_in cpr 6 num_desc" { + tuples "codec0_in cpr 6 num_desc" +} + +SectionVendorTuples."codec0_in cpr 6_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec0_in cpr 6_size_desc" { + tuples "codec0_in cpr 6_size_desc" +} + +SectionVendorTuples."codec0_in cpr 6" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "9" + SKL_TKN_CFG_MOD_FMT_ID "9" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec0_in cpr 6" { + tuples "codec0_in cpr 6" +} + +SectionWidget."codec0_in cpr 6" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec0_in cpr 6 num_desc" + "codec0_in cpr 6_size_desc" + "codec0_in cpr 6" + ] +} + +SectionVendorTuples."codec0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_in mi num_desc" { + tuples "codec0_in mi num_desc" +} + +SectionVendorTuples."codec0_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec0_in mi_size_desc" { + tuples "codec0_in mi_size_desc" +} + +SectionVendorTuples."codec0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec0_in mi" { + tuples "codec0_in mi" +} + +SectionWidget."codec0_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec0_in mi num_desc" + "codec0_in mi_size_desc" + "codec0_in mi" + ] +} + +SectionWidget."codec0_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_out mo num_desc" { + tuples "media0_out mo num_desc" +} + +SectionVendorTuples."media0_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media0_out mo_size_desc" { + tuples "media0_out mo_size_desc" +} + +SectionVendorTuples."media0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "7" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media0_out mo" { + tuples "media0_out mo" +} + +SectionWidget."media0_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec0_in mi Switch" + ] + + data [ + "media0_out mo num_desc" + "media0_out mo_size_desc" + "media0_out mo" + ] +} + +SectionVendorTuples."media0_out cpr 7 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_out cpr 7 num_desc" { + tuples "media0_out cpr 7 num_desc" +} + +SectionVendorTuples."media0_out cpr 7_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media0_out cpr 7_size_desc" { + tuples "media0_out cpr 7_size_desc" +} + +SectionVendorTuples."media0_out cpr 7" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "7" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "8" + SKL_TKN_CFG_MOD_FMT_ID "8" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media0_out cpr 7" { + tuples "media0_out cpr 7" +} + +SectionWidget."media0_out cpr 7" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_out cpr 7 num_desc" + "media0_out cpr 7_size_desc" + "media0_out cpr 7" + ] +} + +SectionVendorTuples."codec1_in cpr 8 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_in cpr 8 num_desc" { + tuples "codec1_in cpr 8 num_desc" +} + +SectionVendorTuples."codec1_in cpr 8_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec1_in cpr 8_size_desc" { + tuples "codec1_in cpr 8_size_desc" +} + +SectionVendorTuples."codec1_in cpr 8" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "8" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "2" + SKL_TKN_CFG_MOD_FMT_ID "2" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec1_in cpr 8" { + tuples "codec1_in cpr 8" +} + +SectionWidget."codec1_in cpr 8" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec1_in cpr 8 num_desc" + "codec1_in cpr 8_size_desc" + "codec1_in cpr 8" + ] +} + +SectionVendorTuples."codec1_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_in mi num_desc" { + tuples "codec1_in mi num_desc" +} + +SectionVendorTuples."codec1_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec1_in mi_size_desc" { + tuples "codec1_in mi_size_desc" +} + +SectionVendorTuples."codec1_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "8" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec1_in mi" { + tuples "codec1_in mi" +} + +SectionWidget."codec1_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec1_in mi num_desc" + "codec1_in mi_size_desc" + "codec1_in mi" + ] +} + +SectionWidget."codec1_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_out mo num_desc" { + tuples "media1_out mo num_desc" +} + +SectionVendorTuples."media1_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media1_out mo_size_desc" { + tuples "media1_out mo_size_desc" +} + +SectionVendorTuples."media1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "9" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media1_out mo" { + tuples "media1_out mo" +} + +SectionWidget."media1_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec1_in mi Switch" + ] + + data [ + "media1_out mo num_desc" + "media1_out mo_size_desc" + "media1_out mo" + ] +} + +SectionVendorTuples."media1_out cpr 9 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_out cpr 9 num_desc" { + tuples "media1_out cpr 9 num_desc" +} + +SectionVendorTuples."media1_out cpr 9_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media1_out cpr 9_size_desc" { + tuples "media1_out cpr 9_size_desc" +} + +SectionVendorTuples."media1_out cpr 9" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "9" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "3" + SKL_TKN_CFG_MOD_FMT_ID "3" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media1_out cpr 9" { + tuples "media1_out cpr 9" +} + +SectionWidget."media1_out cpr 9" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media1_out cpr 9 num_desc" + "media1_out cpr 9_size_desc" + "media1_out cpr 9" + ] +} + +SectionVendorTuples."codec2_in cpr 10 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_in cpr 10 num_desc" { + tuples "codec2_in cpr 10 num_desc" +} + +SectionVendorTuples."codec2_in cpr 10_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec2_in cpr 10_size_desc" { + tuples "codec2_in cpr 10_size_desc" +} + +SectionVendorTuples."codec2_in cpr 10" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "10" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "2" + SKL_TKN_CFG_MOD_FMT_ID "2" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec2_in cpr 10" { + tuples "codec2_in cpr 10" +} + +SectionWidget."codec2_in cpr 10" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec2_in cpr 10 num_desc" + "codec2_in cpr 10_size_desc" + "codec2_in cpr 10" + ] +} + +SectionVendorTuples."codec2_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_in mi num_desc" { + tuples "codec2_in mi num_desc" +} + +SectionVendorTuples."codec2_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec2_in mi_size_desc" { + tuples "codec2_in mi_size_desc" +} + +SectionVendorTuples."codec2_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "10" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec2_in mi" { + tuples "codec2_in mi" +} + +SectionWidget."codec2_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec2_in mi num_desc" + "codec2_in mi_size_desc" + "codec2_in mi" + ] +} + +SectionWidget."codec2_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media2_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_out mo num_desc" { + tuples "media2_out mo num_desc" +} + +SectionVendorTuples."media2_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media2_out mo_size_desc" { + tuples "media2_out mo_size_desc" +} + +SectionVendorTuples."media2_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "11" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "11" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media2_out mo" { + tuples "media2_out mo" +} + +SectionWidget."media2_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec2_in mi Switch" + ] + + data [ + "media2_out mo num_desc" + "media2_out mo_size_desc" + "media2_out mo" + ] +} + +SectionVendorTuples."media2_out cpr 11 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_out cpr 11 num_desc" { + tuples "media2_out cpr 11 num_desc" +} + +SectionVendorTuples."media2_out cpr 11_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media2_out cpr 11_size_desc" { + tuples "media2_out cpr 11_size_desc" +} + +SectionVendorTuples."media2_out cpr 11" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "11" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "11" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "3" + SKL_TKN_CFG_MOD_FMT_ID "3" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media2_out cpr 11" { + tuples "media2_out cpr 11" +} + +SectionWidget."media2_out cpr 11" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media2_out cpr 11 num_desc" + "media2_out cpr 11_size_desc" + "media2_out cpr 11" + ] +} + +SectionVendorTuples."hdmi1_out cpr 12 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi1_out cpr 12 num_desc" { + tuples "hdmi1_out cpr 12 num_desc" +} + +SectionVendorTuples."hdmi1_out cpr 12_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "788" + } +} + +SectionData."hdmi1_out cpr 12_size_desc" { + tuples "hdmi1_out cpr 12_size_desc" +} + +SectionVendorTuples."hdmi1_out cpr 12" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "12" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "12" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "4" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "5" + SKL_TKN_CFG_MOD_FMT_ID "5" + } + + tuples."word._pipe_2" { + SKL_TKN_U32_PIPE_CONFIG_ID "2" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."word._pipe_u32_cfg_out_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."short.u16_pipe_mod_cfg_2" { + SKL_TKN_CFG_MOD_RES_ID "6" + SKL_TKN_CFG_MOD_FMT_ID "6" + } + + tuples."word._pipe_3" { + SKL_TKN_U32_PIPE_CONFIG_ID "3" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."word._pipe_u32_cfg_out_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."short.u16_pipe_mod_cfg_3" { + SKL_TKN_CFG_MOD_RES_ID "7" + SKL_TKN_CFG_MOD_FMT_ID "7" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "13" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi1_out cpr 12" { + tuples "hdmi1_out cpr 12" +} + +SectionWidget."hdmi1_out cpr 12" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi1_out cpr 12 num_desc" + "hdmi1_out cpr 12_size_desc" + "hdmi1_out cpr 12" + ] +} + +SectionVendorTuples."hdmi1_out cpr 13 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi1_out cpr 13 num_desc" { + tuples "hdmi1_out cpr 13 num_desc" +} + +SectionVendorTuples."hdmi1_out cpr 13_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "728" + } +} + +SectionData."hdmi1_out cpr 13_size_desc" { + tuples "hdmi1_out cpr 13_size_desc" +} + +SectionVendorTuples."hdmi1_out cpr 13" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "13" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "12" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "4" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "5" + SKL_TKN_CFG_MOD_FMT_ID "5" + } + + tuples."word._pipe_2" { + SKL_TKN_U32_PIPE_CONFIG_ID "2" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."word._pipe_u32_cfg_out_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."short.u16_pipe_mod_cfg_2" { + SKL_TKN_CFG_MOD_RES_ID "6" + SKL_TKN_CFG_MOD_FMT_ID "6" + } + + tuples."word._pipe_3" { + SKL_TKN_U32_PIPE_CONFIG_ID "3" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."word._pipe_u32_cfg_out_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."short.u16_pipe_mod_cfg_3" { + SKL_TKN_CFG_MOD_RES_ID "7" + SKL_TKN_CFG_MOD_FMT_ID "7" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "12" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi1_out cpr 13" { + tuples "hdmi1_out cpr 13" +} + +SectionWidget."hdmi1_out cpr 13" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi1_out cpr 13 num_desc" + "hdmi1_out cpr 13_size_desc" + "hdmi1_out cpr 13" + ] +} + +SectionControlEnum."hdmi1_out pcm cfg" { + texts "enum_hdmi1_out pcm cfg" + index "0" + + ops."ctl" { + get "259" + put "259" + info "4" + } + + access [ + "read" + "write" + "read_write" + ] + data "hdmi1_out pcm cfg" +} + +SectionText."enum_hdmi1_out pcm cfg" { + + values [ + "IN:f48000-c2-b16 OUT:f48000-c2-b16" + "IN:f48000-c4-b16 OUT:f48000-c4-b16" + "IN:f48000-c6-b16 OUT:f48000-c6-b16" + "IN:f48000-c8-b16 OUT:f48000-c8-b16" + ] +} + +SectionData."hdmi1_out pcm cfg" { + bytes "0x0C, 0x00, 0x00, 0x00" +} + +SectionWidget."iDisp1_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."hdmi2_out cpr 14 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi2_out cpr 14 num_desc" { + tuples "hdmi2_out cpr 14 num_desc" +} + +SectionVendorTuples."hdmi2_out cpr 14_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "788" + } +} + +SectionData."hdmi2_out cpr 14_size_desc" { + tuples "hdmi2_out cpr 14_size_desc" +} + +SectionVendorTuples."hdmi2_out cpr 14" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "14" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "13" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "4" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "5" + SKL_TKN_CFG_MOD_FMT_ID "5" + } + + tuples."word._pipe_2" { + SKL_TKN_U32_PIPE_CONFIG_ID "2" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."word._pipe_u32_cfg_out_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."short.u16_pipe_mod_cfg_2" { + SKL_TKN_CFG_MOD_RES_ID "6" + SKL_TKN_CFG_MOD_FMT_ID "6" + } + + tuples."word._pipe_3" { + SKL_TKN_U32_PIPE_CONFIG_ID "3" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."word._pipe_u32_cfg_out_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."short.u16_pipe_mod_cfg_3" { + SKL_TKN_CFG_MOD_RES_ID "7" + SKL_TKN_CFG_MOD_FMT_ID "7" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "15" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi2_out cpr 14" { + tuples "hdmi2_out cpr 14" +} + +SectionWidget."hdmi2_out cpr 14" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi2_out cpr 14 num_desc" + "hdmi2_out cpr 14_size_desc" + "hdmi2_out cpr 14" + ] +} + +SectionVendorTuples."hdmi2_out cpr 15 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi2_out cpr 15 num_desc" { + tuples "hdmi2_out cpr 15 num_desc" +} + +SectionVendorTuples."hdmi2_out cpr 15_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "728" + } +} + +SectionData."hdmi2_out cpr 15_size_desc" { + tuples "hdmi2_out cpr 15_size_desc" +} + +SectionVendorTuples."hdmi2_out cpr 15" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "15" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "13" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "4" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "5" + SKL_TKN_CFG_MOD_FMT_ID "5" + } + + tuples."word._pipe_2" { + SKL_TKN_U32_PIPE_CONFIG_ID "2" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."word._pipe_u32_cfg_out_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."short.u16_pipe_mod_cfg_2" { + SKL_TKN_CFG_MOD_RES_ID "6" + SKL_TKN_CFG_MOD_FMT_ID "6" + } + + tuples."word._pipe_3" { + SKL_TKN_U32_PIPE_CONFIG_ID "3" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."word._pipe_u32_cfg_out_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."short.u16_pipe_mod_cfg_3" { + SKL_TKN_CFG_MOD_RES_ID "7" + SKL_TKN_CFG_MOD_FMT_ID "7" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "14" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi2_out cpr 15" { + tuples "hdmi2_out cpr 15" +} + +SectionWidget."hdmi2_out cpr 15" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi2_out cpr 15 num_desc" + "hdmi2_out cpr 15_size_desc" + "hdmi2_out cpr 15" + ] +} + +SectionControlEnum."hdmi2_out pcm cfg" { + texts "enum_hdmi2_out pcm cfg" + index "0" + + ops."ctl" { + get "259" + put "259" + info "4" + } + + access [ + "read" + "write" + "read_write" + ] + data "hdmi2_out pcm cfg" +} + +SectionText."enum_hdmi2_out pcm cfg" { + + values [ + "IN:f48000-c2-b16 OUT:f48000-c2-b16" + "IN:f48000-c4-b16 OUT:f48000-c4-b16" + "IN:f48000-c6-b16 OUT:f48000-c6-b16" + "IN:f48000-c8-b16 OUT:f48000-c8-b16" + ] +} + +SectionData."hdmi2_out pcm cfg" { + bytes "0x0D, 0x00, 0x00, 0x00" +} + +SectionWidget."iDisp2_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."hdmi3_out cpr 16 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi3_out cpr 16 num_desc" { + tuples "hdmi3_out cpr 16 num_desc" +} + +SectionVendorTuples."hdmi3_out cpr 16_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "788" + } +} + +SectionData."hdmi3_out cpr 16_size_desc" { + tuples "hdmi3_out cpr 16_size_desc" +} + +SectionVendorTuples."hdmi3_out cpr 16" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "16" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "14" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "4" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "5" + SKL_TKN_CFG_MOD_FMT_ID "5" + } + + tuples."word._pipe_2" { + SKL_TKN_U32_PIPE_CONFIG_ID "2" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."word._pipe_u32_cfg_out_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."short.u16_pipe_mod_cfg_2" { + SKL_TKN_CFG_MOD_RES_ID "6" + SKL_TKN_CFG_MOD_FMT_ID "6" + } + + tuples."word._pipe_3" { + SKL_TKN_U32_PIPE_CONFIG_ID "3" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."word._pipe_u32_cfg_out_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."short.u16_pipe_mod_cfg_3" { + SKL_TKN_CFG_MOD_RES_ID "7" + SKL_TKN_CFG_MOD_FMT_ID "7" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "17" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi3_out cpr 16" { + tuples "hdmi3_out cpr 16" +} + +SectionWidget."hdmi3_out cpr 16" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi3_out cpr 16 num_desc" + "hdmi3_out cpr 16_size_desc" + "hdmi3_out cpr 16" + ] +} + +SectionVendorTuples."hdmi3_out cpr 17 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi3_out cpr 17 num_desc" { + tuples "hdmi3_out cpr 17 num_desc" +} + +SectionVendorTuples."hdmi3_out cpr 17_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "728" + } +} + +SectionData."hdmi3_out cpr 17_size_desc" { + tuples "hdmi3_out cpr 17_size_desc" +} + +SectionVendorTuples."hdmi3_out cpr 17" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "17" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "14" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "4" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "5" + SKL_TKN_CFG_MOD_FMT_ID "5" + } + + tuples."word._pipe_2" { + SKL_TKN_U32_PIPE_CONFIG_ID "2" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."word._pipe_u32_cfg_out_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_2" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "6" + } + + tuples."short.u16_pipe_mod_cfg_2" { + SKL_TKN_CFG_MOD_RES_ID "6" + SKL_TKN_CFG_MOD_FMT_ID "6" + } + + tuples."word._pipe_3" { + SKL_TKN_U32_PIPE_CONFIG_ID "3" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."word._pipe_u32_cfg_out_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_3" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "8" + } + + tuples."short.u16_pipe_mod_cfg_3" { + SKL_TKN_CFG_MOD_RES_ID "7" + SKL_TKN_CFG_MOD_FMT_ID "7" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "16" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi3_out cpr 17" { + tuples "hdmi3_out cpr 17" +} + +SectionWidget."hdmi3_out cpr 17" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi3_out cpr 17 num_desc" + "hdmi3_out cpr 17_size_desc" + "hdmi3_out cpr 17" + ] +} + +SectionControlEnum."hdmi3_out pcm cfg" { + texts "enum_hdmi3_out pcm cfg" + index "0" + + ops."ctl" { + get "259" + put "259" + info "4" + } + + access [ + "read" + "write" + "read_write" + ] + data "hdmi3_out pcm cfg" +} + +SectionText."enum_hdmi3_out pcm cfg" { + + values [ + "IN:f48000-c2-b16 OUT:f48000-c2-b16" + "IN:f48000-c4-b16 OUT:f48000-c4-b16" + "IN:f48000-c6-b16 OUT:f48000-c6-b16" + "IN:f48000-c8-b16 OUT:f48000-c8-b16" + ] +} + +SectionData."hdmi3_out pcm cfg" { + bytes "0x0E, 0x00, 0x00, 0x00" +} + +SectionWidget."iDisp3_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."mch_cap_in cpr 18 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_in cpr 18 num_desc" { + tuples "mch_cap_in cpr 18 num_desc" +} + +SectionVendorTuples."mch_cap_in cpr 18_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "596" + } +} + +SectionData."mch_cap_in cpr 18_size_desc" { + tuples "mch_cap_in cpr 18_size_desc" +} + +SectionVendorTuples."mch_cap_in cpr 18" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "1" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "18" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "0" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "15" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "2" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "11" + SKL_TKN_CFG_MOD_FMT_ID "11" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "13" + SKL_TKN_CFG_MOD_FMT_ID "13" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."mch_cap_in cpr 18" { + tuples "mch_cap_in cpr 18" +} + +SectionWidget."mch_cap_in cpr 18" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "mch_cap_in cpr 18 num_desc" + "mch_cap_in cpr 18_size_desc" + "mch_cap_in cpr 18" + ] +} + +SectionVendorTuples."mch_cap_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_in mi num_desc" { + tuples "mch_cap_in mi num_desc" +} + +SectionVendorTuples."mch_cap_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "512" + } +} + +SectionData."mch_cap_in mi_size_desc" { + tuples "mch_cap_in mi_size_desc" +} + +SectionVendorTuples."mch_cap_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "15" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "2" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "18" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."mch_cap_in mi" { + tuples "mch_cap_in mi" +} + +SectionWidget."mch_cap_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "mch_cap_in mi num_desc" + "mch_cap_in mi_size_desc" + "mch_cap_in mi" + ] +} + +SectionControlEnum."mch_cap_in pcm cfg" { + texts "enum_mch_cap_in pcm cfg" + index "0" + + ops."ctl" { + get "260" + put "260" + info "4" + } + + access [ + "read" + ] + data "mch_cap_in pcm cfg" +} + +SectionText."enum_mch_cap_in pcm cfg" { + + values [ + "IN:f48000-c2-b16 OUT:f48000-c2-b16" + "IN:f48000-c4-b16 OUT:f48000-c4-b16" + ] +} + +SectionData."mch_cap_in pcm cfg" { + bytes "0x0F, 0x00, 0x00, 0x00" +} + +SectionWidget."DMIC01 Rx" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."mch_cap_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_out mo num_desc" { + tuples "mch_cap_out mo num_desc" +} + +SectionVendorTuples."mch_cap_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "632" + } +} + +SectionData."mch_cap_out mo_size_desc" { + tuples "mch_cap_out mo_size_desc" +} + +SectionVendorTuples."mch_cap_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "16" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "2" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "19" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."mch_cap_out mo" { + tuples "mch_cap_out mo" +} + +SectionWidget."mch_cap_out mo" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + mixer [ + "mch_cap_in mi Switch" + ] + + data [ + "mch_cap_out mo num_desc" + "mch_cap_out mo_size_desc" + "mch_cap_out mo" + ] +} + +SectionVendorTuples."mch_cap_out cpr 19 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_out cpr 19 num_desc" { + tuples "mch_cap_out cpr 19 num_desc" +} + +SectionVendorTuples."mch_cap_out cpr 19_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."mch_cap_out cpr 19_size_desc" { + tuples "mch_cap_out cpr 19_size_desc" +} + +SectionVendorTuples."mch_cap_out cpr 19" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "19" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "16" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "2" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "12" + SKL_TKN_CFG_MOD_FMT_ID "12" + } + + tuples."word._pipe_1" { + SKL_TKN_U32_PIPE_CONFIG_ID "1" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."word._pipe_u32_cfg_out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_1" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "4" + } + + tuples."short.u16_pipe_mod_cfg_1" { + SKL_TKN_CFG_MOD_RES_ID "14" + SKL_TKN_CFG_MOD_FMT_ID "14" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."mch_cap_out cpr 19" { + tuples "mch_cap_out cpr 19" +} + +SectionWidget."mch_cap_out cpr 19" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "mch_cap_out cpr 19 num_desc" + "mch_cap_out cpr 19_size_desc" + "mch_cap_out cpr 19" + ] +} + +SectionControlEnum."mch_cap_out pcm cfg" { + texts "enum_mch_cap_out pcm cfg" + index "0" + + ops."ctl" { + get "260" + put "260" + info "4" + } + + access [ + "read" + ] + data "mch_cap_out pcm cfg" +} + +SectionText."enum_mch_cap_out pcm cfg" { + + values [ + "IN:f48000-c2-b16 OUT:f48000-c2-b16" + "IN:f48000-c4-b16 OUT:f48000-c4-b16" + ] +} + +SectionData."mch_cap_out pcm cfg" { + bytes "0x10, 0x00, 0x00, 0x00" +} + +SectionControlMixer."media0_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."media1_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."media2_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec0_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec1_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec2_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."mch_cap_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionGraph."Pipeline 1 Graph" { + index "0" + + lines [ + "media0_in cpr 0, , hda-dsp-analog-playback" + "media0_in updwmix 0, , media0_in cpr 0" + "media0_in srcintc 0, , media0_in updwmix 0" + "media0_in mi, , media0_in srcintc 0" + "codec0_out cpr 1, , codec0_out mo" + "codec0_out, , codec0_out cpr 1" + "media1_in cpr 2, , hda-dsp-digital-playback" + "media1_in mi, , media1_in cpr 2" + "codec1_out cpr 3, , codec1_out mo" + "codec1_out, , codec1_out cpr 3" + "media2_in cpr 4, , hda-dsp-alt-analog-playback" + "media2_in mi, , media2_in cpr 4" + "codec2_out cpr 5, , codec2_out mo" + "codec2_out, , codec2_out cpr 5" + "codec0_in cpr 6, , codec0_in" + "codec0_in mi, , codec0_in cpr 6" + "media0_out cpr 7, , media0_out mo" + "hda-dsp-audio-analog-capture, , media0_out cpr 7" + "codec1_in cpr 8, , codec1_in" + "codec1_in mi, , codec1_in cpr 8" + "media1_out cpr 9, , media1_out mo" + "hda-dsp-audio-digital-capture, , media1_out cpr 9" + "codec2_in cpr 10, , codec2_in" + "codec2_in mi, , codec2_in cpr 10" + "media2_out cpr 11, , media2_out mo" + "hda-dsp-audio-alt-analog-capture, , media2_out cpr 11" + "hdmi1_out cpr 12, , HDMI1 Playback" + "hdmi1_out cpr 13, , hdmi1_out cpr 12" + "iDisp1_out, , hdmi1_out cpr 13" + "hdmi2_out cpr 14, , HDMI2 Playback" + "hdmi2_out cpr 15, , hdmi2_out cpr 14" + "iDisp2_out, , hdmi2_out cpr 15" + "hdmi3_out cpr 16, , HDMI3 Playback" + "hdmi3_out cpr 17, , hdmi3_out cpr 16" + "iDisp3_out, , hdmi3_out cpr 17" + "mch_cap_in cpr 18, , DMIC01 Rx" + "mch_cap_in mi, , mch_cap_in cpr 18" + "mch_cap_out cpr 19, , mch_cap_out mo" + "DMIC-Capture, , mch_cap_out cpr 19" + "codec0_out mo, media0_in mi Switch, media0_in mi" + "codec1_out mo, media1_in mi Switch, media1_in mi" + "codec2_out mo, media2_in mi Switch, media2_in mi" + "media0_out mo, codec0_in mi Switch, codec0_in mi" + "media1_out mo, codec1_in mi Switch, codec1_in mi" + "media2_out mo, codec2_in mi Switch, codec2_in mi" + "mch_cap_out mo, mch_cap_in mi Switch, mch_cap_in mi" + ] +} + +SectionPCMCapabilities."hda-dsp-analog-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-analog-capture" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."Analog HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-analog-dai" { + id "0" + } + + pcm."playback" { + capabilities "hda-dsp-analog-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-analog-capture" + } +} + +SectionPCMCapabilities."hda-dsp-digital-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-digital-capture" { + formats "S24_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "24" +} + +SectionPCM."Digital HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-digital-dai" { + id "1" + } + + pcm."playback" { + capabilities "hda-dsp-digital-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-digital-capture" + } +} + +SectionPCMCapabilities."hda-dsp-alt-analog-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-alt-analog-capture" { + formats "S24_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "24" +} + +SectionPCM."Alt Analog HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-alt-analog-dai" { + id "2" + } + + pcm."playback" { + capabilities "hda-dsp-alt-analog-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-alt-analog-capture" + } +} + +SectionPCMCapabilities."HDMI1 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "8" + sig_bits "16" +} + +SectionPCM."HDA DSP HDMI1" { + index "0" + id "255" + + dai."hdmi1" { + id "3" + } + + pcm."playback" { + capabilities "HDMI1 Playback" + } +} + +SectionPCMCapabilities."HDMI2 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "8" + sig_bits "16" +} + +SectionPCM."HDA DSP HDMI2" { + index "0" + id "255" + + dai."hdmi2" { + id "4" + } + + pcm."playback" { + capabilities "HDMI2 Playback" + } +} + +SectionPCMCapabilities."HDMI3 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "8" + sig_bits "16" +} + +SectionPCM."HDA DSP HDMI3" { + index "0" + id "255" + + dai."hdmi3" { + id "5" + } + + pcm."playback" { + capabilities "HDMI3 Playback" + } +} + +SectionPCMCapabilities."DMIC-Capture" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "4" + sig_bits "16" +} + +SectionPCM."DMIC1" { + index "0" + id "0" + + dai."hda-dsp-dmic-dai" { + id "6" + } + + pcm."capture" { + capabilities "DMIC-Capture" + } +} + +SectionVendorTuples."manifest_data num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."manifest_data num_desc" { + tuples "manifest_data num_desc" +} + +SectionManifest."manifest_data" { + + data [ + "manifest_data num_desc" + "mod_type_data_size_desc" + "mod_type_data" + ] +} -- 2.17.1

3 2

[PATCH AUTOSEL 5.6 45/79] ASoC: meson: axg-card: fix codec-to-codec link setup
by Sasha Levin 02 May '20

02 May '20

From: Jerome Brunet <jbrunet(a)baylibre.com> [ Upstream commit 1164284270779e1865cc2046a2a01b58a1e858a9 ] Since the addition of commit 9b5db059366a ("ASoC: soc-pcm: dpcm: Only allow playback/capture if supported"), meson-axg cards which have codec-to-codec links fail to init and Oops: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000128 Internal error: Oops: 96000044 [#1] PREEMPT SMP CPU: 3 PID: 1582 Comm: arecord Not tainted 5.7.0-rc1 pc : invalidate_paths_ep+0x30/0xe0 lr : snd_soc_dapm_dai_get_connected_widgets+0x170/0x1a8 Call trace: invalidate_paths_ep+0x30/0xe0 snd_soc_dapm_dai_get_connected_widgets+0x170/0x1a8 dpcm_path_get+0x38/0xd0 dpcm_fe_dai_open+0x70/0x920 snd_pcm_open_substream+0x564/0x840 snd_pcm_open+0xfc/0x228 snd_pcm_capture_open+0x4c/0x78 snd_open+0xac/0x1a8 ... While initiliazing the links, ASoC treats the codec-to-codec links of this card type as a DPCM backend. This error eventually leads to the Oops. Most of the card driver code is shared between DPCM backends and codec-to-codec links. The property "no_pcm" marking DCPM BE was left set on codec-to-codec links, leading to this problem. This commit fixes that. Fixes: 0a8f1117a680 ("ASoC: meson: axg-card: add basic codec-to-codec link support") Signed-off-by: Jerome Brunet <jbrunet(a)baylibre.com> Link: https://lore.kernel.org/r/20200420114511.450560-2-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie(a)kernel.org> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- sound/soc/meson/axg-card.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/soc/meson/axg-card.c b/sound/soc/meson/axg-card.c index 1f698adde506c..2b04ac3d8fd3b 100644 --- a/sound/soc/meson/axg-card.c +++ b/sound/soc/meson/axg-card.c @@ -586,8 +586,10 @@ static int axg_card_add_link(struct snd_soc_card *card, struct device_node *np, if (axg_card_cpu_is_tdm_iface(dai_link->cpus->of_node)) ret = axg_card_parse_tdm(card, np, index); - else if (axg_card_cpu_is_codec(dai_link->cpus->of_node)) + else if (axg_card_cpu_is_codec(dai_link->cpus->of_node)) { dai_link->params = &codec_params; + dai_link->no_pcm = 0; /* link is not a DPCM BE */ + } return ret; } -- 2.20.1

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[PATCH] soundwire: (cosmetic) remove multiple superfluous "else" statements
by Guennadi Liakhovetski 02 May '20

02 May '20

No need for an "else" after a "return" statement. Remove multiple such occurrences. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski(a)linux.intel.com> --- drivers/soundwire/bus.c | 17 ++++++++++------- drivers/soundwire/cadence_master.c | 8 ++++++-- drivers/soundwire/intel_init.c | 4 +++- 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c index 488c3c9..32de017 100644 --- a/drivers/soundwire/bus.c +++ b/drivers/soundwire/bus.c @@ -284,9 +284,10 @@ int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave, msg->flags = flags; msg->buf = buf; - if (addr < SDW_REG_NO_PAGE) { /* no paging area */ + if (addr < SDW_REG_NO_PAGE) /* no paging area */ return 0; - } else if (addr >= SDW_REG_MAX) { /* illegal addr */ + + if (addr >= SDW_REG_MAX) { /* illegal addr */ pr_err("SDW: Invalid address %x passed\n", addr); return -EINVAL; } @@ -306,7 +307,9 @@ int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave, if (!slave) { pr_err("SDW: No slave for paging addr\n"); return -EINVAL; - } else if (!slave->prop.paging_support) { + } + + if (!slave->prop.paging_support) { dev_err(&slave->dev, "address %x needs paging but no support\n", addr); return -EINVAL; @@ -375,8 +378,8 @@ static int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value) ret = sdw_transfer(bus, &msg); if (ret < 0) return ret; - else - return buf; + + return buf; } static int @@ -471,8 +474,8 @@ int sdw_read(struct sdw_slave *slave, u32 addr) ret = sdw_nread(slave, addr, 1, &buf); if (ret < 0) return ret; - else - return buf; + + return buf; } EXPORT_SYMBOL(sdw_read); diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c index ecd357d1..9ea8753 100644 --- a/drivers/soundwire/cadence_master.c +++ b/drivers/soundwire/cadence_master.c @@ -407,7 +407,9 @@ void sdw_cdns_debugfs_init(struct sdw_cdns *cdns, struct dentry *root) if (nack) { dev_err_ratelimited(cdns->dev, "Msg NACKed for Slave %d\n", msg->dev_num); return SDW_CMD_FAIL; - } else if (no_ack) { + } + + if (no_ack) { dev_dbg_ratelimited(cdns->dev, "Msg ignored for Slave %d\n", msg->dev_num); return SDW_CMD_IGNORED; } @@ -520,7 +522,9 @@ void sdw_cdns_debugfs_init(struct sdw_cdns *cdns, struct dentry *root) dev_err_ratelimited(cdns->dev, "SCP_addrpage NACKed for Slave %d\n", msg->dev_num); return SDW_CMD_FAIL; - } else if (no_ack) { + } + + if (no_ack) { dev_dbg_ratelimited(cdns->dev, "SCP_addrpage ignored for Slave %d\n", msg->dev_num); return SDW_CMD_IGNORED; diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c index 4b76940..d5d4279 100644 --- a/drivers/soundwire/intel_init.c +++ b/drivers/soundwire/intel_init.c @@ -86,7 +86,9 @@ static int sdw_intel_cleanup_pdev(struct sdw_intel_ctx *ctx) dev_err(&adev->dev, "Link count %d exceeds max %d\n", count, SDW_MAX_LINKS); return NULL; - } else if (!count) { + } + + if (!count) { dev_warn(&adev->dev, "No SoundWire links detected\n"); return NULL; } -- 1.9.3

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