July 2015 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] Bug on Dell Vostro 5480 (Intel Wildcat) kernel driver
by Paulo Roberto de Oliveira Castro 28 Jul '15

28 Jul '15

Hi everyone, After installing Fedora 22 on my Dell Vostro 5480, the speakers don't work, and the sound only comes out of the subwoofer. Here is the output of alsa-info.sh. After talking to "debianuser" on IRC, we found this workaround: sudo hda-verb /dev/snd/hwC1D0 0x14 SET_PIN_WIDGET_CONTROL 0x40 # enable, set it to OUT sudo hda-verb /dev/snd/hwC1D0 0x14 SET_CONNECT_SEL 0 # switch to 0x0c sudo hda-verb /dev/snd/hwC1D0 0x14 SET_AMP_GAIN_MUTE 0xa000 # unmute left sudo hda-verb /dev/snd/hwC1D0 0x14 SET_AMP_GAIN_MUTE 0x9000 # unmute right We suspect that it's a kernel driver bug. This makes the speakers work alongside the headphones (both at the same time) but I need help making it working when headphones are not plugged in. Thanks, Paulo

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[alsa-devel] [PATCH v2] ALSA: hda - Fix race condition between HDA driver and runtime PM
by U. Artie Eoff 28 Jul '15

28 Jul '15

Don't execute runtime suspend if HDA is not finished initializing. Otherwise, the following errors can occur in hda: snd_hda_intel 0000:00:1b.0: CORB reset timeout#2, CORBRP = 65535 snd_hda_intel 0000:00:1b.0: no codecs initialized Debugged and root-cause found by zhuo-hao.lee(a)intel.com v2: remove unnecessary extra check for chip init (libin) Signed-off-by: U. Artie Eoff <ullysses.a.eoff(a)intel.com> --- sound/pci/hda/hda_intel.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index b729b25a6ad6..15d4e28fc64e 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1017,17 +1017,19 @@ static int azx_runtime_idle(struct device *dev) struct snd_card *card = dev_get_drvdata(dev); struct azx *chip; struct hda_intel *hda; + struct hdac_bus *bus; if (!card) return 0; chip = card->private_data; hda = container_of(chip, struct hda_intel, chip); + bus = azx_bus(chip); if (chip->disabled || hda->init_failed || !chip->running) return 0; if (!power_save_controller || !azx_has_pm_runtime(chip) || - azx_bus(chip)->codec_powered) + bus->codec_powered || !bus->chip_init) return -EBUSY; return 0; -- 1.9.3

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[alsa-devel] [PATCH v2 1/2] ASoC: max98088: Get rid of max98088_access table
by Axel Lin 28 Jul '15

28 Jul '15

The max98088_access table is used for look up readable/writable/volatile attributes of registers. The readable/writable/volatile registers are mostly in continuous ranges, so we can replace the max98088_access table entirely by using case range. Below is a summary of the readable/writeable/volatile registers: readable registers: 0x00 ~ 0xC9, 0xFF writeable registers: 0x03 ~ 0xC9 volatile registers: 0x00 ~ 0x03, 0xFF Note, 0x00 should be read-only according to the datasheet. This patch reworks the implement for .readable and .volatile and also add implementation for .writable callback. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- v2: no code change. Just update commit log, 0xff register is not writeable. sound/soc/codecs/max98088.c | 305 ++++---------------------------------------- 1 file changed, 25 insertions(+), 280 deletions(-) diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index 99c2daa..2c2df17 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -258,292 +258,36 @@ static const struct reg_default max98088_reg[] = { { 0xc9, 0x00 }, /* C9 DAI2 biquad */ }; -static struct { - int readable; - int writable; - int vol; -} max98088_access[M98088_REG_CNT] = { - { 0xFF, 0xFF, 1 }, /* 00 IRQ status */ - { 0xFF, 0x00, 1 }, /* 01 MIC status */ - { 0xFF, 0x00, 1 }, /* 02 jack status */ - { 0x1F, 0x1F, 1 }, /* 03 battery voltage */ - { 0xFF, 0xFF, 0 }, /* 04 */ - { 0xFF, 0xFF, 0 }, /* 05 */ - { 0xFF, 0xFF, 0 }, /* 06 */ - { 0xFF, 0xFF, 0 }, /* 07 */ - { 0xFF, 0xFF, 0 }, /* 08 */ - { 0xFF, 0xFF, 0 }, /* 09 */ - { 0xFF, 0xFF, 0 }, /* 0A */ - { 0xFF, 0xFF, 0 }, /* 0B */ - { 0xFF, 0xFF, 0 }, /* 0C */ - { 0xFF, 0xFF, 0 }, /* 0D */ - { 0xFF, 0xFF, 0 }, /* 0E */ - { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */ - - { 0xFF, 0xFF, 0 }, /* 10 master clock */ - { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */ - { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */ - { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */ - { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */ - { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */ - { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */ - { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */ - { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */ - { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */ - { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */ - { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */ - { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */ - { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */ - { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */ - { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */ - - { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */ - { 0xFF, 0xFF, 0 }, /* 21 data config */ - { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */ - { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */ - { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */ - { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */ - { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */ - { 0xFF, 0xFF, 0 }, /* 27 HP control */ - { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */ - { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */ - { 0xFF, 0xFF, 0 }, /* 2A REC control */ - { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */ - { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */ - { 0xFF, 0xFF, 0 }, /* 2D SPK control */ - { 0xFF, 0xFF, 0 }, /* 2E sidetone */ - { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */ - - { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */ - { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */ - { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */ - { 0xFF, 0xFF, 0 }, /* 33 left ADC level */ - { 0xFF, 0xFF, 0 }, /* 34 right ADC level */ - { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */ - { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */ - { 0xFF, 0xFF, 0 }, /* 37 INA level */ - { 0xFF, 0xFF, 0 }, /* 38 INB level */ - { 0xFF, 0xFF, 0 }, /* 39 left HP volume */ - { 0xFF, 0xFF, 0 }, /* 3A right HP volume */ - { 0xFF, 0xFF, 0 }, /* 3B left REC volume */ - { 0xFF, 0xFF, 0 }, /* 3C right REC volume */ - { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */ - { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */ - { 0xFF, 0xFF, 0 }, /* 3F MIC config */ - - { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */ - { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */ - { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */ - { 0xFF, 0xFF, 0 }, /* 43 ALC */ - { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */ - { 0xFF, 0xFF, 0 }, /* 45 power limiter config */ - { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */ - { 0xFF, 0xFF, 0 }, /* 47 audio input */ - { 0xFF, 0xFF, 0 }, /* 48 microphone */ - { 0xFF, 0xFF, 0 }, /* 49 level control */ - { 0xFF, 0xFF, 0 }, /* 4A bypass switches */ - { 0xFF, 0xFF, 0 }, /* 4B jack detect */ - { 0xFF, 0xFF, 0 }, /* 4C input enable */ - { 0xFF, 0xFF, 0 }, /* 4D output enable */ - { 0xFF, 0xFF, 0 }, /* 4E bias control */ - { 0xFF, 0xFF, 0 }, /* 4F DAC power */ - - { 0xFF, 0xFF, 0 }, /* 50 DAC power */ - { 0xFF, 0xFF, 0 }, /* 51 system */ - { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */ - - { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */ - - { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */ - - { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */ - - { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */ - - { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */ - - { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */ - - { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */ - { 0x00, 0x00, 0 }, /* CA */ - { 0x00, 0x00, 0 }, /* CB */ - { 0x00, 0x00, 0 }, /* CC */ - { 0x00, 0x00, 0 }, /* CD */ - { 0x00, 0x00, 0 }, /* CE */ - { 0x00, 0x00, 0 }, /* CF */ - - { 0x00, 0x00, 0 }, /* D0 */ - { 0x00, 0x00, 0 }, /* D1 */ - { 0x00, 0x00, 0 }, /* D2 */ - { 0x00, 0x00, 0 }, /* D3 */ - { 0x00, 0x00, 0 }, /* D4 */ - { 0x00, 0x00, 0 }, /* D5 */ - { 0x00, 0x00, 0 }, /* D6 */ - { 0x00, 0x00, 0 }, /* D7 */ - { 0x00, 0x00, 0 }, /* D8 */ - { 0x00, 0x00, 0 }, /* D9 */ - { 0x00, 0x00, 0 }, /* DA */ - { 0x00, 0x00, 0 }, /* DB */ - { 0x00, 0x00, 0 }, /* DC */ - { 0x00, 0x00, 0 }, /* DD */ - { 0x00, 0x00, 0 }, /* DE */ - { 0x00, 0x00, 0 }, /* DF */ - - { 0x00, 0x00, 0 }, /* E0 */ - { 0x00, 0x00, 0 }, /* E1 */ - { 0x00, 0x00, 0 }, /* E2 */ - { 0x00, 0x00, 0 }, /* E3 */ - { 0x00, 0x00, 0 }, /* E4 */ - { 0x00, 0x00, 0 }, /* E5 */ - { 0x00, 0x00, 0 }, /* E6 */ - { 0x00, 0x00, 0 }, /* E7 */ - { 0x00, 0x00, 0 }, /* E8 */ - { 0x00, 0x00, 0 }, /* E9 */ - { 0x00, 0x00, 0 }, /* EA */ - { 0x00, 0x00, 0 }, /* EB */ - { 0x00, 0x00, 0 }, /* EC */ - { 0x00, 0x00, 0 }, /* ED */ - { 0x00, 0x00, 0 }, /* EE */ - { 0x00, 0x00, 0 }, /* EF */ - - { 0x00, 0x00, 0 }, /* F0 */ - { 0x00, 0x00, 0 }, /* F1 */ - { 0x00, 0x00, 0 }, /* F2 */ - { 0x00, 0x00, 0 }, /* F3 */ - { 0x00, 0x00, 0 }, /* F4 */ - { 0x00, 0x00, 0 }, /* F5 */ - { 0x00, 0x00, 0 }, /* F6 */ - { 0x00, 0x00, 0 }, /* F7 */ - { 0x00, 0x00, 0 }, /* F8 */ - { 0x00, 0x00, 0 }, /* F9 */ - { 0x00, 0x00, 0 }, /* FA */ - { 0x00, 0x00, 0 }, /* FB */ - { 0x00, 0x00, 0 }, /* FC */ - { 0x00, 0x00, 0 }, /* FD */ - { 0x00, 0x00, 0 }, /* FE */ - { 0xFF, 0x00, 1 }, /* FF */ -}; - static bool max98088_readable_register(struct device *dev, unsigned int reg) { - return max98088_access[reg].readable; + switch (reg) { + case M98088_REG_00_IRQ_STATUS ... 0xC9: + case M98088_REG_FF_REV_ID: + return true; + default: + return false; + } +} + +static bool max98088_writeable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9: + return true; + default: + return false; + } } static bool max98088_volatile_register(struct device *dev, unsigned int reg) { - return max98088_access[reg].vol; + switch (reg) { + case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE: + case M98088_REG_FF_REV_ID: + return true; + default: + return false; + } } static const struct regmap_config max98088_regmap = { @@ -551,6 +295,7 @@ static const struct regmap_config max98088_regmap = { .val_bits = 8, .readable_reg = max98088_readable_register, + .writeable_reg = max98088_writeable_register, .volatile_reg = max98088_volatile_register, .max_register = 0xff, -- 2.1.0

1 1

[alsa-devel] [PATCH v3] ASoC: Add support for NAU8825 codec to ASoC
by Chih-Chiang Chang 28 Jul '15

28 Jul '15

The NAU88L25 is an ultra-low power high performance audio codec designed for smartphone, tablet PC, and other portable devices by Nuvoton, now add linux driver support for it. Signed-off-by: Chih-Chiang Chang <ccchang12(a)nuvoton.com> --- v3->v2: - fix the wrong definition of reg_default - fix the flow of set_sys_clk() and nau8825_set_bias_level() - remove unnecessary code in nau8825_volatile_register() and nau8825_i2c_probe() - add trigger function for ADC/DAC control - add some register definitions - fix some coding style issues v2->v1: - fixes according to Lars-Peter Clausen's review comments - removes unused platform data file - corrects the naming of DAPM input widget - fixes some wrong coding of SOC widgets and other codes - adds definition and remark for config FLL clock - moves the code of reset hardware registers from codec_probe() to i2c_probe() - removes unused codes sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/nau8825.c | 724 +++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/nau8825.h | 399 +++++++++++++++++++++++++ 4 files changed, 1130 insertions(+) create mode 100644 sound/soc/codecs/nau8825.c create mode 100644 sound/soc/codecs/nau8825.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index efaafce..1edb781 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -76,6 +76,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_MAX9877 if I2C select SND_SOC_MC13783 if MFD_MC13XXX select SND_SOC_ML26124 if I2C + select SND_SOC_NAU8825 if I2C select SND_SOC_HDMI_CODEC select SND_SOC_PCM1681 if I2C select SND_SOC_PCM1792A if SPI_MASTER @@ -470,6 +471,10 @@ config SND_SOC_MAX98925 config SND_SOC_MAX9850 tristate +config SND_SOC_NAU8825 + tristate "Nuvoton NAU8825 CODEC" + depends on I2C + config SND_SOC_PCM1681 tristate "Texas Instruments PCM1681 CODEC" depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index cf160d9..db0a4ec 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -69,6 +69,7 @@ snd-soc-max98925-objs := max98925.o snd-soc-max9850-objs := max9850.o snd-soc-mc13783-objs := mc13783.o snd-soc-ml26124-objs := ml26124.o +snd-soc-nau8825-objs := nau8825.o snd-soc-hdmi-codec-objs := hdmi.o snd-soc-pcm1681-objs := pcm1681.o snd-soc-pcm1792a-codec-objs := pcm1792a.o @@ -256,6 +257,7 @@ obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o +obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o obj-$(CONFIG_SND_SOC_PCM1792A) += snd-soc-pcm1792a-codec.o diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c new file mode 100644 index 0000000..d3b306a --- /dev/null +++ b/sound/soc/codecs/nau8825.c @@ -0,0 +1,724 @@ +/* + * nau8825.c + * + * Copyright 2015 Nuvoton Technology Corp. + * Author: Meng-Huang Kuo <mhkuo(a)nuvoton.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/device.h> +#include <linux/clk.h> +#include <linux/regmap.h> +#include <linux/acpi.h> +#include <asm/div64.h> +#include <sound/jack.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <linux/delay.h> +#include "nau8825.h" + +static const DECLARE_TLV_DB_SCALE(out_hp_vol_tlv, -5400, 100, 0); +static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -10350, 50, 0); + +static const struct snd_kcontrol_new nau8825_snd_controls[] = { + SOC_SINGLE_TLV("MIC Volume", NAU8825_ADC_DGAIN_CTRL, + NAU8825_ADC_DGAIN_SFT, + NAU8825_ADC_VOL_RSCL_RANGE, 0, adc_vol_tlv), + SOC_DOUBLE_TLV("HP Volume", NAU8825_HSVOL_CTRL, + NAU8825_L_HSVOL_SFT, NAU8825_R_HSVOL_SFT, + NAU8825_VOL_RSCL_RANGE, 1, out_hp_vol_tlv), +}; + +static const struct snd_kcontrol_new nau8825_hpo_mix[] = { + SOC_DAPM_SINGLE("HP L Switch", NAU8825_HSVOL_CTRL, + NAU8825_L_MUTE_SFT, 1, 1), + SOC_DAPM_SINGLE("HP R Switch", NAU8825_HSVOL_CTRL, + NAU8825_R_MUTE_SFT, 1, 1), +}; + +static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = { + /* Input */ + SND_SOC_DAPM_INPUT("MIC"), + SND_SOC_DAPM_SUPPLY("MIC BIAS", NAU8825_BOOST, NAU8825_G_BIAS_SFT, 0, + NULL, 0), + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + /* DACs */ + SND_SOC_DAPM_DAC("DAC L1", NULL, NAU8825_DAC_CTRL, + NAU8825_DAC_L_SFT, 0), + SND_SOC_DAPM_DAC("DAC R1", NULL, NAU8825_DAC_CTRL, + NAU8825_DAC_R_SFT, 0), + /* SPO/HPO/LOUT/Mono Mixer */ + SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, nau8825_hpo_mix, + ARRAY_SIZE(nau8825_hpo_mix)), + SND_SOC_DAPM_SUPPLY("HP amp", NAU8825_CLASSG_CTRL, + NAU8825_CLASSG_EN_SHIFT, 0, NULL, 0), + /* Output */ + SND_SOC_DAPM_OUTPUT("HPOL"), + SND_SOC_DAPM_OUTPUT("HPOR"), +}; + +static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { + {"AIF1TX", NULL, "MIC"}, + {"DAC L1", NULL, "AIF1RX"}, + {"DAC R1", NULL, "AIF1RX"}, + {"HPO MIX", "HP L Switch", "DAC L1"}, + {"HPO MIX", "HP R Switch", "DAC R1"}, + {"HPOL", NULL, "HPO MIX"}, + {"HPOR", NULL, "HPO MIX"}, + {"HPOL", NULL, "HP amp"}, + {"HPOR", NULL, "HP amp"}, +}; + +static int nau8825_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + unsigned int val_len = 0; + + switch (params_width(params)) { + case 16: + break; + case 20: + val_len |= NAU8825_I2S_DL_20; + break; + case 24: + val_len |= NAU8825_I2S_DL_24; + break; + case 32: + val_len |= NAU8825_I2S_DL_32; + break; + default: + return -EINVAL; + } + regmap_update_bits(nau8825->regmap, NAU8825_I2S_PCM_CTRL_1, + NAU8825_I2S_DL_MASK, val_len); + return 0; +} + +static int nau8825_dac_mute(struct snd_soc_dai *codec_dai, int mute) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + + if (mute) + regmap_update_bits(nau8825->regmap, NAU8825_DAC_MUTE_CTRL, + NAU8825_SOFT_MUTE_MASK, NAU8825_SOFT_MUTE_EN); + else + regmap_update_bits(nau8825->regmap, NAU8825_DAC_MUTE_CTRL, + NAU8825_SOFT_MUTE_MASK, NAU8825_SOFT_MUTE_DIS); + return 0; +} + +static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + unsigned int reg_val = 0; + + dev_dbg(codec->dev, " %s ###nau8825_set_dai_fmt %x\n", __func__, fmt); + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + reg_val |= NAU8825_I2S_BP_INV; + break; + default: + dev_alert(codec->dev, "Invalid DAI interface format\n"); + return -EINVAL; + } + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + reg_val |= NAU8825_I2S_DF_I2S; + break; + case SND_SOC_DAIFMT_LEFT_J: + reg_val |= NAU8825_I2S_DF_LEFT; + break; + case SND_SOC_DAIFMT_RIGHT_J: + reg_val |= NAU8825_I2S_DF_RIGHT; + break; + case SND_SOC_DAIFMT_DSP_A: + reg_val |= NAU8825_I2S_DF_PCM_A; + break; + case SND_SOC_DAIFMT_DSP_B: + reg_val |= NAU8825_I2S_DF_PCM_B; + reg_val |= NAU8825_I2S_PCMB_EN; + break; + default: + dev_alert(codec->dev, "Invalid DAI I2S/PCM format\n"); + return -EINVAL; + } + regmap_update_bits(nau8825->regmap, NAU8825_I2S_PCM_CTRL_1, + NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK + | NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK, + reg_val); + return 0; +} + +static void config_fll_clk_12m(struct snd_soc_codec *codec) +{ + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, + NAU8825_CLK_MCLK_SRC_MASK, 0x0003); + regmap_update_bits(nau8825->regmap, NAU8825_FLL_1, + NAU8825_FLL_RATIO_MASK, 0x0001); + /* FLL 16-bit fractional input */ + regmap_write(nau8825->regmap, NAU8825_FLL_2, 0xc49b); + /* FLL 10-bit integer input */ + regmap_update_bits(nau8825->regmap, NAU8825_FLL_3, + NAU8825_FLL_INTEGER_MASK, 0x0020); + /* FLL pre-scaler */ + regmap_update_bits(nau8825->regmap, NAU8825_FLL_4, + NAU8825_FLL_REF_DIV_MASK, 0x0800); + /* select divied VCO input */ + regmap_update_bits(nau8825->regmap, NAU8825_FLL_5, + NAU8825_FLL_FILTER_SW_MASK, 0x0000); + /* FLL sigma delta modulator enable */ + regmap_update_bits(nau8825->regmap, NAU8825_FLL_6, + NAU8825_SDM_EN_MASK, 0x4000); +} + +static void set_sys_clk(struct snd_soc_codec *codec, int sys_clk) +{ + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + + pr_debug("%s :: sys_clk=%x\n", __func__, sys_clk); + switch (sys_clk) { + case NAU8825_INTERNALCLOCK: + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_DIS); + regmap_update_bits(nau8825->regmap, NAU8825_FLL_6, + NAU8825_DCO_EN_MASK, NAU8825_DCO_EN); + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_EN); + break; + case NAU8825_MCLK: + default: + regmap_update_bits(nau8825->regmap, NAU8825_FLL_6, + NAU8825_DCO_EN_MASK, NAU8825_DCO_DIS); + regmap_update_bits(nau8825->regmap, NAU8825_I2S_PCM_CTRL_2, + NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE); + /* FLL clock source from MCLK */ + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_DIS); + mdelay(2); + regmap_update_bits(nau8825->regmap, NAU8825_CLK_DIVIDER, + NAU8825_SYSCLK_EN_MASK, NAU8825_SYSCLK_EN); + break; + } +} + +static int nau8825_dai_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + + switch (clk_id) { + case NAU8825_MCLK: + config_fll_clk_12m(codec); + set_sys_clk(codec, clk_id); + break; + case NAU8825_INTERNALCLOCK: + set_sys_clk(codec, clk_id); + break; + default: + dev_err(codec->dev, "Wrong clock src\n"); + return -EINVAL; + } + return 0; +} + +static int nau8825_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + + switch (level) { + case SND_SOC_BIAS_ON: + /* All power is driven by DAPM system*/ + dev_dbg(codec->dev, "###nau8825_set_bias_level BIAS_ON\n"); + regmap_update_bits(nau8825->regmap, NAU8825_BIAS_ADJ, + NAU8825_VMIDSEL_MASK, NAU8825_VMIDSEL_125KOHM); + regmap_update_bits(nau8825->regmap, NAU8825_BIAS_ADJ, + NAU8825_VMID_MASK, NAU8825_VMID_EN); + regmap_update_bits(nau8825->regmap, NAU8825_BOOST, + NAU8825_G_BIAS_MASK, NAU8825_G_BIAS_EN); + break; + case SND_SOC_BIAS_OFF: + dev_dbg(codec->dev, "###nau8825_set_bias_level OFF\n"); + set_sys_clk(codec, NAU8825_INTERNALCLOCK); + regmap_update_bits(nau8825->regmap, NAU8825_BIAS_ADJ, + NAU8825_VMID_MASK, NAU8825_VMID_DIS); + regmap_update_bits(nau8825->regmap, NAU8825_BOOST, + NAU8825_G_BIAS_MASK, NAU8825_G_BIAS_DIS); + break; + default: + break; + } + codec->dapm.bias_level = level; + dev_dbg(codec->dev, "## nau8825_set_bias_level %d\n", level); + return 0; +} + + +static const struct reg_default nau8825_reg[] = { + {0x000, 0x0000}, + {0x001, 0x00ff}, + {0x003, 0x0050}, + {0x004, 0x0000}, + {0x005, 0x3126}, + {0x006, 0x0008}, + {0x007, 0x0010}, + {0x008, 0x0000}, + {0x009, 0x6000}, + {0x00a, 0xf13c}, + {0x00c, 0x000c}, + {0x00d, 0x0000}, + {0x00f, 0x0800}, + {0x010, 0x0000}, + {0x011, 0x0000}, + {0x012, 0x0010}, + {0x013, 0x0015}, + {0x014, 0x0110}, + {0x015, 0x0000}, + {0x016, 0x0000}, + {0x017, 0x0000}, + {0x018, 0x0000}, + {0x019, 0x0000}, + {0x01a, 0x0000}, + {0x01b, 0x0000}, + {0x01c, 0x000b}, + {0x01d, 0x8010}, + {0x01e, 0x0000}, + {0x01f, 0x0000}, + {0x020, 0x0000}, + {0x021, 0x0000}, + {0x022, 0x0000}, + {0x023, 0x0000}, + {0x024, 0x0000}, + {0x025, 0x0000}, + {0x026, 0x0000}, + {0x027, 0x0000}, + {0x028, 0x0000}, + {0x029, 0x0000}, + {0x02a, 0x0000}, + {0x02b, 0x0010}, + {0x02c, 0x0001}, + {0x02d, 0x0000}, + {0x02f, 0x0000}, + {0x030, 0x01cf}, + {0x031, 0x0000}, + {0x032, 0x0000}, + {0x033, 0x00cf}, + {0x034, 0x0000}, + {0x038, 0x1486}, + {0x039, 0x0f12}, + {0x03a, 0x25ff}, + {0x03b, 0x3457}, + {0x045, 0x1486}, + {0x046, 0x0f12}, + {0x047, 0x25f9}, + {0x048, 0x3457}, + {0x04c, 0x0000}, + {0x04d, 0x0000}, + {0x050, 0x0000}, + {0x051, 0x0000}, + {0x055, 0x0000}, + {0x058, 0x0000}, + {0x059, 0x0000}, + {0x066, 0x0000}, + {0x068, 0x0000}, + {0x069, 0x0000}, + {0x06a, 0x0020}, + {0x071, 0x0011}, + {0x072, 0x0020}, + {0x073, 0x0008}, + {0x074, 0x0006}, + {0x076, 0x0000}, + {0x077, 0x0000}, + {0x07f, 0x0000}, + {0x080, 0x0300}, + {0x081, 0x0000}, + {0x082, 0x0000}, +}; + +static int nau8825_codec_remove(struct snd_soc_codec *codec) +{ + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + + regmap_write(nau8825->regmap, NAU8825_RESET, 0x00); + regmap_write(nau8825->regmap, NAU8825_RESET, 0x00); + return 0; +} + +static int nau8825_codec_probe(struct snd_soc_codec *codec) +{ + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + + /* bias current settings */ + regmap_write(nau8825->regmap, 0x0072, 0x0260); + /* enable bias */ + nau8825_set_bias_level(codec, SND_SOC_BIAS_ON); + mdelay(10); + /* DAC digital default gain 0 dB */ + regmap_write(nau8825->regmap, 0x0033, 0x00cf); + regmap_write(nau8825->regmap, 0x0034, 0x02cf); + /* DAC driver default gain -29 dB */ + regmap_write(nau8825->regmap, 0x0032, 0x075d); + /* ADC digital default gain 8 dB */ + regmap_write(nau8825->regmap, 0x0030, 0x00d2); + /* ehance I2C SDA driver strength */ + regmap_write(nau8825->regmap, 0x0080, 0x0800); + /* enable ADC/DAC clocks */ + regmap_write(nau8825->regmap, 0x0001, 0x07fd); + /* headphone output */ + regmap_write(nau8825->regmap, 0x00C, 0x000c); + return 0; +} + +static const struct snd_soc_codec_driver soc_codec_driver_nau8825 = { + .probe = nau8825_codec_probe, + .remove = nau8825_codec_remove, + .suspend_bias_off = true, + .set_bias_level = nau8825_set_bias_level, + .controls = nau8825_snd_controls, + .num_controls = ARRAY_SIZE(nau8825_snd_controls), + .dapm_widgets = nau8825_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets), + .dapm_routes = nau8825_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes), +}; + +static bool nau8825_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8825_RESET: + case NAU8825_ENA_CTRL: + case NAU8825_CLK_EN: + case NAU8825_CLK_DIVIDER: + case NAU8825_FLL_1: + case NAU8825_FLL_2: + case NAU8825_FLL_3: + case NAU8825_FLL_4: + case NAU8825_FLL_5: + case NAU8825_FLL_6: + case NAU8825_HEADSET_CTRL: + case NAU8825_JACK_DET_CTRL: + case NAU8825_IRQ_MASK: + case NAU8825_IRQ_STATUS: + case NAU8825_IRQ_CLEAR: + case NAU8825_IRQ_CTRL: + case NAU8825_SAR_ADC: + case NAU8825_VDET_COEFFICIENT: + case NAU8825_VDET_THRESHOLD_1: + case NAU8825_VDET_THRESHOLD_2: + case NAU8825_GPIO12_CTRL: + case NAU8825_GPIO34_CTRL: + case NAU8825_I2S_PCM_CTRL_1: + case NAU8825_I2S_PCM_CTRL_2: + case NAU8825_ADC_RATE: + case NAU8825_DAC_CTRL1: + case NAU8825_DAC_CTRL2: + case NAU8825_IMM_MODE_CTRL: + case NAU8825_IMM_RMS_VALUE: + case NAU8825_ADC_DGAIN_CTRL: + case NAU8825_DAC_MUTE_CTRL: + case NAU8825_HSVOL_CTRL: + case NAU8825_DACL_CTRL: + case NAU8825_DACR_CTRL: + case NAU8825_SAR_ADC_OUTPUT: + case NAU8825_ANALOG_CTRL_2: + case NAU8825_ANALOG_ADC_1: + case NAU8825_ANALOG_ADC_2: + case NAU8825_DAC_CTRL: + case NAU8825_MIC_BIAS: + case NAU8825_BOOST: + case NAU8825_CLASSG_CTRL: + case NAU8825_I2C_DEVICE_ID: + case NAU8825_BIAS_ADJ: + case NAU8825_POWER_UP_CTRL: + case NAU8825_CHARGE_BUMP_CTRL: + case NAU8825_CHARGE_BUMP_RD: + case NAU8825_GENERAL_STATUS: + return true; + default: + return false; + } +} + +static bool nau8825_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8825_RESET: + case NAU8825_CLK_DIVIDER: + case NAU8825_FLL_1: + case NAU8825_FLL_2: + case NAU8825_FLL_3: + case NAU8825_FLL_4: + case NAU8825_FLL_5: + case NAU8825_FLL_6: + case NAU8825_ANALOG_CTRL_2: + case NAU8825_ANALOG_ADC_1: + case NAU8825_ANALOG_ADC_2: + case NAU8825_DAC_CTRL: + case NAU8825_MIC_BIAS: + case NAU8825_BOOST: + case NAU8825_CLASSG_CTRL: + case NAU8825_I2C_DEVICE_ID: + case NAU8825_BIAS_ADJ: + case NAU8825_POWER_UP_CTRL: + case NAU8825_CHARGE_BUMP_CTRL: + case NAU8825_GENERAL_STATUS: + return true; + default: + return false; + } +} + +static const struct regmap_config nau8825_regmap = { + .reg_bits = 16, + .val_bits = 16, + .use_single_rw = true, + .max_register = NAU8825_MAX_REGISTER, + .volatile_reg = nau8825_volatile_register, + .readable_reg = nau8825_readable_register, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = nau8825_reg, + .num_reg_defaults = ARRAY_SIZE(nau8825_reg), +}; + +static int ena_adc(struct nau8825_priv *nau8825) +{ + /* adc & clock settings */ + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_ADC_CLK_MASK, NAU8825_ADC_CLK_EN); + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_ADC_MASK, NAU8825_ADC_EN); + /* adc PGA settings */ + regmap_update_bits(nau8825->regmap, NAU8825_POWER_UP_CTRL, + NAU8825_FEPGA_GAIN_MASK, 0x1b00); + regmap_update_bits(nau8825->regmap, NAU8825_POWER_UP_CTRL, + NAU8825_FEPGA_MASK, NAU8825_FEPGA_EN); + /* mic bias output level (1.1V) */ + regmap_update_bits(nau8825->regmap, NAU8825_MIC_BIAS, + NAU8825_MIC_BIAS_LVL_MSK, 0x04); + /* enable mic bias */ + regmap_update_bits(nau8825->regmap, NAU8825_MIC_BIAS, + NAU8825_MIC_POWERUP_MSK, NAU8825_MIC_POWERUP_EN); + mdelay(10); + return 0; +} + +static int dis_adc(struct nau8825_priv *nau8825) +{ + /* disable PGA */ + regmap_update_bits(nau8825->regmap, NAU8825_POWER_UP_CTRL, + NAU8825_FEPGA_MASK, NAU8825_FEPGA_DIS); + /* adc & clock settings */ + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_ADC_MASK, NAU8825_ADC_DIS); + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_ADC_CLK_MASK, NAU8825_ADC_CLK_DIS); + return 0; +} + +static int ena_dac(struct nau8825_priv *nau8825) +{ + /* charge bump settings */ + regmap_update_bits(nau8825->regmap, NAU8825_CHARGE_BUMP_CTRL, + 0x07ff, 0x720); + /* enable DAC clock */ + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_DAC_CLK_MASK, NAU8825_DAC_CLK_EN); + /* enable DAC channel */ + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_DAC_MASK, NAU8825_DAC_EN); + /* classG parameter settings */ + regmap_update_bits(nau8825->regmap, NAU8825_CLASSG_CTRL, + ~NAU8825_CLASSG_EN_MASK, 0x2007); + /* enable DAC */ + regmap_write(nau8825->regmap, NAU8825_DAC_CTRL, 0x332c); + /* output driver settings */ + regmap_write(nau8825->regmap, NAU8825_POWER_UP_CTRL, 0x073c); + /* power up main driver */ + regmap_update_bits(nau8825->regmap, NAU8825_POWER_UP_CTRL, + NAU8825_PUP_MAIN_MASK, NAU8825_PUP_MAIN_ENA); + mdelay(200); + /* enable charge bump */ + regmap_update_bits(nau8825->regmap, NAU8825_CHARGE_BUMP_CTRL, + NAU8825_PD_DAC_MASK, NAU8825_PD_DAC_DIS); + return 0; +} + +static int dis_dac(struct nau8825_priv *nau8825) +{ + /* disable charge bump */ + regmap_update_bits(nau8825->regmap, NAU8825_CHARGE_BUMP_CTRL, + NAU8825_PD_DAC_MASK, NAU8825_PD_DAC_ENA); + /* disable classG */ + regmap_update_bits(nau8825->regmap, NAU8825_CLASSG_CTRL, + NAU8825_CLASSG_PATH_MASK, NAU8825_CLASSG_PATH_DIS); + /* disable DAC */ + regmap_update_bits(nau8825->regmap, NAU8825_DAC_CTRL, + NAU8825_DAC_LR_MASK, NAU8825_DAC_LR_DIS); + regmap_update_bits(nau8825->regmap, NAU8825_DAC_CTRL, + NAU8825_DAC_CLK_LR_MASK, NAU8825_DAC_CLK_LR_DIS); + /* disable output driver */ + regmap_update_bits(nau8825->regmap, NAU8825_POWER_UP_CTRL, + 0x3f, 0x00); + /* disable DAC channel */ + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_L_DAC_MASK, NAU8825_L_DAC_DIS); + /* disable DAC clock */ + regmap_update_bits(nau8825->regmap, NAU8825_ENA_CTRL, + NAU8825_DAC_CLK_MASK, NAU8825_DAC_CLK_DIS); + return 0; +} + +static int nau8825_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct nau8825_priv *nau8825 = snd_soc_codec_get_drvdata(codec); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + config_fll_clk_12m(codec); + set_sys_clk(codec, NAU8825_MCLK); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ena_dac(nau8825); + else + ena_adc(nau8825); + break; + case SNDRV_PCM_TRIGGER_RESUME: + break; + case SNDRV_PCM_TRIGGER_STOP: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + dis_dac(nau8825); + else + dis_adc(nau8825); + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + break; + default: + break; + } + return 0; +} + +#define NAU8825_RATES SNDRV_PCM_RATE_8000_192000 +#define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ + | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dai_ops nau8825_dai_ops = { + .trigger = nau8825_trigger, + .hw_params = nau8825_hw_params, + .set_sysclk = nau8825_dai_set_sysclk, + .set_fmt = nau8825_set_dai_fmt, + .digital_mute = nau8825_dac_mute, +}; + +static struct snd_soc_dai_driver nau8825_dai_driver[] = { + { + .name = "nau8825-aif1", + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = NAU8825_RATES, + .formats = NAU8825_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = NAU8825_RATES, + .formats = NAU8825_FORMATS, + }, + .ops = &nau8825_dai_ops, + } +}; + + +static int nau8825_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *i2c_id) +{ + struct nau8825_priv *nau8825; + int ret; + + nau8825 = devm_kzalloc(&i2c->dev, sizeof(*nau8825), + GFP_KERNEL); + if (nau8825 == NULL) + return -ENOMEM; + nau8825->i2c = i2c; + i2c_set_clientdata(i2c, nau8825); + nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap); + if (IS_ERR(nau8825->regmap)) { + ret = PTR_ERR(nau8825->regmap); + dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); + return ret; + } + /* software reset */ + regmap_write(nau8825->regmap, NAU8825_RESET, 0x00); + regmap_write(nau8825->regmap, NAU8825_RESET, 0x00); + + /* register sound card */ + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_driver_nau8825, + nau8825_dai_driver, + ARRAY_SIZE(nau8825_dai_driver)); + return ret; +} + +static int nau8825_i2c_remove(struct i2c_client *i2c) +{ + snd_soc_unregister_codec(&i2c->dev); + return 0; +} + +static const struct i2c_device_id nau8825_i2c_id[] = { + {"nau8825", 0}, + { } +}; +MODULE_DEVICE_TABLE(i2c, nau8825_i2c_id); + +static const struct acpi_device_id nau8825_acpi_match[] = { + { "10508825", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match); + +static struct i2c_driver nau8825_i2c_driver = { + .driver = { + .name = "nau8825", + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(nau8825_acpi_match), + }, + .probe = nau8825_i2c_probe, + .remove = (nau8825_i2c_remove), + .id_table = nau8825_i2c_id, +}; +module_i2c_driver(nau8825_i2c_driver); + +MODULE_DESCRIPTION("ASoC NAU8825 codec driver"); +MODULE_AUTHOR("Nuvoton"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h new file mode 100644 index 0000000..3050e7c --- /dev/null +++ b/sound/soc/codecs/nau8825.h @@ -0,0 +1,399 @@ +/* + * nau8825.h + * + * Copyright 2015 Nuvoton Technology Corp. + * Author: Meng-Huang Kuo <mhkuo(a)nuvoton.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _NAU8825_H +#define _NAU8825_H + +#define NAU8825_RESET 0x00 +#define NAU8825_ENA_CTRL 0x01 +#define NAU8825_CLK_EN 0x02 +#define NAU8825_CLK_DIVIDER 0x03 +#define NAU8825_FLL_1 0x04 +#define NAU8825_FLL_2 0x05 +#define NAU8825_FLL_3 0x06 +#define NAU8825_FLL_4 0x07 +#define NAU8825_FLL_5 0x08 +#define NAU8825_FLL_6 0x09 +#define NAU8825_HEADSET_CTRL 0x0C +#define NAU8825_JACK_DET_CTRL 0x0D +#define NAU8825_IRQ_MASK 0x0F +#define NAU8825_IRQ_STATUS 0x10 +#define NAU8825_IRQ_CLEAR 0x11 +#define NAU8825_BTN_STATUS 0x11 +#define NAU8825_IRQ_CTRL 0x12 +#define NAU8825_SAR_ADC 0x13 +#define NAU8825_VDET_COEFFICIENT 0x14 +#define NAU8825_VDET_THRESHOLD_1 0x15 +#define NAU8825_VDET_THRESHOLD_2 0x16 +#define NAU8825_GPIO34_CTRL 0x19 +#define NAU8825_GPIO12_CTRL 0x1A +#define NAU8825_TDM_CTRL 0x1B +#define NAU8825_I2S_PCM_CTRL_1 0x1C +#define NAU8825_I2S_PCM_CTRL_2 0x1D +#define NAU8825_BIQ_CTRL 0x20 +#define NAU8825_BIQ_COF1 0x21 +#define NAU8825_BIQ_COF2 0x22 +#define NAU8825_BIQ_COF3 0x23 +#define NAU8825_BIQ_COF4 0x24 +#define NAU8825_BIQ_COF5 0x25 +#define NAU8825_BIQ_COF6 0x26 +#define NAU8825_BIQ_COF7 0x27 +#define NAU8825_BIQ_COF8 0x28 +#define NAU8825_BIQ_COF9 0x29 +#define NAU8825_BIQ_COF10 0x2A +#define NAU8825_ADC_RATE 0x2B +#define NAU8825_DAC_CTRL1 0x2C +#define NAU8825_DAC_CTRL2 0x2D +#define NAU8825_DAC_DGAIN_CTRL 0x2F +#define NAU8825_ADC_DGAIN_CTRL 0x30 +#define NAU8825_DAC_MUTE_CTRL 0x31 +#define NAU8825_HSVOL_CTRL 0x32 +#define NAU8825_DACL_CTRL 0x33 +#define NAU8825_DACR_CTRL 0x34 +#define NAU8825_ADC_DRC_KNEE_IP12 0x38 +#define NAU8825_ADC_DRC_KNEE_IP34 0x39 +#define NAU8825_ADC_DRC_SLOPES 0x3A +#define NAU8825_ADC_DRC_ATKDCY 0x3B +#define NAU8825_DAC_DRC_KNEE_IP12 0x45 +#define NAU8825_DAC_DRC_KNEE_IP34 0x46 +#define NAU8825_DAC_DRC_SLOPES 0x47 +#define NAU8825_DAC_DRC_ATKDCY 0x48 +#define NAU8825_IMM_MODE_CTRL 0x4C +#define NAU8825_IMM_RMS_VALUE 0x4D +#define NAU8825_CLASSG_CTRL 0x50 +#define NAU8825_I2C_DEVICE_ID 0x58 +#define NAU8825_SAR_ADC_OUTPUT 0x59 +#define NAU8825_BIAS_ADJ 0x66 +#define NAU8825_ANALOG_CTRL_2 0x6A +#define NAU8825_ANALOG_ADC_1 0x71 +#define NAU8825_ANALOG_ADC_2 0x72 +#define NAU8825_DAC_CTRL 0x73 +#define NAU8825_MIC_BIAS 0x74 +#define NAU8825_BOOST 0x76 +#define NAU8825_POWER_UP_CTRL 0x7F +#define NAU8825_CHARGE_BUMP_CTRL 0x80 +#define NAU8825_CHARGE_BUMP_RD 0x81 +#define NAU8825_GENERAL_STATUS 0x82 +#define NAU8825_MAX_REGISTER 0xFF + +/* reg. NAU8825_ENA_CTRL (0x01) */ +#define NAU8825_R_DAC_MASK (0x1 << 10) +#define NAU8825_R_DAC_EN (0x1 << 10) +#define NAU8825_R_DAC_DIS (0x0 << 10) +#define NAU8825_L_DAC_MASK (0x1 << 9) +#define NAU8825_L_DAC_EN (0x1 << 9) +#define NAU8825_L_DAC_DIS (0x0 << 9) +#define NAU8825_DAC_MASK (0x3 << 9) +#define NAU8825_DAC_EN (0x3 << 9) +#define NAU8825_DAC_DIS (0x0 << 9) + +#define NAU8825_R_DAC_MASK (0x1 << 10) +#define NAU8825_R_DAC_EN (0x1 << 10) +#define NAU8825_R_DAC_DIS (0x0 << 10) +#define NAU8825_L_DAC_MASK (0x1 << 9) +#define NAU8825_L_DAC_EN (0x1 << 9) +#define NAU8825_L_DAC_DIS (0x0 << 9) +#define NAU8825_ADC_MASK (0x1 << 8) +#define NAU8825_ADC_EN (0x1 << 8) +#define NAU8825_ADC_DIS (0x0 << 8) +#define NAU8825_ADC_CLK_MASK (0x1 << 7) +#define NAU8825_ADC_CLK_EN (0x1 << 7) +#define NAU8825_ADC_CLK_DIS (0x0 << 7) +#define NAU8825_DAC_CLK_MASK (0x1 << 6) +#define NAU8825_DAC_CLK_EN (0x1 << 6) +#define NAU8825_DAC_CLK_DIS (0x0 << 6) +#define NAU8825_IMM_CLK_MASK (0x1 << 5) +#define NAU8825_IMM_CLK_EN (0x1 << 5) +#define NAU8825_IMM_CLK_DIS (0x0 << 5) +#define NAU8825_I2S_CLK_MASK (0x1 << 4) +#define NAU8825_I2S_CLK_EN (0x1 << 4) +#define NAU8825_I2S_CLK_DIS (0x0 << 4) +#define NAU8825_BIST_CLK_MASK (0x1 << 3) +#define NAU8825_BIST_CLK_EN (0x1 << 3) +#define NAU8825_BIST_CLK_DIS (0x0 << 3) +#define NAU8825_OTP_CLK_MASK (0x1 << 2) +#define NAU8825_OTP_CLK_EN (0x1 << 2) +#define NAU8825_OTP_CLK_DIS (0x0 << 2) +#define NAU8825_SAR_CLK_MASK (0x1 << 1) +#define NAU8825_SAR_CLK_EN (0x1 << 1) +#define NAU8825_SAR_CLK_DIS (0x0 << 1) +#define NAU8825_DRC_CLK_MASK (0x1 << 0) +#define NAU8825_DRC_CLK_EN (0x1 << 0) +#define NAU8825_DRC_CLK_DIS (0x0 << 0) + +/* reg. NAU8825_CLK_DIVIDER (0x03) */ +#define NAU8825_SYSCLK_EN_MASK (0x1 << 15) +#define NAU8825_SYSCLK_EN (0x1 << 15) +#define NAU8825_SYSCLK_DIS (0x0 << 15) +#define NAU8825_CLK_MCLK_SRC_MASK (0xF << 0) + +/* reg. NAU8825_FLL_1 (0x04) */ +#define NAU8825_FLL_RATIO_MASK (0x7F << 0) + +/* reg. NAU8825_FLL_3 (0x06) */ +#define NAU8825_FLL_INTEGER_MASK (0x3FF << 0) + +/* reg. NAU8825_FLL_4 (0x07) */ +#define NAU8825_FLL_REF_DIV_MASK (0x3 << 10) + +/* reg. NAU8825_FLL_5 (0x08) */ +#define NAU8825_FLL_FILTER_SW_MASK (0x1 << 14) + +/* reg. NAU8825_FLL_6 (0x09) */ +#define NAU8825_DCO_EN_MASK (0x1 << 15) +#define NAU8825_DCO_EN (0x1 << 15) +#define NAU8825_DCO_DIS (0x0 << 15) +#define NAU8825_SDM_EN_MASK (0x1 << 14) + +/* reg. NAU8825_HEADSET_CTRL (0x0c) */ +#define NAU8825_RESET_HSD_MASK (0x1 << 15) +#define NAU8825_RESET_HSD_EN (0x1 << 15) +#define NAU8825_RESET_HSD_DIS (0x0 << 15) +#define NAU8825_AUTO_DETECT_MASK (0x1 << 6) +#define NAU8825_AUTO_DETECT_EN (0x1 << 6) +#define NAU8825_AUTO_DETECT_DIS (0x0 << 6) +#define NAU8825_MANUAL_START_MASK (0x1 << 4) +#define NAU8825_MANUAL_START_EN (0x1 << 4) +#define NAU8825_MANUAL_START_DIS (0x0 << 4) +#define NAU8825_ENGND_MASK (0x3 << 2) + +/* reg. NAU8825_JACK_DET_CTRL (0x0d) */ +#define NAU8825_DB_BP_MODE_MASK (0x1 << 8) +#define NAU8825_DB_BP_MODE_EN (0x1 << 8) +#define NAU8825_DB_BP_MODE_DIS (0x0 << 8) + +/* reg. NAU8825_IRQ_MASK (0x0f) */ +#define NAU8825_IRQ_QE_MASK (0x1 << 11) +#define NAU8825_IRQ_QE_EN (0x1 << 11) +#define NAU8825_IRQ_QE_DIS (0x0 << 11) +#define NAU8825_IRQ_EJECT_MASK (0x1 << 2) +#define NAU8825_IRQ_EJECT_EN (0x1 << 2) +#define NAU8825_IRQ_EJECT_DIS (0x0 << 2) + + +/* reg. NAU8825_IRQ_STATUS (0x10) */ +#define NAU8825_HSD_COMPLETE_INT (0x1 << 10) +#define NAU8825_EMRG_INT (0x1 << 9) +#define NAU8825_RMS_INT (0x1 << 8) +#define NAU8825_BTN_RELEASE_INT (0x1 << 7) +#define NAU8825_LONG_BTN_INT (0x1 << 6) +#define NAU8825_SHORT_BTN_INT (0x1 << 5) +#define NAU8825_BTN_INT (0x7 << 5) +#define NAU8825_MIC_DET_INT (0x1 << 4) +#define NAU8825_JACK_EJCT_INT (0x3 << 2) +#define NAU8825_JACK_DET_INT (0x3 << 0) +#define NAU8825_JACK_OUT (0x1 << 2) +#define NAU8825_JACK_IN (0x1 << 0) +#define NAU8825_JACK_INT (0xF << 0) + +/* reg. NAU8825_BTN_STATUS (0x11) */ +#define NAU8825_SHORT_BTN_MASK (0xFF << 8) +#define NAU8825_LONG_BTN_MASK (0xFF << 0) +#define NAU8825_BTN_0 (0x01 << 0) +#define NAU8825_BTN_1 (0x01 << 1) +#define NAU8825_BTN_2 (0x01 << 2) +#define NAU8825_BTN_3 (0x01 << 3) + +/* reg. NAU8825_IRQ_CTRL (0x12) */ +#define NAU8825_HEADSET_INT_MASK (0x1 << 10) +#define NAU8825_HEADSET_INT_EN (0x0 << 10) +#define NAU8825_HEADSET_INT_DIS (0x1 << 10) +#define NAU8825_RMS_INT_MASK (0x1 << 8) +#define NAU8825_RMS_INT_EN (0x0 << 8) +#define NAU8825_RMS_INT_DIS (0x1 << 8) +#define NAU8825_KEYREL_INT_MASK (0x1 << 7) +#define NAU8825_KEYREL_INT_EN (0x0 << 7) +#define NAU8825_KEYREL_INT_DIS (0x1 << 7) +#define NAU8825_LONGKEY_INT_MASK (0x1 << 6) +#define NAU8825_LONGKEY_INT_EN (0x0 << 6) +#define NAU8825_LONGKEY_INT_DIS (0x1 << 6) +#define NAU8825_SHORTKEY_INT_MASK (0x1 << 5) +#define NAU8825_SHORTKEY_INT_EN (0x0 << 5) +#define NAU8825_SHORTKEY_INT_DIS (0x1 << 5) +#define NAU8825_EJECT_INT_MASK (0x1 << 2) +#define NAU8825_EJECT_INT_EN (0x0 << 2) +#define NAU8825_EJECT_INT_DIS (0x1 << 2) +#define NAU8825_JACK_IN_INT_MASK (0x1 << 0) +#define NAU8825_JACK_IN_INT_EN (0x0 << 0) +#define NAU8825_JACK_IN_INT_DIS (0x1 << 0) + +/* reg. NAU8825_SAR_ADC (0x13) */ +#define NAU8825_SAR_EN_MASK (0x1 << 12) +#define NAU8825_SAR_EN (0x1 << 12) +#define NAU8825_SAR_DIS (0x0 << 12) +#define NAU8825_JKSLV_MASK (0x1 << 11) +#define NAU8825_JKSLV_EN (0x1 << 11) +#define NAU8825_JKSLV_DIS (0x0 << 11) + +/* reg. NAU8825_I2S_PCM_CTRL_1 (0x1C) */ +#define NAU8825_I2S_TRI_STATE_MASK (0x1 << 15) +#define NAU8825_I2S_TRI_STATE_EN (0x1 << 15) +#define NAU8825_I2S_TRI_STATE_DIS (0x0 << 15) +#define NAU8825_I2S_BP_MASK (0x1 << 7) +#define NAU8825_I2S_BP_INV (0x1 << 7) +#define NAU8825_I2S_PCMB_MASK (0x1 << 6) +#define NAU8825_I2S_PCMB_EN (0x1 << 6) +#define NAU8825_I2S_DL_MASK (0x3 << 2) +#define NAU8825_I2S_DF_MASK 0x3 +#define NAU8825_I2S_DF_RIGHT 0x0 +#define NAU8825_I2S_DF_LEFT 0x1 +#define NAU8825_I2S_DF_I2S 0x2 +#define NAU8825_I2S_DF_PCM_A 0x3 +#define NAU8825_I2S_DF_PCM_B 0x3 + +/* reg. NAU8825_I2S_PCM_CTRL_2 (0x1D) */ +#define NAU8825_I2S_MS_MASK (0x1 << 3) +#define NAU8825_I2S_MS_MASTER (0x1 << 3) +#define NAU8825_I2S_MS_SLAVE (0x0 << 3) + +/* reg. NAU8825_BIQ_CTRL (0x20) */ +#define NAU8825_BIQ_WRT_MASK (0x1 << 4) +#define NAU8825_BIQ_WRT_EN (0x1 << 4) +#define NAU8825_BIQ_WRT_DIS (0x0 << 4) + +/* reg. NAU8825_ADC_DGAIN_CTRL (0x30) */ +#define NAU8825_ADC_DGAIN_SFT 0 + +/* reg. NAU8825_DAC_MUTE_CTRL (0x31) */ +#define NAU8825_SOFT_MUTE_MASK (0x1 << 9) +#define NAU8825_SOFT_MUTE_EN (0x1 << 9) +#define NAU8825_SOFT_MUTE_DIS (0x0 << 9) + +/* reg. NAU8825_HSVOL_CTRL (0x32) */ +#define NAU8825_R_MUTE (0x1 << 15) +#define NAU8825_R_MUTE_SFT 15 +#define NAU8825_L_MUTE (0x1 << 14) +#define NAU8825_L_MUTE_SFT 14 +#define NAU8825_L_HSVOL_SFT 6 +#define NAU8825_R_HSVOL_SFT 0 + +/* reg. NAU8825_IMM_MODE_CTRL (0x4C) */ +#define NAU8825_IMM_MODE_EN_MASK (0x1 << 3) +#define NAU8825_IMM_MODE_EN (0x1 << 3) +#define NAU8825_IMM_MODE_DIS (0x0 << 3) + +/* reg. NAU8825_CLASSG_CTRL (0x50) */ +#define NAU8825_CLASSG_PATH_MASK (0x3 << 1) +#define NAU8825_CLASSG_PATH_EN (0x3 << 1) +#define NAU8825_CLASSG_PATH_DIS (0x3 << 0) +#define NAU8825_CLASSG_LEFT_SHIFT 1 +#define NAU8825_CLASSG_EN_SHIFT 0 +#define NAU8825_CLASSG_EN_MASK (0x1 << 0) +#define NAU8825_CLASSG_EN_SHIFT 0 + +/*#define NAU8825_I2C_DEVICE_ID (0x58) */ +#define NAU8825_GPIO2JD1 (0x1 << 7) + +/* reg. NAU8825_BIAS_ADJ (0x66) */ +#define NAU8825_VMID_MASK (0x1 << 6) +#define NAU8825_VMID_EN (0x1 << 6) +#define NAU8825_VMID_DIS (0x0 << 6) +#define NAU8825_VMIDSEL_MASK (0x3 << 4) +#define NAU8825_VMIDSEL_125KOHM (0x2 << 4) + +/* reg. NAU8825_ANALOG_CTRL_2 (0x6A) */ +#define NAU8825_VMID_MASK (0x1 << 6) +#define NAU8825_VMID_EN (0x1 << 6) +#define NAU8825_VMID_DIS (0x0 << 6) + +/* reg. NAU8825_DAC_CTRL (0x73) */ +#define NAU8825_DAC_R_SFT 13 +#define NAU8825_DAC_L_SFT 12 +#define NAU8825_DAC_CLK_R_SFT 9 +#define NAU8825_DAC_CLK_L_SFT 8 +#define NAU8825_DAC_LR_MASK (0x3 << 12) +#define NAU8825_DAC_LR_EN (0x3 << 12) +#define NAU8825_DAC_LR_DIS (0x0 << 12) +#define NAU8825_DAC_CLK_LR_MASK (0x3 << 8) +#define NAU8825_DAC_CLK_LR_EN (0x3 << 8) +#define NAU8825_DAC_CLK_LR_DIS (0x0 << 8) +#define NAU8825_DAC_CLK_DELAY_MASK (0x7 << 4) +#define NAU8825_DAC_REF_VOLT_MASK (0x3 << 2) + +/* reg. NAU8825_MIC_BIAS (0x74) */ +#define NAU8825_INT2KB_MSK (0x1 << 14) +#define NAU8825_INT2KB_EN (0x1 << 14) +#define NAU8825_INT2KB_DIS (0x0 << 14) +#define NAU8825_INT2KA_MSK (0x1 << 12) +#define NAU8825_INT2KA_EN (0x1 << 12) +#define NAU8825_INT2KA_DIS (0x0 << 12) +#define NAU8825_MIC_POWERUP_MSK (0x1 << 8) +#define NAU8825_MIC_POWERUP_EN (0x1 << 8) +#define NAU8825_MIC_POWERUP_DIS (0x0 << 8) +#define NAU8825_MIC_BIAS_LVL_MSK (0x7 << 0) + +/* reg. NAU8825_BOOST (0x76) */ +#define NAU8825_G_BIAS_MASK (0x1 << 12) +#define NAU8825_G_BIAS_SFT 12 +#define NAU8825_G_BIAS_EN (0x1 << 12) +#define NAU8825_G_BIAS_DIS (0x0 << 12) +#define NAU8825_BOOST_DRV_MASK (0x1 << 9) +#define NAU8825_BOOST_DRV_EN (0x0 << 9) +#define NAU8825_BOOST_DRV_DIS (0x1 << 9) + +/* reg. NAU8825_POWER_UP_CTRL (0x7F) */ +#define NAU8825_FEPGA_MASK (0x1 << 14) +#define NAU8825_FEPGA_EN (0x1 << 14) +#define NAU8825_FEPGA_DIS (0x0 << 14) +#define NAU8825_FEPGA_GAIN_MASK (0x3F << 8) +#define NAU8825_OUTPUT_DRIVER_MASK (0x3F << 0) +#define NAU8825_OUTPUT_DRIVER_EN (0x3F << 0) +#define NAU8825_OUTPUT_DRIVER_DIS (0x0 << 0) +#define NAU8825_PUP_INTEG_MASK (0x3 << 4) +#define NAU8825_PUP_INTEG_ENA (0x3 << 4) +#define NAU8825_PUP_INTEG_DIS (0x0 << 4) +#define NAU8825_PUP_OUT_MASK (0x3 << 2) +#define NAU8825_PUP_OUT_ENA (0x3 << 2) +#define NAU8825_PUP_OUT_DIS (0x0 << 2) +#define NAU8825_PUP_MAIN_MASK (0x3 << 0) +#define NAU8825_PUP_MAIN_ENA (0x3 << 0) +#define NAU8825_PUP_MAIN_DIS (0x0 << 0) + + +/* reg. NAU8825_CHARGE_BUMP_CTRL (0x80) */ +#define NAU8825_PD_DAC_MASK (0x3 << 8) +#define NAU8825_PD_DAC_ENA (0x3 << 8) +#define NAU8825_PD_DAC_DIS (0x0 << 8) +#define NAU8825_CB_CLK_MASK (0x1 << 7) +#define NAU8825_CB_CLK_EN (0x1 << 7) +#define NAU8825_CB_CLK_DIS (0x0 << 7) +#define NAU8825_CB_MASK (0x1 << 5) +#define NAU8825_CB_EN (0x1 << 5) +#define NAU8825_CB_DIS (0x0 << 5) + +/* reg. NAU8825_GENERAL_STATUS (0x82) */ +#define NAU8825_OUT12_MASK (0x3 << 10) +#define NAU8825_OUT2EN_OUT1EN (0x3 << 10) +#define NAU8825_OUT2EN_OUT1DIS (0x2 << 10) +#define NAU8825_OUT2DIS_OUT1EN (0x1 << 10) +#define NAU8825_OUT2DIS_OUT1DIS (0x0 << 10) + +/* Volume Rescale */ +#define NAU8825_VOL_RSCL_RANGE 0x36 +#define NAU8825_ADC_VOL_RSCL_RANGE 0xFF + +/* Data format */ +#define NAU8825_I2S_DL_16 (0x0 << 2) +#define NAU8825_I2S_DL_20 (0x1 << 2) +#define NAU8825_I2S_DL_24 (0x2 << 2) +#define NAU8825_I2S_DL_32 (0x3 << 2) + +enum { + NAU8825_INTERNALCLOCK = 0, + NAU8825_MCLK, +}; + +struct nau8825_priv { + struct regmap *regmap; + struct i2c_client *i2c; +}; +#endif /* _NAU8825_H */ + -- 1.9.3

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[alsa-devel] [PATCH 0/7] ASoC: Cleanup AC'97 reset handling
by Lars-Peter Clausen 27 Jul '15

27 Jul '15

AC'97 devices require that they are properly reset before they can be used. Currently ASoC drivers do this by hand each on its own. This lead to many similar but slightly different implementations. E.g. Some supporting warm reset, some don't. And even though AC'97 do have a device ID which uniquely identifies a device most drivers only use the content of register 0 for device verification. This patch series introduces a new generic helper function in the ALSA AC'97 core that can be used to reset a device and verify its ID if required. And then converts drivers to use this new helper function instead of custom code. snd_soc_new_ac97_codec() is extended to be able to perform a reset between the allocation and registration of the AC'97 device, this will allow more drivers to use it. - Lars Lars-Peter Clausen (7): ALSA: ac97: Add helper function to reset the AC97 device ASoC: ac97: Add support for resetting device before registration ASoC: ad1980: Use core AC'97 reset helper ASoC: stac9766: Use core reset helper ASoC: wm9705: Use core AC'97 reset helper ASoC: wm9712: Use core AC'97 reset helper ASoC: wm9713: Use core AC'97 reset helper include/sound/ac97_codec.h | 2 ++ include/sound/soc.h | 3 ++- sound/ac97_bus.c | 62 +++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/ad1980.c | 36 +++++++++----------------- sound/soc/codecs/stac9766.c | 57 +++++------------------------------------ sound/soc/codecs/wm9705.c | 40 ++++++----------------------- sound/soc/codecs/wm9712.c | 45 ++++++-------------------------- sound/soc/codecs/wm9713.c | 48 ++++++----------------------------- sound/soc/codecs/wm9713.h | 2 -- sound/soc/soc-ac97.c | 30 ++++++++++++++++++---- 10 files changed, 134 insertions(+), 191 deletions(-) -- 2.1.4

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[alsa-devel] [ALC668]: Asus N751JK - Incorrect default pin assignment for external base speaker and external microphone not working
by Arthur Borsboom 27 Jul '15

27 Jul '15

Hi, While being in the process of making my audio work on my new notebook, I noticed that the audio hardware is partially working out-of-the-Linux-kernel-box v4.0.7 Arch. The following two things seem not to work. -------------------------------- 1. External base speaker -------------------------------- The Asus N751JK notebook (ALC668) has a small external 'base' speaker (jack 2,5mm 4 rings), which I only can get to work with the help of hdajackretask with the following setting: * Override unconnected pin 0x1a and connect it to Internal Speaker (LFE). In the sound kernel tree I have noticed PCI ID fixes which are more or less equal to this situation. https://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/tree/sound/pci… This SND_PCI_QUIRK definition looks a lot like it: SND_PCI_QUIRK(0x1043, 0x11cd, "Asus N550", ALC662_FIXUP_BASS_1A), The Vendor/PCI ID is different for this laptop and I guess a new line should be added something like this: SND_PCI_QUIRK(0x1043, 0x17bd, "Asus N751JK", ALC662_FIXUP_BASS_1A), -------------------------------- 2. External microphone -------------------------------- The Asus N751JK notebook (ALC668) has a 3,5mm 4-ring combo jack for headphones and microphone. The headphone is detected correct and auto-mute works good (jack detection). The microphone is not detected and does not work. I was unable to get it to work with hdajackretask or any of the Asus model settings, such as: * options snd_hda_intel model=,asus-mode4 I was able to get the microphone to work with the following setting: * options snd_hda_intel model=,dell-headset-multi This setting creates two new items in PulseAudio making a total of three: * Internal microphone (works out of the box) * Headset microphone (works indeed with a headset) * Microphone (don't know if this works, since I don't have a single microphone, but it does not work with the headset) Unfortunately the auto-input-device-switch to the Headset microphone does not seem to work. When I plugin a headset, the headphones get detected and the Internal speakers are muted. The Input device does not automatically switch from Internal microphone to Headset microphone. I have to do this manually, after which it works. I don't know if the microphone has a jack detection. If it does not, maybe it is possible to use the headphones jack detection? I have added the alsa-info without any snd_intel / alsa modifications here: http://www.alsa-project.org/db/?f=0b5135bd12f28bb5cb182f83bfa21bc50022faa6 I don't mind to help to test, for example module options, patches and/or compile kernels. Who is able and willing to help to fix this issue? With kind regards, Arthur Borsboom. -- Arthur Borsboom Email: arthurborsboom(a)gmail.com

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[alsa-devel] Possible GPL-licensed header included in alsa-lib
by Clemens Lang 27 Jul '15

27 Jul '15

Hi, I recently reviewed the alsa-lib 1.0.27.2 source code from a licensing perspective to ensure compliant usage and distribution. It seems the intention is for the libraries to be covered by LGPL. I had a look at include/list.h, which seems to be licensed under GPL-2.0. It does not have a license header or any other copyright information, but it states it was taken from Linux 2.4.0: include/list.h, line 5: | This code was taken from the Linux 2.4.0 kernel. [jaroslav] I'm not sure one could argue that the header was trivial, especially since it does not only contain constants, structures and interface definitions, but also implementations of inline functions. I found one previous inquiry about a similar issue[1], but it does not cover the include/list.h header. Two questions: 1. Have the copyright holders of the code in question agreed to re-license under a different, LGPL-preserving license and, if yes, is there some documentation about that? 2. If the header is indeed covered by GPL-2.0, would you accept patches to replace it with a different implementation, e.g. Rusty Russell's MIT-licensed list from ccan[2]? [1] http://mailman.alsa-project.org/pipermail/alsa-devel/2011-March/038267.html [2] http://ccodearchive.net/info/list.html Thank you for your time, Clemens Lang -- BMW Car IT GmbH Clemens Lang Spezialist Entwicklung Lise-Meitner-Straße 14 89081 Ulm Mail: clemens.lang(a)bmw-carit.de Web: http://www.bmw-carit.de -------------------------------------------------------------------- BMW Car IT GmbH Geschäftsführer: Michael Würtenberger und Reinhard Stolle Sitz und Registergericht: München HRB 134810 --------------------------------------------------------------------

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[alsa-devel] snd_pcm_set_params faild on set_buffer_time_near and set_period_time_near
by Martin Geier 27 Jul '15

27 Jul '15

Hallo, I tried to configure alsa device with snd_pcm_set_params function, requested parameters was: channel 2, rate: 22050, soft_resample: 1, latency: 50000 Function snd_pcm_hw_params_set_buffer_time_near and snd_pcm_hw_param_set_near is called with: min: 50000, max: 50000, mindir: 0, maxdir: -1 and input params was: ACCESS: RW_INTERLEAVED FORMAT: S16_LE SUBFORMAT: STD SAMPLE_BITS: 16 FRAME_BITS: 32 CHANNELS: 2 RATE: 22050 PERIOD_TIME: (362 743039) PERIOD_SIZE: [8 16384] PERIOD_BYTES: [32 65536] PERIODS: [2 19] BUFFER_TIME: (725 1486078) BUFFER_SIZE: [16 32768] BUFFER_BYTES: [64 131072] TICK_TIME: ALL unfortunately, this function fails, on function snd_pcm_hw_param_set_first: ALSA ERROR hw_params: set_near (BUFFER_TIME) value = 50000 : Invalid argument ACCESS: RW_INTERLEAVED FORMAT: S16_LE SUBFORMAT: STD SAMPLE_BITS: 16 FRAME_BITS: 32 CHANNELS: 2 RATE: 22050 PERIOD_TIME: (4580 5533) PERIOD_SIZE: NONE PERIOD_BYTES: [404 488] PERIODS: 10 BUFFER_TIME: (50022 50023) BUFFER_SIZE: 1103 BUFFER_BYTES: 4412 TICK_TIME: ALL This shouldn't be problem because in snd_pcm_set_params is snd_pcm_hw_params_set_period_time_near called. This function should be called with same params as snd_pcm_hw_params_set_buffer_time_near but the input params are: snd_pcm_hw_param_set_near: min: 12500, max: 12500, mindir: 0, maxdir: -1 hw_params: snd_pcm_hw_param_set_near (PERIOD_TIME) ACCESS: RW_INTERLEAVED FORMAT: S16_LE SUBFORMAT: STD SAMPLE_BITS: 16 FRAME_BITS: 32 CHANNELS: 2 RATE: 22050 PERIOD_TIME: (4580 5533) PERIOD_SIZE: NONE PERIOD_BYTES: [404 488] PERIODS: 10 BUFFER_TIME: (50022 50023) BUFFER_SIZE: 1103 BUFFER_BYTES: 4412 TICK_TIME: ALL because in snd_pcm_hw_param_set_near is if (last) err = snd_pcm_hw_param_set_last(pcm, params, var, val, dir); else err = snd_pcm_hw_param_set_first(pcm, params, var, val, dir); if (err < 0) dump_hw_params(params, "set_near", var, *val, err); return err; and in error part is only debug output and not restore original parameters. Environment: alsa-lib 1.0.27.1 TI AM335x soc Simple fix is attached, but I am not sure if it is correct. BR Martin Geier -- *StreamUnlimited* High Tech Campus Vienna, Gutheil-Schoder-Gasse 10, A-1102 Vienna, Austria Levocska 9, 851 01 Bratislava, Slovakia Email: martin.geier(a)streamunlimited.com www.streamunlimited.com

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[alsa-devel] [PATCH] ALSA: hda - Apply fixup for another Toshiba Satellite S50D
by Takashi Iwai 27 Jul '15

27 Jul '15

Toshiba Satellite S50D has another model with a different PCI SSID (1179:fa93) while the previous fixup was for 1179:fa91. Adjust the fixup entry with SND_PCI_QUIRK_MASK() to match with both devices. Reported-by: Tim Sample <timsample(a)gmail.com> Cc: <stable(a)vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_sigmatel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index dcc7fe91244c..9d947aef2c8b 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -2920,7 +2920,8 @@ static const struct snd_pci_quirk stac92hd83xxx_fixup_tbl[] = { SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x148a, "HP Mini", STAC_92HD83XXX_HP_LED), SND_PCI_QUIRK_VENDOR(PCI_VENDOR_ID_HP, "HP", STAC_92HD83XXX_HP), - SND_PCI_QUIRK(PCI_VENDOR_ID_TOSHIBA, 0xfa91, + /* match both for 0xfa91 and 0xfa93 */ + SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_TOSHIBA, 0xfffd, 0xfa91, "Toshiba Satellite S50D", STAC_92HD83XXX_GPIO10_EAPD), {} /* terminator */ }; -- 2.4.6

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[alsa-devel] [PATCH] ALSA: fireworks: add support for AudioFire2 quirk
by Takashi Sakamoto 27 Jul '15

27 Jul '15

Fireworks uses TSB43CB43(IceLynx-Micro) as its IEC 61883-1/6 interface. This chip includes ARM7 core, and loads and runs program. The firmware is stored in on-board memory and loaded every powering-on. Echo Audio ships several versions of firmwares for each model. These firmwares have each quirk and the quirk changes a sequence of packets. AudioFire2 has a quirk to transfer a first packet with non-zero in its dbc field. This causes ALSA Fireworks driver to detect discontinuity. As long as I investigated, firmware 5.7, 5.7.6 and 5.8 have this quirk. This commit adds a support for the quirk to handle AudioFire2 packets. For safe, CIP_SKIP_INIT_DBC_CHECK is applied to all versions of AudioFire2's firmwares. 02 00050002 90ffffff <- 42 0005000a 90013000 42 00050012 90014400 42 0005001a 90015800 02 0005001a 90ffffff 42 00050022 90019000 42 0005002a 9001a400 42 00050032 9001b800 02 00050032 90ffffff 42 0005003a 9001d000 42 00050042 9001e400 42 0005004a 9001f800 02 0005004a 90ffffff Signed-off-by: Takashi Sakamoto <o-takashi(a)sakamocchi.jp> --- sound/firewire/fireworks/fireworks.c | 2 ++ sound/firewire/fireworks/fireworks.h | 1 + sound/firewire/fireworks/fireworks_stream.c | 3 +++ 3 files changed, 6 insertions(+) diff --git a/sound/firewire/fireworks/fireworks.c b/sound/firewire/fireworks/fireworks.c index 2682e7e..c670db4 100644 --- a/sound/firewire/fireworks/fireworks.c +++ b/sound/firewire/fireworks/fireworks.c @@ -248,6 +248,8 @@ efw_probe(struct fw_unit *unit, err = get_hardware_info(efw); if (err < 0) goto error; + if (entry->model_id == MODEL_ECHO_AUDIOFIRE_2) + efw->is_af2 = true; if (entry->model_id == MODEL_ECHO_AUDIOFIRE_9) efw->is_af9 = true; diff --git a/sound/firewire/fireworks/fireworks.h b/sound/firewire/fireworks/fireworks.h index 4f0201a..c33252b 100644 --- a/sound/firewire/fireworks/fireworks.h +++ b/sound/firewire/fireworks/fireworks.h @@ -70,6 +70,7 @@ struct snd_efw { bool resp_addr_changable; /* for quirks */ + bool is_af2; bool is_af9; u32 firmware_version; diff --git a/sound/firewire/fireworks/fireworks_stream.c b/sound/firewire/fireworks/fireworks_stream.c index c55db1b..a0762dd 100644 --- a/sound/firewire/fireworks/fireworks_stream.c +++ b/sound/firewire/fireworks/fireworks_stream.c @@ -172,6 +172,9 @@ int snd_efw_stream_init_duplex(struct snd_efw *efw) efw->tx_stream.flags |= CIP_DBC_IS_END_EVENT; /* Fireworks reset dbc at bus reset. */ efw->tx_stream.flags |= CIP_SKIP_DBC_ZERO_CHECK; + /* AudioFire2 starts packets with non-zero dbc. */ + if (efw->is_af2) + efw->tx_stream.flags |= CIP_SKIP_INIT_DBC_CHECK; /* AudioFire9 always reports wrong dbs. */ if (efw->is_af9) efw->tx_stream.flags |= CIP_WRONG_DBS; -- 2.1.4

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