July 2015 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [RFC PATCH 0/4] better support for bursty DMA usages
by Pierre-Louis Bossart 30 Jul '15

30 Jul '15

Set of patches to fix issues with hw_ptr fuzziness [1] and increased buffering w/ DSPs 1. disable rewinds to allow for new HDaudio SPIB DMA functionality (fetch up to the application pointer, rewinds not supported) 2. report max in-flight bytes to avoid problems with stale data (late wake-ups, rewinds) [1] http://mailman.alsa-project.org/pipermail/alsa-devel/2015-June/093646.html TODO: 1. fixes and alsa-lib updates (compile-tested only for now) 2. get feedback 3. if supported, set DMA buffering based on negotiation between driver and app (capabilities vs. latency needs) Pierre-Louis Bossart (4): ALSA: core: let low-level driver or userspace disable rewinds ALSA: core: add .notify callback for pcm ops ALSA: core: add report of max dma burst ALSA: hda: add default value for max_dma_burst include/sound/pcm.h | 5 +++++ include/uapi/sound/asound.h | 6 ++++-- sound/core/pcm_lib.c | 19 +++++++++++++++++++ sound/core/pcm_native.c | 33 ++++++++++++++++++++++++++++++++- sound/pci/hda/hda_controller.c | 1 + 5 files changed, 61 insertions(+), 3 deletions(-) -- 1.9.1

6 33

Re: [alsa-devel] [ALC668]: Asus N751JK - Incorrect default pin assignment for external base speaker and external microphone not working
by Raymond Yau 30 Jul '15

30 Jul '15

> > "... after you replaced speakers.conf and lineout.conf by subwoofer.conf ..." > > I must have missed something again. I was under the impression that changing the configuration files was a workaround when the patch would be insufficient. Later today or tomorrow, I will reread this part and apply changes to the configuration files and report back. Ports: analog-output-speaker: Speakers (priority: 10000) analog-output-headphones: Headphones (priority: 9000, not available) Active Port: analog-output-speaker When you select model=dell-headset-multi, the driver create "Headphone Mic Jack" kctl with type 1 which is SND_JACK_HEADPHONE type 2 is SND_JACK_MICROPHONE type 3 is SND_JACK_HEADSET but hda jack does not use this type https://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/tree/include/s… JACK created Headphone Mic, type 1 CTRL: add: Headphone Mic Jack:0 JACK report Headphone Mic, status 0 JACK created Headset Mic Phantom, type 2 CTRL: add: Headset Mic Phantom Jack:0 JACK report Headset Mic Phantom, status 2 CTL Notify: Headset Mic Phantom Jack:0, mask=1 JACK created Internal Mic Phantom, type 2 CTRL: add: Internal Mic Phantom Jack:0 JACK report Internal Mic Phantom, status 2 CTL Notify: Internal Mic Phantom Jack:0, mask=1 JACK created Speaker Front Phantom, type 4 CTRL: add: Speaker Front Phantom Jack:0 JACK report Speaker Front Phantom, status 4 CTL Notify: Speaker Front Phantom Jack:0, mask=1 JACK created External Subwoofer, type 4 CTRL: add: External Subwoofer Jack:0 The problem of hda jack kctls are those retaskable I/O jack controls 1) multi io jacks in those 3 stack desktop 2) headphone/mic jack in asus netbook 3) dell-headset-multi combo jack the role of the jack in 1) change from input to output when "Channel mode" change from "2ch" to "4ch" or "6ch" the role of the jack in 2) and 3) change from Output to Input when "Capture Source" change from Internal Mic/Headset Mic to Headphone Mic In your case, Headphone Mic Jack kctl return the presence of HP jack except when the combo jack is set to support conventional mic (i.e. when the driver change pin ctl of hp pin node 0x15 to zero and set pin ctl of mic pin to IN), The driver already unmute the internal speaker when you change capture source to Headphone Mic The only point is whether pulseaudio still regard this Headphone Mic Jack as the availability of the headphone port when the capture source is Headphone Mic http://cgit.freedesktop.org/pulseaudio/pulseaudio/commit/?id=ca4942e89cf462…

1 0

[alsa-devel] [PATCH] ALSA: hda - Fix race between PM ops and HDA init/probe
by U. Artie Eoff 29 Jul '15

29 Jul '15

PM ops could be triggered before HDA is done initializing and cause PM to set HDA controller to D3Hot. This can result in "CORB reset timeout#2, CORBRP = 65535" and "no codecs initialized". Additionally, PM ops can be triggered before azx_probe_continue finishes (async probe). This can result in a NULL deref kernel crash. To fix this, avoid PM ops if !chip->running. Signed-off-by: U. Artie Eoff <ullysses.a.eoff(a)intel.com> --- sound/pci/hda/hda_intel.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 735bdcb04ce8..c38c68f57938 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -867,7 +867,7 @@ static int azx_suspend(struct device *dev) chip = card->private_data; hda = container_of(chip, struct hda_intel, chip); - if (chip->disabled || hda->init_failed) + if (chip->disabled || hda->init_failed || !chip->running) return 0; bus = azx_bus(chip); @@ -902,7 +902,7 @@ static int azx_resume(struct device *dev) chip = card->private_data; hda = container_of(chip, struct hda_intel, chip); - if (chip->disabled || hda->init_failed) + if (chip->disabled || hda->init_failed || !chip->running) return 0; if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL @@ -1027,7 +1027,7 @@ static int azx_runtime_idle(struct device *dev) return 0; if (!power_save_controller || !azx_has_pm_runtime(chip) || - azx_bus(chip)->codec_powered) + azx_bus(chip)->codec_powered || !chip->running) return -EBUSY; return 0; -- 2.1.0

3 3

[alsa-devel] [PATCH v2] ASoC: rt5677: Return error if devm_gpiod_get_optional return ERR_PTR
by Axel Lin 29 Jul '15

29 Jul '15

If devm_gpiod_get_optional() return ERR_PTR, it means something wrong so request gpio fails. We had better return error in such case. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/rt5677.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 8d70911..83e25a3 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -5133,14 +5133,14 @@ static int rt5677_i2c_probe(struct i2c_client *i2c, if (IS_ERR(rt5677->pow_ldo2)) { ret = PTR_ERR(rt5677->pow_ldo2); dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); - rt5677->pow_ldo2 = 0; + return ret; } rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, "realtek,reset", GPIOD_OUT_HIGH); if (IS_ERR(rt5677->reset_pin)) { ret = PTR_ERR(rt5677->reset_pin); dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); - rt5677->reset_pin = 0; + return ret; } if (rt5677->pow_ldo2 || rt5677->reset_pin) { -- 2.1.0

2 1

[alsa-devel] [PATCH] ASoC: tas2552: Remove unneeded NULL test for tas2552->enable_gpio
by Axel Lin 29 Jul '15

29 Jul '15

It's safe to call gpiod_set_value() with NULL desc. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/tas2552.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c index 2f6a65a..e3a0bca 100644 --- a/sound/soc/codecs/tas2552.c +++ b/sound/soc/codecs/tas2552.c @@ -493,8 +493,7 @@ static int tas2552_runtime_suspend(struct device *dev) regcache_cache_only(tas2552->regmap, true); regcache_mark_dirty(tas2552->regmap); - if (tas2552->enable_gpio) - gpiod_set_value(tas2552->enable_gpio, 0); + gpiod_set_value(tas2552->enable_gpio, 0); return 0; } @@ -503,8 +502,7 @@ static int tas2552_runtime_resume(struct device *dev) { struct tas2552_data *tas2552 = dev_get_drvdata(dev); - if (tas2552->enable_gpio) - gpiod_set_value(tas2552->enable_gpio, 1); + gpiod_set_value(tas2552->enable_gpio, 1); tas2552_sw_shutdown(tas2552, 0); @@ -585,8 +583,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec) return ret; } - if (tas2552->enable_gpio) - gpiod_set_value(tas2552->enable_gpio, 1); + gpiod_set_value(tas2552->enable_gpio, 1); ret = pm_runtime_get_sync(codec->dev); if (ret < 0) { @@ -610,8 +607,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec) return 0; probe_fail: - if (tas2552->enable_gpio) - gpiod_set_value(tas2552->enable_gpio, 0); + gpiod_set_value(tas2552->enable_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(tas2552->supplies), tas2552->supplies); @@ -624,8 +620,7 @@ static int tas2552_codec_remove(struct snd_soc_codec *codec) pm_runtime_put(codec->dev); - if (tas2552->enable_gpio) - gpiod_set_value(tas2552->enable_gpio, 0); + gpiod_set_value(tas2552->enable_gpio, 0); return 0; }; -- 2.1.0

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[alsa-devel] [RFT][PATCH 1/2] ASoC: max98088: Get rid of max98088_access table
by Axel Lin 29 Jul '15

29 Jul '15

The max98088_access table is used for look up readable/writable/volatile attributes of registers. The readable/writable/volatile registers are mostly in continuous ranges, so we can replace the max98088_access table entirely by using case range. Below is a summary of the readable/writeable/volatile registers: readable registers: 0x00 ~ 0xC9, 0xFF writeable registers: 0x03 ~ 0xC9, 0xFF volatile registers: 0x00 ~ 0x03, 0xFF Note, 0x00 should be read-only according to the datasheet. This patch reworks the implement for .readable and .volatile and also add implementation for .writable callback. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/max98088.c | 305 ++++---------------------------------------- 1 file changed, 25 insertions(+), 280 deletions(-) diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index 99c2daa..2c2df17 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -258,292 +258,36 @@ static const struct reg_default max98088_reg[] = { { 0xc9, 0x00 }, /* C9 DAI2 biquad */ }; -static struct { - int readable; - int writable; - int vol; -} max98088_access[M98088_REG_CNT] = { - { 0xFF, 0xFF, 1 }, /* 00 IRQ status */ - { 0xFF, 0x00, 1 }, /* 01 MIC status */ - { 0xFF, 0x00, 1 }, /* 02 jack status */ - { 0x1F, 0x1F, 1 }, /* 03 battery voltage */ - { 0xFF, 0xFF, 0 }, /* 04 */ - { 0xFF, 0xFF, 0 }, /* 05 */ - { 0xFF, 0xFF, 0 }, /* 06 */ - { 0xFF, 0xFF, 0 }, /* 07 */ - { 0xFF, 0xFF, 0 }, /* 08 */ - { 0xFF, 0xFF, 0 }, /* 09 */ - { 0xFF, 0xFF, 0 }, /* 0A */ - { 0xFF, 0xFF, 0 }, /* 0B */ - { 0xFF, 0xFF, 0 }, /* 0C */ - { 0xFF, 0xFF, 0 }, /* 0D */ - { 0xFF, 0xFF, 0 }, /* 0E */ - { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */ - - { 0xFF, 0xFF, 0 }, /* 10 master clock */ - { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */ - { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */ - { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */ - { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */ - { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */ - { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */ - { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */ - { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */ - { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */ - { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */ - { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */ - { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */ - { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */ - { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */ - { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */ - - { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */ - { 0xFF, 0xFF, 0 }, /* 21 data config */ - { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */ - { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */ - { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */ - { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */ - { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */ - { 0xFF, 0xFF, 0 }, /* 27 HP control */ - { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */ - { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */ - { 0xFF, 0xFF, 0 }, /* 2A REC control */ - { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */ - { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */ - { 0xFF, 0xFF, 0 }, /* 2D SPK control */ - { 0xFF, 0xFF, 0 }, /* 2E sidetone */ - { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */ - - { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */ - { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */ - { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */ - { 0xFF, 0xFF, 0 }, /* 33 left ADC level */ - { 0xFF, 0xFF, 0 }, /* 34 right ADC level */ - { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */ - { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */ - { 0xFF, 0xFF, 0 }, /* 37 INA level */ - { 0xFF, 0xFF, 0 }, /* 38 INB level */ - { 0xFF, 0xFF, 0 }, /* 39 left HP volume */ - { 0xFF, 0xFF, 0 }, /* 3A right HP volume */ - { 0xFF, 0xFF, 0 }, /* 3B left REC volume */ - { 0xFF, 0xFF, 0 }, /* 3C right REC volume */ - { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */ - { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */ - { 0xFF, 0xFF, 0 }, /* 3F MIC config */ - - { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */ - { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */ - { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */ - { 0xFF, 0xFF, 0 }, /* 43 ALC */ - { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */ - { 0xFF, 0xFF, 0 }, /* 45 power limiter config */ - { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */ - { 0xFF, 0xFF, 0 }, /* 47 audio input */ - { 0xFF, 0xFF, 0 }, /* 48 microphone */ - { 0xFF, 0xFF, 0 }, /* 49 level control */ - { 0xFF, 0xFF, 0 }, /* 4A bypass switches */ - { 0xFF, 0xFF, 0 }, /* 4B jack detect */ - { 0xFF, 0xFF, 0 }, /* 4C input enable */ - { 0xFF, 0xFF, 0 }, /* 4D output enable */ - { 0xFF, 0xFF, 0 }, /* 4E bias control */ - { 0xFF, 0xFF, 0 }, /* 4F DAC power */ - - { 0xFF, 0xFF, 0 }, /* 50 DAC power */ - { 0xFF, 0xFF, 0 }, /* 51 system */ - { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */ - - { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */ - - { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */ - { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */ - - { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */ - { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */ - { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */ - - { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */ - { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */ - - { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */ - { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */ - { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */ - - { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */ - { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */ - { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */ - - { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */ - { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */ - { 0x00, 0x00, 0 }, /* CA */ - { 0x00, 0x00, 0 }, /* CB */ - { 0x00, 0x00, 0 }, /* CC */ - { 0x00, 0x00, 0 }, /* CD */ - { 0x00, 0x00, 0 }, /* CE */ - { 0x00, 0x00, 0 }, /* CF */ - - { 0x00, 0x00, 0 }, /* D0 */ - { 0x00, 0x00, 0 }, /* D1 */ - { 0x00, 0x00, 0 }, /* D2 */ - { 0x00, 0x00, 0 }, /* D3 */ - { 0x00, 0x00, 0 }, /* D4 */ - { 0x00, 0x00, 0 }, /* D5 */ - { 0x00, 0x00, 0 }, /* D6 */ - { 0x00, 0x00, 0 }, /* D7 */ - { 0x00, 0x00, 0 }, /* D8 */ - { 0x00, 0x00, 0 }, /* D9 */ - { 0x00, 0x00, 0 }, /* DA */ - { 0x00, 0x00, 0 }, /* DB */ - { 0x00, 0x00, 0 }, /* DC */ - { 0x00, 0x00, 0 }, /* DD */ - { 0x00, 0x00, 0 }, /* DE */ - { 0x00, 0x00, 0 }, /* DF */ - - { 0x00, 0x00, 0 }, /* E0 */ - { 0x00, 0x00, 0 }, /* E1 */ - { 0x00, 0x00, 0 }, /* E2 */ - { 0x00, 0x00, 0 }, /* E3 */ - { 0x00, 0x00, 0 }, /* E4 */ - { 0x00, 0x00, 0 }, /* E5 */ - { 0x00, 0x00, 0 }, /* E6 */ - { 0x00, 0x00, 0 }, /* E7 */ - { 0x00, 0x00, 0 }, /* E8 */ - { 0x00, 0x00, 0 }, /* E9 */ - { 0x00, 0x00, 0 }, /* EA */ - { 0x00, 0x00, 0 }, /* EB */ - { 0x00, 0x00, 0 }, /* EC */ - { 0x00, 0x00, 0 }, /* ED */ - { 0x00, 0x00, 0 }, /* EE */ - { 0x00, 0x00, 0 }, /* EF */ - - { 0x00, 0x00, 0 }, /* F0 */ - { 0x00, 0x00, 0 }, /* F1 */ - { 0x00, 0x00, 0 }, /* F2 */ - { 0x00, 0x00, 0 }, /* F3 */ - { 0x00, 0x00, 0 }, /* F4 */ - { 0x00, 0x00, 0 }, /* F5 */ - { 0x00, 0x00, 0 }, /* F6 */ - { 0x00, 0x00, 0 }, /* F7 */ - { 0x00, 0x00, 0 }, /* F8 */ - { 0x00, 0x00, 0 }, /* F9 */ - { 0x00, 0x00, 0 }, /* FA */ - { 0x00, 0x00, 0 }, /* FB */ - { 0x00, 0x00, 0 }, /* FC */ - { 0x00, 0x00, 0 }, /* FD */ - { 0x00, 0x00, 0 }, /* FE */ - { 0xFF, 0x00, 1 }, /* FF */ -}; - static bool max98088_readable_register(struct device *dev, unsigned int reg) { - return max98088_access[reg].readable; + switch (reg) { + case M98088_REG_00_IRQ_STATUS ... 0xC9: + case M98088_REG_FF_REV_ID: + return true; + default: + return false; + } +} + +static bool max98088_writeable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9: + return true; + default: + return false; + } } static bool max98088_volatile_register(struct device *dev, unsigned int reg) { - return max98088_access[reg].vol; + switch (reg) { + case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE: + case M98088_REG_FF_REV_ID: + return true; + default: + return false; + } } static const struct regmap_config max98088_regmap = { @@ -551,6 +295,7 @@ static const struct regmap_config max98088_regmap = { .val_bits = 8, .readable_reg = max98088_readable_register, + .writeable_reg = max98088_writeable_register, .volatile_reg = max98088_volatile_register, .max_register = 0xff, -- 2.1.0

2 3

[alsa-devel] [PATCH] ASoC: wm8983: Get rid of wm8983_access_masks table
by Axel Lin 29 Jul '15

29 Jul '15

The max8983_access table is used for look up readable/writable attributes of registers. The writable registers are mostly in continuous ranges, so we can replace max8983_access table by using case range. The read fields are all 0, so just drop implement of .readable callback. Also set .max_register setting. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/wm8983.c | 80 +++++++++-------------------------------------- 1 file changed, 14 insertions(+), 66 deletions(-) diff --git a/sound/soc/codecs/wm8983.c b/sound/soc/codecs/wm8983.c index f6861cc..f3193fb 100644 --- a/sound/soc/codecs/wm8983.c +++ b/sound/soc/codecs/wm8983.c @@ -84,66 +84,6 @@ static const struct reg_default wm8983_defaults[] = { { 0x3D, 0x0000 }, /* R61 - BIAS CTRL */ }; -static const struct wm8983_reg_access { - u16 read; /* Mask of readable bits */ - u16 write; /* Mask of writable bits */ -} wm8983_access_masks[WM8983_MAX_REGISTER + 1] = { - [0x00] = { 0x0000, 0x01FF }, /* R0 - Software Reset */ - [0x01] = { 0x0000, 0x01FF }, /* R1 - Power management 1 */ - [0x02] = { 0x0000, 0x01FF }, /* R2 - Power management 2 */ - [0x03] = { 0x0000, 0x01EF }, /* R3 - Power management 3 */ - [0x04] = { 0x0000, 0x01FF }, /* R4 - Audio Interface */ - [0x05] = { 0x0000, 0x003F }, /* R5 - Companding control */ - [0x06] = { 0x0000, 0x01FD }, /* R6 - Clock Gen control */ - [0x07] = { 0x0000, 0x000F }, /* R7 - Additional control */ - [0x08] = { 0x0000, 0x003F }, /* R8 - GPIO Control */ - [0x09] = { 0x0000, 0x0070 }, /* R9 - Jack Detect Control 1 */ - [0x0A] = { 0x0000, 0x004F }, /* R10 - DAC Control */ - [0x0B] = { 0x0000, 0x01FF }, /* R11 - Left DAC digital Vol */ - [0x0C] = { 0x0000, 0x01FF }, /* R12 - Right DAC digital vol */ - [0x0D] = { 0x0000, 0x00FF }, /* R13 - Jack Detect Control 2 */ - [0x0E] = { 0x0000, 0x01FB }, /* R14 - ADC Control */ - [0x0F] = { 0x0000, 0x01FF }, /* R15 - Left ADC Digital Vol */ - [0x10] = { 0x0000, 0x01FF }, /* R16 - Right ADC Digital Vol */ - [0x12] = { 0x0000, 0x017F }, /* R18 - EQ1 - low shelf */ - [0x13] = { 0x0000, 0x017F }, /* R19 - EQ2 - peak 1 */ - [0x14] = { 0x0000, 0x017F }, /* R20 - EQ3 - peak 2 */ - [0x15] = { 0x0000, 0x017F }, /* R21 - EQ4 - peak 3 */ - [0x16] = { 0x0000, 0x007F }, /* R22 - EQ5 - high shelf */ - [0x18] = { 0x0000, 0x01FF }, /* R24 - DAC Limiter 1 */ - [0x19] = { 0x0000, 0x007F }, /* R25 - DAC Limiter 2 */ - [0x1B] = { 0x0000, 0x01FF }, /* R27 - Notch Filter 1 */ - [0x1C] = { 0x0000, 0x017F }, /* R28 - Notch Filter 2 */ - [0x1D] = { 0x0000, 0x017F }, /* R29 - Notch Filter 3 */ - [0x1E] = { 0x0000, 0x017F }, /* R30 - Notch Filter 4 */ - [0x20] = { 0x0000, 0x01BF }, /* R32 - ALC control 1 */ - [0x21] = { 0x0000, 0x00FF }, /* R33 - ALC control 2 */ - [0x22] = { 0x0000, 0x01FF }, /* R34 - ALC control 3 */ - [0x23] = { 0x0000, 0x000F }, /* R35 - Noise Gate */ - [0x24] = { 0x0000, 0x001F }, /* R36 - PLL N */ - [0x25] = { 0x0000, 0x003F }, /* R37 - PLL K 1 */ - [0x26] = { 0x0000, 0x01FF }, /* R38 - PLL K 2 */ - [0x27] = { 0x0000, 0x01FF }, /* R39 - PLL K 3 */ - [0x29] = { 0x0000, 0x000F }, /* R41 - 3D control */ - [0x2A] = { 0x0000, 0x01E7 }, /* R42 - OUT4 to ADC */ - [0x2B] = { 0x0000, 0x01BF }, /* R43 - Beep control */ - [0x2C] = { 0x0000, 0x0177 }, /* R44 - Input ctrl */ - [0x2D] = { 0x0000, 0x01FF }, /* R45 - Left INP PGA gain ctrl */ - [0x2E] = { 0x0000, 0x01FF }, /* R46 - Right INP PGA gain ctrl */ - [0x2F] = { 0x0000, 0x0177 }, /* R47 - Left ADC BOOST ctrl */ - [0x30] = { 0x0000, 0x0177 }, /* R48 - Right ADC BOOST ctrl */ - [0x31] = { 0x0000, 0x007F }, /* R49 - Output ctrl */ - [0x32] = { 0x0000, 0x01FF }, /* R50 - Left mixer ctrl */ - [0x33] = { 0x0000, 0x01FF }, /* R51 - Right mixer ctrl */ - [0x34] = { 0x0000, 0x01FF }, /* R52 - LOUT1 (HP) volume ctrl */ - [0x35] = { 0x0000, 0x01FF }, /* R53 - ROUT1 (HP) volume ctrl */ - [0x36] = { 0x0000, 0x01FF }, /* R54 - LOUT2 (SPK) volume ctrl */ - [0x37] = { 0x0000, 0x01FF }, /* R55 - ROUT2 (SPK) volume ctrl */ - [0x38] = { 0x0000, 0x004F }, /* R56 - OUT3 mixer ctrl */ - [0x39] = { 0x0000, 0x00FF }, /* R57 - OUT4 (MONO) mix ctrl */ - [0x3D] = { 0x0000, 0x0100 } /* R61 - BIAS CTRL */ -}; - /* vol/gain update regs */ static const int vol_update_regs[] = { WM8983_LEFT_DAC_DIGITAL_VOL, @@ -605,12 +545,19 @@ static int eqmode_put(struct snd_kcontrol *kcontrol, return 0; } -static bool wm8983_readable(struct device *dev, unsigned int reg) +static bool wm8983_writeable(struct device *dev, unsigned int reg) { - if (reg > WM8983_MAX_REGISTER) - return 0; - - return wm8983_access_masks[reg].read != 0; + switch (reg) { + case WM8983_SOFTWARE_RESET ... WM8983_RIGHT_ADC_DIGITAL_VOL: + case WM8983_EQ1_LOW_SHELF ... WM8983_DAC_LIMITER_2: + case WM8983_NOTCH_FILTER_1 ... WM8983_NOTCH_FILTER_4: + case WM8983_ALC_CONTROL_1 ... WM8983_PLL_K_3: + case WM8983_3D_CONTROL ... WM8983_OUT4_MONO_MIX_CTRL: + case WM8983_BIAS_CTRL: + return true; + default: + return false; + } } static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute) @@ -1048,8 +995,9 @@ static const struct regmap_config wm8983_regmap = { .reg_defaults = wm8983_defaults, .num_reg_defaults = ARRAY_SIZE(wm8983_defaults), .cache_type = REGCACHE_RBTREE, + .max_register = WM8983_MAX_REGISTER, - .readable_reg = wm8983_readable, + .writeable_reg = wm8983_writeable, }; #if defined(CONFIG_SPI_MASTER) -- 2.1.0

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[alsa-devel] [PATCH 1/2] ASoC: Intel: haswell: fix initialize 'NULL device *' issue
by Jie Yang 29 Jul '15

29 Jul '15

Add initialization for sst_hsw.dev at init stage, which fix the 'NULL device *' warning issues. Signed-off-by: Jie Yang <yang.jie(a)intel.com> --- sound/soc/intel/haswell/sst-haswell-ipc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/intel/haswell/sst-haswell-ipc.c b/sound/soc/intel/haswell/sst-haswell-ipc.c index f95f271..f6efa9d 100644 --- a/sound/soc/intel/haswell/sst-haswell-ipc.c +++ b/sound/soc/intel/haswell/sst-haswell-ipc.c @@ -2119,6 +2119,8 @@ int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata) if (hsw == NULL) return -ENOMEM; + hsw->dev = dev; + ipc = &hsw->ipc; ipc->dev = dev; ipc->ops.tx_msg = hsw_tx_msg; -- 1.9.1

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[alsa-devel] [PATCH 0/6] ASoC: Fix sparse warnings
by Lars-Peter Clausen 29 Jul '15

29 Jul '15

Hi, This series fixes a couple of sparse warnings that have appeared recently in the ASoC tree. Non of them are critical mostly just missing annotations or storage qualifiers. It still makes sense to fix those though since it reduces the noise that has to be filtered through when checking new code for new (potentially critical) warnings. - Lars Lars-Peter Clausen (6): ASoC: wm8804: Drop dublicate const ASoC: lpass-ipq806x: Staticise local symbols ASoC: rcar ctu: Staticise local symbols ASoC: uniperf: Add missing __iomem annotation ASoC: uniperf: Staticise local symbols ASoC: xtfpga-i2s: Add missing __rcu annotation sound/soc/codecs/wm8804.c | 2 +- sound/soc/qcom/lpass-ipq806x.c | 2 +- sound/soc/sh/rcar/ctu.c | 2 +- sound/soc/sti/uniperif.h | 2 +- sound/soc/sti/uniperif_player.c | 2 +- sound/soc/xtensa/xtfpga-i2s.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) -- 2.1.4

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[alsa-devel] [PATCH] ASoC: max98090: Simplify max98090_readable_register implementation
by Axel Lin 29 Jul '15

29 Jul '15

The readable registers are in consecutive ranges: 0x01 ~ 0x03, 0x0D ~ 0xD1, 0xFF So simplify the implementation by specifying a range of consecutive values in a single case label. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/max98090.c | 71 ++------------------------------------------- 1 file changed, 2 insertions(+), 69 deletions(-) diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index 91c9f9f..315c71f 100644 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -267,75 +267,8 @@ static bool max98090_volatile_register(struct device *dev, unsigned int reg) static bool max98090_readable_register(struct device *dev, unsigned int reg) { switch (reg) { - case M98090_REG_DEVICE_STATUS: - case M98090_REG_JACK_STATUS: - case M98090_REG_INTERRUPT_S: - case M98090_REG_RESERVED: - case M98090_REG_LINE_INPUT_CONFIG: - case M98090_REG_LINE_INPUT_LEVEL: - case M98090_REG_INPUT_MODE: - case M98090_REG_MIC1_INPUT_LEVEL: - case M98090_REG_MIC2_INPUT_LEVEL: - case M98090_REG_MIC_BIAS_VOLTAGE: - case M98090_REG_DIGITAL_MIC_ENABLE: - case M98090_REG_DIGITAL_MIC_CONFIG: - case M98090_REG_LEFT_ADC_MIXER: - case M98090_REG_RIGHT_ADC_MIXER: - case M98090_REG_LEFT_ADC_LEVEL: - case M98090_REG_RIGHT_ADC_LEVEL: - case M98090_REG_ADC_BIQUAD_LEVEL: - case M98090_REG_ADC_SIDETONE: - case M98090_REG_SYSTEM_CLOCK: - case M98090_REG_CLOCK_MODE: - case M98090_REG_CLOCK_RATIO_NI_MSB: - case M98090_REG_CLOCK_RATIO_NI_LSB: - case M98090_REG_CLOCK_RATIO_MI_MSB: - case M98090_REG_CLOCK_RATIO_MI_LSB: - case M98090_REG_MASTER_MODE: - case M98090_REG_INTERFACE_FORMAT: - case M98090_REG_TDM_CONTROL: - case M98090_REG_TDM_FORMAT: - case M98090_REG_IO_CONFIGURATION: - case M98090_REG_FILTER_CONFIG: - case M98090_REG_DAI_PLAYBACK_LEVEL: - case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: - case M98090_REG_LEFT_HP_MIXER: - case M98090_REG_RIGHT_HP_MIXER: - case M98090_REG_HP_CONTROL: - case M98090_REG_LEFT_HP_VOLUME: - case M98090_REG_RIGHT_HP_VOLUME: - case M98090_REG_LEFT_SPK_MIXER: - case M98090_REG_RIGHT_SPK_MIXER: - case M98090_REG_SPK_CONTROL: - case M98090_REG_LEFT_SPK_VOLUME: - case M98090_REG_RIGHT_SPK_VOLUME: - case M98090_REG_DRC_TIMING: - case M98090_REG_DRC_COMPRESSOR: - case M98090_REG_DRC_EXPANDER: - case M98090_REG_DRC_GAIN: - case M98090_REG_RCV_LOUTL_MIXER: - case M98090_REG_RCV_LOUTL_CONTROL: - case M98090_REG_RCV_LOUTL_VOLUME: - case M98090_REG_LOUTR_MIXER: - case M98090_REG_LOUTR_CONTROL: - case M98090_REG_LOUTR_VOLUME: - case M98090_REG_JACK_DETECT: - case M98090_REG_INPUT_ENABLE: - case M98090_REG_OUTPUT_ENABLE: - case M98090_REG_LEVEL_CONTROL: - case M98090_REG_DSP_FILTER_ENABLE: - case M98090_REG_BIAS_CONTROL: - case M98090_REG_DAC_CONTROL: - case M98090_REG_ADC_CONTROL: - case M98090_REG_DEVICE_SHUTDOWN: - case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: - case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: - case M98090_REG_DMIC3_VOLUME: - case M98090_REG_DMIC4_VOLUME: - case M98090_REG_DMIC34_BQ_PREATTEN: - case M98090_REG_RECORD_TDM_SLOT: - case M98090_REG_SAMPLE_RATE: - case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: + case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S: + case M98090_REG_LINE_INPUT_CONFIG ... 0xD1: case M98090_REG_REVISION_ID: return true; default: -- 2.1.0

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