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[alsa-devel] ALSA Core: Sound Card registration (CPU --> CODEC_1 --> CODEC_2)
by phaniu＠codeaurora.org 04 Sep '14

04 Sep '14

Hi, We have a question regarding how sound card can be registered for the following scenario: CPU connecting to Audio CODEC_1 and then CODEC_1 connecting to another Audio CODEC_2 (over some bus like i2c). CODEC_1 can be represented as a codec_dai and can be registered to ASoC framework (with snd_soc_register_codec()) during system boot up. However, for end-to-end audio to work on this system, we also need CODEC_2 somehow registered to ASoC framework so that audio path on CODEC_2 can configured. Could you please let us know if CODEC_2 can also registered as another dai and if yes, how it can be achieved ? Or is there any other way to probe_defer sound card registration till CODEC_2 is enumerated on the bus. In this case, to what component of the sound card dailink structure, the Audio CODEC_2 can be represented ? Please share your thoughts on this. Best Regards, Phani The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

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Re: [alsa-devel] [v3 04/11] ASoC: Intel: sst: Add IPC handling
by Mark Brown 03 Sep '14

03 Sep '14

On Mon, Sep 01, 2014 at 07:27:07PM +0530, Subhransu S. Prusty wrote: > On Mon, Sep 01, 2014 at 01:51:14PM +0100, Mark Brown wrote: > > On Mon, Sep 01, 2014 at 05:47:53PM +0530, Subhransu S. Prusty wrote: > > > > I'd expect much louder complaints if we try to free something that's not > > > > allocated - what happens if we end up reallocating something quickly and > > > > then double freeing? Better to complain if we hit such a code path. > > > > > "freed" is a block which is passed by the caller to be freed up. Will add a > > > comment. > > How would that address the problem? Obviously the caller is trying to > > free what they're passing in. > sst_create_block() which allocates the memory and sst_free_block() which > frees the memory are called in a synchronous way. A single thread who is > allocating waits till a response arrives, if that response is valid then > after processing the response the sst_free_block() is called to free up the > memory. So the double freeing will not happen. Does this address your concern? No. You've described what happens when things are working and everything is operating correctly and there are no bugs in the kernel, the goal with error checking is to provide robustness against the possibility that one of those things isn't true so we can tell what went wrong more easily than if we get memory corruption.

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[alsa-devel] [PATCH 0/5] ASoC: Remove unnecessary suspend/resume bias level changes
by Lars-Peter Clausen 03 Sep '14

03 Sep '14

Hi, There are a handful of drivers which do set idle_bias_level = true, but at the same time implement suspend and resume handlers which do bias level transitions to OFF in suspend and to STANDBY in resume. Since the ASoC core will only suspend a CODEC if it is idle this means that drivers that set idle_bias_level = true will already be at bias level OFF when suspend is called, which makes the manual transition unnecessary. On the other hand manual transition to STANDBY in resume will be reverted by the core going back to OFF after the resume handler has run. So the manual bias level change in resume is also unnecessary and can cause additional IO operations. This series removes all those unnecessary manual bias level transitions. - Lars Lars-Peter Clausen (5): ASoC: adau1373: Remove unnecessary suspend/resume bias level changes ASoC: lm49453: Remove unnecessary suspend/resume bias level changes ASoC: tlv320aic3x: Remove unnecessary suspend/resume bias level changes ASoC: wm8804: Remove unnecessary suspend/resume bias level changes ASoC: wm8995: Remove unnecessary suspend/resume bias level changes sound/soc/codecs/adau1373.c | 14 -------------- sound/soc/codecs/lm49453.c | 14 -------------- sound/soc/codecs/tlv320aic3x.c | 16 ---------------- sound/soc/codecs/wm8804.c | 19 ------------------- sound/soc/codecs/wm8995.c | 19 ------------------- 5 files changed, 82 deletions(-) -- 1.8.0

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[alsa-devel] [GIT PULL] ASoC fixes for v3.17
by Mark Brown 03 Sep '14

03 Sep '14

The following changes since commit 69e273c0b0a3c337a521d083374c918dc52c666f: Linux 3.17-rc3 (2014-08-31 18:23:04 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git asoc-v3.17-rc3 for you to fetch changes up to f58f0cba15c2d0bfbc72b1eedd0a6294e8c83419: Merge remote-tracking branches 'asoc/fix/axi', 'asoc/fix/cs4265', 'asoc/fix/da732x', 'asoc/fix/omap', 'asoc/fix/rsnd', 'asoc/fix/rt5640', 'asoc/fix/rt5677', 'asoc/fix/simple' and 'asoc/fix/tegra' into asoc-linus (2014-09-02 23:33:39 +0100) ---------------------------------------------------------------- ASoC: Fixes for v3.17 A few more driver specific fixes on top of the currently pending fixes (which are already in your tree but not Linus'). ---------------------------------------------------------------- Andreas Färber (1): ASoC: axi: Fix ADI AXI SPDIF specification Bard Liao (1): ASoC: rt5677: correct mismatch widget name Jarkko Nikula (1): ASoC: rt5640: Do not allow regmap to use bulk read-write operations Lars-Peter Clausen (2): ASoC: Use dev_set_name() instead of init_name ASoC: rcar: Use && instead of & for boolean expressions Mark Brown (2): Merge remote-tracking branch 'asoc/fix/core' into asoc-linus Merge remote-tracking branches 'asoc/fix/axi', 'asoc/fix/cs4265', 'asoc/fix/da732x', 'asoc/fix/omap', 'asoc/fix/rsnd', 'asoc/fix/rt5640', 'asoc/fix/rt5677', 'asoc/fix/simple' and 'asoc/fix/tegra' into asoc-linus Paul Handrigan (2): ASoC: cs4265: Fix clock rates in clock map table ASoC: cs4265: Fix setting of functional mode and clock divider Peter Ujfalusi (1): ASoC: omap-twl4030: Fix typo in 2nd dai link's platform_name Rasmus Villemoes (2): ASoC: da732x: Fix typo in include guard ASoC: tegra: Fix typo in include guard Subhransu S. Prusty (1): ASoC: core: fix .info for SND_SOC_BYTES_TLV Xiubo Li (1): ASoC: simple-card: Fix bug of wrong decrement DT node's refcount Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt | 2 +- include/sound/soc.h | 2 +- sound/soc/codecs/cs4265.c | 12 ++++++------ sound/soc/codecs/da732x.h | 2 +- sound/soc/codecs/rt5640.c | 1 + sound/soc/codecs/rt5677.c | 8 ++++---- sound/soc/generic/simple-card.c | 8 ++++++++ sound/soc/omap/omap-twl4030.c | 2 +- sound/soc/sh/rcar/gen.c | 2 +- sound/soc/soc-core.c | 2 +- sound/soc/tegra/tegra_asoc_utils.h | 2 +- 11 files changed, 26 insertions(+), 17 deletions(-)

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[alsa-devel] [PATCH] ASoC: davinci-mcasp: Fix rx rotation settings
by Peter Ujfalusi 03 Sep '14

03 Sep '14

We need to take into account the slot size as well when calculating the RROT for received data. This patch will fix S24_3LE audio capture. Signed-off-by: Peter Ujfalusi <peter.ujfalusi(a)ti.com> --- sound/soc/davinci/davinci-mcasp.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index 6a6b2ff7d7d7..267cd4937c7c 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -463,11 +463,11 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, } static int davinci_config_channel_size(struct davinci_mcasp *mcasp, - int word_length) + int slot_size, int word_length) { u32 fmt; u32 tx_rotate = (word_length / 4) & 0x7; - u32 rx_rotate = (32 - word_length) / 4; + u32 rx_rotate = (slot_size - word_length) / 4; u32 mask = (1ULL << word_length) - 1; /* @@ -726,7 +726,7 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[substream->stream]; - int word_length; + int word_length, slot_size; int channels = params_channels(params); int period_size = params_period_size(params); int ret; @@ -766,31 +766,32 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, case SNDRV_PCM_FORMAT_U8: case SNDRV_PCM_FORMAT_S8: dma_params->data_type = 1; - word_length = 8; + slot_size = word_length = 8; break; case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_S16_LE: dma_params->data_type = 2; - word_length = 16; + slot_size = word_length = 16; break; case SNDRV_PCM_FORMAT_U24_3LE: case SNDRV_PCM_FORMAT_S24_3LE: dma_params->data_type = 3; - word_length = 24; + slot_size = word_length = 24; break; case SNDRV_PCM_FORMAT_U24_LE: case SNDRV_PCM_FORMAT_S24_LE: dma_params->data_type = 4; word_length = 24; + slot_size = 32; break; case SNDRV_PCM_FORMAT_U32_LE: case SNDRV_PCM_FORMAT_S32_LE: dma_params->data_type = 4; - word_length = 32; + slot_size = word_length = 32; break; default: @@ -803,7 +804,7 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, else dma_params->acnt = dma_params->data_type; - davinci_config_channel_size(mcasp, word_length); + davinci_config_channel_size(mcasp, slot_size, word_length); return 0; } -- 2.1.0

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[alsa-devel] [PATCH] ASoC: max98090: Add recovery for PLL lock failure
by Jarkko Nikula 03 Sep '14

03 Sep '14

All MAX98090 input clocks MCLK, LRCLK and BCLK must be running and stable before powering on the codec in slave mode. Otherwise the PLL may not lock to LRCLK causing silence in playback and capture. How often that happens is somewhat hardware and clock configuration specific. Now if wanting to follow strictly this clocks must be active before powering the codec on requirement we should have a notification from DAI driver to codec driver when clocks are activated and take codec out of shutdown only after that. Plus take care of possible active bypass paths. However, when PLL unlock occurs, MAX98090 asserts the PLL Unlock Flag which can be configured as an IRQ source. This allows to workaround around the issue by toggling the codec power shortly in case of PLL lock failure. In order to prevent needlessly toggling codec power in case of short PLL unlocks at the beginning of stream this patch implements delayed activation for PLL unlock interrupt. Then workaround is run only when the PLL doesn't lock at all. Power toggling workaround for PLL unlock comes originally from Liam Girdwood <liam.r.girdwood(a)linux.intel.com> and delayed activation from me. Signed-off-by: Jarkko Nikula <jarkko.nikula(a)linux.intel.com> Cc: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- For normal development cycle. We have observed this on a byt-max98090 based machine earlier when another MCLK rate was showing silent audio occasionally but with current 25 MHz MCLK it either doesn't occur or is much more rare. I'm not sure is this needed but wanted to share it if tegra_max98090 for instance have noticed it. --- sound/soc/codecs/max98090.c | 111 +++++++++++++++++++++++++++++++++++++++++++- sound/soc/codecs/max98090.h | 3 ++ 2 files changed, 112 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index 4a063fa88526..f1543653a699 100644 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -1972,6 +1972,102 @@ static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) return 0; } +static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (!max98090->master && dai->active == 1) + queue_delayed_work(system_power_efficient_wq, + &max98090->pll_det_enable_work, + msecs_to_jiffies(10)); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (!max98090->master && dai->active == 1) + schedule_work(&max98090->pll_det_disable_work); + break; + default: + break; + } + + return 0; +} + +static void max98090_pll_det_enable_work(struct work_struct *work) +{ + struct max98090_priv *max98090 = + container_of(work, struct max98090_priv, + pll_det_enable_work.work); + struct snd_soc_codec *codec = max98090->codec; + unsigned int status, mask; + + /* + * Clear status register in order to clear possibly already occurred + * PLL unlock. If PLL hasn't still locked, the status will be set + * again and PLL unlock interrupt will occur. + * Note this will clear all status bits + */ + regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); + + /* + * Queue jack work in case jack state has just changed but handler + * hasn't run yet + */ + regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); + status &= mask; + if (status & M98090_JDET_MASK) + queue_delayed_work(system_power_efficient_wq, + &max98090->jack_work, + msecs_to_jiffies(100)); + + /* Enable PLL unlock interrupt */ + snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, + M98090_IULK_MASK, + 1 << M98090_IULK_SHIFT); +} + +static void max98090_pll_det_disable_work(struct work_struct *work) +{ + struct max98090_priv *max98090 = + container_of(work, struct max98090_priv, pll_det_disable_work); + struct snd_soc_codec *codec = max98090->codec; + + cancel_delayed_work_sync(&max98090->pll_det_enable_work); + + /* Disable PLL unlock interrupt */ + snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, + M98090_IULK_MASK, 0); +} + +static void max98090_pll_work(struct work_struct *work) +{ + struct max98090_priv *max98090 = + container_of(work, struct max98090_priv, pll_work); + struct snd_soc_codec *codec = max98090->codec; + + if (!snd_soc_codec_is_active(codec)) + return; + + dev_info(codec->dev, "PLL unlocked\n"); + + /* Toggle shutdown OFF then ON */ + snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN, + M98090_SHDNN_MASK, 0); + msleep(10); + snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN, + M98090_SHDNN_MASK, M98090_SHDNN_MASK); + + /* Give PLL time to lock */ + msleep(10); +} + static void max98090_jack_work(struct work_struct *work) { struct max98090_priv *max98090 = container_of(work, @@ -2103,8 +2199,10 @@ static irqreturn_t max98090_interrupt(int irq, void *data) if (active & M98090_SLD_MASK) dev_dbg(codec->dev, "M98090_SLD_MASK\n"); - if (active & M98090_ULK_MASK) - dev_err(codec->dev, "M98090_ULK_MASK\n"); + if (active & M98090_ULK_MASK) { + dev_dbg(codec->dev, "M98090_ULK_MASK\n"); + schedule_work(&max98090->pll_work); + } if (active & M98090_JDET_MASK) { dev_dbg(codec->dev, "M98090_JDET_MASK\n"); @@ -2177,6 +2275,7 @@ static struct snd_soc_dai_ops max98090_dai_ops = { .set_tdm_slot = max98090_set_tdm_slot, .hw_params = max98090_dai_hw_params, .digital_mute = max98090_dai_digital_mute, + .trigger = max98090_dai_trigger, }; static struct snd_soc_dai_driver max98090_dai[] = { @@ -2258,6 +2357,11 @@ static int max98090_probe(struct snd_soc_codec *codec) max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); + INIT_DELAYED_WORK(&max98090->pll_det_enable_work, + max98090_pll_det_enable_work); + INIT_WORK(&max98090->pll_det_disable_work, + max98090_pll_det_disable_work); + INIT_WORK(&max98090->pll_work, max98090_pll_work); /* Enable jack detection */ snd_soc_write(codec, M98090_REG_JACK_DETECT, @@ -2310,6 +2414,9 @@ static int max98090_remove(struct snd_soc_codec *codec) struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); cancel_delayed_work_sync(&max98090->jack_work); + cancel_delayed_work_sync(&max98090->pll_det_enable_work); + cancel_work_sync(&max98090->pll_det_disable_work); + cancel_work_sync(&max98090->pll_work); return 0; } diff --git a/sound/soc/codecs/max98090.h b/sound/soc/codecs/max98090.h index cf1b6062ba8c..14427a566f41 100644 --- a/sound/soc/codecs/max98090.h +++ b/sound/soc/codecs/max98090.h @@ -1532,6 +1532,9 @@ struct max98090_priv { int irq; int jack_state; struct delayed_work jack_work; + struct delayed_work pll_det_enable_work; + struct work_struct pll_det_disable_work; + struct work_struct pll_work; struct snd_soc_jack *jack; unsigned int dai_fmt; int tdm_slots; -- 2.1.0

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[alsa-devel] [PATCH 0/2] tlv320aic31xx PLL programming fix and cleanup
by Jyri Sarha 03 Sep '14

03 Sep '14

The first patch is the fix and the second is only a cleanup. Jyri Sarha (2): ASoC: tlv320aic31xx: Fix 24bit samples with I2S format and 12MHz mclk ASoC: tlv320aic31xx: Choose PLL p divider automatically sound/soc/codecs/tlv320aic31xx.c | 128 +++++++++++++++++++++++--------------- 1 file changed, 77 insertions(+), 51 deletions(-) -- 1.7.9.5

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[alsa-devel] [PATCH v8 3/7] clk: Move all drivers to use internal API
by Tomeu Vizoso 03 Sep '14

03 Sep '14

In preparation to change the public API to return a per-user clk structure, remove any usage of this public API from the clock implementations. The reason for having this in a separate commit from the one that introduces the implementation of the new functions is to separate the changes generated with Coccinelle from the rest, and keep the patches' size reasonable. Signed-off-by: Tomeu Vizoso <tomeu.vizoso(a)collabora.com> Tested-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> Tested-by: Heiko Stuebner <heiko(a)sntech.de> Acked-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> --- arch/arm/mach-dove/common.c | 10 +- arch/arm/mach-imx/clk-busy.c | 8 +- arch/arm/mach-imx/clk-fixup-div.c | 4 +- arch/arm/mach-imx/clk-fixup-mux.c | 4 +- arch/arm/mach-imx/clk-gate2.c | 4 +- arch/arm/mach-imx/clk-imx1.c | 2 +- arch/arm/mach-imx/clk-imx21.c | 2 +- arch/arm/mach-imx/clk-imx25.c | 8 +- arch/arm/mach-imx/clk-imx27.c | 4 +- arch/arm/mach-imx/clk-imx31.c | 10 +- arch/arm/mach-imx/clk-imx35.c | 22 +- arch/arm/mach-imx/clk-imx51-imx53.c | 77 +++--- arch/arm/mach-imx/clk-imx6q.c | 53 ++-- arch/arm/mach-imx/clk-imx6sl.c | 21 +- arch/arm/mach-imx/clk-imx6sx.c | 97 ++++--- arch/arm/mach-imx/clk-pfd.c | 4 +- arch/arm/mach-imx/clk-pllv1.c | 4 +- arch/arm/mach-imx/clk-pllv2.c | 4 +- arch/arm/mach-imx/clk-pllv3.c | 4 +- arch/arm/mach-imx/clk-vf610.c | 44 +-- arch/arm/mach-imx/clk.c | 10 +- arch/arm/mach-imx/clk.h | 42 +-- arch/arm/mach-msm/clock-pcom.c | 2 +- arch/arm/mach-mv78xx0/common.c | 2 +- arch/arm/mach-omap2/cclock3xxx_data.c | 370 +++++++++++++------------- arch/arm/mach-omap2/clkt2xxx_dpll.c | 4 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 4 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 2 +- arch/arm/mach-omap2/clkt_clksel.c | 46 ++-- arch/arm/mach-omap2/clkt_dpll.c | 8 +- arch/arm/mach-omap2/clock.c | 52 ++-- arch/arm/mach-omap2/clock.h | 18 +- arch/arm/mach-omap2/clock3xxx.c | 22 +- arch/arm/mach-omap2/clock3xxx.h | 4 +- arch/arm/mach-omap2/clock_common_data.c | 2 +- arch/arm/mach-omap2/clockdomain.c | 8 +- arch/arm/mach-omap2/clockdomain.h | 4 +- arch/arm/mach-omap2/display.c | 4 +- arch/arm/mach-omap2/dpll3xxx.c | 28 +- arch/arm/mach-omap2/dpll44xx.c | 4 +- arch/arm/mach-omap2/mcbsp.c | 4 +- arch/arm/mach-omap2/omap_device.c | 8 +- arch/arm/mach-omap2/omap_hwmod.c | 42 +-- arch/arm/mach-omap2/omap_hwmod.h | 12 +- arch/arm/mach-omap2/pm24xx.c | 12 +- arch/arm/mach-orion5x/common.c | 2 +- arch/arm/mach-shmobile/clock.c | 8 +- arch/arm/mach-vexpress/spc.c | 4 +- arch/arm/plat-orion/common.c | 20 +- arch/arm/plat-orion/include/plat/common.h | 12 +- arch/powerpc/platforms/512x/clock-commonclk.c | 48 ++-- drivers/clk/at91/clk-main.c | 24 +- drivers/clk/at91/clk-master.c | 6 +- drivers/clk/at91/clk-peripheral.c | 12 +- drivers/clk/at91/clk-pll.c | 6 +- drivers/clk/at91/clk-plldiv.c | 6 +- drivers/clk/at91/clk-programmable.c | 10 +- drivers/clk/at91/clk-slow.c | 24 +- drivers/clk/at91/clk-smd.c | 6 +- drivers/clk/at91/clk-system.c | 6 +- drivers/clk/at91/clk-usb.c | 18 +- drivers/clk/at91/clk-utmi.c | 6 +- drivers/clk/bcm/clk-kona-setup.c | 6 +- drivers/clk/bcm/clk-kona.c | 12 +- drivers/clk/bcm/clk-kona.h | 2 +- drivers/clk/berlin/berlin2-avpll.c | 4 +- drivers/clk/berlin/berlin2-avpll.h | 4 +- drivers/clk/berlin/berlin2-div.c | 2 +- drivers/clk/berlin/berlin2-div.h | 2 +- drivers/clk/berlin/berlin2-pll.c | 2 +- drivers/clk/berlin/berlin2-pll.h | 2 +- drivers/clk/berlin/bg2.c | 12 +- drivers/clk/berlin/bg2q.c | 8 +- drivers/clk/clk-axi-clkgen.c | 2 +- drivers/clk/clk-axm5516.c | 4 +- drivers/clk/clk-bcm2835.c | 2 +- drivers/clk/clk-composite.c | 10 +- drivers/clk/clk-conf.c | 16 +- drivers/clk/clk-divider.c | 8 +- drivers/clk/clk-efm32gg.c | 2 +- drivers/clk/clk-fixed-factor.c | 6 +- drivers/clk/clk-fixed-rate.c | 8 +- drivers/clk/clk-fractional-divider.c | 4 +- drivers/clk/clk-gate.c | 4 +- drivers/clk/clk-highbank.c | 8 +- drivers/clk/clk-ls1x.c | 16 +- drivers/clk/clk-max77686.c | 10 +- drivers/clk/clk-moxart.c | 8 +- drivers/clk/clk-mux.c | 6 +- drivers/clk/clk-nomadik.c | 14 +- drivers/clk/clk-nspire.c | 4 +- drivers/clk/clk-ppc-corenet.c | 8 +- drivers/clk/clk-s2mps11.c | 6 +- drivers/clk/clk-si5351.c | 17 +- drivers/clk/clk-si570.c | 4 +- drivers/clk/clk-twl6040.c | 2 +- drivers/clk/clk-u300.c | 12 +- drivers/clk/clk-vt8500.c | 4 +- drivers/clk/clk-wm831x.c | 6 +- drivers/clk/clk-xgene.c | 12 +- drivers/clk/clk.h | 4 +- drivers/clk/hisilicon/clk-hi3620.c | 8 +- drivers/clk/hisilicon/clk.c | 16 +- drivers/clk/hisilicon/clk.h | 2 +- drivers/clk/hisilicon/clkgate-separated.c | 4 +- drivers/clk/keystone/gate.c | 6 +- drivers/clk/keystone/pll.c | 10 +- drivers/clk/mmp/clk-apbc.c | 4 +- drivers/clk/mmp/clk-apmu.c | 4 +- drivers/clk/mmp/clk-frac.c | 4 +- drivers/clk/mmp/clk-mmp2.c | 14 +- drivers/clk/mmp/clk-pxa168.c | 12 +- drivers/clk/mmp/clk-pxa910.c | 12 +- drivers/clk/mmp/clk.h | 8 +- drivers/clk/mvebu/clk-corediv.c | 4 +- drivers/clk/mvebu/clk-cpu.c | 8 +- drivers/clk/mvebu/common.c | 14 +- drivers/clk/mvebu/kirkwood.c | 6 +- drivers/clk/mxs/clk-div.c | 4 +- drivers/clk/mxs/clk-frac.c | 4 +- drivers/clk/mxs/clk-imx23.c | 4 +- drivers/clk/mxs/clk-imx28.c | 4 +- drivers/clk/mxs/clk-pll.c | 4 +- drivers/clk/mxs/clk-ref.c | 4 +- drivers/clk/mxs/clk.h | 16 +- drivers/clk/qcom/clk-rcg.c | 8 +- drivers/clk/qcom/clk-rcg2.c | 14 +- drivers/clk/qcom/clk-regmap.c | 2 +- drivers/clk/qcom/clk-regmap.h | 2 +- drivers/clk/qcom/common.c | 6 +- drivers/clk/qcom/gcc-msm8660.c | 2 +- drivers/clk/qcom/gcc-msm8960.c | 2 +- drivers/clk/qcom/gcc-msm8974.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 6 +- drivers/clk/rockchip/clk-pll.c | 8 +- drivers/clk/rockchip/clk-rk3188.c | 2 +- drivers/clk/rockchip/clk-rk3288.c | 2 +- drivers/clk/rockchip/clk-rockchip.c | 2 +- drivers/clk/rockchip/clk.c | 14 +- drivers/clk/rockchip/clk.h | 4 +- drivers/clk/samsung/clk-exynos-audss.c | 16 +- drivers/clk/samsung/clk-exynos-clkout.c | 8 +- drivers/clk/samsung/clk-exynos4.c | 6 +- drivers/clk/samsung/clk-pll.c | 6 +- drivers/clk/samsung/clk-pll.h | 2 +- drivers/clk/samsung/clk-s3c2410-dclk.c | 30 +-- drivers/clk/samsung/clk.c | 22 +- drivers/clk/samsung/clk.h | 2 +- drivers/clk/shmobile/clk-div6.c | 2 +- drivers/clk/shmobile/clk-emev2.c | 4 +- drivers/clk/shmobile/clk-mstp.c | 6 +- drivers/clk/shmobile/clk-r8a7740.c | 6 +- drivers/clk/shmobile/clk-r8a7779.c | 6 +- drivers/clk/shmobile/clk-rcar-gen2.c | 10 +- drivers/clk/shmobile/clk-rz.c | 6 +- drivers/clk/sirf/clk-atlas6.c | 2 +- drivers/clk/sirf/clk-common.c | 30 +-- drivers/clk/sirf/clk-prima2.c | 2 +- drivers/clk/socfpga/clk-gate.c | 2 +- drivers/clk/socfpga/clk-periph.c | 2 +- drivers/clk/socfpga/clk-pll.c | 4 +- drivers/clk/spear/clk-aux-synth.c | 8 +- drivers/clk/spear/clk-frac-synth.c | 4 +- drivers/clk/spear/clk-gpt-synth.c | 4 +- drivers/clk/spear/clk-vco-pll.c | 8 +- drivers/clk/spear/clk.h | 14 +- drivers/clk/spear/spear1310_clock.c | 2 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/clk/spear/spear3xx_clock.c | 16 +- drivers/clk/spear/spear6xx_clock.c | 2 +- drivers/clk/st/clk-flexgen.c | 12 +- drivers/clk/st/clkgen-fsyn.c | 22 +- drivers/clk/st/clkgen-mux.c | 32 +-- drivers/clk/st/clkgen-pll.c | 34 +-- drivers/clk/sunxi/clk-a10-hosc.c | 2 +- drivers/clk/sunxi/clk-a20-gmac.c | 2 +- drivers/clk/sunxi/clk-factors.c | 4 +- drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 2 +- drivers/clk/sunxi/clk-sun6i-apb0.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 6 +- drivers/clk/sunxi/clk-sun8i-apb0.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 18 +- drivers/clk/tegra/clk-audio-sync.c | 4 +- drivers/clk/tegra/clk-divider.c | 4 +- drivers/clk/tegra/clk-periph-gate.c | 4 +- drivers/clk/tegra/clk-periph.c | 8 +- drivers/clk/tegra/clk-pll-out.c | 4 +- drivers/clk/tegra/clk-pll.c | 40 +-- drivers/clk/tegra/clk-super.c | 4 +- drivers/clk/tegra/clk-tegra-audio.c | 4 +- drivers/clk/tegra/clk-tegra-fixed.c | 8 +- drivers/clk/tegra/clk-tegra-periph.c | 12 +- drivers/clk/tegra/clk-tegra-pmc.c | 4 +- drivers/clk/tegra/clk-tegra-super-gen4.c | 8 +- drivers/clk/tegra/clk-tegra114.c | 10 +- drivers/clk/tegra/clk-tegra124.c | 6 +- drivers/clk/tegra/clk-tegra20.c | 12 +- drivers/clk/tegra/clk-tegra30.c | 8 +- drivers/clk/tegra/clk.c | 24 +- drivers/clk/tegra/clk.h | 38 +-- drivers/clk/ti/apll.c | 8 +- drivers/clk/ti/clk-2xxx.c | 8 +- drivers/clk/ti/clk-33xx.c | 18 +- drivers/clk/ti/clk-3xxx.c | 8 +- drivers/clk/ti/clk-43xx.c | 8 +- drivers/clk/ti/clk-44xx.c | 16 +- drivers/clk/ti/clk-54xx.c | 25 +- drivers/clk/ti/clk-7xx.c | 28 +- drivers/clk/ti/clk-dra7-atl.c | 6 +- drivers/clk/ti/clk.c | 2 +- drivers/clk/ti/clockdomain.c | 4 +- drivers/clk/ti/composite.c | 2 +- drivers/clk/ti/divider.c | 6 +- drivers/clk/ti/dpll.c | 8 +- drivers/clk/ti/fixed-factor.c | 2 +- drivers/clk/ti/gate.c | 2 +- drivers/clk/ti/interface.c | 2 +- drivers/clk/ti/mux.c | 6 +- drivers/clk/ux500/abx500-clk.c | 2 +- drivers/clk/ux500/clk-prcc.c | 8 +- drivers/clk/ux500/clk-prcmu.c | 16 +- drivers/clk/ux500/clk-sysctrl.c | 10 +- drivers/clk/ux500/clk.h | 22 +- drivers/clk/ux500/u8500_clk.c | 2 +- drivers/clk/ux500/u8500_of_clk.c | 12 +- drivers/clk/ux500/u8540_clk.c | 2 +- drivers/clk/versatile/clk-icst.c | 4 +- drivers/clk/versatile/clk-icst.h | 2 +- drivers/clk/versatile/clk-impd1.c | 18 +- drivers/clk/versatile/clk-realview.c | 2 +- drivers/clk/versatile/clk-sp810.c | 30 ++- drivers/clk/versatile/clk-versatile.c | 2 +- drivers/clk/versatile/clk-vexpress-osc.c | 2 +- drivers/clk/versatile/clk-vexpress.c | 6 +- drivers/clk/x86/clk-lpt.c | 2 +- drivers/clk/zynq/clkc.c | 22 +- drivers/clk/zynq/pll.c | 4 +- drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 2 +- drivers/media/platform/exynos4-is/media-dev.c | 16 +- drivers/media/platform/exynos4-is/media-dev.h | 6 +- drivers/staging/imx-drm/imx-tve.c | 26 +- include/asm-generic/clkdev.h | 4 +- include/linux/clk/ti.h | 10 +- include/linux/clk/zynq.h | 2 +- include/linux/platform_data/si5351.h | 4 +- 246 files changed, 1433 insertions(+), 1381 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 0d1a892..4d95685 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -71,9 +71,9 @@ void __init dove_map_io(void) static int dove_tclk; static DEFINE_SPINLOCK(gating_lock); -static struct clk *tclk; +static struct clk_core *tclk; -static struct clk __init *dove_register_gate(const char *name, +static struct clk_core __init *dove_register_gate(const char *name, const char *parent, u8 bit_idx) { return clk_register_gate(NULL, name, parent, 0, @@ -83,9 +83,9 @@ static struct clk __init *dove_register_gate(const char *name, static void __init dove_clk_init(void) { - struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; - struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; - struct clk *xor0, *xor1, *ge, *gephy; + struct clk_core *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; + struct clk_core *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; + struct clk_core *xor0, *xor1, *ge, *gephy; tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, dove_tclk); diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c index 4bb1bc4..e4161ed 100644 --- a/arch/arm/mach-imx/clk-busy.c +++ b/arch/arm/mach-imx/clk-busy.c @@ -78,12 +78,12 @@ static struct clk_ops clk_busy_divider_ops = { .set_rate = clk_busy_divider_set_rate, }; -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift) { struct clk_busy_divider *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); @@ -152,12 +152,12 @@ static struct clk_ops clk_busy_mux_ops = { .set_parent = clk_busy_mux_set_parent, }; -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents) { struct clk_busy_mux *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c index 21db020..8a62bfd 100644 --- a/arch/arm/mach-imx/clk-fixup-div.c +++ b/arch/arm/mach-imx/clk-fixup-div.c @@ -92,12 +92,12 @@ static const struct clk_ops clk_fixup_div_ops = { .set_rate = clk_fixup_div_set_rate, }; -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)) { struct clk_fixup_div *fixup_div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c index 0d40b35..e29dc62 100644 --- a/arch/arm/mach-imx/clk-fixup-mux.c +++ b/arch/arm/mach-imx/clk-fixup-mux.c @@ -71,12 +71,12 @@ static const struct clk_ops clk_fixup_mux_ops = { .set_parent = clk_fixup_mux_set_parent, }; -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)) { struct clk_fixup_mux *fixup_mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 84acdfd..d78f409 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -108,14 +108,14 @@ static struct clk_ops clk_gate2_ops = { .is_enabled = clk_gate2_is_enabled, }; -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) { struct clk_gate2 *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 37c307a..4802cb4 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -32,7 +32,7 @@ static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", }; static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem", "fclk", }; -static struct clk *clk[IMX1_CLK_MAX]; +static struct clk_core *clk[IMX1_CLK_MAX]; static struct clk_onecell_data clk_data; static void __iomem *ccm __initdata; diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index 4b4c753..58b3109 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -36,7 +36,7 @@ static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", }; -static struct clk *clk[IMX21_CLK_MAX]; +static struct clk_core *clk[IMX21_CLK_MAX]; static struct clk_onecell_data clk_data; static void __init _mx21_clocks_init(unsigned long lref, unsigned long href) diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 59c0c85..a80c11e 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -87,7 +87,7 @@ enum mx25_clks { wdt_ipg, cko_div, cko_sel, cko, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static int __init __mx25_clocks_init(unsigned long osc_rate, void __iomem *ccm_base) @@ -225,16 +225,16 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, imx_check_clocks(clk, ARRAY_SIZE(clk)); - clk_prepare_enable(clk[emi_ahb]); + clk_provider_prepare_enable(clk[emi_ahb]); /* Clock source for gpt must be derived from AHB */ - clk_set_parent(clk[per5_sel], clk[ahb]); + clk_provider_set_parent(clk[per5_sel], clk[ahb]); /* * Let's initially set up CLKO parent as ipg, since this configuration * is used on some imx25 board designs to clock the audio codec. */ - clk_set_parent(clk[cko_sel], clk[ipg]); + clk_provider_set_parent(clk[cko_sel], clk[ipg]); return 0; } diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index ab6349e..b0b7f06 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -39,7 +39,7 @@ static const char *clko_sel_clks[] = { static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; -static struct clk *clk[IMX27_CLK_MAX]; +static struct clk_core *clk[IMX27_CLK_MAX]; static struct clk_onecell_data clk_data; static void __init _mx27_clocks_init(unsigned long fref) @@ -156,7 +156,7 @@ static void __init _mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); - clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); + clk_provider_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); imx_print_silicon_rev("i.MX27", mx27_revision()); } diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index 286ef42..355d253 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -45,7 +45,7 @@ enum mx31_clks { gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; int __init mx31_clocks_init(unsigned long fref) @@ -176,11 +176,11 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); clk_register_clkdev(clk[iim_gate], "iim", NULL); - clk_set_parent(clk[csi], clk[upll]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[iim_gate]); + clk_provider_set_parent(clk[csi], clk[upll]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[iim_gate]); mx31_revision(); - clk_disable_unprepare(clk[iim_gate]); + clk_provider_disable_unprepare(clk[iim_gate]); mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index a0d2b57..8eeb563 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -67,7 +67,7 @@ enum mx35_clks { gpu2d_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; int __init mx35_clocks_init(void) { @@ -99,7 +99,7 @@ int __init mx35_clocks_init(void) else clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); - if (clk_get_rate(clk[arm]) > 400000000) + if (clk_provider_get_rate(clk[arm]) > 400000000) hsp_div = hsp_div_532; else hsp_div = hsp_div_400; @@ -257,14 +257,14 @@ int __init mx35_clocks_init(void) clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); clk_register_clkdev(clk[admux_gate], "audmux", NULL); - clk_prepare_enable(clk[spba_gate]); - clk_prepare_enable(clk[gpio1_gate]); - clk_prepare_enable(clk[gpio2_gate]); - clk_prepare_enable(clk[gpio3_gate]); - clk_prepare_enable(clk[iim_gate]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[max_gate]); - clk_prepare_enable(clk[iomuxc_gate]); + clk_provider_prepare_enable(clk[spba_gate]); + clk_provider_prepare_enable(clk[gpio1_gate]); + clk_provider_prepare_enable(clk[gpio2_gate]); + clk_provider_prepare_enable(clk[gpio3_gate]); + clk_provider_prepare_enable(clk[iim_gate]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[max_gate]); + clk_provider_prepare_enable(clk[iomuxc_gate]); /* * SCC is needed to boot via mmc after a watchdog reset. The clock code @@ -272,7 +272,7 @@ int __init mx35_clocks_init(void) * handled here and not needed for mmc) and IIM (which is enabled * unconditionally above). */ - clk_prepare_enable(clk[scc_gate]); + clk_provider_prepare_enable(clk[scc_gate]); imx_print_silicon_rev("i.MX35", mx35_revision()); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 72d6521..47cc37c 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -126,7 +126,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_ static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; -static struct clk *clk[IMX5_CLK_END]; +static struct clk_core *clk[IMX5_CLK_END]; static struct clk_onecell_data clk_data; static void __init mx5_clocks_common_init(void __iomem *ccm_base) @@ -289,26 +289,28 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); /* Set SDHC parents to be PLL2 */ - clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); - clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], + clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], + clk[IMX5_CLK_PLL2_SW]); /* move usb phy clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); - - clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); - clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_SPBA]); - clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); - clk_prepare_enable(clk[IMX5_CLK_TMAX1]); - clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ - clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ + clk_provider_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); + + clk_provider_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); + clk_provider_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_SPBA]); + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX1]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ } static void __init mx50_clocks_init(struct device_node *np) @@ -361,15 +363,15 @@ static void __init mx50_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); } CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); @@ -435,15 +437,16 @@ static void __init mx51_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* set the usboh3 parent to pll2_sw */ - clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_USBOH3_SEL], + clk[IMX5_CLK_PLL2_SW]); /* set SDHC root clock to 166.25MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX51", mx51_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); /* * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no @@ -545,17 +548,17 @@ static void __init mx53_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); /* move can bus clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); + clk_provider_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX53", mx53_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); } CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 2edcebf..5a73164 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -74,7 +74,7 @@ static const char *lvds_sels[] = { "pcie_ref_125m", "sata_ref_100m", }; -static struct clk *clk[IMX6QDL_CLK_END]; +static struct clk_core *clk[IMX6QDL_CLK_END]; static struct clk_onecell_data clk_data; static unsigned int const clks_init_on[] __initconst = { @@ -415,50 +415,65 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); } - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], + clk[IMX6QDL_CLK_IPU1_DI0_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], + clk[IMX6QDL_CLK_IPU1_DI1_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], + clk[IMX6QDL_CLK_IPU2_DI0_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], + clk[IMX6QDL_CLK_IPU2_DI1_PRE]); /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, * We can not get the 100MHz from the pll2_pfd0_352m. * So choose pll2_pfd2_396m as enfc_sel's parent. */ - clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); + clk_provider_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], + clk[IMX6QDL_CLK_PLL2_PFD2_396M]); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); + clk_provider_prepare_enable(clk[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); } /* * Let's initially set up CLKO with OSC24M, since this configuration * is widely used by imx6q board designs to clock audio codec. */ - ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); + ret = clk_provider_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], + clk[IMX6QDL_CLK_OSC]); if (!ret) - ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); + ret = clk_provider_set_parent(clk[IMX6QDL_CLK_CKO], + clk[IMX6QDL_CLK_CKO2]); if (ret) pr_warn("failed to set up CLKO: %d\n", ret); /* Audio-related clocks configuration */ - clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); + clk_provider_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], + clk[IMX6QDL_CLK_PLL3_PFD3_454M]); /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) - clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); + clk_provider_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], + clk[IMX6QDL_CLK_SATA_REF_100M]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index 11908e8..0e7508f 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -80,7 +80,7 @@ static struct clk_div_table video_div_table[] = { { } }; -static struct clk *clks[IMX6SL_CLK_END]; +static struct clk_core *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; static void __iomem *ccm_base; static void __iomem *anatop_base; @@ -356,7 +356,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* Ensure the AHB clk is at 132MHz. */ - ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); + ret = clk_provider_set_rate(clks[IMX6SL_CLK_AHB], 132000000); if (ret) pr_warn("%s: failed to set AHB clock rate %d!\n", __func__, ret); @@ -366,22 +366,23 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) * usecount and enabling/disabling of parent PLLs. */ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); } /* Audio-related clocks configuration */ - clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + clk_provider_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], + clks[IMX6SL_CLK_PLL3_PFD3]); /* set PLL5 video as lcdif pix parent clock */ - clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], - clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], + clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], - clks[IMX6SL_CLK_PLL2_PFD2]); + clk_provider_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], + clks[IMX6SL_CLK_PLL2_PFD2]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index ecde72b..c5de9c1 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -82,7 +82,7 @@ static const char *lvds_sels[] = { "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", }; -static struct clk *clks[IMX6SX_CLK_CLK_END]; +static struct clk_core *clks[IMX6SX_CLK_CLK_END]; static struct clk_onecell_data clk_data; static int const clks_init_on[] __initconst = { @@ -136,12 +136,14 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); - clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); + clks[IMX6SX_CLK_CKIL] = of_clk_provider_get_by_name(ccm_node, "ckil"); + clks[IMX6SX_CLK_OSC] = of_clk_provider_get_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); - clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); + clks[IMX6SX_CLK_IPP_DI0] = of_clk_provider_get_by_name(ccm_node, + "ipp_di0"); + clks[IMX6SX_CLK_IPP_DI1] = of_clk_provider_get_by_name(ccm_node, + "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); base = of_iomap(np, 0); @@ -453,65 +455,80 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); } /* Set the default 132MHz for EIM module */ - clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); + clk_provider_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); /* set parent clock for LCDIF1 pixel clock */ - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], + clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], + clks[IMX6SX_CLK_LCDIF1_PODF]); /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ - if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) pr_err("Failed to set pcie bus parent clk.\n"); - if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) pr_err("Failed to set pcie parent clk.\n"); /* * Init enet system AHB clock, set to 200Mhz * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB */ - clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]); - clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); - clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); - clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_SEL], + clks[IMX6SX_CLK_ENET_PODF]); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); /* Audio clocks */ - clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); - - clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); - - clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); - clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); - - clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); - - clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); + + clk_provider_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SSI1_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI2_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI3_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); + + clk_provider_set_parent(clks[IMX6SX_CLK_ESAI_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); /* Set parent clock for vadc */ - clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_parent(clks[IMX6SX_CLK_VID_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); /* default parent of can_sel clock is invalid, manually set it here */ - clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); + clk_provider_set_parent(clks[IMX6SX_CLK_CAN_SEL], + clks[IMX6SX_CLK_PLL3_60M]); /* Update gpu clock from default 528M to 720M */ - clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); - clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c index 0b0f6f6..8f7590a 100644 --- a/arch/arm/mach-imx/clk-pfd.c +++ b/arch/arm/mach-imx/clk-pfd.c @@ -128,11 +128,11 @@ static const struct clk_ops clk_pfd_ops = { .is_enabled = clk_pfd_is_enabled, }; -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_pfd *pfd; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index d21d14c..fbe33f3 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -97,11 +97,11 @@ static struct clk_ops clk_pllv1_ops = { .recalc_rate = clk_pllv1_recalc_rate, }; -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base) { struct clk_pllv1 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kmalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c index 20889d5..7882848 100644 --- a/arch/arm/mach-imx/clk-pllv2.c +++ b/arch/arm/mach-imx/clk-pllv2.c @@ -237,11 +237,11 @@ static struct clk_ops clk_pllv2_ops = { .set_rate = clk_pllv2_set_rate, }; -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base) { struct clk_pllv2 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index 6136405..3edcfdc 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -320,13 +320,13 @@ static const struct clk_ops clk_pllv3_enet_ops = { .recalc_rate = clk_pllv3_enet_recalc_rate, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) { struct clk_pllv3 *pll; const struct clk_ops *ops; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index a178184..edab0e6 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -97,7 +97,7 @@ static struct clk_div_table pll4_main_div_table[] = { { } }; -static struct clk *clk[VF610_CLK_END]; +static struct clk_core *clk[VF610_CLK_END]; static struct clk_onecell_data clk_data; static unsigned int const clks_init_on[] __initconst = { @@ -321,23 +321,35 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) imx_check_clocks(clk, ARRAY_SIZE(clk)); - clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_QSPI0_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_QSPI1_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_SAI0_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI1_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI2_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI3_SEL], + clk[VF610_CLK_AUDIO_EXT]); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); + clk_provider_prepare_enable(clk[clks_init_on[i]]); /* Add the clocks to provider list */ clk_data.clks = clk; diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index df12b53..10a681e 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c @@ -7,7 +7,7 @@ DEFINE_SPINLOCK(imx_ccm_lock); -void __init imx_check_clocks(struct clk *clks[], unsigned int count) +void __init imx_check_clocks(struct clk_core *clks[], unsigned int count) { unsigned i; @@ -17,10 +17,10 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count) i, PTR_ERR(clks[i])); } -static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) +static struct clk_core * __init imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; - struct clk *clk = ERR_PTR(-ENODEV); + struct clk_core *clk = ERR_PTR(-ENODEV); char *path; path = kasprintf(GFP_KERNEL, "/clocks/%s", name); @@ -37,10 +37,10 @@ static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) return clk; } -struct clk * __init imx_obtain_fixed_clock( +struct clk_core * __init imx_obtain_fixed_clock( const char *name, unsigned long rate) { - struct clk *clk; + struct clk_core *clk; clk = imx_obtain_fixed_clock_from_dt(name); if (IS_ERR(clk)) diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index d5ba76f..0926889 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -6,14 +6,14 @@ extern spinlock_t imx_ccm_lock; -void imx_check_clocks(struct clk *clks[], unsigned int count); +void imx_check_clocks(struct clk_core *clks[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base); enum imx_pllv3_type { @@ -24,26 +24,26 @@ enum imx_pllv3_type { IMX_PLLV3_ENET, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); -struct clk * imx_obtain_fixed_clock( +struct clk_core * imx_obtain_fixed_clock( const char *name, unsigned long rate); -static inline struct clk *imx_clk_gate2(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock, NULL); } -static inline struct clk *imx_clk_gate2_shared(const char *name, +static inline struct clk_core *imx_clk_gate2_shared(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) { @@ -51,38 +51,38 @@ static inline struct clk *imx_clk_gate2_shared(const char *name, shift, 0, &imx_ccm_lock, share_count); } -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift); -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents); -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)); -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)); -static inline struct clk *imx_clk_fixed(const char *name, int rate) +static inline struct clk_core *imx_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *imx_clk_divider(const char *name, const char *parent, +static inline struct clk_core *imx_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_divider_flags(const char *name, +static inline struct clk_core *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) { @@ -90,21 +90,21 @@ static inline struct clk *imx_clk_divider_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_gate(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate_dis(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { return clk_register_mux(NULL, name, parents, num_parents, @@ -112,7 +112,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux_flags(const char *name, +static inline struct clk_core *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, unsigned long flags) { @@ -121,7 +121,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } -static inline struct clk *imx_clk_fixed_factor(const char *name, +static inline struct clk_core *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent, diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index 9a80449..14352c4 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -132,7 +132,7 @@ static int msm_clock_pcom_probe(struct platform_device *pdev) for (i = 0; i < pdata->num_lookups; i++) { const struct clk_pcom_desc *desc = &pdata->lookup[i]; - struct clk *c; + struct clk_core *c; struct clk_pcom *p; struct clk_hw *hw; struct clk_init_data init; diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index e6ac679..fee2643 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -164,7 +164,7 @@ void __init mv78xx0_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; static void __init clk_init(void) { diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index eb8c75e..b593f2b 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -107,7 +107,7 @@ static struct dpll_data dpll3_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll3_ck; +static struct clk_core dpll3_ck; static const char *dpll3_ck_parent_names[] = { "sys_ck", @@ -137,7 +137,7 @@ DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll3_m2_ck", @@ -158,7 +158,7 @@ DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0, OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk security_l4_ick2; +static struct clk_core security_l4_ick2; static const char *security_l4_ick2_parent_names[] = { "l4_ick", @@ -167,7 +167,7 @@ static const char *security_l4_ick2_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL); DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops); -static struct clk aes1_ick; +static struct clk_core aes1_ick; static const char *aes1_ick_parent_names[] = { "security_l4_ick2", @@ -190,7 +190,7 @@ static struct clk_hw_omap aes1_ick_hw = { DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk core_l4_ick; +static struct clk_core core_l4_ick; static const struct clk_ops core_l4_ick_ops = { .init = &omap2_init_clk_clkdm, @@ -199,7 +199,7 @@ static const struct clk_ops core_l4_ick_ops = { DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk aes2_ick; +static struct clk_core aes2_ick; static const char *aes2_ick_parent_names[] = { "core_l4_ick", @@ -224,7 +224,7 @@ static struct clk_hw_omap aes2_ick_hw = { DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk dpll1_fck; +static struct clk_core dpll1_fck; static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -248,7 +248,7 @@ static struct dpll_data dpll1_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll1_ck; +static struct clk_core dpll1_ck; static const struct clk_ops dpll1_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -279,7 +279,7 @@ DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0, OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_ck; +static struct clk_core mpu_ck; static const char *mpu_ck_parent_names[] = { "dpll1_x2m2_ck", @@ -293,7 +293,7 @@ DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0, OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH, 0x0, NULL); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -358,7 +358,7 @@ static struct dpll_data dpll4_dd_3630 __initdata = { .flags = DPLL_J_TYPE }; -static struct clk dpll4_ck; +static struct clk_core dpll4_ck; static const struct clk_ops dpll4_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -422,7 +422,7 @@ DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m5x2_ck; +static struct clk_core dpll4_m5x2_ck; static const char *dpll4_m5x2_ck_parent_names[] = { "dpll4_m5_ck", @@ -459,7 +459,7 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m5x2_ck_3630 = { +static struct clk_core dpll4_m5x2_ck_3630 = { .name = "dpll4_m5x2_ck", .hw = &dpll4_m5x2_ck_hw.hw, .parent_names = dpll4_m5x2_ck_parent_names, @@ -468,7 +468,7 @@ static struct clk dpll4_m5x2_ck_3630 = { .flags = CLK_SET_RATE_PARENT, }; -static struct clk cam_mclk; +static struct clk_core cam_mclk; static const char *cam_mclk_parent_names[] = { "dpll4_m5x2_ck", @@ -483,7 +483,7 @@ static struct clk_hw_omap cam_mclk_hw = { .clkdm_name = "cam_clkdm", }; -static struct clk cam_mclk = { +static struct clk_core cam_mclk = { .name = "cam_mclk", .hw = &cam_mclk_hw.hw, .parent_names = cam_mclk_parent_names, @@ -512,7 +512,7 @@ DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m2x2_ck; +static struct clk_core dpll4_m2x2_ck; static const char *dpll4_m2x2_ck_parent_names[] = { "dpll4_m2_ck", @@ -531,7 +531,7 @@ static struct clk_hw_omap dpll4_m2x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m2x2_ck_3630 = { +static struct clk_core dpll4_m2x2_ck_3630 = { .name = "dpll4_m2x2_ck", .hw = &dpll4_m2x2_ck_hw.hw, .parent_names = dpll4_m2x2_ck_parent_names, @@ -539,7 +539,7 @@ static struct clk dpll4_m2x2_ck_3630 = { .ops = &dpll4_m5x2_ck_3630_ops, }; -static struct clk omap_96m_alwon_fck; +static struct clk_core omap_96m_alwon_fck; static const char *omap_96m_alwon_fck_parent_names[] = { "dpll4_m2x2_ck", @@ -549,7 +549,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk cm_96m_fck; +static struct clk_core cm_96m_fck; static const char *cm_96m_fck_parent_names[] = { "omap_96m_alwon_fck", @@ -568,7 +568,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m3x2_ck; +static struct clk_core dpll4_m3x2_ck; static const char *dpll4_m3x2_ck_parent_names[] = { "dpll4_m3_ck", @@ -587,7 +587,7 @@ static struct clk_hw_omap dpll4_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m3x2_ck_3630 = { +static struct clk_core dpll4_m3x2_ck_3630 = { .name = "dpll4_m3x2_ck", .hw = &dpll4_m3x2_ck_hw.hw, .parent_names = dpll4_m3x2_ck_parent_names, @@ -651,7 +651,7 @@ static const char *omap_48m_fck_parent_names[] = { "cm_96m_fck", "sys_altclk", }; -static struct clk omap_48m_fck; +static struct clk_core omap_48m_fck; static const struct clk_ops omap_48m_fck_ops = { .recalc_rate = &omap2_clksel_recalc, @@ -672,7 +672,7 @@ DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops); DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4); -static struct clk core_12m_fck; +static struct clk_core core_12m_fck; static const char *core_12m_fck_parent_names[] = { "omap_12m_fck", @@ -681,7 +681,7 @@ static const char *core_12m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops); -static struct clk core_48m_fck; +static struct clk_core core_48m_fck; static const char *core_48m_fck_parent_names[] = { "omap_48m_fck", @@ -698,7 +698,7 @@ DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL); -static struct clk core_96m_fck; +static struct clk_core core_96m_fck; static const char *core_96m_fck_parent_names[] = { "omap_96m_fck", @@ -707,7 +707,7 @@ static const char *core_96m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops); -static struct clk core_l3_ick; +static struct clk_core core_l3_ick; static const char *core_l3_ick_parent_names[] = { "l3_ick", @@ -718,7 +718,7 @@ DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops); DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1); -static struct clk corex2_fck; +static struct clk_core corex2_fck; static const char *corex2_fck_parent_names[] = { "dpll3_m2x2_ck", @@ -727,7 +727,7 @@ static const char *corex2_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL); DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops); -static struct clk cpefuse_fck; +static struct clk_core cpefuse_fck; static struct clk_hw_omap cpefuse_fck_hw = { .hw = { @@ -740,7 +740,7 @@ static struct clk_hw_omap cpefuse_fck_hw = { DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk csi2_96m_fck; +static struct clk_core csi2_96m_fck; static const char *csi2_96m_fck_parent_names[] = { "core_96m_fck", @@ -757,7 +757,7 @@ static struct clk_hw_omap csi2_96m_fck_hw = { DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk d2d_26m_fck; +static struct clk_core d2d_26m_fck; static struct clk_hw_omap d2d_26m_fck_hw = { .hw = { @@ -771,7 +771,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = { DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk des1_ick; +static struct clk_core des1_ick; static struct clk_hw_omap des1_ick_hw = { .hw = { @@ -784,7 +784,7 @@ static struct clk_hw_omap des1_ick_hw = { DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk des2_ick; +static struct clk_core des2_ick; static struct clk_hw_omap des2_ick_hw = { .hw = { @@ -803,7 +803,7 @@ DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0, OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll2_fck; +static struct clk_core dpll2_fck; static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -828,7 +828,7 @@ static struct dpll_data dpll2_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll2_ck; +static struct clk_core dpll2_ck; static struct clk_hw_omap dpll2_ck_hw = { .hw = { @@ -857,7 +857,7 @@ DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll3_m3x2_ck; +static struct clk_core dpll3_m3x2_ck; static const char *dpll3_m3x2_ck_parent_names[] = { "dpll3_m3_ck", @@ -876,7 +876,7 @@ static struct clk_hw_omap dpll3_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll3_m3x2_ck_3630 = { +static struct clk_core dpll3_m3x2_ck_3630 = { .name = "dpll3_m3x2_ck", .hw = &dpll3_m3x2_ck_hw.hw, .parent_names = dpll3_m3x2_ck_parent_names, @@ -891,7 +891,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m4x2_ck; +static struct clk_core dpll4_m4x2_ck; static const char *dpll4_m4x2_ck_parent_names[] = { "dpll4_m4_ck", @@ -911,7 +911,7 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m4x2_ck_3630 = { +static struct clk_core dpll4_m4x2_ck_3630 = { .name = "dpll4_m4x2_ck", .hw = &dpll4_m4x2_ck_hw.hw, .parent_names = dpll4_m4x2_ck_parent_names, @@ -925,7 +925,7 @@ DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m6x2_ck; +static struct clk_core dpll4_m6x2_ck; static const char *dpll4_m6x2_ck_parent_names[] = { "dpll4_m6_ck", @@ -944,7 +944,7 @@ static struct clk_hw_omap dpll4_m6x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m6x2_ck_3630 = { +static struct clk_core dpll4_m6x2_ck_3630 = { .name = "dpll4_m6x2_ck", .hw = &dpll4_m6x2_ck_hw.hw, .parent_names = dpll4_m6x2_ck_parent_names, @@ -976,7 +976,7 @@ static struct dpll_data dpll5_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll5_ck; +static struct clk_core dpll5_ck; static struct clk_hw_omap dpll5_ck_hw = { .hw = { @@ -994,7 +994,7 @@ DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0, OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dss1_alwon_fck_3430es1; +static struct clk_core dss1_alwon_fck_3430es1; static const char *dss1_alwon_fck_3430es1_parent_names[] = { "dpll4_m4x2_ck", @@ -1013,7 +1013,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss1_alwon_fck_3430es2; +static struct clk_core dss1_alwon_fck_3430es2; static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = { .hw = { @@ -1029,7 +1029,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss2_alwon_fck; +static struct clk_core dss2_alwon_fck; static struct clk_hw_omap dss2_alwon_fck_hw = { .hw = { @@ -1042,7 +1042,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = { DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk dss_96m_fck; +static struct clk_core dss_96m_fck; static struct clk_hw_omap dss_96m_fck_hw = { .hw = { @@ -1055,7 +1055,7 @@ static struct clk_hw_omap dss_96m_fck_hw = { DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es1; +static struct clk_core dss_ick_3430es1; static struct clk_hw_omap dss_ick_3430es1_hw = { .hw = { @@ -1069,7 +1069,7 @@ static struct clk_hw_omap dss_ick_3430es1_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es2; +static struct clk_core dss_ick_3430es2; static struct clk_hw_omap dss_ick_3430es2_hw = { .hw = { @@ -1083,7 +1083,7 @@ static struct clk_hw_omap dss_ick_3430es2_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_tv_fck; +static struct clk_core dss_tv_fck; static const char *dss_tv_fck_parent_names[] = { "omap_54m_fck", @@ -1100,7 +1100,7 @@ static struct clk_hw_omap dss_tv_fck_hw = { DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops); -static struct clk emac_fck; +static struct clk_core emac_fck; static const char *emac_fck_parent_names[] = { "rmii_ck", @@ -1116,7 +1116,7 @@ static struct clk_hw_omap emac_fck_hw = { DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops); -static struct clk ipss_ick; +static struct clk_core ipss_ick; static const char *ipss_ick_parent_names[] = { "core_l3_ick", @@ -1134,7 +1134,7 @@ static struct clk_hw_omap ipss_ick_hw = { DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops); -static struct clk emac_ick; +static struct clk_core emac_ick; static const char *emac_ick_parent_names[] = { "ipss_ick", @@ -1152,7 +1152,7 @@ static struct clk_hw_omap emac_ick_hw = { DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk emu_core_alwon_ck; +static struct clk_core emu_core_alwon_ck; static const char *emu_core_alwon_ck_parent_names[] = { "dpll3_m3x2_ck", @@ -1162,7 +1162,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm"); DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names, core_l4_ick_ops); -static struct clk emu_mpu_alwon_ck; +static struct clk_core emu_mpu_alwon_ck; static const char *emu_mpu_alwon_ck_parent_names[] = { "mpu_ck", @@ -1171,7 +1171,7 @@ static const char *emu_mpu_alwon_ck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL); DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops); -static struct clk emu_per_alwon_ck; +static struct clk_core emu_per_alwon_ck; static const char *emu_per_alwon_ck_parent_names[] = { "dpll4_m6x2_ck", @@ -1222,7 +1222,7 @@ static const struct clk_ops emu_src_ck_ops = { .disable = &omap2_clkops_disable_clkdm, }; -static struct clk emu_src_ck; +static struct clk_core emu_src_ck; static struct clk_hw_omap emu_src_ck_hw = { .hw = { @@ -1241,7 +1241,7 @@ DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -1255,7 +1255,7 @@ static struct clk_hw_omap fac_ick_hw = { DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk fshostusb_fck; +static struct clk_core fshostusb_fck; static const char *fshostusb_fck_parent_names[] = { "core_48m_fck", @@ -1273,7 +1273,7 @@ static struct clk_hw_omap fshostusb_fck_hw = { DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ck; +static struct clk_core gfx_l3_ck; static struct clk_hw_omap gfx_l3_ck_hw = { .hw = { @@ -1292,7 +1292,7 @@ DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0, OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk gfx_cg1_ck; +static struct clk_core gfx_cg1_ck; static const char *gfx_cg1_ck_parent_names[] = { "gfx_l3_fck", @@ -1310,7 +1310,7 @@ static struct clk_hw_omap gfx_cg1_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_cg2_ck; +static struct clk_core gfx_cg2_ck; static struct clk_hw_omap gfx_cg2_ck_hw = { .hw = { @@ -1324,7 +1324,7 @@ static struct clk_hw_omap gfx_cg2_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ick; +static struct clk_core gfx_l3_ick; static const char *gfx_l3_ick_parent_names[] = { "gfx_l3_ck", @@ -1333,7 +1333,7 @@ static const char *gfx_l3_ick_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm"); DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops); -static struct clk wkup_32k_fck; +static struct clk_core wkup_32k_fck; static const char *wkup_32k_fck_parent_names[] = { "omap_32k_fck", @@ -1342,7 +1342,7 @@ static const char *wkup_32k_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio1_dbck; +static struct clk_core gpio1_dbck; static const char *gpio1_dbck_parent_names[] = { "wkup_32k_fck", @@ -1359,12 +1359,12 @@ static struct clk_hw_omap gpio1_dbck_hw = { DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wkup_l4_ick; +static struct clk_core wkup_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops); -static struct clk gpio1_ick; +static struct clk_core gpio1_ick; static const char *gpio1_ick_parent_names[] = { "wkup_l4_ick", @@ -1382,13 +1382,13 @@ static struct clk_hw_omap gpio1_ick_hw = { DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk per_32k_alwon_fck; +static struct clk_core per_32k_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio2_dbck; +static struct clk_core gpio2_dbck; static const char *gpio2_dbck_parent_names[] = { "per_32k_alwon_fck", @@ -1405,12 +1405,12 @@ static struct clk_hw_omap gpio2_dbck_hw = { DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk per_l4_ick; +static struct clk_core per_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm"); DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk gpio2_ick; +static struct clk_core gpio2_ick; static const char *gpio2_ick_parent_names[] = { "per_l4_ick", @@ -1428,7 +1428,7 @@ static struct clk_hw_omap gpio2_ick_hw = { DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio3_dbck; +static struct clk_core gpio3_dbck; static struct clk_hw_omap gpio3_dbck_hw = { .hw = { @@ -1441,7 +1441,7 @@ static struct clk_hw_omap gpio3_dbck_hw = { DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio3_ick; +static struct clk_core gpio3_ick; static struct clk_hw_omap gpio3_ick_hw = { .hw = { @@ -1455,7 +1455,7 @@ static struct clk_hw_omap gpio3_ick_hw = { DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio4_dbck; +static struct clk_core gpio4_dbck; static struct clk_hw_omap gpio4_dbck_hw = { .hw = { @@ -1468,7 +1468,7 @@ static struct clk_hw_omap gpio4_dbck_hw = { DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio4_ick; +static struct clk_core gpio4_ick; static struct clk_hw_omap gpio4_ick_hw = { .hw = { @@ -1482,7 +1482,7 @@ static struct clk_hw_omap gpio4_ick_hw = { DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio5_dbck; +static struct clk_core gpio5_dbck; static struct clk_hw_omap gpio5_dbck_hw = { .hw = { @@ -1495,7 +1495,7 @@ static struct clk_hw_omap gpio5_dbck_hw = { DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio5_ick; +static struct clk_core gpio5_ick; static struct clk_hw_omap gpio5_ick_hw = { .hw = { @@ -1509,7 +1509,7 @@ static struct clk_hw_omap gpio5_ick_hw = { DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio6_dbck; +static struct clk_core gpio6_dbck; static struct clk_hw_omap gpio6_dbck_hw = { .hw = { @@ -1522,7 +1522,7 @@ static struct clk_hw_omap gpio6_dbck_hw = { DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio6_ick; +static struct clk_core gpio6_ick; static struct clk_hw_omap gpio6_ick_hw = { .hw = { @@ -1536,7 +1536,7 @@ static struct clk_hw_omap gpio6_ick_hw = { DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -1565,7 +1565,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -1586,7 +1586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -1600,7 +1600,7 @@ static struct clk_hw_omap gpt11_ick_hw = { DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk gpt12_fck; +static struct clk_core gpt12_fck; static const char *gpt12_fck_parent_names[] = { "secure_32k_fck", @@ -1609,7 +1609,7 @@ static const char *gpt12_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -1630,7 +1630,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -1651,7 +1651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -1672,7 +1672,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -1693,7 +1693,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -1714,7 +1714,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -1735,7 +1735,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -1756,7 +1756,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -1777,7 +1777,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -1798,7 +1798,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -1812,7 +1812,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static const char *hdq_fck_parent_names[] = { "core_12m_fck", @@ -1830,7 +1830,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -1844,7 +1844,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk hecc_ck; +static struct clk_core hecc_ck; static struct clk_hw_omap hecc_ck_hw = { .hw = { @@ -1858,7 +1858,7 @@ static struct clk_hw_omap hecc_ck_hw = { DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_fck_am35xx; +static struct clk_core hsotgusb_fck_am35xx; static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { .hw = { @@ -1871,7 +1871,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es1; +static struct clk_core hsotgusb_ick_3430es1; static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { .hw = { @@ -1885,7 +1885,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es2; +static struct clk_core hsotgusb_ick_3430es2; static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { .hw = { @@ -1899,7 +1899,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_am35xx; +static struct clk_core hsotgusb_ick_am35xx; static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { .hw = { @@ -1913,7 +1913,7 @@ static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops); -static struct clk i2c1_fck; +static struct clk_core i2c1_fck; static struct clk_hw_omap i2c1_fck_hw = { .hw = { @@ -1927,7 +1927,7 @@ static struct clk_hw_omap i2c1_fck_hw = { DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -1941,7 +1941,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c2_fck; +static struct clk_core i2c2_fck; static struct clk_hw_omap i2c2_fck_hw = { .hw = { @@ -1955,7 +1955,7 @@ static struct clk_hw_omap i2c2_fck_hw = { DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -1969,7 +1969,7 @@ static struct clk_hw_omap i2c2_ick_hw = { DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c3_fck; +static struct clk_core i2c3_fck; static struct clk_hw_omap i2c3_fck_hw = { .hw = { @@ -1983,7 +1983,7 @@ static struct clk_hw_omap i2c3_fck_hw = { DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c3_ick; +static struct clk_core i2c3_ick; static struct clk_hw_omap i2c3_ick_hw = { .hw = { @@ -1997,7 +1997,7 @@ static struct clk_hw_omap i2c3_ick_hw = { DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk icr_ick; +static struct clk_core icr_ick; static struct clk_hw_omap icr_ick_hw = { .hw = { @@ -2011,7 +2011,7 @@ static struct clk_hw_omap icr_ick_hw = { DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk iva2_ck; +static struct clk_core iva2_ck; static const char *iva2_ck_parent_names[] = { "dpll2_m2_ck", @@ -2029,7 +2029,7 @@ static struct clk_hw_omap iva2_ck_hw = { DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops); -static struct clk mad2d_ick; +static struct clk_core mad2d_ick; static struct clk_hw_omap mad2d_ick_hw = { .hw = { @@ -2043,7 +2043,7 @@ static struct clk_hw_omap mad2d_ick_hw = { DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -2084,7 +2084,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -2098,7 +2098,7 @@ static struct clk_hw_omap mcbsp1_ick_hw = { DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk per_96m_fck; +static struct clk_core per_96m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops); @@ -2120,7 +2120,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -2141,7 +2141,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp3_ick; +static struct clk_core mcbsp3_ick; static struct clk_hw_omap mcbsp3_ick_hw = { .hw = { @@ -2162,7 +2162,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp4_ick; +static struct clk_core mcbsp4_ick; static struct clk_hw_omap mcbsp4_ick_hw = { .hw = { @@ -2183,7 +2183,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp5_ick; +static struct clk_core mcbsp5_ick; static struct clk_hw_omap mcbsp5_ick_hw = { .hw = { @@ -2197,7 +2197,7 @@ static struct clk_hw_omap mcbsp5_ick_hw = { DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static struct clk_hw_omap mcspi1_fck_hw = { .hw = { @@ -2211,7 +2211,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -2225,7 +2225,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -2239,7 +2239,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -2253,7 +2253,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi3_fck; +static struct clk_core mcspi3_fck; static struct clk_hw_omap mcspi3_fck_hw = { .hw = { @@ -2267,7 +2267,7 @@ static struct clk_hw_omap mcspi3_fck_hw = { DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi3_ick; +static struct clk_core mcspi3_ick; static struct clk_hw_omap mcspi3_ick_hw = { .hw = { @@ -2281,7 +2281,7 @@ static struct clk_hw_omap mcspi3_ick_hw = { DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi4_fck; +static struct clk_core mcspi4_fck; static struct clk_hw_omap mcspi4_fck_hw = { .hw = { @@ -2295,7 +2295,7 @@ static struct clk_hw_omap mcspi4_fck_hw = { DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi4_ick; +static struct clk_core mcspi4_ick; static struct clk_hw_omap mcspi4_ick_hw = { .hw = { @@ -2309,7 +2309,7 @@ static struct clk_hw_omap mcspi4_ick_hw = { DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs1_fck; +static struct clk_core mmchs1_fck; static struct clk_hw_omap mmchs1_fck_hw = { .hw = { @@ -2323,7 +2323,7 @@ static struct clk_hw_omap mmchs1_fck_hw = { DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs1_ick; +static struct clk_core mmchs1_ick; static struct clk_hw_omap mmchs1_ick_hw = { .hw = { @@ -2337,7 +2337,7 @@ static struct clk_hw_omap mmchs1_ick_hw = { DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs2_fck; +static struct clk_core mmchs2_fck; static struct clk_hw_omap mmchs2_fck_hw = { .hw = { @@ -2351,7 +2351,7 @@ static struct clk_hw_omap mmchs2_fck_hw = { DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs2_ick; +static struct clk_core mmchs2_ick; static struct clk_hw_omap mmchs2_ick_hw = { .hw = { @@ -2365,7 +2365,7 @@ static struct clk_hw_omap mmchs2_ick_hw = { DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs3_fck; +static struct clk_core mmchs3_fck; static struct clk_hw_omap mmchs3_fck_hw = { .hw = { @@ -2379,7 +2379,7 @@ static struct clk_hw_omap mmchs3_fck_hw = { DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs3_ick; +static struct clk_core mmchs3_ick; static struct clk_hw_omap mmchs3_ick_hw = { .hw = { @@ -2393,7 +2393,7 @@ static struct clk_hw_omap mmchs3_ick_hw = { DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk modem_fck; +static struct clk_core modem_fck; static struct clk_hw_omap modem_fck_hw = { .hw = { @@ -2407,7 +2407,7 @@ static struct clk_hw_omap modem_fck_hw = { DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -2421,7 +2421,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -2435,13 +2435,13 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk omap_192m_alwon_fck; +static struct clk_core omap_192m_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk omap_32ksync_ick; +static struct clk_core omap_32ksync_ick; static struct clk_hw_omap omap_32ksync_ick_hw = { .hw = { @@ -2466,7 +2466,7 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = { { .parent = NULL } }; -static struct clk omap_96m_alwon_fck_3630; +static struct clk_core omap_96m_alwon_fck_3630; static const char *omap_96m_alwon_fck_3630_parent_names[] = { "omap_192m_alwon_fck", @@ -2487,7 +2487,7 @@ static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = { .clksel_mask = OMAP3630_CLKSEL_96M_MASK, }; -static struct clk omap_96m_alwon_fck_3630 = { +static struct clk_core omap_96m_alwon_fck_3630 = { .name = "omap_96m_alwon_fck", .hw = &omap_96m_alwon_fck_3630_hw.hw, .parent_names = omap_96m_alwon_fck_3630_parent_names, @@ -2495,7 +2495,7 @@ static struct clk omap_96m_alwon_fck_3630 = { .ops = &omap_96m_alwon_fck_3630_ops, }; -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -2520,17 +2520,17 @@ DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk per_48m_fck; +static struct clk_core per_48m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops); -static struct clk security_l3_ick; +static struct clk_core security_l3_ick; DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL); DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static const char *pka_ick_parent_names[] = { "security_l3_ick", @@ -2552,7 +2552,7 @@ DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0, OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -2565,7 +2565,7 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sad2d_ick; +static struct clk_core sad2d_ick; static struct clk_hw_omap sad2d_ick_hw = { .hw = { @@ -2579,7 +2579,7 @@ static struct clk_hw_omap sad2d_ick_hw = { DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -2630,7 +2630,7 @@ static const char *sgx_fck_parent_names[] = { "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck", }; -static struct clk sgx_fck; +static struct clk_core sgx_fck; static const struct clk_ops sgx_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -2651,7 +2651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel, OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops); -static struct clk sgx_ick; +static struct clk_core sgx_ick; static struct clk_hw_omap sgx_ick_hw = { .hw = { @@ -2665,7 +2665,7 @@ static struct clk_hw_omap sgx_ick_hw = { DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sha11_ick; +static struct clk_core sha11_ick; static struct clk_hw_omap sha11_ick_hw = { .hw = { @@ -2678,7 +2678,7 @@ static struct clk_hw_omap sha11_ick_hw = { DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sha12_ick; +static struct clk_core sha12_ick; static struct clk_hw_omap sha12_ick_hw = { .hw = { @@ -2692,7 +2692,7 @@ static struct clk_hw_omap sha12_ick_hw = { DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk sr1_fck; +static struct clk_core sr1_fck; static struct clk_hw_omap sr1_fck_hw = { .hw = { @@ -2706,7 +2706,7 @@ static struct clk_hw_omap sr1_fck_hw = { DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr2_fck; +static struct clk_core sr2_fck; static struct clk_hw_omap sr2_fck_hw = { .hw = { @@ -2720,17 +2720,17 @@ static struct clk_hw_omap sr2_fck_hw = { DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr_l4_ick; +static struct clk_core sr_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_ick_3430es1; +static struct clk_core ssi_ick_3430es1; static const char *ssi_ick_3430es1_parent_names[] = { "ssi_l4_ick", @@ -2748,7 +2748,7 @@ static struct clk_hw_omap ssi_ick_3430es1_hw = { DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops); -static struct clk ssi_ick_3430es2; +static struct clk_core ssi_ick_3430es2; static struct clk_hw_omap ssi_ick_3430es2_hw = { .hw = { @@ -2813,7 +2813,7 @@ DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1", DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2", &ssi_ssr_fck_3430es2, 0x0, 1, 2); -static struct clk sys_clkout1; +static struct clk_core sys_clkout1; static const char *sys_clkout1_parent_names[] = { "osc_sys_ck", @@ -2843,7 +2843,7 @@ DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0, OMAP3430_CLKSEL_TRACECLK_SHIFT, OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk ts_fck; +static struct clk_core ts_fck; static struct clk_hw_omap ts_fck_hw = { .hw = { @@ -2856,7 +2856,7 @@ static struct clk_hw_omap ts_fck_hw = { DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -2870,7 +2870,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -2884,7 +2884,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -2898,7 +2898,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -2912,7 +2912,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static const char *uart3_fck_parent_names[] = { "per_48m_fck", @@ -2930,7 +2930,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -2944,7 +2944,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_fck; +static struct clk_core uart4_fck; static struct clk_hw_omap uart4_fck_hw = { .hw = { @@ -2958,7 +2958,7 @@ static struct clk_hw_omap uart4_fck_hw = { DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart4_fck_am35xx; +static struct clk_core uart4_fck_am35xx; static struct clk_hw_omap uart4_fck_am35xx_hw = { .hw = { @@ -2972,7 +2972,7 @@ static struct clk_hw_omap uart4_fck_am35xx_hw = { DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart4_ick; +static struct clk_core uart4_ick; static struct clk_hw_omap uart4_ick_hw = { .hw = { @@ -2986,7 +2986,7 @@ static struct clk_hw_omap uart4_ick_hw = { DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_ick_am35xx; +static struct clk_core uart4_ick_am35xx; static struct clk_hw_omap uart4_ick_am35xx_hw = { .hw = { @@ -3023,7 +3023,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel, &clkhwops_iclk_wait, usb_l4_ick_parent_names, ssi_ssr_fck_3430es1_ops); -static struct clk usbhost_120m_fck; +static struct clk_core usbhost_120m_fck; static const char *usbhost_120m_fck_parent_names[] = { "dpll5_m2_ck", @@ -3041,7 +3041,7 @@ static struct clk_hw_omap usbhost_120m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_48m_fck; +static struct clk_core usbhost_48m_fck; static struct clk_hw_omap usbhost_48m_fck_hw = { .hw = { @@ -3055,7 +3055,7 @@ static struct clk_hw_omap usbhost_48m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_ick; +static struct clk_core usbhost_ick; static struct clk_hw_omap usbhost_ick_hw = { .hw = { @@ -3069,7 +3069,7 @@ static struct clk_hw_omap usbhost_ick_hw = { DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk usbtll_fck; +static struct clk_core usbtll_fck; static struct clk_hw_omap usbtll_fck_hw = { .hw = { @@ -3083,7 +3083,7 @@ static struct clk_hw_omap usbtll_fck_hw = { DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbtll_ick; +static struct clk_core usbtll_ick; static struct clk_hw_omap usbtll_ick_hw = { .hw = { @@ -3124,7 +3124,7 @@ static const char *usim_fck_parent_names[] = { "omap_96m_fck", "dpll5_m2_ck", "sys_ck", }; -static struct clk usim_fck; +static struct clk_core usim_fck; static const struct clk_ops usim_fck_ops = { .enable = &omap2_dflt_clk_enable, @@ -3142,7 +3142,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel, OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait, usim_fck_parent_names, usim_fck_ops); -static struct clk usim_ick; +static struct clk_core usim_ick; static struct clk_hw_omap usim_ick_hw = { .hw = { @@ -3156,7 +3156,7 @@ static struct clk_hw_omap usim_ick_hw = { DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk vpfe_fck; +static struct clk_core vpfe_fck; static const char *vpfe_fck_parent_names[] = { "pclk_ck", @@ -3172,7 +3172,7 @@ static struct clk_hw_omap vpfe_fck_hw = { DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops); -static struct clk vpfe_ick; +static struct clk_core vpfe_ick; static struct clk_hw_omap vpfe_ick_hw = { .hw = { @@ -3186,12 +3186,12 @@ static struct clk_hw_omap vpfe_ick_hw = { DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk wdt1_fck; +static struct clk_core wdt1_fck; DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -3205,7 +3205,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt2_fck; +static struct clk_core wdt2_fck; static struct clk_hw_omap wdt2_fck_hw = { .hw = { @@ -3219,7 +3219,7 @@ static struct clk_hw_omap wdt2_fck_hw = { DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wdt2_ick; +static struct clk_core wdt2_ick; static struct clk_hw_omap wdt2_ick_hw = { .hw = { @@ -3233,7 +3233,7 @@ static struct clk_hw_omap wdt2_ick_hw = { DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt3_fck; +static struct clk_core wdt3_fck; static struct clk_hw_omap wdt3_fck_hw = { .hw = { @@ -3247,7 +3247,7 @@ static struct clk_hw_omap wdt3_fck_hw = { DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk wdt3_ick; +static struct clk_core wdt3_ick; static struct clk_hw_omap wdt3_ick_hw = { .hw = { @@ -3661,10 +3661,10 @@ int __init omap3xxx_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&osc_sys_ck) / 1000000), - (clk_get_rate(&osc_sys_ck) / 100000) % 10, - (clk_get_rate(&core_ck) / 1000000), - (clk_get_rate(&arm_fck) / 1000000)); + (clk_provider_get_rate(&osc_sys_ck) / 1000000), + (clk_provider_get_rate(&osc_sys_ck) / 100000) % 10, + (clk_provider_get_rate(&core_ck) / 1000000), + (clk_provider_get_rate(&arm_fck) / 1000000)); /* * Lock DPLL5 -- here only until other device init code can @@ -3674,8 +3674,8 @@ int __init omap3xxx_clk_init(void) omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ - sdrc_ick_p = clk_get(NULL, "sdrc_ick"); - arm_fck_p = clk_get(NULL, "arm_fck"); + sdrc_ick_p = clk_provider_get(NULL, "sdrc_ick"); + arm_fck_p = clk_provider_get(NULL, "arm_fck"); return 0; } diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 82572e2..28a6d42 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -22,7 +22,7 @@ /** * _allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. The DPLL will enter low-power * stop when its downstream clocks are gated. No return value. @@ -39,7 +39,7 @@ static void _allow_idle(struct clk_hw_omap *clk) /** * _deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 59cf310..6723d916 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -48,7 +48,7 @@ static struct clk_hw_omap *dpll_core_ck; * Returns the CORE_CLK rate. CORE_CLK can have one of three rate * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz * (the latter is unusual). This currently should be called with - * struct clk *dpll_ck, which is a composite clock of dpll_ck and + * struct clk_core *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ unsigned long omap2xxx_clk_get_core_rate(void) @@ -179,7 +179,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, /** * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck - * @clk: struct clk *dpll_ck + * @clk: struct clk_core *dpll_ck * * Store a local copy of @clk in dpll_core_ck so other code can query * the core rate without having to clk_get(), which can sleep. Must diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 85e0b0c0..67014e1 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -198,14 +198,14 @@ void omap2xxx_clkt_vps_check_bootloader_rates(void) */ void omap2xxx_clkt_vps_late_init(void) { - struct clk *c; + struct clk_core *c; - c = clk_get(NULL, "sys_ck"); + c = clk_provider_get(NULL, "sys_ck"); if (IS_ERR(c)) { WARN(1, "could not locate sys_ck\n"); } else { - sys_ck_rate = clk_get_rate(c); - clk_put(c); + sys_ck_rate = clk_provider_get_rate(c); + __clk_put(c); } } @@ -230,7 +230,7 @@ void omap2xxx_clkt_vps_init(void) { struct clk_init_data init = { NULL }; struct clk_hw_omap *hw = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name = "mpu_ck"; struct clk_lookup *lookup = NULL; diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index eb69acf..9e96363 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -38,7 +38,7 @@ /** * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Program the DPLL M2 divider with the rounded target rate. Returns diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 7ee2610..b4796b3 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -51,15 +51,15 @@ /** * _get_clksel_by_parent() - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for + * @clk: OMAP struct clk_core ptr to inspect + * @src_clk: OMAP struct clk_core ptr of the parent clk to search for * * Scan the struct clksel array associated with the clock to find * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, - struct clk *src_clk) + struct clk_core *src_clk) { const struct clksel *clks; @@ -82,7 +82,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, /** * _write_clksel_reg() - program a clock's clksel register in hardware - * @clk: struct clk * to program + * @clk: struct clk_core * to program * @v: clksel bitfield value to program (with LSB at bit 0) * * Shift the clksel register bitfield value @v to its appropriate @@ -107,10 +107,10 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) /** * _clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @field_val: register field value to find * - * Given a struct clk of a rate-selectable clksel clock, and a register field + * Given a struct clk_core of a rate-selectable clksel clock, and a register field * value to search for, find the corresponding clock divisor. The register * field value should be pre-masked and shifted down so the LSB is at bit 0 * before calling. Returns 0 on error or returns the actual integer divisor @@ -120,7 +120,7 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; parent = __clk_get_parent(clk->hw.clk); @@ -149,10 +149,10 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) /** * _divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @div: integer divisor to search for * - * Given a struct clk of a rate-selectable clksel clock, and a clock + * Given a struct clk_core of a rate-selectable clksel clock, and a clock * divisor, find the corresponding register field value. Returns the * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. @@ -161,7 +161,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; /* should never happen */ WARN_ON(div == 0); @@ -191,7 +191,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) /** * _read_divisor() - get current divisor applied to parent clock (from hdwr) - * @clk: OMAP struct clk to use. + * @clk: OMAP struct clk_core to use. * * Read the current divisor register value for @clk that is programmed * into the hardware, convert it into the actual divisor value, and @@ -215,7 +215,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk) /** * omap2_clksel_round_rate_div() - find divisor for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * @new_div: ptr to where we should store the divisor * @@ -233,7 +233,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, const struct clksel *clks; const struct clksel_rate *clkr; u32 last_div = 0; - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; const char *clk_name; @@ -286,7 +286,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, /* * Clocktype interface functions to the OMAP clock code - * (i.e., those used in struct clk field function pointers, etc.) + * (i.e., those used in struct clk_core field function pointers, etc.) */ /** @@ -309,7 +309,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) const struct clksel *clks; const struct clksel_rate *clkr; u32 r, found = 0; - struct clk *parent; + struct clk_core *parent; const char *clk_name; int ret = 0, f = 0; @@ -345,11 +345,11 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) /** - * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field - * @clk: struct clk * + * omap2_clksel_recalc() - function ptr to pass via struct clk_core .recalc field + * @clk: struct clk_core * * * This function is intended to be called only by the clock framework. - * Each clksel clock should have its struct clk .recalc field set to this + * Each clksel clock should have its struct clk_core .recalc field set to this * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ @@ -376,7 +376,7 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * * This function is intended to be called only by the clock framework. @@ -396,7 +396,7 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, /** * omap2_clksel_set_rate() - program clock rate in hardware - * @clk: struct clk * to program rate + * @clk: struct clk_core * to program rate * @rate: target rate to program * * This function is intended to be called only by the clock framework. @@ -435,7 +435,7 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, } /* - * Clksel parent setting function - not passed in struct clk function + * Clksel parent setting function - not passed in struct clk_core function * pointer - instead, the OMAP clock code currently assumes that any * parent-setting clock is a clksel clock, and calls * omap2_clksel_set_parent() by default @@ -443,8 +443,8 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap2_clksel_set_parent() - change a clock's parent clock - * @clk: struct clk * of the child clock - * @new_parent: struct clk * of the new parent clock + * @clk: struct clk_core * of the child clock + * @new_parent: struct clk_core * of the new parent clock * * This function is intended to be called only by the clock framework. * Change the parent clock of clock @clk to @new_parent. This is diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index f251a14..36f263d 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -56,7 +56,7 @@ /* * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test + * @clk: DPLL struct clk_core to test * @n: divider value (N) to test * * Tests whether a particular divider @n will result in a valid DPLL @@ -215,7 +215,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - /* Reparent the struct clk in case the dpll is in bypass */ + /* Reparent the struct clk_core in case the dpll is in bypass */ if (_omap2_dpll_is_in_bypass(v)) return 1; @@ -224,7 +224,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) /** * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL + * @clk: struct clk_core * of a DPLL * * DPLLs can be locked or bypassed - basically, enabled or disabled. * When locked, the DPLL output depends on the M and N values. When @@ -270,7 +270,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) /** * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL + * @clk: struct clk_core * for a DPLL * @target_rate: desired DPLL clock rate * * Given a DPLL and a desired target rate, round the target rate to a diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 500530d..ab341e4 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -142,7 +142,7 @@ static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, /** * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module + * @clk: struct clk_core * belonging to the module * * If the necessary clocks for the OMAP hardware IP block that * corresponds to clock @clk are enabled, then wait for the module to @@ -181,7 +181,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use * - * Convert a clockdomain name stored in a struct clk 'clk' into a + * Convert a clockdomain name stored in a struct clk_core 'clk' into a * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ @@ -222,7 +222,7 @@ void __init omap2_clk_disable_clkdm_control(void) /** * omap2_clk_dflt_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of + * @clk: struct clk_core * to find the companion clock of * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in * @other_bit: u8 ** to return the companion clock bit shift in * @@ -258,7 +258,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, /** * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk - * @clk: struct clk * to find IDLEST info for + * @clk: struct clk_core * to find IDLEST info for * @idlest_reg: void __iomem ** to return the CM_IDLEST va in * @idlest_bit: u8 * to return the CM_IDLEST bit shift in * @idlest_val: u8 * to return the idle status indicator @@ -502,14 +502,14 @@ __setup("mpurate=", omap_clk_setup); /** * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock - * @clk: struct clk * to initialize + * @clk: struct clk_core * to initialize * * Add an OMAP clock @clk to the internal list of OMAP clocks. Used * temporarily for autoidle handling, until this support can be * integrated into the common clock framework code in some way. No * return value. */ -void omap2_init_clk_hw_omap_clocks(struct clk *clk) +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk) { struct clk_hw_omap *c; @@ -566,11 +566,11 @@ int omap2_clk_disable_autoidle_all(void) /** * omap2_clk_deny_idle - disable autoidle on an OMAP clock - * @clk: struct clk * to disable autoidle for + * @clk: struct clk_core * to disable autoidle for * * Disable autoidle on an OMAP clock. */ -int omap2_clk_deny_idle(struct clk *clk) +int omap2_clk_deny_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -585,11 +585,11 @@ int omap2_clk_deny_idle(struct clk *clk) /** * omap2_clk_allow_idle - enable autoidle on an OMAP clock - * @clk: struct clk * to enable autoidle for + * @clk: struct clk_core * to enable autoidle for * * Enable autoidle on an OMAP clock. */ -int omap2_clk_allow_idle(struct clk *clk) +int omap2_clk_allow_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -614,12 +614,12 @@ int omap2_clk_allow_idle(struct clk *clk) */ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) { - struct clk *init_clk; + struct clk_core *init_clk; int i; for (i = 0; i < num_clocks; i++) { - init_clk = clk_get(NULL, clk_names[i]); - clk_prepare_enable(init_clk); + init_clk = clk_provider_get(NULL, clk_names[i]); + clk_provider_prepare_enable(init_clk); } } @@ -655,31 +655,31 @@ void __init omap_clocks_register(struct omap_clk oclks[], int cnt) * the OPP layer. XXX This is intended to be handled by the OPP layer * code in the near future and should be removed from the clock code. * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects - * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name + * the rate, -ENOENT if the struct clk_core referred to by @mpurate_ck_name * cannot be found, or 0 upon success. */ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) { - struct clk *mpurate_ck; + struct clk_core *mpurate_ck; int r; if (!mpurate) return -EINVAL; - mpurate_ck = clk_get(NULL, mpurate_ck_name); + mpurate_ck = clk_provider_get(NULL, mpurate_ck_name); if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) return -ENOENT; - r = clk_set_rate(mpurate_ck, mpurate); + r = clk_provider_set_rate(mpurate_ck, mpurate); if (r < 0) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", mpurate_ck_name, mpurate, r); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return 0; } @@ -700,27 +700,27 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name) { - struct clk *hfclkin_ck, *core_ck, *mpu_ck; + struct clk_core *hfclkin_ck, *core_ck, *mpu_ck; unsigned long hfclkin_rate; - mpu_ck = clk_get(NULL, mpu_ck_name); + mpu_ck = clk_provider_get(NULL, mpu_ck_name); if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) return; - core_ck = clk_get(NULL, core_ck_name); + core_ck = clk_provider_get(NULL, core_ck_name); if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) return; - hfclkin_ck = clk_get(NULL, hfclkin_ck_name); + hfclkin_ck = clk_provider_get(NULL, hfclkin_ck_name); if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) return; - hfclkin_rate = clk_get_rate(hfclkin_ck); + hfclkin_rate = clk_provider_get_rate(hfclkin_ck); pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), - (clk_get_rate(core_ck) / 1000000), - (clk_get_rate(mpu_ck) / 1000000)); + (clk_provider_get_rate(core_ck) / 1000000), + (clk_provider_get_rate(mpu_ck) / 1000000)); } /** diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 4592a27..7068684 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -40,7 +40,7 @@ struct omap_clk { struct clockdomain; #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -50,7 +50,7 @@ struct clockdomain; #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ _clkops_name, _flags) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -70,7 +70,7 @@ struct clockdomain; #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ _clksel_reg, _clksel_mask, \ _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -86,7 +86,7 @@ struct clockdomain; _clksel_reg, _clksel_mask, \ _enable_reg, _enable_bit, \ _hwops, _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -142,14 +142,14 @@ struct clksel_rate { /** * struct clksel - available parent clocks, and a pointer to their divisors - * @parent: struct clk * to a possible parent clock + * @parent: struct clk_core * to a possible parent clock * @rates: available divisors for this parent clock * * A struct clksel is always associated with one or more struct clks * and one or more struct clksel_rates. */ struct clksel { - struct clk *parent; + struct clk_core *parent; const struct clksel_rate *rates; }; @@ -208,8 +208,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); int omap2_clk_enable_autoidle_all(void); -int omap2_clk_allow_idle(struct clk *clk); -int omap2_clk_deny_idle(struct clk *clk); +int omap2_clk_allow_idle(struct clk_core *clk); +int omap2_clk_deny_idle(struct clk_core *clk); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -247,7 +247,7 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; -extern struct clk dummy_ck; +extern struct clk_core dummy_ck; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 0b02b41..17abc81 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -37,7 +37,7 @@ #define DPLL5_FREQ_FOR_USBHOST 120000000 /* needed by omap3_core_dpll_m2_set_rate() */ -struct clk *sdrc_ick_p, *arm_fck_p; +struct clk_core *sdrc_ick_p, *arm_fck_p; int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -56,20 +56,20 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, void __init omap3_clk_lock_dpll5(void) { - struct clk *dpll5_clk; - struct clk *dpll5_m2_clk; + struct clk_core *dpll5_clk; + struct clk_core *dpll5_m2_clk; - dpll5_clk = clk_get(NULL, "dpll5_ck"); - clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_prepare_enable(dpll5_clk); + dpll5_clk = clk_provider_get(NULL, "dpll5_ck"); + clk_provider_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); + clk_provider_prepare_enable(dpll5_clk); /* Program dpll5_m2_clk divider for no division */ - dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_prepare_enable(dpll5_m2_clk); - clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); + dpll5_m2_clk = clk_provider_get(NULL, "dpll5_m2_ck"); + clk_provider_prepare_enable(dpll5_m2_clk); + clk_provider_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - clk_disable_unprepare(dpll5_m2_clk); - clk_disable_unprepare(dpll5_clk); + clk_provider_disable_unprepare(dpll5_m2_clk); + clk_provider_disable_unprepare(dpll5_clk); return; } diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 78d9f56..063fbf1 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -12,8 +12,8 @@ int omap3xxx_clk_init(void); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); -extern struct clk *sdrc_ick_p; -extern struct clk *arm_fck_p; +extern struct clk_core *sdrc_ick_p; +extern struct clk_core *arm_fck_p; extern const struct clkops clkops_noncore_dpll_ops; diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index ef4d21b..31e3e79 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -119,7 +119,7 @@ const struct clksel_rate div31_1to31_rates[] = { static struct clk_ops dummy_ck_ops = {}; -struct clk dummy_ck = { +struct clk_core dummy_ck = { .name = "dummy_clk", .ops = &dummy_ck_ops, .flags = CLK_IS_BASIC, diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 2da3b5e..ce0971c 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1141,7 +1141,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) /** * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the enabled downstream clock + * @clk: struct clk_core * of the enabled downstream clock * * Increment the usecount of the clockdomain @clkdm and ensure that it * is awake before @clk is enabled. Intended to be called by @@ -1152,7 +1152,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) * by on-chip processors. Returns -EINVAL if passed null pointers; * returns 0 upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk) { /* * XXX Rewrite this code to maintain a list of enabled @@ -1168,7 +1168,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) /** * clkdm_clk_disable - remove an enabled downstream clock from this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the disabled downstream clock + * @clk: struct clk_core * of the disabled downstream clock * * Decrement the usecount of this clockdomain @clkdm when @clk is * disabled. Intended to be called by clk_disable() code. If the @@ -1178,7 +1178,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0 * upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk) { if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 82c37b1..f1a2cad 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -207,8 +207,8 @@ int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep_nolock(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk); +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 0f9e479..94b3232 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -524,7 +524,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_prepare_enable(oc->_clk); + clk_provider_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -551,7 +551,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_disable_unprepare(oc->_clk); + clk_provider_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index ac3d789..dfbead1 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -288,7 +288,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) /* * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @freqsel: FREQSEL value to set * * Program the DPLL with the last M, N values calculated, and wait for @@ -410,7 +410,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw) struct clk_hw_omap *clk = to_clk_hw_omap(hw); int r; struct dpll_data *dd; - struct clk *parent; + struct clk_core *parent; dd = clk->dpll_data; if (!dd) @@ -461,7 +461,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) /** * omap3_noncore_dpll_set_rate - set non-core DPLL rate - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Set the DPLL CLKOUT to the target rate. If the DPLL can enter @@ -474,7 +474,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct clk *new_parent = NULL; + struct clk_core *new_parent = NULL; unsigned long rrate; u16 freqsel = 0; struct dpll_data *dd; @@ -493,15 +493,15 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __func__, __clk_get_name(hw->clk)); __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); + clk_provider_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; - clk_disable(dd->clk_bypass); + clk_provider_disable(dd->clk_bypass); __clk_unprepare(dd->clk_bypass); } else { __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); + clk_provider_enable(dd->clk_ref); /* XXX this check is probably pointless in the CCF context */ if (dd->last_rounded_rate != rate) { @@ -530,7 +530,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; - clk_disable(dd->clk_ref); + clk_provider_disable(dd->clk_ref); __clk_unprepare(dd->clk_ref); } /* @@ -540,7 +540,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, * stuff is inherited for free */ - if (!ret && clk_get_parent(hw->clk) != new_parent) + if (!ret && clk_provider_get_parent(hw->clk) != new_parent) __clk_reparent(hw->clk, new_parent); return 0; @@ -550,10 +550,10 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap3_dpll_autoidle_read - read a DPLL's autoidle bits - * @clk: struct clk * of the DPLL to read + * @clk: struct clk_core * of the DPLL to read * * Return the DPLL's autoidle bits, shifted down to bit 0. Returns - * -EINVAL if passed a null pointer or if the struct clk does not + * -EINVAL if passed a null pointer or if the struct clk_core does not * appear to refer to a DPLL. */ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) @@ -578,7 +578,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) /** * omap3_dpll_allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. This automatic idle mode * switching takes effect only when the DPLL is locked, at least on @@ -612,7 +612,7 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk) /** * omap3_dpll_deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ @@ -642,7 +642,7 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk) static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) { struct clk_hw_omap *pclk = NULL; - struct clk *parent; + struct clk_core *parent; /* Walk up the parents of clk, looking for a DPLL */ do { diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 4613f1e..e6d24a2 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -124,7 +124,7 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to compute the rate for + * @clk: struct clk_core * of the DPLL to compute the rate for * * Compute the output rate for the OMAP4 DPLL represented by @clk. * Takes the REGM4XEN bit into consideration, which is needed for the @@ -156,7 +156,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, /** * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to round a rate for + * @clk: struct clk_core * of the DPLL to round a rate for * @target_rate: the desired rate of the DPLL * * Compute the rate that would be programmed into the DPLL hardware diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index b4ac3af..e7ea6ba 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -34,7 +34,7 @@ #include "cm3xxx.h" #include "cm-regbits-34xx.h" -static struct clk *mcbsp_iclks[5]; +static struct clk_core *mcbsp_iclks[5]; static int omap3_enable_st_clock(unsigned int id, bool enable) { @@ -98,7 +98,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); pdata->enable_st_clock = omap3_enable_st_clock; sprintf(clk_name, "mcbsp%d_ick", id); - mcbsp_iclks[id] = clk_get(NULL, clk_name); + mcbsp_iclks[id] = clk_provider_get(NULL, clk_name); count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index f138a62..56b8222 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -47,7 +47,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, const char *clk_name) { - struct clk *r; + struct clk_core *r; struct clk_lookup *l; if (!clk_alias || !clk_name) @@ -55,15 +55,15 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name); - r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); + r = clk_provider_get_sys(dev_name(&od->pdev->dev), clk_alias); if (!IS_ERR(r)) { dev_dbg(&od->pdev->dev, "alias %s already exists\n", clk_alias); - clk_put(r); + __clk_put(r); return; } - r = clk_get(NULL, clk_name); + r = clk_provider_get(NULL, clk_name); if (IS_ERR(r)) { dev_err(&od->pdev->dev, "clk_get for %s failed\n", clk_name); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index da1b256..2d951d2 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -753,7 +753,7 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) } /** - * _init_main_clk - get a struct clk * for the the hwmod's main functional clk + * _init_main_clk - get a struct clk_core * for the the hwmod's main functional clk * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh _clk (main @@ -767,7 +767,7 @@ static int _init_main_clk(struct omap_hwmod *oh) if (!oh->main_clk) return 0; - oh->_clk = clk_get(NULL, oh->main_clk); + oh->_clk = clk_provider_get(NULL, oh->main_clk); if (IS_ERR(oh->_clk)) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", oh->name, oh->main_clk); @@ -781,7 +781,7 @@ static int _init_main_clk(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oh->_clk); + clk_provider_prepare(oh->_clk); if (!_get_clkdm(oh)) pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", @@ -791,7 +791,7 @@ static int _init_main_clk(struct omap_hwmod *oh) } /** - * _init_interface_clks - get a struct clk * for the the hwmod's interface clks + * _init_interface_clks - get a struct clk_core * for the the hwmod's interface clks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh OCP slave interface @@ -801,7 +801,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) { struct omap_hwmod_ocp_if *os; struct list_head *p; - struct clk *c; + struct clk_core *c; int i = 0; int ret = 0; @@ -812,7 +812,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) if (!os->clk) continue; - c = clk_get(NULL, os->clk); + c = clk_provider_get(NULL, os->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", oh->name, os->clk); @@ -828,14 +828,14 @@ static int _init_interface_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(os->_clk); + clk_provider_prepare(os->_clk); } return ret; } /** - * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks + * _init_opt_clk - get a struct clk_core * for the the hwmod's optional clocks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk @@ -844,12 +844,12 @@ static int _init_interface_clks(struct omap_hwmod *oh) static int _init_opt_clks(struct omap_hwmod *oh) { struct omap_hwmod_opt_clk *oc; - struct clk *c; + struct clk_core *c; int i; int ret = 0; for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { - c = clk_get(NULL, oc->clk); + c = clk_provider_get(NULL, oc->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", oh->name, oc->clk); @@ -865,7 +865,7 @@ static int _init_opt_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oc->_clk); + clk_provider_prepare(oc->_clk); } return ret; @@ -887,7 +887,7 @@ static int _enable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); if (oh->_clk) - clk_enable(oh->_clk); + clk_provider_enable(oh->_clk); p = oh->slave_ports.next; @@ -895,7 +895,7 @@ static int _enable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -918,7 +918,7 @@ static int _disable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); if (oh->_clk) - clk_disable(oh->_clk); + clk_provider_disable(oh->_clk); p = oh->slave_ports.next; @@ -926,7 +926,7 @@ static int _disable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_disable(os->_clk); + clk_provider_disable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -945,7 +945,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_enable(oc->_clk); + clk_provider_enable(oc->_clk); } } @@ -960,7 +960,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: disable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_disable(oc->_clk); + clk_provider_disable(oc->_clk); } } @@ -2589,7 +2589,7 @@ static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) /* XXX omap_iclk_deny_idle(c); */ } else { /* XXX omap_iclk_allow_idle(c); */ - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } } @@ -3393,7 +3393,7 @@ static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) * Initialize and set up a single hwmod. Intended to be used for a * small number of early devices, such as the timer IP blocks used for * the scheduler clock. Must be called after omap2_clk_init(). - * Resolves the struct clk names to struct clk pointers for each + * Resolves the struct clk_core names to struct clk_core pointers for each * registered omap_hwmod. Also calls _setup() on each hwmod. Returns * -EINVAL upon error or 0 upon success. */ @@ -3422,7 +3422,7 @@ int __init omap_hwmod_setup_one(const char *oh_name) * * Initialize and set up all IP blocks registered with the hwmod code. * Must be called after omap2_clk_init(). Resolves the struct clk - * names to struct clk pointers for each registered omap_hwmod. Also + * names to struct clk_core pointers for each registered omap_hwmod. Also * calls _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) @@ -3789,7 +3789,7 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, */ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { - struct clk *c; + struct clk_core *c; struct omap_hwmod_ocp_if *oi; struct clockdomain *clkdm; struct clk_hw_omap *clk; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0f97d63..46ffd06 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -207,7 +207,7 @@ struct omap_hwmod_rst_info { * struct omap_hwmod_opt_clk - optional clocks used by this hwmod * @role: "sys", "32k", "tv", etc -- for use in clk_get() * @clk: opt clock: OMAP clock name - * @_clk: pointer to the struct clk (filled in at runtime) + * @_clk: pointer to the struct clk_core (filled in at runtime) * * The module's interface clock and main functional clock should not * be added as optional clocks. @@ -215,7 +215,7 @@ struct omap_hwmod_rst_info { struct omap_hwmod_opt_clk { const char *role; const char *clk; - struct clk *_clk; + struct clk_core *_clk; }; @@ -289,7 +289,7 @@ struct omap_hwmod_addr_space { * @slave: struct omap_hwmod that responds to OCP transactions on this link * @addr: address space associated with this link * @clk: interface clock: OMAP clock name - * @_clk: pointer to the interface struct clk (filled in at runtime) + * @_clk: pointer to the interface struct clk_core (filled in at runtime) * @fw: interface firewall data * @width: OCP data width * @user: initiators using this interface (see OCP_USER_* macros above) @@ -306,7 +306,7 @@ struct omap_hwmod_ocp_if { struct omap_hwmod *slave; struct omap_hwmod_addr_space *addr; const char *clk; - struct clk *_clk; + struct clk_core *_clk; union { struct omap_hwmod_omap2_firewall omap2; } fw; @@ -611,7 +611,7 @@ struct omap_hwmod_link { * @sdma_reqs: ptr to an array of System DMA request IDs * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name - * @_clk: pointer to the main struct clk (filled in at runtime) + * @_clk: pointer to the main struct clk_core (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @voltdm: pointer to voltage domain (filled in at runtime) * @dev_attr: arbitrary device attributes that can be passed to the driver @@ -653,7 +653,7 @@ struct omap_hwmod { struct omap_hwmod_omap4_prcm omap4; } prcm; const char *main_clk; - struct clk *_clk; + struct clk_core *_clk; struct omap_hwmod_opt_clk *opt_clks; char *clkdm_name; struct clockdomain *clkdm; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index fe01c5a..56e5e77 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -60,7 +60,7 @@ static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, static struct powerdomain *mpu_pwrdm, *core_pwrdm; static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; -static struct clk *osc_ck, *emul_ck; +static struct clk_core *osc_ck, *emul_ck; static int omap2_enter_full_retention(void) { @@ -71,7 +71,7 @@ static int omap2_enter_full_retention(void) * oscillator itself it will be disabled if/when we enter retention * mode. */ - clk_disable(osc_ck); + clk_provider_disable(osc_ck); /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ @@ -101,7 +101,7 @@ static int omap2_enter_full_retention(void) no_sleep: omap2_gpio_resume_after_idle(); - clk_enable(osc_ck); + clk_provider_enable(osc_ck); /* clear CORE wake-up events */ omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); @@ -287,17 +287,17 @@ int __init omap2_pm_init(void) pr_err("PM: gfx_clkdm not found\n"); - osc_ck = clk_get(NULL, "osc_ck"); + osc_ck = clk_provider_get(NULL, "osc_ck"); if (IS_ERR(osc_ck)) { printk(KERN_ERR "could not get osc_ck\n"); return -ENODEV; } if (cpu_is_omap242x()) { - emul_ck = clk_get(NULL, "emul_ck"); + emul_ck = clk_provider_get(NULL, "emul_ck"); if (IS_ERR(emul_ck)) { printk(KERN_ERR "could not get emul_ck\n"); - clk_put(osc_ck); + __clk_put(osc_ck); return -ENODEV; } } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 6bbb7b5..6be2d2d 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -62,7 +62,7 @@ void __init orion5x_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; void __init clk_init(void) { diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index ed415dc..1637b65 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -32,17 +32,17 @@ void __init shmobile_clk_workaround(const struct clk_name *clks, int nr_clks, bool enable) { const struct clk_name *clkn; - struct clk *clk; + struct clk_core *clk; unsigned int i; for (i = 0; i < nr_clks; ++i) { clkn = clks + i; - clk = clk_get(NULL, clkn->clk); + clk = clk_provider_get(NULL, clkn->clk); if (!IS_ERR(clk)) { clk_register_clkdev(clk, clkn->con_id, clkn->dev_id); if (enable) - clk_prepare_enable(clk); - clk_put(clk); + clk_provider_prepare_enable(clk); + __clk_put(clk); } } } diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c index 2c2754e..f0d73be 100644 --- a/arch/arm/mach-vexpress/spc.c +++ b/arch/arm/mach-vexpress/spc.c @@ -523,7 +523,7 @@ static struct clk_ops clk_spc_ops = { .set_rate = spc_set_rate, }; -static struct clk *ve_spc_clk_register(struct device *cpu_dev) +static struct clk_core *ve_spc_clk_register(struct device *cpu_dev) { struct clk_init_data init; struct clk_spc *spc; @@ -548,7 +548,7 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev) static int __init ve_spc_clk_init(void) { int cpu; - struct clk *clk; + struct clk_core *clk; if (!info) return 0; /* Continue only if SPC is initialised */ diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 961b593..7bf2fe6 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -27,7 +27,7 @@ /* Create a clkdev entry for a given device/clk */ void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk) + struct clk_core *clk) { struct clk_lookup *cl; @@ -40,7 +40,7 @@ void __init orion_clkdev_add(const char *con_id, const char *dev_id, Kirkwood has gated clocks for some of its peripherals, so creates its own clkdev entries. For all the other orion devices, create clkdev entries to the tclk. */ -void __init orion_clkdev_init(struct clk *tclk) +void __init orion_clkdev_init(struct clk_core *tclk) { orion_clkdev_add(NULL, "orion_spi.0", tclk); orion_clkdev_add(NULL, "orion_spi.1", tclk); @@ -78,10 +78,10 @@ static void fill_resources(struct platform_device *device, /***************************************************************************** * UART ****************************************************************************/ -static unsigned long __init uart_get_clk_rate(struct clk *clk) +static unsigned long __init uart_get_clk_rate(struct clk_core *clk) { - clk_prepare_enable(clk); - return clk_get_rate(clk); + clk_provider_prepare_enable(clk); + return clk_provider_get_rate(clk); } static void __init uart_complete( @@ -91,7 +91,7 @@ static void __init uart_complete( void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { data->mapbase = mapbase; data->membase = membase; @@ -125,7 +125,7 @@ static struct platform_device orion_uart0 = { void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources, membase, mapbase, irq, clk); @@ -153,7 +153,7 @@ static struct platform_device orion_uart1 = { void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources, membase, mapbase, irq, clk); @@ -181,7 +181,7 @@ static struct platform_device orion_uart2 = { void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources, membase, mapbase, irq, clk); @@ -209,7 +209,7 @@ static struct platform_device orion_uart3 = { void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, membase, mapbase, irq, clk); diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index d9a24f6..44f1bbe 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -18,22 +18,22 @@ struct mv_sata_platform_data; void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); @@ -107,7 +107,7 @@ void __init orion_crypto_init(unsigned long mapbase, unsigned long irq); void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk); + struct clk_core *clk); -void __init orion_clkdev_init(struct clk *tclk); +void __init orion_clkdev_init(struct clk_core *tclk); #endif diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index 6eb614a..81afe83 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c @@ -70,7 +70,7 @@ enum { }; /* data required for the OF clock provider registration */ -static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; +static struct clk_core *clks[MPC512x_CLK_LAST_PRIVATE]; static struct clk_onecell_data clk_data; /* CCM register access */ @@ -218,12 +218,12 @@ static bool soc_has_mclk_mux0_canin(void) /* common clk API wrappers {{{ */ /* convenience wrappers around the common clk API */ -static inline struct clk *mpc512x_clk_fixed(const char *name, int rate) +static inline struct clk_core *mpc512x_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mpc512x_clk_factor( +static inline struct clk_core *mpc512x_clk_factor( const char *name, const char *parent_name, int mul, int div) { @@ -234,7 +234,7 @@ static inline struct clk *mpc512x_clk_factor( mul, div); } -static inline struct clk *mpc512x_clk_divider( +static inline struct clk_core *mpc512x_clk_divider( const char *name, const char *parent_name, u8 clkflags, u32 __iomem *reg, u8 pos, u8 len, int divflags) { @@ -242,7 +242,7 @@ static inline struct clk *mpc512x_clk_divider( reg, pos, len, divflags, &clklock); } -static inline struct clk *mpc512x_clk_divtable( +static inline struct clk_core *mpc512x_clk_divtable( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos, u8 len, const struct clk_div_table *divtab) @@ -255,7 +255,7 @@ static inline struct clk *mpc512x_clk_divtable( divtab, &clklock); } -static inline struct clk *mpc512x_clk_gated( +static inline struct clk_core *mpc512x_clk_gated( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos) { @@ -266,7 +266,7 @@ static inline struct clk *mpc512x_clk_gated( reg, pos, 0, &clklock); } -static inline struct clk *mpc512x_clk_muxed(const char *name, +static inline struct clk_core *mpc512x_clk_muxed(const char *name, const char **parent_names, int parent_count, u32 __iomem *reg, u8 pos, u8 len) { @@ -422,7 +422,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, int *sys_mul, int *sys_div, int *ips_div) { - struct clk *osc_clk; + struct clk_core *osc_clk; int calc_freq; /* fetch mul/div factors from the hardware */ @@ -432,7 +432,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, *ips_div = get_bit_field(&clkregs->scfr1, 23, 3); /* lookup the oscillator clock for its rate */ - osc_clk = of_clk_get_by_name(np, "osc"); + osc_clk = of_clk_provider_get_by_name(np, "osc"); /* * either descend from OSC to REF (and in bypassing verify the @@ -444,7 +444,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, */ if (!IS_ERR(osc_clk)) { clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); - calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); + calc_freq = clk_provider_get_rate(clks[MPC512x_CLK_REF]); calc_freq *= *sys_mul; calc_freq /= *sys_div; calc_freq /= 2; @@ -647,8 +647,8 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx) * - MCLK 0 enabled * - MCLK 1 from MCLK DIV */ - div = clk_get_rate(clks[MPC512x_CLK_SYS]); - div /= clk_get_rate(clks[MPC512x_CLK_IPS]); + div = clk_provider_get_rate(clks[MPC512x_CLK_SYS]); + div /= clk_provider_get_rate(clks[MPC512x_CLK_IPS]); out_be32(mccr_reg, (0 << 16)); out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17)); out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17)); @@ -925,12 +925,12 @@ static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq) * claimed by any peripheral driver, to not have the clock * subsystem disable them late at startup */ - clk_prepare_enable(clks[MPC512x_CLK_DUMMY]); - clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ - clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ - clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ - clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ - clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DUMMY]); + clk_provider_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ + clk_provider_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ } /* @@ -969,9 +969,9 @@ static void mpc5121_clk_provide_migration_support(void) * has attached to bridges, otherwise the PCI clock remains * unused and so it gets disabled */ - clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ + clk_provider_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci")) - clk_prepare_enable(clks[MPC512x_CLK_PCI]); + clk_provider_prepare_enable(clks[MPC512x_CLK_PCI]); } /* @@ -988,8 +988,8 @@ static void mpc5121_clk_provide_migration_support(void) } while (0) #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \ - struct clk *clk; \ - clk = of_clk_get_by_name(np, clkname); \ + struct clk_core *clk; \ + clk = of_clk_provider_get_by_name(np, clkname); \ if (IS_ERR(clk)) { \ clk = clkitem; \ clk_register_clkdev(clk, clkname, devname); \ @@ -999,7 +999,7 @@ static void mpc5121_clk_provide_migration_support(void) pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \ clkname, devname, clk); \ } else { \ - clk_put(clk); \ + __clk_put(clk); \ } \ } while (0) @@ -1090,7 +1090,7 @@ static void mpc5121_clk_provide_backwards_compat(void) * workaround obsolete */ if (did_register & DID_REG_I2C) - clk_prepare_enable(clks[MPC512x_CLK_I2C]); + clk_provider_prepare_enable(clks[MPC512x_CLK_I2C]); FOR_NODES("fsl,mpc5121-diu") { NODE_PREP; diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 59fa3cc..11bcdb1 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -138,7 +138,7 @@ static const struct clk_ops main_osc_ops = { .is_prepared = clk_main_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -147,7 +147,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, { int ret; struct clk_main_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !parent_name) @@ -192,7 +192,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; const char *name = np->name; const char *parent_name; @@ -291,7 +291,7 @@ static const struct clk_ops main_rc_osc_ops = { .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_rc_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -299,7 +299,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, { int ret; struct clk_main_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !frequency) @@ -340,7 +340,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; u32 frequency = 0; u32 accuracy = 0; @@ -424,13 +424,13 @@ static const struct clk_ops rm9200_main_ops = { .recalc_rate = clk_rm9200_main_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_rm9200_main(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_rm9200_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -462,7 +462,7 @@ at91_clk_register_rm9200_main(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -555,7 +555,7 @@ static const struct clk_ops sam9x5_main_ops = { .get_parent = clk_sam9x5_main_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_main(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -564,7 +564,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, { int ret; struct clk_sam9x5_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name) @@ -607,7 +607,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; unsigned int irq; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index c1af80b..95ae1b6 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -131,7 +131,7 @@ static const struct clk_ops master_ops = { .get_parent = clk_master_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, const char *name, int num_parents, const char **parent_names, @@ -140,7 +140,7 @@ at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, { int ret; struct clk_master *master; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !num_parents || !parent_names) @@ -216,7 +216,7 @@ static void __init of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc, const struct clk_master_layout *layout) { - struct clk *clk; + struct clk_core *clk; int num_parents; int i; unsigned int irq; diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 597fed4..cdf8e8a 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -100,12 +100,12 @@ static const struct clk_ops peripheral_ops = { .is_enabled = clk_peripheral_is_enabled, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id) { struct clk_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX) @@ -134,7 +134,7 @@ at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) { - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; int shift = 0; @@ -309,13 +309,13 @@ static const struct clk_ops sam9x5_peripheral_ops = { .set_rate = clk_sam9x5_peripheral_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id, const struct clk_range *range) { struct clk_sam9x5_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name) @@ -352,7 +352,7 @@ of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type) { int num; u32 id; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name; struct device_node *periphclknp; diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index cf6ed02..0d22f65f 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -297,14 +297,14 @@ static const struct clk_ops pll_ops = { .set_rate = clk_pll_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; int offset = PLL_REG(id); @@ -474,7 +474,7 @@ of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc, { u32 id; unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; struct clk_pll_characteristics *characteristics; diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index ea22656..f8204d8 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -79,12 +79,12 @@ static const struct clk_ops plldiv_ops = { .set_rate = clk_plldiv_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_plldiv *plldiv; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); @@ -111,7 +111,7 @@ at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, static void __init of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 62e2509..b72e98c 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -57,9 +57,9 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, static long clk_programmable_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { - struct clk *parent = NULL; + struct clk_core *parent = NULL; long best_rate = -EINVAL; unsigned long parent_rate; unsigned long tmp_rate; @@ -169,14 +169,14 @@ static const struct clk_ops programmable_ops = { .set_rate = clk_programmable_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_programmable(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout) { struct clk_programmable *prog; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (id > PROG_ID_MAX) @@ -229,7 +229,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc, int num; u32 id; int i; - struct clk *clk; + struct clk_core *clk; int num_parents; const char *parent_names[PROG_SOURCE_MAX]; const char *name; diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index 0300c46..d50fe02 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -117,7 +117,7 @@ static const struct clk_ops slow_osc_ops = { .is_prepared = clk_slow_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const char *parent_name, @@ -125,7 +125,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, bool bypass) { struct clk_slow_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_name) @@ -159,7 +159,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 startup; @@ -229,7 +229,7 @@ static const struct clk_ops slow_rc_osc_ops = { .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_rc_osc(void __iomem *sckcr, const char *name, unsigned long frequency, @@ -237,7 +237,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, unsigned long startup) { struct clk_slow_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name) @@ -269,7 +269,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; u32 frequency = 0; u32 accuracy = 0; u32 startup = 0; @@ -327,14 +327,14 @@ static const struct clk_ops sam9x5_slow_ops = { .get_parent = clk_sam9x5_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_slow(void __iomem *sckcr, const char *name, const char **parent_names, int num_parents) { struct clk_sam9x5_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_names || !num_parents) @@ -364,7 +364,7 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; @@ -401,14 +401,14 @@ static const struct clk_ops sam9260_slow_ops = { .get_parent = clk_sam9260_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9260_slow(struct at91_pmc *pmc, const char *name, const char **parent_names, int num_parents) { struct clk_sam9260_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -440,7 +440,7 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc, void __init of_at91sam9260_clk_slow_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index 144d47e..8820b84 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -113,12 +113,12 @@ static const struct clk_ops at91sam9x5_smd_ops = { .set_rate = at91sam9x5_clk_smd_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_smd *smd; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; smd = kzalloc(sizeof(*smd), GFP_KERNEL); @@ -144,7 +144,7 @@ at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[SMD_SOURCE_MAX]; diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 8c96307..770d9bf 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -99,12 +99,12 @@ static const struct clk_ops system_ops = { .is_prepared = clk_system_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_system(struct at91_pmc *pmc, const char *name, const char *parent_name, u8 id, int irq) { struct clk_system *sys; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; @@ -153,7 +153,7 @@ of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc) int num; int irq = 0; u32 id; - struct clk *clk; + struct clk_core *clk; const char *name; struct device_node *sysclknp; const char *parent_name; diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 7d1d26a..246989c 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -162,12 +162,12 @@ static const struct clk_ops at91sam9n12_usb_ops = { .set_rate = at91sam9x5_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -190,12 +190,12 @@ at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, return clk; } -static struct clk * __init +static struct clk_core * __init at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -295,12 +295,12 @@ static const struct clk_ops at91rm9200_usb_ops = { .set_rate = at91rm9200_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name, const u32 *divisors) { struct at91rm9200_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -327,7 +327,7 @@ at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[USB_SOURCE_MAX]; @@ -355,7 +355,7 @@ void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -375,7 +375,7 @@ void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, void __init of_at91rm9200_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 divisors[4] = {0, 0, 0, 0}; diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index ae3263b..0502050 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -92,13 +92,13 @@ static const struct clk_ops utmi_ops = { .recalc_rate = clk_utmi_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name) { int ret; struct clk_utmi *utmi; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; utmi = kzalloc(sizeof(*utmi), GFP_KERNEL); @@ -132,7 +132,7 @@ static void __init of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc) { unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c index e5aeded..122e7b0 100644 --- a/drivers/clk/bcm/clk-kona-setup.c +++ b/drivers/clk/bcm/clk-kona-setup.c @@ -697,7 +697,7 @@ static void bcm_clk_teardown(struct kona_clk *bcm_clk) bcm_clk->type = bcm_clk_none; } -static void kona_clk_teardown(struct clk *clk) +static void kona_clk_teardown(struct clk_core *clk) { struct clk_hw *hw; struct kona_clk *bcm_clk; @@ -716,10 +716,10 @@ static void kona_clk_teardown(struct clk *clk) bcm_clk_teardown(bcm_clk); } -struct clk *kona_clk_setup(struct kona_clk *bcm_clk) +struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk) { struct clk_init_data *init_data = &bcm_clk->init_data; - struct clk *clk = NULL; + struct clk_core *clk = NULL; switch (bcm_clk->type) { case bcm_clk_peri: diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c index 95af2e6..a301aa9 100644 --- a/drivers/clk/bcm/clk-kona.c +++ b/drivers/clk/bcm/clk-kona.c @@ -1032,11 +1032,11 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate, } static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *best_parent_rate, struct clk **best_parent) + unsigned long *best_parent_rate, struct clk_core **best_parent) { struct kona_clk *bcm_clk = to_kona_clk(hw); - struct clk *clk = hw->clk; - struct clk *current_parent; + struct clk_core *clk = hw->clk; + struct clk_core *current_parent; unsigned long parent_rate; unsigned long best_delta; unsigned long best_rate; @@ -1053,14 +1053,14 @@ static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, return kona_peri_clk_round_rate(hw, rate, best_parent_rate); /* Unless we can do better, stick with current parent */ - current_parent = clk_get_parent(clk); + current_parent = clk_provider_get_parent(clk); parent_rate = __clk_get_rate(current_parent); best_rate = kona_peri_clk_round_rate(hw, rate, &parent_rate); best_delta = abs(best_rate - rate); /* Check whether any other parent clock can produce a better result */ for (which = 0; which < parent_count; which++) { - struct clk *parent = clk_get_parent_by_index(clk, which); + struct clk_core *parent = clk_get_parent_by_index(clk, which); unsigned long delta; unsigned long other_rate; @@ -1260,7 +1260,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu) { unsigned long flags; unsigned int which; - struct clk **clks = ccu->clk_data.clks; + struct clk_core **clks = ccu->clk_data.clks; bool success = true; flags = ccu_lock(ccu); diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h index 2537b30..c2d0152 100644 --- a/drivers/clk/bcm/clk-kona.h +++ b/drivers/clk/bcm/clk-kona.h @@ -508,7 +508,7 @@ extern u64 scaled_div_max(struct bcm_clk_div *div); extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths); -extern struct clk *kona_clk_setup(struct kona_clk *bcm_clk); +extern struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk); extern void __init kona_dt_ccu_setup(struct ccu_data *ccu, struct device_node *node); extern bool __init kona_ccu_init(struct ccu_data *ccu); diff --git a/drivers/clk/berlin/berlin2-avpll.c b/drivers/clk/berlin/berlin2-avpll.c index fd0f26c..488d986 100644 --- a/drivers/clk/berlin/berlin2-avpll.c +++ b/drivers/clk/berlin/berlin2-avpll.c @@ -188,7 +188,7 @@ static const struct clk_ops berlin2_avpll_vco_ops = { .recalc_rate = berlin2_avpll_vco_recalc_rate, }; -struct clk * __init berlin2_avpll_vco_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags) { @@ -364,7 +364,7 @@ static const struct clk_ops berlin2_avpll_channel_ops = { */ static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 }; -struct clk * __init berlin2_avpll_channel_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags) { diff --git a/drivers/clk/berlin/berlin2-avpll.h b/drivers/clk/berlin/berlin2-avpll.h index a37f506..216eee7 100644 --- a/drivers/clk/berlin/berlin2-avpll.h +++ b/drivers/clk/berlin/berlin2-avpll.h @@ -24,11 +24,11 @@ struct clk; #define BERLIN2_AVPLL_BIT_QUIRK BIT(0) #define BERLIN2_AVPLL_SCRAMBLE_QUIRK BIT(1) -struct clk * __init +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags); -struct clk * __init +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags); diff --git a/drivers/clk/berlin/berlin2-div.c b/drivers/clk/berlin/berlin2-div.c index 81ff97f..c673082 100644 --- a/drivers/clk/berlin/berlin2-div.c +++ b/drivers/clk/berlin/berlin2-div.c @@ -234,7 +234,7 @@ static const struct clk_ops berlin2_div_mux_ops = { .get_parent = berlin2_div_get_parent, }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-div.h b/drivers/clk/berlin/berlin2-div.h index 15e3384..3ddb87a 100644 --- a/drivers/clk/berlin/berlin2-div.h +++ b/drivers/clk/berlin/berlin2-div.h @@ -80,7 +80,7 @@ struct berlin2_div_data { u8 div_flags; }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-pll.c b/drivers/clk/berlin/berlin2-pll.c index bdc506b..b7a3016 100644 --- a/drivers/clk/berlin/berlin2-pll.c +++ b/drivers/clk/berlin/berlin2-pll.c @@ -91,7 +91,7 @@ static const struct clk_ops berlin2_pll_ops = { .recalc_rate = berlin2_pll_recalc_rate, }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags) diff --git a/drivers/clk/berlin/berlin2-pll.h b/drivers/clk/berlin/berlin2-pll.h index 8831ce2..6b6a6ed 100644 --- a/drivers/clk/berlin/berlin2-pll.h +++ b/drivers/clk/berlin/berlin2-pll.h @@ -29,7 +29,7 @@ struct berlin2_pll_map { u8 divsel_shift; }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags); diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c index 4c81e09..1329721 100644 --- a/drivers/clk/berlin/bg2.c +++ b/drivers/clk/berlin/bg2.c @@ -93,7 +93,7 @@ */ #define MAX_CLKS 41 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -504,7 +504,7 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = { static void __init berlin2_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; u8 avpll_flags = 0; int n; @@ -513,16 +513,16 @@ static void __init berlin2_clock_setup(struct device_node *np) return; /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } - clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]); + clk = of_clk_provider_get_by_name(np, clk_names[VIDEO_EXT0]); if (!IS_ERR(clk)) { clk_names[VIDEO_EXT0] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c index 748da9b..0b251bd 100644 --- a/drivers/clk/berlin/bg2q.c +++ b/drivers/clk/berlin/bg2q.c @@ -47,7 +47,7 @@ #define REG_SDIO1XIN_CLKCTL 0x015c #define MAX_CLKS 27 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -293,7 +293,7 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = { static void __init berlin2q_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; int n; gbase = of_iomap(np, 0); @@ -311,10 +311,10 @@ static void __init berlin2q_clock_setup(struct device_node *np) } /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 1127ee4..4b64834 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -489,7 +489,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) const char *parent_name; const char *clk_name; struct resource *mem; - struct clk *clk; + struct clk_core *clk; if (!pdev->dev.of_node) return -ENODEV; diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c index d2f1e11..3dc6e58 100644 --- a/drivers/clk/clk-axm5516.c +++ b/drivers/clk/clk-axm5516.c @@ -532,7 +532,7 @@ MODULE_DEVICE_TABLE(of, axmclk_match_table); struct axmclk_priv { struct clk_onecell_data onecell; - struct clk *clks[]; + struct clk_core *clks[]; }; static int axmclk_probe(struct platform_device *pdev) @@ -541,7 +541,7 @@ static int axmclk_probe(struct platform_device *pdev) struct resource *res; int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct regmap *regmap; size_t num_clks; struct axmclk_priv *priv; diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c index 6b950ca..f25e85e 100644 --- a/drivers/clk/clk-bcm2835.c +++ b/drivers/clk/clk-bcm2835.c @@ -29,7 +29,7 @@ */ void __init bcm2835_init_clocks(void) { - struct clk *clk; + struct clk_core *clk; int ret; clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT, diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index b9355da..a812a56 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -57,14 +57,14 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_composite *composite = to_clk_composite(hw); const struct clk_ops *rate_ops = composite->rate_ops; const struct clk_ops *mux_ops = composite->mux_ops; struct clk_hw *rate_hw = composite->rate_hw; struct clk_hw *mux_hw = composite->mux_hw; - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; long tmp_rate, best_rate = 0; unsigned long rate_diff; @@ -80,7 +80,7 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, *best_parent_p = NULL; if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) { - *best_parent_p = clk_get_parent(mux_hw->clk); + *best_parent_p = clk_provider_get_parent(mux_hw->clk); *best_parent_rate = __clk_get_rate(*best_parent_p); return rate_ops->round_rate(rate_hw, rate, @@ -181,14 +181,14 @@ static void clk_composite_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } -struct clk *clk_register_composite(struct device *dev, const char *name, +struct clk_core *clk_register_composite(struct device *dev, const char *name, const char **parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct clk_composite *composite; struct clk_ops *clk_composite_ops; diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index d36a7b3..a7d3a48 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -20,7 +20,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) { struct of_phandle_args clkspec; int index, rc, num_parents; - struct clk *clk, *pclk; + struct clk_core *clk, *pclk; num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", "#clock-cells"); @@ -63,16 +63,16 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) goto err; } - rc = clk_set_parent(clk, pclk); + rc = clk_provider_set_parent(clk, pclk); if (rc < 0) pr_err("clk: failed to reparent %s to %s: %d\n", __clk_get_name(clk), __clk_get_name(pclk), rc); - clk_put(clk); - clk_put(pclk); + __clk_put(clk); + __clk_put(pclk); } return 0; err: - clk_put(pclk); + __clk_put(pclk); return rc; } @@ -82,7 +82,7 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) struct property *prop; const __be32 *cur; int rc, index = 0; - struct clk *clk; + struct clk_core *clk; u32 rate; of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) { @@ -106,11 +106,11 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) return PTR_ERR(clk); } - rc = clk_set_rate(clk, rate); + rc = clk_provider_set_rate(clk, rate); if (rc < 0) pr_err("clk: couldn't set %s clock rate: %d\n", __clk_get_name(clk), rc); - clk_put(clk); + __clk_put(clk); } index++; } diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 18a9de2..3c78139 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -366,14 +366,14 @@ const struct clk_ops clk_divider_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_divider_ro_ops); -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -429,7 +429,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_divider(struct device *dev, const char *name, +struct clk_core *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock) @@ -453,7 +453,7 @@ EXPORT_SYMBOL_GPL(clk_register_divider); * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ -struct clk *clk_register_divider_table(struct device *dev, const char *name, +struct clk_core *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c index bac2ddf..26e0485 100644 --- a/drivers/clk/clk-efm32gg.c +++ b/drivers/clk/clk-efm32gg.c @@ -16,7 +16,7 @@ #define CMU_HFPERCLKEN0 0x44 -static struct clk *clk[37]; +static struct clk_core *clk[37]; static struct clk_onecell_data clk_data = { .clks = clk, .clk_num = ARRAY_SIZE(clk), diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index d9e3f67..ae1fef0 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -65,13 +65,13 @@ struct clk_ops clk_fixed_factor_ops = { }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { struct clk_fixed_factor *fix; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fix = kmalloc(sizeof(*fix), GFP_KERNEL); if (!fix) { @@ -105,7 +105,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_factor); */ void __init of_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index 0fc56ab..56c0ced 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -56,12 +56,12 @@ EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, +struct clk_core *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy) { struct clk_fixed_rate *fixed; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate fixed-rate clock */ @@ -99,7 +99,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy); * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate) { @@ -114,7 +114,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate); */ void of_fixed_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; u32 rate; u32 accuracy = 0; diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index ede685c..8104683 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -96,14 +96,14 @@ const struct clk_ops clk_fractional_divider_ops = { }; EXPORT_SYMBOL_GPL(clk_fractional_divider_ops); -struct clk *clk_register_fractional_divider(struct device *dev, +struct clk_core *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock) { struct clk_fractional_divider *fd; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fd = kzalloc(sizeof(*fd), GFP_KERNEL); if (!fd) { diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 4a58c55..429d302 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -118,13 +118,13 @@ EXPORT_SYMBOL_GPL(clk_gate_ops); * @clk_gate_flags: gate-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_gate(struct device *dev, const char *name, +struct clk_core *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clk_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 2e7e9d9..cad2fba 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -271,10 +271,10 @@ static const struct clk_ops periclk_ops = { .set_rate = clk_periclk_set_rate, }; -static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops) +static __init struct clk_core *hb_clk_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct hb_clk *hb_clk; const char *clk_name = node->name; const char *parent_name; @@ -330,8 +330,8 @@ CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init); static void __init hb_a9bus_init(struct device_node *node) { - struct clk *clk = hb_clk_init(node, &a9bclk_ops); - clk_prepare_enable(clk); + struct clk_core *clk = hb_clk_init(node, &a9bclk_ops); + clk_provider_prepare_enable(clk); } CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init); diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c index f20b750..796043c 100644 --- a/drivers/clk/clk-ls1x.c +++ b/drivers/clk/clk-ls1x.c @@ -48,11 +48,11 @@ static const struct clk_ops ls1x_pll_clk_ops = { .recalc_rate = ls1x_pll_recalc_rate, }; -static struct clk * __init clk_register_pll(struct device *dev, +static struct clk_core * __init clk_register_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags) { struct clk_hw *hw; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the divider */ @@ -80,32 +80,32 @@ static struct clk * __init clk_register_pll(struct device *dev, void __init ls1x_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk = clk_register_divider(NULL, "cpu_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT, DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "cpu", NULL); clk = clk_register_divider(NULL, "dc_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "dc", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "ahb", NULL); clk_register_clkdev(clk, "stmmaceth", NULL); clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "apb", NULL); clk_register_clkdev(clk, "serial8250", NULL); } diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 3d7e8dd..42fa43a 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -112,10 +112,10 @@ static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = { }, }; -static struct clk *max77686_clk_register(struct device *dev, +static struct clk_core *max77686_clk_register(struct device *dev, struct max77686_clk *max77686) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *hw = &max77686->hw; clk = clk_register(dev, hw); @@ -138,10 +138,10 @@ static int max77686_clk_probe(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct max77686_clk *max77686_clks[MAX77686_CLKS_NUM]; - struct clk **clocks; + struct clk_core **clocks; int i, ret; - clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk *) + clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * MAX77686_CLKS_NUM, GFP_KERNEL); if (!clocks) return -ENOMEM; @@ -203,7 +203,7 @@ err_clocks: static int max77686_clk_remove(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); - struct clk **clocks = platform_get_drvdata(pdev); + struct clk_core **clocks = platform_get_drvdata(pdev); int i; if (iodev->dev->of_node) diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c index 30a3b69..c503c09 100644 --- a/drivers/clk/clk-moxart.c +++ b/drivers/clk/clk-moxart.c @@ -18,7 +18,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *ref_clk; + struct clk_core *clk, *ref_clk; unsigned int mul; const char *name = node->name; const char *parent_name; @@ -35,7 +35,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) mul = readl(base + 0x30) >> 3 & 0x3f; iounmap(base); - ref_clk = of_clk_get(node, 0); + ref_clk = of_clk_provider_get(node, 0); if (IS_ERR(ref_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; @@ -56,7 +56,7 @@ CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock", void __init moxart_of_apb_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *pll_clk; + struct clk_core *clk, *pll_clk; unsigned int div, val; unsigned int div_idx[] = { 2, 3, 4, 6, 8}; const char *name = node->name; @@ -78,7 +78,7 @@ void __init moxart_of_apb_clk_init(struct device_node *node) val = 0; div = div_idx[val] * 2; - pll_clk = of_clk_get(node, 0); + pll_clk = of_clk_provider_get(node, 0); if (IS_ERR(pll_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 4f96ff3..2879053 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -113,13 +113,13 @@ const struct clk_ops clk_mux_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_mux_ro_ops); -struct clk *clk_register_mux_table(struct device *dev, const char *name, +struct clk_core *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; u8 width = 0; @@ -165,7 +165,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, } EXPORT_SYMBOL_GPL(clk_register_mux_table); -struct clk *clk_register_mux(struct device *dev, const char *name, +struct clk_core *clk_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock) diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 05e04ce..5d87366 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -254,11 +254,11 @@ static const struct clk_ops pll_clk_ops = { .recalc_rate = pll_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init pll_clk_register(struct device *dev, const char *name, const char *parent_name, u32 id) { - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll; struct clk_init_data init; @@ -346,11 +346,11 @@ static const struct clk_ops src_clk_ops = { .recalc_rate = src_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init src_clk_register(struct device *dev, const char *name, const char *parent_name, u8 id) { - struct clk *clk; + struct clk_core *clk; struct clk_src *sclk; struct clk_init_data init; @@ -510,7 +510,7 @@ module_init(nomadik_src_clk_init_debugfs); static void __init of_nomadik_pll_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 pll_id; @@ -533,7 +533,7 @@ CLK_OF_DECLARE(nomadik_pll_clk, static void __init of_nomadik_hclk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; @@ -557,7 +557,7 @@ CLK_OF_DECLARE(nomadik_hclk_clk, static void __init of_nomadik_src_clk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 clk_id; diff --git a/drivers/clk/clk-nspire.c b/drivers/clk/clk-nspire.c index a378db7..e9c43f4 100644 --- a/drivers/clk/clk-nspire.c +++ b/drivers/clk/clk-nspire.c @@ -69,7 +69,7 @@ static void __init nspire_ahbdiv_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; struct nspire_clk_info info; @@ -111,7 +111,7 @@ static void __init nspire_clk_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct nspire_clk_info info; diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c index 8e58edf..5619ee9 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-ppc-corenet.c @@ -64,7 +64,7 @@ const struct clk_ops cmux_ops = { static void __init core_mux_init(struct device_node *np) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct cmux_clk *cmux_clk; struct device_node *node; @@ -150,7 +150,7 @@ static void __init core_pll_init(struct device_node *np) int i, rc, count; const char *clk_name, *parent_name; struct clk_onecell_data *onecell_data; - struct clk **subclks; + struct clk_core **subclks; void __iomem *base; base = of_iomap(np, 0); @@ -184,7 +184,7 @@ static void __init core_pll_init(struct device_node *np) /* output clock number per PLL */ clocks_per_pll = count; - subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); + subclks = kzalloc(sizeof(struct clk_core *) * count, GFP_KERNEL); if (!subclks) { pr_err("%s: could not allocate subclks\n", __func__); goto err_map; @@ -246,7 +246,7 @@ err_map: static void __init sysclk_init(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct device_node *np = of_get_parent(node); u32 rate; diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index b7797fb..17fc7e1 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -29,7 +29,7 @@ #define s2mps11_name(a) (a->hw.init->name) -static struct clk **clk_table; +static struct clk_core **clk_table; static struct clk_onecell_data clk_data; enum { @@ -43,7 +43,7 @@ struct s2mps11_clk { struct sec_pmic_dev *iodev; struct device_node *clk_np; struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_lookup *lookup; u32 mask; unsigned int reg; @@ -174,7 +174,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev) s2mps11_clk = s2mps11_clks; - clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk *) * + clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * S2MPS11_CLKS_NUM, GFP_KERNEL); if (!clk_table) return -ENOMEM; diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 3b2a66f..57c9eb5 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -56,10 +56,10 @@ struct si5351_driver_data { struct regmap *regmap; struct clk_onecell_data onecell; - struct clk *pxtal; + struct clk_core *pxtal; const char *pxtal_name; struct clk_hw xtal; - struct clk *pclkin; + struct clk_core *pclkin; const char *pclkin_name; struct clk_hw clkin; @@ -1128,12 +1128,12 @@ static int si5351_dt_parse(struct i2c_client *client, if (!pdata) return -ENOMEM; - pdata->clk_xtal = of_clk_get(np, 0); + pdata->clk_xtal = of_clk_provider_get(np, 0); if (!IS_ERR(pdata->clk_xtal)) - clk_put(pdata->clk_xtal); - pdata->clk_clkin = of_clk_get(np, 1); + __clk_put(pdata->clk_xtal); + pdata->clk_clkin = of_clk_provider_get(np, 1); if (!IS_ERR(pdata->clk_clkin)) - clk_put(pdata->clk_clkin); + __clk_put(pdata->clk_clkin); /* * property silabs,pll-source : <num src>, [<..>] @@ -1306,7 +1306,7 @@ static int si5351_i2c_probe(struct i2c_client *client, struct si5351_platform_data *pdata; struct si5351_driver_data *drvdata; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; const char *parent_names[4]; u8 num_parents, num_clocks; int ret, n; @@ -1545,7 +1545,8 @@ static int si5351_i2c_probe(struct i2c_client *client, /* set initial clkout rate */ if (pdata->clkout[n].rate != 0) { int ret; - ret = clk_set_rate(clk, pdata->clkout[n].rate); + ret = clk_provider_set_rate(clk, + pdata->clkout[n].rate); if (ret != 0) { dev_err(&client->dev, "Cannot set rate : %d\n", ret); diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c index fc167b3..f0eec4e 100644 --- a/drivers/clk/clk-si570.c +++ b/drivers/clk/clk-si570.c @@ -407,7 +407,7 @@ static int si570_probe(struct i2c_client *client, { struct clk_si570 *data; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; u32 initial_fout, factory_fout, stability; int err; enum clk_si570_variant variant = id->driver_data; @@ -476,7 +476,7 @@ static int si570_probe(struct i2c_client *client, /* Read the requested initial output frequency from device tree */ if (!of_property_read_u32(client->dev.of_node, "clock-frequency", &initial_fout)) { - err = clk_set_rate(clk, initial_fout); + err = clk_provider_set_rate(clk, initial_fout); if (err) { of_clk_del_provider(client->dev.of_node); return err; diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c index 1ada79a..2422857 100644 --- a/drivers/clk/clk-twl6040.c +++ b/drivers/clk/clk-twl6040.c @@ -31,7 +31,7 @@ struct twl6040_clk { struct twl6040 *twl6040; struct device *dev; struct clk_hw mcpdm_fclk; - struct clk *clk; + struct clk_core *clk; int enabled; }; diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index 406bfc1..7e9ec00 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -688,7 +688,7 @@ static const struct clk_ops syscon_clk_ops = { .set_rate = syscon_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init syscon_clk_register(struct device *dev, const char *name, const char *parent_name, unsigned long flags, bool hw_ctrld, @@ -696,7 +696,7 @@ syscon_clk_register(struct device *dev, const char *name, void __iomem *en_reg, u8 en_bit, u16 clk_val) { - struct clk *clk; + struct clk_core *clk; struct clk_syscon *sclk; struct clk_init_data init; @@ -867,7 +867,7 @@ static struct u300_clock const u300_clk_lookup[] __initconst = { static void __init of_u300_syscon_clk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; void __iomem *res_reg; @@ -1110,11 +1110,11 @@ static const struct clk_ops mclk_ops = { .set_rate = mclk_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init mclk_clk_register(struct device *dev, const char *name, const char *parent_name, bool is_mspro) { - struct clk *clk; + struct clk_core *clk; struct clk_mclk *mclk; struct clk_init_data init; @@ -1141,7 +1141,7 @@ mclk_clk_register(struct device *dev, const char *name, static void __init of_u300_syscon_mclk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index 37e9288..e5fb933 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -232,7 +232,7 @@ static const struct clk_ops vt8500_gated_divisor_clk_ops = { static __init void vtwm_device_clk_init(struct device_node *node) { u32 en_reg, div_reg; - struct clk *clk; + struct clk_core *clk; struct clk_device *dev_clk; const char *clk_name = node->name; const char *parent_name; @@ -650,7 +650,7 @@ static const struct clk_ops vtwm_pll_ops = { static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c index b131041..d2d745e 100644 --- a/drivers/clk/clk-wm831x.c +++ b/drivers/clk/clk-wm831x.c @@ -25,9 +25,9 @@ struct wm831x_clk { struct clk_hw xtal_hw; struct clk_hw fll_hw; struct clk_hw clkout_hw; - struct clk *xtal; - struct clk *fll; - struct clk *clkout; + struct clk_core *xtal; + struct clk_core *fll; + struct clk_core *clkout; bool xtal_ena; }; diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index dd8a62d..ce3ed34 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -124,13 +124,13 @@ const struct clk_ops xgene_clk_pll_ops = { .recalc_rate = xgene_clk_pll_recalc_rate, }; -static struct clk *xgene_register_clk_pll(struct device *dev, +static struct clk_core *xgene_register_clk_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 pll_offset, u32 type, spinlock_t *lock) { struct xgene_clk_pll *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the APM clock structure */ @@ -166,7 +166,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev, static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; void *reg; reg = of_iomap(np, 0); @@ -395,12 +395,12 @@ const struct clk_ops xgene_clk_ops = { .round_rate = xgene_clk_round_rate, }; -static struct clk *xgene_register_clk(struct device *dev, +static struct clk_core *xgene_register_clk(struct device *dev, const char *name, const char *parent_name, struct xgene_dev_parameters *parameters, spinlock_t *lock) { struct xgene_clk *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int rc; @@ -442,7 +442,7 @@ static struct clk *xgene_register_clk(struct device *dev, static void __init xgene_devclk_init(struct device_node *np) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; struct resource res; int rc; struct xgene_dev_parameters parameters; diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h index c798138..d278572 100644 --- a/drivers/clk/clk.h +++ b/drivers/clk/clk.h @@ -10,8 +10,8 @@ */ #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) -struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); -struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec); +struct clk_core *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); +struct clk_core *__of_clk_get_from_provider(struct of_phandle_args *clkspec); void of_clk_lock(void); void of_clk_unlock(void); #endif diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 339945d..d7d3667 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -296,7 +296,7 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw, static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_mmc *mclk = to_mmc(hw); unsigned long best = 0; @@ -427,11 +427,11 @@ static struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, +static struct clk_core *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, void __iomem *base, struct device_node *np) { struct clk_mmc *mclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; mclk = kzalloc(sizeof(*mclk), GFP_KERNEL); @@ -487,7 +487,7 @@ static void __init hi3620_mmc_clk_init(struct device_node *node) if (WARN_ON(!clk_data)) return; - clk_data->clks = kzalloc(sizeof(struct clk *) * num, GFP_KERNEL); + clk_data->clks = kzalloc(sizeof(struct clk_core *) * num, GFP_KERNEL); if (!clk_data->clks) { pr_err("%s: fail to allocate mmc clk\n", __func__); return; diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index a078e84..3fcd2ba 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -42,7 +42,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, int nr_clks) { struct hisi_clock_data *clk_data; - struct clk **clk_table; + struct clk_core **clk_table; void __iomem *base; if (np) { @@ -63,7 +63,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, } clk_data->base = base; - clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); + clk_table = kzalloc(sizeof(struct clk_core *) * nr_clks, GFP_KERNEL); if (!clk_table) { pr_err("%s: could not allocate clock lookup table\n", __func__); goto err_data; @@ -81,7 +81,7 @@ err: void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -102,7 +102,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -122,7 +122,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -151,7 +151,7 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -180,7 +180,7 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -208,7 +208,7 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..f7fc4b9 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -90,7 +90,7 @@ struct hisi_gate_clock { const char *alias; }; -struct clk *hisi_register_clkgate_sep(struct device *, const char *, +struct clk_core *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, u8, spinlock_t *); diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index b03d5a7..61f7236 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -96,14 +96,14 @@ static struct clk_ops clkgate_separated_ops = { .is_enabled = clkgate_separated_is_enabled, }; -struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, +struct clk_core *hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clkgate_separated *sclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c index 86f1e36..3f7db44 100644 --- a/drivers/clk/keystone/gate.c +++ b/drivers/clk/keystone/gate.c @@ -163,7 +163,7 @@ static const struct clk_ops clk_psc_ops = { * @psc_data: platform data to configure this clock * @lock: spinlock used by this clock */ -static struct clk *clk_register_psc(struct device *dev, +static struct clk_core *clk_register_psc(struct device *dev, const char *name, const char *parent_name, struct clk_psc_data *psc_data, @@ -171,7 +171,7 @@ static struct clk *clk_register_psc(struct device *dev, { struct clk_init_data init; struct clk_psc *psc; - struct clk *clk; + struct clk_core *clk; psc = kzalloc(sizeof(*psc), GFP_KERNEL); if (!psc) @@ -204,7 +204,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) const char *clk_name = node->name; const char *parent_name; struct clk_psc_data *data; - struct clk *clk; + struct clk_core *clk; int i; data = kzalloc(sizeof(*data), GFP_KERNEL); diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 0dd8a4b..fc3156e 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -116,14 +116,14 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pllclk_recalc, }; -static struct clk *clk_register_pll(struct device *dev, +static struct clk_core *clk_register_pll(struct device *dev, const char *name, const char *parent_name, struct clk_pll_data *pll_data) { struct clk_init_data init; struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -158,7 +158,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) { struct clk_pll_data *pll_data; const char *parent_name; - struct clk *clk; + struct clk_core *clk; int i; pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL); @@ -239,7 +239,7 @@ static void __init of_pll_div_clk_init(struct device_node *node) const char *parent_name; void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; of_property_read_string(node, "clock-output-names", &clk_name); @@ -282,7 +282,7 @@ static void __init of_pll_mux_clk_init(struct device_node *node) { void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *parents[2]; const char *clk_name = node->name; diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c index d14120e..4ca8713 100644 --- a/drivers/clk/mmp/clk-apbc.c +++ b/drivers/clk/mmp/clk-apbc.c @@ -120,12 +120,12 @@ struct clk_ops clk_apbc_ops = { .unprepare = clk_apbc_unprepare, }; -struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock) { struct clk_apbc *apbc; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apbc = kzalloc(sizeof(*apbc), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c index abe182b..c24e6e7 100644 --- a/drivers/clk/mmp/clk-apmu.c +++ b/drivers/clk/mmp/clk-apmu.c @@ -66,11 +66,11 @@ struct clk_ops clk_apmu_ops = { .disable = clk_apmu_disable, }; -struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock) { struct clk_apmu *apmu; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apmu = kzalloc(sizeof(*apmu), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c index 23a56f5..0386cdd 100644 --- a/drivers/clk/mmp/clk-frac.c +++ b/drivers/clk/mmp/clk-frac.c @@ -116,14 +116,14 @@ static struct clk_ops clk_factor_ops = { .set_rate = clk_factor_set_rate, }; -struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt) { struct clk_factor *factor; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!masks) { pr_err("%s: must pass a clk_factor_mask\n", __func__); diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c index b2721ca..98bd73f 100644 --- a/drivers/clk/mmp/clk-mmp2.c +++ b/drivers/clk/mmp/clk-mmp2.c @@ -77,8 +77,8 @@ static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"}; void __init mmp2_clk_init(void) { - struct clk *clk; - struct clk *vctcxo; + struct clk_core *clk; + struct clk_core *vctcxo; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -192,7 +192,7 @@ void __init mmp2_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(clk, 14745600); + clk_provider_set_rate(clk, 14745600); clk_register_clkdev(clk, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "vctcxo", @@ -251,7 +251,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -262,7 +262,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -273,7 +273,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", @@ -284,7 +284,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.3", NULL); clk = mmp_clk_register_apbc("uart3", "uart3_mux", diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c index 014396b..e4f50ab 100644 --- a/drivers/clk/mmp/clk-pxa168.c +++ b/drivers/clk/mmp/clk-pxa168.c @@ -68,8 +68,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa168_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -159,7 +159,7 @@ void __init pxa168_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -202,7 +202,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -213,7 +213,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -224,7 +224,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c index 9efc6a4..b5c215e 100644 --- a/drivers/clk/mmp/clk-pxa910.c +++ b/drivers/clk/mmp/clk-pxa910.c @@ -66,8 +66,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa910_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbcp_base; @@ -164,7 +164,7 @@ void __init pxa910_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -207,7 +207,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -218,7 +218,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -229,7 +229,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h index ab86dd4..1477e61 100644 --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h @@ -20,15 +20,15 @@ struct clk_factor_tbl { unsigned int den; }; -extern struct clk *mmp_clk_register_pll2(const char *name, +extern struct clk_core *mmp_clk_register_pll2(const char *name, const char *parent_name, unsigned long flags); -extern struct clk *mmp_clk_register_apbc(const char *name, +extern struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock); -extern struct clk *mmp_clk_register_apmu(const char *name, +extern struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock); -extern struct clk *mmp_clk_register_factor(const char *name, +extern struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt); diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index d1e5863..1be15c4 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -238,7 +238,7 @@ mvebu_corediv_clk_init(struct device_node *node, { struct clk_init_data init; struct clk_corediv *corediv; - struct clk **clks; + struct clk_core **clks; void __iomem *base; const char *parent_name; const char *clk_name; @@ -253,7 +253,7 @@ mvebu_corediv_clk_init(struct device_node *node, clk_data.clk_num = soc_desc->ndescs; /* clks holds the clock array */ - clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), + clks = kcalloc(clk_data.clk_num, sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clks)) goto err_unmap; diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c index 3821a88..59a40c7 100644 --- a/drivers/clk/mvebu/clk-cpu.c +++ b/drivers/clk/mvebu/clk-cpu.c @@ -40,7 +40,7 @@ struct cpu_clk { void __iomem *pmu_dfs; }; -static struct clk **clks; +static struct clk_core **clks; static struct clk_onecell_data clk_data; @@ -195,8 +195,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) for_each_node_by_type(dn, "cpu") { struct clk_init_data init; - struct clk *clk; - struct clk *parent_clk; + struct clk_core *clk; + struct clk_core *parent_clk; char *clk_name = kzalloc(5, GFP_KERNEL); int cpu, err; @@ -208,7 +208,7 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out; sprintf(clk_name, "cpu%d", cpu); - parent_clk = of_clk_get(node, 0); + parent_clk = of_clk_provider_get(node, 0); cpuclk[cpu].parent_name = __clk_get_name(parent_clk); cpuclk[cpu].clk_name = clk_name; diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 8145c4e..489cb65 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -43,7 +43,7 @@ void __init mvebu_coreclk_setup(struct device_node *np, /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; - clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { iounmap(base); @@ -93,13 +93,13 @@ DEFINE_SPINLOCK(ctrl_gating_lock); struct clk_gating_ctrl { spinlock_t *lock; - struct clk **gates; + struct clk_core **gates; int num_gates; }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) -static struct clk *clk_gating_get_src( +static struct clk_core *clk_gating_get_src( struct of_phandle_args *clkspec, void *data) { struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data; @@ -121,7 +121,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, const struct clk_gating_soc_desc *desc) { struct clk_gating_ctrl *ctrl; - struct clk *clk; + struct clk_core *clk; void __iomem *base; const char *default_parent = NULL; int n; @@ -130,10 +130,10 @@ void __init mvebu_clk_gating_setup(struct device_node *np, if (WARN_ON(!base)) return; - clk = of_clk_get(np, 0); + clk = of_clk_provider_get(np, 0); if (!IS_ERR(clk)) { default_parent = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); @@ -148,7 +148,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, n++; ctrl->num_gates = n; - ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), + ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!ctrl->gates)) goto gates_out; diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c index d5c5786..1334970 100644 --- a/drivers/clk/mvebu/kirkwood.c +++ b/drivers/clk/mvebu/kirkwood.c @@ -242,7 +242,7 @@ struct clk_muxing_soc_desc { struct clk_muxing_ctrl { spinlock_t *lock; - struct clk **muxes; + struct clk_core **muxes; int num_muxes; }; @@ -258,7 +258,7 @@ static const struct clk_muxing_soc_desc kirkwood_mux_desc[] __initconst = { #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) -static struct clk *clk_muxing_get_src( +static struct clk_core *clk_muxing_get_src( struct of_phandle_args *clkspec, void *data) { struct clk_muxing_ctrl *ctrl = (struct clk_muxing_ctrl *)data; @@ -299,7 +299,7 @@ static void __init kirkwood_clk_muxing_setup(struct device_node *np, n++; ctrl->num_muxes = n; - ctrl->muxes = kzalloc(ctrl->num_muxes * sizeof(struct clk *), + ctrl->muxes = kzalloc(ctrl->num_muxes * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!ctrl->muxes)) goto muxes_out; diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c index 90e1da9..57f93e5 100644 --- a/drivers/clk/mxs/clk-div.c +++ b/drivers/clk/mxs/clk-div.c @@ -74,11 +74,11 @@ static struct clk_ops clk_div_ops = { .set_rate = clk_div_set_rate, }; -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_div *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; div = kzalloc(sizeof(*div), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c index e6aa6b5..87083e4 100644 --- a/drivers/clk/mxs/clk-frac.c +++ b/drivers/clk/mxs/clk-frac.c @@ -108,11 +108,11 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; frac = kzalloc(sizeof(*frac), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 9fc9359..fc7fdf2 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -94,7 +94,7 @@ enum imx23_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx23_clk clks_init_on[] __initdata = { @@ -171,7 +171,7 @@ static void __init mx23_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init); diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index a6c3501..083add7 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -148,7 +148,7 @@ enum imx28_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx28_clk clks_init_on[] __initdata = { @@ -250,6 +250,6 @@ static void __init mx28_clocks_init(struct device_node *np) clk_register_clkdev(clks[enet_out], NULL, "enet_out"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init); diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c index fadae41..8e29d79 100644 --- a/drivers/clk/mxs/clk-pll.c +++ b/drivers/clk/mxs/clk-pll.c @@ -86,11 +86,11 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate) { struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 4adeed6..ad1aa00 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -125,11 +125,11 @@ static const struct clk_ops clk_ref_ops = { .set_rate = clk_ref_set_rate, }; -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_ref *ref; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; ref = kzalloc(sizeof(*ref), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h index ef10ad9..b258ea5 100644 --- a/drivers/clk/mxs/clk.h +++ b/drivers/clk/mxs/clk.h @@ -23,24 +23,24 @@ extern spinlock_t mxs_lock; int mxs_clk_wait(void __iomem *reg, u8 shift); -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate); -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -static inline struct clk *mxs_clk_fixed(const char *name, int rate) +static inline struct clk_core *mxs_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mxs_clk_gate(const char *name, +static inline struct clk_core *mxs_clk_gate(const char *name, const char *parent_name, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, @@ -48,7 +48,7 @@ static inline struct clk *mxs_clk_gate(const char *name, &mxs_lock); } -static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *mxs_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parent_names, int num_parents) { return clk_register_mux(NULL, name, parent_names, num_parents, @@ -56,7 +56,7 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, reg, shift, width, 0, &mxs_lock); } -static inline struct clk *mxs_clk_fixed_factor(const char *name, +static inline struct clk_core *mxs_clk_fixed_factor(const char *name, const char *parent_name, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent_name, diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index b638c58..59f118c 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -375,7 +375,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -402,7 +402,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg *rcg = to_clk_rcg(hw); @@ -410,7 +410,7 @@ static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, } static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); @@ -418,7 +418,7 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, } static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg *rcg = to_clk_rcg(hw); const struct freq_tbl *f = rcg->freq_tbl; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index cd185d5..6aac1ec 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -188,7 +188,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -219,7 +219,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -372,7 +372,7 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, } static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -423,7 +423,7 @@ const struct clk_ops clk_edp_pixel_ops = { EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -485,14 +485,14 @@ static const struct frac_entry frac_table_pixel[] = { }; static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); unsigned long request, src_rate; int delta = 100000; const struct freq_tbl *f = rcg->freq_tbl; const struct frac_entry *frac = frac_table_pixel; - struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src); + struct clk_core *parent = *p = clk_get_parent_by_index(hw->clk, f->src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; @@ -519,7 +519,7 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, int delta = 100000; u32 mask = BIT(rcg->hid_width) - 1; u32 hid_div; - struct clk *parent = clk_get_parent_by_index(hw->clk, f.src); + struct clk_core *parent = clk_get_parent_by_index(hw->clk, f.src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; diff --git a/drivers/clk/qcom/clk-regmap.c b/drivers/clk/qcom/clk-regmap.c index a58ba39..2a98040 100644 --- a/drivers/clk/qcom/clk-regmap.c +++ b/drivers/clk/qcom/clk-regmap.c @@ -101,7 +101,7 @@ EXPORT_SYMBOL_GPL(clk_disable_regmap); * clk_regmap struct via this function so that the regmap is initialized * and so that the clock is registered with the common clock framework. */ -struct clk *devm_clk_register_regmap(struct device *dev, +struct clk_core *devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) { if (dev && dev_get_regmap(dev, NULL)) diff --git a/drivers/clk/qcom/clk-regmap.h b/drivers/clk/qcom/clk-regmap.h index 491a63d..89258cb 100644 --- a/drivers/clk/qcom/clk-regmap.h +++ b/drivers/clk/qcom/clk-regmap.h @@ -39,7 +39,7 @@ struct clk_regmap { int clk_is_enabled_regmap(struct clk_hw *hw); int clk_enable_regmap(struct clk_hw *hw); void clk_disable_regmap(struct clk_hw *hw); -struct clk * +struct clk_core * devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk); #endif diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index eeb3eea..afd40ea 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -24,7 +24,7 @@ struct qcom_cc { struct qcom_reset_controller reset; struct clk_onecell_data data; - struct clk *clks[]; + struct clk_core *clks[]; }; struct regmap * @@ -48,9 +48,9 @@ int qcom_cc_really_probe(struct platform_device *pdev, { int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct clk_onecell_data *data; - struct clk **clks; + struct clk_core **clks; struct qcom_reset_controller *reset; struct qcom_cc *cc; size_t num_clks = desc->num_clks; diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c index 0c4b727..2d41fdb 100644 --- a/drivers/clk/qcom/gcc-msm8660.c +++ b/drivers/clk/qcom/gcc-msm8660.c @@ -2718,7 +2718,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); static int gcc_msm8660_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; /* Temporary until RPM clocks supported */ diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 007534f..ed8f8f5 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -3488,7 +3488,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table); static int gcc_msm8960_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; const struct of_device_id *match; diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 7af7c18..8326b1f 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -2699,7 +2699,7 @@ static void msm8974_pro_clock_override(void) static int gcc_msm8974_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; bool pro; const struct of_device_id *id; diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 2e80a21..bb60d61 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -505,7 +505,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) int ret = 0; u32 val; struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); - struct clk *clk = hw->clk; + struct clk_core *clk = hw->clk; int num_parents = __clk_get_num_parents(hw->clk); /* @@ -517,7 +517,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) * needs to be on at what time. */ for (i = 0; i < num_parents; i++) { - ret = clk_prepare_enable(clk_get_parent_by_index(clk, i)); + ret = clk_provider_prepare_enable(clk_get_parent_by_index(clk, i)); if (ret) goto err; } @@ -546,7 +546,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) err: for (i--; i >= 0; i--) - clk_disable_unprepare(clk_get_parent_by_index(clk, i)); + clk_provider_disable_unprepare(clk_get_parent_by_index(clk, i)); return ret; } diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index f2a1c7a..3b82a43 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -297,7 +297,7 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { * Common registering of pll clocks */ -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, +struct clk_core *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, @@ -308,7 +308,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, struct clk_init_data init; struct rockchip_clk_pll *pll; struct clk_mux *pll_mux; - struct clk *pll_clk, *mux_clk; + struct clk_core *pll_clk, *mux_clk; char pll_name[20]; int ret; @@ -377,7 +377,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, goto err_pll; } - ret = clk_notifier_register(pll_clk, &pll->clk_nb); + ret = clk_provider_notifier_register(pll_clk, &pll->clk_nb); if (ret) { pr_err("%s: failed to register clock notifier for %s : %d\n", __func__, name, ret); @@ -417,7 +417,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, return mux_clk; err_mux: - ret = clk_notifier_unregister(pll_clk, &pll->clk_nb); + ret = clk_provider_notifier_unregister(pll_clk, &pll->clk_nb); if (ret) { pr_err("%s: could not unregister clock notifier in error path : %d\n", __func__, ret); diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index a83a6d8..89b2a17 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { static void __init rk3188_common_clk_init(struct device_node *np) { void __iomem *reg_base; - struct clk *clk; + struct clk_core *clk; reg_base = of_iomap(np, 0); if (!reg_base) { diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 0d8c6c5..f52f73e 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -683,7 +683,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { static void __init rk3288_clk_init(struct device_node *np) { void __iomem *reg_base; - struct clk *clk; + struct clk_core *clk; reg_base = of_iomap(np, 0); if (!reg_base) { diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c index 4cf838d5..faa8dfa 100644 --- a/drivers/clk/rockchip/clk-rockchip.c +++ b/drivers/clk/rockchip/clk-rockchip.c @@ -54,7 +54,7 @@ static void __init rk2928_gate_clk_init(struct device_node *node) if (!clk_data) return; - clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc(qty * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 278cf9d..66d6348 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -37,7 +37,7 @@ * * sometimes without one of those components. */ -struct clk *rockchip_clk_register_branch(const char *name, +struct clk_core *rockchip_clk_register_branch(const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, @@ -45,7 +45,7 @@ struct clk *rockchip_clk_register_branch(const char *name, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) { - struct clk *clk; + struct clk_core *clk; struct clk_mux *mux = NULL; struct clk_gate *gate = NULL; struct clk_divider *div = NULL; @@ -104,7 +104,7 @@ struct clk *rockchip_clk_register_branch(const char *name, } static DEFINE_SPINLOCK(clk_lock); -static struct clk **clk_table; +static struct clk_core **clk_table; static void __iomem *reg_base; static struct clk_onecell_data clk_data; static struct device_node *cru_node; @@ -117,7 +117,7 @@ void __init rockchip_clk_init(struct device_node *np, void __iomem *base, cru_node = np; grf = ERR_PTR(-EPROBE_DEFER); - clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); + clk_table = kcalloc(nr_clks, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_table) pr_err("%s: could not allocate clock lookup table\n", __func__); @@ -133,7 +133,7 @@ struct regmap *rockchip_clk_get_grf(void) return grf; } -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) +void rockchip_clk_add_lookup(struct clk_core *clk, unsigned int id) { if (clk_table && id) clk_table[id] = clk; @@ -142,7 +142,7 @@ void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) { - struct clk *clk; + struct clk_core *clk; int idx; for (idx = 0; idx < nr_pll; idx++, list++) { @@ -165,7 +165,7 @@ void __init rockchip_clk_register_branches( struct rockchip_clk_branch *list, unsigned int nr_clk) { - struct clk *clk = NULL; + struct clk_core *clk = NULL; unsigned int idx; unsigned long flags; diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 887cbde..8d761ba 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -113,7 +113,7 @@ struct rockchip_pll_clock { .rate_table = _rtable, \ } -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, +struct clk_core *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int con_offset, int grf_lock_offset, int lock_shift, int reg_mode, int mode_shift, @@ -324,7 +324,7 @@ struct rockchip_clk_branch { void rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); struct regmap *rockchip_clk_get_grf(void); -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id); +void rockchip_clk_add_lookup(struct clk_core *clk, unsigned int id); void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list, unsigned int nr_clk); void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list, diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 13eae14c..f5639bf 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -26,7 +26,7 @@ enum exynos_audss_clk_type { }; static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; +static struct clk_core **clk_table; static void __iomem *reg_base; static struct clk_onecell_data clk_data; @@ -83,7 +83,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; const char *sclk_pcm_p = "sclk_pcm0"; - struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; + struct clk_core *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; const struct of_device_id *match; enum exynos_audss_clk_type variant; @@ -100,7 +100,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + sizeof(struct clk_core *) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -111,8 +111,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) else clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1; - pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); - pll_in = devm_clk_get(&pdev->dev, "pll_in"); + pll_ref = devm_clk_provider_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_provider_get(&pdev->dev, "pll_in"); if (!IS_ERR(pll_ref)) mout_audss_p[0] = __clk_get_name(pll_ref); if (!IS_ERR(pll_in)) @@ -122,8 +122,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); - cdclk = devm_clk_get(&pdev->dev, "cdclk"); - sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + cdclk = devm_clk_provider_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_provider_get(&pdev->dev, "sclk_audio"); if (!IS_ERR(cdclk)) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) @@ -161,7 +161,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); - sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + sclk_pcm_in = devm_clk_provider_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 3a7cb25..50eea66 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -30,7 +30,7 @@ struct exynos_clkout { struct clk_mux mux; spinlock_t slock; struct clk_onecell_data data; - struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS]; + struct clk_core *clk_table[EXYNOS_CLKOUT_NR_CLKS]; void __iomem *reg; u32 pmu_debug_save; }; @@ -57,7 +57,7 @@ static struct syscore_ops exynos_clkout_syscore_ops = { static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) { const char *parent_names[EXYNOS_CLKOUT_PARENTS]; - struct clk *parents[EXYNOS_CLKOUT_PARENTS]; + struct clk_core *parents[EXYNOS_CLKOUT_PARENTS]; int parent_count; int ret; int i; @@ -73,7 +73,7 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) char name[] = "clkoutXX"; snprintf(name, sizeof(name), "clkout%d", i); - parents[i] = of_clk_get_by_name(node, name); + parents[i] = of_clk_provider_get_by_name(node, name); if (IS_ERR(parents[i])) { parent_names[i] = "none"; continue; @@ -125,7 +125,7 @@ err_unmap: clks_put: for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) if (!IS_ERR(parents[i])) - clk_put(parents[i]); + __clk_put(parents[i]); free_clkout: kfree(clkout); diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ac163d7..9a2270b 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1230,19 +1230,19 @@ static unsigned long exynos4_get_xom(void) static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) { struct samsung_fixed_rate_clock fclk; - struct clk *clk; + struct clk_core *clk; unsigned long finpll_f = 24000000; char *parent_name; unsigned int xom = exynos4_get_xom(); parent_name = xom & 1 ? "xusbxti" : "xxti"; - clk = clk_get(NULL, parent_name); + clk = clk_provider_get(NULL, parent_name); if (IS_ERR(clk)) { pr_err("%s: failed to lookup parent clock %s, assuming " "fin_pll clock frequency is 24MHz\n", __func__, parent_name); } else { - finpll_f = clk_get_rate(clk); + finpll_f = clk_provider_get_rate(clk); } fclk.id = CLK_FIN_PLL; diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..aaf234a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -910,12 +910,12 @@ static const struct clk_ops samsung_pll2550x_clk_ops = { .recalc_rate = samsung_pll2550x_recalc_rate, }; -struct clk * __init samsung_clk_register_pll2550x(const char *name, +struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset) { struct samsung_clk_pll2550x *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -1149,7 +1149,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, void __iomem *base) { struct samsung_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int ret, len; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..81af344 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -97,7 +97,7 @@ struct samsung_pll_rate_table { unsigned int vsel; }; -extern struct clk * __init samsung_clk_register_pll2550x(const char *name, +extern struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset); diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c index 0449cc0..05354bd 100644 --- a/drivers/clk/samsung/clk-s3c2410-dclk.c +++ b/drivers/clk/samsung/clk-s3c2410-dclk.c @@ -87,12 +87,12 @@ const struct clk_ops s3c24xx_clkout_ops = { .determine_rate = __clk_mux_determine_rate, }; -struct clk *s3c24xx_register_clkout(struct device *dev, const char *name, +struct clk_core *s3c24xx_register_clkout(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u8 shift, u32 mask) { struct s3c24xx_clkout *clkout; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the clkout */ @@ -237,7 +237,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk; struct resource *mem; - struct clk **clk_table; + struct clk_core **clk_table; struct s3c24xx_dclk_drv_data *dclk_variant; int ret, i; @@ -251,7 +251,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) spin_lock_init(&s3c24xx_dclk->dclk_lock); clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * DCLK_MAX_CLKS, + sizeof(struct clk_core *) * DCLK_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -329,21 +329,21 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) s3c24xx_dclk->dclk1_div_change_nb.notifier_call = s3c24xx_dclk1_div_notify; - ret = clk_notifier_register(clk_table[DIV_DCLK0], - &s3c24xx_dclk->dclk0_div_change_nb); + ret = clk_provider_notifier_register(clk_table[DIV_DCLK0], + &s3c24xx_dclk->dclk0_div_change_nb); if (ret) goto err_clk_register; - ret = clk_notifier_register(clk_table[DIV_DCLK1], - &s3c24xx_dclk->dclk1_div_change_nb); + ret = clk_provider_notifier_register(clk_table[DIV_DCLK1], + &s3c24xx_dclk->dclk1_div_change_nb); if (ret) goto err_dclk_notify; return 0; err_dclk_notify: - clk_notifier_unregister(clk_table[DIV_DCLK0], - &s3c24xx_dclk->dclk0_div_change_nb); + clk_provider_notifier_unregister(clk_table[DIV_DCLK0], + &s3c24xx_dclk->dclk0_div_change_nb); err_clk_register: for (i = 0; i < DCLK_MAX_CLKS; i++) if (clk_table[i] && !IS_ERR(clk_table[i])) @@ -355,13 +355,13 @@ err_clk_register: static int s3c24xx_dclk_remove(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); - struct clk **clk_table = s3c24xx_dclk->clk_data.clks; + struct clk_core **clk_table = s3c24xx_dclk->clk_data.clks; int i; - clk_notifier_unregister(clk_table[DIV_DCLK1], - &s3c24xx_dclk->dclk1_div_change_nb); - clk_notifier_unregister(clk_table[DIV_DCLK0], - &s3c24xx_dclk->dclk0_div_change_nb); + clk_provider_notifier_unregister(clk_table[DIV_DCLK1], + &s3c24xx_dclk->dclk1_div_change_nb); + clk_provider_notifier_unregister(clk_table[DIV_DCLK0], + &s3c24xx_dclk->dclk0_div_change_nb); for (i = 0; i < DCLK_MAX_CLKS; i++) clk_unregister(clk_table[i]); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index deab84d..68133fa 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -52,14 +52,14 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks) { struct samsung_clk_provider *ctx; - struct clk **clk_table; + struct clk_core **clk_table; int i; ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); if (!ctx) panic("could not allocate clock provider context.\n"); - clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); + clk_table = kcalloc(nr_clks, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_table) panic("could not allocate clock lookup table\n"); @@ -85,7 +85,7 @@ void __init samsung_clk_of_add_provider(struct device_node *np, } /* add a clock instance to the clock lookup table used for dt based lookup */ -void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, +void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk_core *clk, unsigned int id) { if (ctx->clk_data.clks && id) @@ -97,7 +97,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; if (!ctx->clk_data.clks) { @@ -130,7 +130,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -159,7 +159,7 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -180,7 +180,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, struct samsung_mux_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -212,7 +212,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, struct samsung_div_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -251,7 +251,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, struct samsung_gate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -303,7 +303,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, /* utility function to get the rate of a specified clock */ unsigned long _get_rate(const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = __clk_lookup(clk_name); if (!clk) { @@ -311,5 +311,5 @@ unsigned long _get_rate(const char *clk_name) return 0; } - return clk_get_rate(clk); + return clk_provider_get_rate(clk); } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 66ab36b..a13c8b2 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -336,7 +336,7 @@ extern void __init samsung_clk_of_register_fixed_ext( const struct of_device_id *clk_matches); extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, - struct clk *clk, unsigned int id); + struct clk_core *clk, unsigned int id); extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index f065f69..c6712fb 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -119,7 +119,7 @@ static void __init cpg_div6_clock_init(struct device_node *np) struct div6_clock *clock; const char *parent_name; const char *name; - struct clk *clk; + struct clk_core *clk; int ret; clock = kzalloc(sizeof(*clock), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-emev2.c b/drivers/clk/shmobile/clk-emev2.c index 6c7c929..2e3a45b 100644 --- a/drivers/clk/shmobile/clk-emev2.c +++ b/drivers/clk/shmobile/clk-emev2.c @@ -71,7 +71,7 @@ static void __init emev2_smu_init(void) static void __init emev2_smu_clkdiv_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; @@ -89,7 +89,7 @@ CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv", static void __init emev2_smu_gclk_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c index 2d2fe77..2659676 100644 --- a/drivers/clk/shmobile/clk-mstp.c +++ b/drivers/clk/shmobile/clk-mstp.c @@ -121,13 +121,13 @@ static const struct clk_ops cpg_mstp_clock_ops = { .is_enabled = cpg_mstp_clock_is_enabled, }; -static struct clk * __init +static struct clk_core * __init cpg_mstp_clock_register(const char *name, const char *parent_name, unsigned int index, struct mstp_clock_group *group) { struct clk_init_data init; struct mstp_clock *clock; - struct clk *clk; + struct clk_core *clk; clock = kzalloc(sizeof(*clock), GFP_KERNEL); if (!clock) { @@ -157,7 +157,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) { struct mstp_clock_group *group; const char *idxname; - struct clk **clks; + struct clk_core **clks; unsigned int i; group = kzalloc(sizeof(*group), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-r8a7740.c b/drivers/clk/shmobile/clk-r8a7740.c index 1e2eaae..8889e6a 100644 --- a/drivers/clk/shmobile/clk-r8a7740.c +++ b/drivers/clk/shmobile/clk-r8a7740.c @@ -61,7 +61,7 @@ static const struct clk_div_table div4_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, const char *name) { @@ -147,7 +147,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, static void __init r8a7740_cpg_clocks_init(struct device_node *np) { struct r8a7740_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -180,7 +180,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c index 652ecac..96b51b1 100644 --- a/drivers/clk/shmobile/clk-r8a7779.c +++ b/drivers/clk/shmobile/clk-r8a7779.c @@ -90,7 +90,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, const struct cpg_clk_config *config, unsigned int plla_mult, const char *name) @@ -124,7 +124,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) { const struct cpg_clk_config *config; struct r8a7779_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i, plla_mult; int num_clks; @@ -153,7 +153,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index dff7f79..d8bdeb8 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -133,12 +133,12 @@ static const struct clk_ops cpg_z_clk_ops = { .set_rate = cpg_z_clk_set_rate, }; -static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) +static struct clk_core * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) { static const char *parent_name = "pll0"; struct clk_init_data init; struct cpg_z_clk *zclk; - struct clk *clk; + struct clk_core *clk; zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); if (!zclk) @@ -212,7 +212,7 @@ static const struct clk_div_table cpg_sd01_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, const struct cpg_pll_config *config, const char *name) @@ -279,7 +279,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) { const struct cpg_pll_config *config; struct rcar_gen2_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -312,7 +312,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c index 7e68e86..414e20e 100644 --- a/drivers/clk/shmobile/clk-rz.c +++ b/drivers/clk/shmobile/clk-rz.c @@ -28,7 +28,7 @@ struct rz_cpg { * Initialization */ -static struct clk * __init +static struct clk_core * __init rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) { u32 val; @@ -67,7 +67,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static void __init rz_cpg_clocks_init(struct device_node *np) { struct rz_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned i; int num_clks; @@ -86,7 +86,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/sirf/clk-atlas6.c b/drivers/clk/sirf/clk-atlas6.c index d63b76c..9cce269 100644 --- a/drivers/clk/sirf/clk-atlas6.c +++ b/drivers/clk/sirf/clk-atlas6.c @@ -113,7 +113,7 @@ static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *atlas6_clks[maxclk]; +static struct clk_core *atlas6_clks[maxclk]; static void __init atlas6_clk_init(struct device_node *np) { diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c index 37af51c..05f5040 100644 --- a/drivers/clk/sirf/clk-common.c +++ b/drivers/clk/sirf/clk-common.c @@ -165,9 +165,9 @@ static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, * SiRF SoC has not cpu clock control, * So bypass to it's parent pll. */ - struct clk *parent_clk = clk_get_parent(hw->clk); - struct clk *pll_parent_clk = clk_get_parent(parent_clk); - unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); + struct clk_core *pll_parent_clk = clk_provider_get_parent(parent_clk); + unsigned long pll_parent_rate = clk_provider_get_rate(pll_parent_clk); return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate); } @@ -178,7 +178,7 @@ static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, * SiRF SoC has not cpu clock control, * So return the parent pll rate. */ - struct clk *parent_clk = clk_get_parent(hw->clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); return __clk_get_rate(parent_clk); } @@ -403,34 +403,34 @@ static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int ret1, ret2; - struct clk *cur_parent; + struct clk_core *cur_parent; - if (rate == clk_get_rate(clk_pll1.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + if (rate == clk_provider_get_rate(clk_pll1.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll2.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + if (rate == clk_provider_get_rate(clk_pll2.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll3.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); + if (rate == clk_provider_get_rate(clk_pll3.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll3.hw.clk); return ret1; } - cur_parent = clk_get_parent(hw->clk); + cur_parent = clk_provider_get_parent(hw->clk); /* switch to tmp pll before setting parent clock's rate */ if (cur_parent == clk_pll1.hw.clk) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); BUG_ON(ret1); } - ret2 = clk_set_rate(clk_pll1.hw.clk, rate); + ret2 = clk_provider_set_rate(clk_pll1.hw.clk, rate); - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret2 ? ret2 : ret1; } diff --git a/drivers/clk/sirf/clk-prima2.c b/drivers/clk/sirf/clk-prima2.c index 6968e2e..751187b 100644 --- a/drivers/clk/sirf/clk-prima2.c +++ b/drivers/clk/sirf/clk-prima2.c @@ -112,7 +112,7 @@ static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *prima2_clks[maxclk]; +static struct clk_core *prima2_clks[maxclk]; static void __init prima2_clk_init(struct device_node *np) { diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index dd3a78c..e3a6fe6 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -188,7 +188,7 @@ static void __init __socfpga_gate_init(struct device_node *node, u32 div_reg[3]; u32 clk_phase[2]; u32 fixed_div; - struct clk *clk; + struct clk_core *clk; struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 46531c3..a63be19 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -53,7 +53,7 @@ static __init void __socfpga_periph_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index de6da95..4ed91a4 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -81,11 +81,11 @@ static struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static __init struct clk *__socfpga_pll_init(struct device_node *node, +static __init struct clk_core *__socfpga_pll_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c index bdfb442..18334c3 100644 --- a/drivers/clk/spear/clk-aux-synth.c +++ b/drivers/clk/spear/clk-aux-synth.c @@ -134,14 +134,14 @@ static struct clk_ops clk_aux_ops = { .set_rate = clk_aux_set_rate, }; -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk) { struct clk_aux *aux; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); @@ -177,7 +177,7 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name, goto free_aux; if (gate_name) { - struct clk *tgate_clk; + struct clk_core *tgate_clk; tgate_clk = clk_register_gate(NULL, gate_name, aux_name, CLK_SET_RATE_PARENT, reg, diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c index dffd4ce..bce2c0e 100644 --- a/drivers/clk/spear/clk-frac-synth.c +++ b/drivers/clk/spear/clk-frac-synth.c @@ -122,13 +122,13 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *clk_register_frac(const char *name, const char *parent_name, +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c index 1afc18c..f8e13f3 100644 --- a/drivers/clk/spear/clk-gpt-synth.c +++ b/drivers/clk/spear/clk-gpt-synth.c @@ -111,13 +111,13 @@ static struct clk_ops clk_gpt_ops = { .set_rate = clk_gpt_set_rate, }; -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_gpt *gpt; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c index 1b9b65b..226f2ec 100644 --- a/drivers/clk/spear/clk-vco-pll.c +++ b/drivers/clk/spear/clk-vco-pll.c @@ -272,16 +272,16 @@ static struct clk_ops clk_vco_ops = { .set_rate = clk_vco_set_rate, }; -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk) + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk) { struct clk_vco *vco; struct clk_pll *pll; - struct clk *vco_clk, *tpll_clk, *tvco_gate_clk; + struct clk_core *vco_clk, *tpll_clk, *tvco_gate_clk; struct clk_init_data vco_init, pll_init; const char **vco_parent_name; diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h index 9317376..777322e 100644 --- a/drivers/clk/spear/clk.h +++ b/drivers/clk/spear/clk.h @@ -110,22 +110,22 @@ typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, int index); /* clk register routines */ -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); -struct clk *clk_register_frac(const char *name, const char *parent_name, + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk); +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk); + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk); long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index 4daa597..1e95410 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c @@ -385,7 +385,7 @@ static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c index 5a5c664..f42965c 100644 --- a/drivers/clk/spear/spear1340_clock.c +++ b/drivers/clk/spear/spear1340_clock.c @@ -442,7 +442,7 @@ static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", void __init spear1340_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index bb5f387..5b8d659 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c @@ -140,7 +140,7 @@ static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", #ifdef CONFIG_MACH_SPEAR300 static void __init spear300_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 1, 1); @@ -170,7 +170,7 @@ static inline void spear300_clk_init(void) { } #ifdef CONFIG_MACH_SPEAR310 static void __init spear310_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 1); @@ -246,9 +246,9 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; static void __init spear320_clk_init(void __iomem *soc_config_base, - struct clk *ras_apb_clk) + struct clk_core *ras_apb_clk) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, CLK_IS_ROOT, 125000000); @@ -344,7 +344,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, 0, &_lock); clk_register_clkdev(clk, NULL, "a3000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -353,7 +353,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a4000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -384,12 +384,12 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, clk_register_clkdev(clk, NULL, "60100000.serial"); } #else -static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } +static inline void spear320_clk_init(void __iomem *sb, struct clk_core *rc) { } #endif void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) { - struct clk *clk, *clk1, *ras_apb_clk; + struct clk_core *clk, *clk1, *ras_apb_clk; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index 4f649c9..db946f7 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c @@ -116,7 +116,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = { void __init spear6xx_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c index 2282cef..699f7a1 100644 --- a/drivers/clk/st/clk-flexgen.c +++ b/drivers/clk/st/clk-flexgen.c @@ -163,12 +163,12 @@ static const struct clk_ops flexgen_ops = { .set_rate = flexgen_set_rate, }; -struct clk *clk_register_flexgen(const char *name, +struct clk_core *clk_register_flexgen(const char *name, const char **parent_names, u8 num_parents, void __iomem *reg, spinlock_t *lock, u32 idx, unsigned long flexgen_flags) { struct flexgen *fgxbar; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; u32 xbar_shift; void __iomem *xbar_reg, *fdiv_reg; @@ -223,8 +223,8 @@ struct clk *clk_register_flexgen(const char *name, else pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); return clk; } @@ -283,7 +283,7 @@ void __init st_of_flexgen_setup(struct device_node *np) goto err; } - clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), + clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; @@ -293,7 +293,7 @@ void __init st_of_flexgen_setup(struct device_node *np) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index af94ed8..ceda1f2 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -614,13 +614,13 @@ static const struct clk_ops st_quadfs_pll_c32_ops = { .set_rate = quadfs_pll_fs660c32_set_rate, }; -static struct clk * __init st_clk_register_quadfs_pll( +static struct clk_core * __init st_clk_register_quadfs_pll( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, spinlock_t *lock) { struct st_clk_quadfs_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -1018,13 +1018,13 @@ static const struct clk_ops st_quadfs_ops = { .recalc_rate = quadfs_recalc_rate, }; -static struct clk * __init st_clk_register_quadfs_fsynth( +static struct clk_core * __init st_clk_register_quadfs_fsynth( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, spinlock_t *lock) { struct st_clk_quadfs_fsynth *fs; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -1102,7 +1102,7 @@ static void __init st_of_create_quadfs_fsynths( return; clk_data->clk_num = QUADFS_MAX_CHAN; - clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *), + clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { @@ -1111,7 +1111,7 @@ static void __init st_of_create_quadfs_fsynths( } for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -1136,8 +1136,8 @@ static void __init st_of_create_quadfs_fsynths( clk_data->clks[fschan] = clk; pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); } } @@ -1147,7 +1147,7 @@ static void __init st_of_create_quadfs_fsynths( static void __init st_of_quadfs_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *pll_name, *clk_parent_name; void __iomem *reg; spinlock_t *lock; @@ -1181,8 +1181,8 @@ static void __init st_of_quadfs_setup(struct device_node *np) else pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); st_of_create_quadfs_fsynths(np, pll_name, (struct clkgen_quadfs_data *)match->data, diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c index 79dc40b..d2a951f 100644 --- a/drivers/clk/st/clkgen-mux.c +++ b/drivers/clk/st/clkgen-mux.c @@ -215,7 +215,7 @@ static const struct clk_ops clkgena_divmux_ops = { /** * clk_register_genamux - register a genamux clock with the clock framework */ -struct clk *clk_register_genamux(const char *name, +struct clk_core *clk_register_genamux(const char *name, const char **parent_names, u8 num_parents, void __iomem *reg, const struct clkgena_divmux_data *muxdata, @@ -227,7 +227,7 @@ struct clk *clk_register_genamux(const char *name, const int mux_width = 2; const int divider_width = 5; struct clkgena_divmux *genamux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int i; @@ -280,8 +280,8 @@ struct clk *clk_register_genamux(const char *name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); err: return clk; } @@ -413,14 +413,14 @@ void __init st_of_clkgena_divmux_setup(struct device_node *np) goto err; clk_data->clk_num = data->num_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -490,7 +490,7 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) const struct of_device_id *match; void __iomem *reg; const char *parent_name, *clk_name; - struct clk *clk; + struct clk_core *clk; struct clkgena_prediv_data *data; match = of_match_node(clkgena_prediv_of_match, np); @@ -522,8 +522,8 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) of_clk_add_provider(np, of_clk_src_simple_get, clk); pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); return; } @@ -625,7 +625,7 @@ static struct of_device_id mux_of_match[] = { void __init st_of_clkgen_mux_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; void __iomem *reg; const char **parents; int num_parents; @@ -662,8 +662,8 @@ void __init st_of_clkgen_mux_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); of_clk_add_provider(np, of_clk_src_simple_get, clk); @@ -726,14 +726,14 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) goto err; clk_data->clk_num = VCC_MAX_CHANNELS; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; struct clk_gate *gate; struct clk_divider *div; @@ -796,8 +796,8 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); clk_data->clks[i] = clk; } diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index 29769d7..32bac02 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -390,13 +390,13 @@ static const struct clk_ops st_pll1200c32_ops = { .recalc_rate = recalc_stm_pll1200c32, }; -static struct clk * __init clkgen_pll_register(const char *parent_name, +static struct clk_core * __init clkgen_pll_register(const char *parent_name, struct clkgen_pll_data *pll_data, void __iomem *reg, const char *clk_name) { struct clkgen_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -422,16 +422,16 @@ static struct clk * __init clkgen_pll_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } -static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, +static struct clk_core * __init clkgen_c65_lsdiv_register(const char *parent_name, const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2); if (IS_ERR(clk)) @@ -439,8 +439,8 @@ static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -484,7 +484,7 @@ static void __init clkgena_c65_pll_setup(struct device_node *np) return; clk_data->clk_num = num_pll_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) @@ -543,14 +543,14 @@ err: CLK_OF_DECLARE(clkgena_c65_plls, "st,clkgena-plls-c65", clkgena_c65_pll_setup); -static struct clk * __init clkgen_odf_register(const char *parent_name, +static struct clk_core * __init clkgen_odf_register(const char *parent_name, void * __iomem reg, struct clkgen_pll_data *pll_data, int odf, spinlock_t *odf_lock, const char *odf_name) { - struct clk *clk; + struct clk_core *clk; unsigned long flags; struct clk_gate *gate; struct clk_divider *div; @@ -588,8 +588,8 @@ static struct clk * __init clkgen_odf_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -640,7 +640,7 @@ static struct of_device_id c32_pll_of_match[] = { static void __init clkgen_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name, *pll_name; void __iomem *pll_base; int num_odfs, odf; @@ -676,14 +676,14 @@ static void __init clkgen_c32_pll_setup(struct device_node *np) return; clk_data->clk_num = num_odfs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (odf = 0; odf < num_odfs; odf++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -723,7 +723,7 @@ static struct of_device_id c32_gpu_pll_of_match[] = { static void __init clkgengpu_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; const char *clk_name; diff --git a/drivers/clk/sunxi/clk-a10-hosc.c b/drivers/clk/sunxi/clk-a10-hosc.c index 0481d5d..c5e4c41 100644 --- a/drivers/clk/sunxi/clk-a10-hosc.c +++ b/drivers/clk/sunxi/clk-a10-hosc.c @@ -25,7 +25,7 @@ static DEFINE_SPINLOCK(hosc_lock); static void __init sun4i_osc_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_fixed_rate *fixed; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c index 5296fd6..63c7dd5 100644 --- a/drivers/clk/sunxi/clk-a20-gmac.c +++ b/drivers/clk/sunxi/clk-a20-gmac.c @@ -55,7 +55,7 @@ static DEFINE_SPINLOCK(gmac_lock); static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_mux *mux; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c index 2057c8a..bb2d4b2 100644 --- a/drivers/clk/sunxi/clk-factors.c +++ b/drivers/clk/sunxi/clk-factors.c @@ -79,9 +79,9 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate, static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { - struct clk *clk = hw->clk, *parent, *best_parent = NULL; + struct clk_core *clk = hw->clk, *parent, *best_parent = NULL; int i, num_parents; unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c index e10d052..f29b06e 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c @@ -74,7 +74,7 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev) /* Worst-case size approximation and memory allocation */ ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE); clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1), - sizeof(struct clk *), GFP_KERNEL); + sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) return -ENOMEM; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c index 1fa2337..5e4649e 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0.c @@ -35,7 +35,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev) const char *clk_parent; struct resource *r; void __iomem *reg; - struct clk *clk; + struct clk_core *clk; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, r); diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c index eca8ca0..984d5d0 100644 --- a/drivers/clk/sunxi/clk-sun6i-ar100.c +++ b/drivers/clk/sunxi/clk-sun6i-ar100.c @@ -46,7 +46,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw, static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { int nparents = __clk_get_num_parents(hw->clk); long best_rate = -EINVAL; @@ -57,7 +57,7 @@ static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, for (i = 0; i < nparents; i++) { unsigned long parent_rate; unsigned long tmp_rate; - struct clk *parent; + struct clk_core *parent; unsigned long div; int shift; @@ -176,7 +176,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev) struct clk_init_data init; struct ar100_clk *ar100; struct resource *r; - struct clk *clk; + struct clk_core *clk; int nparents; int i; diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c index 1f5ba9b..fa308fd 100644 --- a/drivers/clk/sunxi/clk-sun8i-apb0.c +++ b/drivers/clk/sunxi/clk-sun8i-apb0.c @@ -26,7 +26,7 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev) const char *clk_parent; struct resource *r; void __iomem *reg; - struct clk *clk; + struct clk_core *clk; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, r); diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index b654b7b..44c4470 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -403,7 +403,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, * clk_sunxi_mmc_phase_control() - configures MMC clock phase control */ -void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output) +void clk_sunxi_mmc_phase_control(struct clk_core *clk, u8 sample, u8 output) { #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) @@ -582,10 +582,10 @@ static const struct factors_data sun7i_a20_out_data __initconst = { .getter = sun7i_a20_get_out_factors, }; -static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, +static struct clk_core * __init sunxi_factors_clk_setup(struct device_node *node, const struct factors_data *data) { - struct clk *clk; + struct clk_core *clk; struct clk_factors *factors; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; @@ -695,7 +695,7 @@ static const struct mux_data sun4i_apb1_mux_data __initconst = { static void __init sunxi_mux_clk_setup(struct device_node *node, struct mux_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parents[SUNXI_MAX_PARENTS]; void __iomem *reg; @@ -777,7 +777,7 @@ static const struct div_data sun6i_a31_apb2_div_data __initconst = { static void __init sunxi_divider_clk_setup(struct device_node *node, struct div_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *clk_parent; void __iomem *reg; @@ -976,7 +976,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) return; - clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; @@ -1078,7 +1078,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, struct clk_onecell_data *clk_data; const char *parent; const char *clk_name; - struct clk **clks, *pclk; + struct clk_core **clks, *pclk; struct clk_hw *gate_hw, *rate_hw; const struct clk_ops *rate_ops; struct clk_gate *gate = NULL; @@ -1291,10 +1291,10 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks) /* Protect the clocks that needs to stay on */ for (i = 0; i < nclocks; i++) { - struct clk *clk = clk_get(NULL, clocks[i]); + struct clk_core *clk = clk_provider_get(NULL, clocks[i]); if (!IS_ERR(clk)) - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); } } diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c index c0f7843..53c3488 100644 --- a/drivers/clk/tegra/clk-audio-sync.c +++ b/drivers/clk/tegra/clk-audio-sync.c @@ -54,12 +54,12 @@ const struct clk_ops tegra_clk_sync_source_ops = { .recalc_rate = clk_sync_source_recalc_rate, }; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long rate, unsigned long max_rate) { struct tegra_clk_sync_source *sync; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; sync = kzalloc(sizeof(*sync), GFP_KERNEL); if (!sync) { diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 290f9c1..7a1212b7 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -147,13 +147,13 @@ const struct clk_ops tegra_clk_frac_div_ops = { .round_rate = clk_frac_div_round_rate, }; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock) { struct tegra_clk_frac_div *divider; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; divider = kzalloc(sizeof(*divider), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 0aa8830..61f5d55 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -128,12 +128,12 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .disable = clk_periph_disable, }; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt) { struct tegra_clk_periph_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *pregs; diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 9e899c18..ea26de3 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -138,13 +138,13 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = { .set_rate = clk_periph_set_rate, }; -static struct clk *_tegra_clk_register_periph(const char *name, +static struct clk_core *_tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *bank; bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); @@ -186,7 +186,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, return clk; } -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) @@ -195,7 +195,7 @@ struct clk *tegra_clk_register_periph(const char *name, periph, clk_base, offset, flags); } -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset) diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 3598987..49ae7b1 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -87,13 +87,13 @@ const struct clk_ops tegra_clk_pll_out_ops = { .disable = clk_pll_out_disable, }; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags, spinlock_t *lock) { struct tegra_clk_pll_out *pll_out; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c7c6d8f..cb61b7d 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -729,7 +729,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) static int clk_plle_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); struct tegra_clk_pll_freq_table sel; u32 val; int err; @@ -1033,7 +1033,7 @@ static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, state = clk_pll_is_enabled(hw); if (state) { - if (rate != clk_get_rate(hw->clk)) { + if (rate != clk_provider_get_rate(hw->clk)) { pr_err("%s: Cannot change active PLLM\n", __func__); ret = -EINVAL; goto out; @@ -1285,7 +1285,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) u32 val; int ret; unsigned long flags = 0; - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) return -EINVAL; @@ -1430,7 +1430,7 @@ static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, return pll; } -static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, +static struct clk_core *_tegra_clk_register_pll(struct tegra_clk_pll *pll, const char *name, const char *parent_name, unsigned long flags, const struct clk_ops *ops) { @@ -1448,13 +1448,13 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, return clk_register(NULL, &pll->hw); } -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1479,13 +1479,13 @@ static struct div_nmp pll_e_nmp = { .divp_width = PLLE_BASE_DIVP_WIDTH, }; -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1550,14 +1550,14 @@ static const struct clk_ops tegra_clk_plle_tegra114_ops = { }; -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; int err; u32 val, val_iddq; @@ -1603,7 +1603,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, @@ -1611,7 +1611,7 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, { u32 val; struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; @@ -1649,14 +1649,14 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; if (!pll_params->pdiv_tohw) @@ -1688,13 +1688,13 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { - struct clk *parent, *clk; + struct clk_core *parent, *clk; struct pdiv_map *p_tohw = pll_params->pdiv_tohw; struct tegra_clk_pll *pll; struct tegra_clk_pll_freq_table cfg; @@ -1762,14 +1762,14 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 val, val_aux; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1812,13 +1812,13 @@ static const struct clk_ops tegra_clk_pllss_ops = { .set_rate = clk_pllxc_set_rate, }; -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; struct tegra_clk_pll_freq_table cfg; unsigned long parent_rate; u32 val; diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 2fd924d..e843d20 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -127,13 +127,13 @@ const struct clk_ops tegra_clk_super_ops = { .set_parent = clk_super_set_parent, }; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock) { struct tegra_clk_super_mux *super; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; super = kzalloc(sizeof(*super), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c index 5c38aab..484a900 100644 --- a/drivers/clk/tegra/clk-tegra-audio.c +++ b/drivers/clk/tegra/clk-tegra-audio.c @@ -128,8 +128,8 @@ void __init tegra_audio_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_a_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; /* PLLA */ diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index f3b7738..503e261 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -36,8 +36,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, unsigned long *osc_freq, unsigned long *pll_ref_freq) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; u32 val, pll_ref_div; unsigned osc_idx; @@ -81,8 +81,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* clk_32k */ dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 37f32c4..125dfa2 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -585,8 +585,8 @@ static void __init periph_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { struct tegra_clk_periph_regs *bank; @@ -615,8 +615,8 @@ static void __init gate_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { struct tegra_periph_init_data *data; @@ -640,8 +640,8 @@ static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c index 08b21c1..2ff427a 100644 --- a/drivers/clk/tegra/clk-tegra-pmc.c +++ b/drivers/clk/tegra/clk-tegra-pmc.c @@ -82,8 +82,8 @@ static struct pmc_clk_init_data pmc_clks[] = { void __init tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index feb3201..e6224c4 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -53,8 +53,8 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", static void __init tegra_sclk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* SCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); @@ -99,8 +99,8 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* CCLKG */ dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index f760f31..68efd84 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -936,14 +936,14 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = { [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, }; -static struct clk **clks; +static struct clk_core **clks; static unsigned long osc_freq; static unsigned long pll_ref_freq; static int __init tegra114_osc_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; u32 val, pll_ref_div; val = readl_relaxed(clk_base + OSC_CTRL); @@ -973,7 +973,7 @@ static int __init tegra114_osc_clk_init(void __iomem *clk_base) static void __init tegra114_fixed_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; /* clk_32k */ clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, @@ -1078,7 +1078,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, @@ -1200,7 +1200,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = { static __init void tegra114_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; struct tegra_periph_init_data *data; int i; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 9525c68..43f0632 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1017,7 +1017,7 @@ static struct tegra_devclk devclks[] __initdata = { { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, }; -static struct clk **clks; +static struct clk_core **clks; static void tegra124_utmi_param_configure(void __iomem *clk_base) { @@ -1104,7 +1104,7 @@ static void tegra124_utmi_param_configure(void __iomem *clk_base) static __init void tegra124_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; /* xusb_ss_div2 */ clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, @@ -1148,7 +1148,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index dace2b1..6783355 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -162,7 +162,7 @@ static void __iomem *pmc_base; _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { { 12000000, 600000000, 600, 12, 0, 8 }, @@ -633,7 +633,7 @@ static unsigned int tegra20_get_pll_ref_div(void) static void tegra20_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, @@ -713,7 +713,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void tegra20_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* CCLK */ clk = tegra_clk_register_super_mux("cclk", cclk_parents, @@ -738,7 +738,7 @@ static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", static void __init tegra20_audio_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* audio */ clk = clk_register_mux(NULL, "audio_mux", audio_parents, @@ -800,7 +800,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* ac97 */ @@ -871,7 +871,7 @@ static void __init tegra20_periph_clk_init(void) static void __init tegra20_osc_clk_init(void) { - struct clk *clk; + struct clk_core *clk; unsigned long input_freq; unsigned int pll_ref_div; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 5bbacd0..5a03645 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -205,7 +205,7 @@ static DEFINE_SPINLOCK(pll_d_lock); _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; /* * Structure defining the fields for USB UTMI clocks Parameters. @@ -921,7 +921,7 @@ static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; static void __init tegra30_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, @@ -1012,7 +1012,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void __init tegra30_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* * Clock input to cclk_g divided from pll_p using @@ -1134,7 +1134,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra30_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* dsia */ diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index f87c609..e90432c 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -69,7 +69,7 @@ struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; int *periph_clk_enb_refcnt; static int periph_banks; -static struct clk **clks; +static struct clk_core **clks; static int clk_num; static struct clk_onecell_data clk_data; @@ -165,7 +165,7 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } -struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) +struct clk_core ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; @@ -179,7 +179,7 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) periph_banks = banks; - clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); + clks = kzalloc(num * sizeof(struct clk_core *), GFP_KERNEL); if (!clks) kfree(periph_clk_enb_refcnt); @@ -189,9 +189,9 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) } void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; dup_list->clk_id < clk_max; dup_list++) { clk = clks[dup_list->clk_id]; @@ -201,9 +201,9 @@ void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, } void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; tbl->clk_id < clk_max; tbl++) { clk = clks[tbl->clk_id]; @@ -211,8 +211,8 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, return; if (tbl->parent_id < clk_max) { - struct clk *parent = clks[tbl->parent_id]; - if (clk_set_parent(clk, parent)) { + struct clk_core *parent = clks[tbl->parent_id]; + if (clk_provider_set_parent(clk, parent)) { pr_err("%s: Failed to set parent %s of %s\n", __func__, __clk_get_name(parent), __clk_get_name(clk)); @@ -221,7 +221,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->rate) - if (clk_set_rate(clk, tbl->rate)) { + if (clk_provider_set_rate(clk, tbl->rate)) { pr_err("%s: Failed to set rate %lu of %s\n", __func__, tbl->rate, __clk_get_name(clk)); @@ -229,7 +229,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->state) - if (clk_prepare_enable(clk)) { + if (clk_provider_prepare_enable(clk)) { pr_err("%s: Failed to enable %s\n", __func__, __clk_get_name(clk)); WARN_ON(1); @@ -286,7 +286,7 @@ void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num) } } -struct clk ** __init tegra_lookup_dt_id(int clk_id, +struct clk_core ** __init tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk) { if (tegra_clk[clk_id].present) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 16ec8d6..3093aa4 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -39,7 +39,7 @@ struct tegra_clk_sync_source { extern const struct clk_ops tegra_clk_sync_source_ops; extern int *periph_clk_enb_refcnt; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long fixed_rate, unsigned long max_rate); /** @@ -82,7 +82,7 @@ struct tegra_clk_frac_div { #define TEGRA_DIVIDER_UART BIT(3) extern const struct clk_ops tegra_clk_frac_div_ops; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); @@ -258,47 +258,47 @@ struct tegra_clk_pll { extern const struct clk_ops tegra_clk_pll_ops; extern const struct clk_ops tegra_clk_plle_ops; -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock, unsigned long parent_rate); -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); @@ -325,7 +325,7 @@ struct tegra_clk_pll_out { #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) extern const struct clk_ops tegra_clk_pll_out_ops; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, spinlock_t *lock); @@ -394,7 +394,7 @@ struct tegra_clk_periph_gate { #define TEGRA_PERIPH_NO_GATE BIT(5) extern const struct clk_ops tegra_clk_periph_gate_ops; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt); @@ -427,11 +427,11 @@ struct tegra_clk_periph { #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 extern const struct clk_ops tegra_clk_periph_ops; -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags); -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset); @@ -540,7 +540,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) extern const struct clk_ops tegra_clk_super_ops; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); @@ -590,15 +590,15 @@ struct tegra_devclk { }; void tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); struct tegra_clk_periph_regs *get_reg_bank(int clkid); -struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); +struct clk_core **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); -struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); +struct clk_core **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); void tegra_add_of_provider(struct device_node *np); void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index 72d9727..a162c21 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -135,10 +135,10 @@ static void __init omap_clk_register_apll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *ad = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - ad->clk_ref = of_clk_get(node, 0); - ad->clk_bypass = of_clk_get(node, 1); + ad->clk_ref = of_clk_provider_get(node, 0); + ad->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) { pr_debug("clk-ref or clk-bypass for %s not ready, retry\n", @@ -332,7 +332,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) struct dpll_data *ad = NULL; struct clk_hw_omap *clk_hw = NULL; struct clk_init_data *init = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name; u32 val; diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c index c808ab3..a48fe6f 100644 --- a/drivers/clk/ti/clk-2xxx.c +++ b/drivers/clk/ti/clk-2xxx.c @@ -237,10 +237,10 @@ static int __init omap2xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "dpll_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "mpu_ck")) / 1000000)); return 0; } diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 028b337..0988f1e 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -121,7 +121,7 @@ static const char *enable_init_clks[] = { int __init am33xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am33xx_clks); @@ -139,12 +139,12 @@ int __init am33xx_dt_clk_init(void) * oscillator clock. */ - clk1 = clk_get_sys(NULL, "sys_clkin_ck"); - clk2 = clk_get_sys(NULL, "timer3_fck"); - clk_set_parent(clk2, clk1); + clk1 = clk_provider_get_sys(NULL, "sys_clkin_ck"); + clk2 = clk_provider_get_sys(NULL, "timer3_fck"); + clk_provider_set_parent(clk2, clk1); - clk2 = clk_get_sys(NULL, "timer6_fck"); - clk_set_parent(clk2, clk1); + clk2 = clk_provider_get_sys(NULL, "timer6_fck"); + clk_provider_set_parent(clk2, clk1); /* * The On-Chip 32K RC Osc clock is not an accurate clock-source as per * the design/spec, so as a result, for example, timer which supposed @@ -152,9 +152,9 @@ int __init am33xx_dt_clk_init(void) * not expected by any use-case, so change WDT1 clock source to PRCM * 32KHz clock. */ - clk1 = clk_get_sys(NULL, "wdt1_fck"); - clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "wdt1_fck"); + clk2 = clk_provider_get_sys(NULL, "clkdiv32k_ick"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 0d1750a..58ef20e 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -365,10 +365,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "core_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "arm_fck")) / 1000000)); if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) omap3_clk_lock_dpll5(); diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 3795fce..1277452 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -116,7 +116,7 @@ static struct ti_dt_clk am43xx_clks[] = { int __init am43xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am43xx_clks); @@ -132,9 +132,9 @@ int __init am43xx_dt_clk_init(void) * By selecting dpll_core_m5_ck as the clocksource fixes this issue. * In AM335x dpll_core_m5_ck is the default clocksource. */ - clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); - clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "cpsw_cpts_rft_clk"); + clk2 = clk_provider_get_sys(NULL, "dpll_core_m5_ck"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 02517a8..1adc399 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -281,7 +281,7 @@ static struct ti_dt_clk omap44xx_clks[] = { int __init omap4xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap44xx_clks); @@ -291,8 +291,8 @@ int __init omap4xxx_dt_clk_init(void) * Lock USB DPLL on OMAP4 devices so that the L3INIT power * domain can transition to retention state when not in use. */ - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); @@ -302,12 +302,12 @@ int __init omap4xxx_dt_clk_init(void) * locking the ABE DPLL on boot. * Lock the ABE DPLL in any case to avoid issues with audio. */ - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_refclk_mux_ck"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 5e18399..5b603b5 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -225,34 +225,35 @@ static struct ti_dt_clk omap54xx_clks[] = { int __init omap5xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap54xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_clk_mux"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_m2x2_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); + rc = clk_provider_set_rate(abe_dpll, + OMAP5_DPLL_ABE_DEFFREQ * 2); if (rc) pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ / 2); if (rc) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 62ac8f6..9dba0bb 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -307,39 +307,39 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + struct clk_core *abe_dpll_mux, *sys_clkin2, *dpll_ck; ti_dt_clocks_register(dra7xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); - sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); - dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_mux = clk_provider_get_sys(NULL, "abe_dpll_sys_clk_mux"); + sys_clkin2 = clk_provider_get_sys(NULL, "sys_clkin2"); + dpll_ck = clk_provider_get_sys(NULL, "dpll_abe_ck"); - rc = clk_set_parent(abe_dpll_mux, sys_clkin2); + rc = clk_provider_set_parent(abe_dpll_mux, sys_clkin2); if (!rc) - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2); + dpll_ck = clk_provider_get_sys(NULL, "dpll_abe_m2x2_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2); if (rc) pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); + dpll_ck = clk_provider_get_sys(NULL, "dpll_gmac_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); if (rc) pr_err("%s: failed to configure GMAC DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); + dpll_ck = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); + dpll_ck = clk_provider_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ / 2); if (rc) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index 4a65b41..029a0d3 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c @@ -40,7 +40,7 @@ struct dra7_atl_clock_info; struct dra7_atl_desc { - struct clk *clk; + struct clk_core *clk; struct clk_hw hw; struct dra7_atl_clock_info *cinfo; int id; @@ -165,7 +165,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) struct dra7_atl_desc *clk_hw = NULL; struct clk_init_data init = { 0 }; const char **parent_names = NULL; - struct clk *clk; + struct clk_core *clk; clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); if (!clk_hw) { @@ -233,7 +233,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) char prop[5]; struct dra7_atl_desc *cdesc; struct of_phandle_args clkspec; - struct clk *clk; + struct clk_core *clk; int rc; rc = of_parse_phandle_with_args(node, "ti,provided-clocks", diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index b1a6f71..d88a70d0 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -41,7 +41,7 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) { struct ti_dt_clk *c; struct device_node *node; - struct clk *clk; + struct clk_core *clk; struct of_phandle_args clkspec; for (c = oclks; c->node_name != NULL; c++) { diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index f1e0038..6bc75d8 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -26,7 +26,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *clk_hw; const char *clkdm_name = node->name; int i; @@ -35,7 +35,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells"); for (i = 0; i < num_clks; i++) { - clk = of_clk_get(node, i); + clk = of_clk_provider_get(node, i); if (__clk_get_flags(clk) & CLK_IS_BASIC) { pr_warn("can't setup clkdm for basic clk %s\n", __clk_get_name(clk)); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index 19d8980..2cbee34 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -119,7 +119,7 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) static void __init ti_clk_register_composite(struct clk_hw *hw, struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); struct component_clk *comp; int num_parents = 0; diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index e6aa10d..1c41515 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -246,7 +246,7 @@ const struct clk_ops ti_clk_divider_ops = { .set_rate = ti_clk_divider_set_rate, }; -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, @@ -254,7 +254,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -434,7 +434,7 @@ static int __init ti_clk_divider_populate(struct device_node *node, */ static void __init of_ti_divider_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; u8 clk_divider_flags = 0; diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 79791e1..e1f74cc 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -128,10 +128,10 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *dd = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - dd->clk_ref = of_clk_get(node, 0); - dd->clk_bypass = of_clk_get(node, 1); + dd->clk_ref = of_clk_provider_get(node, 0); + dd->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) { pr_debug("clk-ref or clk-bypass missing for %s, retry later\n", @@ -175,7 +175,7 @@ static void ti_clk_register_dpll_x2(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *name = node->name; diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c index c2c8a28..2aa2701 100644 --- a/drivers/clk/ti/fixed-factor.c +++ b/drivers/clk/ti/fixed-factor.c @@ -33,7 +33,7 @@ */ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index b326d27..dd1b813 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -94,7 +94,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *clk_name = node->name; diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c index 9c3e8c4..e2f2bc0 100644 --- a/drivers/clk/ti/interface.c +++ b/drivers/clk/ti/interface.c @@ -34,7 +34,7 @@ static const struct clk_ops ti_interface_clk_ops = { static void __init _of_ti_interface_clk_setup(struct device_node *node, const struct clk_hw_omap_ops *ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *parent_name; diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index e9d650e..7456198 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -104,14 +104,14 @@ const struct clk_ops ti_clk_mux_ops = { .determine_rate = __clk_mux_determine_rate, }; -static struct clk *_register_mux(struct device *dev, const char *name, +static struct clk_core *_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the mux */ @@ -152,7 +152,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, */ static void of_mux_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; void __iomem *reg; int num_parents; const char **parent_names; diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c index e7bd62c..dabb8e6 100644 --- a/drivers/clk/ux500/abx500-clk.c +++ b/drivers/clk/ux500/abx500-clk.c @@ -23,7 +23,7 @@ static int ab8500_reg_clks(struct device *dev) { int ret; - struct clk *clk; + struct clk_core *clk; const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"}; u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1}; diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c index bd4769a..7eb055f 100644 --- a/drivers/clk/ux500/clk-prcc.c +++ b/drivers/clk/ux500/clk-prcc.c @@ -92,7 +92,7 @@ static struct clk_ops clk_prcc_kclk_ops = { .is_enabled = clk_prcc_is_enabled, }; -static struct clk *clk_reg_prcc(const char *name, +static struct clk_core *clk_reg_prcc(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -101,7 +101,7 @@ static struct clk *clk_reg_prcc(const char *name, { struct clk_prcc *clk; struct clk_init_data clk_prcc_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcc: %s invalid arguments passed\n", __func__); @@ -142,7 +142,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -152,7 +152,7 @@ struct clk *clk_reg_prcc_pclk(const char *name, &clk_prcc_pclk_ops); } -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index e2d63bc..bac54c9 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -243,7 +243,7 @@ static struct clk_ops clk_prcmu_opp_volt_scalable_ops = { .set_rate = clk_prcmu_set_rate, }; -static struct clk *clk_reg_prcmu(const char *name, +static struct clk_core *clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -252,7 +252,7 @@ static struct clk *clk_reg_prcmu(const char *name, { struct clk_prcmu *clk; struct clk_init_data clk_prcmu_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcmu: %s invalid arguments passed\n", __func__); @@ -292,7 +292,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -302,7 +302,7 @@ struct clk *clk_reg_prcmu_scalable(const char *name, &clk_prcmu_scalable_ops); } -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -311,7 +311,7 @@ struct clk *clk_reg_prcmu_gate(const char *name, &clk_prcmu_gate_ops); } -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -321,7 +321,7 @@ struct clk *clk_reg_prcmu_scalable_rate(const char *name, &clk_prcmu_scalable_rate_ops); } -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -330,7 +330,7 @@ struct clk *clk_reg_prcmu_rate(const char *name, &clk_prcmu_rate_ops); } -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -339,7 +339,7 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name, &clk_prcmu_opp_gate_ops); } -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c index e364c9d..dc6608a 100644 --- a/drivers/clk/ux500/clk-sysctrl.c +++ b/drivers/clk/ux500/clk-sysctrl.c @@ -114,7 +114,7 @@ static struct clk_ops clk_sysctrl_set_parent_ops = { .get_parent = clk_sysctrl_get_parent, }; -static struct clk *clk_reg_sysctrl(struct device *dev, +static struct clk_core *clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, @@ -128,7 +128,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, { struct clk_sysctrl *clk; struct clk_init_data clk_sysctrl_init; - struct clk *clk_reg; + struct clk_core *clk_reg; int i; if (!dev) @@ -176,7 +176,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, return clk_reg; } -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -193,7 +193,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, flags, &clk_sysctrl_gate_ops); } -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -212,7 +212,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, &clk_sysctrl_gate_fixed_rate_ops); } -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h index a2bb92d..da40a2d 100644 --- a/drivers/clk/ux500/clk.h +++ b/drivers/clk/ux500/clk.h @@ -14,52 +14,52 @@ #include <linux/device.h> #include <linux/types.h> -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -68,7 +68,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -78,7 +78,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 80069c3..8a2b4bc 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -19,7 +19,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, { struct prcmu_fw_version *fw_version; const char *sgaclk_parent = NULL; - struct clk *clk; + struct clk_core *clk; /* Clock sources */ clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c index 7b55ef8..afda303 100644 --- a/drivers/clk/ux500/u8500_of_clk.c +++ b/drivers/clk/ux500/u8500_of_clk.c @@ -18,9 +18,9 @@ #define PRCC_NUM_PERIPH_CLUSTERS 6 #define PRCC_PERIPHS_PER_CLUSTER 32 -static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; -static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; -static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcmu_clk[PRCMU_NUM_CLKS]; +static struct clk_core *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; #define PRCC_SHOW(clk, base, bit) \ clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] @@ -29,10 +29,10 @@ static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_C #define PRCC_KCLK_STORE(clk, base, bit) \ prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk -static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, +static struct clk_core *ux500_twocell_get(struct of_phandle_args *clkspec, void *data) { - struct clk **clk_data = data; + struct clk_core **clk_data = data; unsigned int base, bit; if (clkspec->args_count != 2) @@ -61,7 +61,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, struct device_node *np = NULL; struct device_node *child = NULL; const char *sgaclk_parent = NULL; - struct clk *clk, *rtc_clk, *twd_clk; + struct clk_core *clk, *rtc_clk, *twd_clk; if (of_have_populated_dt()) np = of_find_matching_node(NULL, u8500_clk_of_match); diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c index 20c8add..897daf6 100644 --- a/drivers/clk/ux500/u8540_clk.c +++ b/drivers/clk/ux500/u8540_clk.c @@ -17,7 +17,7 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, u32 clkrst5_base, u32 clkrst6_base) { - struct clk *clk; + struct clk_core *clk; /* Clock sources. */ /* Fixed ClockGen */ diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index bc96f10..8df4acc 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -121,13 +121,13 @@ static const struct clk_ops icst_ops = { .set_rate = icst_set_rate, }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, void __iomem *base) { - struct clk *clk; + struct clk_core *clk; struct clk_icst *icst; struct clk_init_data init; struct icst_params *pclone; diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h index 04e6f0a..ede867b 100644 --- a/drivers/clk/versatile/clk-icst.h +++ b/drivers/clk/versatile/clk-icst.h @@ -13,7 +13,7 @@ struct clk_icst_desc { u32 lock_offset; }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c index 1cc1330..6b35629 100644 --- a/drivers/clk/versatile/clk-impd1.c +++ b/drivers/clk/versatile/clk-impd1.c @@ -21,18 +21,18 @@ struct impd1_clk { char *pclkname; - struct clk *pclk; + struct clk_core *pclk; char *vco1name; - struct clk *vco1clk; + struct clk_core *vco1clk; char *vco2name; - struct clk *vco2clk; - struct clk *mmciclk; + struct clk_core *vco2clk; + struct clk_core *mmciclk; char *uartname; - struct clk *uartclk; + struct clk_core *uartclk; char *spiname; - struct clk *spiclk; + struct clk_core *spiclk; char *scname; - struct clk *scclk; + struct clk_core *scclk; struct clk_lookup *clks[15]; }; @@ -87,8 +87,8 @@ static const struct clk_icst_desc impd1_icst2_desc = { void integrator_impd1_clk_init(void __iomem *base, unsigned int id) { struct impd1_clk *imc; - struct clk *clk; - struct clk *pclk; + struct clk_core *clk; + struct clk_core *pclk; int i; if (id > 3) { diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c index c8b5231..4fa61b3 100644 --- a/drivers/clk/versatile/clk-realview.c +++ b/drivers/clk/versatile/clk-realview.c @@ -50,7 +50,7 @@ static const struct clk_icst_desc __initdata realview_osc4_desc = { */ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176) { - struct clk *clk; + struct clk_core *clk; /* APB clock dummy */ clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); diff --git a/drivers/clk/versatile/clk-sp810.c b/drivers/clk/versatile/clk-sp810.c index c6e86a9..9256d25 100644 --- a/drivers/clk/versatile/clk-sp810.c +++ b/drivers/clk/versatile/clk-sp810.c @@ -25,7 +25,7 @@ struct clk_sp810; struct clk_sp810_timerclken { struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_sp810 *sp810; int channel; }; @@ -36,8 +36,8 @@ struct clk_sp810 { void __iomem *base; spinlock_t lock; struct clk_sp810_timerclken timerclken[4]; - struct clk *refclk; - struct clk *timclk; + struct clk_core *refclk; + struct clk_core *timclk; }; static u8 clk_sp810_timerclken_get_parent(struct clk_hw *hw) @@ -79,29 +79,31 @@ static int clk_sp810_timerclken_prepare(struct clk_hw *hw) { struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - struct clk *old_parent = __clk_get_parent(hw->clk); - struct clk *new_parent; + struct clk_core *old_parent = __clk_get_parent(hw->clk); + struct clk_core *new_parent; if (!sp810->refclk) - sp810->refclk = of_clk_get(sp810->node, sp810->refclk_index); + sp810->refclk = of_clk_provider_get(sp810->node, + sp810->refclk_index); if (!sp810->timclk) - sp810->timclk = of_clk_get(sp810->node, sp810->timclk_index); + sp810->timclk = of_clk_provider_get(sp810->node, + sp810->timclk_index); if (WARN_ON(IS_ERR(sp810->refclk) || IS_ERR(sp810->timclk))) return -ENOENT; /* Select fastest parent */ - if (clk_get_rate(sp810->refclk) > clk_get_rate(sp810->timclk)) + if (clk_provider_get_rate(sp810->refclk) > clk_provider_get_rate(sp810->timclk)) new_parent = sp810->refclk; else new_parent = sp810->timclk; /* Switch the parent if necessary */ if (old_parent != new_parent) { - clk_prepare(new_parent); - clk_set_parent(hw->clk, new_parent); - clk_unprepare(old_parent); + clk_provider_prepare(new_parent); + clk_provider_set_parent(hw->clk, new_parent); + clk_provider_unprepare(old_parent); } return 0; @@ -112,8 +114,8 @@ static void clk_sp810_timerclken_unprepare(struct clk_hw *hw) struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - clk_put(sp810->timclk); - clk_put(sp810->refclk); + __clk_put(sp810->timclk); + __clk_put(sp810->refclk); } static const struct clk_ops clk_sp810_timerclken_ops = { @@ -123,7 +125,7 @@ static const struct clk_ops clk_sp810_timerclken_ops = { .set_parent = clk_sp810_timerclken_set_parent, }; -static struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, +static struct clk_core *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, void *data) { struct clk_sp810 *sp810 = data; diff --git a/drivers/clk/versatile/clk-versatile.c b/drivers/clk/versatile/clk-versatile.c index a76981e..08ce5af 100644 --- a/drivers/clk/versatile/clk-versatile.c +++ b/drivers/clk/versatile/clk-versatile.c @@ -60,7 +60,7 @@ static const struct clk_icst_desc versatile_auxosc_desc __initconst = { static void __init cm_osc_setup(struct device_node *np, const struct clk_icst_desc *desc) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c index 529a59c..c9e175f 100644 --- a/drivers/clk/versatile/clk-vexpress-osc.c +++ b/drivers/clk/versatile/clk-vexpress-osc.c @@ -73,7 +73,7 @@ static int vexpress_osc_probe(struct platform_device *pdev) struct clk_lookup *cl = pdev->dev.platform_data; /* Non-DT lookup */ struct clk_init_data init; struct vexpress_osc *osc; - struct clk *clk; + struct clk_core *clk; u32 range[2]; osc = devm_kzalloc(&pdev->dev, sizeof(*osc), GFP_KERNEL); diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c index 2d5e1b4..e77f3d5 100644 --- a/drivers/clk/versatile/clk-vexpress.c +++ b/drivers/clk/versatile/clk-vexpress.c @@ -17,7 +17,7 @@ #include <linux/err.h> #include <linux/vexpress.h> -static struct clk *vexpress_sp810_timerclken[4]; +static struct clk_core *vexpress_sp810_timerclken[4]; static DEFINE_SPINLOCK(vexpress_sp810_lock); static void __init vexpress_sp810_init(void __iomem *base) @@ -54,7 +54,7 @@ static const char * const vexpress_clk_24mhz_periphs[] __initconst = { void __init vexpress_clk_init(void __iomem *sp810_base) { - struct clk *clk; + struct clk_core *clk; int i; clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, @@ -77,7 +77,7 @@ void __init vexpress_clk_init(void __iomem *sp810_base) vexpress_sp810_init(sp810_base); for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++) - WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk)); + WARN_ON(clk_provider_set_parent(vexpress_sp810_timerclken[i], clk)); WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0], "v2m-timer0", "sp804")); diff --git a/drivers/clk/x86/clk-lpt.c b/drivers/clk/x86/clk-lpt.c index 812f83f..1b4a5e1 100644 --- a/drivers/clk/x86/clk-lpt.c +++ b/drivers/clk/x86/clk-lpt.c @@ -21,7 +21,7 @@ static int lpt_clk_probe(struct platform_device *pdev) { struct lpss_clk_data *drvdata; - struct clk *clk; + struct clk_core *clk; drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 246cf12..0efdd9a 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -67,8 +67,8 @@ enum zynq_clk { i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; -static struct clk *ps_clk; -static struct clk *clks[clk_max]; +static struct clk_core *ps_clk; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(armpll_lock); @@ -108,7 +108,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, const char **parents, int enable) { - struct clk *clk; + struct clk_core *clk; u32 enable_reg; char *mux_name; char *div0_name; @@ -154,7 +154,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); enable_reg = clk_readl(fclk_gate_reg) & 1; if (enable && !enable_reg) { - if (clk_prepare_enable(clks[fclk])) + if (clk_provider_prepare_enable(clks[fclk])) pr_warn("%s: FCLK%u enable failed\n", __func__, fclk - fclk0); } @@ -181,7 +181,7 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, const char *clk_name1, void __iomem *clk_ctrl, const char **parents, unsigned int two_gates) { - struct clk *clk; + struct clk_core *clk; char *mux_name; char *div_name; spinlock_t *lock; @@ -222,7 +222,7 @@ static void __init zynq_clk_setup(struct device_node *np) int i; u32 tmp; int ret; - struct clk *clk; + struct clk_core *clk; char *clk_name; unsigned int fclk_enable = 0; const char *clk_output_name[clk_max]; @@ -333,13 +333,13 @@ static void __init zynq_clk_setup(struct device_node *np) CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr2x]); + clk_provider_prepare_enable(clks[ddr2x]); clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr3x]); + clk_provider_prepare_enable(clks[ddr3x]); clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | @@ -351,7 +351,7 @@ static void __init zynq_clk_setup(struct device_node *np) clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, &dciclk_lock); - clk_prepare_enable(clks[dci]); + clk_provider_prepare_enable(clks[dci]); /* Peripheral clocks */ for (i = fclk0; i <= fclk3; i++) { @@ -505,10 +505,10 @@ static void __init zynq_clk_setup(struct device_node *np) /* leave debug clocks in the state the bootloader set them up to */ tmp = clk_readl(SLCR_DBG_CLK_CTRL); if (tmp & DBG_CLK_CTRL_CLKACT_TRC) - if (clk_prepare_enable(clks[dbg_trc])) + if (clk_provider_prepare_enable(clks[dbg_trc])) pr_warn("%s: trace clk enable failed\n", __func__); if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) - if (clk_prepare_enable(clks[dbg_apb])) + if (clk_provider_prepare_enable(clks[dbg_apb])) pr_warn("%s: debug APB clk enable failed\n", __func__); /* One gated clock for all APER clocks. */ diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c index cec9759..5176f65 100644 --- a/drivers/clk/zynq/pll.c +++ b/drivers/clk/zynq/pll.c @@ -193,12 +193,12 @@ static const struct clk_ops zynq_pll_ops = { * @lock Register lock * Returns handle to the registered clock. */ -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock) { struct zynq_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 reg; const char *parent_arr[1] = {parent}; unsigned long flags = 0; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c index 902d768..9616f7d 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c @@ -24,7 +24,7 @@ struct hdmi_phy_8960 { struct hdmi_phy base; struct hdmi *hdmi; struct clk_hw pll_hw; - struct clk *pll; + struct clk_core *pll; unsigned long pixclk; }; #define to_hdmi_phy_8960(x) container_of(x, struct hdmi_phy_8960, base) diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index 2620c48..c2461af 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -215,7 +215,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) { - ret = clk_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); + ret = clk_provider_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); if (ret < 0) return ret; } @@ -225,7 +225,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, return 0; if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret; } @@ -254,7 +254,7 @@ static int __fimc_pipeline_close(struct exynos_media_pipeline *ep) /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret == -ENXIO ? 0 : ret; } @@ -954,7 +954,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) while (--i >= 0) { if (IS_ERR(fmd->camclk[i].clock)) continue; - clk_put(fmd->camclk[i].clock); + __clk_put(fmd->camclk[i].clock); fmd->camclk[i].clock = ERR_PTR(-EINVAL); } @@ -962,7 +962,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_WBCLKS; i++) { if (IS_ERR(fmd->wbclk[i])) continue; - clk_put(fmd->wbclk[i]); + __clk_put(fmd->wbclk[i]); fmd->wbclk[i] = ERR_PTR(-EINVAL); } } @@ -971,7 +971,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) { struct device *dev = &fmd->pdev->dev; char clk_name[32]; - struct clk *clock; + struct clk_core *clock; int i, ret = 0; for (i = 0; i < FIMC_MAX_CAMCLKS; i++) @@ -979,7 +979,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_CAMCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { dev_err(dev, "Failed to get clock: %s\n", clk_name); @@ -1001,7 +1001,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = CLK_IDX_WB_B; i < FIMC_MAX_WBCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "pxl_async%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { v4l2_err(&fmd->v4l2_dev, "Failed to get clock: %s\n", clk_name); diff --git a/drivers/media/platform/exynos4-is/media-dev.h b/drivers/media/platform/exynos4-is/media-dev.h index 0321454..79e4b42 100644 --- a/drivers/media/platform/exynos4-is/media-dev.h +++ b/drivers/media/platform/exynos4-is/media-dev.h @@ -72,7 +72,7 @@ struct fimc_csis_info { }; struct fimc_camclk_info { - struct clk *clock; + struct clk_core *clock; int use_count; unsigned long frequency; }; @@ -124,7 +124,7 @@ struct fimc_md { struct fimc_sensor_info sensor[FIMC_MAX_SENSORS]; int num_sensors; struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS]; - struct clk *wbclk[FIMC_MAX_WBCLKS]; + struct clk_core *wbclk[FIMC_MAX_WBCLKS]; struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS]; struct fimc_dev *fimc[FIMC_MAX_DEVS]; struct fimc_is *fimc_is; @@ -141,7 +141,7 @@ struct fimc_md { } pinctl; struct cam_clk_provider { - struct clk *clks[FIMC_MAX_CAMCLKS]; + struct clk_core *clks[FIMC_MAX_CAMCLKS]; struct clk_onecell_data clk_data; struct device_node *of_node; struct cam_clk camclk[FIMC_MAX_CAMCLKS]; diff --git a/drivers/staging/imx-drm/imx-tve.c b/drivers/staging/imx-drm/imx-tve.c index 31fe7cf..2ce5bf6 100644 --- a/drivers/staging/imx-drm/imx-tve.c +++ b/drivers/staging/imx-drm/imx-tve.c @@ -121,10 +121,10 @@ struct imx_tve { struct regmap *regmap; struct regulator *dac_reg; struct i2c_adapter *ddc; - struct clk *clk; - struct clk *di_sel_clk; + struct clk_core *clk; + struct clk_core *di_sel_clk; struct clk_hw clk_hw_di; - struct clk *di_clk; + struct clk_core *di_clk; int vsync_pin; int hsync_pin; }; @@ -151,7 +151,7 @@ static void tve_enable(struct imx_tve *tve) if (!tve->enabled) { tve->enabled = true; - clk_prepare_enable(tve->clk); + clk_provider_prepare_enable(tve->clk); ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_IPU_CLK_EN | TVE_EN, TVE_IPU_CLK_EN | TVE_EN); @@ -178,7 +178,7 @@ static void tve_disable(struct imx_tve *tve) tve->enabled = false; ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_IPU_CLK_EN | TVE_EN, 0); - clk_disable_unprepare(tve->clk); + clk_provider_disable_unprepare(tve->clk); } } @@ -253,12 +253,12 @@ static int imx_tve_connector_mode_valid(struct drm_connector *connector, unsigned long rate; /* pixel clock with 2x oversampling */ - rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; + rate = clk_provider_round_rate(tve->clk, 2000UL * mode->clock) / 2000; if (rate == mode->clock) return MODE_OK; /* pixel clock without oversampling */ - rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; + rate = clk_provider_round_rate(tve->clk, 1000UL * mode->clock) / 1000; if (rate == mode->clock) return MODE_OK; @@ -327,13 +327,13 @@ static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, * and enable 4x oversampling for lower resolutions */ rate = 2000UL * mode->clock; - clk_set_rate(tve->clk, rate); - rounded_rate = clk_get_rate(tve->clk); + clk_provider_set_rate(tve->clk, rate); + rounded_rate = clk_provider_get_rate(tve->clk); if (rounded_rate >= rate) div = 2; - clk_set_rate(tve->di_clk, rounded_rate / div); + clk_provider_set_rate(tve->di_clk, rounded_rate / div); - ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); + ret = clk_provider_set_parent(tve->di_sel_clk, tve->di_clk); if (ret < 0) { dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", ret); @@ -645,7 +645,7 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data) return ret; } - tve->clk = devm_clk_get(dev, "tve"); + tve->clk = devm_clk_provider_get(dev, "tve"); if (IS_ERR(tve->clk)) { dev_err(dev, "failed to get high speed tve clock: %ld\n", PTR_ERR(tve->clk)); @@ -653,7 +653,7 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data) } /* this is the IPU DI clock input selector, can be parented to tve_di */ - tve->di_sel_clk = devm_clk_get(dev, "di_sel"); + tve->di_sel_clk = devm_clk_provider_get(dev, "di_sel"); if (IS_ERR(tve->di_sel_clk)) { dev_err(dev, "failed to get ipu di mux clock: %ld\n", PTR_ERR(tve->di_sel_clk)); diff --git a/include/asm-generic/clkdev.h b/include/asm-generic/clkdev.h index 90a32a6..16d43d9 100644 --- a/include/asm-generic/clkdev.h +++ b/include/asm-generic/clkdev.h @@ -17,8 +17,8 @@ struct clk; -static inline int __clk_get(struct clk *clk) { return 1; } -static inline void __clk_put(struct clk *clk) { } +static inline int __clk_get(struct clk_core *clk) { return 1; } +static inline void __clk_put(struct clk_core *clk) { } static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) { diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index e8d8a35..6b9e6b4 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -22,8 +22,8 @@ * @mult_div1_reg: register containing the DPLL M and N bitfields * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input + * @clk_bypass: struct clk_core pointer to the clock's bypass clock input + * @clk_ref: struct clk_core pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() @@ -68,8 +68,8 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; + struct clk_core *clk_bypass; + struct clk_core *clk_ref; void __iomem *control_reg; u32 enable_mask; unsigned long last_rounded_rate; @@ -251,7 +251,7 @@ extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) -void omap2_init_clk_hw_omap_clocks(struct clk *clk); +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h index a990a59..6c35291 100644 --- a/include/linux/clk/zynq.h +++ b/include/linux/clk/zynq.h @@ -25,7 +25,7 @@ void zynq_clock_init(void); -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock); #endif diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index a947ab8..4b34c69 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -107,8 +107,8 @@ struct si5351_clkout_config { * @clkout: array of clkout configuration */ struct si5351_platform_data { - struct clk *clk_xtal; - struct clk *clk_clkin; + struct clk_core *clk_xtal; + struct clk_core *clk_clkin; enum si5351_pll_src pll_src[2]; struct si5351_clkout_config clkout[8]; }; -- 1.9.3

2 2

[alsa-devel] ASoC:simple-card: problem with multi-DAIs
by Jean-Francois Moine 03 Sep '14

03 Sep '14

Hi Kuninori, In your patch ASoC: simple-card: remove dai_link->cpu_dai_name when DT (commit 179949bc04c7157a4b2279f62a842638b61f78f9 in /kernel/git/broonie/sound.git/) you removed all 'cpu_dai_name's, and this creates problems in my system. I have an audio controller with 2 DAIs. The audio system is defined as: sound { compatible = "simple-audio-card"; simple-audio-card,name = "Cubox Audio"; simple-audio-card,dai-link@0 { /* I2S - HDMI */ format = "i2s"; cpu { sound-dai = <&audio1 0>; }; codec { sound-dai = <&hdmi 0>; }; }; simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ cpu { sound-dai = <&audio1 1>; }; codec@0 { sound-dai = <&hdmi 1>; }; }; ... } The 'cpu_of_node' of both CPU DAIs is the same ('audio1'), and only the cpu_dai_name permits to know the CPU DAI. But, as you removed it, both DAI links are built with the 1st CPU DAI (I2S), and the second link (via S/PDIF) does not work. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/

3 4

[alsa-devel] Audio mini conference 2014?
by Takashi Iwai 03 Sep '14

03 Sep '14

Hi, did anyone think of a meeting in this year? AFAIK, a couple of good candidates to tie with are: - LinuxCon + KS will be at Chicago, USA (in August 18-22) - Plumbers will be at Duesseldorf, Germany (in October 15-17) Any other opportunities? I'm not sure whether I'll be in the former (due to private reason), but very likely I'll attend the latter. And, if we hold a meeting, in which format? I find the previous year's meeting was nice; i.e. a kind of mini-summit that doesn't conflict with other meetings is my preference. But I'm open for other options. thanks, Takashi

14 75

[alsa-devel] [PATCH 1/2] ALSA: hda - Add common pin macros for ALC269 family
by David Henningsson 03 Sep '14

03 Sep '14

This will be used in a later patch to make the pin quirk table shorter. Signed-off-by: David Henningsson <david.henningsson(a)canonical.com> --- sound/pci/hda/patch_realtek.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) Note: there is a checkpatch error on this one: ERROR: Macros with complex values should be enclosed in parenthesis ...but in this case I believe checkpatch is wrong, as adding parenthesis around the "complex values" will cause a compilation error. diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 00fc594..b8ff33b 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -5029,6 +5029,37 @@ static const struct hda_model_fixup alc269_fixup_models[] = { {} }; +#define ALC255_STANDARD_PINS \ + {0x18, 0x411111f0}, \ + {0x19, 0x411111f0}, \ + {0x1a, 0x411111f0}, \ + {0x1b, 0x411111f0}, \ + {0x1e, 0x411111f0} + +#define ALC282_STANDARD_PINS \ + {0x14, 0x90170110}, \ + {0x18, 0x411111f0}, \ + {0x1a, 0x411111f0}, \ + {0x1b, 0x411111f0}, \ + {0x1e, 0x411111f0} + +#define ALC290_STANDARD_PINS \ + {0x12, 0x99a30130}, \ + {0x13, 0x40000000}, \ + {0x16, 0x411111f0}, \ + {0x17, 0x411111f0}, \ + {0x19, 0x411111f0}, \ + {0x1b, 0x411111f0}, \ + {0x1e, 0x411111f0} + +#define ALC292_STANDARD_PINS \ + {0x14, 0x90170110}, \ + {0x15, 0x0221401f}, \ + {0x1a, 0x411111f0}, \ + {0x1b, 0x411111f0}, \ + {0x1d, 0x40700001}, \ + {0x1e, 0x411111f0} + static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = { SND_HDA_PIN_QUIRK(0x10ec0255, 0x1028, "Dell", ALC255_FIXUP_DELL2_MIC_NO_PRESENCE, {0x12, 0x40300000}, -- 1.9.1

2 2

[alsa-devel] [PATCHv2 0/4] simple-card: simplify the code.
by Xiubo Li 03 Sep '14

03 Sep '14

And comment and advice are welcome. Change in v2: - Maintian compatibility with the old DTs. Change in v1: - Add simple-card dts node patches. - Fix format parsing bug from Jean-Francois's comment. - Rebase to Kuninori-san's newest changes in next branch. Xiubo Li (4): ASoC: simple-card: add asoc_simple_card_fmt_master() to simplify the code. ASoC: simple-card: Merge single and muti DAI link(s) code. ASoC: simple-card: Adjust the comments of simple card. ASoC: simple-card: binding: update binding to support the new style. .../devicetree/bindings/sound/simple-card.txt | 184 ++++++++++++++------- sound/soc/generic/simple-card.c | 131 ++++++++------- 2 files changed, 191 insertions(+), 124 deletions(-) -- 1.8.4

7 28

[alsa-devel] [PATCH 0/8] move some existing quirks to pin quirks
by Hui Wang 03 Sep '14

03 Sep '14

These changes are based on the alsa-info.txt we have, if an existing quirk shows up in the quirk table more than 3 times, I tried to move it. After this change, we can avoid repeatly adding items in the old quirk table. Hui Wang (8): ALSA: hda/realtek - move DELL2_MIC_NO_PRESENCE quirk for alc292 ALSA: hda/realtek - move DELL1_MIC_NO_PRESENCE quirk for alc283 ALSA: hda/realtek - move DELL1_MIC_NO_PRESENCE quirk for alc255 ALSA: hda/realtek - move DELL2_MIC_NO_PRESENCE quirk for alc255 ALSA: hda/realtek - move HP_MUTE_LED_MIC1 quirk for alc282 ALSA: hda/realtek - move HP_MUTE_LED_MIC1 quirk for alc290 ALSA: hda/realtek - move HP_LINE1_MIC1_LED quirk for alc282 ALSA: hda/realtek - move HP_GPIO_MIC1_LED quirk for alc280 sound/pci/hda/patch_realtek.c | 305 ++++++++++++++++++++++++++++++------------ 1 file changed, 216 insertions(+), 89 deletions(-) -- 1.9.1

2 9

Re: [alsa-devel] [PATCH] ASoC: tlv320aic31xx: place codec into reset state initially
by Peter S. Housel 03 Sep '14

03 Sep '14

Ping... Thanks, -Peter- On 08/05/2014 12:34 AM, Jyri Sarha wrote: > On 08/05/2014 01:13 AM, Peter S. Housel wrote: >> Previously the driver would only place the TLV320AIC31XX into reset >> using the gpio reset line when at least one of the power supply >> regulators was disabled, so that if these supplies were always enabled >> no reset would ever occur. This change resets the codec state at probe >> time so that the initial register cache values are correct. >> >> Signed-off-by: Peter S. Housel <housel(a)acm.org> >> --- >> sound/soc/codecs/tlv320aic31xx.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/sound/soc/codecs/tlv320aic31xx.c >> b/sound/soc/codecs/tlv320aic31xx.c >> index 0f64c78..89a4daf 100644 >> --- a/sound/soc/codecs/tlv320aic31xx.c >> +++ b/sound/soc/codecs/tlv320aic31xx.c >> @@ -1194,7 +1194,7 @@ static int aic31xx_device_init(struct >> aic31xx_priv *aic31xx) >> if (aic31xx->pdata.gpio_reset) { >> ret = devm_gpio_request_one(aic31xx->dev, >> aic31xx->pdata.gpio_reset, >> - GPIOF_OUT_INIT_HIGH, >> + GPIOF_OUT_INIT_LOW, >> "aic31xx-reset-pin"); >> if (ret < 0) { >> dev_err(aic31xx->dev, "not able to acquire gpio\n"); >> > > Oops, aic3111 and friends indeed have an active low reset line. The > line was not behind a gpio on my board. > > Acked-by: Jyri Sarha <jsarha(a)ti.com> > _______________________________________________ > Alsa-devel mailing list > Alsa-devel(a)alsa-project.org > http://mailman.alsa-project.org/mailman/listinfo/alsa-devel

2 1

Re: [alsa-devel] [PATCH] ALSA: virtuoso: add Xonar Essence STX II support
by Andreas Allacher 02 Sep '14

02 Sep '14

Hi, I just tested the card with the H6 board and the patch and it seems to work fine - only tested 5.1 because I do not have 7.1 but I guess 7.1 should work as well. One question: Could it be that under Linux the same sound volume is a bit lower than under Windows (not really a problem but...)? Will this patch make it into 3.17 final or will it be moved to 3.18? Regards, Andreas Clemens Ladisch wrote: > Andreas Allacher wrote: >> Is the path already in the kernel source git or do I have to apply it manually? > This patch is completely untested and not yet in any git. > > > Regards, > Clemens >

1 1

[alsa-devel] [RFC][PATCH 0/2] Allow nonatomic trigger operations
by Takashi Iwai 02 Sep '14

02 Sep '14

Hi, this is a quick hack for the features that have been requested by quite a few people since long time ago: the support of non-atomic PCM trigger. I've tested only with a limited driver set, so more tests and comments/reviews are appreciated. [PATCH 1/2] ALSA: pcm: Allow nonatomic trigger operations [PATCH 2/2] ALSA: pcm: Uninline snd_pcm_stream_lock() and _unlock() thanks, Takashi

2 5

[alsa-devel] [PATCHv1 0/7] simple-card: simplify the code.
by Xiubo Li 02 Sep '14

02 Sep '14

Change in v1: - Add simple-card dts node patches. - Fix format parsing bug from Jean-Francois's comment. - Rebase to Kuninori-san's newest changes in next branch. Xiubo Li (7): ASoC: simple-card: Merge single and muti DAI link code. ASoC: simple-card: Adjust the comments of simple card. ASoC: dts: vf610-twr: To support simple card newest style. ASoC: dts: kirkwood-t5325: To support simple card newest style. ASoC: dts: r8a7740-armadillo800eva-reference: To support simple card newest style. ASoC: dts: sh73a0-kzm9g-reference: To support simple card newest style. ASoC: dts: kirkwood-openrd-client: To support simple card newest style. .../devicetree/bindings/sound/simple-card.txt | 101 ++++++------ arch/arm/boot/dts/kirkwood-openrd-client.dts | 15 +- arch/arm/boot/dts/kirkwood-t5325.dts | 15 +- .../boot/dts/r8a7740-armadillo800eva-reference.dts | 21 +-- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 18 ++- arch/arm/boot/dts/vf610-twr.dts | 17 +- sound/soc/generic/simple-card.c | 176 ++++++++------------- 7 files changed, 160 insertions(+), 203 deletions(-) -- 1.8.4

6 17

[alsa-devel] [PATCH v2 0/4] ASoC: atmel_ssc: enable fslen extension feature
by Bo Shen 02 Sep '14

02 Sep '14

On at91sam9rl, at91sam9g10, at91sam9g20, at91sam9g45 and newer SoCs, the SSC peripheral supports frame sync length extension feature. When SSC works as master, it can generate frame sync lenght larger than 16 bits. After enable this feature, it can playback 24/32 bits audio clips. Changes in v2: - Using compatible string to distinguish whether SSC supports frame sync length extension to replace check IP version. - Add related modification for dts file. Bo Shen (4): ASoC: atmel-ssc: distinguish whether SSC supports fslen ext ASoC: atmel_ssc_dai: enable fslen extension feature dts: atmel: at91sam9rl: switch ssc compatible string dts: atmel: at91sam9g20: switch ssc compatible string arch/arm/boot/dts/at91sam9g20.dtsi | 4 ++++ arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++-- drivers/misc/atmel-ssc.c | 13 +++++++++++++ include/linux/atmel-ssc.h | 13 +++++++++++++ sound/soc/atmel/atmel_ssc_dai.c | 34 ++++++++++++++++++---------------- 5 files changed, 50 insertions(+), 18 deletions(-) -- 1.8.5.2

3 9

[alsa-devel] [RFC][PATCH] ASoC: simple-card: Merge single and muti DAI link code.
by Xiubo Li 02 Sep '14

02 Sep '14

This patch merge single DAI link and muti-DAI links code together, and simply the simple-card driver code. And also do some other improvement: Since from the DAI format micro SND_SOC_DAIFMT_CBx_CFx, the 'CBx' mean Codec's bit clock is as master/slave and the 'CFx' mean Codec's frame clock is as master/slave. So these same DAI formats should be informed to CPU and CODE DAIs at the same time. For the Codec driver will set the bit clock and frame clock as the DAI formats said, but for the CPU driver, if the the bit clock or frame clock is as Codec master, so it should be set CPU DAI device as bit clock or frame clock as slave, and vice versa. The old code will cause confusion, and we should be clear that the letter 'C' here mean to Codec. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> Cc: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Cc: Jean-Francois Moine <moinejf(a)free.fr> Cc: Jyri Sarha <jsarha(a)ti.com> Cc: Nicolin Chen <nicoleotsuka(a)gmail.com> --- Hi, This patch will break the old DT, so i just send one RFC version, and will add the old DT patches in next version if this patch can work well. Any comments and advices are welcome. .../devicetree/bindings/sound/simple-card.txt | 98 ++++++++------- sound/soc/generic/simple-card.c | 135 ++++++--------------- 2 files changed, 88 insertions(+), 145 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt index c2e9841..457fd0b 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.txt +++ b/Documentation/devicetree/bindings/sound/simple-card.txt @@ -1,13 +1,12 @@ Simple-Card: +==== Simple-Card specifies audio DAI connections of SoC <-> codec. Required properties: - - compatible : "simple-audio-card" Optional properties: - - simple-audio-card,name : User specified audio sound card name, one string property. - simple-audio-card,widgets : Please refer to widgets.txt. @@ -18,68 +17,57 @@ Optional properties: - simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec mclk. -Optional subnodes: - -- simple-audio-card,dai-link : Container for dai-link level - properties and the CPU and CODEC - sub-nodes. This container may be - omitted when the card has only one - DAI link. See the examples and the - section bellow. - -Dai-link subnode properties and subnodes: - -If dai-link subnode is omitted and the subnode properties are directly -under "sound"-node the subnode property and subnode names have to be -prefixed with "simple-audio-card,"-prefix. +==== +DAI link node(s) and its or their subnodes: -Required dai-link subnodes: +There must be one DAI link node exsit at least, and each DAI link must +contain one CPU subnode and one CODEC subnode. -- cpu : CPU sub-node -- codec : CODEC sub-node - -Optional dai-link subnode properties: +Required DAI link node(s): +- simple-audio-card,dai-link : Container for DAI link level + properties and the CPU and CODEC + sub-nodes. +Optional DAI link node properties: - format : CPU/CODEC common audio format. "i2s", "right_j", "left_j" , "dsp_a" "dsp_b", "ac97", "pdm", "msb", "lsb" -- frame-master : Indicates dai-link frame master. - phandle to a cpu or codec subnode. -- bitclock-master : Indicates dai-link bit clock master. - phandle to a cpu or codec subnode. -- bitclock-inversion : bool property. Add this if the - dai-link uses bit clock inversion. -- frame-inversion : bool property. Add this if the - dai-link uses frame clock inversion. - -For backward compatibility the frame-master and bitclock-master -properties can be used as booleans in codec subnode to indicate if the -codec is the dai-link frame or bit clock master. In this case there -should be no dai-link node, the same properties should not be present -at sound-node level, and the bitclock-inversion and frame-inversion -properties should also be placed in the codec node if needed. - -Required CPU/CODEC subnodes properties: - -- sound-dai : phandle and port of CPU/CODEC +- frame-master : Boolean property. If present, for this + DAI link the Codec DAI's frame will be + as master and the CPU DAI's frame will + be as slave, or vice versa. +- bitclock-master : Boolean property. If present, for this + DAI link the Codec DAI's bit clock will + be as master and the CPU DAI's bit clock + will be as slave, or vice versa. +==== +DAI link's subnodes and their properties: + +Required DAI link subnodes: +- cpu : CPU sub-node +- codec : CODEC sub-node -Optional CPU/CODEC subnodes properties: +Required DAI link subnodes' properties: +- sound-dai : Phandle and port of CPU/CODEC +Optional DAI link subnodes' properties: +- bitclock-inversion : Boolean property. Add this if the DAI + device needs bit clock to be inversed. +- frame-inversion : Boolean property. Add this if the DAI + device needs frame clock to be inversed. - dai-tdm-slot-num : Please refer to tdm-slot.txt. - dai-tdm-slot-width : Please refer to tdm-slot.txt. - clocks / system-clock-frequency : specify subnode's clock if needed. it can be specified via "clocks" if system has clock node (= common clock), or "system-clock-frequency" (if system doens't support common clock) +==== Example 1 - single DAI link: sound { compatible = "simple-audio-card"; simple-audio-card,name = "VF610-Tower-Sound-Card"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack", @@ -89,13 +77,23 @@ sound { "Headphone Jack", "HP_OUT", "External Speaker", "LINE_OUT"; - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; + simple-audio-card,dai-link { + format = "left_j"; + cpu { + sound-dai = <&sh_fsi2 0>; + + bitclock-inversion; + frame-inversion; + }; + codec { + sound-dai = <&ak4648>; + clocks = <&osc>; + + bitclock-inversion; + }; - dailink0_master: simple-audio-card,codec { - sound-dai = <&ak4648>; - clocks = <&osc>; + bitclock-master; + frame-master; }; }; diff --git a/sound/soc/generic/simple-card.c b/sound/soc/generic/simple-card.c index 21b0ea2..a0d3622 100644 --- a/sound/soc/generic/simple-card.c +++ b/sound/soc/generic/simple-card.c @@ -112,13 +112,20 @@ static int asoc_simple_card_sub_parse_of(struct device_node *np, struct asoc_simple_dai *dai, struct device_node **p_node, - const char **name) + const char **name, + unsigned int *daifmt) { struct device_node *node; struct clk *clk; u32 val; int ret; + if (!daifmt) + return -EINVAL; + + *daifmt = snd_soc_of_parse_daifmt(np, NULL, NULL, NULL); + *daifmt &= ~SND_SOC_DAIFMT_MASTER_MASK; + /* * get node via "sound-dai = <&phandle port>" * it will be used as xxx_of_node on soc_bind_dai_link() @@ -166,102 +173,55 @@ asoc_simple_card_sub_parse_of(struct device_node *np, static int simple_card_dai_link_of(struct device_node *node, struct device *dev, struct snd_soc_dai_link *dai_link, - struct simple_dai_props *dai_props, - bool is_top_level_node) + struct simple_dai_props *dai_props) { struct device_node *np = NULL; - struct device_node *bitclkmaster = NULL; - struct device_node *framemaster = NULL; unsigned int daifmt; char *name; - char prop[128]; - char *prefix = ""; int ret; - if (is_top_level_node) - prefix = "simple-audio-card,"; - - daifmt = snd_soc_of_parse_daifmt(node, prefix, - &bitclkmaster, &framemaster); - daifmt &= ~SND_SOC_DAIFMT_MASTER_MASK; + daifmt = snd_soc_of_parse_daifmt(node, NULL, NULL, NULL); + daifmt &= SND_SOC_DAIFMT_MASTER_MASK; + dai_props->cpu_dai.fmt = dai_props->codec_dai.fmt = daifmt; - snprintf(prop, sizeof(prop), "%scpu", prefix); - np = of_get_child_by_name(node, prop); + np = of_get_child_by_name(node, "cpu"); if (!np) { ret = -EINVAL; - dev_err(dev, "%s: Can't find %s DT node\n", __func__, prop); + dev_err(dev, "%s: Can't find cpu DT node\n", __func__); goto dai_link_of_err; } ret = asoc_simple_card_sub_parse_of(np, &dai_props->cpu_dai, &dai_link->cpu_of_node, - &dai_link->cpu_dai_name); + &dai_link->cpu_dai_name, + &daifmt); if (ret < 0) goto dai_link_of_err; - dai_props->cpu_dai.fmt = daifmt; - switch (((np == bitclkmaster) << 4) | (np == framemaster)) { - case 0x11: - dai_props->cpu_dai.fmt |= SND_SOC_DAIFMT_CBS_CFS; - break; - case 0x10: - dai_props->cpu_dai.fmt |= SND_SOC_DAIFMT_CBS_CFM; - break; - case 0x01: - dai_props->cpu_dai.fmt |= SND_SOC_DAIFMT_CBM_CFS; - break; - default: - dai_props->cpu_dai.fmt |= SND_SOC_DAIFMT_CBM_CFM; - break; - } - + dai_props->cpu_dai.fmt |= daifmt; of_node_put(np); - snprintf(prop, sizeof(prop), "%scodec", prefix); - np = of_get_child_by_name(node, prop); + + np = of_get_child_by_name(node, "codec"); if (!np) { ret = -EINVAL; - dev_err(dev, "%s: Can't find %s DT node\n", __func__, prop); + dev_err(dev, "%s: Can't find codec DT node\n", __func__); goto dai_link_of_err; } ret = asoc_simple_card_sub_parse_of(np, &dai_props->codec_dai, &dai_link->codec_of_node, - &dai_link->codec_dai_name); + &dai_link->codec_dai_name, + &daifmt); if (ret < 0) goto dai_link_of_err; - if (strlen(prefix) && !bitclkmaster && !framemaster) { - /* No dai-link level and master setting was not found from - sound node level, revert back to legacy DT parsing and - take the settings from codec node. */ - dev_dbg(dev, "%s: Revert to legacy daifmt parsing\n", - __func__); - dai_props->cpu_dai.fmt = dai_props->codec_dai.fmt = - snd_soc_of_parse_daifmt(np, NULL, NULL, NULL) | - (daifmt & ~SND_SOC_DAIFMT_CLOCK_MASK); - } else { - dai_props->codec_dai.fmt = daifmt; - switch (((np == bitclkmaster) << 4) | (np == framemaster)) { - case 0x11: - dai_props->codec_dai.fmt |= SND_SOC_DAIFMT_CBM_CFM; - break; - case 0x10: - dai_props->codec_dai.fmt |= SND_SOC_DAIFMT_CBM_CFS; - break; - case 0x01: - dai_props->codec_dai.fmt |= SND_SOC_DAIFMT_CBS_CFM; - break; - default: - dai_props->codec_dai.fmt |= SND_SOC_DAIFMT_CBS_CFS; - break; - } - } - if (!dai_link->cpu_dai_name || !dai_link->codec_dai_name) { ret = -EINVAL; goto dai_link_of_err; } + dai_props->codec_dai.fmt |= daifmt; + /* simple-card assumes platform == cpu */ dai_link->platform_of_node = dai_link->cpu_of_node; @@ -288,22 +248,18 @@ static int simple_card_dai_link_of(struct device_node *node, dai_link_of_err: if (np) of_node_put(np); - if (bitclkmaster) - of_node_put(bitclkmaster); - if (framemaster) - of_node_put(framemaster); return ret; } static int asoc_simple_card_parse_of(struct device_node *node, struct simple_card_data *priv, - struct device *dev, - int multi) + struct device *dev) { struct snd_soc_dai_link *dai_link = priv->snd_card.dai_link; struct simple_dai_props *dai_props = priv->dai_props; + struct device_node *np = NULL; u32 val; - int ret; + int ret, i; /* parsing the card name from DT */ snd_soc_of_parse_card_name(&priv->snd_card, "simple-audio-card,name"); @@ -332,23 +288,15 @@ static int asoc_simple_card_parse_of(struct device_node *node, dev_dbg(dev, "New simple-card: %s\n", priv->snd_card.name ? priv->snd_card.name : ""); - if (multi) { - struct device_node *np = NULL; - int i; - for (i = 0; (np = of_get_next_child(node, np)); i++) { - dev_dbg(dev, "\tlink %d:\n", i); - ret = simple_card_dai_link_of(np, dev, dai_link + i, - dai_props + i, false); - if (ret < 0) { - of_node_put(np); - return ret; - } - } - } else { - ret = simple_card_dai_link_of(node, dev, dai_link, dai_props, - true); - if (ret < 0) + /* Parse DAI link(s) */ + for (i = 0; (np = of_get_next_child(node, np)); i++) { + dev_dbg(dev, "\tlink %d:\n", i); + ret = simple_card_dai_link_of(np, dev, dai_link + i, + dai_props + i); + if (ret < 0) { + of_node_put(np); return ret; + } } if (!priv->snd_card.name) @@ -384,16 +332,13 @@ static int asoc_simple_card_probe(struct platform_device *pdev) struct snd_soc_dai_link *dai_link; struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; - int num_links, multi, ret; + int num_links, ret; /* get the number of DAI links */ - if (np && of_get_child_by_name(np, "simple-audio-card,dai-link")) { + if (np && of_get_child_by_name(np, "simple-audio-card,dai-link")) num_links = of_get_child_count(np); - multi = 1; - } else { - num_links = 1; - multi = 0; - } + else + return -EINVAL; /* allocate the private data and the DAI link array */ priv = devm_kzalloc(dev, @@ -420,7 +365,7 @@ static int asoc_simple_card_probe(struct platform_device *pdev) if (np && of_device_is_available(np)) { - ret = asoc_simple_card_parse_of(np, priv, dev, multi); + ret = asoc_simple_card_parse_of(np, priv, dev); if (ret < 0) { if (ret != -EPROBE_DEFER) dev_err(dev, "parse error %d\n", ret); -- 1.8.5

5 6

[alsa-devel] [PATCH] ALSA: hda - Add TLV_DB_SCALE_MUTE bit for relevant controls
by Takashi Iwai 02 Sep '14

02 Sep '14

The DACs on Sigmatel/IDT codecs do mute at the lowest volume level, and in the earlier drivers, we passed TLV_DB_SCALE_MUTE bit for each volume control element like Speaker and Headphone as well as Master. Along with the translation to the generic parser, however, the TLV bit was lost for the slave controls (e.g. Speaker) but set only to Master. In theory this should have sufficed, but apps, particularly PA, do care the slave volume bits, so we seem to see a regression in the volume controls. This patch adds a flag to hda_gen_spec to specify the DAC mute feature, and adds the TLV bit properly for all relevant volume controls. Also, the TLV bit for vmaster is set in hda_generic.c, so that we can get rid of all tricks from the codec driver side. As the similar hack is applied to Conexant 5051 stuff, we can get rid of it as well. BugLink: https://bugs.launchpad.net/bugs/1357928 Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/hda_generic.c | 9 ++++++++- sound/pci/hda/hda_generic.h | 1 + sound/pci/hda/patch_conexant.c | 8 ++------ sound/pci/hda/patch_sigmatel.c | 5 +---- 4 files changed, 12 insertions(+), 11 deletions(-) diff --git a/sound/pci/hda/hda_generic.c b/sound/pci/hda/hda_generic.c index b956449ddada..95121e818b4d 100644 --- a/sound/pci/hda/hda_generic.c +++ b/sound/pci/hda/hda_generic.c @@ -31,6 +31,7 @@ #include <linux/module.h> #include <sound/core.h> #include <sound/jack.h> +#include <sound/tlv.h> #include "hda_codec.h" #include "hda_local.h" #include "hda_auto_parser.h" @@ -1105,6 +1106,7 @@ enum { */ static int assign_out_path_ctls(struct hda_codec *codec, struct nid_path *path) { + struct hda_gen_spec *spec = codec->spec; hda_nid_t nid; unsigned int val; int badness = 0; @@ -1119,6 +1121,8 @@ static int assign_out_path_ctls(struct hda_codec *codec, struct nid_path *path) nid = look_for_out_vol_nid(codec, path); if (nid) { val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT); + if (spec->dac_min_mute) + val |= HDA_AMP_VAL_MIN_MUTE; if (is_ctl_used(codec, val, NID_PATH_VOL_CTL)) badness += BAD_SHARED_VOL; else @@ -1880,9 +1884,12 @@ static int parse_output_paths(struct hda_codec *codec) path = snd_hda_get_path_from_idx(codec, spec->out_paths[0]); if (path) spec->vmaster_nid = look_for_out_vol_nid(codec, path); - if (spec->vmaster_nid) + if (spec->vmaster_nid) { snd_hda_set_vmaster_tlv(codec, spec->vmaster_nid, HDA_OUTPUT, spec->vmaster_tlv); + if (spec->dac_min_mute) + spec->vmaster_tlv[3] |= TLV_DB_SCALE_MUTE; + } } /* set initial pinctl targets */ diff --git a/sound/pci/hda/hda_generic.h b/sound/pci/hda/hda_generic.h index bb2dea743986..3f95f1d3f1f8 100644 --- a/sound/pci/hda/hda_generic.h +++ b/sound/pci/hda/hda_generic.h @@ -231,6 +231,7 @@ struct hda_gen_spec { unsigned int add_stereo_mix_input:1; /* add aamix as a capture src */ unsigned int add_jack_modes:1; /* add i/o jack mode enum ctls */ unsigned int power_down_unused:1; /* power down unused widgets */ + unsigned int dac_min_mute:1; /* minimal = mute for DACs */ /* other internal flags */ unsigned int no_analog:1; /* digital I/O only */ diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c index 6f2fa838b635..c0b03c112187 100644 --- a/sound/pci/hda/patch_conexant.c +++ b/sound/pci/hda/patch_conexant.c @@ -26,7 +26,6 @@ #include <linux/module.h> #include <sound/core.h> #include <sound/jack.h> -#include <sound/tlv.h> #include "hda_codec.h" #include "hda_local.h" @@ -779,6 +778,7 @@ static const struct hda_model_fixup cxt5066_fixup_models[] = { */ static void add_cx5051_fake_mutes(struct hda_codec *codec) { + struct conexant_spec *spec = codec->spec; static hda_nid_t out_nids[] = { 0x10, 0x11, 0 }; @@ -788,6 +788,7 @@ static void add_cx5051_fake_mutes(struct hda_codec *codec) snd_hda_override_amp_caps(codec, *p, HDA_OUTPUT, AC_AMPCAP_MIN_MUTE | query_amp_caps(codec, *p, HDA_OUTPUT)); + spec->gen.dac_min_mute = true; } static int patch_conexant_auto(struct hda_codec *codec) @@ -860,11 +861,6 @@ static int patch_conexant_auto(struct hda_codec *codec) if (err < 0) goto error; - if (codec->vendor_id == 0x14f15051) { - /* minimum value is actually mute */ - spec->gen.vmaster_tlv[3] |= TLV_DB_SCALE_MUTE; - } - codec->patch_ops = cx_auto_patch_ops; /* Some laptops with Conexant chips show stalls in S3 resume, diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index ea823e1100da..f26ec04a29b5 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -32,7 +32,6 @@ #include <linux/module.h> #include <sound/core.h> #include <sound/jack.h> -#include <sound/tlv.h> #include "hda_codec.h" #include "hda_local.h" #include "hda_auto_parser.h" @@ -4227,9 +4226,6 @@ static int stac_parse_auto_config(struct hda_codec *codec) if (err < 0) return err; - /* minimum value is actually mute */ - spec->gen.vmaster_tlv[3] |= TLV_DB_SCALE_MUTE; - /* setup analog beep controls */ if (spec->anabeep_nid > 0) { err = stac_auto_create_beep_ctls(codec, @@ -4413,6 +4409,7 @@ static int alloc_stac_spec(struct hda_codec *codec) snd_hda_gen_spec_init(&spec->gen); codec->spec = spec; codec->no_trigger_sense = 1; /* seems common with STAC/IDT codecs */ + spec->gen.dac_min_mute = true; return 0; } -- 2.1.0

1 0

[alsa-devel] ALC1150 broken on SuperMicro X10SAT
by Dana Goyette 02 Sep '14

02 Sep '14

On my SuperMicro X10SAT, the ALC1150 audio codec has horrific audio quality by default. The only output that seems to work is the front channel, and it's quiet, distorted, and unbalanced (the right is louder than the left). alsa-info.sh output: http://www.alsa-project.org/db/?f=8fbcab1d61590060ceddc1e63eb00d508e94d731 I've gotten the audio to work by guessing a model: options snd-hda-intel model=auto,acer-aspire,auto In tracing through the source: {.id = ALC883_FIXUP_ACER_EAPD, .name = "acer-aspire"} This name leads to: [ALC883_FIXUP_ACER_EAPD] = { .type = HDA_FIXUP_VERBS, .v.verbs = (const struct hda_verb[]) { /* eanable EAPD on Acer laptops */ { 0x20, AC_VERB_SET_COEF_INDEX, 0x07 }, { 0x20, AC_VERB_SET_PROC_COEF, 0x3050 }, { } } }, There's another override I did not try, since it has no model= name: [ALC883_FIXUP_EAPD] = { .type = HDA_FIXUP_VERBS, .v.verbs = (const struct hda_verb[]) { /* change to EAPD mode */ { 0x20, AC_VERB_SET_COEF_INDEX, 0x07 }, { 0x20, AC_VERB_SET_PROC_COEF, 0x3070 }, { } } },

2 4

[alsa-devel] [PATCH alsa-lib] pcm: fix return value of snd_pcm_share_slave_avail
by Alexander E. Patrakov 02 Sep '14

02 Sep '14

The return value was wrong for playback if slave->hw_ptr was near the boundary and *pcm->appl.ptr was near zero. The wrong result was greater than the boundary. Signed-off-by: Alexander E. Patrakov <patrakov(a)gmail.com> --- src/pcm/pcm_share.c | 2 ++ 1 file changed, 2 insertions(+) Only compile-tested, as I don't know how to setup the "share" pcm. diff --git a/src/pcm/pcm_share.c b/src/pcm/pcm_share.c index 9770544..c301c7a 100644 --- a/src/pcm/pcm_share.c +++ b/src/pcm/pcm_share.c @@ -128,6 +128,8 @@ static snd_pcm_uframes_t snd_pcm_share_slave_avail(snd_pcm_share_slave_t *slave) avail += pcm->buffer_size; if (avail < 0) avail += pcm->boundary; + else if ((snd_pcm_uframes_t) avail >= pcm->boundary) + avail -= pcm->boundary; return avail; } -- 2.1.0

2 1

Re: [alsa-devel] [pulseaudio-discuss] [PATCH] alsa-mixer: recognize Dock headphone jack
by Raymond Yau 02 Sep '14

02 Sep '14

> > > > > > Recognize the Dock headphone jack in the same way the normal & front > > > headphone jacks are detected. > > > --- > > > src/modules/alsa/mixer/paths/analog-output-headphones.conf | 8 ++++++++ > > > src/modules/alsa/mixer/paths/analog-output-speaker.conf | 4 ++++ > > > 2 files changed, 12 insertions(+) > > > > > > diff --git a/src/modules/alsa/mixer/paths/analog-output-headphones.conf > > b/src/modules/alsa/mixer/paths/analog-output-headphones.conf > > > index 89d794f..199b2c5 100644 > > > --- a/src/modules/alsa/mixer/paths/analog-output-headphones.conf > > > +++ b/src/modules/alsa/mixer/paths/analog-output-headphones.conf > > > @@ -25,6 +25,14 @@ description-key = analog-output-headphones > > > [Properties] > > > device.icon_name = audio-headphones > > > > > > +[Jack Dock Headphone] > > > +required-any = any > > > > As you assume dock headphone and headphone share the same headphone volume > > control > > The do on my machine indeed. For reference i've uploaded my alsa-info > into: >http://www.alsa-project.org/db/?f=5a1c208208ff33a2231d2d03d5bea5ec452dc24d > > > Do you mean the current alsa driver support surround 40 for notebook with > > dock headphone is incorrect ? > https://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/commit/sound/p… You will get auto mute lineout+speaker if the pin fixup is dock line out instead of dock headphone but pulseaudio don't like headphone and line out share pcm playback volume control and no headphone playback switch https://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/commit/sound/p… For notebook with dual headphone jacks which support multi channel and headphone Jack won't mute the other headphone Jack As you expect headphone can mute dock headphone and speaker

1 0

[alsa-devel] [PATCHv3 1/9] Clean WM8971 through checkpatch
by Xavier Hsu 02 Sep '14

02 Sep '14

This patch improves WM8971. We clean the file through checkpatch. Any comments about improving the patch are welcome. Thanks. Signed-off-by: Xavier Hsu <xavier.hsu(a)linaro.org> Signed-off-by: Andy Green <andy.green(a)linaro.org> --- sound/soc/codecs/wm8971.c | 107 ++++++++++++++++++++++++--------------------- 1 file changed, 56 insertions(+), 51 deletions(-) diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c index 0499cd4..064278f 100644 --- a/sound/soc/codecs/wm8971.c +++ b/sound/soc/codecs/wm8971.c @@ -31,7 +31,7 @@ #define WM8971_REG_COUNT 43 -static struct workqueue_struct *wm8971_workq = NULL; +static struct workqueue_struct *wm8971_workq; /* codec private data */ struct wm8971_priv { @@ -92,25 +92,28 @@ static const struct reg_default wm8971_reg_defaults[] = { #define wm8971_reset(c) snd_soc_write(c, WM8971_RESET, 0) /* WM8971 Controls */ -static const char *wm8971_bass[] = { "Linear Control", "Adaptive Boost" }; -static const char *wm8971_bass_filter[] = { "130Hz @ 48kHz", - "200Hz @ 48kHz" }; -static const char *wm8971_treble[] = { "8kHz", "4kHz" }; -static const char *wm8971_alc_func[] = { "Off", "Right", "Left", "Stereo" }; -static const char *wm8971_ng_type[] = { "Constant PGA Gain", - "Mute ADC Output" }; -static const char *wm8971_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; -static const char *wm8971_mono_mux[] = {"Stereo", "Mono (Left)", - "Mono (Right)", "Digital Mono"}; -static const char *wm8971_dac_phase[] = { "Non Inverted", "Inverted" }; -static const char *wm8971_lline_mux[] = {"Line", "NC", "NC", "PGA", - "Differential"}; -static const char *wm8971_rline_mux[] = {"Line", "Mic", "NC", "PGA", - "Differential"}; -static const char *wm8971_lpga_sel[] = {"Line", "NC", "NC", "Differential"}; -static const char *wm8971_rpga_sel[] = {"Line", "Mic", "NC", "Differential"}; -static const char *wm8971_adcpol[] = {"Normal", "L Invert", "R Invert", - "L + R Invert"}; +static const char const *wm8971_bass[] = {"Linear Control", "Adaptive Boost"}; +static const char const *wm8971_bass_filter[] = {"130Hz @ 48kHz", + "200Hz @ 48kHz"}; +static const char const *wm8971_treble[] = {"8kHz", "4kHz"}; +static const char const *wm8971_alc_func[] = {"Off", "Right", + "Left", "Stereo"}; +static const char const *wm8971_ng_type[] = {"Constant PGA Gain", + "Mute ADC Output"}; +static const char const *wm8971_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz"}; +static const char const *wm8971_mono_mux[] = {"Stereo", "Mono (Left)", + "Mono (Right)", "Digital Mono"}; +static const char const *wm8971_dac_phase[] = {"Non Inverted", "Inverted"}; +static const char const *wm8971_lline_mux[] = {"Line", "NC", "NC", + "PGA", "Differential"}; +static const char const *wm8971_rline_mux[] = {"Line", "Mic", "NC", + "PGA", "Differential"}; +static const char const *wm8971_lpga_sel[] = {"Line", "NC", "NC", + "Differential"}; +static const char const *wm8971_rpga_sel[] = {"Line", "Mic", "NC", + "Differential"}; +static const char const *wm8971_adcpol[] = {"Normal", "L Invert", + "R Invert", "L + R Invert"}; static const struct soc_enum wm8971_enum[] = { SOC_ENUM_SINGLE(WM8971_BASS, 7, 2, wm8971_bass), /* 0 */ @@ -136,24 +139,24 @@ static const struct snd_kcontrol_new wm8971_snd_controls[] = { SOC_DOUBLE_R("Capture Switch", WM8971_LINVOL, WM8971_RINVOL, 7, 1, 1), SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8971_LOUT1V, - WM8971_ROUT1V, 7, 1, 0), + WM8971_ROUT1V, 7, 1, 0), SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8971_LOUT2V, - WM8971_ROUT2V, 7, 1, 0), + WM8971_ROUT2V, 7, 1, 0), SOC_SINGLE("Mono Playback ZC Switch", WM8971_MOUTV, 7, 1, 0), SOC_DOUBLE_R("PCM Volume", WM8971_LDAC, WM8971_RDAC, 0, 255, 0), SOC_DOUBLE_R("Bypass Left Playback Volume", WM8971_LOUTM1, - WM8971_LOUTM2, 4, 7, 1), + WM8971_LOUTM2, 4, 7, 1), SOC_DOUBLE_R("Bypass Right Playback Volume", WM8971_ROUTM1, - WM8971_ROUTM2, 4, 7, 1), + WM8971_ROUTM2, 4, 7, 1), SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8971_MOUTM1, - WM8971_MOUTM2, 4, 7, 1), + WM8971_MOUTM2, 4, 7, 1), SOC_DOUBLE_R("Headphone Playback Volume", WM8971_LOUT1V, - WM8971_ROUT1V, 0, 127, 0), + WM8971_ROUT1V, 0, 127, 0), SOC_DOUBLE_R("Speaker Playback Volume", WM8971_LOUT2V, - WM8971_ROUT2V, 0, 127, 0), + WM8971_ROUT2V, 0, 127, 0), SOC_ENUM("Bass Boost", wm8971_enum[0]), SOC_ENUM("Bass Filter", wm8971_enum[1]), @@ -238,14 +241,14 @@ SOC_DAPM_ENUM("Route", wm8971_enum[13]); static const struct snd_soc_dapm_widget wm8971_dapm_widgets[] = { SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, - &wm8971_left_mixer_controls[0], - ARRAY_SIZE(wm8971_left_mixer_controls)), + &wm8971_left_mixer_controls[0], + ARRAY_SIZE(wm8971_left_mixer_controls)), SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, - &wm8971_right_mixer_controls[0], - ARRAY_SIZE(wm8971_right_mixer_controls)), + &wm8971_right_mixer_controls[0], + ARRAY_SIZE(wm8971_right_mixer_controls)), SND_SOC_DAPM_MIXER("Mono Mixer", WM8971_PWR2, 2, 0, - &wm8971_mono_mixer_controls[0], - ARRAY_SIZE(wm8971_mono_mixer_controls)), + &wm8971_mono_mixer_controls[0], + ARRAY_SIZE(wm8971_mono_mixer_controls)), SND_SOC_DAPM_PGA("Right Out 2", WM8971_PWR2, 3, 0, NULL, 0), SND_SOC_DAPM_PGA("Left Out 2", WM8971_PWR2, 4, 0, NULL, 0), @@ -260,18 +263,18 @@ static const struct snd_soc_dapm_widget wm8971_dapm_widgets[] = { SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8971_PWR1, 3, 0), SND_SOC_DAPM_MUX("Left PGA Mux", WM8971_PWR1, 5, 0, - &wm8971_left_pga_controls), + &wm8971_left_pga_controls), SND_SOC_DAPM_MUX("Right PGA Mux", WM8971_PWR1, 4, 0, - &wm8971_right_pga_controls), + &wm8971_right_pga_controls), SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, - &wm8971_left_line_controls), + &wm8971_left_line_controls), SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, - &wm8971_right_line_controls), + &wm8971_right_line_controls), SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, - &wm8971_monomux_controls), + &wm8971_monomux_controls), SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, - &wm8971_monomux_controls), + &wm8971_monomux_controls), SND_SOC_DAPM_OUTPUT("LOUT1"), SND_SOC_DAPM_OUTPUT("ROUT1"), @@ -431,7 +434,7 @@ static int get_coeff(int mclk, int rate) } static int wm8971_set_dai_sysclk(struct snd_soc_dai *codec_dai, - int clk_id, unsigned int freq, int dir) + int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = codec_dai->codec; struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); @@ -449,7 +452,7 @@ static int wm8971_set_dai_sysclk(struct snd_soc_dai *codec_dai, } static int wm8971_set_dai_fmt(struct snd_soc_dai *codec_dai, - unsigned int fmt) + unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; u16 iface = 0; @@ -507,8 +510,8 @@ static int wm8971_set_dai_fmt(struct snd_soc_dai *codec_dai, } static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); @@ -553,7 +556,7 @@ static int wm8971_mute(struct snd_soc_dai *dai, int mute) } static int wm8971_set_bias_level(struct snd_soc_codec *codec, - enum snd_soc_bias_level level) + enum snd_soc_bias_level level) { u16 pwr_reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; @@ -580,11 +583,12 @@ static int wm8971_set_bias_level(struct snd_soc_codec *codec, } #define WM8971_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) #define WM8971_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ - SNDRV_PCM_FMTBIT_S24_LE) + SNDRV_PCM_FMTBIT_S24_LE) static const struct snd_soc_dai_ops wm8971_dai_ops = { .hw_params = wm8971_pcm_hw_params, @@ -616,6 +620,7 @@ static void wm8971_work(struct work_struct *work) container_of(work, struct snd_soc_dapm_context, delayed_work.work); struct snd_soc_codec *codec = dapm->codec; + wm8971_set_bias_level(codec, codec->dapm.bias_level); } @@ -637,7 +642,7 @@ static int wm8971_resume(struct snd_soc_codec *codec) snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); codec->dapm.bias_level = SND_SOC_BIAS_ON; queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work, - msecs_to_jiffies(1000)); + msecs_to_jiffies(1000)); } return 0; @@ -660,7 +665,7 @@ static int wm8971_probe(struct snd_soc_codec *codec) snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); codec->dapm.bias_level = SND_SOC_BIAS_STANDBY; queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work, - msecs_to_jiffies(1000)); + msecs_to_jiffies(1000)); /* set the update bits */ snd_soc_update_bits(codec, WM8971_LDAC, 0x0100, 0x0100); @@ -729,8 +734,8 @@ static int wm8971_i2c_probe(struct i2c_client *i2c, i2c_set_clientdata(i2c, wm8971); - ret = snd_soc_register_codec(&i2c->dev, - &soc_codec_dev_wm8971, &wm8971_dai, 1); + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_wm8971, + &wm8971_dai, 1); return ret; } -- 1.7.9.5

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[alsa-devel] [PATCH] ASoC: ab8500-codec: Revert back to regmap
by Lars-Peter Clausen 01 Sep '14

01 Sep '14

Commit ff795d614bfa ("ASoC: ab8500: Convert register I/O to regmap") initially converted the ab8500 CODEC driver to use regmap rather than legacy ASoC IO. This was reverted though in commit 63e6d43bf80d ("ASoC: ab8500: Revert to using custom I/O functions") since the inital conversion was not working properly. This was presumebly because the SOC_SINGLE_XR_SX controls, which are used by this driver, did not properly support regmap at that point. This has since been fixed in commit 6137a5ca326d ("ASoC: Prepare SOC_SINGLE_XR_SX controls for regmap"). So revert back to regmap again. Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> --- I don't have the hardware, so I haven't been able to verify that it actually works now, but I think there is a very good chance. Lee, do you have access to a Snowball board and can give this a test? --- sound/soc/codecs/ab8500-codec.c | 62 +++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c index 62cf231..fd43827 100644 --- a/sound/soc/codecs/ab8500-codec.c +++ b/sound/soc/codecs/ab8500-codec.c @@ -125,6 +125,8 @@ struct ab8500_codec_drvdata_dbg { /* Private data for AB8500 device-driver */ struct ab8500_codec_drvdata { + struct regmap *regmap; + /* Sidetone */ long *sid_fir_values; enum sid_state sid_status; @@ -165,49 +167,35 @@ static inline const char *amic_type_str(enum amic_type type) */ /* Read a register from the audio-bank of AB8500 */ -static unsigned int ab8500_codec_read_reg(struct snd_soc_codec *codec, - unsigned int reg) +static int ab8500_codec_read_reg(void *context, unsigned int reg, + unsigned int *value) { + struct device *dev = context; int status; - unsigned int value = 0; u8 value8; - status = abx500_get_register_interruptible(codec->dev, AB8500_AUDIO, - reg, &value8); - if (status < 0) { - dev_err(codec->dev, - "%s: ERROR: Register (0x%02x:0x%02x) read failed (%d).\n", - __func__, (u8)AB8500_AUDIO, (u8)reg, status); - } else { - dev_dbg(codec->dev, - "%s: Read 0x%02x from register 0x%02x:0x%02x\n", - __func__, value8, (u8)AB8500_AUDIO, (u8)reg); - value = (unsigned int)value8; - } + status = abx500_get_register_interruptible(dev, AB8500_AUDIO, + reg, &value8); + *value = (unsigned int)value8; - return value; + return status; } /* Write to a register in the audio-bank of AB8500 */ -static int ab8500_codec_write_reg(struct snd_soc_codec *codec, - unsigned int reg, unsigned int value) +static int ab8500_codec_write_reg(void *context, unsigned int reg, + unsigned int value) { - int status; - - status = abx500_set_register_interruptible(codec->dev, AB8500_AUDIO, - reg, value); - if (status < 0) - dev_err(codec->dev, - "%s: ERROR: Register (%02x:%02x) write failed (%d).\n", - __func__, (u8)AB8500_AUDIO, (u8)reg, status); - else - dev_dbg(codec->dev, - "%s: Wrote 0x%02x into register %02x:%02x\n", - __func__, (u8)value, (u8)AB8500_AUDIO, (u8)reg); + struct device *dev = context; - return status; + return abx500_set_register_interruptible(dev, AB8500_AUDIO, + reg, value); } +static const struct regmap_config ab8500_codec_regmap = { + .reg_read = ab8500_codec_read_reg, + .reg_write = ab8500_codec_write_reg, +}; + /* * Controls - DAPM */ @@ -2564,9 +2552,6 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec) static struct snd_soc_codec_driver ab8500_codec_driver = { .probe = ab8500_codec_probe, - .read = ab8500_codec_read_reg, - .write = ab8500_codec_write_reg, - .reg_word_size = sizeof(u8), .controls = ab8500_ctrls, .num_controls = ARRAY_SIZE(ab8500_ctrls), .dapm_widgets = ab8500_dapm_widgets, @@ -2591,6 +2576,15 @@ static int ab8500_codec_driver_probe(struct platform_device *pdev) drvdata->anc_status = ANC_UNCONFIGURED; dev_set_drvdata(&pdev->dev, drvdata); + drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev, + &ab8500_codec_regmap); + if (IS_ERR(drvdata->regmap)) { + status = PTR_ERR(drvdata->regmap); + dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n", + __func__, status); + return status; + } + dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__); status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver, ab8500_codec_dai, -- 1.8.0

2 1

[alsa-devel] [PATCHv3] ASoC: simple-card: Fix bug of wrong decrement DT node's refcount
by Xiubo Li 01 Sep '14

01 Sep '14

DAI links's cpu_of_node's and codec_of_node's refcounts shouldn't be decremented immediately at the end of the probe() fucntion. Because we will still use them before the audio card is removed. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> Cc: Jean-Francois Moine <moinejf(a)free.fr> --- Change in v3: - Follow Jean-Francois Moine's advice. - Remove the following patch: "ASoC: simple-card: Fix bug of forgetting decrement DT node's refcount" sound/soc/generic/simple-card.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/soc/generic/simple-card.c b/sound/soc/generic/simple-card.c index fd8b045..986d2c7 100644 --- a/sound/soc/generic/simple-card.c +++ b/sound/soc/generic/simple-card.c @@ -481,12 +481,19 @@ static int asoc_simple_card_probe(struct platform_device *pdev) snd_soc_card_set_drvdata(&priv->snd_card, priv); ret = devm_snd_soc_register_card(&pdev->dev, &priv->snd_card); + if (ret >= 0) + return ret; err: asoc_simple_card_unref(pdev); return ret; } +static int asoc_simple_card_remove(struct platform_device *pdev) +{ + return asoc_simple_card_unref(pdev); +} + static const struct of_device_id asoc_simple_of_match[] = { { .compatible = "simple-audio-card", }, {}, @@ -500,6 +507,7 @@ static struct platform_driver asoc_simple_card = { .of_match_table = asoc_simple_of_match, }, .probe = asoc_simple_card_probe, + .remove = asoc_simple_card_remove, }; module_platform_driver(asoc_simple_card); -- 1.8.4

2 1

[alsa-devel] [PATCH v4 0/2] ASoC: tda998x: add a codec to the HDMI transmitter
by Jean-Francois Moine 01 Sep '14

01 Sep '14

The NXP TDA998x HDMI transmitter may transmit audio to the HDMI link from 2 different sources, I2S and S/PDIF. This patch set adds a generic HDMI CODEC module which is used by the TDA998x driver to update the audio constraints from the display characteristics (EDID) and by the audio subsystem to connect the chosen audio source to the HDMI link. v4: - remove all the TDA998x specific stuff from the CODEC - move the EDID scan from the CODEC to the TDA998x - move the CODEC to sound/soc (Mark Brown) - update the audio_sample_rate from the EDID (Andrew Jackson) v3: fix bad rate (Andrew Jackson) v2: check double stream start (Mark Brown) Jean-Francois Moine (2): ASoC:codecs: Add a generic HDMI audio CODEC drm/i2c:tda998x: Use the HDMI2 audio CODEC Documentation/devicetree/bindings/sound/hdmi2.txt | 32 ++++ drivers/gpu/drm/i2c/Kconfig | 1 + drivers/gpu/drm/i2c/tda998x_drv.c | 142 ++++++++++++++- include/sound/hdmi2.h | 24 +++ sound/soc/codecs/Kconfig | 3 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/hdmi2.c | 204 ++++++++++++++++++++++ 7 files changed, 400 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/hdmi2.txt create mode 100644 include/sound/hdmi2.h create mode 100644 sound/soc/codecs/hdmi2.c -- 2.1.0

2 3

[alsa-devel] [PATCHv2] ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.
by Xiubo Li 01 Sep '14

01 Sep '14

The 'big-endian-data' property is originally used to indicate whether the LSB firstly or MSB firstly will be transmitted to the CODEC or received from the CODEC, and there has nothing relation to the memory data. Generally, if the audio data in big endian format, which will be using the bytes reversion, Here this can only be used to bits reversion. So using the 'lsb-first' instead of 'big-endian-data' can make the code to be readable easier and more easy to understand what this property is used to do. This property used for configuring whether the LSB or the MSB is transmitted first for the fifo data. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> Cc: Nicolin Chen <nicoleotsuka(a)gmail.com> --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 8 ++++---- sound/soc/fsl/fsl_sai.c | 6 +++--- sound/soc/fsl/fsl_sai.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 06a405e..4956b14 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -20,9 +20,9 @@ Required properties: See ../pinctrl/pinctrl-bindings.txt for details of the property values. - big-endian: Boolean property, required if all the FTM_PWM registers are big-endian rather than little-endian. -- big-endian-data: If this property is absent, the little endian mode will - be in use as default, or the big endian mode will be in use for all the - fifo data. +- lsb-first: Configures whether the LSB or the MSB is transmitted first for + the fifo data. If this property is absent, the MSB is transmitted first as + default, or the LSB is transmitted first. - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating that SAI will work in the synchronous mode (sync Tx with Rx) which means both the transimitter and receiver will send and receive data by following @@ -53,5 +53,5 @@ sai2: sai@40031000 { dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; big-endian; - big-endian-data; + lsb-first; }; diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index a6eb784..7eeb1dd 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -175,7 +175,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, bool tx = fsl_dir == FSL_FMT_TRANSMITTER; u32 val_cr2 = 0, val_cr4 = 0; - if (!sai->big_endian_data) + if (!sai->is_lsb_first) val_cr4 |= FSL_SAI_CR4_MF; /* DAI mode */ @@ -304,7 +304,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, val_cr5 |= FSL_SAI_CR5_WNW(word_width); val_cr5 |= FSL_SAI_CR5_W0W(word_width); - if (sai->big_endian_data) + if (sai->is_lsb_first) val_cr5 |= FSL_SAI_CR5_FBT(0); else val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); @@ -573,7 +573,7 @@ static int fsl_sai_probe(struct platform_device *pdev) if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) sai->sai_on_imx = true; - sai->big_endian_data = of_property_read_bool(np, "big-endian-data"); + sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 2cded44..3466720 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -132,7 +132,7 @@ struct fsl_sai { struct clk *bus_clk; struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; - bool big_endian_data; + bool is_lsb_first; bool is_dsp_mode; bool sai_on_imx; bool synchronous[2]; -- 1.8.5

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[alsa-devel] [PATCH 1/3 v4 RESEND] mfd: arizona: Export function to control subsystem DVFS
by Richard Fitzgerald 01 Sep '14

01 Sep '14

From: Richard Fitzgerald <rf(a)opensource.wolfsonmicro.com> Moving this control from being a side-effect of the LDO1 regulator driver to a specific exported function. Signed-off-by: Richard Fitzgerald <rf(a)opensource.wolfsonmicro.com> Signed-off-by: Charles Keepax <ckeepax(a)opensource.wolfsonmicro.com> --- drivers/mfd/arizona-core.c | 89 ++++++++++++++++++++++++++++++++++++++ include/linux/mfd/arizona/core.h | 12 +++++ 2 files changed, 101 insertions(+), 0 deletions(-) diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c index cfc191a..04cde4b 100644 --- a/drivers/mfd/arizona-core.c +++ b/drivers/mfd/arizona-core.c @@ -94,6 +94,94 @@ int arizona_clk32k_disable(struct arizona *arizona) } EXPORT_SYMBOL_GPL(arizona_clk32k_disable); +int arizona_dvfs_up(struct arizona *arizona, unsigned int flags) +{ + unsigned int new_flags; + int ret = 0; + + mutex_lock(&arizona->subsys_max_lock); + + new_flags = arizona->subsys_max_rq | flags; + + if (arizona->subsys_max_rq != new_flags) { + switch (arizona->type) { + case WM5102: + case WM8997: + ret = regulator_set_voltage(arizona->dcvdd, + 1800000, 1800000); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to set DCVDD (DVFS up): %d\n", + ret); + goto err; + } + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_DYNAMIC_FREQUENCY_SCALING_1, + ARIZONA_SUBSYS_MAX_FREQ, 1); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to enable subsys max: %d\n", + ret); + regulator_set_voltage(arizona->dcvdd, + 1200000, 1800000); + goto err; + } + break; + + default: + break; + } + + arizona->subsys_max_rq = new_flags; + } +err: + mutex_unlock(&arizona->subsys_max_lock); + return ret; +} +EXPORT_SYMBOL_GPL(arizona_dvfs_up); + +int arizona_dvfs_down(struct arizona *arizona, unsigned int flags) +{ + int ret = 0; + + mutex_lock(&arizona->subsys_max_lock); + + if ((arizona->subsys_max_rq & flags) != flags) + dev_warn(arizona->dev, "Unbalanced DVFS down: %x\n", flags); + + arizona->subsys_max_rq &= ~flags; + + if (arizona->subsys_max_rq == 0) { + switch (arizona->type) { + case WM5102: + case WM8997: + ret = regmap_update_bits(arizona->regmap, + ARIZONA_DYNAMIC_FREQUENCY_SCALING_1, + ARIZONA_SUBSYS_MAX_FREQ, 0); + if (ret != 0) + dev_err(arizona->dev, + "Failed to disable subsys max: %d\n", + ret); + + ret = regulator_set_voltage(arizona->dcvdd, + 1200000, 1800000); + if (ret != 0) + dev_err(arizona->dev, + "Failed to set DCVDD (DVFS down): %d\n", + ret); + break; + + default: + break; + } + } + + mutex_unlock(&arizona->subsys_max_lock); + return ret; +} +EXPORT_SYMBOL_GPL(arizona_dvfs_down); + static irqreturn_t arizona_clkgen_err(int irq, void *data) { struct arizona *arizona = data; @@ -641,6 +729,7 @@ int arizona_dev_init(struct arizona *arizona) dev_set_drvdata(arizona->dev, arizona); mutex_init(&arizona->clk_lock); + mutex_init(&arizona->subsys_max_lock); if (dev_get_platdata(arizona->dev)) memcpy(&arizona->pdata, dev_get_platdata(arizona->dev), diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h index a614b33..4aec6a3 100644 --- a/include/linux/mfd/arizona/core.h +++ b/include/linux/mfd/arizona/core.h @@ -109,6 +109,9 @@ struct arizona { struct mutex clk_lock; int clk32k_ref; + struct mutex subsys_max_lock; + unsigned int subsys_max_rq; + struct snd_soc_dapm_context *dapm; int tdm_width[ARIZONA_MAX_AIF]; @@ -118,8 +121,17 @@ struct arizona { uint8_t dac_comp_enabled; }; +#define ARIZONA_DVFS_SR1_RQ 0x00000001 +#define ARIZONA_DVFS_SR2_RQ 0x00000002 +#define ARIZONA_DVFS_SR3_RQ 0x00000004 +#define ARIZONA_DVFS_ASR1_RQ 0x00000010 +#define ARIZONA_DVFS_ASR2_RQ 0x00000020 +#define ARIZONA_DVFS_ADSP1_RQ 0x00010000 + int arizona_clk32k_enable(struct arizona *arizona); int arizona_clk32k_disable(struct arizona *arizona); +int arizona_dvfs_up(struct arizona *arizona, unsigned int mask); +int arizona_dvfs_down(struct arizona *arizona, unsigned int mask); int arizona_request_irq(struct arizona *arizona, int irq, char *name, irq_handler_t handler, void *data); -- 1.7.2.5

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Re: [alsa-devel] [v3 04/11] ASoC: Intel: sst: Add IPC handling
by Mark Brown 01 Sep '14

01 Sep '14

On Mon, Sep 01, 2014 at 05:47:53PM +0530, Subhransu S. Prusty wrote: > On Wed, Aug 27, 2014 at 09:37:37PM +0100, Mark Brown wrote: > > > + spin_unlock_bh(&ctx->block_lock); > > > + return 0; > > > + } > > > + } > > > + spin_unlock_bh(&ctx->block_lock); > > > + return -EINVAL; > > I'd expect much louder complaints if we try to free something that's not > > allocated - what happens if we end up reallocating something quickly and > > then double freeing? Better to complain if we hit such a code path. > "freed" is a block which is passed by the caller to be freed up. Will add a > comment. How would that address the problem? Obviously the caller is trying to free what they're passing in.

2 1

[alsa-devel] [PATCH alsa-lib] pcm: fix snd_pcm_mmap_hw_avail() near the boundary
by Alexander E. Patrakov 01 Sep '14

01 Sep '14

This function returned incorrect results when hw.ptr was near the boundary and hw.appl_ptr was near zero. Here "incorrect" means "greater than the boundary". The result was incorrect, because it was used as a return value of various *_rewindable() functions and also as the delay for ioplug. Signed-off-by: Alexander E. Patrakov <patrakov(a)gmail.com> --- src/pcm/pcm_local.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/pcm/pcm_local.h b/src/pcm/pcm_local.h index 80bbe59..74ebd60 100644 --- a/src/pcm/pcm_local.h +++ b/src/pcm/pcm_local.h @@ -461,13 +461,7 @@ static inline snd_pcm_sframes_t snd_pcm_mmap_capture_hw_avail(snd_pcm_t *pcm) static inline snd_pcm_sframes_t snd_pcm_mmap_hw_avail(snd_pcm_t *pcm) { - snd_pcm_sframes_t avail; - avail = *pcm->hw.ptr - *pcm->appl.ptr; - if (pcm->stream == SND_PCM_STREAM_PLAYBACK) - avail += pcm->buffer_size; - if (avail < 0) - avail += pcm->boundary; - return pcm->buffer_size - avail; + return pcm->buffer_size - snd_pcm_mmap_avail(pcm); } static inline const snd_pcm_channel_area_t *snd_pcm_mmap_areas(snd_pcm_t *pcm) -- 2.1.0

2 1

[alsa-devel] [PATCH] ALSA: hda - Fix digital mic on Acer Aspire 3830TG
by Takashi Iwai 01 Sep '14

01 Sep '14

Acer Aspire 3830TG with CX20588 codec has a digital built-in mic that has the same problem like many others, the inverted signal in stereo. Apply the same fixup to this machine, too. Cc: <stable(a)vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_conexant.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c index 6f2fa838b635..6e5d0cb4e3d7 100644 --- a/sound/pci/hda/patch_conexant.c +++ b/sound/pci/hda/patch_conexant.c @@ -217,6 +217,7 @@ enum { CXT_FIXUP_HEADPHONE_MIC_PIN, CXT_FIXUP_HEADPHONE_MIC, CXT_FIXUP_GPIO1, + CXT_FIXUP_ASPIRE_DMIC, CXT_FIXUP_THINKPAD_ACPI, CXT_FIXUP_OLPC_XO, CXT_FIXUP_CAP_MIX_AMP, @@ -664,6 +665,12 @@ static const struct hda_fixup cxt_fixups[] = { { } }, }, + [CXT_FIXUP_ASPIRE_DMIC] = { + .type = HDA_FIXUP_FUNC, + .v.func = cxt_fixup_stereo_dmic, + .chained = true, + .chain_id = CXT_FIXUP_GPIO1, + }, [CXT_FIXUP_THINKPAD_ACPI] = { .type = HDA_FIXUP_FUNC, .v.func = hda_fixup_thinkpad_acpi, @@ -744,7 +751,7 @@ static const struct hda_model_fixup cxt5051_fixup_models[] = { static const struct snd_pci_quirk cxt5066_fixups[] = { SND_PCI_QUIRK(0x1025, 0x0543, "Acer Aspire One 522", CXT_FIXUP_STEREO_DMIC), - SND_PCI_QUIRK(0x1025, 0x054c, "Acer Aspire 3830TG", CXT_FIXUP_GPIO1), + SND_PCI_QUIRK(0x1025, 0x054c, "Acer Aspire 3830TG", CXT_FIXUP_ASPIRE_DMIC), SND_PCI_QUIRK(0x1043, 0x138d, "Asus", CXT_FIXUP_HEADPHONE_MIC_PIN), SND_PCI_QUIRK(0x152d, 0x0833, "OLPC XO-1.5", CXT_FIXUP_OLPC_XO), SND_PCI_QUIRK(0x17aa, 0x20f2, "Lenovo T400", CXT_PINCFG_LENOVO_TP410), -- 2.1.0

1 0

[alsa-devel] [v3 00/11] ASoC: Intel: sst - add the merrifield IPC driver
by Subhransu S. Prusty 01 Sep '14

01 Sep '14

This path series adds the Merrifield IPC driver which is used to load and manage the DSP along with sending and receiving IPCs for PCM and compressed audio. Changes in v3: * First patch is splitted into multiple patches * Now download fw during device resume * Removed runtime reference counting from driver context * Using dedicated functions instead ioctl * Addressed review comments Subhransu S. Prusty (8): ASoC: Intel: mrfld - add the dsp sst driver ASoC: Intel: mrfld - Add DSP load and management ASoC: Intel: sst - add pcm ops handling ASoC: Intel: sst: Add IPC handling ASoC: Intel: sst: add stream operations ASoC: Intel: sst: Add some helper functions ASoC: Intel: sst: Add makefile and kconfig changes ASoC: mfld-compress: Use dedicated function instead of ioctl Vinod Koul (3): ASoC: Intel: sst: add power management handling ASoC: Intel: sst: load firmware using async callback ASoC: Intel: sst - add compressed ops handling arch/x86/include/asm/platform_sst_audio.h | 33 + sound/soc/intel/Kconfig | 4 + sound/soc/intel/Makefile | 3 + sound/soc/intel/sst-mfld-platform-compress.c | 38 +- sound/soc/intel/sst-mfld-platform.h | 27 +- sound/soc/intel/sst/Makefile | 3 + sound/soc/intel/sst/sst.c | 576 ++++++++++++++++ sound/soc/intel/sst/sst.h | 654 ++++++++++++++++++ sound/soc/intel/sst/sst_drv_interface.c | 784 +++++++++++++++++++++ sound/soc/intel/sst/sst_ipc.c | 368 ++++++++++ sound/soc/intel/sst/sst_loader.c | 975 +++++++++++++++++++++++++++ sound/soc/intel/sst/sst_pvt.c | 207 ++++++ sound/soc/intel/sst/sst_stream.c | 526 +++++++++++++++ 13 files changed, 4179 insertions(+), 19 deletions(-) create mode 100644 sound/soc/intel/sst/Makefile create mode 100644 sound/soc/intel/sst/sst.c create mode 100644 sound/soc/intel/sst/sst.h create mode 100644 sound/soc/intel/sst/sst_drv_interface.c create mode 100644 sound/soc/intel/sst/sst_ipc.c create mode 100644 sound/soc/intel/sst/sst_loader.c create mode 100644 sound/soc/intel/sst/sst_pvt.c create mode 100644 sound/soc/intel/sst/sst_stream.c -- 1.9.0

2 24

Re: [alsa-devel] [v3 01/11] ASoC: Intel: mrfld - add the dsp sst driver
by Mark Brown 01 Sep '14

01 Sep '14

On Mon, Sep 01, 2014 at 04:07:55PM +0530, Subhransu S. Prusty wrote: > On Wed, Aug 27, 2014 at 08:40:21PM +0100, Mark Brown wrote: > > On Thu, Aug 21, 2014 at 06:20:40PM +0530, Subhransu S. Prusty wrote: > > > +static inline unsigned int sst_assign_pvt_id(struct intel_sst_drv *sst_drv_ctx) > > > +{ > > > + unsigned int local; > > > + > > > + spin_lock(&sst_drv_ctx->block_lock); > > > + sst_drv_ctx->pvt_id++; > > > + if (sst_drv_ctx->pvt_id > MAX_BLOCKS) > > > + sst_drv_ctx->pvt_id = 1; > > > + local = sst_drv_ctx->pvt_id; > > > + spin_unlock(&sst_drv_ctx->block_lock); > > > + return local; > > > +} > > The comments about overflow continue to apply here. > Vinod has already replied to you regarding this, below is a snippet from > the conversation earlier. Is there anything else we need to address? Yes, and as I said I just don't buy that argument. It's code that has fairly clear problems on inspection, saying "we've not hit the problem yet" isn't particularly persuasive. Something like a new firmware could easily trigger problems.

1 0

[alsa-devel] [PATCH -next] ASoC: es8328: fix error return code in es8328_codec_probe()
by weiyj_lk＠163.com 01 Sep '14

01 Sep '14

From: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Signed-off-by: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> --- sound/soc/codecs/es8328.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/codecs/es8328.c b/sound/soc/codecs/es8328.c index 7a9f65a..3ff7870 100644 --- a/sound/soc/codecs/es8328.c +++ b/sound/soc/codecs/es8328.c @@ -665,6 +665,7 @@ static int es8328_codec_probe(struct snd_soc_codec *codec) es8328->clk = devm_clk_get(codec->dev, NULL); if (IS_ERR(es8328->clk)) { dev_err(codec->dev, "codec clock missing or invalid\n"); + ret = PTR_ERR(es8328->clk); goto clk_fail; }

2 1

[alsa-devel] [PATCH] ASoC: tlv320aic31xx: Correct interface register 2 variable name
by Peter Ujfalusi 01 Sep '14

01 Sep '14

Rename iface_reg3 to iface_reg2 since this variable is actually used for interface register 2. Signed-off-by: Peter Ujfalusi <peter.ujfalusi(a)ti.com> --- sound/soc/codecs/tlv320aic31xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c index 0f64c7890eed..9f9d23b94c22 100644 --- a/sound/soc/codecs/tlv320aic31xx.c +++ b/sound/soc/codecs/tlv320aic31xx.c @@ -813,7 +813,7 @@ static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, { struct snd_soc_codec *codec = codec_dai->codec; u8 iface_reg1 = 0; - u8 iface_reg3 = 0; + u8 iface_reg2 = 0; u8 dsp_a_val = 0; dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt); @@ -838,7 +838,7 @@ static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_NB_NF: - iface_reg3 |= AIC31XX_BCLKINV_MASK; + iface_reg2 |= AIC31XX_BCLKINV_MASK; break; case SND_SOC_DAIFMT_IB_NF: break; @@ -870,7 +870,7 @@ static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, dsp_a_val); snd_soc_update_bits(codec, AIC31XX_IFACE2, AIC31XX_BCLKINV_MASK, - iface_reg3); + iface_reg2); return 0; } -- 2.0.4

2 1

[alsa-devel] [PATCH v5 0/2] mfd: arizona: add support for INn_MODE register control
by Inha Song 01 Sep '14

01 Sep '14

This patch series add support for INn_MODE register control using platform data. Each input signal path can be configurated either as a Analogue or Digital using the INn_MODE registers. Changes for v5 - Change to use of_property_for_each_u32 Changes for v4 - Update document content for more clarity Changes for v3 - Change to use of_property_read_u32_array - Fix a few typos - Update commit message Changes for v2 - Change to support - Update commit message - Update document content for more clarity Inha Song (2): mfd: arizona: Add support for INn_Mode register control mfd: arizona: Update DT binding to support INn_MODE init_data Documentation/devicetree/bindings/mfd/arizona.txt | 7 +++++++ drivers/mfd/arizona-core.c | 13 +++++++++++++ 2 files changed, 20 insertions(+) -- 2.0.0.390.gcb682f8

3 6

[alsa-devel] [PATCHv2 0/2] ASoC: simple-card: Fix bug about DT node's refcount
by Xiubo Li 01 Sep '14

01 Sep '14

Change for v2: - Just rebased to the next branch newest head. Xiubo Li (2): ASoC: simple-card: Fix bug of forgetting decrement DT node's refcount ASoC: simple-card: Fix bug of wrong decrement DT node's refcount sound/soc/generic/simple-card.c | 53 ++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 24 deletions(-) -- 1.8.4

3 6

Re: [alsa-devel] [PATCH] ALSA: virtuoso: add Xonar Essence STX II support
by Andreas Allacher 31 Aug '14

31 Aug '14

Just to let you know. I might not be able to do the test today (but I hope I will be able to). If not, it will be sometime in the coming week but cannot say when. Regards, Andreas Am 29.08.2014 21:08, schrieb Clemens Ladisch: > Andreas Allacher wrote: >> Is the path already in the kernel source git or do I have to apply it manually? > This patch is completely untested and not yet in any git. > > > Regards, > Clemens >

1 0

[alsa-devel] [PATCH 0/2] rockchip-i2s: add power setting for I2S controller and fix some critical bugs
by Jianqun 30 Aug '14

30 Aug '14

Add optional power setting for i2s controller found on rk3066, rk3168 and rk3288 processors from rockchip, should according to hardware design. Default setting for I2S controller is powered by 3.3V, there needs this patch if it's powered by 1.8V by hardware design. Jianqun (2): rockchip-i2s: dt: add grf requested properties to set power of I2S controller rockchip-i2s: add power setting for I2S controller, also fix some bugs .../devicetree/bindings/sound/rockchip-i2s.txt | 6 +- sound/soc/rockchip/rockchip_i2s.c | 93 +++++++++++++--------- sound/soc/rockchip/rockchip_i2s.h | 13 +-- 3 files changed, 68 insertions(+), 44 deletions(-) -- 1.8.3.2

4 5

[alsa-devel] [PATCH] ALSA: hda - Add a de-pop quirk for some HP machines
by Hui Wang 30 Aug '14

30 Aug '14

On some HP machines, there will be pop noise when the machine is shutting down, rebooting or booting up from poweroff state. Set EAPD enable only when stream starts can help to fix this problem. [The patch was originally written by Kailang, we tested it and rebased it on latest kernel.] Signed-off-by: Kailang Yang <kailang(a)realtek.com> Signed-off-by: Hui Wang <hui.wang(a)canonical.com> --- sound/pci/hda/patch_realtek.c | 55 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 48d6d10..51811a6 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -4282,6 +4282,47 @@ static void alc290_fixup_mono_speakers(struct hda_codec *codec, } } +/* + * ALC290 PCM hooks + */ +static void alc290_playback_pcm_hook(struct hda_pcm_stream *hinfo, + struct hda_codec *codec, + struct snd_pcm_substream *substream, + int action) +{ + int val; + + switch (action) { + case HDA_GEN_PCM_ACT_OPEN: + val = alc_read_coef_idx(codec, 0x4); /* EAPD manual high */ + if ((val & 0xc000) != 0xc000) + alc_write_coef_idx(codec, 0x4, val | (1<<14)); + break; + } +} + +static void alc290_fixup_pop_noise(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + struct alc_spec *spec = codec->spec; + int val; + + switch (action) { + case HDA_FIXUP_ACT_PRE_PROBE: + snd_hda_codec_write(codec, 0x17, 0, + AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); + val = alc_read_coef_idx(codec, 0x4); + if ((val & 0xc000) != 0xc000) + alc_write_coef_idx(codec, 0x4, val | (3<<14)); /* EAPD low */ + spec->gen.pcm_playback_hook = alc290_playback_pcm_hook; + break; + case HDA_FIXUP_ACT_INIT: + snd_hda_codec_write(codec, 0x17, 0, + AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); + break; + } +} + /* for hda_fixup_thinkpad_acpi() */ #include "thinkpad_helper.c" @@ -4354,6 +4395,7 @@ enum { ALC283_FIXUP_BXBT2807_MIC, ALC255_FIXUP_DELL_WMI_MIC_MUTE_LED, ALC282_FIXUP_ASPIRE_V5_PINS, + ALC290_FIXUP_HP_DEPOP_WITH_MUTE_LED, }; static const struct hda_fixup alc269_fixups[] = { @@ -4817,7 +4859,12 @@ static const struct hda_fixup alc269_fixups[] = { { }, }, }, - + [ALC290_FIXUP_HP_DEPOP_WITH_MUTE_LED] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc290_fixup_pop_noise, + .chained = true, + .chain_id = ALC269_FIXUP_HP_MUTE_LED_MIC1, + }, }; static const struct snd_pci_quirk alc269_fixup_tbl[] = { @@ -4975,12 +5022,14 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x103c, 0x2280, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), SND_PCI_QUIRK(0x103c, 0x2281, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), SND_PCI_QUIRK(0x103c, 0x2282, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), - SND_PCI_QUIRK(0x103c, 0x2289, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), + SND_PCI_QUIRK(0x103c, 0x2289, "HP", ALC290_FIXUP_HP_DEPOP_WITH_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x228a, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), SND_PCI_QUIRK(0x103c, 0x228b, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), - SND_PCI_QUIRK(0x103c, 0x228c, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), + SND_PCI_QUIRK(0x103c, 0x228c, "HP", ALC290_FIXUP_HP_DEPOP_WITH_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x228d, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), SND_PCI_QUIRK(0x103c, 0x228e, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), + SND_PCI_QUIRK(0x103c, 0x228f, "HP", ALC290_FIXUP_HP_DEPOP_WITH_MUTE_LED), + SND_PCI_QUIRK(0x103c, 0x22a8, "HP", ALC290_FIXUP_HP_DEPOP_WITH_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x22c5, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), SND_PCI_QUIRK(0x103c, 0x22c6, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), SND_PCI_QUIRK(0x103c, 0x22c7, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1), -- 1.9.1

4 5

[alsa-devel] icon utrack pro usb audio interface
by Adrien Plisson 30 Aug '14

30 Aug '14

hello, i just bought an "icon utrack pro" usb audio interface <http://www.icon-global.com/ShowPro.aspx?ID=24>. as expected, this interface is not supported under linux: it is not usb audio class compliant, even the midi port is not class compliant... first, i would like to know if anybody ever managed to use this interface under linux: is there an existing driver ? a hack or patch that would allow the kernel to recognize this interface ? a specific module dedicated to this kind of interface ? i can't find any reference to this interface anywhere on the net... anyway, while searching, i found that its firewire counterpart, the "firexon", has an experimental support on ffado. it seems that the firewire interface uses the bridgeco BeBoB chipset. given that some versions of BeBoB supports both firewire and usb, i suppose (but i may be wrong) that the "utrack pro" is also based on BeBoB. is there any other BeBoB based usb interface supported under linux ? finally, i would proudly help the development of a specific driver for this interface: if anyone wants me to test some piece of code, or wants some information on this interface, don't hesitate to contact me. i am also a software developper, so i could help writing a module, but i first need to learn more about the alsa code base (actually, i don't know where to start...). thanks a lot, and have a nice day ! -- rien

3 3

[alsa-devel] [PATCH] Documentation: fsl, ssi.txt: Avoid cryptic acronyms
by Fabio Estevam 29 Aug '14

29 Aug '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> It is much clearer to use the full terms here: left-justified/right-justified. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Documentation/devicetree/bindings/sound/fsl,ssi.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt index 3aa4a8f..ceca880 100644 --- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt +++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt @@ -62,9 +62,9 @@ Optional properties: "i2s-slave" - I2S mode, SSI is clock slave "i2s-master" - I2S mode, SSI is clock master "lj-slave" - left-justified mode, SSI is clock slave - "lj-master" - l.j. mode, SSI is clock master + "lj-master" - left-justified mode, SSI is clock master "rj-slave" - right-justified mode, SSI is clock slave - "rj-master" - r.j., SSI is clock master + "rj-master" - right-justified mode, SSI is clock master "ac97-slave" - AC97 mode, SSI is clock slave "ac97-master" - AC97 mode, SSI is clock master -- 1.9.1

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Re: [alsa-devel] [PATCH] ALSA: virtuoso: add Xonar Essence STX II support
by Andreas Allacher 29 Aug '14

29 Aug '14

On 26.08.2014 10:44, Andreas Allacher wrote: > Andreas Allacher wrote: > >/ Is there any reason why the daughterboard does not work yet? > / > No code written yet. > > Does your question imply that you would be able to test it? > > > Regards, > Clemens Not yet, but I would be willing to buy and test it, if someone were to write the code. In that case I would order the device today or tomorrow. Regards, Andreas

2 4

[alsa-devel] [PATCH 0/8] ASoC: simple-card: DPCM support
by Kuninori Morimoto 29 Aug '14

29 Aug '14

Hi Mark These patches are DPCM support for simple-card, and milestone is (*) * 1. simple DPCM support on DT 2. sampling rate convert support on DPCM 3. multi FE/BE support on DT 4. rsnd multi block IP use multi DPCM 1) - 4) are tidyup patches of simple-card 5) adds DPCM support on simple-card 6) tidyups asoc_simple_card_sub_parse_of() (based on 5) 7) is requred DPCM on Renesas R-Car driver 8) is DT support on dummy driver 5) and 8) are main patch for DPCM on simple-card. I'm still not 100% understand about DPCM, but 8) patch was needed to DPCM FE/BE route, but is it wrong solution ? About 5) patch, I know Lars-Peter pointed DT idea for DPCM via http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/medi… My 5) patch used this idea, but, not 100%. Because DPCM can use multi FE-BE connection (?) So, it is just pointing BE endpoint via "remote". /* FrontEnd */ simple-audio-card,dai-link@0 { remote = <&endpoint>; cpu { ... }; codec { ... }; }; /* BackEnd */ endpoint: simple-audio-card,dai-link@1 { cpu { ... }; codec { ... }; }; We can list many DAI in future ? remote = <&endpoint0, &endpoint1, &endpoint2>; Kuninori Morimoto (8): 1) ASoC: simple-card: use asoc_simple_xxx prefix 2) ASoC: simple-card: remove dai_link->cpu_dai_name when DT 3) ASoC: simple-card: dai_link->init should be cared when multi DAI 4) ASoC: simple-card: use common for_each_child_of_node() for loop 5) ASoC: simple-card: add DPCM support when DT case 6) ASoC: simple-card: remove is_top_level_node from asoc_simple_card_sub_parse_of() 7) ASoC: rsnd: add dai_link stream name 8) ASoC: add snd-soc-dummy DT support .../devicetree/bindings/sound/simple-card.txt | 35 +++++++++ .../devicetree/bindings/sound/snd-soc-dummy | 13 +++ sound/soc/generic/simple-card.c | 83 +++++++++++++------- sound/soc/sh/rcar/core.c | 8 ++ sound/soc/sh/rcar/rsnd.h | 1 + sound/soc/soc-utils.c | 12 ++- 6 files changed, 120 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/snd-soc-dummy -- 1.7.9.5 Best regards --- Kuninori Morimoto

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[alsa-devel] [PATCH v4 00/15] Rework OMAP4+ HDMI audio support
by Jyri Sarha 29 Aug '14

29 Aug '14

The patches are based on: git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux.git for-next The base, the patches, and couple of additional not-to-be-merged omap2plus_defconfig patches can be found here: git://git.ti.com/~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-fe… omap-hdmi-audio Changes since v3: - Move ASoC parts into library module under sound/soc/omap - Come up with API for the library - Some cleaning up The patch set fixes OMAP4+ HDMI audio. The structure of the implementation looks a bit different than before. Instead of creating a driver specific API for a separate ASoC component driver to connect to, these patches implement a single audio library module under sound/soc/omap for ASoC side implementation. The library exports omap_hdmi_audio_register() and omap_hdmi_audio_unregister() functions. With the functions OMAPDSS HDMI implementation registers and unregisters all ASoC components needed for OMAP HDMI audio. The library implements cpu-dai component using the callbacks provided by OMAPDSS. Omap-pcm is registered for platform component, dummy hdmi-audio-codec is registered for codec component, and asoc-simple-card is registered for machine driver. Big part of the HDMI audio code is still unchanged and there is a need for a cleanup there. Also there is still probably something wrong with speaker mapping of multi-channel streams. I will get back to cleaning up these issues later. Best regards, Jyri Jyri Sarha (15): OMAPDSS: hdmi.h: Add HDMI_AUDIO_LAYOUT_6CH enum value OMAPDSS: hdmi: Remove most of OMAP[45]_DSS_HDMI_AUDIO ifdefs OMAPDSS: hdmi4_core: Remove unused hdmi4_audio_get_dma_port() OMAPDSS: hdmi_wp: Add function for getting audio dma address OMAPDSS: hdmi: Make hdmi structure public OMAPDSS: hdmi: Add exported functions for storing HDMI audio data OMAPDSS: hdmi: Make hdmi_mode_has_audio() more user friedly ASoC: omap-hdmi-audio: Add OMAP HDMI audio support library OMAPDSS: Kconfig: Implement options for OMAP4 and OMAP5 HDMI audio support OMAPDSS: hdmi4: Register HDMI audio with omap_hdmi_audio_register() OMAPDSS: hdmi5: Register HDMI audio with omap_hdmi_audio_register() ASoC: omap: Remove obsolete HDMI audio code and Kconfig options OMAPDSS: hdmi4: Remove callbacks for an external ASoC DAI driver OMAPDSS: hdmi5: Remove callbacks for an external ASoC DAI driver OMAPDSS: Remove all references to obsolete HDMI audio callbacks .../fbdev/omap2/displays-new/connector-hdmi.c | 99 ------ .../fbdev/omap2/displays-new/encoder-tpd12s015.c | 56 --- drivers/video/fbdev/omap2/dss/Kconfig | 28 +- drivers/video/fbdev/omap2/dss/hdmi.h | 35 +- drivers/video/fbdev/omap2/dss/hdmi4.c | 233 ++++++------- drivers/video/fbdev/omap2/dss/hdmi4_core.c | 14 - drivers/video/fbdev/omap2/dss/hdmi4_core.h | 4 - drivers/video/fbdev/omap2/dss/hdmi5.c | 216 +++++------- drivers/video/fbdev/omap2/dss/hdmi5_core.c | 6 - drivers/video/fbdev/omap2/dss/hdmi5_core.h | 2 - drivers/video/fbdev/omap2/dss/hdmi_common.c | 18 +- drivers/video/fbdev/omap2/dss/hdmi_wp.c | 8 +- include/sound/omap-hdmi-audio.h | 50 +++ include/video/omapdss.h | 34 +- sound/soc/omap/Kconfig | 15 +- sound/soc/omap/Makefile | 6 +- sound/soc/omap/omap-hdmi-audio.c | 357 +++++++++++++++++++ sound/soc/omap/omap-hdmi-card.c | 87 ----- sound/soc/omap/omap-hdmi.c | 364 -------------------- sound/soc/omap/omap-hdmi.h | 38 -- 20 files changed, 676 insertions(+), 994 deletions(-) create mode 100644 include/sound/omap-hdmi-audio.h create mode 100644 sound/soc/omap/omap-hdmi-audio.c delete mode 100644 sound/soc/omap/omap-hdmi-card.c delete mode 100644 sound/soc/omap/omap-hdmi.c delete mode 100644 sound/soc/omap/omap-hdmi.h -- 1.7.9.5

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[alsa-devel] [PATCH] ASoC: omap-twl4030: Fix typo in 2nd dai link's platform_name
by Peter Ujfalusi 29 Aug '14

29 Aug '14

The platform_name should be omap-mcasp3 for the 2nd link which is used for voice connection. Reported-by: Tony Lindgren <tony(a)atomide.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi(a)ti.com> --- sound/soc/omap/omap-twl4030.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/omap/omap-twl4030.c b/sound/soc/omap/omap-twl4030.c index f8a6adc2d81c..4336d1831485 100644 --- a/sound/soc/omap/omap-twl4030.c +++ b/sound/soc/omap/omap-twl4030.c @@ -260,7 +260,7 @@ static struct snd_soc_dai_link omap_twl4030_dai_links[] = { .stream_name = "TWL4030 Voice", .cpu_dai_name = "omap-mcbsp.3", .codec_dai_name = "twl4030-voice", - .platform_name = "omap-mcbsp.2", + .platform_name = "omap-mcbsp.3", .codec_name = "twl4030-codec", .dai_fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM, -- 2.0.4

2 1

[alsa-devel] [PATCH 0/2] ASoC: simple-card: Fix bug about DT node's refcount
by Xiubo Li 29 Aug '14

29 Aug '14

This patch series hasn't any dependency with the previous one: "[RFC][PATCH] ASoC: simple-card: Merge single and muti DAI link code." Xiubo Li (2): ASoC: simple-card: Fix bug of forgetting decrement DT node's refcount ASoC: simple-card: Fix bug of wrong decrement DT node's refcount sound/soc/generic/simple-card.c | 53 ++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 24 deletions(-) -- 1.8.5

1 2

[alsa-devel] [PATCH v3 1/2] mfd: arizona: Add support for INn_Modec register control
by Inha Song 29 Aug '14

29 Aug '14

Some boards need to set the INn_MODE[1:0] register to change the input signal patch. This wlf,inmode property is optional. If present, values must be specified less than or equal to the number of input singals. If values less than the number of input signals, elements that has not been specifed are set to 0 by default. Example: - wlf,inmode = <2 0 2>; /* IN1, IN3 use DMIC */ Signed-off-by: Inha Song <ideal.song(a)samsung.com> --- drivers/mfd/arizona-core.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c index 10a0cb9..81e6db8 100644 --- a/drivers/mfd/arizona-core.c +++ b/drivers/mfd/arizona-core.c @@ -534,7 +534,7 @@ EXPORT_SYMBOL_GPL(arizona_of_get_named_gpio); static int arizona_of_get_core_pdata(struct arizona *arizona) { struct arizona_pdata *pdata = &arizona->pdata; - int ret, i; + int ret, i, proplen; pdata->reset = arizona_of_get_named_gpio(arizona, "wlf,reset", true); @@ -560,6 +560,12 @@ static int arizona_of_get_core_pdata(struct arizona *arizona) ret); } + proplen = of_property_count_u32_elems(arizona->dev->of_node, + "wlf,inmode"); + if (proplen > 0 && proplen <= ARRAY_SIZE(arizona->pdata.inmode)) + of_property_read_u32_array(arizona->dev->of_node, "wlf,inmode", + arizona->pdata.inmode, proplen); + return 0; } -- 2.0.0.390.gcb682f8

3 5

[alsa-devel] [PATCH 0/2] Fix a regression for Dice driver at higher sampling rate
by Takashi Sakamoto 29 Aug '14

29 Aug '14

Commit 10550bea44a8 ("ALSA: dice/firewire-lib: Keep dualwire mode but obsolete CIP_HI_DUALWIRE") brought a regression to Dice driver. As a result, Dice driver cannot work correctly at higher sampling rate. This series of patches fixes the regression. Reported-by: Daniel Robbins <drobbins(a)funtoo.org> Fixes: 10550bea44a8 ("ALSA: dice/firewire-lib: Keep dualwire mode but obsolete CIP_HI_DUALWIRE") Takashi Sakamoto (2): ALSA: dice: fix wrong channel mappping at higher sampling rate ALSA: firewire-lib/dice: add arrangements of PCM pointer and interrupts for Dice quirk sound/firewire/amdtp.c | 11 ++++++++++- sound/firewire/amdtp.h | 1 + sound/firewire/dice.c | 29 ++++++++++++++++++++--------- 3 files changed, 31 insertions(+), 10 deletions(-) -- 1.9.1

2 3

Re: [alsa-devel] [PATCH 8/8] ASoC: add snd-soc-dummy DT support
by Kuninori Morimoto 29 Aug '14

29 Aug '14

Hi Lars Thank you for your comment > > sound { > > compatible = "simple-audio-card"; > > > > /* FrontEnd */ > > simple-audio-card,dai-link@0 { > > ... > > format = "left_j"; > > remote = <&endpoint>; > > > > cpu { > > sound-dai = <&rcar_sound 0>; > > }; > > codec { /* dummy */ }; > > }; > > > > /* BackEnd */ > > endpoint: simple-audio-card,dai-link@1 { > > ... > > format = "left_j"; > > > > cpu { /* dummy */ }; > > codec1: codec { > > sound-dai = <&ak4643>; > > }; > > }; > > }; > > When you try to come up with with a binding try to completely ignore that > something call DPCM exists. The binding is supposed to describe the hardware > and how the different hardware components are interconnected. So try to come > up with a binding that accurately describes the hardware connections. Once > that is done try to map the binding onto the existing software framework. > The last step may require some adjustments to the framework. Now, my system is working well with simple-card by this sound { compatible = "simple-audio-card"; ... cpu { sound-dai = <&rcar_sound 0>; }; codec { sound-dai = <&ak4643>; }; }; The reason why I'm tring to support DPCM on simple-card is "sampling rate convert". My rcar_sound can convert sampling rate, and I tried to add this feature as rcar_sound property. But, Mark rejected and requests me to use DPCM for it, since it can be common featrue. Current existing simple-card can't use it, and I'm tring. But, am I misunderstanding ? Best regards --- Kuninori Morimoto

3 5

[alsa-devel] [PATCH] ASoC: cs35l32: Simplify implementation of cs35l32_codec_set_sysclk
by Axel Lin 28 Aug '14

28 Aug '14

Use single snd_soc_update_bits() call to update the register bits. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/cs35l32.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/sound/soc/codecs/cs35l32.c b/sound/soc/codecs/cs35l32.c index 9c6b272..380c212 100644 --- a/sound/soc/codecs/cs35l32.c +++ b/sound/soc/codecs/cs35l32.c @@ -242,41 +242,27 @@ static struct snd_soc_dai_driver cs35l32_dai[] = { static int cs35l32_codec_set_sysclk(struct snd_soc_codec *codec, int clk_id, int source, unsigned int freq, int dir) { + unsigned int val; switch (freq) { case 6000000: - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_DIV2_MASK, 0); - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_RATIO_MASK, - CS35L32_MCLK_RATIO); + val = CS35L32_MCLK_RATIO; break; case 12000000: - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_DIV2_MASK, - CS35L32_MCLK_DIV2_MASK); - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_RATIO_MASK, - CS35L32_MCLK_RATIO); + val = CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO; break; case 6144000: - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_DIV2_MASK, 0); - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_RATIO_MASK, 0); + val = 0; break; case 12288000: - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_DIV2_MASK, - CS35L32_MCLK_DIV2_MASK); - snd_soc_update_bits(codec, CS35L32_CLK_CTL, - CS35L32_MCLK_RATIO_MASK, 0); + val = CS35L32_MCLK_DIV2_MASK; break; default: return -EINVAL; } - return 0; + return snd_soc_update_bits(codec, CS35L32_CLK_CTL, + CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO_MASK, val); } static struct snd_soc_codec_driver soc_codec_dev_cs35l32 = { -- 1.9.1

3 2

[alsa-devel] [PATCH 1/2] ASoC: cs35l32: Remove unneeded regulator_bulk_free call in cs35l32_i2c_remove
by Axel Lin 28 Aug '14

28 Aug '14

The regulator_bulk_free() call is not required because current code is using devm_regulator_bulk_get(). Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/cs35l32.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/sound/soc/codecs/cs35l32.c b/sound/soc/codecs/cs35l32.c index 380c212..718569f 100644 --- a/sound/soc/codecs/cs35l32.c +++ b/sound/soc/codecs/cs35l32.c @@ -548,8 +548,6 @@ static int cs35l32_i2c_remove(struct i2c_client *i2c_client) if (cs35l32->reset_gpio) gpiod_set_value_cansleep(cs35l32->reset_gpio, 0); - regulator_bulk_free(ARRAY_SIZE(cs35l32->supplies), cs35l32->supplies); - return 0; } -- 1.9.1

3 3

[alsa-devel] [PATCH] ASoC: Remove unused cache_only from struct snd_soc_codec
by Jarkko Nikula 28 Aug '14

28 Aug '14

There are no real users for cache_only in "struct snd_soc_codec" so remove it and needless debugfs node. Signed-off-by: Jarkko Nikula <jarkko.nikula(a)linux.intel.com> --- include/sound/soc.h | 1 - sound/soc/soc-core.c | 2 -- 2 files changed, 3 deletions(-) diff --git a/include/sound/soc.h b/include/sound/soc.h index e43fbb6f8f8c..29650de0df7b 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -792,7 +792,6 @@ struct snd_soc_codec { unsigned int ac97_registered:1; /* Codec has been AC97 registered */ unsigned int ac97_created:1; /* Codec has been created by SoC */ unsigned int cache_init:1; /* codec cache has been initialized */ - u32 cache_only; /* Suppress writes to hardware */ u32 cache_sync; /* Cache needs to be synced to hardware */ /* codec IO */ diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index 4974b4f9c952..b1327ef05860 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -311,8 +311,6 @@ static void soc_init_codec_debugfs(struct snd_soc_component *component) debugfs_create_bool("cache_sync", 0444, codec->component.debugfs_root, &codec->cache_sync); - debugfs_create_bool("cache_only", 0444, codec->component.debugfs_root, - &codec->cache_only); codec->debugfs_reg = debugfs_create_file("codec_reg", 0644, codec->component.debugfs_root, -- 2.1.0

2 1

[alsa-devel] [PATCH 1/3] ASoC: cs35l32: use true/false returns for bool functions
by Brian Austin 28 Aug '14

28 Aug '14

Return true or false instead of 1 and 0 Reported-by: Fengguang Wu <fengguang.wu(a)intel.com> Signed-off-by: Brian Austin <brian.austin(a)cirrus.com> --- sound/soc/codecs/cs35l32.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/codecs/cs35l32.c b/sound/soc/codecs/cs35l32.c index 9c6b272..ca897c4 100644 --- a/sound/soc/codecs/cs35l32.c +++ b/sound/soc/codecs/cs35l32.c @@ -121,9 +121,9 @@ static bool cs35l32_volatile_register(struct device *dev, unsigned int reg) case CS35L32_INT_STATUS_2: case CS35L32_INT_STATUS_3: case CS35L32_LED_STATUS: - return 1; + return true; default: - return 0; + return false; } } @@ -134,9 +134,9 @@ static bool cs35l32_precious_register(struct device *dev, unsigned int reg) case CS35L32_INT_STATUS_2: case CS35L32_INT_STATUS_3: case CS35L32_LED_STATUS: - return 1; + return true; default: - return 0; + return false; } } -- 1.7.9.5

2 3

[alsa-devel] [PATCH 1/3] Add CHIP_ID as a readable register.
by Paul Handrigan 28 Aug '14

28 Aug '14

Reported-by: Zoltán Szenczi <zoltan(a)raspberrypi.org> Signed-off-by: Paul Handrigan <Paul.Handrigan(a)cirrus.com> --- sound/soc/codecs/cs4265.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/codecs/cs4265.c b/sound/soc/codecs/cs4265.c index a20b30c..2dad15a 100644 --- a/sound/soc/codecs/cs4265.c +++ b/sound/soc/codecs/cs4265.c @@ -77,6 +77,7 @@ static bool cs4265_readable_register(struct device *dev, unsigned int reg) case CS4265_INT_MASK: case CS4265_STATUS_MODE_MSB: case CS4265_STATUS_MODE_LSB: + case CS4265_CHIP_ID: return true; default: return false; -- 1.9.1

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[alsa-devel] [PATCH] ASoC: Allow SND_SOC_WM8978 to be selected manually
by Geert Uytterhoeven 28 Aug '14

28 Aug '14

When using a DT-based multi-platform kernel, there's not always Kconfig logic that selects the right codec driver. Allow the user to manually select WM8978. This is needed for Armadillo 800 EVA using a generic r8a7740 multi-platform kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas(a)glider.be> --- sound/soc/codecs/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 7678122f8fe0..8ab154756934 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -731,7 +731,8 @@ config SND_SOC_WM8974 tristate config SND_SOC_WM8978 - tristate + tristate "Wolfson Microelectronics WM8978 codec" + depends on I2C config SND_SOC_WM8983 tristate -- 1.9.1

2 1

Re: [alsa-devel] [question about DPCM] dpcm_be_disconnect race condition
by Mark Brown 28 Aug '14

28 Aug '14

On Wed, Aug 27, 2014 at 04:15:00PM +0800, Qiao Zhou wrote: > Hi Liam, Mark > > I'm developing audio with DPCM on one phone platform, and met one kernel > panic issue related with dpcm_be_connect. Could you please help to suggest? Adding Liam. > Taking audio playback for example: > 1. User space writes all the data into audio buffer. When the blocking write > returns, it closes audio path(which updates dapm and triggers > soc_dpcm_runtime_update). > 2. When user space closes audio path, kernel audio driver(DMA) is still > transferring data from audio buffer to audio peripheral. So DMA interrupt > will come, and the interrupt handler runs on different cpu comparing to > which the task to close audio path runs on. > 3. Due to system schedule, below case may happen. > > cpu0 cpu1 > > soc_dapm_mixer_update_power -> | DMA interrupt -> > soc_dpcm_runtime_update -> | snd_pcm_period_elapsed -> > dpcm_be_disconnect(old) -> | snd_pcm_update_hw_ptr0 -> > __________________________ | xrun -> > | | | snd_pcm_stop -> > |list_del(&dpcm->list_be) | | dpcm_fe_dai_trigger -> > |list_del(&dpcm->list_fe) | | dpcm_be_dai_trigger -> > |kfree(dpcm); | | list_for_each_entry(dpcm.. > |_________________________| | > > On CPU1, list_for_each_entry(dpcm, &fe->dpcm[stream].be_clients, list_be) > will get dpcm and corresponding be, but there is no protection against the > dpcm_be_disconnect on cpu0. Related dpcm for the BE may be invalid/freed > when cpu1 tries to access it. > Should we require user space to make sure audio transfer ends before closing > audio path to avoid such issue? I'm not sure if I missed anything or used it > wrongly. Well, it should do that in general if it wants to make sure that the audio actually gets played but the kernel should protect against this. We should be holding a lock whenever we update the lists. > Thanks in advance! > -- > > Best Regards > Qiao >

2 2

[alsa-devel] [PATCHv3 0/4] ASoC: Convert to use regmap framework's endianness method.
by Xiubo Li 27 Aug '14

27 Aug '14

Changes in V3: - Delete 'ASoC: fsl-sai: rename big_endian_data to is_msb_first.' patch. Changes in V2: - Modified the regmap config to const type. - Added ASRC patch. - Followed Rutland's advice. Xiubo Li (4): ASoC: fsl-asrc: Convert to use regmap framework's endianness method. ASoC: fsl-esai: Convert to use regmap framework's endianness method. ASoC: fsl-spdif: Convert to use regmap framework's endianness method. ASoC: fsl-sai: Convert to use regmap framework's endianness method. Documentation/devicetree/bindings/sound/fsl-sai.txt | 7 +++---- sound/soc/fsl/fsl_asrc.c | 6 +----- sound/soc/fsl/fsl_esai.c | 5 +---- sound/soc/fsl/fsl_sai.c | 6 +----- sound/soc/fsl/fsl_sai.h | 1 - sound/soc/fsl/fsl_spdif.c | 5 +---- 6 files changed, 7 insertions(+), 23 deletions(-) -- 1.8.5

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Re: [alsa-devel] [PATCH 2/2] ASoC: rt5677: Add DMIC2 clock selection
by Mark Brown 27 Aug '14

27 Aug '14

On Wed, Aug 27, 2014 at 07:50:34PM +0800, bardliao(a)realtek.com wrote: > From: Bard Liao <bardliao(a)realtek.com> > > There are two pins can be used for rt5677's DMIC2 clock. This patch > add the select options for it. Applied, thanks.

1 0

Re: [alsa-devel] [PATCH 1/2] ASoC: rt5677: correct mismatch widget name
by Mark Brown 27 Aug '14

27 Aug '14

On Wed, Aug 27, 2014 at 07:50:33PM +0800, bardliao(a)realtek.com wrote: > From: Bard Liao <bardliao(a)realtek.com> > > We name MICBIAS1 in dapm widget, but micbias1 in route table. Applied, thanks.

1 0

[alsa-devel] [PATCH] ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.
by Xiubo Li 27 Aug '14

27 Aug '14

This property used for configuring whether the LSB or the MSB is transmitted first for the fifo data. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> Cc: Nicolin Chen <nicoleotsuka(a)gmail.com> --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 8 ++++---- sound/soc/fsl/fsl_sai.c | 6 +++--- sound/soc/fsl/fsl_sai.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 06a405e..4956b14 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -20,9 +20,9 @@ Required properties: See ../pinctrl/pinctrl-bindings.txt for details of the property values. - big-endian: Boolean property, required if all the FTM_PWM registers are big-endian rather than little-endian. -- big-endian-data: If this property is absent, the little endian mode will - be in use as default, or the big endian mode will be in use for all the - fifo data. +- lsb-first: Configures whether the LSB or the MSB is transmitted first for + the fifo data. If this property is absent, the MSB is transmitted first as + default, or the LSB is transmitted first. - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating that SAI will work in the synchronous mode (sync Tx with Rx) which means both the transimitter and receiver will send and receive data by following @@ -53,5 +53,5 @@ sai2: sai@40031000 { dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; big-endian; - big-endian-data; + lsb-first; }; diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index a6eb784..7eeb1dd 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -175,7 +175,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, bool tx = fsl_dir == FSL_FMT_TRANSMITTER; u32 val_cr2 = 0, val_cr4 = 0; - if (!sai->big_endian_data) + if (!sai->is_lsb_first) val_cr4 |= FSL_SAI_CR4_MF; /* DAI mode */ @@ -304,7 +304,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, val_cr5 |= FSL_SAI_CR5_WNW(word_width); val_cr5 |= FSL_SAI_CR5_W0W(word_width); - if (sai->big_endian_data) + if (sai->is_lsb_first) val_cr5 |= FSL_SAI_CR5_FBT(0); else val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); @@ -573,7 +573,7 @@ static int fsl_sai_probe(struct platform_device *pdev) if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) sai->sai_on_imx = true; - sai->big_endian_data = of_property_read_bool(np, "big-endian-data"); + sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 2cded44..3466720 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -132,7 +132,7 @@ struct fsl_sai { struct clk *bus_clk; struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; - bool big_endian_data; + bool is_lsb_first; bool is_dsp_mode; bool sai_on_imx; bool synchronous[2]; -- 1.8.5

5 6

[alsa-devel] [PATCH] ALSA: hda - Set up initial pins for Acer Aspire V5
by Takashi Iwai 27 Aug '14

27 Aug '14

Acer Aspire V5 doesn't set up the pins correctly at the cold boot while the pins are corrected after the warm reboot. This patch gives the proper pin configs statically in the driver as a workaround. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=81561 Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_realtek.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index d71270a3f73f..d446ac3137b3 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -4408,6 +4408,7 @@ enum { ALC292_FIXUP_TPT440_DOCK, ALC283_FIXUP_BXBT2807_MIC, ALC255_FIXUP_DELL_WMI_MIC_MUTE_LED, + ALC282_FIXUP_ASPIRE_V5_PINS, }; static const struct hda_fixup alc269_fixups[] = { @@ -4855,6 +4856,22 @@ static const struct hda_fixup alc269_fixups[] = { .chained_before = true, .chain_id = ALC255_FIXUP_DELL1_MIC_NO_PRESENCE }, + [ALC282_FIXUP_ASPIRE_V5_PINS] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x12, 0x90a60130 }, + { 0x14, 0x90170110 }, + { 0x17, 0x40000008 }, + { 0x18, 0x411111f0 }, + { 0x19, 0x411111f0 }, + { 0x1a, 0x411111f0 }, + { 0x1b, 0x411111f0 }, + { 0x1d, 0x40f89b2d }, + { 0x1e, 0x411111f0 }, + { 0x21, 0x0321101f }, + { }, + }, + }, }; @@ -4866,6 +4883,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1025, 0x0740, "Acer AO725", ALC271_FIXUP_HP_GATE_MIC_JACK), SND_PCI_QUIRK(0x1025, 0x0742, "Acer AO756", ALC271_FIXUP_HP_GATE_MIC_JACK), SND_PCI_QUIRK(0x1025, 0x0775, "Acer Aspire E1-572", ALC271_FIXUP_HP_GATE_MIC_JACK_E1_572), + SND_PCI_QUIRK(0x1025, 0x079b, "Acer Aspire V5-573G", ALC282_FIXUP_ASPIRE_V5_PINS), SND_PCI_QUIRK(0x1028, 0x0470, "Dell M101z", ALC269_FIXUP_DELL_M101Z), SND_PCI_QUIRK(0x1028, 0x05bd, "Dell", ALC269_FIXUP_DELL2_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x05be, "Dell", ALC269_FIXUP_DELL2_MIC_NO_PRESENCE), -- 2.1.0

1 0

[alsa-devel] [PATCH 1/1] ice1712: Replacing hex with #defines
by Konstantinos Tsimpoukas 27 Aug '14

27 Aug '14

Adds to te readability of the ice1712 driver. Signed-off-by: Konstantinos Tsimpoukas <kostaslinuxxx(a)gmail.com> --- sound/pci/ice1712/ice1712.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/ice1712/ice1712.c b/sound/pci/ice1712/ice1712.c index 87f7fc4..206ed2c 100644 --- a/sound/pci/ice1712/ice1712.c +++ b/sound/pci/ice1712/ice1712.c @@ -2528,7 +2528,7 @@ static int snd_ice1712_free(struct snd_ice1712 *ice) if (!ice->port) goto __hw_end; /* mask all interrupts */ - outb(0xc0, ICEMT(ice, IRQ)); + outb(ICE1712_MULTI_CAPTURE | ICE1712_MULTI_PLAYBACK, ICEMT(ice, IRQ)); outb(0xff, ICEREG(ice, IRQMASK)); /* --- */ __hw_end: -- 1.9.1

2 1

[alsa-devel] [PATCH 0/2] ASoC/regmap: rt5640: Fix resume
by Jarkko Nikula 27 Aug '14

27 Aug '14

Realtek RT5642 audio codec fails to resume because regmap/regcache tries to sync consecutive registers using block writes but RT5642 doesn't support autoincrementing I2C writes according to debugging and oscilloscope measurments. I'm not sure is there regression after 75a5f89f635c ("regmap: cache: Write consecutive registers in a single block write") or was RT564x resume ever working in mainline so I didn't mark stable yet. Both patches are independent from each other and can be applied into their own subsystems separately. Jarkko Nikula (2): regmap: cache: Fix regcache_sync_block for non-autoincrementing devices ASoC: rt5640: Do not allow regmap to use bulk read-write operations drivers/base/regmap/regcache.c | 14 +++++++++++++- sound/soc/codecs/rt5640.c | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) -- 2.1.0

2 4

[alsa-devel] [PATCH] sound: pci: ctxfi: fix broken user-visible string
by Sudip Mukherjee 26 Aug '14

26 Aug '14

fixed broken user visible strings Signed-off-by: Sudip Mukherjee <sudip(a)vectorindia.org> --- I am not exactly sure about the patch as some lines after fixing has crossed the limit of 80 characters. But the coding style says : "never break user-visible strings such as printk messages, because that breaks the ability to grep for them" sound/pci/ctxfi/ctatc.c | 18 +++++++----------- sound/pci/ctxfi/cthw20k1.c | 3 +-- sound/pci/ctxfi/cthw20k2.c | 11 +++++------ sound/pci/ctxfi/ctmixer.c | 6 ++---- sound/pci/ctxfi/ctresource.c | 20 ++++++++------------ sound/pci/ctxfi/ctvmem.c | 6 ++---- sound/pci/ctxfi/xfi.c | 6 ++---- 7 files changed, 27 insertions(+), 43 deletions(-) diff --git a/sound/pci/ctxfi/ctatc.c b/sound/pci/ctxfi/ctatc.c index ce9061a..d92a08c 100644 --- a/sound/pci/ctxfi/ctatc.c +++ b/sound/pci/ctxfi/ctatc.c @@ -185,7 +185,7 @@ static unsigned int convert_format(snd_pcm_format_t snd_format) case SNDRV_PCM_FORMAT_FLOAT_LE: return SRC_SF_F32; default: - pr_err("ctxfi: not recognized snd format is %d \n", + pr_err("ctxfi: not recognized snd format is %d\n", snd_format); return SRC_SF_S16; } @@ -1282,8 +1282,7 @@ static int atc_identify_card(struct ct_atc *atc, unsigned int ssid) p = snd_pci_quirk_lookup_id(vendor_id, device_id, list); if (p) { if (p->value < 0) { - pr_err("ctxfi: " - "Device %04x:%04x is black-listed\n", + pr_err("ctxfi: Device %04x:%04x is black-listed\n", vendor_id, device_id); return -ENOENT; } @@ -1315,8 +1314,7 @@ int ct_atc_create_alsa_devs(struct ct_atc *atc) err = alsa_dev_funcs[i].create(atc, i, alsa_dev_funcs[i].public_name); if (err) { - pr_err("ctxfi: " - "Creating alsa device %d failed!\n", i); + pr_err("ctxfi: Creating alsa device %d failed!\n", i); return err; } } @@ -1351,8 +1349,7 @@ static int atc_create_hw_devs(struct ct_atc *atc) err = rsc_mgr_funcs[i].create(atc->hw, &atc->rsc_mgrs[i]); if (err) { - pr_err("ctxfi: " - "Failed to create rsc_mgr %d!!!\n", i); + pr_err("ctxfi: Failed to create rsc_mgr %d!!!\n", i); return err; } } @@ -1399,8 +1396,8 @@ static int atc_get_resources(struct ct_atc *atc) err = daio_mgr->get_daio(daio_mgr, &da_desc, (struct daio **)&atc->daios[i]); if (err) { - pr_err("ctxfi: Failed to get DAIO " - "resource %d!!!\n", i); + pr_err("ctxfi: Failed to get DAIO resource %d!!!\n", + i); return err; } atc->n_daio++; @@ -1603,8 +1600,7 @@ static int atc_resume(struct ct_atc *atc) /* Do hardware resume. */ err = atc_hw_resume(atc); if (err < 0) { - pr_err("ctxfi: pci_enable_device failed, " - "disabling device\n"); + pr_err("ctxfi: pci_enable_device failed, disabling device\n"); snd_card_disconnect(atc->card); return err; } diff --git a/sound/pci/ctxfi/cthw20k1.c b/sound/pci/ctxfi/cthw20k1.c index 782641e..71d496f 100644 --- a/sound/pci/ctxfi/cthw20k1.c +++ b/sound/pci/ctxfi/cthw20k1.c @@ -1911,8 +1911,7 @@ static int hw_card_start(struct hw *hw) /* Set DMA transfer mask */ if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 || pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) { - pr_err("architecture does not support PCI " - "busmaster DMA with mask 0x%llx\n", + pr_err("architecture does not support PCI busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK); err = -ENXIO; goto error1; diff --git a/sound/pci/ctxfi/cthw20k2.c b/sound/pci/ctxfi/cthw20k2.c index 8a72fac..df2d8c5 100644 --- a/sound/pci/ctxfi/cthw20k2.c +++ b/sound/pci/ctxfi/cthw20k2.c @@ -1246,8 +1246,7 @@ static int hw_trn_init(struct hw *hw, const struct trn_conf *info) /* Set up device page table */ if ((~0UL) == info->vm_pgt_phys) { - pr_alert("ctxfi: " - "Wrong device page table page address!!!\n"); + pr_alert("ctxfi: Wrong device page table page address!!!\n"); return -1; } @@ -1890,8 +1889,8 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), MAKE_WM8775_DATA(0x0A)); } else { - pr_alert("ctxfi: Invalid master sampling " - "rate (msr %d)!!!\n", info->msr); + pr_alert("ctxfi: Invalid master sampling rate (msr %d)!!!\n", + info->msr); err = -EINVAL; goto error; } @@ -2034,8 +2033,8 @@ static int hw_card_start(struct hw *hw) /* Set DMA transfer mask */ if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 || pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) { - pr_err("ctxfi: architecture does not support PCI " - "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK); + pr_err("ctxfi: architecture does not support PCI busmaster DMA with mask 0x%llx\n", + CT_XFI_DMA_MASK); err = -ENXIO; goto error1; } diff --git a/sound/pci/ctxfi/ctmixer.c b/sound/pci/ctxfi/ctmixer.c index 8d986e4..017fa91 100644 --- a/sound/pci/ctxfi/ctmixer.c +++ b/sound/pci/ctxfi/ctmixer.c @@ -854,8 +854,7 @@ static int ct_mixer_get_resources(struct ct_mixer *mixer) for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) { err = sum_mgr->get_sum(sum_mgr, &sum_desc, &sum); if (err) { - pr_err("ctxfi:Failed to get sum resources for " - "front output!\n"); + pr_err("ctxfi:Failed to get sum resources for front output!\n"); break; } mixer->sums[i] = sum; @@ -869,8 +868,7 @@ static int ct_mixer_get_resources(struct ct_mixer *mixer) for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) { err = amixer_mgr->get_amixer(amixer_mgr, &am_desc, &amixer); if (err) { - pr_err("ctxfi:Failed to get amixer resources " - "for mixer obj!\n"); + pr_err("ctxfi:Failed to get amixer resources for mixer obj!\n"); break; } mixer->amixers[i] = amixer; diff --git a/sound/pci/ctxfi/ctresource.c b/sound/pci/ctxfi/ctresource.c index 11ac934..e49d2be 100644 --- a/sound/pci/ctxfi/ctresource.c +++ b/sound/pci/ctxfi/ctresource.c @@ -162,14 +162,12 @@ int rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, void *hw) case DAIO: break; default: - pr_err( - "ctxfi: Invalid resource type value %d!\n", type); + pr_err("ctxfi: Invalid resource type value %d!\n", type); return -EINVAL; } if (err) { - pr_err( - "ctxfi: Failed to get resource control block!\n"); + pr_err("ctxfi: Failed to get resource control block!\n"); return err; } @@ -192,8 +190,8 @@ int rsc_uninit(struct rsc *rsc) case DAIO: break; default: - pr_err("ctxfi: " - "Invalid resource type value %d!\n", rsc->type); + pr_err("ctxfi: Invalid resource type value %d!\n", + rsc->type); break; } @@ -235,15 +233,13 @@ int rsc_mgr_init(struct rsc_mgr *mgr, enum RSCTYP type, case SUM: break; default: - pr_err( - "ctxfi: Invalid resource type value %d!\n", type); + pr_err("ctxfi: Invalid resource type value %d!\n", type); err = -EINVAL; goto error; } if (err) { - pr_err( - "ctxfi: Failed to get manager control block!\n"); + pr_err("ctxfi: Failed to get manager control block!\n"); goto error; } @@ -286,8 +282,8 @@ int rsc_mgr_uninit(struct rsc_mgr *mgr) case SUM: break; default: - pr_err("ctxfi: " - "Invalid resource type value %d!\n", mgr->type); + pr_err("ctxfi: Invalid resource type value %d!\n", + mgr->type); break; } diff --git a/sound/pci/ctxfi/ctvmem.c b/sound/pci/ctxfi/ctvmem.c index 5ea015b..38163f5 100644 --- a/sound/pci/ctxfi/ctvmem.c +++ b/sound/pci/ctxfi/ctvmem.c @@ -36,8 +36,7 @@ get_vm_block(struct ct_vm *vm, unsigned int size) size = CT_PAGE_ALIGN(size); if (size > vm->size) { - pr_err("ctxfi: Fail! No sufficient device virtual " - "memory space available!\n"); + pr_err("ctxfi: Fail! No sufficient device virtual memory space available!\n"); return NULL; } @@ -132,8 +131,7 @@ ct_vm_map(struct ct_vm *vm, struct snd_pcm_substream *substream, int size) block = get_vm_block(vm, size); if (block == NULL) { - pr_err("ctxfi: No virtual memory block that is big " - "enough to allocate!\n"); + pr_err("ctxfi: No virtual memory block that is big enough to allocate!\n"); return NULL; } diff --git a/sound/pci/ctxfi/xfi.c b/sound/pci/ctxfi/xfi.c index af8c498..35e85ba 100644 --- a/sound/pci/ctxfi/xfi.c +++ b/sound/pci/ctxfi/xfi.c @@ -78,15 +78,13 @@ ct_card_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) if ((reference_rate != 48000) && (reference_rate != 44100)) { pr_err("ctxfi: Invalid reference_rate value %u!!!\n", reference_rate); - pr_err("ctxfi: The valid values for reference_rate " - "are 48000 and 44100, Value 48000 is assumed.\n"); + pr_err("ctxfi: The valid values for reference_rate are 48000 and 44100, Value 48000 is assumed.\n"); reference_rate = 48000; } if ((multiple != 1) && (multiple != 2) && (multiple != 4)) { pr_err("ctxfi: Invalid multiple value %u!!!\n", multiple); - pr_err("ctxfi: The valid values for multiple are " - "1, 2 and 4, Value 2 is assumed.\n"); + pr_err("ctxfi: The valid values for multiple are 1, 2 and 4, Value 2 is assumed.\n"); multiple = 2; } err = ct_atc_create(card, pci, reference_rate, multiple, -- 1.8.1.2

2 3

[alsa-devel] [PATCH 1/2] sound: pci: ctxfi: prink replacement
by Sudip Mukherjee 26 Aug '14

26 Aug '14

as pr_* macros are more preffered over printk, so printk replaced with corresponding pr_err and pr_alert this patch will generate a warning from checkpatch for an unnecessary space before new line and has not been fixed as this patch is only for printk replacement. Signed-off-by: Sudip Mukherjee <sudip(a)vectorindia.org> --- Initially started by copy-paste but as Takashi suggested it was done by a script. bash script is as follows : OLD="printk(KERN_ERR \?" OLD1="printk(KERN_ALERT \?" NEW="pr_err(" NEW1="pr_alert(" TFILE="/tmp/out.tmp.$$" for f in *.c do sed "s/$OLD/$NEW/g" "$f" > $TFILE && mv $TFILE "$f" sed "s/$OLD1/$NEW1/g" "$f" > $TFILE && mv $TFILE "$f" done sound/pci/ctxfi/ctamixer.c | 4 ++-- sound/pci/ctxfi/ctatc.c | 20 ++++++++++---------- sound/pci/ctxfi/ctdaio.c | 2 +- sound/pci/ctxfi/cthw20k1.c | 10 +++++----- sound/pci/ctxfi/cthw20k2.c | 16 ++++++++-------- sound/pci/ctxfi/ctmixer.c | 4 ++-- sound/pci/ctxfi/ctresource.c | 12 ++++++------ sound/pci/ctxfi/ctsrc.c | 4 ++-- sound/pci/ctxfi/ctvmem.c | 4 ++-- sound/pci/ctxfi/xfi.c | 8 ++++---- 10 files changed, 42 insertions(+), 42 deletions(-) diff --git a/sound/pci/ctxfi/ctamixer.c b/sound/pci/ctxfi/ctamixer.c index fee35cf..fed6e6a 100644 --- a/sound/pci/ctxfi/ctamixer.c +++ b/sound/pci/ctxfi/ctamixer.c @@ -258,7 +258,7 @@ static int get_amixer_rsc(struct amixer_mgr *mgr, } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet AMIXER resource request!\n"); + pr_err("ctxfi: Can't meet AMIXER resource request!\n"); goto error; } @@ -411,7 +411,7 @@ static int get_sum_rsc(struct sum_mgr *mgr, } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet SUM resource request!\n"); + pr_err("ctxfi: Can't meet SUM resource request!\n"); goto error; } diff --git a/sound/pci/ctxfi/ctatc.c b/sound/pci/ctxfi/ctatc.c index af632bd..ce9061a 100644 --- a/sound/pci/ctxfi/ctatc.c +++ b/sound/pci/ctxfi/ctatc.c @@ -185,7 +185,7 @@ static unsigned int convert_format(snd_pcm_format_t snd_format) case SNDRV_PCM_FORMAT_FLOAT_LE: return SRC_SF_F32; default: - printk(KERN_ERR "ctxfi: not recognized snd format is %d \n", + pr_err("ctxfi: not recognized snd format is %d \n", snd_format); return SRC_SF_S16; } @@ -1282,7 +1282,7 @@ static int atc_identify_card(struct ct_atc *atc, unsigned int ssid) p = snd_pci_quirk_lookup_id(vendor_id, device_id, list); if (p) { if (p->value < 0) { - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Device %04x:%04x is black-listed\n", vendor_id, device_id); return -ENOENT; @@ -1315,7 +1315,7 @@ int ct_atc_create_alsa_devs(struct ct_atc *atc) err = alsa_dev_funcs[i].create(atc, i, alsa_dev_funcs[i].public_name); if (err) { - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Creating alsa device %d failed!\n", i); return err; } @@ -1332,7 +1332,7 @@ static int atc_create_hw_devs(struct ct_atc *atc) err = create_hw_obj(atc->pci, atc->chip_type, atc->model, &hw); if (err) { - printk(KERN_ERR "Failed to create hw obj!!!\n"); + pr_err("Failed to create hw obj!!!\n"); return err; } atc->hw = hw; @@ -1351,7 +1351,7 @@ static int atc_create_hw_devs(struct ct_atc *atc) err = rsc_mgr_funcs[i].create(atc->hw, &atc->rsc_mgrs[i]); if (err) { - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Failed to create rsc_mgr %d!!!\n", i); return err; } @@ -1399,7 +1399,7 @@ static int atc_get_resources(struct ct_atc *atc) err = daio_mgr->get_daio(daio_mgr, &da_desc, (struct daio **)&atc->daios[i]); if (err) { - printk(KERN_ERR "ctxfi: Failed to get DAIO " + pr_err("ctxfi: Failed to get DAIO " "resource %d!!!\n", i); return err; } @@ -1603,7 +1603,7 @@ static int atc_resume(struct ct_atc *atc) /* Do hardware resume. */ err = atc_hw_resume(atc); if (err < 0) { - printk(KERN_ERR "ctxfi: pci_enable_device failed, " + pr_err("ctxfi: pci_enable_device failed, " "disabling device\n"); snd_card_disconnect(atc->card); return err; @@ -1701,7 +1701,7 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, /* Find card model */ err = atc_identify_card(atc, ssid); if (err < 0) { - printk(KERN_ERR "ctatc: Card not recognised\n"); + pr_err("ctatc: Card not recognised\n"); goto error1; } @@ -1717,7 +1717,7 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, err = ct_mixer_create(atc, (struct ct_mixer **)&atc->mixer); if (err) { - printk(KERN_ERR "ctxfi: Failed to create mixer obj!!!\n"); + pr_err("ctxfi: Failed to create mixer obj!!!\n"); goto error1; } @@ -1744,6 +1744,6 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, error1: ct_atc_destroy(atc); - printk(KERN_ERR "ctxfi: Something wrong!!!\n"); + pr_err("ctxfi: Something wrong!!!\n"); return err; } diff --git a/sound/pci/ctxfi/ctdaio.c b/sound/pci/ctxfi/ctdaio.c index 84f86bf..6f0654e 100644 --- a/sound/pci/ctxfi/ctdaio.c +++ b/sound/pci/ctxfi/ctdaio.c @@ -541,7 +541,7 @@ static int get_daio_rsc(struct daio_mgr *mgr, err = daio_mgr_get_rsc(&mgr->mgr, desc->type); spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "Can't meet DAIO resource request!\n"); + pr_err("Can't meet DAIO resource request!\n"); return err; } diff --git a/sound/pci/ctxfi/cthw20k1.c b/sound/pci/ctxfi/cthw20k1.c index 6ac40be..782641e 100644 --- a/sound/pci/ctxfi/cthw20k1.c +++ b/sound/pci/ctxfi/cthw20k1.c @@ -1268,7 +1268,7 @@ static int hw_trn_init(struct hw *hw, const struct trn_conf *info) /* Set up device page table */ if ((~0UL) == info->vm_pgt_phys) { - printk(KERN_ERR "Wrong device page table page address!\n"); + pr_err("Wrong device page table page address!\n"); return -1; } @@ -1327,7 +1327,7 @@ static int hw_pll_init(struct hw *hw, unsigned int rsr) mdelay(40); } if (i >= 3) { - printk(KERN_ALERT "PLL initialization failed!!!\n"); + pr_alert("PLL initialization failed!!!\n"); return -EBUSY; } @@ -1351,7 +1351,7 @@ static int hw_auto_init(struct hw *hw) break; } if (!get_field(gctl, GCTL_AID)) { - printk(KERN_ALERT "Card Auto-init failed!!!\n"); + pr_alert("Card Auto-init failed!!!\n"); return -EBUSY; } @@ -1911,7 +1911,7 @@ static int hw_card_start(struct hw *hw) /* Set DMA transfer mask */ if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 || pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) { - printk(KERN_ERR "architecture does not support PCI " + pr_err("architecture does not support PCI " "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK); err = -ENXIO; @@ -1942,7 +1942,7 @@ static int hw_card_start(struct hw *hw) err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED, KBUILD_MODNAME, hw); if (err < 0) { - printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq); + pr_err("XFi: Cannot get irq %d\n", pci->irq); goto error2; } hw->irq = pci->irq; diff --git a/sound/pci/ctxfi/cthw20k2.c b/sound/pci/ctxfi/cthw20k2.c index b143886..8a72fac 100644 --- a/sound/pci/ctxfi/cthw20k2.c +++ b/sound/pci/ctxfi/cthw20k2.c @@ -1187,7 +1187,7 @@ static int hw_daio_init(struct hw *hw, const struct daio_conf *info) hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121); hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); } else { - printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n"); + pr_alert("ctxfi: ERROR!!! Invalid sampling rate!!!\n"); return -EINVAL; } @@ -1246,7 +1246,7 @@ static int hw_trn_init(struct hw *hw, const struct trn_conf *info) /* Set up device page table */ if ((~0UL) == info->vm_pgt_phys) { - printk(KERN_ALERT "ctxfi: " + pr_alert("ctxfi: " "Wrong device page table page address!!!\n"); return -1; } @@ -1352,7 +1352,7 @@ static int hw_pll_init(struct hw *hw, unsigned int rsr) break; } if (i >= 1000) { - printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n"); + pr_alert("ctxfi: PLL initialization failed!!!\n"); return -EBUSY; } @@ -1376,7 +1376,7 @@ static int hw_auto_init(struct hw *hw) break; } if (!get_field(gctl, GCTL_AID)) { - printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n"); + pr_alert("ctxfi: Card Auto-init failed!!!\n"); return -EBUSY; } @@ -1847,7 +1847,7 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info) /* Initialize I2C */ err = hw20k2_i2c_init(hw, 0x1A, 1, 1); if (err < 0) { - printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n"); + pr_alert("ctxfi: Failure to acquire I2C!!!\n"); goto error; } @@ -1890,7 +1890,7 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), MAKE_WM8775_DATA(0x0A)); } else { - printk(KERN_ALERT "ctxfi: Invalid master sampling " + pr_alert("ctxfi: Invalid master sampling " "rate (msr %d)!!!\n", info->msr); err = -EINVAL; goto error; @@ -2034,7 +2034,7 @@ static int hw_card_start(struct hw *hw) /* Set DMA transfer mask */ if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 || pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) { - printk(KERN_ERR "ctxfi: architecture does not support PCI " + pr_err("ctxfi: architecture does not support PCI " "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK); err = -ENXIO; goto error1; @@ -2063,7 +2063,7 @@ static int hw_card_start(struct hw *hw) err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED, KBUILD_MODNAME, hw); if (err < 0) { - printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq); + pr_err("XFi: Cannot get irq %d\n", pci->irq); goto error2; } hw->irq = pci->irq; diff --git a/sound/pci/ctxfi/ctmixer.c b/sound/pci/ctxfi/ctmixer.c index 48fe0e3..8d986e4 100644 --- a/sound/pci/ctxfi/ctmixer.c +++ b/sound/pci/ctxfi/ctmixer.c @@ -854,7 +854,7 @@ static int ct_mixer_get_resources(struct ct_mixer *mixer) for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) { err = sum_mgr->get_sum(sum_mgr, &sum_desc, &sum); if (err) { - printk(KERN_ERR "ctxfi:Failed to get sum resources for " + pr_err("ctxfi:Failed to get sum resources for " "front output!\n"); break; } @@ -869,7 +869,7 @@ static int ct_mixer_get_resources(struct ct_mixer *mixer) for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) { err = amixer_mgr->get_amixer(amixer_mgr, &am_desc, &amixer); if (err) { - printk(KERN_ERR "ctxfi:Failed to get amixer resources " + pr_err("ctxfi:Failed to get amixer resources " "for mixer obj!\n"); break; } diff --git a/sound/pci/ctxfi/ctresource.c b/sound/pci/ctxfi/ctresource.c index 7dfaf67..11ac934 100644 --- a/sound/pci/ctxfi/ctresource.c +++ b/sound/pci/ctxfi/ctresource.c @@ -162,13 +162,13 @@ int rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, void *hw) case DAIO: break; default: - printk(KERN_ERR + pr_err( "ctxfi: Invalid resource type value %d!\n", type); return -EINVAL; } if (err) { - printk(KERN_ERR + pr_err( "ctxfi: Failed to get resource control block!\n"); return err; } @@ -192,7 +192,7 @@ int rsc_uninit(struct rsc *rsc) case DAIO: break; default: - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Invalid resource type value %d!\n", rsc->type); break; } @@ -235,14 +235,14 @@ int rsc_mgr_init(struct rsc_mgr *mgr, enum RSCTYP type, case SUM: break; default: - printk(KERN_ERR + pr_err( "ctxfi: Invalid resource type value %d!\n", type); err = -EINVAL; goto error; } if (err) { - printk(KERN_ERR + pr_err( "ctxfi: Failed to get manager control block!\n"); goto error; } @@ -286,7 +286,7 @@ int rsc_mgr_uninit(struct rsc_mgr *mgr) case SUM: break; default: - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Invalid resource type value %d!\n", mgr->type); break; } diff --git a/sound/pci/ctxfi/ctsrc.c b/sound/pci/ctxfi/ctsrc.c index 6e77e86..19df9b4 100644 --- a/sound/pci/ctxfi/ctsrc.c +++ b/sound/pci/ctxfi/ctsrc.c @@ -431,7 +431,7 @@ get_src_rsc(struct src_mgr *mgr, const struct src_desc *desc, struct src **rsrc) spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet SRC resource request!\n"); + pr_err("ctxfi: Can't meet SRC resource request!\n"); return err; } @@ -739,7 +739,7 @@ static int get_srcimp_rsc(struct srcimp_mgr *mgr, } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet SRCIMP resource request!\n"); + pr_err("ctxfi: Can't meet SRCIMP resource request!\n"); goto error1; } diff --git a/sound/pci/ctxfi/ctvmem.c b/sound/pci/ctxfi/ctvmem.c index 6109490..5ea015b 100644 --- a/sound/pci/ctxfi/ctvmem.c +++ b/sound/pci/ctxfi/ctvmem.c @@ -36,7 +36,7 @@ get_vm_block(struct ct_vm *vm, unsigned int size) size = CT_PAGE_ALIGN(size); if (size > vm->size) { - printk(KERN_ERR "ctxfi: Fail! No sufficient device virtual " + pr_err("ctxfi: Fail! No sufficient device virtual " "memory space available!\n"); return NULL; } @@ -132,7 +132,7 @@ ct_vm_map(struct ct_vm *vm, struct snd_pcm_substream *substream, int size) block = get_vm_block(vm, size); if (block == NULL) { - printk(KERN_ERR "ctxfi: No virtual memory block that is big " + pr_err("ctxfi: No virtual memory block that is big " "enough to allocate!\n"); return NULL; } diff --git a/sound/pci/ctxfi/xfi.c b/sound/pci/ctxfi/xfi.c index 8f8b566..af8c498 100644 --- a/sound/pci/ctxfi/xfi.c +++ b/sound/pci/ctxfi/xfi.c @@ -76,16 +76,16 @@ ct_card_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) if (err) return err; if ((reference_rate != 48000) && (reference_rate != 44100)) { - printk(KERN_ERR "ctxfi: Invalid reference_rate value %u!!!\n", + pr_err("ctxfi: Invalid reference_rate value %u!!!\n", reference_rate); - printk(KERN_ERR "ctxfi: The valid values for reference_rate " + pr_err("ctxfi: The valid values for reference_rate " "are 48000 and 44100, Value 48000 is assumed.\n"); reference_rate = 48000; } if ((multiple != 1) && (multiple != 2) && (multiple != 4)) { - printk(KERN_ERR "ctxfi: Invalid multiple value %u!!!\n", + pr_err("ctxfi: Invalid multiple value %u!!!\n", multiple); - printk(KERN_ERR "ctxfi: The valid values for multiple are " + pr_err("ctxfi: The valid values for multiple are " "1, 2 and 4, Value 2 is assumed.\n"); multiple = 2; } -- 1.8.1.2

1 1

[alsa-devel] [PATCH] sound: pci: ctxfi: prink replacement
by Sudip Mukherjee 26 Aug '14

26 Aug '14

printk replaced with corresponding pr_err and pr_alert Signed-off-by: Sudip Mukherjee <sudip(a)vectorindia.org> --- Initially started by copy-paste but as Takashi suggested it was done by a script. bash script is as follows : OLD="printk(KERN_ERR \?" OLD1="printk(KERN_ALERT \?" NEW="pr_err(" NEW1="pr_alert(" TFILE="/tmp/out.tmp.$$" for f in *.c do sed "s/$OLD/$NEW/g" "$f" > $TFILE && mv $TFILE "$f" sed "s/$OLD1/$NEW1/g" "$f" > $TFILE && mv $TFILE "$f" done this patch will generate a warning from checkpatch for an unnecessary space before new line and has not been fixed as this patch is only for printk replacement. sound/pci/ctxfi/ctamixer.c | 4 ++-- sound/pci/ctxfi/ctatc.c | 20 ++++++++++---------- sound/pci/ctxfi/ctdaio.c | 2 +- sound/pci/ctxfi/cthw20k1.c | 10 +++++----- sound/pci/ctxfi/cthw20k2.c | 16 ++++++++-------- sound/pci/ctxfi/ctmixer.c | 4 ++-- sound/pci/ctxfi/ctresource.c | 12 ++++++------ sound/pci/ctxfi/ctsrc.c | 4 ++-- sound/pci/ctxfi/ctvmem.c | 4 ++-- sound/pci/ctxfi/xfi.c | 8 ++++---- 10 files changed, 42 insertions(+), 42 deletions(-) diff --git a/sound/pci/ctxfi/ctamixer.c b/sound/pci/ctxfi/ctamixer.c index fee35cf..fed6e6a 100644 --- a/sound/pci/ctxfi/ctamixer.c +++ b/sound/pci/ctxfi/ctamixer.c @@ -258,7 +258,7 @@ static int get_amixer_rsc(struct amixer_mgr *mgr, } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet AMIXER resource request!\n"); + pr_err("ctxfi: Can't meet AMIXER resource request!\n"); goto error; } @@ -411,7 +411,7 @@ static int get_sum_rsc(struct sum_mgr *mgr, } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet SUM resource request!\n"); + pr_err("ctxfi: Can't meet SUM resource request!\n"); goto error; } diff --git a/sound/pci/ctxfi/ctatc.c b/sound/pci/ctxfi/ctatc.c index af632bd..ce9061a 100644 --- a/sound/pci/ctxfi/ctatc.c +++ b/sound/pci/ctxfi/ctatc.c @@ -185,7 +185,7 @@ static unsigned int convert_format(snd_pcm_format_t snd_format) case SNDRV_PCM_FORMAT_FLOAT_LE: return SRC_SF_F32; default: - printk(KERN_ERR "ctxfi: not recognized snd format is %d \n", + pr_err("ctxfi: not recognized snd format is %d \n", snd_format); return SRC_SF_S16; } @@ -1282,7 +1282,7 @@ static int atc_identify_card(struct ct_atc *atc, unsigned int ssid) p = snd_pci_quirk_lookup_id(vendor_id, device_id, list); if (p) { if (p->value < 0) { - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Device %04x:%04x is black-listed\n", vendor_id, device_id); return -ENOENT; @@ -1315,7 +1315,7 @@ int ct_atc_create_alsa_devs(struct ct_atc *atc) err = alsa_dev_funcs[i].create(atc, i, alsa_dev_funcs[i].public_name); if (err) { - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Creating alsa device %d failed!\n", i); return err; } @@ -1332,7 +1332,7 @@ static int atc_create_hw_devs(struct ct_atc *atc) err = create_hw_obj(atc->pci, atc->chip_type, atc->model, &hw); if (err) { - printk(KERN_ERR "Failed to create hw obj!!!\n"); + pr_err("Failed to create hw obj!!!\n"); return err; } atc->hw = hw; @@ -1351,7 +1351,7 @@ static int atc_create_hw_devs(struct ct_atc *atc) err = rsc_mgr_funcs[i].create(atc->hw, &atc->rsc_mgrs[i]); if (err) { - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Failed to create rsc_mgr %d!!!\n", i); return err; } @@ -1399,7 +1399,7 @@ static int atc_get_resources(struct ct_atc *atc) err = daio_mgr->get_daio(daio_mgr, &da_desc, (struct daio **)&atc->daios[i]); if (err) { - printk(KERN_ERR "ctxfi: Failed to get DAIO " + pr_err("ctxfi: Failed to get DAIO " "resource %d!!!\n", i); return err; } @@ -1603,7 +1603,7 @@ static int atc_resume(struct ct_atc *atc) /* Do hardware resume. */ err = atc_hw_resume(atc); if (err < 0) { - printk(KERN_ERR "ctxfi: pci_enable_device failed, " + pr_err("ctxfi: pci_enable_device failed, " "disabling device\n"); snd_card_disconnect(atc->card); return err; @@ -1701,7 +1701,7 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, /* Find card model */ err = atc_identify_card(atc, ssid); if (err < 0) { - printk(KERN_ERR "ctatc: Card not recognised\n"); + pr_err("ctatc: Card not recognised\n"); goto error1; } @@ -1717,7 +1717,7 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, err = ct_mixer_create(atc, (struct ct_mixer **)&atc->mixer); if (err) { - printk(KERN_ERR "ctxfi: Failed to create mixer obj!!!\n"); + pr_err("ctxfi: Failed to create mixer obj!!!\n"); goto error1; } @@ -1744,6 +1744,6 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, error1: ct_atc_destroy(atc); - printk(KERN_ERR "ctxfi: Something wrong!!!\n"); + pr_err("ctxfi: Something wrong!!!\n"); return err; } diff --git a/sound/pci/ctxfi/ctdaio.c b/sound/pci/ctxfi/ctdaio.c index 84f86bf..6f0654e 100644 --- a/sound/pci/ctxfi/ctdaio.c +++ b/sound/pci/ctxfi/ctdaio.c @@ -541,7 +541,7 @@ static int get_daio_rsc(struct daio_mgr *mgr, err = daio_mgr_get_rsc(&mgr->mgr, desc->type); spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "Can't meet DAIO resource request!\n"); + pr_err("Can't meet DAIO resource request!\n"); return err; } diff --git a/sound/pci/ctxfi/cthw20k1.c b/sound/pci/ctxfi/cthw20k1.c index 6ac40be..782641e 100644 --- a/sound/pci/ctxfi/cthw20k1.c +++ b/sound/pci/ctxfi/cthw20k1.c @@ -1268,7 +1268,7 @@ static int hw_trn_init(struct hw *hw, const struct trn_conf *info) /* Set up device page table */ if ((~0UL) == info->vm_pgt_phys) { - printk(KERN_ERR "Wrong device page table page address!\n"); + pr_err("Wrong device page table page address!\n"); return -1; } @@ -1327,7 +1327,7 @@ static int hw_pll_init(struct hw *hw, unsigned int rsr) mdelay(40); } if (i >= 3) { - printk(KERN_ALERT "PLL initialization failed!!!\n"); + pr_alert("PLL initialization failed!!!\n"); return -EBUSY; } @@ -1351,7 +1351,7 @@ static int hw_auto_init(struct hw *hw) break; } if (!get_field(gctl, GCTL_AID)) { - printk(KERN_ALERT "Card Auto-init failed!!!\n"); + pr_alert("Card Auto-init failed!!!\n"); return -EBUSY; } @@ -1911,7 +1911,7 @@ static int hw_card_start(struct hw *hw) /* Set DMA transfer mask */ if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 || pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) { - printk(KERN_ERR "architecture does not support PCI " + pr_err("architecture does not support PCI " "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK); err = -ENXIO; @@ -1942,7 +1942,7 @@ static int hw_card_start(struct hw *hw) err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED, KBUILD_MODNAME, hw); if (err < 0) { - printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq); + pr_err("XFi: Cannot get irq %d\n", pci->irq); goto error2; } hw->irq = pci->irq; diff --git a/sound/pci/ctxfi/cthw20k2.c b/sound/pci/ctxfi/cthw20k2.c index b143886..8a72fac 100644 --- a/sound/pci/ctxfi/cthw20k2.c +++ b/sound/pci/ctxfi/cthw20k2.c @@ -1187,7 +1187,7 @@ static int hw_daio_init(struct hw *hw, const struct daio_conf *info) hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121); hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); } else { - printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n"); + pr_alert("ctxfi: ERROR!!! Invalid sampling rate!!!\n"); return -EINVAL; } @@ -1246,7 +1246,7 @@ static int hw_trn_init(struct hw *hw, const struct trn_conf *info) /* Set up device page table */ if ((~0UL) == info->vm_pgt_phys) { - printk(KERN_ALERT "ctxfi: " + pr_alert("ctxfi: " "Wrong device page table page address!!!\n"); return -1; } @@ -1352,7 +1352,7 @@ static int hw_pll_init(struct hw *hw, unsigned int rsr) break; } if (i >= 1000) { - printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n"); + pr_alert("ctxfi: PLL initialization failed!!!\n"); return -EBUSY; } @@ -1376,7 +1376,7 @@ static int hw_auto_init(struct hw *hw) break; } if (!get_field(gctl, GCTL_AID)) { - printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n"); + pr_alert("ctxfi: Card Auto-init failed!!!\n"); return -EBUSY; } @@ -1847,7 +1847,7 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info) /* Initialize I2C */ err = hw20k2_i2c_init(hw, 0x1A, 1, 1); if (err < 0) { - printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n"); + pr_alert("ctxfi: Failure to acquire I2C!!!\n"); goto error; } @@ -1890,7 +1890,7 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), MAKE_WM8775_DATA(0x0A)); } else { - printk(KERN_ALERT "ctxfi: Invalid master sampling " + pr_alert("ctxfi: Invalid master sampling " "rate (msr %d)!!!\n", info->msr); err = -EINVAL; goto error; @@ -2034,7 +2034,7 @@ static int hw_card_start(struct hw *hw) /* Set DMA transfer mask */ if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 || pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) { - printk(KERN_ERR "ctxfi: architecture does not support PCI " + pr_err("ctxfi: architecture does not support PCI " "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK); err = -ENXIO; goto error1; @@ -2063,7 +2063,7 @@ static int hw_card_start(struct hw *hw) err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED, KBUILD_MODNAME, hw); if (err < 0) { - printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq); + pr_err("XFi: Cannot get irq %d\n", pci->irq); goto error2; } hw->irq = pci->irq; diff --git a/sound/pci/ctxfi/ctmixer.c b/sound/pci/ctxfi/ctmixer.c index 48fe0e3..8d986e4 100644 --- a/sound/pci/ctxfi/ctmixer.c +++ b/sound/pci/ctxfi/ctmixer.c @@ -854,7 +854,7 @@ static int ct_mixer_get_resources(struct ct_mixer *mixer) for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) { err = sum_mgr->get_sum(sum_mgr, &sum_desc, &sum); if (err) { - printk(KERN_ERR "ctxfi:Failed to get sum resources for " + pr_err("ctxfi:Failed to get sum resources for " "front output!\n"); break; } @@ -869,7 +869,7 @@ static int ct_mixer_get_resources(struct ct_mixer *mixer) for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) { err = amixer_mgr->get_amixer(amixer_mgr, &am_desc, &amixer); if (err) { - printk(KERN_ERR "ctxfi:Failed to get amixer resources " + pr_err("ctxfi:Failed to get amixer resources " "for mixer obj!\n"); break; } diff --git a/sound/pci/ctxfi/ctresource.c b/sound/pci/ctxfi/ctresource.c index 7dfaf67..11ac934 100644 --- a/sound/pci/ctxfi/ctresource.c +++ b/sound/pci/ctxfi/ctresource.c @@ -162,13 +162,13 @@ int rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, void *hw) case DAIO: break; default: - printk(KERN_ERR + pr_err( "ctxfi: Invalid resource type value %d!\n", type); return -EINVAL; } if (err) { - printk(KERN_ERR + pr_err( "ctxfi: Failed to get resource control block!\n"); return err; } @@ -192,7 +192,7 @@ int rsc_uninit(struct rsc *rsc) case DAIO: break; default: - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Invalid resource type value %d!\n", rsc->type); break; } @@ -235,14 +235,14 @@ int rsc_mgr_init(struct rsc_mgr *mgr, enum RSCTYP type, case SUM: break; default: - printk(KERN_ERR + pr_err( "ctxfi: Invalid resource type value %d!\n", type); err = -EINVAL; goto error; } if (err) { - printk(KERN_ERR + pr_err( "ctxfi: Failed to get manager control block!\n"); goto error; } @@ -286,7 +286,7 @@ int rsc_mgr_uninit(struct rsc_mgr *mgr) case SUM: break; default: - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Invalid resource type value %d!\n", mgr->type); break; } diff --git a/sound/pci/ctxfi/ctsrc.c b/sound/pci/ctxfi/ctsrc.c index 6e77e86..19df9b4 100644 --- a/sound/pci/ctxfi/ctsrc.c +++ b/sound/pci/ctxfi/ctsrc.c @@ -431,7 +431,7 @@ get_src_rsc(struct src_mgr *mgr, const struct src_desc *desc, struct src **rsrc) spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet SRC resource request!\n"); + pr_err("ctxfi: Can't meet SRC resource request!\n"); return err; } @@ -739,7 +739,7 @@ static int get_srcimp_rsc(struct srcimp_mgr *mgr, } spin_unlock_irqrestore(&mgr->mgr_lock, flags); if (err) { - printk(KERN_ERR "ctxfi: Can't meet SRCIMP resource request!\n"); + pr_err("ctxfi: Can't meet SRCIMP resource request!\n"); goto error1; } diff --git a/sound/pci/ctxfi/ctvmem.c b/sound/pci/ctxfi/ctvmem.c index 6109490..5ea015b 100644 --- a/sound/pci/ctxfi/ctvmem.c +++ b/sound/pci/ctxfi/ctvmem.c @@ -36,7 +36,7 @@ get_vm_block(struct ct_vm *vm, unsigned int size) size = CT_PAGE_ALIGN(size); if (size > vm->size) { - printk(KERN_ERR "ctxfi: Fail! No sufficient device virtual " + pr_err("ctxfi: Fail! No sufficient device virtual " "memory space available!\n"); return NULL; } @@ -132,7 +132,7 @@ ct_vm_map(struct ct_vm *vm, struct snd_pcm_substream *substream, int size) block = get_vm_block(vm, size); if (block == NULL) { - printk(KERN_ERR "ctxfi: No virtual memory block that is big " + pr_err("ctxfi: No virtual memory block that is big " "enough to allocate!\n"); return NULL; } diff --git a/sound/pci/ctxfi/xfi.c b/sound/pci/ctxfi/xfi.c index 8f8b566..af8c498 100644 --- a/sound/pci/ctxfi/xfi.c +++ b/sound/pci/ctxfi/xfi.c @@ -76,16 +76,16 @@ ct_card_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) if (err) return err; if ((reference_rate != 48000) && (reference_rate != 44100)) { - printk(KERN_ERR "ctxfi: Invalid reference_rate value %u!!!\n", + pr_err("ctxfi: Invalid reference_rate value %u!!!\n", reference_rate); - printk(KERN_ERR "ctxfi: The valid values for reference_rate " + pr_err("ctxfi: The valid values for reference_rate " "are 48000 and 44100, Value 48000 is assumed.\n"); reference_rate = 48000; } if ((multiple != 1) && (multiple != 2) && (multiple != 4)) { - printk(KERN_ERR "ctxfi: Invalid multiple value %u!!!\n", + pr_err("ctxfi: Invalid multiple value %u!!!\n", multiple); - printk(KERN_ERR "ctxfi: The valid values for multiple are " + pr_err("ctxfi: The valid values for multiple are " "1, 2 and 4, Value 2 is assumed.\n"); multiple = 2; } -- 1.8.1.2

2 2

[alsa-devel] [PATCH] sound: pci: ctxfi: ctatc.c: printk replacement
by Sudip Mukherjee 26 Aug '14

26 Aug '14

printk replaced ith corresponding pr_err fixed three broken user-visible strings fixed a checkpatch warning of space before new line Signed-off-by: Sudip Mukherjee <sudip(a)vectorindia.org> --- sound/pci/ctxfi/ctatc.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/sound/pci/ctxfi/ctatc.c b/sound/pci/ctxfi/ctatc.c index af632bd..41597a8 100644 --- a/sound/pci/ctxfi/ctatc.c +++ b/sound/pci/ctxfi/ctatc.c @@ -185,7 +185,7 @@ static unsigned int convert_format(snd_pcm_format_t snd_format) case SNDRV_PCM_FORMAT_FLOAT_LE: return SRC_SF_F32; default: - printk(KERN_ERR "ctxfi: not recognized snd format is %d \n", + pr_err("ctxfi: not recognized snd format is %d\n", snd_format); return SRC_SF_S16; } @@ -1282,7 +1282,7 @@ static int atc_identify_card(struct ct_atc *atc, unsigned int ssid) p = snd_pci_quirk_lookup_id(vendor_id, device_id, list); if (p) { if (p->value < 0) { - printk(KERN_ERR "ctxfi: " + pr_err("ctxfi: " "Device %04x:%04x is black-listed\n", vendor_id, device_id); return -ENOENT; @@ -1315,8 +1315,7 @@ int ct_atc_create_alsa_devs(struct ct_atc *atc) err = alsa_dev_funcs[i].create(atc, i, alsa_dev_funcs[i].public_name); if (err) { - printk(KERN_ERR "ctxfi: " - "Creating alsa device %d failed!\n", i); + pr_err("ctxfi: Creating alsa device %d failed!\n", i); return err; } } @@ -1332,7 +1331,7 @@ static int atc_create_hw_devs(struct ct_atc *atc) err = create_hw_obj(atc->pci, atc->chip_type, atc->model, &hw); if (err) { - printk(KERN_ERR "Failed to create hw obj!!!\n"); + pr_err("Failed to create hw obj!!!\n"); return err; } atc->hw = hw; @@ -1351,8 +1350,7 @@ static int atc_create_hw_devs(struct ct_atc *atc) err = rsc_mgr_funcs[i].create(atc->hw, &atc->rsc_mgrs[i]); if (err) { - printk(KERN_ERR "ctxfi: " - "Failed to create rsc_mgr %d!!!\n", i); + pr_err("ctxfi: Failed to create rsc_mgr %d!!!\n", i); return err; } } @@ -1399,7 +1397,7 @@ static int atc_get_resources(struct ct_atc *atc) err = daio_mgr->get_daio(daio_mgr, &da_desc, (struct daio **)&atc->daios[i]); if (err) { - printk(KERN_ERR "ctxfi: Failed to get DAIO " + pr_err("ctxfi: Failed to get DAIO " "resource %d!!!\n", i); return err; } @@ -1603,8 +1601,7 @@ static int atc_resume(struct ct_atc *atc) /* Do hardware resume. */ err = atc_hw_resume(atc); if (err < 0) { - printk(KERN_ERR "ctxfi: pci_enable_device failed, " - "disabling device\n"); + pr_err("ctxfi: pci_enable_device failed, disabling device\n"); snd_card_disconnect(atc->card); return err; } @@ -1701,7 +1698,7 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, /* Find card model */ err = atc_identify_card(atc, ssid); if (err < 0) { - printk(KERN_ERR "ctatc: Card not recognised\n"); + pr_err("ctatc: Card not recognised\n"); goto error1; } @@ -1717,7 +1714,7 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, err = ct_mixer_create(atc, (struct ct_mixer **)&atc->mixer); if (err) { - printk(KERN_ERR "ctxfi: Failed to create mixer obj!!!\n"); + pr_err("ctxfi: Failed to create mixer obj!!!\n"); goto error1; } @@ -1744,6 +1741,6 @@ int ct_atc_create(struct snd_card *card, struct pci_dev *pci, error1: ct_atc_destroy(atc); - printk(KERN_ERR "ctxfi: Something wrong!!!\n"); + pr_err("ctxfi: Something wrong!!!\n"); return err; } -- 1.8.1.2

2 3

[alsa-devel] [PATCH] ASoC: Restore idle_bias_off initialization
by Lars-Peter Clausen 26 Aug '14

26 Aug '14

This was accidentally lost in commit f1d45cc3ae96 ("ASoC: Consolidate platform and CODEC probe/remove"). Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> --- sound/soc/soc-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index e982cb0..4974b4f 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -4010,6 +4010,7 @@ static int snd_soc_component_initialize(struct snd_soc_component *component, dapm->dev = dev; dapm->component = component; dapm->bias_level = SND_SOC_BIAS_OFF; + dapm->idle_bias_off = true; if (driver->seq_notifier) dapm->seq_notifier = snd_soc_component_seq_notifier; if (driver->stream_event) @@ -4399,6 +4400,7 @@ int snd_soc_register_codec(struct device *dev, codec->component.read = snd_soc_codec_drv_read; codec->component.ignore_pmdown_time = codec_drv->ignore_pmdown_time; codec->dapm.codec = codec; + codec->dapm.idle_bias_off = codec_drv->idle_bias_off; if (codec_drv->seq_notifier) codec->dapm.seq_notifier = codec_drv->seq_notifier; if (codec_drv->set_bias_level) -- 1.8.0

2 1

Re: [alsa-devel] ASoC: bug report for ssm2602
by Lars-Peter Clausen 26 Aug '14

26 Aug '14

On 08/22/2014 11:21 AM, Scott Jiang wrote: > Hi Mark and Lars, > > commit 9d863b88ec371491e926e0828dbe3d36ead0f6f9 > Author: Lars-Peter Clausen <lars(a)metafoo.de> > Date: Sat Aug 31 18:15:23 2013 +0200 > > ASoC: ssm2602: Fix cache sync > > The ssm2602 uses regmap for caching not soc-cache, so we need to use > regcache_sync() instead of snd_soc_cache_sync(). > > According my test, regcache_sync() can't recover register values when > resume. While snd_soc_cache_sync() works fine. I used regmap_read() to > read registers in regmap layer and found it's the same as suspend. But > regcache_sync() didn't sync these registers correctly to hardware. > That does not make too much sense. snd_soc_cache_sync() is definitely a no-op when using regmap. Which kernel version are you on? Are there any additional changes to this driver in your tree? - Lars

3 6

Re: [alsa-devel] [PATCH] ALSA: virtuoso: add Xonar Essence STX II support
by Andreas Allacher 26 Aug '14

26 Aug '14

Is there any reason why the daughterboard does not work yet or hasn't it only been tested yet? Any idea how much work it would be to implement daughterboard support? Regards, Andreas At Mon, 04 Aug 2014 15:17:55 +0200, Andreas Allacher wrote: > At Mon, 04 Aug 2014 15:17:55 +0200, > Clemens Ladisch wrote: > >/ > />/ Just add the PCI ID for the STX II. It appears to work the same as the > />/ STX, except for the addition of the not-yet-supported daughterboard. > />/ > />/ Tested-by: Mario <fugazzi99 at gmail.com <http://mailman.alsa-project.org/mailman/listinfo/alsa-devel>> > />/ Tested-by: corubba <corubba at gmx.de <http://mailman.alsa-project.org/mailman/listinfo/alsa-devel>> > />/ Cc: <stable at vger.kernel.org <http://mailman.alsa-project.org/mailman/listinfo/alsa-devel>> > />/ Signed-off-by: Clemens Ladisch <clemens at ladisch.de <http://mailman.alsa-project.org/mailman/listinfo/alsa-devel>> > / > Applied, thanks. > > > Takashi > > >/ --- > />/ Documentation/sound/alsa/ALSA-Configuration.txt | 4 ++-- > />/ sound/pci/Kconfig | 4 ++-- > />/ sound/pci/oxygen/virtuoso.c | 1 + > />/ sound/pci/oxygen/xonar_pcm179x.c | 12 ++++++++++-- > />/ 4 files changed, 15 insertions(+), 6 deletions(-) > />/ > />/ diff --git a/Documentation/sound/alsa/ALSA-Configuration.txt b/Documentation/sound/alsa/ALSA-Configuration.txt > />/ index 7ccf933..48148d6 100644 > />/ --- a/Documentation/sound/alsa/ALSA-Configuration.txt > />/ +++ b/Documentation/sound/alsa/ALSA-Configuration.txt > />/ @@ -2026,8 +2026,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed. > />/ ------------------- > />/ > />/ Module for sound cards based on the Asus AV66/AV100/AV200 chips, > />/ - i.e., Xonar D1, DX, D2, D2X, DS, Essence ST (Deluxe), Essence STX, > />/ - HDAV1.3 (Deluxe), and HDAV1.3 Slim. > />/ + i.e., Xonar D1, DX, D2, D2X, DS, DSX, Essence ST (Deluxe), > />/ + Essence STX (II), HDAV1.3 (Deluxe), and HDAV1.3 Slim. > />/ > />/ This module supports autoprobe and multiple cards. > />/ > />/ diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig > />/ index 3a3a3a7..50dd008 100644 > />/ --- a/sound/pci/Kconfig > />/ +++ b/sound/pci/Kconfig > />/ @@ -858,8 +858,8 @@ config SND_VIRTUOSO > />/ select SND_JACK if INPUT=y || INPUT=SND > />/ help > />/ Say Y here to include support for sound cards based on the > />/ - Asus AV66/AV100/AV200 chips, i.e., Xonar D1, DX, D2, D2X, DS, > />/ - Essence ST (Deluxe), and Essence STX. > />/ + Asus AV66/AV100/AV200 chips, i.e., Xonar D1, DX, D2, D2X, DS, DSX, > />/ + Essence ST (Deluxe), and Essence STX (II). > />/ Support for the HDAV1.3 (Deluxe) and HDAV1.3 Slim is experimental; > />/ for the Xense, missing. > />/ > />/ diff --git a/sound/pci/oxygen/virtuoso.c b/sound/pci/oxygen/virtuoso.c > />/ index 64b9fda..dbbbacf 100644 > />/ --- a/sound/pci/oxygen/virtuoso.c > />/ +++ b/sound/pci/oxygen/virtuoso.c > />/ @@ -53,6 +53,7 @@ static DEFINE_PCI_DEVICE_TABLE(xonar_ids) = { > />/ { OXYGEN_PCI_SUBID(0x1043, 0x835e) }, > />/ { OXYGEN_PCI_SUBID(0x1043, 0x838e) }, > />/ { OXYGEN_PCI_SUBID(0x1043, 0x8522) }, > />/ + { OXYGEN_PCI_SUBID(0x1043, 0x85f4) }, > />/ { OXYGEN_PCI_SUBID_BROKEN_EEPROM }, > />/ { } > />/ }; > />/ diff --git a/sound/pci/oxygen/xonar_pcm179x.c b/sound/pci/oxygen/xonar_pcm179x.c > />/ index c8c7f2c..e026059 100644 > />/ --- a/sound/pci/oxygen/xonar_pcm179x.c > />/ +++ b/sound/pci/oxygen/xonar_pcm179x.c > />/ @@ -100,8 +100,8 @@ > />/ */ > />/ > />/ /* > />/ - * Xonar Essence ST (Deluxe)/STX > />/ - * ----------------------------- > />/ + * Xonar Essence ST (Deluxe)/STX (II) > />/ + * ---------------------------------- > />/ * > />/ * CMI8788: > />/ * > />/ @@ -1138,6 +1138,14 @@ int get_xonar_pcm179x_model(struct oxygen *chip, > />/ chip->model.resume = xonar_stx_resume; > />/ chip->model.set_dac_params = set_pcm1796_params; > />/ break; > />/ + case 0x85f4: > />/ + chip->model = model_xonar_st; > />/ + /* TODO: daughterboard support */ > />/ + chip->model.shortname = "Xonar STX II"; > />/ + chip->model.init = xonar_stx_init; > />/ + chip->model.resume = xonar_stx_resume; > />/ + chip->model.set_dac_params = set_pcm1796_params; > />/ + break; > />/ default: > />/ return -EINVAL; > />/ } > />/ /

2 1

Re: [alsa-devel] Audio mini conference 2014?
by Koul, Vinod 26 Aug '14

26 Aug '14

On 26 Aug 2014 07:17, "Austin, Brian" <Brian.Austin(a)cirrus.com> wrote: > > > On Aug 20, 2014, at 12:01 PM, Mark Brown <broonie(a)kernel.org> wrote: > > > On Wed, Aug 20, 2014 at 02:11:07PM +0530, Vinod Koul wrote: > >> On Wed, Aug 20, 2014 at 09:33:05AM +0200, Takashi Iwai wrote: > > > >>> I thought UCM was targeted to this, but not widely used as expected? > > > >> Chrome uses t but not Android due to licensing issues. What happend to > >> tinyucm? > > > > The latest Google reference designs use something which is essentially > > tinyucm - the configuration is mostly stored in an XML configuration > > file which is read at runtime. It's not consistent with what anyone > > else uses. > > Those must be the qcom designs. They use a “tinyucm" that is xml based. > > I would like to see if we could get a consistent UCM for Android/Chrome/etc. > Has this made it into the topics list? I thought it was in the topic list sent by takashi. this is certainly something I plan to discuss :) -- ~Vinod

1 0

Re: [alsa-devel] ALSA snd-fireworks Echo AudioFire 2
by Takashi Sakamoto 26 Aug '14

26 Aug '14

Hi Harry, (C.C.ed to alsa-devel and Clemens) On Aug 25 2014 09:06, Harry van Haaren wrote:> Hi Takashi, > I can report the AudioFire2 registers correctly, see output: > [...] > On testing the device with alsa_delay[1], using 256 frames/buffer, 2 buffers. > A sine wave should be audible, however a clicking sound occurs about 3 > times per second. > > Dmesg prints a list of snd-fireworks logs: > [54749.309250] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54749.467216] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54749.627157] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54749.785195] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54749.944205] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54750.102188] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54750.262195] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.420170] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.580185] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.738154] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.898172] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.056187] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.216153] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54751.374195] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.534182] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.692164] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > > > The the device works using FFADO, and the mixer settings are all set > to pass trough any audio. > > Is the above information enough to help debug? Is there anything I can > do to assit you in finding this playback bug? Thanks for your report. The dmesg means that your AudioFire2 transmits packets with disorder. (I note that Fireworks driver start duplex streams for timestamp synchronization even if you use playback only.) I know that some Fireworks devices with a certain firmware (not exactly identified) sometimes perform the same behaviour. Could I ask you to confirm to see these logs always when you playback, or sometimes? # Currently I'm working for moving to my new flat. # So during a few weeks, I may not reply as you expected, sorry. Regards Takashi Sakamoto o-takashi(a)sakamocchi.jp On Aug 25 2014 09:06, Harry van Haaren wrote: > Hi Takashi, > > Thanks for your work on the Echo ALSA support! > > I can report the AudioFire2 registers correctly, see output: > > /cardX/firewire/clock: > Clock Source: 0 > Sampling Rate: 44100 > > /cardX/firewire/meters: > Physical Meters: > 6 Outputs: > Analog [0]: 22784 > Analog [1]: 19200 > Headphones [0]: 0 > Headphones [1]: 0 > S/PDIF [0]: 0 > S/PDIF [1]: 0 > 4 Inputs: > Analog [0]: 22784 > Analog [1]: 19200 > S/PDIF [0]: 0 > S/PDIF [1]: 0 > > > /cardX/firewire/firmware: > > guid_hi: 0x14860E > guid_lo: 0xD7FF1CAB > type: 0xAF2 > version: 0x0 > vendor_name: Echo Digital Audio > model_name: AudioFire2 > dsp_version: 0x0 > arm_version: 0x5070300 > fpga_version: 0x3000200 > flags: 0xA1 > max_sample_rate: 0x17700 > min_sample_rate: 0x7D00 > supported_clock: 0x9 > phys out: 0x6 > phys in: 0x4 > phys in grps: 0x2 > phys in grp[0]: type 0x0, count 0x2 > phys in grp[1]: type 0x5, count 0x2 > phys out grps: 0x3 > phys out grps[0]: type 0x0, count 0x2 > phys out grps[1]: type 0x5, count 0x2 > phys out grps[2]: type 0x1, count 0x2 > amdtp rx pcm channels 1x: 0x6 > amdtp tx pcm channels 1x: 0x4 > amdtp rx pcm channels 2x: 0x6 > amdtp tx pcm channels 2x: 0x4 > amdtp rx pcm channels 4x: 0x6 > amdtp tx pcm channels 4x: 0x4 > midi out ports: 0x1 > midi in ports: 0x1 > mixer playback channels: 0x6 > mixer capture channels: 0x4 > > > On testing the device with alsa_delay[1], using 256 frames/buffer, 2 buffers. > A sine wave should be audible, however a clicking sound occurs about 3 > times per second. > > Dmesg prints a list of snd-fireworks logs: > [54749.309250] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54749.467216] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54749.627157] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54749.785195] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54749.944205] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54750.102188] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54750.262195] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.420170] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.580185] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.738154] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54750.898172] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.056187] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.216153] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 12 > [54751.374195] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.534182] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > [54751.692164] snd-fireworks fw1.0: Detect discontinuity of CIP: 00 0A > > > The the device works using FFADO, and the mixer settings are all set > to pass trough any audio. > > Is the above information enough to help debug? Is there anything I can > do to assit you in finding this playback bug? > Greetings from Ireland, -Harry > > [1] http://kokkinizita.linuxaudio.org/linuxaudio/downloads/zita-alsa-pcmi-0.2.0…

3 4

[alsa-devel] [PATCH] sound: pci: ctxfi: ctpcm.c: printk replacement
by Sudip Mukherjee 25 Aug '14

25 Aug '14

replaced printk with corresponding pr_err Signed-off-by: Sudip Mukherjee <sudip(a)vectorindia.org> --- sound/pci/ctxfi/ctpcm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/pci/ctxfi/ctpcm.c b/sound/pci/ctxfi/ctpcm.c index e8a4feb..6826c2c 100644 --- a/sound/pci/ctxfi/ctpcm.c +++ b/sound/pci/ctxfi/ctpcm.c @@ -217,7 +217,7 @@ static int ct_pcm_playback_prepare(struct snd_pcm_substream *substream) err = atc->pcm_playback_prepare(atc, apcm); if (err < 0) { - printk(KERN_ERR "ctxfi: Preparing pcm playback failed!!!\n"); + pr_err("ctxfi: Preparing pcm playback failed!!!\n"); return err; } @@ -324,7 +324,7 @@ static int ct_pcm_capture_prepare(struct snd_pcm_substream *substream) err = atc->pcm_capture_prepare(atc, apcm); if (err < 0) { - printk(KERN_ERR "ctxfi: Preparing pcm capture failed!!!\n"); + pr_err("ctxfi: Preparing pcm capture failed!!!\n"); return err; } @@ -435,7 +435,7 @@ int ct_alsa_pcm_create(struct ct_atc *atc, err = snd_pcm_new(atc->card, "ctxfi", device, playback_count, capture_count, &pcm); if (err < 0) { - printk(KERN_ERR "ctxfi: snd_pcm_new failed!! Err=%d\n", err); + pr_err("ctxfi: snd_pcm_new failed!! Err=%d\n", err); return err; } -- 1.8.1.2

2 1

[alsa-devel] [PATCH] doc: fix cross-compiling example
by Dmitry Voytik 25 Aug '14

25 Aug '14

Simplest way to configure cross-compilation with configure script is to pass '--host' option. Passing just '--target' doesn't work. Signed-off-by: Dmitry Voytik <voytikd(a)gmail.com> --- INSTALL | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/INSTALL b/INSTALL index 91a8648..47086e3 100644 --- a/INSTALL +++ b/INSTALL @@ -78,16 +78,13 @@ When you would like to cross-compile ALSA library (e.g. compile on i686 host but for arm architecture) you will need to call ./configure script with additional parameters: -CC=arm-linux-gcc ./configure --target=arm-linux +CC=arm-linux-gcc ./configure --host=arm-linux -In this example host where the library is build is guessed (should be -given with --host=platform) and target for which is the library build is -Linux on ARM architecture. You should omit setting 'CC' variable and -cross-compiler will be guessed too. +You can omit setting 'CC' variable and cross-compiler will be guessed too. So simplest version would be: -./configure --target=arm-linux +./configure --host=arm-linux For platform names in the form cpu-vendor-os (or aliases for this) you should look in 'config.guess' script. Target and all paths -- 1.7.9.5

2 1

[alsa-devel] [RESEND PATCH v4 0/2] mfd: arizona: add support for INn_MODE register
by Inha Song 25 Aug '14

25 Aug '14

This patch series add support for INn_MODE register control using platform data. Each input signal path can be configurated either as a Analogue or Digital using the INn_MODE registers. Changes for v4 - Update document content for more clarity Changes for v3 - Change to use of_property_read_u32_array - Fix a few typos - Update commit message Changes for v2 - Change to support - Update commit message - Update document content for more clarity Inha Song (2): mfd: arizona: Add support for INn_Mode register control mfd: arizona: Update DT binding to support INn_MODE init_data Documentation/devicetree/bindings/mfd/arizona.txt | 7 +++++++ drivers/mfd/arizona-core.c | 8 +++++++- 2 files changed, 14 insertions(+), 1 deletion(-) -- 2.0.0.390.gcb682f8

1 2

[alsa-devel] [PATCH v2 1/2] mfd: arizona: Add support for INn_Mode register control
by Inha Song 25 Aug '14

25 Aug '14

Some boards need to set the INn_MODE[1:0] register to change the input signal patch. This wlf,inmode property is optional. If present values must be specified by the number of ARIZONA_MAX_INPUT. Example: - wlf,inmode = <2 0 2 0>; /* IN1, IN3 use DMIC */ Signed-off-by: Inha Song <ideal.song(a)samsung.com> --- drivers/mfd/arizona-core.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c index 10a0cb9..2b68ccd 100644 --- a/drivers/mfd/arizona-core.c +++ b/drivers/mfd/arizona-core.c @@ -534,7 +534,7 @@ EXPORT_SYMBOL_GPL(arizona_of_get_named_gpio); static int arizona_of_get_core_pdata(struct arizona *arizona) { struct arizona_pdata *pdata = &arizona->pdata; - int ret, i; + int ret, i, proplen; pdata->reset = arizona_of_get_named_gpio(arizona, "wlf,reset", true); @@ -560,6 +560,15 @@ static int arizona_of_get_core_pdata(struct arizona *arizona) ret); } + proplen = of_property_count_u32_elems(arizona->dev->of_node, + "wlf,inmode"); + if (proplen > 0 && proplen <= ARRAY_SIZE(arizona->pdata.inmode)) { + for (i = 0; i < proplen; i++) + of_property_read_u32_index(arizona->dev->of_node, + "wlf,inmode", i, + &arizona->pdata.inmode[i]); + } + return 0; } -- 2.0.0.390.gcb682f8

3 3

[alsa-devel] [PATCH] pcm/kernel: Add DSD formats silence patterns
by Jurgen Kramer 25 Aug '14

25 Aug '14

This patch adds the silence patterns for the DSD sample formats, kernel side. Signed-off-by: Jurgen Kramer <gtmkramer(a)xs4all.nl> --- sound/core/pcm_misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/core/pcm_misc.c b/sound/core/pcm_misc.c index 4560ca0..2c6fd80 100644 --- a/sound/core/pcm_misc.c +++ b/sound/core/pcm_misc.c @@ -142,11 +142,11 @@ static struct pcm_format_data pcm_formats[(INT)SNDRV_PCM_FORMAT_LAST+1] = { }, [SNDRV_PCM_FORMAT_DSD_U8] = { .width = 8, .phys = 8, .le = 1, .signd = 0, - .silence = {}, + .silence = { 0x69 }, }, [SNDRV_PCM_FORMAT_DSD_U16_LE] = { .width = 16, .phys = 16, .le = 1, .signd = 0, - .silence = {}, + .silence = { 0x69, 0x69 }, }, /* FIXME: the following three formats are not defined properly yet */ [SNDRV_PCM_FORMAT_MPEG] = { -- 1.9.3

2 3

[alsa-devel] [PATCHv3] ASoC: fsl-sai: rename big_endian_data to is_lsb_first.
by Xiubo Li 25 Aug '14

25 Aug '14

Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 8 ++++---- sound/soc/fsl/fsl_sai.c | 6 +++--- sound/soc/fsl/fsl_sai.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 06a405e..929ca74 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -20,9 +20,9 @@ Required properties: See ../pinctrl/pinctrl-bindings.txt for details of the property values. - big-endian: Boolean property, required if all the FTM_PWM registers are big-endian rather than little-endian. -- big-endian-data: If this property is absent, the little endian mode will - be in use as default, or the big endian mode will be in use for all the - fifo data. +- lsb-first: Configures whether the LSB or the MSB is transmitted first for + the fifo data. If this property is absent, the LSB is transmitted first as + default, or the MSB is transmitted first. - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating that SAI will work in the synchronous mode (sync Tx with Rx) which means both the transimitter and receiver will send and receive data by following @@ -53,5 +53,5 @@ sai2: sai@40031000 { dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; big-endian; - big-endian-data; + lsb-first; }; diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index a6eb784..7eeb1dd 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -175,7 +175,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, bool tx = fsl_dir == FSL_FMT_TRANSMITTER; u32 val_cr2 = 0, val_cr4 = 0; - if (!sai->big_endian_data) + if (!sai->is_lsb_first) val_cr4 |= FSL_SAI_CR4_MF; /* DAI mode */ @@ -304,7 +304,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, val_cr5 |= FSL_SAI_CR5_WNW(word_width); val_cr5 |= FSL_SAI_CR5_W0W(word_width); - if (sai->big_endian_data) + if (sai->is_lsb_first) val_cr5 |= FSL_SAI_CR5_FBT(0); else val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); @@ -573,7 +573,7 @@ static int fsl_sai_probe(struct platform_device *pdev) if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) sai->sai_on_imx = true; - sai->big_endian_data = of_property_read_bool(np, "big-endian-data"); + sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 2cded44..3466720 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -132,7 +132,7 @@ struct fsl_sai { struct clk *bus_clk; struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; - bool big_endian_data; + bool is_lsb_first; bool is_dsp_mode; bool sai_on_imx; bool synchronous[2]; -- 1.8.5

2 1

[alsa-devel] [PATCHv2 0/5] Convert to use regmap framework's endianness method.
by Xiubo Li 25 Aug '14

25 Aug '14

Changes in V2: - Modified the regmap config to const type. - Added ASRC patch. - Followed Rutland's advice. Xiubo Li (5): ASoC: fsl-asrc: Convert to use regmap framework's endianness method. ASoC: fsl-esai: Convert to use regmap framework's endianness method. ASoC: fsl-spdif: Convert to use regmap framework's endianness method. ASoC: fsl-sai: Convert to use regmap framework's endianness method. ASoC: fsl-sai: rename big_endian_data to is_msb_first. Documentation/devicetree/bindings/sound/fsl-sai.txt | 15 +++++++-------- sound/soc/fsl/fsl_asrc.c | 6 +----- sound/soc/fsl/fsl_esai.c | 5 +---- sound/soc/fsl/fsl_sai.c | 12 ++++-------- sound/soc/fsl/fsl_sai.h | 3 +-- sound/soc/fsl/fsl_spdif.c | 5 +---- 6 files changed, 15 insertions(+), 31 deletions(-) -- 1.8.5

4 20

[alsa-devel] 120 BPM equals 16 beats per 2 seconds
by Joël Krähemann 24 Aug '14

24 Aug '14

Is this statement correct? 120 BPM equals 16 beats per 2 seconds because this is what my sequencer does and everything should be fine. GNU/Linux rules ... please take a look at http://sf.net/p/ags best regards Joël

2 1

[alsa-devel] Grey noise with HDA Intel PCH
by Julian Wollrath 23 Aug '14

23 Aug '14

Hello, when having my soundcard not muted, I get to hear grey noise over the speakers or over the headphone, depending if I have a headphone plugged in or not. I did not experience this constant hearing of grey noise under Windows, so I suspect, that their is some problem with the linux driver but I do not have any idea, what it could be. Therefore, I attached the alsa-info.sh output, maybe that could give somebody a clue. Thank you for your time, with best regards, Julian Wollrath alsa-info.sh Output: !!################################ !!ALSA Information Script v 0.4.63 !!################################ !!Script ran on: Thu Aug 14 09:16:55 UTC 2014 !!Linux Distribution !!------------------ Debian GNU/Linux jessie/sid \n \l PRETTY_NAME="Debian GNU/Linux jessie/sid" NAME="Debian GNU/Linux" ID=debian HOME_URL="http://www.debian.org/" SUPPORT_URL="http://www.debian.org/support/" BUG_REPORT_URL="https://bugs.debian.org/" !!DMI Information !!--------------- Manufacturer: LENOVO Product Name: 23250BM Product Version: ThinkPad X230 Firmware Version: G2ETA1WW (2.61 ) !!Kernel Information !!------------------ Kernel release: 3.16.1 Operating System: GNU/Linux Architecture: x86_64 Processor: unknown SMP Enabled: Yes !!ALSA Version !!------------ Driver version: k3.16.1 Library version: 1.0.28 Utilities version: 1.0.28 !!Loaded ALSA modules !!------------------- snd_hda_intel thinkpad_acpi !!Sound Servers on this system !!---------------------------- No sound servers found. !!Soundcards recognised by ALSA !!----------------------------- 0 [PCH ]: HDA-Intel - HDA Intel PCH HDA Intel PCH at 0xf2530000 irq 45 29 [ThinkPadEC ]: ThinkPad EC - ThinkPad Console Audio Control ThinkPad Console Audio Control at EC reg 0x30, fw unknown !!PCI Soundcards installed in the system !!-------------------------------------- 00:1b.0 Audio device: Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller (rev 04) !!Advanced information - PCI Vendor/Device/Subsystem ID's !!------------------------------------------------------- 00:1b.0 0403: 8086:1e20 (rev 04) Subsystem: 17aa:21fa !!Modprobe options (Sound related) !!-------------------------------- snd_pcsp: index=-2 snd_usb_audio: index=-2 snd_atiixp_modem: index=-2 snd_intel8x0m: index=-2 snd_via82xx_modem: index=-2 !!Loaded sound module options !!--------------------------- !!Module: snd_hda_intel align_buffer_size : -1 bdl_pos_adj : 1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 beep_mode : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y enable : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y enable_msi : -1 id : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null) index : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 jackpoll_ms : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 model : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null) patch : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null) position_fix : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 power_save : 1 power_save_controller : Y probe_mask : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 probe_only : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 single_cmd : N snoop : Y !!Module: thinkpad_acpi brightness_enable : 2 brightness_mode : 4 enable : Y experimental : 0 fan_control : N force_load : N id : ThinkPadEC index : -536870912 volume_capabilities : 0 volume_control : N volume_mode : 3 !!HDA-Intel Codec information !!--------------------------- --startcollapse-- Codec: Realtek ALC269VC Address: 0 AFG Function Id: 0x1 (unsol 1) Vendor Id: 0x10ec0269 Subsystem Id: 0x17aa21fa Revision Id: 0x100203 No Modem Function Group found Default PCM: rates [0x5f0]: 32000 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Default Amp-In caps: N/A Default Amp-Out caps: N/A State of AFG node 0x01: Power states: D0 D1 D2 D3 CLKSTOP EPSS Power: setting=D0, actual=D0 GPIO: io=2, o=0, i=0, unsolicited=1, wake=0 IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 Node 0x02 [Audio Output] wcaps 0x41d: Stereo Amp-Out Control: name="Speaker Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Device: name="ALC269VC Analog", type="Audio", device=0 Amp-Out caps: ofs=0x57, nsteps=0x57, stepsize=0x02, mute=0 Amp-Out vals: [0x13 0x13] Converter: stream=8, channel=0 PCM: rates [0x560]: 44100 48000 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x03 [Audio Output] wcaps 0x41d: Stereo Amp-Out Control: name="Headphone Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x57, nsteps=0x57, stepsize=0x02, mute=0 Amp-Out vals: [0x13 0x13] Converter: stream=8, channel=0 PCM: rates [0x560]: 44100 48000 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x04 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x05 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x06 [Audio Output] wcaps 0x611: Stereo Digital Converter: stream=0, channel=0 Digital: Digital category: 0x0 IEC Coding Type: 0x0 PCM: rates [0x5f0]: 32000 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x07 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x08 [Audio Input] wcaps 0x10051b: Stereo Amp-In Amp-In caps: ofs=0x17, nsteps=0x3f, stepsize=0x02, mute=1 Amp-In vals: [0x97 0x97] Converter: stream=0, channel=0 SDI-Select: 0 PCM: rates [0x560]: 44100 48000 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x23 Node 0x09 [Audio Input] wcaps 0x10051b: Stereo Amp-In Control: name="Capture Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Capture Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Device: name="ALC269VC Analog", type="Audio", device=0 Amp-In caps: ofs=0x17, nsteps=0x3f, stepsize=0x02, mute=1 Amp-In vals: [0xbf 0xbf] Converter: stream=0, channel=0 SDI-Select: 0 PCM: rates [0x560]: 44100 48000 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x22 Node 0x0a [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x0b [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Control: name="Mic Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Mic Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Dock Mic Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=1, ofs=0 Control: name="Dock Mic Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=1, ofs=0 Control: name="Beep Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=4, ofs=0 Control: name="Beep Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=4, ofs=0 Amp-In caps: ofs=0x17, nsteps=0x1f, stepsize=0x05, mute=1 Amp-In vals: [0x00 0x00] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] Connection: 5 0x18 0x19 0x1a 0x1b 0x1d Node 0x0c [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x00 0x00] Connection: 2 0x02 0x0b Node 0x0d [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x00 0x00] Connection: 2 0x03 0x0b Node 0x0e [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x0f [Audio Mixer] wcaps 0x20010a: Mono Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00] [0x80] Connection: 2 0x02 0x0b Node 0x10 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x11 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x12 [Pin Complex] wcaps 0x40040b: Stereo Amp-In Control: name="Internal Mic Boost Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Internal Mic Phantom Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Pincap 0x00000020: IN Pin Default 0x90a60140: [Fixed] Mic at Int N/A Conn = Digital, Color = Unknown DefAssociation = 0x4, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x13 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x14 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Control: name="Speaker Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Speaker Phantom Jack", index=0, device=0 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x00010014: OUT EAPD Detect EAPD 0x2: EAPD Pin Default 0x90170110: [Fixed] Speaker at Int N/A Conn = Analog, Color = Unknown DefAssociation = 0x1, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x00: Unsolicited: tag=00, enabled=0 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 2 0x0c* 0x0d Node 0x15 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Control: name="Headphone Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Headphone Jack", index=0, device=0 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x0001001c: OUT HP EAPD Detect EAPD 0x2: EAPD Pin Default 0x03211020: [Jack] HP Out at Ext Left Conn = 1/8, Color = Black DefAssociation = 0x2, Sequence = 0x0 Pin-ctls: 0xc0: OUT HP Unsolicited: tag=01, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 2 0x0c 0x0d* Node 0x16 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x17 [Pin Complex] wcaps 0x40050c: Mono Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80] Pincap 0x00000010: OUT Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x00: Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x0f Node 0x18 [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Control: name="Mic Boost Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Mic Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x00003734: IN OUT Detect Vref caps: HIZ 50 GRD 80 100 Pin Default 0x03a11830: [Jack] Mic at Ext Left Conn = 1/8, Color = Black DefAssociation = 0x3, Sequence = 0x0 Pin-ctls: 0x24: IN VREF_80 Unsolicited: tag=04, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 2 0x0c* 0x0d Node 0x19 [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Control: name="Dock Mic Boost Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Dock Mic Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x00003734: IN OUT Detect Vref caps: HIZ 50 GRD 80 100 Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x24: IN VREF_80 Unsolicited: tag=03, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 2 0x0c* 0x0d Node 0x1a [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000373c: IN OUT HP Detect Vref caps: HIZ 50 GRD 80 100 Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN VREF_HIZ Unsolicited: tag=00, enabled=0 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 2 0x0c* 0x0d Node 0x1b [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Control: name="Headphone Playback Switch", index=1, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Dock Headphone Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x00003734: IN OUT Detect Vref caps: HIZ 50 GRD 80 100 Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x40: OUT VREF_HIZ Unsolicited: tag=02, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 2 0x0c 0x0d* Node 0x1c [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x1d [Pin Complex] wcaps 0x400400: Mono Pincap 0x00000020: IN Pin Default 0x40138205: [N/A] Speaker at Ext N/A Conn = ATAPI, Color = Purple DefAssociation = 0x0, Sequence = 0x5 Pin-ctls: 0x20: IN Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x1e [Pin Complex] wcaps 0x400781: Stereo Digital Pincap 0x00000014: OUT Detect Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x40: OUT Unsolicited: tag=00, enabled=0 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x06 Node 0x1f [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x20 [Vendor Defined Widget] wcaps 0xf00040: Mono Processing caps: benign=0, ncoeff=37 Node 0x21 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x22 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x00 0x00] Connection: 7 0x18 0x19 0x1a 0x1b 0x1d 0x0b 0x12 Node 0x23 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] Connection: 6 0x18 0x19 0x1a 0x1b 0x1d 0x0b Codec: Intel PantherPoint HDMI Address: 3 AFG Function Id: 0x1 (unsol 0) Vendor Id: 0x80862806 Subsystem Id: 0x80860101 Revision Id: 0x100000 No Modem Function Group found Default PCM: rates [0x0]: bits [0x0]: formats [0x0]: Default Amp-In caps: N/A Default Amp-Out caps: N/A State of AFG node 0x01: Power states: D0 D3 CLKSTOP EPSS Power: setting=D0, actual=D0, Clock-stop-OK GPIO: io=0, o=0, i=0, unsolicited=0, wake=0 Node 0x02 [Audio Output] wcaps 0x6611: 8-Channels Digital Converter: stream=0, channel=0 Digital: Enabled Digital category: 0x0 IEC Coding Type: 0x0 PCM: rates [0x7f0]: 32000 44100 48000 88200 96000 176400 192000 bits [0x1e]: 16 20 24 32 formats [0x5]: PCM AC3 Power states: D0 D3 EPSS Power: setting=D0, actual=D0 Node 0x03 [Audio Output] wcaps 0x6611: 8-Channels Digital Converter: stream=0, channel=0 Digital: Enabled Digital category: 0x0 IEC Coding Type: 0x0 PCM: rates [0x7f0]: 32000 44100 48000 88200 96000 176400 192000 bits [0x1e]: 16 20 24 32 formats [0x5]: PCM AC3 Power states: D0 D3 EPSS Power: setting=D0, actual=D0 Node 0x04 [Audio Output] wcaps 0x6611: 8-Channels Digital Converter: stream=0, channel=0 Digital: Enabled Digital category: 0x0 IEC Coding Type: 0x0 PCM: rates [0x7f0]: 32000 44100 48000 88200 96000 176400 192000 bits [0x1e]: 16 20 24 32 formats [0x5]: PCM AC3 Power states: D0 D3 EPSS Power: setting=D0, actual=D0 Node 0x05 [Pin Complex] wcaps 0x40778d: 8-Channels Digital Amp-Out CP Control: name="HDMI/DP,pcm=3 Jack", index=0, device=0 Control: name="IEC958 Playback Con Mask", index=0, device=0 Control: name="IEC958 Playback Pro Mask", index=0, device=0 Control: name="IEC958 Playback Default", index=0, device=0 Control: name="IEC958 Playback Switch", index=0, device=0 Control: name="ELD", index=0, device=3 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x09000094: OUT Detect HBR HDMI DP Pin Default 0x18560010: [Jack] Digital Out at Int HDMI Conn = Digital, Color = Unknown DefAssociation = 0x1, Sequence = 0x0 Pin-ctls: 0x40: OUT Unsolicited: tag=01, enabled=1 Power states: D0 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x02 Node 0x06 [Pin Complex] wcaps 0x40778d: 8-Channels Digital Amp-Out CP Control: name="HDMI/DP,pcm=7 Jack", index=0, device=0 Control: name="IEC958 Playback Con Mask", index=1, device=0 Control: name="IEC958 Playback Pro Mask", index=1, device=0 Control: name="IEC958 Playback Default", index=1, device=0 Control: name="IEC958 Playback Switch", index=1, device=0 Control: name="ELD", index=0, device=7 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x09000094: OUT Detect HBR HDMI DP Pin Default 0x18560020: [Jack] Digital Out at Int HDMI Conn = Digital, Color = Unknown DefAssociation = 0x2, Sequence = 0x0 Pin-ctls: 0x40: OUT Unsolicited: tag=02, enabled=1 Power states: D0 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x03 Node 0x07 [Pin Complex] wcaps 0x40778d: 8-Channels Digital Amp-Out CP Control: name="HDMI/DP,pcm=8 Jack", index=0, device=0 Control: name="IEC958 Playback Con Mask", index=2, device=0 Control: name="IEC958 Playback Pro Mask", index=2, device=0 Control: name="IEC958 Playback Default", index=2, device=0 Control: name="IEC958 Playback Switch", index=2, device=0 Control: name="ELD", index=0, device=8 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x09000094: OUT Detect HBR HDMI DP Pin Default 0x18560030: [Jack] Digital Out at Int HDMI Conn = Digital, Color = Unknown DefAssociation = 0x3, Sequence = 0x0 Pin-ctls: 0x40: OUT Unsolicited: tag=03, enabled=1 Power states: D0 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x04 Node 0x08 [Vendor Defined Widget] wcaps 0xf00000: Mono --endcollapse-- !!ALSA Device nodes !!----------------- crw-rw----+ 1 root audio 116, 3 Aug 14 10:30 /dev/snd/controlC0 crw-rw----+ 1 root audio 116, 2 Aug 14 10:30 /dev/snd/controlC29 crw-rw----+ 1 root audio 116, 9 Aug 14 10:30 /dev/snd/hwC0D0 crw-rw----+ 1 root audio 116, 10 Aug 14 10:30 /dev/snd/hwC0D3 crw-rw----+ 1 root audio 116, 5 Aug 14 10:30 /dev/snd/pcmC0D0c crw-rw----+ 1 root audio 116, 4 Aug 14 11:01 /dev/snd/pcmC0D0p crw-rw----+ 1 root audio 116, 6 Aug 14 10:30 /dev/snd/pcmC0D3p crw-rw----+ 1 root audio 116, 7 Aug 14 10:30 /dev/snd/pcmC0D7p crw-rw----+ 1 root audio 116, 8 Aug 14 10:30 /dev/snd/pcmC0D8p crw-rw----+ 1 root audio 116, 33 Aug 14 10:30 /dev/snd/timer /dev/snd/by-path: total 0 drwxr-xr-x 2 root root 80 Aug 14 10:30 . drwxr-xr-x 3 root root 260 Aug 14 10:30 .. lrwxrwxrwx 1 root root 12 Aug 14 10:30 pci-0000:00:1b.0 -> ../controlC0 lrwxrwxrwx 1 root root 13 Aug 14 10:30 platform-thinkpad_acpi -> ../controlC29 !!Aplay/Arecord output !!-------------------- APLAY **** List of PLAYBACK Hardware Devices **** card 0: PCH [HDA Intel PCH], device 0: ALC269VC Analog [ALC269VC Analog] Subdevices: 0/1 Subdevice #0: subdevice #0 card 0: PCH [HDA Intel PCH], device 3: HDMI 0 [HDMI 0] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: PCH [HDA Intel PCH], device 7: HDMI 1 [HDMI 1] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: PCH [HDA Intel PCH], device 8: HDMI 2 [HDMI 2] Subdevices: 1/1 Subdevice #0: subdevice #0 ARECORD **** List of CAPTURE Hardware Devices **** card 0: PCH [HDA Intel PCH], device 0: ALC269VC Analog [ALC269VC Analog] Subdevices: 1/1 Subdevice #0: subdevice #0 !!Amixer output !!------------- !!-------Mixer controls for card 0 [PCH] Card hw:0 'PCH'/'HDA Intel PCH at 0xf2530000 irq 45' Mixer name : 'Intel PantherPoint HDMI' Components : 'HDA:10ec0269,17aa21fa,00100203 HDA:80862806,80860101,00100000' Controls : 50 Simple ctrls : 17 Simple mixer control 'Master',0 Capabilities: pvolume pvolume-joined pswitch pswitch-joined Playback channels: Mono Limits: Playback 0 - 87 Mono: Playback 19 [22%] [-51.00dB] [on] Simple mixer control 'Headphone',0 Capabilities: pvolume pswitch Playback channels: Front Left - Front Right Limits: Playback 0 - 87 Mono: Front Left: Playback 87 [100%] [0.00dB] [on] Front Right: Playback 87 [100%] [0.00dB] [on] Simple mixer control 'Headphone',1 Capabilities: pswitch Playback channels: Front Left - Front Right Mono: Front Left: Playback [on] Front Right: Playback [on] Simple mixer control 'Speaker',0 Capabilities: pvolume pswitch Playback channels: Front Left - Front Right Limits: Playback 0 - 87 Mono: Front Left: Playback 87 [100%] [0.00dB] [on] Front Right: Playback 87 [100%] [0.00dB] [on] Simple mixer control 'PCM',0 Capabilities: pvolume Playback channels: Front Left - Front Right Limits: Playback 0 - 255 Mono: Front Left: Playback 255 [100%] [0.00dB] Front Right: Playback 255 [100%] [0.00dB] Simple mixer control 'Mic',0 Capabilities: pvolume pswitch Playback channels: Front Left - Front Right Limits: Playback 0 - 31 Mono: Front Left: Playback 0 [0%] [-34.50dB] [on] Front Right: Playback 0 [0%] [-34.50dB] [on] Simple mixer control 'Mic Boost',0 Capabilities: volume Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: 0 - 3 Front Left: 0 [0%] [0.00dB] Front Right: 0 [0%] [0.00dB] Simple mixer control 'IEC958',0 Capabilities: pswitch pswitch-joined Playback channels: Mono Mono: Playback [on] Simple mixer control 'IEC958',1 Capabilities: pswitch pswitch-joined Playback channels: Mono Mono: Playback [on] Simple mixer control 'IEC958',2 Capabilities: pswitch pswitch-joined Playback channels: Mono Mono: Playback [on] Simple mixer control 'Beep',0 Capabilities: pvolume pswitch Playback channels: Front Left - Front Right Limits: Playback 0 - 31 Mono: Front Left: Playback 0 [0%] [-34.50dB] [off] Front Right: Playback 0 [0%] [-34.50dB] [off] Simple mixer control 'Capture',0 Capabilities: cvolume cswitch Capture channels: Front Left - Front Right Limits: Capture 0 - 63 Front Left: Capture 63 [100%] [30.00dB] [off] Front Right: Capture 63 [100%] [30.00dB] [off] Simple mixer control 'Auto-Mute Mode',0 Capabilities: enum Items: 'Disabled' 'Enabled' Item0: 'Enabled' Simple mixer control 'Digital',0 Capabilities: cvolume Capture channels: Front Left - Front Right Limits: Capture 0 - 120 Front Left: Capture 60 [50%] [0.00dB] Front Right: Capture 60 [50%] [0.00dB] Simple mixer control 'Dock Mic',0 Capabilities: pvolume pswitch Playback channels: Front Left - Front Right Limits: Playback 0 - 31 Mono: Front Left: Playback 0 [0%] [-34.50dB] [off] Front Right: Playback 0 [0%] [-34.50dB] [off] Simple mixer control 'Dock Mic Boost',0 Capabilities: volume Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: 0 - 3 Front Left: 0 [0%] [0.00dB] Front Right: 0 [0%] [0.00dB] Simple mixer control 'Internal Mic Boost',0 Capabilities: volume Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: 0 - 3 Front Left: 0 [0%] [0.00dB] Front Right: 0 [0%] [0.00dB] !!-------Mixer controls for card 29 [ThinkPadEC] Card hw:29 'ThinkPadEC'/'ThinkPad Console Audio Control at EC reg 0x30, fw unknown' Mixer name : 'ThinkPad EC (unknown)' Components : '' Controls : 1 Simple ctrls : 1 Simple mixer control 'Console',0 Capabilities: pswitch pswitch-joined Playback channels: Mono Mono: Playback [on] !!Alsactl output !!-------------- --startcollapse-- state.PCH { control.1 { iface MIXER name 'Speaker Playback Volume' value.0 87 value.1 87 comment { access 'read write' type INTEGER count 2 range '0 - 87' dbmin -6525 dbmax 0 dbvalue.0 0 dbvalue.1 0 } } control.2 { iface MIXER name 'Speaker Playback Switch' value.0 true value.1 true comment { access 'read write' type BOOLEAN count 2 } } control.3 { iface MIXER name 'Headphone Playback Volume' value.0 87 value.1 87 comment { access 'read write' type INTEGER count 2 range '0 - 87' dbmin -6525 dbmax 0 dbvalue.0 0 dbvalue.1 0 } } control.4 { iface MIXER name 'Headphone Playback Switch' value.0 true value.1 true comment { access 'read write' type BOOLEAN count 2 } } control.5 { iface MIXER name 'Headphone Playback Switch' index 1 value.0 true value.1 true comment { access 'read write' type BOOLEAN count 2 } } control.6 { iface MIXER name 'Mic Playback Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 31' dbmin -3450 dbmax 1200 dbvalue.0 -3450 dbvalue.1 -3450 } } control.7 { iface MIXER name 'Mic Playback Switch' value.0 true value.1 true comment { access 'read write' type BOOLEAN count 2 } } control.8 { iface MIXER name 'Dock Mic Playback Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 31' dbmin -3450 dbmax 1200 dbvalue.0 -3450 dbvalue.1 -3450 } } control.9 { iface MIXER name 'Dock Mic Playback Switch' value.0 false value.1 false comment { access 'read write' type BOOLEAN count 2 } } control.10 { iface MIXER name 'Auto-Mute Mode' value Enabled comment { access 'read write' type ENUMERATED count 1 item.0 Disabled item.1 Enabled } } control.11 { iface MIXER name 'Capture Volume' value.0 63 value.1 63 comment { access 'read write' type INTEGER count 2 range '0 - 63' dbmin -1725 dbmax 3000 dbvalue.0 3000 dbvalue.1 3000 } } control.12 { iface MIXER name 'Capture Switch' value.0 false value.1 false comment { access 'read write' type BOOLEAN count 2 } } control.13 { iface MIXER name 'Mic Boost Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 3' dbmin 0 dbmax 3000 dbvalue.0 0 dbvalue.1 0 } } control.14 { iface MIXER name 'Dock Mic Boost Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 3' dbmin 0 dbmax 3000 dbvalue.0 0 dbvalue.1 0 } } control.15 { iface MIXER name 'Internal Mic Boost Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 3' dbmin 0 dbmax 3000 dbvalue.0 0 dbvalue.1 0 } } control.16 { iface MIXER name 'Master Playback Volume' value 19 comment { access 'read write' type INTEGER count 1 range '0 - 87' dbmin -6525 dbmax 0 dbvalue.0 -5100 } } control.17 { iface MIXER name 'Master Playback Switch' value true comment { access 'read write' type BOOLEAN count 1 } } control.18 { iface CARD name 'Mic Jack' value false comment { access read type BOOLEAN count 1 } } control.19 { iface CARD name 'Dock Mic Jack' value false comment { access read type BOOLEAN count 1 } } control.20 { iface CARD name 'Internal Mic Phantom Jack' value true comment { access read type BOOLEAN count 1 } } control.21 { iface CARD name 'Speaker Phantom Jack' value true comment { access read type BOOLEAN count 1 } } control.22 { iface CARD name 'Headphone Jack' value true comment { access read type BOOLEAN count 1 } } control.23 { iface CARD name 'Dock Headphone Jack' value false comment { access read type BOOLEAN count 1 } } control.24 { iface MIXER name 'Beep Playback Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 31' dbmin -3450 dbmax 1200 dbvalue.0 -3450 dbvalue.1 -3450 } } control.25 { iface MIXER name 'Beep Playback Switch' value.0 false value.1 false comment { access 'read write' type BOOLEAN count 2 } } control.26 { iface PCM name 'Playback Channel Map' value.0 3 value.1 4 value.2 0 value.3 0 comment { access read type INTEGER count 4 range '0 - 36' } } control.27 { iface PCM name 'Capture Channel Map' value.0 0 value.1 0 comment { access read type INTEGER count 2 range '0 - 36' } } control.28 { iface CARD name 'HDMI/DP,pcm=3 Jack' value false comment { access read type BOOLEAN count 1 } } control.29 { iface MIXER name 'IEC958 Playback Con Mask' value '0fff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access read type IEC958 count 1 } } control.30 { iface MIXER name 'IEC958 Playback Pro Mask' value '0f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access read type IEC958 count 1 } } control.31 { iface MIXER name 'IEC958 Playback Default' value '0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access 'read write' type IEC958 count 1 } } control.32 { iface MIXER name 'IEC958 Playback Switch' value true comment { access 'read write' type BOOLEAN count 1 } } control.33 { iface PCM device 3 name ELD value '' comment { access 'read volatile' type BYTES count 0 } } control.34 { iface CARD name 'HDMI/DP,pcm=7 Jack' value false comment { access read type BOOLEAN count 1 } } control.35 { iface MIXER name 'IEC958 Playback Con Mask' index 1 value '0fff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access read type IEC958 count 1 } } control.36 { iface MIXER name 'IEC958 Playback Pro Mask' index 1 value '0f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access read type IEC958 count 1 } } control.37 { iface MIXER name 'IEC958 Playback Default' index 1 value '0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access 'read write' type IEC958 count 1 } } control.38 { iface MIXER name 'IEC958 Playback Switch' index 1 value true comment { access 'read write' type BOOLEAN count 1 } } control.39 { iface PCM device 7 name ELD value '' comment { access 'read volatile' type BYTES count 0 } } control.40 { iface CARD name 'HDMI/DP,pcm=8 Jack' value false comment { access read type BOOLEAN count 1 } } control.41 { iface MIXER name 'IEC958 Playback Con Mask' index 2 value '0fff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access read type IEC958 count 1 } } control.42 { iface MIXER name 'IEC958 Playback Pro Mask' index 2 value '0f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access read type IEC958 count 1 } } control.43 { iface MIXER name 'IEC958 Playback Default' index 2 value '0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access 'read write' type IEC958 count 1 } } control.44 { iface MIXER name 'IEC958 Playback Switch' index 2 value true comment { access 'read write' type BOOLEAN count 1 } } control.45 { iface PCM device 8 name ELD value '' comment { access 'read volatile' type BYTES count 0 } } control.46 { iface PCM device 3 name 'Playback Channel Map' value.0 0 value.1 0 value.2 0 value.3 0 value.4 0 value.5 0 value.6 0 value.7 0 comment { access 'read write' type INTEGER count 8 range '0 - 36' } } control.47 { iface PCM device 7 name 'Playback Channel Map' value.0 0 value.1 0 value.2 0 value.3 0 value.4 0 value.5 0 value.6 0 value.7 0 comment { access 'read write' type INTEGER count 8 range '0 - 36' } } control.48 { iface PCM device 8 name 'Playback Channel Map' value.0 0 value.1 0 value.2 0 value.3 0 value.4 0 value.5 0 value.6 0 value.7 0 comment { access 'read write' type INTEGER count 8 range '0 - 36' } } control.49 { iface MIXER name 'PCM Playback Volume' value.0 255 value.1 255 comment { access 'read write user' type INTEGER count 2 range '0 - 255' tlv '0000000100000008ffffec1400000014' dbmin -5100 dbmax 0 dbvalue.0 0 dbvalue.1 0 } } control.50 { iface MIXER name 'Digital Capture Volume' value.0 60 value.1 60 comment { access 'read write user' type INTEGER count 2 range '0 - 120' tlv '0000000100000008fffff44800000032' dbmin -3000 dbmax 3000 dbvalue.0 0 dbvalue.1 0 } } } state.ThinkPadEC { control.1 { iface MIXER name 'Console Playback Switch' value true comment { access read type BOOLEAN count 1 } } } --endcollapse-- !!All Loaded Modules !!------------------ Module acpi_call arc4 iwldvm uvcvideo x86_pkg_temp_thermal intel_powerclamp intel_rapl ecb videobuf2_vmalloc videobuf2_memops coretemp videobuf2_core kvm_intel mac80211 btusb bluetooth crc16 snd_hda_codec_hdmi i915 v4l2_common kvm videodev snd_hda_codec_realtek snd_hda_codec_generic iwlwifi cfg80211 snd_hda_intel i2c_algo_bit drm_kms_helper drm evdev snd_hda_controller thinkpad_acpi wmi pcspkr snd_hda_codec psmouse nvram serio_raw rfkill snd_hwdep i2c_i801 snd_pcm snd_timer snd tpm_tis soundcore tpm i2c_core battery ac video button processor sch_fq fuse autofs4 dm_crypt dm_mod sd_mod crc_t10dif crct10dif_generic crct10dif_pclmul crct10dif_common crc32_pclmul crc32c_intel ghash_clmulni_intel ahci libahci ehci_pci xhci_hcd ehci_hcd libata sdhci_pci sdhci scsi_mod usbcore e1000e mmc_core usb_common ptp pps_core thermal thermal_sys !!Sysfs Files !!----------- /sys/class/sound/hwC0D0/init_pin_configs: 0x12 0x90a60140 0x14 0x90170110 0x15 0x03211020 0x17 0x411111f0 0x18 0x03a11830 0x19 0x411111f0 0x1a 0x411111f0 0x1b 0x411111f0 0x1d 0x40138205 0x1e 0x411111f0 /sys/class/sound/hwC0D0/driver_pin_configs: 0x19 0x23a11040 0x1b 0x2121103f /sys/class/sound/hwC0D0/user_pin_configs: /sys/class/sound/hwC0D0/init_verbs: /sys/class/sound/hwC0D0/hints: /sys/class/sound/hwC0D3/init_pin_configs: 0x05 0x18560010 0x06 0x18560020 0x07 0x18560030 /sys/class/sound/hwC0D3/driver_pin_configs: /sys/class/sound/hwC0D3/user_pin_configs: /sys/class/sound/hwC0D3/init_verbs: /sys/class/sound/hwC0D3/hints: !!ALSA/HDA dmesg !!-------------- [ 15.620516] [drm] Initialized drm 1.1.0 20060810 [ 15.750496] snd_hda_intel 0000:00:1b.0: irq 45 for MSI/MSI-X [ 15.810710] cfg80211: Calling CRDA to update world regulatory domain -- [ 15.858672] iwlwifi 0000:03:00.0: irq 46 for MSI/MSI-X [ 15.937398] sound hdaudioC0D0: autoconfig: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker [ 15.937403] sound hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 15.937406] sound hdaudioC0D0: hp_outs=2 (0x15/0x1b/0x0/0x0/0x0) [ 15.937408] sound hdaudioC0D0: mono: mono_out=0x0 [ 15.937410] sound hdaudioC0D0: inputs: [ 15.937413] sound hdaudioC0D0: Mic=0x18 [ 15.937415] sound hdaudioC0D0: Dock Mic=0x19 [ 15.937417] sound hdaudioC0D0: Internal Mic=0x12 [ 15.941372] usb 1-1.4: new full-speed USB device number 5 using ehci-pci -- [ 15.972070] Console: switching to colour dummy device 80x25 [ 15.980930] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1b.0/sound/card0/hdaudioC0D0/input8 [ 15.981282] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 [ 15.981677] input: HDA Intel PCH Dock Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 [ 15.981779] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 [ 15.981879] input: HDA Intel PCH Dock Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input12 [ 15.982280] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input13 [ 15.982802] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input14 [ 15.983440] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input15 [ 15.993203] i915 0000:00:02.0: irq 47 for MSI/MSI-X

3 16

[alsa-devel] [PATCH] ASoC: ac97-codec: Remove ASoC level IO support
by Lars-Peter Clausen 23 Aug '14

23 Aug '14

This driver doesn't use any ASoC level IO nor does it register any controls or DAPM elements that require it. This means it can safely be removed. Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> --- sound/soc/codecs/ac97.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/sound/soc/codecs/ac97.c b/sound/soc/codecs/ac97.c index e889e1b..bd9b183 100644 --- a/sound/soc/codecs/ac97.c +++ b/sound/soc/codecs/ac97.c @@ -69,19 +69,6 @@ static struct snd_soc_dai_driver ac97_dai = { .ops = &ac97_dai_ops, }; -static unsigned int ac97_read(struct snd_soc_codec *codec, - unsigned int reg) -{ - return soc_ac97_ops->read(codec->ac97, reg); -} - -static int ac97_write(struct snd_soc_codec *codec, unsigned int reg, - unsigned int val) -{ - soc_ac97_ops->write(codec->ac97, reg, val); - return 0; -} - static int ac97_soc_probe(struct snd_soc_codec *codec) { struct snd_ac97_bus *ac97_bus; @@ -122,8 +109,6 @@ static int ac97_soc_resume(struct snd_soc_codec *codec) #endif static struct snd_soc_codec_driver soc_codec_dev_ac97 = { - .write = ac97_write, - .read = ac97_read, .probe = ac97_soc_probe, .suspend = ac97_soc_suspend, .resume = ac97_soc_resume, -- 1.8.0

2 1

[alsa-devel] [PATCH] sound: tegra: tegra_asoc_utils.h: Fix typo in include guard
by Rasmus Villemoes 22 Aug '14

22 Aug '14

Signed-off-by: Rasmus Villemoes <linux(a)rasmusvillemoes.dk> --- sound/soc/tegra/tegra_asoc_utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/tegra/tegra_asoc_utils.h b/sound/soc/tegra/tegra_asoc_utils.h index 9577121..ca80376 100644 --- a/sound/soc/tegra/tegra_asoc_utils.h +++ b/sound/soc/tegra/tegra_asoc_utils.h @@ -21,7 +21,7 @@ */ #ifndef __TEGRA_ASOC_UTILS_H__ -#define __TEGRA_ASOC_UTILS_H_ +#define __TEGRA_ASOC_UTILS_H__ struct clk; struct device; -- 1.9.2

3 2

[alsa-devel] [PATCH] sound: soc: da732x.h: Fix typo in include guard
by Rasmus Villemoes 22 Aug '14

22 Aug '14

Signed-off-by: Rasmus Villemoes <linux(a)rasmusvillemoes.dk> --- sound/soc/codecs/da732x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/da732x.h b/sound/soc/codecs/da732x.h index 1dceafe..f586cbd 100644 --- a/sound/soc/codecs/da732x.h +++ b/sound/soc/codecs/da732x.h @@ -11,7 +11,7 @@ */ #ifndef __DA732X_H_ -#define __DA732X_H +#define __DA732X_H_ #include <sound/soc.h> -- 1.9.2

2 1

[alsa-devel] [PATCH] sound: pci: ct20k1reg: Fix typo in include guard
by Rasmus Villemoes 22 Aug '14

22 Aug '14

Signed-off-by: Rasmus Villemoes <linux(a)rasmusvillemoes.dk> --- sound/pci/ctxfi/ct20k1reg.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/sound/pci/ctxfi/ct20k1reg.h b/sound/pci/ctxfi/ct20k1reg.h index f2e34e3..5851249 100644 --- a/sound/pci/ctxfi/ct20k1reg.h +++ b/sound/pci/ctxfi/ct20k1reg.h @@ -7,7 +7,7 @@ */ #ifndef CT20K1REG_H -#define CT20k1REG_H +#define CT20K1REG_H /* 20k1 registers */ #define DSPXRAM_START 0x000000 @@ -632,5 +632,3 @@ #define I2SD_R 0x19L #endif /* CT20K1REG_H */ - - -- 1.9.2

2 2

[alsa-devel] [PATCH] sound: pci: ca0132_regs.h: Fix typo in include guard
by Rasmus Villemoes 22 Aug '14

22 Aug '14

Signed-off-by: Rasmus Villemoes <linux(a)rasmusvillemoes.dk> --- sound/pci/hda/ca0132_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/hda/ca0132_regs.h b/sound/pci/hda/ca0132_regs.h index 07e7609..8371274 100644 --- a/sound/pci/hda/ca0132_regs.h +++ b/sound/pci/hda/ca0132_regs.h @@ -20,7 +20,7 @@ */ #ifndef __CA0132_REGS_H -#define __CA0312_REGS_H +#define __CA0132_REGS_H #define DSP_CHIP_OFFSET 0x100000 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30 -- 1.9.2

2 1

[alsa-devel] [PATCH v2] pcm: 2nd round of pcm_misc DSD fixes
by Jurgen Kramer 22 Aug '14

22 Aug '14

Functions 'snd_pcm_format_silence_64' and 'snd_pcm_format_size' also need to be able to handle the DSD smaple format. Changes from v1: - Correct silence pattern for DSD Signed-off-by: Jurgen Kramer <gtmkramer(a)xs4all.nl> --- src/pcm/pcm_misc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/pcm/pcm_misc.c b/src/pcm/pcm_misc.c index 24d52f9..46fc771 100644 --- a/src/pcm/pcm_misc.c +++ b/src/pcm/pcm_misc.c @@ -317,11 +317,13 @@ ssize_t snd_pcm_format_size(snd_pcm_format_t format, size_t samples) switch (format) { case SNDRV_PCM_FORMAT_S8: case SNDRV_PCM_FORMAT_U8: + case SNDRV_PCM_FORMAT_DSD_U8: return samples; case SNDRV_PCM_FORMAT_S16_LE: case SNDRV_PCM_FORMAT_S16_BE: case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_U16_BE: + case SNDRV_PCM_FORMAT_DSD_U16_LE: return samples * 2; case SNDRV_PCM_FORMAT_S18_3LE: case SNDRV_PCM_FORMAT_S18_3BE: @@ -390,6 +392,9 @@ u_int64_t snd_pcm_format_silence_64(snd_pcm_format_t format) return 0; case SNDRV_PCM_FORMAT_U8: return 0x8080808080808080ULL; + case SNDRV_PCM_FORMAT_DSD_U8: + case SNDRV_PCM_FORMAT_DSD_U16_LE: + return 0x6969696969696969ULL; #ifdef SNDRV_LITTLE_ENDIAN case SNDRV_PCM_FORMAT_U16_LE: return 0x8000800080008000ULL; -- 1.9.3

2 1

[alsa-devel] [PATCH 1/2] alsa-info: Make sure all full script is run even with "output" option
by David Henningsson 22 Aug '14

22 Aug '14

For some reason, when the --output option is used, less information is included compared to when no options are used. This is unexpected. Fix this by running "withall" also when the output option is used. Signed-off-by: David Henningsson <david.henningsson(a)canonical.com> --- alsa-info/alsa-info.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/alsa-info/alsa-info.sh b/alsa-info/alsa-info.sh index 859d7bc..47157f0 100755 --- a/alsa-info/alsa-info.sh +++ b/alsa-info/alsa-info.sh @@ -661,6 +661,7 @@ if [ -n "$1" ]; then shift NFILE="$1" KEEP_OUTPUT="yes" + withall ;; --debug) echo "Debugging enabled. $FILE and $TEMPDIR will not be deleted" -- 1.9.1

2 2

[alsa-devel] trouble using S/PDIF input on CMI8738-MC6: C-Media CMI8738 (model 55)
by jon 22 Aug '14

22 Aug '14

Greetings, I hope I have sent this email to the correct list, I apologize if I am in error. I have a somewhat antiquated motherboard (SOYO SY-K7V DRAGON Plus!) with an on-board soundcard using the cmipci driver. Audio playback through the analog output jacks works, as does audio capture from the analog line-in jack. I really would like to get either of the digital inputs to work for recording instead though (it has both optical and coaxial input *and* output jacks available on an optional breakout connector) however I have so far been unable to do so for either the coaxial or optical inputs even after having tested several different cables and external devices as audio sources. Neither recording nor the "monitor" feature of either digital inputs works. Unfortunately though I have no means by which to test the digital output other than to look into the end of a connected toslink cable and verify it indeed lights up. Initially I suspected my alsamixer settings were simply wrong, however after extensive testing and searching I have begun to suspect that the driver is simply not properly recognizing the optional (apparently somewhat rare) extra i/o expansion header. When I try to record from the digital input device, arecord outputs the status text, pauses for a few seconds and then spits out an i/o error. Below, in sections divided by the "####" bars I have included what I hope is enough relevant information for someone knowledgeable to help me troubleshoot/fix this issue. If information is missing I will happily provide it given instructions on how to find it. ######################################################################## Here is the arecord output: $ arecord -v -v -D hw:0,2 -f dat test.wav Recording WAVE 'test.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo Hardware PCM card 0 'C-Media CMI8738' device 2 subdevice 0 Its setup is: stream : CAPTURE access : RW_INTERLEAVED format : S16_LE subformat : STD channels : 2 rate : 48000 exact rate : 48000 (48000/1) msbits : 16 buffer_size : 16384 period_size : 4096 period_time : 85333 tstamp_mode : NONE period_step : 1 avail_min : 4096 period_event : 0 start_threshold : 1 stop_threshold : 16384 silence_threshold: 0 silence_size : 0 boundary : 1073741824 appl_ptr : 0 hw_ptr : 0 arecord: pcm_read:1801: read error: Input/output error ######################################################################## In case its relevant, here is the contents of the cmipci registry file before I run arecord: ~$ cat /proc/asound/card0/cmipci C-Media CMI8738 (model 55) at 0xd000, irq 11 00: 02 00 00 00 04: 12 e0 00 00 08: 0c 00 09 00 0c: 00 00 00 08 10: c0 00 00 00 14: 00 00 00 00 18: 00 01 81 0a 1c: ff ff ff ff 20: 10 40 08 00 24: 00 01 00 00 90: 20 09 00 10 And here is its contents while arecord is "hanging" - after I start the arecord command but before it spits out the i/o error then exits: $ cat /proc/asound/card0/cmipci C-Media CMI8738 (model 55) at 0xd000, irq 11 00: 02 00 02 00 04: 12 e2 00 00 08: 0c 00 09 00 0c: 00 00 02 08 10: c0 00 00 00 14: 00 00 00 00 18: 00 01 01 0a 1c: ff ff ff ff 20: 10 40 08 00 24: 00 01 00 00 90: 20 09 00 10 The second contents are the same as while its successfully recording from the analog input. After the i/o error it reverts to the previous contents, but the output is always a silent file of exactly 44 bytes which I assume to be the minimum size for an empty PCM WAV file. ######################################################################## And, last but not least, here is the output of the alsa-info.sh test script which I hope will contain everything else relevant. Note that While the current kernel is version 3.12 (vanilla) with both the "#if 0" lines in the cmipci.c file changed to "#if 1", the behavior as I have tested it is basically unchanged with the exception of the appearance of some more S/PDIF switches in alsamixer, and also unchanged from the stock wheezy 3.2 kernel. upload=true&script=true&cardinfo= !!################################ !!ALSA Information Script v 0.4.63 !!################################ !!Script ran on: Tue Aug 12 15:22:29 UTC 2014 !!Linux Distribution !!------------------ Debian GNU/Linux 7 \n \l PRETTY_NAME="Debian GNU/Linux 7 (wheezy)" NAME="Debian GNU/Linux" ID=debian HOME_URL="http://www.debian.org/" SUPPORT_URL="http://www.debian.org/support/" BUG_REPORT_URL="http://bugs.debian.org/" !!DMI Information !!--------------- Manufacturer: VIA Technologies, Inc. Product Name: VT8366-8233 Product Version: Firmware Version: 6.00 PG !!Kernel Information !!------------------ Kernel release: 3.12.0dionysus1 Operating System: GNU/Linux Architecture: i686 Processor: unknown SMP Enabled: No !!ALSA Version !!------------ Driver version: k3.12.0dionysus1 Library version: 1.0.25 Utilities version: 1.0.25 !!Loaded ALSA modules !!------------------- snd_cmipci !!Sound Servers on this system !!---------------------------- No sound servers found. !!Soundcards recognised by ALSA !!----------------------------- 0 [CMI8738 ]: CMI8738-MC6 - C-Media CMI8738 C-Media CMI8738 (model 55) at 0xd000, irq 11 !!PCI Soundcards installed in the system !!-------------------------------------- 00:0b.0 Multimedia video controller: Brooktree Corporation Bt848 Video Capture (rev 12) 00:0e.0 Multimedia audio controller: C-Media Electronics Inc CMI8738/CMI8768 PCI Audio (rev 10) !!Advanced information - PCI Vendor/Device/Subsystem ID's !!------------------------------------------------------- 00:0e.0 0401: 13f6:0111 (rev 10) Subsystem: 10fd:a701 !!Modprobe options (Sound related) !!-------------------------------- snd_pcsp: index=-2 snd_usb_audio: index=-2 snd_atiixp_modem: index=-2 snd_intel8x0m: index=-2 snd_via82xx_modem: index=-2 snd_cmipci: joystick_port=1 !!Loaded sound module options !!--------------------------- !!Module: snd_cmipci enable : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y fm_port : 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 id : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null) index : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 joystick_port : 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 mpu_port : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 soft_ac3 : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y !!ALSA Device nodes !!----------------- crw-rw---T 1 root audio 116, 9 Aug 12 07:33 /dev/snd/controlC0 crw-rw---T 1 root audio 116, 8 Aug 12 07:33 /dev/snd/hwC0D0 crw-rw---T 1 root audio 116, 2 Aug 12 07:33 /dev/snd/midiC0D0 crw-rw---T 1 root audio 116, 7 Aug 12 07:50 /dev/snd/pcmC0D0c crw-rw---T 1 root audio 116, 6 Aug 12 07:33 /dev/snd/pcmC0D0p crw-rw---T 1 root audio 116, 5 Aug 12 07:33 /dev/snd/pcmC0D1p crw-rw---T 1 root audio 116, 4 Aug 12 07:47 /dev/snd/pcmC0D2c crw-rw---T 1 root audio 116, 3 Aug 12 07:33 /dev/snd/pcmC0D2p crw-rw---T 1 root audio 116, 1 Aug 12 07:33 /dev/snd/seq crw-rw---T 1 root audio 116, 33 Aug 12 07:33 /dev/snd/timer /dev/snd/by-path: total 0 drwxr-xr-x 2 root root 60 Aug 12 07:33 . drwxr-xr-x 3 root root 260 Aug 12 07:33 .. lrwxrwxrwx 1 root root 12 Aug 12 07:33 pci-0000:00:0e.0 -> ../controlC0 !!Aplay/Arecord output !!-------------------- APLAY **** List of PLAYBACK Hardware Devices **** card 0: CMI8738 [C-Media CMI8738], device 0: CMI8738-MC6 [C-Media PCI DAC/ADC] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: CMI8738 [C-Media CMI8738], device 1: CMI8738-MC6 [C-Media PCI 2nd DAC] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: CMI8738 [C-Media CMI8738], device 2: CMI8738-MC6 [C-Media PCI IEC958] Subdevices: 1/1 Subdevice #0: subdevice #0 ARECORD **** List of CAPTURE Hardware Devices **** card 0: CMI8738 [C-Media CMI8738], device 0: CMI8738-MC6 [C-Media PCI DAC/ADC] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: CMI8738 [C-Media CMI8738], device 2: CMI8738-MC6 [C-Media PCI IEC958] Subdevices: 1/1 Subdevice #0: subdevice #0 !!Amixer output !!------------- !!-------Mixer controls for card 0 [CMI8738] Card hw:0 'CMI8738'/'C-Media CMI8738 (model 55) at 0xd000, irq 11' Mixer name : 'CMedia PCI' Components : '' Controls : 45 Simple ctrls : 25 Simple mixer control 'Master',0 Capabilities: pvolume penum Playback channels: Front Left - Front Right Limits: Playback 0 - 31 Mono: Front Left: Playback 31 [100%] Front Right: Playback 31 [100%] Simple mixer control '3D Control - Switch',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'PCM',0 Capabilities: pvolume pswitch pswitch-joined cswitch penum Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: Playback 0 - 31 Front Left: Playback 31 [100%] [on] Capture [off] Front Right: Playback 31 [100%] [on] Capture [off] Simple mixer control 'Synth',0 Capabilities: pvolume pswitch pswitch-joined cswitch penum Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: Playback 0 - 31 Front Left: Playback 26 [84%] [on] Capture [off] Front Right: Playback 26 [84%] [on] Capture [off] Simple mixer control 'Line',0 Capabilities: pvolume pswitch cswitch penum Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: Playback 0 - 31 Front Left: Playback 17 [55%] [on] Capture [on] Front Right: Playback 17 [55%] [on] Capture [on] Simple mixer control 'Line-In Mode',0 Capabilities: enum Items: 'Line-In' 'Rear Output' 'Bass Output' Item0: 'Line-In' Simple mixer control 'CD',0 Capabilities: pvolume pswitch cswitch penum Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: Playback 0 - 31 Front Left: Playback 0 [0%] [off] Capture [off] Front Right: Playback 0 [0%] [off] Capture [off] Simple mixer control 'Mic',0 Capabilities: pvolume pvolume-joined cvolume cvolume-joined pswitch pswitch-joined cswitch cswitch-joined penum Playback channels: Mono Capture channels: Mono Limits: Playback 0 - 31 Capture 0 - 7 Mono: Playback 0 [0%] [off] Capture 0 [0%] [off] Simple mixer control 'Mic Boost',0 Capabilities: pswitch pswitch-joined cswitch cswitch-joined penum Playback channels: Mono Capture channels: Mono Mono: Playback [off] Capture [off] Simple mixer control 'Mic-In Mode',0 Capabilities: enum Items: 'Mic-In' 'Center/LFE Output' Item0: 'Mic-In' Simple mixer control 'Phone',0 Capabilities: pvolume pvolume-joined pswitch pswitch-joined penum Playback channels: Mono Limits: Playback 0 - 7 Mono: Playback 0 [0%] [off] Simple mixer control 'IEC958 5V',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 Copyright',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 In Monitor',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 In Phase Inverse',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 In Record',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 In Select',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [on] Simple mixer control 'IEC958 In Valid',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 Loop',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 Out',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 Out To DAC',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'IEC958 Output',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] Simple mixer control 'Beep',0 Capabilities: pvolume pvolume-joined pswitch pswitch-joined penum Playback channels: Mono Limits: Playback 0 - 3 Mono: Playback 1 [33%] [on] Simple mixer control 'Aux',0 Capabilities: pvolume pswitch cswitch penum Playback channels: Front Left - Front Right Capture channels: Front Left - Front Right Limits: Playback 0 - 15 Front Left: Playback 0 [0%] [off] Capture [off] Front Right: Playback 0 [0%] [off] Capture [off] Simple mixer control 'Four Channel Mode',0 Capabilities: pswitch pswitch-joined penum Playback channels: Mono Mono: Playback [off] !!Alsactl output !!-------------- --startcollapse-- state.CMI8738 { control.1 { iface PCM device 2 name 'Playback Channel Map' value.0 0 value.1 0 value.2 0 value.3 0 value.4 0 value.5 0 comment { access read type INTEGER count 6 range '0 - 36' } } control.2 { iface MIXER name 'Master Playback Volume' value.0 31 value.1 31 comment { access 'read write' type INTEGER count 2 range '0 - 31' } } control.3 { iface MIXER name '3D Control - Switch' value false comment { access 'read write' type BOOLEAN count 1 } } control.4 { iface MIXER name 'PCM Playback Volume' value.0 31 value.1 31 comment { access 'read write' type INTEGER count 2 range '0 - 31' } } control.5 { iface MIXER name 'PCM Playback Switch' value true comment { access 'read write' type BOOLEAN count 1 } } control.6 { iface MIXER name 'PCM Capture Switch' value.0 false value.1 false comment { access 'read write' type BOOLEAN count 2 } } control.7 { iface MIXER name 'Synth Playback Volume' value.0 26 value.1 26 comment { access 'read write' type INTEGER count 2 range '0 - 31' } } control.8 { iface MIXER name 'Synth Playback Switch' value true comment { access 'read write' type BOOLEAN count 1 } } control.9 { iface MIXER name 'Synth Capture Route' value.0 false value.1 false value.2 false value.3 false comment { access 'read write' type BOOLEAN count 4 } } control.10 { iface MIXER name 'CD Playback Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 31' } } control.11 { iface MIXER name 'CD Playback Switch' value.0 false value.1 false comment { access 'read write' type BOOLEAN count 2 } } control.12 { iface MIXER name 'CD Capture Route' value.0 false value.1 false value.2 false value.3 false comment { access 'read write' type BOOLEAN count 4 } } control.13 { iface MIXER name 'Line Playback Volume' value.0 17 value.1 17 comment { access 'read write' type INTEGER count 2 range '0 - 31' } } control.14 { iface MIXER name 'Line Playback Switch' value.0 true value.1 true comment { access 'read write' type BOOLEAN count 2 } } control.15 { iface MIXER name 'Line Capture Route' value.0 true value.1 false value.2 false value.3 true comment { access 'read write' type BOOLEAN count 4 } } control.16 { iface MIXER name 'Mic Playback Volume' value 0 comment { access 'read write' type INTEGER count 1 range '0 - 31' } } control.17 { iface MIXER name 'Mic Playback Switch' value false comment { access 'read write' type BOOLEAN count 1 } } control.18 { iface MIXER name 'Mic Capture Switch' value false comment { access 'read write' type BOOLEAN count 1 } } control.19 { iface MIXER name 'Beep Playback Volume' value 1 comment { access 'read write' type INTEGER count 1 range '0 - 3' } } control.20 { iface MIXER name 'Aux Playback Volume' value.0 0 value.1 0 comment { access 'read write' type INTEGER count 2 range '0 - 15' } } control.21 { iface MIXER name 'Aux Playback Switch' value.0 false value.1 false comment { access 'read write' type BOOLEAN count 2 } } control.22 { iface MIXER name 'Aux Capture Switch' value.0 false value.1 false comment { access 'read write' type BOOLEAN count 2 } } control.23 { iface MIXER name 'Mic Boost Playback Switch' value false comment { access 'read write' type BOOLEAN count 1 } } control.24 { iface MIXER name 'Mic Capture Volume' value 0 comment { access 'read write' type INTEGER count 1 range '0 - 7' } } control.25 { iface MIXER name 'Phone Playback Volume' value 0 comment { access 'read write' type INTEGER count 1 range '0 - 7' } } control.26 { iface MIXER name 'Phone Playback Switch' value false comment { access 'read write' type BOOLEAN count 1 } } control.27 { iface MIXER name 'Beep Playback Switch' value true comment { access 'read write' type BOOLEAN count 1 } } control.28 { iface MIXER name 'Mic Boost Capture Switch' value false comment { access 'read write' type BOOLEAN count 1 } } control.29 { iface MIXER name 'Four Channel Mode' value false comment { access 'read write' type BOOLEAN count 1 } } control.30 { iface MIXER name 'Line-In Mode' value Line-In comment { access 'read write' type ENUMERATED count 1 item.0 Line-In item.1 'Rear Output' item.2 'Bass Output' } } control.31 { iface MIXER name 'IEC958 In Record' value false comment { access 'read write' type BOOLEAN count 1 } } control.32 { iface MIXER name 'IEC958 Out' value false comment { access 'read write' type BOOLEAN count 1 } } control.33 { iface MIXER name 'IEC958 Out To DAC' value false comment { access 'read write' type BOOLEAN count 1 } } control.34 { iface MIXER name 'IEC958 Output Switch' value false comment { access 'read write' type BOOLEAN count 1 } } control.35 { iface MIXER name 'IEC958 In Valid' value false comment { access 'read write' type BOOLEAN count 1 } } control.36 { iface MIXER name 'IEC958 Copyright' value false comment { access 'read write' type BOOLEAN count 1 } } control.37 { iface MIXER name 'IEC958 5V' value false comment { access 'read write' type BOOLEAN count 1 } } control.38 { iface MIXER name 'IEC958 Loop' value false comment { access 'read write' type BOOLEAN count 1 } } control.39 { iface MIXER name 'IEC958 In Monitor' value false comment { access 'read write' type BOOLEAN count 1 } } control.40 { iface PCM device 2 name 'IEC958 Playback Default' value '0082000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access 'read write' type IEC958 count 1 } } control.41 { iface PCM device 2 name 'IEC958 Playback Con Mask' value ffffffff00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 comment { access read type IEC958 count 1 } } control.42 { iface PCM device 2 name 'IEC958 Playback PCM Stream' value '0082000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' comment { access 'read write inactive' type IEC958 count 1 } } control.43 { iface MIXER name 'IEC958 In Select' value true comment { access 'read write' type BOOLEAN count 1 } } control.44 { iface MIXER name 'IEC958 In Phase Inverse' value false comment { access 'read write' type BOOLEAN count 1 } } control.45 { iface MIXER name 'Mic-In Mode' value Mic-In comment { access 'read write' type ENUMERATED count 1 item.0 Mic-In item.1 'Center/LFE Output' } } } --endcollapse-- !!All Loaded Modules !!------------------ Module fuse nfsd auth_rpcgss oid_registry nfs_acl nfs lockd fscache sunrpc reiserfs it87 hwmon_vid snd_pcm_oss snd_mixer_oss analog ns558 loop tuner_simple tuner_types tuner tda7432 tvaudio snd_cmipci snd_mpu401_uart snd_opl3_lib snd_hwdep snd_pcm snd_page_alloc msp3400 bttv snd_seq_midi snd_seq_midi_event tveeprom btcx_risc videobuf_dma_sg snd_rawmidi videobuf_core nouveau i2c_viapro via_ircc rc_core video mxm_wmi snd_seq snd_timer snd_seq_device v4l2_common wmi snd soundcore ttm videodev drm_kms_helper drm psmouse serio_raw evdev joydev pcspkr processor media i2c_algo_bit i2c_core thermal_sys gameport irda button crc_ccitt ext4 crc16 jbd2 mbcache sd_mod sg sr_mod cdrom crc_t10dif crct10dif_common ata_generic hid_generic usbhid hid pata_via libata uhci_hcd ehci_hcd via_rhine mii scsi_mod usbcore usb_common !!ALSA/HDA dmesg !!--------------

2 6

[alsa-devel] /proc/asound/card0/oss_mixer stack corruption
by Tommi Rantala 22 Aug '14

22 Aug '14

Hello, Trinity discovered that writing 128 bytes to /proc/asound/card0/oss_mixer triggers a stack corruption. Tommi # printf %128s > /proc/asound/card0/oss_mixer ALSA: mixer_oss: invalid OSS volume '' Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in: ffffffff81e193ba CPU: 0 PID: 2778 Comm: bash Not tainted 3.17.0-rc1+ #13 Hardware name: Bochs Bochs, BIOS Bochs 01/01/2011 ffff880039fd4bf0 ffff880034c87bd8 ffffffff8229824a ffffffff828e2a40 ffff880034c87c50 ffffffff8229051d ffff880000000010 ffff880034c87c60 ffff880034c87c00 0000000000000020 ffffffff81e193ba 0000000000000080 Call Trace: [<ffffffff8229824a>] dump_stack+0x4d/0x66 [<ffffffff8229051d>] panic+0xc8/0x201 [<ffffffff81e193ba>] ? snd_mixer_oss_proc_write+0x24a/0x270 [<ffffffff8113c716>] __stack_chk_fail+0x16/0x20 [<ffffffff81e193ba>] snd_mixer_oss_proc_write+0x24a/0x270 [<ffffffff810a8a27>] ? kvm_clock_read+0x27/0x40 [<ffffffff81dfb54c>] snd_info_entry_release+0x6c/0x110 [<ffffffff812e9af6>] close_pdeo+0x136/0x1a0 [<ffffffff8118bec1>] ? __lock_acquire+0x951/0xb40 [<ffffffff810a8a27>] ? kvm_clock_read+0x27/0x40 [<ffffffff812e9b9e>] proc_reg_release+0x3e/0x60 [<ffffffff8127fa41>] __fput+0x111/0x1e0 [<ffffffff8127fb59>] ____fput+0x9/0x10 [<ffffffff8115e3ee>] task_work_run+0x9e/0xd0 [<ffffffff8106aaa5>] do_notify_resume+0x55/0x70 [<ffffffff822b12e2>] int_signal+0x12/0x17 Kernel Offset: 0x0 from 0xffffffff81000000 (relocation range: 0xffffffff80000000-0xffffffff9fffffff)

3 2

[alsa-devel] usb-usx2y: playback fails with Tascam US122 on kernel 3.14
by Dr Nicholas J Bailey 21 Aug '14

21 Aug '14

I am having trouble with the US122 in playback and duplex mode. In capture mode, it is working. This problem occurs on (at least) Linux arial 3.14-1-686-pae #1 SMP Debian 3.14.7-1 (2014-06-16) i686 GNU/Linux I note that my computer uses the much-maligned Intel Corporation 5 Series/3400 chipset (rev 05), but I have a UK£12 5.1 out/2.0 in audio adaptor which works in either capture or playback (although not in duplex). Also, booting an old kernel: Linux arial 3.2.0-4-686-pae #1 SMP Debian 3.2.57-3+deb7u2 i686 GNU/Linux or Linux arial 3.10.11 #1 SMP Wed Oct 2 19:26:59 BST 2013 i686 GNU/Linux both seem to support full duplex operation. This is therefore a regression between 3.10.11 and 3.14-1 (at least, something on my system has regressed and I am suspecting the usx2y module). dmesg tells me: [ 2873.134973] usb 2-1.6: new full-speed USB device number 9 using ehci-pci [ 2873.228117] usb 2-1.6: New USB device found, idVendor=1604, idProduct=8006 [ 2873.228122] usb 2-1.6: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2873.447646] usb 2-1.6: USB disconnect, device number 9 [ 2875.183348] usb 2-1.6: new full-speed USB device number 10 using ehci-pci [ 2875.277235] usb 2-1.6: New USB device found, idVendor=1604, idProduct=8007 [ 2875.277240] usb 2-1.6: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2877.844821] cannot submit datapipe for urb 0, err = -28 ... this message repeated many times ... [ 2877.912388] cannot submit datapipe for urb 0, err = -28 [ 3528.609688] active frame status -18. Most probably some hardware problem. I used to use these interfaces with jack in duplex mode, but this is no longer possible. Running up audacity for a test, capture from the US122 works fine, but once the US122 is selected for playback, audacity pops up an "Error opening sound device". Further attempts to record (even capture-only) result in corrupted, high-amplitude noise. Nick/. Other info which might help (a bit noisy, because I'm not sure exactly what's wrong) follows. Using aplay with --dump-hw-parameters: Under kernel 3.14-1: HW Params of device "hw:USX2Y": -------------------- ACCESS: MMAP_INTERLEAVED RW_INTERLEAVED FORMAT: S16_LE S24_3LE SUBFORMAT: STD SAMPLE_BITS: [16 24] FRAME_BITS: [32 48] CHANNELS: 2 RATE: [44100 48000] PERIOD_TIME: [1000 185760) PERIOD_SIZE: [45 8192] PERIOD_BYTES: [180 49152] PERIODS: [2 365) BUFFER_TIME: [1875 371520) BUFFER_SIZE: [90 16384] BUFFER_BYTES: [360 65536] TICK_TIME: ALL -------------------- aplay: set_params:1297: Unable to install hw params: ACCESS: RW_INTERLEAVED FORMAT: S16_LE SUBFORMAT: STD SAMPLE_BITS: 16 FRAME_BITS: 32 CHANNELS: 2 RATE: 44100 PERIOD_TIME: (92879 92880) PERIOD_SIZE: 4096 PERIOD_BYTES: 16384 PERIODS: 4 BUFFER_TIME: (371519 371520) BUFFER_SIZE: 16384 BUFFER_BYTES: 65536 TICK_TIME: 0 Using kernel 3.10.11: HW Params of device "hw:USX2Y": -------------------- ACCESS: MMAP_INTERLEAVED RW_INTERLEAVED FORMAT: S16_LE S24_3LE SUBFORMAT: STD SAMPLE_BITS: [16 24] FRAME_BITS: [32 48] CHANNELS: 2 RATE: [44100 48000] PERIOD_TIME: [1000 185760) PERIOD_SIZE: [45 8192] PERIOD_BYTES: [180 49152] PERIODS: [2 365) BUFFER_TIME: [1875 371520) BUFFER_SIZE: [90 16384] BUFFER_BYTES: [360 65536] TICK_TIME: ALL -------------------- (plays OK) Error log when running jackd from qjackctl on the 3.14 kernel: 15:22:31.126 Patchbay deactivated. 15:22:31.165 Statistics reset. 15:22:31.295 ALSA connection change. 15:22:33.840 D-BUS: Service is available (org.jackaudio.service aka jackdbus). Cannot connect to server socket err = No such file or directory Cannot connect to server request channel jack server is not running or cannot be started 15:22:43.516 D-BUS: JACK server could not be started. Sorry Cannot connect to server socket err = No such file or directory Cannot connect to server request channel jack server is not running or cannot be started Thu Jun 26 15:22:43 2014: Starting jack server... Thu Jun 26 15:22:43 2014: JACK server starting in non-realtime mode Thu Jun 26 15:22:43 2014: self-connect-mode is "Don't restrict self connect requests" Thu Jun 26 15:22:43 2014: Acquired audio card Audio1 Thu Jun 26 15:22:43 2014: creating alsa driver ... hw:USX2Y|hw:USX2Y|1024|3| 48000|0|0|nomon|swmeter|-|16bit Thu Jun 26 15:22:43 2014: configuring for 48000Hz, period = 1024 frames (21.3 ms), buffer = 3 periods Thu Jun 26 15:22:43 2014: ALSA: final selected sample format for capture: 16bit little-endian Thu Jun 26 15:22:43 2014: ALSA: use 3 periods for capture Thu Jun 26 15:22:43 2014: ALSA: final selected sample format for playback: 16bit little-endian Thu Jun 26 15:22:43 2014: ALSA: use 3 periods for playback Thu Jun 26 15:22:43 2014: ERROR: ALSA: cannot set hardware parameters for playback Thu Jun 26 15:22:43 2014: ERROR: ALSA: cannot configure playback channel Thu Jun 26 15:22:43 2014: ERROR: Cannot initialize driver Thu Jun 26 15:22:43 2014: ERROR: JackServer::Open failed with -1 Thu Jun 26 15:22:43 2014: ERROR: Failed to open server Thu Jun 26 15:22:44 2014: Saving settings to "/home/nick/.config/jack/conf.xml" ... 15:23:00.574 Could not connect to JACK server as client. - Overall operation failed. - Unable to connect to server. Please check the messages window for more info. Cannot connect to server socket err = No such file or directory Cannot connect to server request channel jack server is not running or cannot be started nick@arial:~$ cat .jackdrc /usr/bin/jackd -r -m -dalsa -dhw:USX2Y -r48000 -p1024 -n3 -S nick@arial:~$ cat .config/jack/conf.xml <?xml version="1.0"?>   <jack> <engine> <option name="driver">alsa</option> <option name="realtime">false</option> <option name="verbose">false</option> <option name="client-timeout">500</option> </engine> <drivers> <driver name="net"> </driver> <driver name="alsarawmidi"> </driver> <driver name="loopback"> </driver> <driver name="firewire"> <option name="period">512</option> <option name="nperiods">3</option> <option name="rate">48000</option> <option name="duplex">true</option> </driver> <driver name="netone"> </driver> <driver name="alsa"> <option name="device">hw:USX2Y</option> <option name="capture">hw:USX2Y</option> <option name="playback">hw:USX2Y</option> <option name="rate">48000</option> <option name="period">1024</option> <option name="nperiods">3</option> <option name="hwmon">false</option> <option name="hwmeter">false</option> <option name="duplex">true</option> <option name="softmode">false</option> <option name="monitor">false</option> <option name="dither">n</option> <option name="shorts">true</option> </driver> <driver name="dummy"> </driver> </drivers> <internals> <internal name="audioadapter"> </internal> <internal name="profiler"> </internal> <internal name="netadapter"> </internal> <internal name="netmanager"> </internal> </internals> </jack>

3 8

[alsa-devel] can't insmod patched snd-usb-audio
by Orm Finnendahl 21 Aug '14

21 Aug '14

Hi, hope it's ok to post it here as it's not (yet) official alsa: After having no issues with Tobias Hoffmann's scarlett alsa mixer patch on my older kernels, trying to insmod the patched kernel modules on my most current kernel (the patch and documentation obtained with "git clone http://github.com/trrichard/alsa-driver_scarlett.git") fails with the following message: root@x1-orm:/usr/src/linux-source-3.14# insmod sound/usb/snd-usbmidi-lib.ko insmod: ERROR: could not insert module sound/usb/snd-usbmidi-lib.ko: Unknown symbol in module root@x1-orm:/usr/src/linux-source-3.14# insmod sound/usb/snd-usb-audio.ko insmod: ERROR: could not insert module sound/usb/snd-usb-audio.ko: Unknown symbol in module I'm on debian testing with 3.14-2-amd64 kernel and followed all the instructions in the scarlett kernel patch README (I tried three times each with a fresh kernel source tree from scratch to be sure). The patch has worked for me on older kernels without any problems. Does anybody know how to deal with this? Let me know if you need further information. Yours, Orm

3 3

[alsa-devel] ALSA - Channel swap
by Tomas Matejka 20 Aug '14

20 Aug '14

Good afternoon, i have a problem: I use sound codec CS4202, which I control with AT91SAM9263. I'm using ALSA sound library. When i use CAPTURE mode, sometimes it swaps left and right channel. I have found this discussions on Internet, where is described similar problem: http://pl.it-usenet.org/thread/17996/3593/ http://sinustrom.info/2013/03/21/atmel-soc-ssc-channel-swapping/ I have figured out, that the problem could be in driver or in ALSA library. Have you any solution ? Did you encountered similar problem ?

2 4

[alsa-devel] buffer time
by Joël Krähemann 20 Aug '14

20 Aug '14

What's the correct buffer time to use with alsa? since I have following in ags.sf.net buffer size: 940 alsa iterations: 47 per second Since I don't have segmentation of tact in my application BPM is the only scale I got really slow output. Further can't run anymore with realtime priorities. I would prefer using 940 because its near a good throughput rate. Years ago I calculated it the exact value would be something 93.whatever Please help best regards Joël

3 4

[alsa-devel] [PATCH 1/2] ASoC: sh: Don't opencode DMAengine API calls
by Lars-Peter Clausen 19 Aug '14

19 Aug '14

Use the proper wrapper functions instead of directly calling the DMAengine callback functions. Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> --- sound/soc/sh/siu_pcm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/sh/siu_pcm.c b/sound/soc/sh/siu_pcm.c index 488f9be..32eb6da 100644 --- a/sound/soc/sh/siu_pcm.c +++ b/sound/soc/sh/siu_pcm.c @@ -139,7 +139,7 @@ static int siu_pcm_wr_set(struct siu_port *port_info, desc->callback = siu_dma_tx_complete; desc->callback_param = siu_stream; - cookie = desc->tx_submit(desc); + cookie = dmaengine_submit(desc); if (cookie < 0) { dev_err(dev, "Failed to submit a dma transfer\n"); return cookie; @@ -189,7 +189,7 @@ static int siu_pcm_rd_set(struct siu_port *port_info, desc->callback = siu_dma_tx_complete; desc->callback_param = siu_stream; - cookie = desc->tx_submit(desc); + cookie = dmaengine_submit(desc); if (cookie < 0) { dev_err(dev, "Failed to submit dma descriptor\n"); return cookie; -- 1.8.0

2 3

[alsa-devel] [PATCH V2] ASoC: fsl-asoc-card: move 'config SND_SOC_FSL_ASOC_CARD' to 'if SND_IMX_SOC'
by Shengjiu Wang 19 Aug '14

19 Aug '14

Build kernel with SND_SOC_FSL_ASOC_CARD=m && SND_SOC_FSL_{SSI,SAI,ESAI}=y leads the following error: sound/built-in.o: In function `fsl_sai_probe': >> fsl_sai.c:(.text+0x5f662): undefined reference to `imx_pcm_dma_init' sound/built-in.o: In function `fsl_esai_probe': >> fsl_esai.c:(.text+0x6044b): undefined reference to `imx_pcm_dma_init' The config SND_SOC_FSL_ASOC_CARD is for IMX SOC, So move it under condition of 'if SND_IMX_SOC'. Reported-by: kbuild test robot <fengguang.wu(a)intel.com> Signed-off-by: Shengjiu Wang <shengjiu.wang(a)freescale.com> --- sound/soc/fsl/Kconfig | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 417ff70..9348fef 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -58,23 +58,6 @@ config SND_SOC_FSL_ESAI config SND_SOC_FSL_UTILS tristate -config SND_SOC_FSL_ASOC_CARD - tristate "Generic ASoC Sound Card with ASRC support" - depends on OF && I2C - select SND_SOC_IMX_AUDMUX - select SND_SOC_IMX_PCM_DMA - select SND_SOC_FSL_ESAI - select SND_SOC_FSL_SAI - select SND_SOC_FSL_SSI - select SND_SOC_CS42XX8_I2C - select SND_SOC_SGTL5000 - select SND_SOC_WM8962 - help - ALSA SoC Audio support with ASRC feature for Freescale SoCs that have - ESAI/SAI/SSI and connect with external CODECs such as WM8962, CS42888 - and SGTL5000. - Say Y if you want to add support for Freescale Generic ASoC Sound Card. - config SND_SOC_IMX_PCM_DMA tristate select SND_SOC_GENERIC_DMAENGINE_PCM @@ -285,6 +268,23 @@ config SND_SOC_IMX_MC13783 select SND_SOC_MC13783 select SND_SOC_IMX_PCM_DMA +config SND_SOC_FSL_ASOC_CARD + tristate "Generic ASoC Sound Card with ASRC support" + depends on OF && I2C + select SND_SOC_IMX_AUDMUX + select SND_SOC_IMX_PCM_DMA + select SND_SOC_FSL_ESAI + select SND_SOC_FSL_SAI + select SND_SOC_FSL_SSI + select SND_SOC_CS42XX8_I2C + select SND_SOC_SGTL5000 + select SND_SOC_WM8962 + help + ALSA SoC Audio support with ASRC feature for Freescale SoCs that have + ESAI/SAI/SSI and connect with external CODECs such as WM8962, CS42888 + and SGTL5000. + Say Y if you want to add support for Freescale Generic ASoC Sound Card. + endif # SND_IMX_SOC endmenu -- 1.7.9.5

2 1

Re: [alsa-devel] [v4 10/12] ASoC: Intel: mrfld: add the DSP DAPM widgets
by Mark Brown 19 Aug '14

19 Aug '14

On Tue, Aug 19, 2014 at 09:57:11AM +0530, Subhransu S. Prusty wrote: > On Mon, Aug 18, 2014 at 08:56:33AM -0500, Mark Brown wrote: > > The problem is that it looks like you are reading the value from the > > control, treating it as a boolean and discarding it. > Well the mixer input is on/off, so it should be treated as boolean. How will > it have any other value. OK, so you're trying to read a boolean value. Perhaps what you need here is some comments then - the way you fiddle about with the bitmasks afterwards doesn't make it sufficient obvious.

1 0

[alsa-devel] [v2 0/5] ASoC: Intel: sst - add the merrifield DSP driver
by Subhransu S. Prusty 19 Aug '14

19 Aug '14

This path series add the Merrifield DSP driver which is used to load and managed the DSP along with sending and receiving IPCs for PCM and compressed audio. Changes in v2: * Now download fw during device resume * Removed runtime reference counting from driver context * Using dedicated functions instead ioctl * Addressed review comments Subhransu S. Prusty (1): ASoC: mfld-compress: Use dedicated function instead of ioctl Vinod Koul (4): ASoC: Intel: mrfld - add the dsp sst driver ASoC: Intel: sst: add power management handling ASoC: Intel: sst: load firmware using async callback ASoC: Intel: sst - add compressed ops handling arch/x86/include/asm/platform_sst_audio.h | 33 + sound/soc/intel/Kconfig | 4 + sound/soc/intel/Makefile | 3 + sound/soc/intel/sst-mfld-platform-compress.c | 38 +- sound/soc/intel/sst-mfld-platform.h | 27 +- sound/soc/intel/sst/Makefile | 3 + sound/soc/intel/sst/sst.c | 576 ++++++++++++++++ sound/soc/intel/sst/sst.h | 654 ++++++++++++++++++ sound/soc/intel/sst/sst_drv_interface.c | 773 +++++++++++++++++++++ sound/soc/intel/sst/sst_ipc.c | 373 ++++++++++ sound/soc/intel/sst/sst_loader.c | 975 +++++++++++++++++++++++++++ sound/soc/intel/sst/sst_pvt.c | 207 ++++++ sound/soc/intel/sst/sst_stream.c | 526 +++++++++++++++ 13 files changed, 4173 insertions(+), 19 deletions(-) create mode 100644 sound/soc/intel/sst/Makefile create mode 100644 sound/soc/intel/sst/sst.c create mode 100644 sound/soc/intel/sst/sst.h create mode 100644 sound/soc/intel/sst/sst_drv_interface.c create mode 100644 sound/soc/intel/sst/sst_ipc.c create mode 100644 sound/soc/intel/sst/sst_loader.c create mode 100644 sound/soc/intel/sst/sst_pvt.c create mode 100644 sound/soc/intel/sst/sst_stream.c -- 1.9.0

3 7

[alsa-devel] [PATCH 00/13] ASoC: Componentization: Unified probe/remove path
by Lars-Peter Clausen 19 Aug '14

19 Aug '14

This patch-set starts with consolidating the probe and remove paths of snd_soc_codec and snd_soc_platform drivers. Once that has been done it uses the new generic paths to also add probe and remove support to snd_soc_component drivers. With that in place the AUX dev handling is then moved to the component layer as there is no longer any snd_soc_codec specifics required to handle them. The later patches in the series deal with cleaning things up and consolidating a few code paths between CPU and CODEC DAI handling. After this patch-set the core of the ASoC core is now fully componentized and doesn't care anymore (except for one small hack which is documented in the commit) about whether something is a snd_soc_codec, snd_soc_platform or snd_soc_component. This does unfortunately not mean that componentization is done yet. There are still a few things left to do. This includes bringing more things to the component level for example clock and PCM handling. There is also still the issue that we handle CPU DAIs and CODEC DAIs differently. For CODEC DAIs the capture stream is output and the playback stream is input while it is the other way around for CPU DAIs. Also we expect them to handle the SND_SOC_DAIFMT_CBx_CFx settings depending on whether they are a CPU or CODEC DAI. So we need a way to distinguish between the two. At this point it is already possible though to convert simple snd_soc_codec drivers that don't need any of this (e.g. some of the external amplifier drivers) to snd_soc_components. Since the series adds a centralized path for probing and removing it also paves the way towards easier integration of the drivers/base/component.c framework, which in turn will allow some cleanups and to fix some long standing bugs in the way hot-unplug is handled (or rather not handled). - Lars Lars-Peter Clausen (13): ASoC: Move debugfs registration to the component level ASoC: Consolidate platform and CODEC probe/remove ASoC: Make rtd->codec optional ASoC: Add component level probe/remove support ASoC: Move AUX dev support to the component level ASoC: Pass component instead of DAPM context to AUX dev init callback ASoC: Move component->probed check into soc_{remove,probe}_component() ASoC: Cleanup DAI module reference counting ASoC: Consolidate CPU and CODEC DAI removal ASoC: Consolidate CPU and CODEC DAI look-up ASoC: Automatically initialize regmap for all components ASoC: Remove support for legacy snd_soc_platform IO ASoC: Replace list_empty(&card->codec_dev_list) with !card->instantiated include/sound/soc.h | 67 ++-- sound/soc/samsung/speyside.c | 6 +- sound/soc/soc-core.c | 667 ++++++++++++++++------------------ sound/soc/soc-generic-dmaengine-pcm.c | 4 +- sound/soc/soc-io.c | 28 -- 5 files changed, 357 insertions(+), 415 deletions(-) -- 1.8.0

2 14

[alsa-devel] [PATCH] ASoC: fsl: Fix building of imx-es8328 on PPC
by Sean Cross 19 Aug '14

19 Aug '14

The imx-es8328 driver fails to build on PPC because it explicitly depends on SND_SOC_IMX_PCM_FIQ, which itself doesn't build on PPC. Instead, rely on the SND_SOC_FSL_SSI config option to pull in the necessary libraries. While we're at it, remove SND_SOC_FSL_UTILS, which also is not needed. Signed-off-by: Sean Cross <xobs(a)kosagi.com> --- sound/soc/fsl/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index c0ace69..13199b5 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -237,8 +237,6 @@ config SND_SOC_IMX_ES8328 select SND_SOC_IMX_PCM_DMA select SND_SOC_IMX_AUDMUX select SND_SOC_FSL_SSI - select SND_SOC_FSL_UTILS - select SND_SOC_IMX_PCM_FIQ help Say Y if you want to add support for the ES8328 audio codec connected via SSI/I2S over either SPI or I2C. -- 2.0.0

2 1

[alsa-devel] [PATCH 1/2] usbtv: split core and video implementation
by Federico Simoncelli 19 Aug '14

19 Aug '14

From: Federico Simoncelli <fsimonce(a)redhat.com> Signed-off-by: Federico Simoncelli <fsimonce(a)redhat.com> Reviewed-by: Lubomir Rintel <lkundrak(a)v3.sk> --- drivers/media/usb/usbtv/Makefile | 3 + drivers/media/usb/usbtv/usbtv-core.c | 136 +++++++++++++++++ drivers/media/usb/usbtv/{usbtv.c => usbtv-video.c} | 163 ++------------------- drivers/media/usb/usbtv/usbtv.h | 98 +++++++++++++ 4 files changed, 246 insertions(+), 154 deletions(-) create mode 100644 drivers/media/usb/usbtv/usbtv-core.c rename drivers/media/usb/usbtv/{usbtv.c => usbtv-video.c} (82%) create mode 100644 drivers/media/usb/usbtv/usbtv.h diff --git a/drivers/media/usb/usbtv/Makefile b/drivers/media/usb/usbtv/Makefile index 28b872f..775316a 100644 --- a/drivers/media/usb/usbtv/Makefile +++ b/drivers/media/usb/usbtv/Makefile @@ -1 +1,4 @@ +usbtv-y := usbtv-core.o \ + usbtv-video.o + obj-$(CONFIG_VIDEO_USBTV) += usbtv.o diff --git a/drivers/media/usb/usbtv/usbtv-core.c b/drivers/media/usb/usbtv/usbtv-core.c new file mode 100644 index 0000000..e89e48b --- /dev/null +++ b/drivers/media/usb/usbtv/usbtv-core.c @@ -0,0 +1,136 @@ +/* + * Fushicai USBTV007 Video Grabber Driver + * + * Product web site: + * http://www.fushicai.com/products_detail/&productId=d05449ee-b690-42f9-a661-… + * + * Following LWN articles were very useful in construction of this driver: + * Video4Linux2 API series: http://lwn.net/Articles/203924/ + * videobuf2 API explanation: http://lwn.net/Articles/447435/ + * Thanks go to Jonathan Corbet for providing this quality documentation. + * He is awesome. + * + * Copyright (c) 2013 Lubomir Rintel + * All rights reserved. + * No physical hardware was harmed running Windows during the + * reverse-engineering activity + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL"). + */ + +#include <linux/module.h> + +#include "usbtv.h" + +int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size) +{ + int ret; + int pipe = usb_rcvctrlpipe(usbtv->udev, 0); + int i; + + for (i = 0; i < size; i++) { + u16 index = regs[i][0]; + u16 value = regs[i][1]; + + ret = usb_control_msg(usbtv->udev, pipe, USBTV_REQUEST_REG, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + value, index, NULL, 0, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int usbtv_probe(struct usb_interface *intf, + const struct usb_device_id *id) +{ + int ret; + int size; + struct device *dev = &intf->dev; + struct usbtv *usbtv; + + /* Checks that the device is what we think it is. */ + if (intf->num_altsetting != 2) + return -ENODEV; + if (intf->altsetting[1].desc.bNumEndpoints != 4) + return -ENODEV; + + /* Packet size is split into 11 bits of base size and count of + * extra multiplies of it.*/ + size = usb_endpoint_maxp(&intf->altsetting[1].endpoint[0].desc); + size = (size & 0x07ff) * (((size & 0x1800) >> 11) + 1); + + /* Device structure */ + usbtv = kzalloc(sizeof(struct usbtv), GFP_KERNEL); + if (usbtv == NULL) + return -ENOMEM; + usbtv->dev = dev; + usbtv->udev = usb_get_dev(interface_to_usbdev(intf)); + + usbtv->iso_size = size; + + usb_set_intfdata(intf, usbtv); + + ret = usbtv_video_init(usbtv); + if (ret < 0) + goto usbtv_video_fail; + + /* for simplicity we exploit the v4l2_device reference counting */ + v4l2_device_get(&usbtv->v4l2_dev); + + dev_info(dev, "Fushicai USBTV007 Video Grabber\n"); + return 0; + +usbtv_video_fail: + kfree(usbtv); + + return ret; +} + +static void usbtv_disconnect(struct usb_interface *intf) +{ + struct usbtv *usbtv = usb_get_intfdata(intf); + usb_set_intfdata(intf, NULL); + + if (!usbtv) + return; + + usbtv_video_free(usbtv); + + usb_put_dev(usbtv->udev); + usbtv->udev = NULL; + + /* the usbtv structure will be deallocated when v4l2 will be + done using it */ + v4l2_device_put(&usbtv->v4l2_dev); +} + +struct usb_device_id usbtv_id_table[] = { + { USB_DEVICE(0x1b71, 0x3002) }, + {} +}; +MODULE_DEVICE_TABLE(usb, usbtv_id_table); + +MODULE_AUTHOR("Lubomir Rintel"); +MODULE_DESCRIPTION("Fushicai USBTV007 Video Grabber Driver"); +MODULE_LICENSE("Dual BSD/GPL"); + +struct usb_driver usbtv_usb_driver = { + .name = "usbtv", + .id_table = usbtv_id_table, + .probe = usbtv_probe, + .disconnect = usbtv_disconnect, +}; + +module_usb_driver(usbtv_usb_driver); diff --git a/drivers/media/usb/usbtv/usbtv.c b/drivers/media/usb/usbtv/usbtv-video.c similarity index 82% rename from drivers/media/usb/usbtv/usbtv.c rename to drivers/media/usb/usbtv/usbtv-video.c index 6222a4a..496bc2e 100644 --- a/drivers/media/usb/usbtv/usbtv.c +++ b/drivers/media/usb/usbtv/usbtv-video.c @@ -28,45 +28,10 @@ * GNU General Public License ("GPL"). */ -#include <linux/init.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/usb.h> -#include <linux/videodev2.h> - -#include <media/v4l2-device.h> #include <media/v4l2-ioctl.h> #include <media/videobuf2-core.h> -#include <media/videobuf2-vmalloc.h> - -/* Hardware. */ -#define USBTV_VIDEO_ENDP 0x81 -#define USBTV_BASE 0xc000 -#define USBTV_REQUEST_REG 12 - -/* Number of concurrent isochronous urbs submitted. - * Higher numbers was seen to overly saturate the USB bus. */ -#define USBTV_ISOC_TRANSFERS 16 -#define USBTV_ISOC_PACKETS 8 - -#define USBTV_CHUNK_SIZE 256 -#define USBTV_CHUNK 240 - -/* Chunk header. */ -#define USBTV_MAGIC_OK(chunk) ((be32_to_cpu(chunk[0]) & 0xff000000) \ - == 0x88000000) -#define USBTV_FRAME_ID(chunk) ((be32_to_cpu(chunk[0]) & 0x00ff0000) >> 16) -#define USBTV_ODD(chunk) ((be32_to_cpu(chunk[0]) & 0x0000f000) >> 15) -#define USBTV_CHUNK_NO(chunk) (be32_to_cpu(chunk[0]) & 0x00000fff) - -#define USBTV_TV_STD (V4L2_STD_525_60 | V4L2_STD_PAL) - -/* parameters for supported TV norms */ -struct usbtv_norm_params { - v4l2_std_id norm; - int cap_width, cap_height; -}; + +#include "usbtv.h" static struct usbtv_norm_params norm_params[] = { { @@ -81,43 +46,6 @@ static struct usbtv_norm_params norm_params[] = { } }; -/* A single videobuf2 frame buffer. */ -struct usbtv_buf { - struct vb2_buffer vb; - struct list_head list; -}; - -/* Per-device structure. */ -struct usbtv { - struct device *dev; - struct usb_device *udev; - struct v4l2_device v4l2_dev; - struct video_device vdev; - struct vb2_queue vb2q; - struct mutex v4l2_lock; - struct mutex vb2q_lock; - - /* List of videobuf2 buffers protected by a lock. */ - spinlock_t buflock; - struct list_head bufs; - - /* Number of currently processed frame, useful find - * out when a new one begins. */ - u32 frame_id; - int chunks_done; - - enum { - USBTV_COMPOSITE_INPUT, - USBTV_SVIDEO_INPUT, - } input; - v4l2_std_id norm; - int width, height; - int n_chunks; - int iso_size; - unsigned int sequence; - struct urb *isoc_urbs[USBTV_ISOC_TRANSFERS]; -}; - static int usbtv_configure_for_norm(struct usbtv *usbtv, v4l2_std_id norm) { int i, ret = 0; @@ -142,26 +70,6 @@ static int usbtv_configure_for_norm(struct usbtv *usbtv, v4l2_std_id norm) return ret; } -static int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size) -{ - int ret; - int pipe = usb_rcvctrlpipe(usbtv->udev, 0); - int i; - - for (i = 0; i < size; i++) { - u16 index = regs[i][0]; - u16 value = regs[i][1]; - - ret = usb_control_msg(usbtv->udev, pipe, USBTV_REQUEST_REG, - USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - value, index, NULL, 0, 0); - if (ret < 0) - return ret; - } - - return 0; -} - static int usbtv_select_input(struct usbtv *usbtv, int input) { int ret; @@ -560,12 +468,6 @@ start_fail: return ret; } -struct usb_device_id usbtv_id_table[] = { - { USB_DEVICE(0x1b71, 0x3002) }, - {} -}; -MODULE_DEVICE_TABLE(usb, usbtv_id_table); - static int usbtv_querycap(struct file *file, void *priv, struct v4l2_capability *cap) { @@ -759,33 +661,9 @@ static void usbtv_release(struct v4l2_device *v4l2_dev) kfree(usbtv); } -static int usbtv_probe(struct usb_interface *intf, - const struct usb_device_id *id) +int usbtv_video_init(struct usbtv *usbtv) { int ret; - int size; - struct device *dev = &intf->dev; - struct usbtv *usbtv; - - /* Checks that the device is what we think it is. */ - if (intf->num_altsetting != 2) - return -ENODEV; - if (intf->altsetting[1].desc.bNumEndpoints != 4) - return -ENODEV; - - /* Packet size is split into 11 bits of base size and count of - * extra multiplies of it.*/ - size = usb_endpoint_maxp(&intf->altsetting[1].endpoint[0].desc); - size = (size & 0x07ff) * (((size & 0x1800) >> 11) + 1); - - /* Device structure */ - usbtv = kzalloc(sizeof(struct usbtv), GFP_KERNEL); - if (usbtv == NULL) - return -ENOMEM; - usbtv->dev = dev; - usbtv->udev = usb_get_dev(interface_to_usbdev(intf)); - - usbtv->iso_size = size; (void)usbtv_configure_for_norm(usbtv, V4L2_STD_525_60); @@ -805,20 +683,18 @@ static int usbtv_probe(struct usb_interface *intf, usbtv->vb2q.lock = &usbtv->vb2q_lock; ret = vb2_queue_init(&usbtv->vb2q); if (ret < 0) { - dev_warn(dev, "Could not initialize videobuf2 queue\n"); - goto usbtv_fail; + dev_warn(usbtv->dev, "Could not initialize videobuf2 queue\n"); + return ret; } /* v4l2 structure */ usbtv->v4l2_dev.release = usbtv_release; - ret = v4l2_device_register(dev, &usbtv->v4l2_dev); + ret = v4l2_device_register(usbtv->dev, &usbtv->v4l2_dev); if (ret < 0) { - dev_warn(dev, "Could not register v4l2 device\n"); + dev_warn(usbtv->dev, "Could not register v4l2 device\n"); goto v4l2_fail; } - usb_set_intfdata(intf, usbtv); - /* Video structure */ strlcpy(usbtv->vdev.name, "usbtv", sizeof(usbtv->vdev.name)); usbtv->vdev.v4l2_dev = &usbtv->v4l2_dev; @@ -832,52 +708,31 @@ static int usbtv_probe(struct usb_interface *intf, video_set_drvdata(&usbtv->vdev, usbtv); ret = video_register_device(&usbtv->vdev, VFL_TYPE_GRABBER, -1); if (ret < 0) { - dev_warn(dev, "Could not register video device\n"); + dev_warn(usbtv->dev, "Could not register video device\n"); goto vdev_fail; } - dev_info(dev, "Fushicai USBTV007 Video Grabber\n"); return 0; vdev_fail: v4l2_device_unregister(&usbtv->v4l2_dev); v4l2_fail: vb2_queue_release(&usbtv->vb2q); -usbtv_fail: - kfree(usbtv); return ret; } -static void usbtv_disconnect(struct usb_interface *intf) +void usbtv_video_free(struct usbtv *usbtv) { - struct usbtv *usbtv = usb_get_intfdata(intf); - mutex_lock(&usbtv->vb2q_lock); mutex_lock(&usbtv->v4l2_lock); usbtv_stop(usbtv); - usb_set_intfdata(intf, NULL); video_unregister_device(&usbtv->vdev); v4l2_device_disconnect(&usbtv->v4l2_dev); - usb_put_dev(usbtv->udev); - usbtv->udev = NULL; mutex_unlock(&usbtv->v4l2_lock); mutex_unlock(&usbtv->vb2q_lock); v4l2_device_put(&usbtv->v4l2_dev); } - -MODULE_AUTHOR("Lubomir Rintel"); -MODULE_DESCRIPTION("Fushicai USBTV007 Video Grabber Driver"); -MODULE_LICENSE("Dual BSD/GPL"); - -struct usb_driver usbtv_usb_driver = { - .name = "usbtv", - .id_table = usbtv_id_table, - .probe = usbtv_probe, - .disconnect = usbtv_disconnect, -}; - -module_usb_driver(usbtv_usb_driver); diff --git a/drivers/media/usb/usbtv/usbtv.h b/drivers/media/usb/usbtv/usbtv.h new file mode 100644 index 0000000..536343d --- /dev/null +++ b/drivers/media/usb/usbtv/usbtv.h @@ -0,0 +1,98 @@ +/* + * Fushicai USBTV007 Video Grabber Driver + * + * Copyright (c) 2013 Lubomir Rintel + * All rights reserved. + * No physical hardware was harmed running Windows during the + * reverse-engineering activity + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL"). + */ + +#include <linux/slab.h> +#include <linux/usb.h> + +#include <media/v4l2-device.h> +#include <media/videobuf2-vmalloc.h> + +/* Hardware. */ +#define USBTV_VIDEO_ENDP 0x81 +#define USBTV_BASE 0xc000 +#define USBTV_REQUEST_REG 12 + +/* Number of concurrent isochronous urbs submitted. + * Higher numbers was seen to overly saturate the USB bus. */ +#define USBTV_ISOC_TRANSFERS 16 +#define USBTV_ISOC_PACKETS 8 + +#define USBTV_CHUNK_SIZE 256 +#define USBTV_CHUNK 240 + +/* Chunk header. */ +#define USBTV_MAGIC_OK(chunk) ((be32_to_cpu(chunk[0]) & 0xff000000) \ + == 0x88000000) +#define USBTV_FRAME_ID(chunk) ((be32_to_cpu(chunk[0]) & 0x00ff0000) >> 16) +#define USBTV_ODD(chunk) ((be32_to_cpu(chunk[0]) & 0x0000f000) >> 15) +#define USBTV_CHUNK_NO(chunk) (be32_to_cpu(chunk[0]) & 0x00000fff) + +#define USBTV_TV_STD (V4L2_STD_525_60 | V4L2_STD_PAL) + +/* parameters for supported TV norms */ +struct usbtv_norm_params { + v4l2_std_id norm; + int cap_width, cap_height; +}; + +/* A single videobuf2 frame buffer. */ +struct usbtv_buf { + struct vb2_buffer vb; + struct list_head list; +}; + +/* Per-device structure. */ +struct usbtv { + struct device *dev; + struct usb_device *udev; + + /* video */ + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct vb2_queue vb2q; + struct mutex v4l2_lock; + struct mutex vb2q_lock; + + /* List of videobuf2 buffers protected by a lock. */ + spinlock_t buflock; + struct list_head bufs; + + /* Number of currently processed frame, useful find + * out when a new one begins. */ + u32 frame_id; + int chunks_done; + + enum { + USBTV_COMPOSITE_INPUT, + USBTV_SVIDEO_INPUT, + } input; + v4l2_std_id norm; + int width, height; + int n_chunks; + int iso_size; + unsigned int sequence; + struct urb *isoc_urbs[USBTV_ISOC_TRANSFERS]; +}; + +int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size); + +int usbtv_video_init(struct usbtv *usbtv); +void usbtv_video_free(struct usbtv *usbtv); -- 1.8.4.2

4 5

[alsa-devel] Getting started
by Tom 19 Aug '14

19 Aug '14

I've got an AKAI EIE and I'd like to get it working under alsa I've been programming for a lot of years on lots of different things so can someone point me to how to get started? Tom

2 1

[alsa-devel] [PATCH v4 2/2] mfd: arizona: Update DT binding to support INn_MODE init_data
by Inha Song 19 Aug '14

19 Aug '14

This patch update DT binding to support INn_MODE init_data. Each input signal path can be configurated either as a Analogue or Digital using the INn_MODE registers. Signed-off-by: Inha Song <ideal.song(a)samsung.com> --- Documentation/devicetree/bindings/mfd/arizona.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index 5c7e723..7bd1273 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -42,6 +42,13 @@ Optional properties: the chip default will be used. If present exactly five values must be specified. + - wlf,inmode : A list of INn_MODE register values, where n is the number + of input signals. Valid values are 0 (Differential), 1 (Single-ended) and + 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. + If present, values must be specified less than or equal to the number of + input singals. If values less than the number of input signals, elements + that has not been specifed are set to 0 by default. + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if they are being externally supplied. As covered in Documentation/devicetree/bindings/regulator/regulator.txt -- 2.0.0.390.gcb682f8

2 1

[alsa-devel] [PATCH v4 1/2] mfd: arizona: Add support for INn_Mode register control
by Inha Song 19 Aug '14

19 Aug '14

Some boards need to set the INn_MODE[1:0] register to change the input signal patch. This wlf,inmode property is optional. If present, values must be specified less than or equal to the number of input singals. If values less than the number of input signals, elements that has not been specifed are set to 0 by default. Example: - wlf,inmode = <2 0 2>; /* IN1, IN3 use DMIC */ Signed-off-by: Inha Song <ideal.song(a)samsung.com> Reviewed-by: Charles Keepax <ckeepax(a)opensource.wolfsonmicro.com> --- drivers/mfd/arizona-core.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c index 10a0cb9..81e6db8 100644 --- a/drivers/mfd/arizona-core.c +++ b/drivers/mfd/arizona-core.c @@ -534,7 +534,7 @@ EXPORT_SYMBOL_GPL(arizona_of_get_named_gpio); static int arizona_of_get_core_pdata(struct arizona *arizona) { struct arizona_pdata *pdata = &arizona->pdata; - int ret, i; + int ret, i, proplen; pdata->reset = arizona_of_get_named_gpio(arizona, "wlf,reset", true); @@ -560,6 +560,12 @@ static int arizona_of_get_core_pdata(struct arizona *arizona) ret); } + proplen = of_property_count_u32_elems(arizona->dev->of_node, + "wlf,inmode"); + if (proplen > 0 && proplen <= ARRAY_SIZE(arizona->pdata.inmode)) + of_property_read_u32_array(arizona->dev->of_node, "wlf,inmode", + arizona->pdata.inmode, proplen); + return 0; } -- 2.0.0.390.gcb682f8

1 0

[alsa-devel] [PATCH v4 0/2] mfd: arizona: add support for INn_MODE register control using platform data
by Inha Song 19 Aug '14

19 Aug '14

This patch series add support for INn_MODE register control using platform data. Each input signal path can be configurated either as a Analogue or Digital using the INn_MODE registers. Changes for v4 - Update document content for more clarity Changes for v3 - Change to use of_property_read_u32_array - Fix a few typos - Update commit message Changes for v2 - Change to support - Update commit message - Update document content for more clarity Inha Song (2): mfd: arizona: Add support for INn_Mode register control mfd: arizona: Update DT binding to support INn_MODE init_data Documentation/devicetree/bindings/mfd/arizona.txt | 7 +++++++ drivers/mfd/arizona-core.c | 8 +++++++- 2 files changed, 14 insertions(+), 1 deletion(-) -- 2.0.0.390.gcb682f8

1 0

[alsa-devel] [PATCH V1 0/3] fix build error/warning in sound/soc/fsl
by Shengjiu Wang 19 Aug '14

19 Aug '14

This series patch is for fixing build error/waring in sound/soc/fsl Shengjiu Wang (3): ASoC: fsl: Kconfig: remove dependence of SND_IMX_SOC for SND_SOC_IMX_PCM_DMA ASoC: fsl-asoc-card: Fix build warning for maybe-uninitialized ASoC: fsl: fsl-asoc-card: Select SND_SOC_IMX_AUDMUX sound/soc/fsl/Kconfig | 9 +++++---- sound/soc/fsl/fsl-asoc-card.c | 9 +++++---- 2 files changed, 10 insertions(+), 8 deletions(-) -- 1.7.9.5

6 17

[alsa-devel] [PATCH 1/2] ALSA: hda/hdmi - set depop_delay for haswell plus
by libin.yang＠intel.com 19 Aug '14

19 Aug '14

From: Libin Yang <libin.yang(a)intel.com> Both Haswell and Broadwell need set depop_delay to 0. So apply this setting to haswell plus. Signed-off-by: Libin Yang <libin.yang(a)intel.com> --- sound/pci/hda/patch_hdmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 36badba..5e229f7 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -2330,9 +2330,8 @@ static int patch_generic_hdmi(struct hda_codec *codec) intel_haswell_fixup_enable_dp12(codec); } - if (is_haswell(codec) || is_valleyview(codec)) { + if (is_haswell_plus(codec) || is_valleyview(codec)) codec->depop_delay = 0; - } if (hdmi_parse_codec(codec) < 0) { codec->spec = NULL; -- 1.9.1

2 2

[alsa-devel] [PATCH v2] ALSA: hda - restore the gpio led after resume
by Hui Wang 19 Aug '14

19 Aug '14

On some HP laptops, the mute led is controlled by codec gpio. When some machine resume from s3/s4, the codec gpio data will be cleared to 0 by BIOS: Before suspend: IO[3]: enable=1, dir=1, wake=0, sticky=0, data=1, unsol=0 After resume: IO[3]: enable=1, dir=1, wake=0, sticky=0, data=0, unsol=0 To skip the AFG node to enter D3 can't fix this problem. A workaround is to restore the gpio data when the system resume back from s3/s4. It is safe even on the machines without this problem. BugLink: https://bugs.launchpad.net/bugs/1358116 Tested-by: Franz Hsieh <franz.hsieh(a)canonical.com> Cc: stable(a)vger.kernel.org Signed-off-by: Hui Wang <hui.wang(a)canonical.com> --- V2: move the verb write from led_power_filter to alc269_resume sound/pci/hda/patch_realtek.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index b32ce08..d71270a 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -3268,6 +3268,15 @@ static int alc269_resume(struct hda_codec *codec) snd_hda_codec_resume_cache(codec); alc_inv_dmic_sync(codec, true); hda_call_check_power_status(codec, 0x01); + + /* on some machine, the BIOS will clear the codec gpio data when enter + * suspend, and won't restore the data after resume, so we restore it + * in the driver. + */ + if (spec->gpio_led) + snd_hda_codec_write(codec, codec->afg, 0, AC_VERB_SET_GPIO_DATA, + spec->gpio_led); + if (spec->has_alc5505_dsp) alc5505_dsp_resume(codec); -- 1.9.1

2 1

[alsa-devel] [PATCH] ALSA: hda - Set TLV_DB_SCALE_MUTE bit for cx5051 vmaster
by Takashi Iwai 19 Aug '14

19 Aug '14

Conexnat HD-audio driver has a workaround for cx5051 (aka CX20561) chip to add fake mute controls to each amp (commit 3868137e). This implies the minimum-as-mute TLV bit in TLV for each corresponding control. Meanwhile we build the virtual master from these, but the TLV bit is missing, even though the slaves have it. This patch simply adds the missing TLV_DB_SCALE_MUTE bit for vmaster, as already done in patch_sigmatel.c. Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_conexant.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c index 7627a69ca6d7..6f2fa838b635 100644 --- a/sound/pci/hda/patch_conexant.c +++ b/sound/pci/hda/patch_conexant.c @@ -26,6 +26,7 @@ #include <linux/module.h> #include <sound/core.h> #include <sound/jack.h> +#include <sound/tlv.h> #include "hda_codec.h" #include "hda_local.h" @@ -859,6 +860,11 @@ static int patch_conexant_auto(struct hda_codec *codec) if (err < 0) goto error; + if (codec->vendor_id == 0x14f15051) { + /* minimum value is actually mute */ + spec->gen.vmaster_tlv[3] |= TLV_DB_SCALE_MUTE; + } + codec->patch_ops = cx_auto_patch_ops; /* Some laptops with Conexant chips show stalls in S3 resume, -- 2.0.4

2 4

Re: [alsa-devel] [v4 10/12] ASoC: Intel: mrfld: add the DSP DAPM widgets
by Mark Brown 19 Aug '14

19 Aug '14

On Mon, Aug 18, 2014 at 09:58:11AM +0530, Subhransu S. Prusty wrote: > On Thu, Aug 14, 2014 at 02:07:08PM +0100, Mark Brown wrote: > > > for (i = 0; i < w->num_kcontrols; i++) { > > > if (dapm_kcontrol_get_value(w->kcontrols[i])) { > > > val |= 1 << i; > > > } > > > Is this ok? > > No, that doesn't seem safe. Why not read the data from the control - if > > we were calling a function which returned the value that'd be much > > clearer. > So lets step back and see what is required here. > I get a mixer update for one of the inputs of the mixer. This needs to be > communicated to the DSP via the IPC. But the IPC expects that we send all > the values of all the inputs of a mixer to the DSP. > That is why here we are reading the all mixer inputs to find the values and > send the bitmap of all inputs. > So from the driver if I have to find out what is the value of the inputs in > mixer, how do I do that, is there a simpler way? Or should we push > this/<something else> into framework to query The problem is that it looks like you are reading the value from the control, treating it as a boolean and discarding it.

2 1

[alsa-devel] [PATCH 0/5] Convert to use regmap framework's endianness method.
by Xiubo Li 19 Aug '14

19 Aug '14

Changes in V2: - Modified the regmap config to const type. - Added ASRC patch. - Followed Rutland's advice. Xiubo Li (5): ASoC: fsl-asrc: Convert to use regmap framework's endianness method. ASoC: fsl-esai: Convert to use regmap framework's endianness method. ASoC: fsl-spdif: Convert to use regmap framework's endianness method. ASoC: fsl-sai: Convert to use regmap framework's endianness method. ASoC: fsl-sai: rename big_endian_data to is_msb_first. Documentation/devicetree/bindings/sound/fsl-sai.txt | 15 +++++++-------- sound/soc/fsl/fsl_asrc.c | 6 +----- sound/soc/fsl/fsl_esai.c | 5 +---- sound/soc/fsl/fsl_sai.c | 12 ++++-------- sound/soc/fsl/fsl_sai.h | 3 +-- sound/soc/fsl/fsl_spdif.c | 5 +---- 6 files changed, 15 insertions(+), 31 deletions(-) -- 1.8.5

1 5

[alsa-devel] [PATCH v3 2/2] mfd: arizona: Update DT binding to support INn_MODE init_data
by Inha Song 19 Aug '14

19 Aug '14

This patch update DT binding to support INn_MODE init_data. Each input signal path can be configurated either as a Analogue or Digital using the INn_MODE registers. Signed-off-by: Inha Song <ideal.song(a)samsung.com> --- Documentation/devicetree/bindings/mfd/arizona.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index 5c7e723..0064b21 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -42,6 +42,14 @@ Optional properties: the chip default will be used. If present exactly five values must be specified. + - wlf,inmode : A list of INn_MODE register values, where n is the number + of input signals. Each input signal path can be configurated either as a + Analogue or Digital using the INn_MODE registers. If absent, INn_MODE + registers set to 0 by default. If present, values must be specified less + than or equal to the number of input singals. If values less than the + number of input signals, elements that has not been specifed are set to 0 + by default. + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if they are being externally supplied. As covered in Documentation/devicetree/bindings/regulator/regulator.txt -- 2.0.0.390.gcb682f8

2 2

[alsa-devel] [PATCH] ALSA: hda/hdmi - apply Valleyview fix-ups to Cherryview display codec
by libin.yang＠intel.com 19 Aug '14

19 Aug '14

From: Libin Yang <libin.yang(a)intel.com> Valleyview and Cherryview have the same behavior on display audio. So this patch defines is_valleyview_plus() to include codecs for both Valleyview and its successor Cherryview, and apply Valleyview fix-ups to Cherryview. Signed-off-by: Libin Yang <libin.yang(a)intel.com> --- sound/pci/hda/patch_hdmi.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 36badba..99d7d7f 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -50,6 +50,8 @@ MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec)) #define is_valleyview(codec) ((codec)->vendor_id == 0x80862882) +#define is_cherryview(codec) ((codec)->vendor_id == 0x80862883) +#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) struct hdmi_spec_per_cvt { hda_nid_t cvt_nid; @@ -1459,7 +1461,7 @@ static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, mux_idx); /* configure unused pins to choose other converters */ - if (is_haswell_plus(codec) || is_valleyview(codec)) + if (is_haswell_plus(codec) || is_valleyview_plus(codec)) intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx); snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid); @@ -1598,7 +1600,8 @@ static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) * and this can make HW reset converter selection on a pin. */ if (eld->eld_valid && !old_eld_valid && per_pin->setup) { - if (is_haswell_plus(codec) || is_valleyview(codec)) { + if (is_haswell_plus(codec) || + is_valleyview_plus(codec)) { intel_verify_pin_cvt_connect(codec, per_pin); intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx); @@ -1779,7 +1782,7 @@ static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, bool non_pcm; int pinctl; - if (is_haswell_plus(codec) || is_valleyview(codec)) { + if (is_haswell_plus(codec) || is_valleyview_plus(codec)) { /* Verify pin:cvt selections to avoid silent audio after S3. * After S3, the audio driver restores pin:cvt selections * but this can happen before gfx is ready and such selection @@ -2330,9 +2333,8 @@ static int patch_generic_hdmi(struct hda_codec *codec) intel_haswell_fixup_enable_dp12(codec); } - if (is_haswell(codec) || is_valleyview(codec)) { + if (is_haswell_plus(codec) || is_valleyview_plus(codec)) codec->depop_delay = 0; - } if (hdmi_parse_codec(codec) < 0) { codec->spec = NULL; -- 1.9.1

3 2

[alsa-devel] Warning Big Yield
by Joël Krähemann 19 Aug '14

19 Aug '14

I'd really like to know if there's a common way to do syncing applications. What frequencies are required to run a GUI? How does Xorg work and how can I prevent interfering with ALSA output? And what base frequency is recommended to threads? Warning you may experience big yield. please take a look at ags_thread_loop() in: http://sourceforge.net/p/ags/code/HEAD/tree/src/ags/thread/ags_thread-posix…

3 4

[alsa-devel] [PATCH alsa-lib] Sync enum snd_hwdep_iface_t with include/asound/asound.h
by Takashi Sakamoto 19 Aug '14

19 Aug '14

Some members in this enumerated type has not updated for 9 years, although kernel-drivers added them during this period. This commit adds them following to a commit 87df9f3 'sync include/asound/asound.h with 3.17-rc1 kernel'. Signed-off-by: Takashi Sakamoto <o-takashi(a)sakamocchi.jp> --- include/hwdep.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/include/hwdep.h b/include/hwdep.h index ab12822..6ec421c 100644 --- a/include/hwdep.h +++ b/include/hwdep.h @@ -68,8 +68,13 @@ typedef enum _snd_hwdep_iface { SND_HWDEP_IFACE_USX2Y_PCM, /**< Tascam US122, US224 & US428 raw USB PCM */ SND_HWDEP_IFACE_PCXHR, /**< Digigram PCXHR */ SND_HWDEP_IFACE_SB_RC, /**< SB Extigy/Audigy2NX remote control */ - - SND_HWDEP_IFACE_LAST = SND_HWDEP_IFACE_SB_RC /**< last known hwdep interface */ + SNDRV_HWDEP_IFACE_HDA, /* HD-audio */ + SNDRV_HWDEP_IFACE_USB_STREAM, /* direct access to usb stream */ + SNDRV_HWDEP_IFACE_FW_DICE, /* TC DICE FireWire device */ + SNDRV_HWDEP_IFACE_FW_FIREWORKS, /* Echo Audio Fireworks based device */ + SNDRV_HWDEP_IFACE_FW_BEBOB, /* BridgeCo BeBoB based device */ + + SND_HWDEP_IFACE_LAST = SND_HWDEP_IFACE_FW_BEBOB /**< last known hwdep interface */ } snd_hwdep_iface_t; /** open for reading */ -- 1.9.1

2 7

[alsa-devel] [PATCH v3] ASOC: dapm: add code to configure dai link parameters
by Nikesh Oswal 18 Aug '14

18 Aug '14

dai-link params for codec-codec links were fixed. The fixed link between codec and another chip which may be another codec, baseband, bluetooth codec etc may require run time configuaration changes. This change provides an optional alsa control to select one of the params from a list of params. Signed-off-by: Nikesh Oswal <nikesh(a)opensource.wolfsonmicro.com> --- include/sound/soc-dapm.h | 3 + include/sound/soc.h | 1 + sound/soc/soc-core.c | 4 +- sound/soc/soc-dapm.c | 140 ++++++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 141 insertions(+), 7 deletions(-) diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index 6b59471..3ee031e 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -378,6 +378,7 @@ int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card); void snd_soc_dapm_connect_dai_link_widgets(struct snd_soc_card *card); int snd_soc_dapm_new_pcm(struct snd_soc_card *card, const struct snd_soc_pcm_stream *params, + unsigned int num_params, struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink); @@ -531,6 +532,8 @@ struct snd_soc_dapm_widget { void *priv; /* widget specific data */ struct regulator *regulator; /* attached regulator */ const struct snd_soc_pcm_stream *params; /* params for dai links */ + unsigned int num_params; /* number of params for dai links */ + unsigned int params_select; /* currently selected param for dai link */ /* dapm control */ int reg; /* negative reg = no direct dapm */ diff --git a/include/sound/soc.h b/include/sound/soc.h index ed9e2d7..51c6c4f 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -906,6 +906,7 @@ struct snd_soc_dai_link { int be_id; /* optional ID for machine driver BE identification */ const struct snd_soc_pcm_stream *params; + unsigned int num_params; unsigned int dai_fmt; /* format to set on init */ diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index b87d7d8..db1572a 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -1461,7 +1461,7 @@ static int soc_link_dai_widgets(struct snd_soc_card *card, capture_w = cpu_dai->capture_widget; if (play_w && capture_w) { ret = snd_soc_dapm_new_pcm(card, dai_link->params, - capture_w, play_w); + dai_link->num_params, capture_w, play_w); if (ret != 0) { dev_err(card->dev, "ASoC: Can't link %s to %s: %d\n", play_w->name, capture_w->name, ret); @@ -1473,7 +1473,7 @@ static int soc_link_dai_widgets(struct snd_soc_card *card, capture_w = codec_dai->capture_widget; if (play_w && capture_w) { ret = snd_soc_dapm_new_pcm(card, dai_link->params, - capture_w, play_w); + dai_link->num_params, capture_w, play_w); if (ret != 0) { dev_err(card->dev, "ASoC: Can't link %s to %s: %d\n", play_w->name, capture_w->name, ret); diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index cdc837e..41f835b 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c @@ -729,6 +729,33 @@ static int dapm_new_pga(struct snd_soc_dapm_widget *w) return 0; } +/* create new dapm dai link control */ +static int dapm_new_dai_link(struct snd_soc_dapm_widget *w) +{ + int i, ret; + struct snd_kcontrol *kcontrol; + struct snd_soc_dapm_context *dapm = w->dapm; + struct snd_card *card = dapm->card->snd_card; + + + /* add kcontrol */ + for (i = 0; i < w->num_kcontrols; i++) { + kcontrol = snd_soc_cnew(&w->kcontrol_news[i], w, + w->name, NULL); + ret = snd_ctl_add(card, kcontrol); + if (ret < 0) { + dev_err(dapm->dev, + "ASoC: failed to add widget %s dapm kcontrol %s: %d\n", + w->name, w->kcontrol_news[i].name, ret); + return ret; + } + kcontrol->private_data = w; + w->kcontrols[i] = kcontrol; + } + + return 0; +} + /* reset 'walked' bit for each dapm path */ static void dapm_clear_walk_output(struct snd_soc_dapm_context *dapm, struct list_head *sink) @@ -2664,6 +2691,9 @@ int snd_soc_dapm_new_widgets(struct snd_soc_card *card) case snd_soc_dapm_out_drv: dapm_new_pga(w); break; + case snd_soc_dapm_dai_link: + dapm_new_dai_link(w); + break; default: break; } @@ -3142,6 +3172,9 @@ static int snd_soc_dai_link_event(struct snd_soc_dapm_widget *w, source = source_p->source->priv; sink = sink_p->sink->priv; + /* Select the configuration set by alsa control */ + config += w->params_select; + /* Be a little careful as we don't want to overflow the mask array */ if (config->formats) { fmt = ffs(config->formats) - 1; @@ -3222,8 +3255,35 @@ out: return ret; } +static int snd_soc_dapm_dai_link_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); + + ucontrol->value.integer.value[0] = w->params_select; + + return 0; +} + +static int snd_soc_dapm_dai_link_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); + + if (ucontrol->value.integer.value[0] == w->params_select) + return 0; + + if (ucontrol->value.integer.value[0] >= w->num_params) + return -EINVAL; + + w->params_select = ucontrol->value.integer.value[0]; + + return 0; +} + int snd_soc_dapm_new_pcm(struct snd_soc_card *card, const struct snd_soc_pcm_stream *params, + unsigned int num_params, struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink) { @@ -3231,12 +3291,44 @@ int snd_soc_dapm_new_pcm(struct snd_soc_card *card, struct snd_soc_dapm_widget *w; size_t len; char *link_name; - int ret; + int ret, count; + unsigned long private_value; + char **w_param_text; + struct soc_enum w_param_enum[] = { + SOC_ENUM_SINGLE(0, 0, 0, NULL), + }; + struct snd_kcontrol_new kcontrol_dai_link[] = { + SOC_ENUM_EXT(NULL, w_param_enum[0], + snd_soc_dapm_dai_link_get, snd_soc_dapm_dai_link_put), + }; + const struct snd_soc_pcm_stream *config = params; + + w_param_text = kzalloc(sizeof(char *) * num_params, GFP_KERNEL); + if (!w_param_text) + return -ENOMEM; + + for (count = 0 ; count < num_params; count++) { + w_param_text[count] = kzalloc(sizeof(char) * 100, GFP_KERNEL); + if (!w_param_text) { + ret = -ENOMEM; + goto outfree_w_param; + } + + sprintf(w_param_text[count], "SampleRate=%d:Channels=%d:BitsPerSample=%d", + config->rate_min, config->channels_min, + snd_pcm_format_width(ffs(config->formats) - 1)); + config++; + } + w_param_enum[0].items = num_params; + w_param_enum[0].texts = (const char * const *) w_param_text; len = strlen(source->name) + strlen(sink->name) + 2; link_name = devm_kzalloc(card->dev, len, GFP_KERNEL); - if (!link_name) - return -ENOMEM; + if (!link_name) { + ret = -ENOMEM; + goto outfree_w_param; + } + snprintf(link_name, len, "%s-%s", source->name, sink->name); memset(&template, 0, sizeof(template)); @@ -3246,6 +3338,25 @@ int snd_soc_dapm_new_pcm(struct snd_soc_card *card, template.event = snd_soc_dai_link_event; template.event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD; + template.num_kcontrols = 1; + private_value = + (unsigned long) kmemdup((void *)(kcontrol_dai_link[0].private_value), + sizeof(struct soc_enum), GFP_KERNEL); + if (!private_value) { + dev_err(card->dev, "ASoC: Failed to create control for %s widget\n", + link_name); + ret = -ENOMEM; + goto outfree_link_name; + } + kcontrol_dai_link[0].private_value = private_value; + template.kcontrol_news = kmemdup(&kcontrol_dai_link[0], + sizeof(struct snd_kcontrol_new), GFP_KERNEL); + if (!template.kcontrol_news) { + dev_err(card->dev, "ASoC: Failed to create control for %s widget\n", + link_name); + ret = -ENOMEM; + goto outfree_private_value; + } dev_dbg(card->dev, "ASoC: adding %s widget\n", link_name); @@ -3253,15 +3364,34 @@ int snd_soc_dapm_new_pcm(struct snd_soc_card *card, if (!w) { dev_err(card->dev, "ASoC: Failed to create %s widget\n", link_name); - return -ENOMEM; + ret = -ENOMEM; + goto outfree_kcontrol_news; } w->params = params; + w->num_params = num_params; ret = snd_soc_dapm_add_path(&card->dapm, source, w, NULL, NULL); if (ret) - return ret; + goto outfree_w; return snd_soc_dapm_add_path(&card->dapm, w, sink, NULL, NULL); + +outfree_w: + kfree(w); +outfree_kcontrol_news: + kfree(template.kcontrol_news); +outfree_private_value: + kfree((void *)private_value); +outfree_link_name: + kfree(link_name); +outfree_w_param: + for (count = 0 ; count < num_params; count++) { + if (w_param_text[count]) + kfree(w_param_text[count]); + } + kfree(w_param_text); + + return ret; } int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm, -- 1.7.9.5

3 7

[alsa-devel] [PATCH] ASoC: simple-card: Fix the compile warning.
by Xiubo Li 18 Aug '14

18 Aug '14

sound/soc/generic/simple-card.c: In function simple_card_dai_link_of: sound/soc/generic/simple-card.c:198:10: warning: passing argument 3 of asoc_simple_card_sub_parse_of from incompatible pointer type [enabled by default] &dai_link->cpu_dai_name); ^ sound/soc/generic/simple-card.c:112:1: note: expected const struct device_node ** but argument is of type struct device_node ** asoc_simple_card_sub_parse_of(struct device_node *np, ^ sound/soc/generic/simple-card.c:229:10: warning: passing argument 3 of asoc_simple_card_sub_parse_of from incompatible pointer type [enabled by default] &dai_link->codec_dai_name); ^ sound/soc/generic/simple-card.c:112:1: note: expected const struct device_node ** but argument is of type struct device_node ** asoc_simple_card_sub_parse_of(struct device_node *np, ^ Since the asoc_simple_card_sub_parse_of() is used in simple-card module only, and the third argument is just used to get the node ponters address, so there is no need it must to be 'const' type. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> --- sound/soc/generic/simple-card.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/generic/simple-card.c b/sound/soc/generic/simple-card.c index 159e517f..21b0ea2 100644 --- a/sound/soc/generic/simple-card.c +++ b/sound/soc/generic/simple-card.c @@ -111,7 +111,7 @@ static int asoc_simple_card_dai_init(struct snd_soc_pcm_runtime *rtd) static int asoc_simple_card_sub_parse_of(struct device_node *np, struct asoc_simple_dai *dai, - const struct device_node **p_node, + struct device_node **p_node, const char **name) { struct device_node *node; -- 1.8.5

2 1

[alsa-devel] [PATCH v7 5/8] clk: Move all drivers to use internal API
by Tomeu Vizoso 18 Aug '14

18 Aug '14

In preparation to change the public API to return a per-user clk structure, remove any usage of this public API from the clock implementations. The reason for having this in a separate commit from the one that introduces the implementation of the new functions is to separate the changes generated with Coccinelle from the rest, and keep the patches' size reasonable. Signed-off-by: Tomeu Vizoso <tomeu.vizoso(a)collabora.com> Tested-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> --- arch/arm/mach-dove/common.c | 10 +- arch/arm/mach-imx/clk-busy.c | 8 +- arch/arm/mach-imx/clk-fixup-div.c | 4 +- arch/arm/mach-imx/clk-fixup-mux.c | 4 +- arch/arm/mach-imx/clk-gate2.c | 4 +- arch/arm/mach-imx/clk-imx1.c | 2 +- arch/arm/mach-imx/clk-imx21.c | 2 +- arch/arm/mach-imx/clk-imx25.c | 8 +- arch/arm/mach-imx/clk-imx27.c | 4 +- arch/arm/mach-imx/clk-imx31.c | 10 +- arch/arm/mach-imx/clk-imx35.c | 22 +- arch/arm/mach-imx/clk-imx51-imx53.c | 77 +++--- arch/arm/mach-imx/clk-imx6q.c | 53 ++-- arch/arm/mach-imx/clk-imx6sl.c | 13 +- arch/arm/mach-imx/clk-imx6sx.c | 97 ++++--- arch/arm/mach-imx/clk-pfd.c | 4 +- arch/arm/mach-imx/clk-pllv1.c | 4 +- arch/arm/mach-imx/clk-pllv2.c | 4 +- arch/arm/mach-imx/clk-pllv3.c | 4 +- arch/arm/mach-imx/clk-vf610.c | 42 +-- arch/arm/mach-imx/clk.c | 10 +- arch/arm/mach-imx/clk.h | 42 +-- arch/arm/mach-msm/clock-pcom.c | 2 +- arch/arm/mach-mv78xx0/common.c | 2 +- arch/arm/mach-omap2/cclock3xxx_data.c | 370 +++++++++++++------------- arch/arm/mach-omap2/clkt2xxx_dpll.c | 4 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 4 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 2 +- arch/arm/mach-omap2/clkt_clksel.c | 46 ++-- arch/arm/mach-omap2/clkt_dpll.c | 8 +- arch/arm/mach-omap2/clock.c | 52 ++-- arch/arm/mach-omap2/clock.h | 18 +- arch/arm/mach-omap2/clock3xxx.c | 22 +- arch/arm/mach-omap2/clock3xxx.h | 4 +- arch/arm/mach-omap2/clock_common_data.c | 2 +- arch/arm/mach-omap2/clockdomain.c | 8 +- arch/arm/mach-omap2/clockdomain.h | 4 +- arch/arm/mach-omap2/display.c | 4 +- arch/arm/mach-omap2/dpll3xxx.c | 28 +- arch/arm/mach-omap2/dpll44xx.c | 4 +- arch/arm/mach-omap2/mcbsp.c | 4 +- arch/arm/mach-omap2/omap_device.c | 8 +- arch/arm/mach-omap2/omap_hwmod.c | 42 +-- arch/arm/mach-omap2/omap_hwmod.h | 12 +- arch/arm/mach-omap2/pm24xx.c | 12 +- arch/arm/mach-orion5x/common.c | 2 +- arch/arm/mach-shmobile/clock.c | 14 +- arch/arm/mach-shmobile/clock.h | 4 +- arch/arm/mach-vexpress/spc.c | 4 +- arch/arm/plat-orion/common.c | 20 +- arch/arm/plat-orion/include/plat/common.h | 12 +- arch/powerpc/platforms/512x/clock-commonclk.c | 48 ++-- drivers/clk/at91/clk-main.c | 24 +- drivers/clk/at91/clk-master.c | 6 +- drivers/clk/at91/clk-peripheral.c | 12 +- drivers/clk/at91/clk-pll.c | 6 +- drivers/clk/at91/clk-plldiv.c | 6 +- drivers/clk/at91/clk-programmable.c | 10 +- drivers/clk/at91/clk-slow.c | 24 +- drivers/clk/at91/clk-smd.c | 6 +- drivers/clk/at91/clk-system.c | 6 +- drivers/clk/at91/clk-usb.c | 18 +- drivers/clk/at91/clk-utmi.c | 6 +- drivers/clk/bcm/clk-kona-setup.c | 6 +- drivers/clk/bcm/clk-kona.c | 12 +- drivers/clk/bcm/clk-kona.h | 2 +- drivers/clk/berlin/berlin2-avpll.c | 4 +- drivers/clk/berlin/berlin2-avpll.h | 4 +- drivers/clk/berlin/berlin2-div.c | 2 +- drivers/clk/berlin/berlin2-div.h | 2 +- drivers/clk/berlin/berlin2-pll.c | 2 +- drivers/clk/berlin/berlin2-pll.h | 2 +- drivers/clk/berlin/bg2.c | 12 +- drivers/clk/berlin/bg2q.c | 8 +- drivers/clk/clk-axi-clkgen.c | 2 +- drivers/clk/clk-axm5516.c | 4 +- drivers/clk/clk-bcm2835.c | 2 +- drivers/clk/clk-composite.c | 10 +- drivers/clk/clk-conf.c | 16 +- drivers/clk/clk-divider.c | 8 +- drivers/clk/clk-efm32gg.c | 2 +- drivers/clk/clk-fixed-factor.c | 6 +- drivers/clk/clk-fixed-rate.c | 8 +- drivers/clk/clk-fractional-divider.c | 4 +- drivers/clk/clk-gate.c | 4 +- drivers/clk/clk-highbank.c | 8 +- drivers/clk/clk-ls1x.c | 16 +- drivers/clk/clk-max77686.c | 10 +- drivers/clk/clk-moxart.c | 8 +- drivers/clk/clk-mux.c | 6 +- drivers/clk/clk-nomadik.c | 14 +- drivers/clk/clk-nspire.c | 4 +- drivers/clk/clk-ppc-corenet.c | 8 +- drivers/clk/clk-s2mps11.c | 6 +- drivers/clk/clk-si5351.c | 17 +- drivers/clk/clk-si570.c | 4 +- drivers/clk/clk-twl6040.c | 2 +- drivers/clk/clk-u300.c | 12 +- drivers/clk/clk-vt8500.c | 4 +- drivers/clk/clk-wm831x.c | 6 +- drivers/clk/clk-xgene.c | 12 +- drivers/clk/clk.h | 4 +- drivers/clk/hisilicon/clk-hi3620.c | 8 +- drivers/clk/hisilicon/clk.c | 16 +- drivers/clk/hisilicon/clk.h | 2 +- drivers/clk/hisilicon/clkgate-separated.c | 4 +- drivers/clk/keystone/gate.c | 6 +- drivers/clk/keystone/pll.c | 10 +- drivers/clk/mmp/clk-apbc.c | 4 +- drivers/clk/mmp/clk-apmu.c | 4 +- drivers/clk/mmp/clk-frac.c | 4 +- drivers/clk/mmp/clk-mmp2.c | 14 +- drivers/clk/mmp/clk-pxa168.c | 12 +- drivers/clk/mmp/clk-pxa910.c | 12 +- drivers/clk/mmp/clk.h | 8 +- drivers/clk/mvebu/clk-corediv.c | 4 +- drivers/clk/mvebu/clk-cpu.c | 8 +- drivers/clk/mvebu/common.c | 14 +- drivers/clk/mxs/clk-div.c | 4 +- drivers/clk/mxs/clk-frac.c | 4 +- drivers/clk/mxs/clk-imx23.c | 4 +- drivers/clk/mxs/clk-imx28.c | 4 +- drivers/clk/mxs/clk-pll.c | 4 +- drivers/clk/mxs/clk-ref.c | 4 +- drivers/clk/mxs/clk.h | 16 +- drivers/clk/qcom/clk-rcg.c | 8 +- drivers/clk/qcom/clk-rcg2.c | 14 +- drivers/clk/qcom/clk-regmap.c | 2 +- drivers/clk/qcom/clk-regmap.h | 2 +- drivers/clk/qcom/common.c | 6 +- drivers/clk/qcom/gcc-msm8660.c | 2 +- drivers/clk/qcom/gcc-msm8960.c | 2 +- drivers/clk/qcom/gcc-msm8974.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 6 +- drivers/clk/rockchip/clk-pll.c | 8 +- drivers/clk/rockchip/clk-rk3188.c | 2 +- drivers/clk/rockchip/clk-rk3288.c | 2 +- drivers/clk/rockchip/clk-rockchip.c | 2 +- drivers/clk/rockchip/clk.c | 14 +- drivers/clk/rockchip/clk.h | 4 +- drivers/clk/samsung/clk-exynos-audss.c | 16 +- drivers/clk/samsung/clk-exynos-clkout.c | 8 +- drivers/clk/samsung/clk-exynos4.c | 6 +- drivers/clk/samsung/clk-pll.c | 6 +- drivers/clk/samsung/clk-pll.h | 2 +- drivers/clk/samsung/clk-s3c2410-dclk.c | 30 +-- drivers/clk/samsung/clk.c | 22 +- drivers/clk/samsung/clk.h | 2 +- drivers/clk/shmobile/clk-div6.c | 2 +- drivers/clk/shmobile/clk-emev2.c | 4 +- drivers/clk/shmobile/clk-mstp.c | 6 +- drivers/clk/shmobile/clk-r8a7740.c | 6 +- drivers/clk/shmobile/clk-r8a7779.c | 6 +- drivers/clk/shmobile/clk-rcar-gen2.c | 10 +- drivers/clk/shmobile/clk-rz.c | 6 +- drivers/clk/sirf/clk-atlas6.c | 2 +- drivers/clk/sirf/clk-common.c | 30 +-- drivers/clk/sirf/clk-prima2.c | 2 +- drivers/clk/socfpga/clk-gate.c | 2 +- drivers/clk/socfpga/clk-periph.c | 2 +- drivers/clk/socfpga/clk-pll.c | 4 +- drivers/clk/spear/clk-aux-synth.c | 8 +- drivers/clk/spear/clk-frac-synth.c | 4 +- drivers/clk/spear/clk-gpt-synth.c | 4 +- drivers/clk/spear/clk-vco-pll.c | 8 +- drivers/clk/spear/clk.h | 14 +- drivers/clk/spear/spear1310_clock.c | 2 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/clk/spear/spear3xx_clock.c | 16 +- drivers/clk/spear/spear6xx_clock.c | 2 +- drivers/clk/st/clk-flexgen.c | 12 +- drivers/clk/st/clkgen-fsyn.c | 22 +- drivers/clk/st/clkgen-mux.c | 32 +-- drivers/clk/st/clkgen-pll.c | 34 +-- drivers/clk/sunxi/clk-a10-hosc.c | 2 +- drivers/clk/sunxi/clk-a20-gmac.c | 2 +- drivers/clk/sunxi/clk-factors.c | 4 +- drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 2 +- drivers/clk/sunxi/clk-sun6i-apb0.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 6 +- drivers/clk/sunxi/clk-sun8i-apb0.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 18 +- drivers/clk/tegra/clk-audio-sync.c | 4 +- drivers/clk/tegra/clk-divider.c | 4 +- drivers/clk/tegra/clk-periph-gate.c | 4 +- drivers/clk/tegra/clk-periph.c | 8 +- drivers/clk/tegra/clk-pll-out.c | 4 +- drivers/clk/tegra/clk-pll.c | 40 +-- drivers/clk/tegra/clk-super.c | 4 +- drivers/clk/tegra/clk-tegra-audio.c | 4 +- drivers/clk/tegra/clk-tegra-fixed.c | 8 +- drivers/clk/tegra/clk-tegra-periph.c | 12 +- drivers/clk/tegra/clk-tegra-pmc.c | 4 +- drivers/clk/tegra/clk-tegra-super-gen4.c | 8 +- drivers/clk/tegra/clk-tegra114.c | 10 +- drivers/clk/tegra/clk-tegra124.c | 6 +- drivers/clk/tegra/clk-tegra20.c | 12 +- drivers/clk/tegra/clk-tegra30.c | 8 +- drivers/clk/tegra/clk.c | 24 +- drivers/clk/tegra/clk.h | 38 +-- drivers/clk/ti/apll.c | 8 +- drivers/clk/ti/clk-2xxx.c | 8 +- drivers/clk/ti/clk-33xx.c | 18 +- drivers/clk/ti/clk-3xxx.c | 8 +- drivers/clk/ti/clk-43xx.c | 8 +- drivers/clk/ti/clk-44xx.c | 16 +- drivers/clk/ti/clk-54xx.c | 25 +- drivers/clk/ti/clk-7xx.c | 28 +- drivers/clk/ti/clk-dra7-atl.c | 6 +- drivers/clk/ti/clk.c | 2 +- drivers/clk/ti/clockdomain.c | 4 +- drivers/clk/ti/composite.c | 2 +- drivers/clk/ti/divider.c | 6 +- drivers/clk/ti/dpll.c | 8 +- drivers/clk/ti/fixed-factor.c | 2 +- drivers/clk/ti/gate.c | 2 +- drivers/clk/ti/interface.c | 2 +- drivers/clk/ti/mux.c | 6 +- drivers/clk/ux500/abx500-clk.c | 2 +- drivers/clk/ux500/clk-prcc.c | 8 +- drivers/clk/ux500/clk-prcmu.c | 16 +- drivers/clk/ux500/clk-sysctrl.c | 10 +- drivers/clk/ux500/clk.h | 22 +- drivers/clk/ux500/u8500_clk.c | 2 +- drivers/clk/ux500/u8500_of_clk.c | 12 +- drivers/clk/ux500/u8540_clk.c | 2 +- drivers/clk/versatile/clk-icst.c | 4 +- drivers/clk/versatile/clk-icst.h | 2 +- drivers/clk/versatile/clk-impd1.c | 18 +- drivers/clk/versatile/clk-realview.c | 2 +- drivers/clk/versatile/clk-sp810.c | 30 ++- drivers/clk/versatile/clk-versatile.c | 2 +- drivers/clk/versatile/clk-vexpress-osc.c | 2 +- drivers/clk/versatile/clk-vexpress.c | 6 +- drivers/clk/x86/clk-lpt.c | 2 +- drivers/clk/zynq/clkc.c | 22 +- drivers/clk/zynq/pll.c | 4 +- drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 2 +- drivers/media/platform/exynos4-is/media-dev.c | 16 +- drivers/media/platform/exynos4-is/media-dev.h | 6 +- drivers/staging/imx-drm/imx-tve.c | 26 +- include/asm-generic/clkdev.h | 4 +- include/linux/clk/ti.h | 10 +- include/linux/clk/zynq.h | 2 +- include/linux/platform_data/si5351.h | 4 +- 246 files changed, 1430 insertions(+), 1378 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 0d1a892..4d95685 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -71,9 +71,9 @@ void __init dove_map_io(void) static int dove_tclk; static DEFINE_SPINLOCK(gating_lock); -static struct clk *tclk; +static struct clk_core *tclk; -static struct clk __init *dove_register_gate(const char *name, +static struct clk_core __init *dove_register_gate(const char *name, const char *parent, u8 bit_idx) { return clk_register_gate(NULL, name, parent, 0, @@ -83,9 +83,9 @@ static struct clk __init *dove_register_gate(const char *name, static void __init dove_clk_init(void) { - struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; - struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; - struct clk *xor0, *xor1, *ge, *gephy; + struct clk_core *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; + struct clk_core *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; + struct clk_core *xor0, *xor1, *ge, *gephy; tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, dove_tclk); diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c index 4bb1bc4..e4161ed 100644 --- a/arch/arm/mach-imx/clk-busy.c +++ b/arch/arm/mach-imx/clk-busy.c @@ -78,12 +78,12 @@ static struct clk_ops clk_busy_divider_ops = { .set_rate = clk_busy_divider_set_rate, }; -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift) { struct clk_busy_divider *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); @@ -152,12 +152,12 @@ static struct clk_ops clk_busy_mux_ops = { .set_parent = clk_busy_mux_set_parent, }; -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents) { struct clk_busy_mux *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c index 21db020..8a62bfd 100644 --- a/arch/arm/mach-imx/clk-fixup-div.c +++ b/arch/arm/mach-imx/clk-fixup-div.c @@ -92,12 +92,12 @@ static const struct clk_ops clk_fixup_div_ops = { .set_rate = clk_fixup_div_set_rate, }; -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)) { struct clk_fixup_div *fixup_div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c index 0d40b35..e29dc62 100644 --- a/arch/arm/mach-imx/clk-fixup-mux.c +++ b/arch/arm/mach-imx/clk-fixup-mux.c @@ -71,12 +71,12 @@ static const struct clk_ops clk_fixup_mux_ops = { .set_parent = clk_fixup_mux_set_parent, }; -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)) { struct clk_fixup_mux *fixup_mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 84acdfd..d78f409 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -108,14 +108,14 @@ static struct clk_ops clk_gate2_ops = { .is_enabled = clk_gate2_is_enabled, }; -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) { struct clk_gate2 *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 37c307a..4802cb4 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -32,7 +32,7 @@ static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", }; static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem", "fclk", }; -static struct clk *clk[IMX1_CLK_MAX]; +static struct clk_core *clk[IMX1_CLK_MAX]; static struct clk_onecell_data clk_data; static void __iomem *ccm __initdata; diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index 4b4c753..58b3109 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -36,7 +36,7 @@ static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", }; -static struct clk *clk[IMX21_CLK_MAX]; +static struct clk_core *clk[IMX21_CLK_MAX]; static struct clk_onecell_data clk_data; static void __init _mx21_clocks_init(unsigned long lref, unsigned long href) diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 59c0c85..a80c11e 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -87,7 +87,7 @@ enum mx25_clks { wdt_ipg, cko_div, cko_sel, cko, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static int __init __mx25_clocks_init(unsigned long osc_rate, void __iomem *ccm_base) @@ -225,16 +225,16 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, imx_check_clocks(clk, ARRAY_SIZE(clk)); - clk_prepare_enable(clk[emi_ahb]); + clk_provider_prepare_enable(clk[emi_ahb]); /* Clock source for gpt must be derived from AHB */ - clk_set_parent(clk[per5_sel], clk[ahb]); + clk_provider_set_parent(clk[per5_sel], clk[ahb]); /* * Let's initially set up CLKO parent as ipg, since this configuration * is used on some imx25 board designs to clock the audio codec. */ - clk_set_parent(clk[cko_sel], clk[ipg]); + clk_provider_set_parent(clk[cko_sel], clk[ipg]); return 0; } diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index ab6349e..b0b7f06 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -39,7 +39,7 @@ static const char *clko_sel_clks[] = { static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; -static struct clk *clk[IMX27_CLK_MAX]; +static struct clk_core *clk[IMX27_CLK_MAX]; static struct clk_onecell_data clk_data; static void __init _mx27_clocks_init(unsigned long fref) @@ -156,7 +156,7 @@ static void __init _mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); - clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); + clk_provider_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); imx_print_silicon_rev("i.MX27", mx27_revision()); } diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index 286ef42..355d253 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -45,7 +45,7 @@ enum mx31_clks { gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; int __init mx31_clocks_init(unsigned long fref) @@ -176,11 +176,11 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); clk_register_clkdev(clk[iim_gate], "iim", NULL); - clk_set_parent(clk[csi], clk[upll]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[iim_gate]); + clk_provider_set_parent(clk[csi], clk[upll]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[iim_gate]); mx31_revision(); - clk_disable_unprepare(clk[iim_gate]); + clk_provider_disable_unprepare(clk[iim_gate]); mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index a0d2b57..8eeb563 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -67,7 +67,7 @@ enum mx35_clks { gpu2d_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; int __init mx35_clocks_init(void) { @@ -99,7 +99,7 @@ int __init mx35_clocks_init(void) else clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); - if (clk_get_rate(clk[arm]) > 400000000) + if (clk_provider_get_rate(clk[arm]) > 400000000) hsp_div = hsp_div_532; else hsp_div = hsp_div_400; @@ -257,14 +257,14 @@ int __init mx35_clocks_init(void) clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); clk_register_clkdev(clk[admux_gate], "audmux", NULL); - clk_prepare_enable(clk[spba_gate]); - clk_prepare_enable(clk[gpio1_gate]); - clk_prepare_enable(clk[gpio2_gate]); - clk_prepare_enable(clk[gpio3_gate]); - clk_prepare_enable(clk[iim_gate]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[max_gate]); - clk_prepare_enable(clk[iomuxc_gate]); + clk_provider_prepare_enable(clk[spba_gate]); + clk_provider_prepare_enable(clk[gpio1_gate]); + clk_provider_prepare_enable(clk[gpio2_gate]); + clk_provider_prepare_enable(clk[gpio3_gate]); + clk_provider_prepare_enable(clk[iim_gate]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[max_gate]); + clk_provider_prepare_enable(clk[iomuxc_gate]); /* * SCC is needed to boot via mmc after a watchdog reset. The clock code @@ -272,7 +272,7 @@ int __init mx35_clocks_init(void) * handled here and not needed for mmc) and IIM (which is enabled * unconditionally above). */ - clk_prepare_enable(clk[scc_gate]); + clk_provider_prepare_enable(clk[scc_gate]); imx_print_silicon_rev("i.MX35", mx35_revision()); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 72d6521..47cc37c 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -126,7 +126,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_ static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; -static struct clk *clk[IMX5_CLK_END]; +static struct clk_core *clk[IMX5_CLK_END]; static struct clk_onecell_data clk_data; static void __init mx5_clocks_common_init(void __iomem *ccm_base) @@ -289,26 +289,28 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); /* Set SDHC parents to be PLL2 */ - clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); - clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], + clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], + clk[IMX5_CLK_PLL2_SW]); /* move usb phy clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); - - clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); - clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_SPBA]); - clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); - clk_prepare_enable(clk[IMX5_CLK_TMAX1]); - clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ - clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ + clk_provider_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); + + clk_provider_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); + clk_provider_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_SPBA]); + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX1]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ } static void __init mx50_clocks_init(struct device_node *np) @@ -361,15 +363,15 @@ static void __init mx50_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); } CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); @@ -435,15 +437,16 @@ static void __init mx51_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* set the usboh3 parent to pll2_sw */ - clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_USBOH3_SEL], + clk[IMX5_CLK_PLL2_SW]); /* set SDHC root clock to 166.25MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX51", mx51_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); /* * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no @@ -545,17 +548,17 @@ static void __init mx53_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); /* move can bus clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); + clk_provider_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX53", mx53_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); } CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 6cceb77..05df226 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -74,7 +74,7 @@ static const char *lvds_sels[] = { "pcie_ref_125m", "sata_ref_100m", }; -static struct clk *clk[IMX6QDL_CLK_END]; +static struct clk_core *clk[IMX6QDL_CLK_END]; static struct clk_onecell_data clk_data; static unsigned int const clks_init_on[] __initconst = { @@ -408,50 +408,65 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); } - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); - clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); - clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], + clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], + clk[IMX6QDL_CLK_IPU1_DI0_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], + clk[IMX6QDL_CLK_IPU1_DI1_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], + clk[IMX6QDL_CLK_IPU2_DI0_PRE]); + clk_provider_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], + clk[IMX6QDL_CLK_IPU2_DI1_PRE]); /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, * We can not get the 100MHz from the pll2_pfd0_352m. * So choose pll2_pfd2_396m as enfc_sel's parent. */ - clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); + clk_provider_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], + clk[IMX6QDL_CLK_PLL2_PFD2_396M]); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); + clk_provider_prepare_enable(clk[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); } /* * Let's initially set up CLKO with OSC24M, since this configuration * is widely used by imx6q board designs to clock audio codec. */ - ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); + ret = clk_provider_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], + clk[IMX6QDL_CLK_OSC]); if (!ret) - ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); + ret = clk_provider_set_parent(clk[IMX6QDL_CLK_CKO], + clk[IMX6QDL_CLK_CKO2]); if (ret) pr_warn("failed to set up CLKO: %d\n", ret); /* Audio-related clocks configuration */ - clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); + clk_provider_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], + clk[IMX6QDL_CLK_PLL3_PFD3_454M]); /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) - clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); + clk_provider_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], + clk[IMX6QDL_CLK_SATA_REF_100M]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index fef46fa..69868f3 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -79,7 +79,7 @@ static struct clk_div_table video_div_table[] = { { } }; -static struct clk *clks[IMX6SL_CLK_END]; +static struct clk_core *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; static void __iomem *ccm_base; static void __iomem *anatop_base; @@ -355,7 +355,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); /* Ensure the AHB clk is at 132MHz. */ - ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); + ret = clk_provider_set_rate(clks[IMX6SL_CLK_AHB], 132000000); if (ret) pr_warn("%s: failed to set AHB clock rate %d!\n", __func__, ret); @@ -365,15 +365,16 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) * usecount and enabling/disabling of parent PLLs. */ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); } /* Audio-related clocks configuration */ - clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + clk_provider_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], + clks[IMX6SL_CLK_PLL3_PFD3]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index ecde72b..c5de9c1 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -82,7 +82,7 @@ static const char *lvds_sels[] = { "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", }; -static struct clk *clks[IMX6SX_CLK_CLK_END]; +static struct clk_core *clks[IMX6SX_CLK_CLK_END]; static struct clk_onecell_data clk_data; static int const clks_init_on[] __initconst = { @@ -136,12 +136,14 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); - clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); + clks[IMX6SX_CLK_CKIL] = of_clk_provider_get_by_name(ccm_node, "ckil"); + clks[IMX6SX_CLK_OSC] = of_clk_provider_get_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); - clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); + clks[IMX6SX_CLK_IPP_DI0] = of_clk_provider_get_by_name(ccm_node, + "ipp_di0"); + clks[IMX6SX_CLK_IPP_DI1] = of_clk_provider_get_by_name(ccm_node, + "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); base = of_iomap(np, 0); @@ -453,65 +455,80 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); } /* Set the default 132MHz for EIM module */ - clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); + clk_provider_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); /* set parent clock for LCDIF1 pixel clock */ - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], + clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], + clks[IMX6SX_CLK_LCDIF1_PODF]); /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ - if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) pr_err("Failed to set pcie bus parent clk.\n"); - if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) pr_err("Failed to set pcie parent clk.\n"); /* * Init enet system AHB clock, set to 200Mhz * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB */ - clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]); - clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); - clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); - clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_SEL], + clks[IMX6SX_CLK_ENET_PODF]); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); /* Audio clocks */ - clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); - - clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); - - clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); - clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); - - clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); - - clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); + + clk_provider_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SSI1_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI2_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI3_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); + + clk_provider_set_parent(clks[IMX6SX_CLK_ESAI_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); /* Set parent clock for vadc */ - clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_parent(clks[IMX6SX_CLK_VID_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); /* default parent of can_sel clock is invalid, manually set it here */ - clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); + clk_provider_set_parent(clks[IMX6SX_CLK_CAN_SEL], + clks[IMX6SX_CLK_PLL3_60M]); /* Update gpu clock from default 528M to 720M */ - clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); - clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c index 0b0f6f6..8f7590a 100644 --- a/arch/arm/mach-imx/clk-pfd.c +++ b/arch/arm/mach-imx/clk-pfd.c @@ -128,11 +128,11 @@ static const struct clk_ops clk_pfd_ops = { .is_enabled = clk_pfd_is_enabled, }; -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_pfd *pfd; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index d21d14c..fbe33f3 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -97,11 +97,11 @@ static struct clk_ops clk_pllv1_ops = { .recalc_rate = clk_pllv1_recalc_rate, }; -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base) { struct clk_pllv1 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kmalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c index 20889d5..7882848 100644 --- a/arch/arm/mach-imx/clk-pllv2.c +++ b/arch/arm/mach-imx/clk-pllv2.c @@ -237,11 +237,11 @@ static struct clk_ops clk_pllv2_ops = { .set_rate = clk_pllv2_set_rate, }; -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base) { struct clk_pllv2 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index 6136405..3edcfdc 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -320,13 +320,13 @@ static const struct clk_ops clk_pllv3_enet_ops = { .recalc_rate = clk_pllv3_enet_recalc_rate, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) { struct clk_pllv3 *pll; const struct clk_ops *ops; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index f60d6d5..6604c02 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -95,7 +95,7 @@ static struct clk_div_table pll4_main_div_table[] = { { } }; -static struct clk *clk[VF610_CLK_END]; +static struct clk_core *clk[VF610_CLK_END]; static struct clk_onecell_data clk_data; static void __init vf610_clocks_init(struct device_node *ccm_node) @@ -307,20 +307,32 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) imx_check_clocks(clk, ARRAY_SIZE(clk)); - clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_QSPI0_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_QSPI1_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_SAI0_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI1_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI2_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI3_SEL], + clk[VF610_CLK_AUDIO_EXT]); /* Add the clocks to provider list */ clk_data.clks = clk; diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index df12b53..10a681e 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c @@ -7,7 +7,7 @@ DEFINE_SPINLOCK(imx_ccm_lock); -void __init imx_check_clocks(struct clk *clks[], unsigned int count) +void __init imx_check_clocks(struct clk_core *clks[], unsigned int count) { unsigned i; @@ -17,10 +17,10 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count) i, PTR_ERR(clks[i])); } -static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) +static struct clk_core * __init imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; - struct clk *clk = ERR_PTR(-ENODEV); + struct clk_core *clk = ERR_PTR(-ENODEV); char *path; path = kasprintf(GFP_KERNEL, "/clocks/%s", name); @@ -37,10 +37,10 @@ static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) return clk; } -struct clk * __init imx_obtain_fixed_clock( +struct clk_core * __init imx_obtain_fixed_clock( const char *name, unsigned long rate) { - struct clk *clk; + struct clk_core *clk; clk = imx_obtain_fixed_clock_from_dt(name); if (IS_ERR(clk)) diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index d5ba76f..0926889 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -6,14 +6,14 @@ extern spinlock_t imx_ccm_lock; -void imx_check_clocks(struct clk *clks[], unsigned int count); +void imx_check_clocks(struct clk_core *clks[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base); enum imx_pllv3_type { @@ -24,26 +24,26 @@ enum imx_pllv3_type { IMX_PLLV3_ENET, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); -struct clk * imx_obtain_fixed_clock( +struct clk_core * imx_obtain_fixed_clock( const char *name, unsigned long rate); -static inline struct clk *imx_clk_gate2(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock, NULL); } -static inline struct clk *imx_clk_gate2_shared(const char *name, +static inline struct clk_core *imx_clk_gate2_shared(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) { @@ -51,38 +51,38 @@ static inline struct clk *imx_clk_gate2_shared(const char *name, shift, 0, &imx_ccm_lock, share_count); } -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift); -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents); -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)); -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)); -static inline struct clk *imx_clk_fixed(const char *name, int rate) +static inline struct clk_core *imx_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *imx_clk_divider(const char *name, const char *parent, +static inline struct clk_core *imx_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_divider_flags(const char *name, +static inline struct clk_core *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) { @@ -90,21 +90,21 @@ static inline struct clk *imx_clk_divider_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_gate(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate_dis(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { return clk_register_mux(NULL, name, parents, num_parents, @@ -112,7 +112,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux_flags(const char *name, +static inline struct clk_core *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, unsigned long flags) { @@ -121,7 +121,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } -static inline struct clk *imx_clk_fixed_factor(const char *name, +static inline struct clk_core *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent, diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index 9a80449..14352c4 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -132,7 +132,7 @@ static int msm_clock_pcom_probe(struct platform_device *pdev) for (i = 0; i < pdata->num_lookups; i++) { const struct clk_pcom_desc *desc = &pdata->lookup[i]; - struct clk *c; + struct clk_core *c; struct clk_pcom *p; struct clk_hw *hw; struct clk_init_data init; diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index e6ac679..fee2643 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -164,7 +164,7 @@ void __init mv78xx0_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; static void __init clk_init(void) { diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index eb8c75e..b593f2b 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -107,7 +107,7 @@ static struct dpll_data dpll3_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll3_ck; +static struct clk_core dpll3_ck; static const char *dpll3_ck_parent_names[] = { "sys_ck", @@ -137,7 +137,7 @@ DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll3_m2_ck", @@ -158,7 +158,7 @@ DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0, OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk security_l4_ick2; +static struct clk_core security_l4_ick2; static const char *security_l4_ick2_parent_names[] = { "l4_ick", @@ -167,7 +167,7 @@ static const char *security_l4_ick2_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL); DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops); -static struct clk aes1_ick; +static struct clk_core aes1_ick; static const char *aes1_ick_parent_names[] = { "security_l4_ick2", @@ -190,7 +190,7 @@ static struct clk_hw_omap aes1_ick_hw = { DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk core_l4_ick; +static struct clk_core core_l4_ick; static const struct clk_ops core_l4_ick_ops = { .init = &omap2_init_clk_clkdm, @@ -199,7 +199,7 @@ static const struct clk_ops core_l4_ick_ops = { DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk aes2_ick; +static struct clk_core aes2_ick; static const char *aes2_ick_parent_names[] = { "core_l4_ick", @@ -224,7 +224,7 @@ static struct clk_hw_omap aes2_ick_hw = { DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk dpll1_fck; +static struct clk_core dpll1_fck; static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -248,7 +248,7 @@ static struct dpll_data dpll1_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll1_ck; +static struct clk_core dpll1_ck; static const struct clk_ops dpll1_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -279,7 +279,7 @@ DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0, OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_ck; +static struct clk_core mpu_ck; static const char *mpu_ck_parent_names[] = { "dpll1_x2m2_ck", @@ -293,7 +293,7 @@ DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0, OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH, 0x0, NULL); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -358,7 +358,7 @@ static struct dpll_data dpll4_dd_3630 __initdata = { .flags = DPLL_J_TYPE }; -static struct clk dpll4_ck; +static struct clk_core dpll4_ck; static const struct clk_ops dpll4_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -422,7 +422,7 @@ DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m5x2_ck; +static struct clk_core dpll4_m5x2_ck; static const char *dpll4_m5x2_ck_parent_names[] = { "dpll4_m5_ck", @@ -459,7 +459,7 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m5x2_ck_3630 = { +static struct clk_core dpll4_m5x2_ck_3630 = { .name = "dpll4_m5x2_ck", .hw = &dpll4_m5x2_ck_hw.hw, .parent_names = dpll4_m5x2_ck_parent_names, @@ -468,7 +468,7 @@ static struct clk dpll4_m5x2_ck_3630 = { .flags = CLK_SET_RATE_PARENT, }; -static struct clk cam_mclk; +static struct clk_core cam_mclk; static const char *cam_mclk_parent_names[] = { "dpll4_m5x2_ck", @@ -483,7 +483,7 @@ static struct clk_hw_omap cam_mclk_hw = { .clkdm_name = "cam_clkdm", }; -static struct clk cam_mclk = { +static struct clk_core cam_mclk = { .name = "cam_mclk", .hw = &cam_mclk_hw.hw, .parent_names = cam_mclk_parent_names, @@ -512,7 +512,7 @@ DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m2x2_ck; +static struct clk_core dpll4_m2x2_ck; static const char *dpll4_m2x2_ck_parent_names[] = { "dpll4_m2_ck", @@ -531,7 +531,7 @@ static struct clk_hw_omap dpll4_m2x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m2x2_ck_3630 = { +static struct clk_core dpll4_m2x2_ck_3630 = { .name = "dpll4_m2x2_ck", .hw = &dpll4_m2x2_ck_hw.hw, .parent_names = dpll4_m2x2_ck_parent_names, @@ -539,7 +539,7 @@ static struct clk dpll4_m2x2_ck_3630 = { .ops = &dpll4_m5x2_ck_3630_ops, }; -static struct clk omap_96m_alwon_fck; +static struct clk_core omap_96m_alwon_fck; static const char *omap_96m_alwon_fck_parent_names[] = { "dpll4_m2x2_ck", @@ -549,7 +549,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk cm_96m_fck; +static struct clk_core cm_96m_fck; static const char *cm_96m_fck_parent_names[] = { "omap_96m_alwon_fck", @@ -568,7 +568,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m3x2_ck; +static struct clk_core dpll4_m3x2_ck; static const char *dpll4_m3x2_ck_parent_names[] = { "dpll4_m3_ck", @@ -587,7 +587,7 @@ static struct clk_hw_omap dpll4_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m3x2_ck_3630 = { +static struct clk_core dpll4_m3x2_ck_3630 = { .name = "dpll4_m3x2_ck", .hw = &dpll4_m3x2_ck_hw.hw, .parent_names = dpll4_m3x2_ck_parent_names, @@ -651,7 +651,7 @@ static const char *omap_48m_fck_parent_names[] = { "cm_96m_fck", "sys_altclk", }; -static struct clk omap_48m_fck; +static struct clk_core omap_48m_fck; static const struct clk_ops omap_48m_fck_ops = { .recalc_rate = &omap2_clksel_recalc, @@ -672,7 +672,7 @@ DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops); DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4); -static struct clk core_12m_fck; +static struct clk_core core_12m_fck; static const char *core_12m_fck_parent_names[] = { "omap_12m_fck", @@ -681,7 +681,7 @@ static const char *core_12m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops); -static struct clk core_48m_fck; +static struct clk_core core_48m_fck; static const char *core_48m_fck_parent_names[] = { "omap_48m_fck", @@ -698,7 +698,7 @@ DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL); -static struct clk core_96m_fck; +static struct clk_core core_96m_fck; static const char *core_96m_fck_parent_names[] = { "omap_96m_fck", @@ -707,7 +707,7 @@ static const char *core_96m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops); -static struct clk core_l3_ick; +static struct clk_core core_l3_ick; static const char *core_l3_ick_parent_names[] = { "l3_ick", @@ -718,7 +718,7 @@ DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops); DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1); -static struct clk corex2_fck; +static struct clk_core corex2_fck; static const char *corex2_fck_parent_names[] = { "dpll3_m2x2_ck", @@ -727,7 +727,7 @@ static const char *corex2_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL); DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops); -static struct clk cpefuse_fck; +static struct clk_core cpefuse_fck; static struct clk_hw_omap cpefuse_fck_hw = { .hw = { @@ -740,7 +740,7 @@ static struct clk_hw_omap cpefuse_fck_hw = { DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk csi2_96m_fck; +static struct clk_core csi2_96m_fck; static const char *csi2_96m_fck_parent_names[] = { "core_96m_fck", @@ -757,7 +757,7 @@ static struct clk_hw_omap csi2_96m_fck_hw = { DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk d2d_26m_fck; +static struct clk_core d2d_26m_fck; static struct clk_hw_omap d2d_26m_fck_hw = { .hw = { @@ -771,7 +771,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = { DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk des1_ick; +static struct clk_core des1_ick; static struct clk_hw_omap des1_ick_hw = { .hw = { @@ -784,7 +784,7 @@ static struct clk_hw_omap des1_ick_hw = { DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk des2_ick; +static struct clk_core des2_ick; static struct clk_hw_omap des2_ick_hw = { .hw = { @@ -803,7 +803,7 @@ DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0, OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll2_fck; +static struct clk_core dpll2_fck; static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -828,7 +828,7 @@ static struct dpll_data dpll2_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll2_ck; +static struct clk_core dpll2_ck; static struct clk_hw_omap dpll2_ck_hw = { .hw = { @@ -857,7 +857,7 @@ DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll3_m3x2_ck; +static struct clk_core dpll3_m3x2_ck; static const char *dpll3_m3x2_ck_parent_names[] = { "dpll3_m3_ck", @@ -876,7 +876,7 @@ static struct clk_hw_omap dpll3_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll3_m3x2_ck_3630 = { +static struct clk_core dpll3_m3x2_ck_3630 = { .name = "dpll3_m3x2_ck", .hw = &dpll3_m3x2_ck_hw.hw, .parent_names = dpll3_m3x2_ck_parent_names, @@ -891,7 +891,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m4x2_ck; +static struct clk_core dpll4_m4x2_ck; static const char *dpll4_m4x2_ck_parent_names[] = { "dpll4_m4_ck", @@ -911,7 +911,7 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m4x2_ck_3630 = { +static struct clk_core dpll4_m4x2_ck_3630 = { .name = "dpll4_m4x2_ck", .hw = &dpll4_m4x2_ck_hw.hw, .parent_names = dpll4_m4x2_ck_parent_names, @@ -925,7 +925,7 @@ DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m6x2_ck; +static struct clk_core dpll4_m6x2_ck; static const char *dpll4_m6x2_ck_parent_names[] = { "dpll4_m6_ck", @@ -944,7 +944,7 @@ static struct clk_hw_omap dpll4_m6x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m6x2_ck_3630 = { +static struct clk_core dpll4_m6x2_ck_3630 = { .name = "dpll4_m6x2_ck", .hw = &dpll4_m6x2_ck_hw.hw, .parent_names = dpll4_m6x2_ck_parent_names, @@ -976,7 +976,7 @@ static struct dpll_data dpll5_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll5_ck; +static struct clk_core dpll5_ck; static struct clk_hw_omap dpll5_ck_hw = { .hw = { @@ -994,7 +994,7 @@ DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0, OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dss1_alwon_fck_3430es1; +static struct clk_core dss1_alwon_fck_3430es1; static const char *dss1_alwon_fck_3430es1_parent_names[] = { "dpll4_m4x2_ck", @@ -1013,7 +1013,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss1_alwon_fck_3430es2; +static struct clk_core dss1_alwon_fck_3430es2; static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = { .hw = { @@ -1029,7 +1029,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss2_alwon_fck; +static struct clk_core dss2_alwon_fck; static struct clk_hw_omap dss2_alwon_fck_hw = { .hw = { @@ -1042,7 +1042,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = { DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk dss_96m_fck; +static struct clk_core dss_96m_fck; static struct clk_hw_omap dss_96m_fck_hw = { .hw = { @@ -1055,7 +1055,7 @@ static struct clk_hw_omap dss_96m_fck_hw = { DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es1; +static struct clk_core dss_ick_3430es1; static struct clk_hw_omap dss_ick_3430es1_hw = { .hw = { @@ -1069,7 +1069,7 @@ static struct clk_hw_omap dss_ick_3430es1_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es2; +static struct clk_core dss_ick_3430es2; static struct clk_hw_omap dss_ick_3430es2_hw = { .hw = { @@ -1083,7 +1083,7 @@ static struct clk_hw_omap dss_ick_3430es2_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_tv_fck; +static struct clk_core dss_tv_fck; static const char *dss_tv_fck_parent_names[] = { "omap_54m_fck", @@ -1100,7 +1100,7 @@ static struct clk_hw_omap dss_tv_fck_hw = { DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops); -static struct clk emac_fck; +static struct clk_core emac_fck; static const char *emac_fck_parent_names[] = { "rmii_ck", @@ -1116,7 +1116,7 @@ static struct clk_hw_omap emac_fck_hw = { DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops); -static struct clk ipss_ick; +static struct clk_core ipss_ick; static const char *ipss_ick_parent_names[] = { "core_l3_ick", @@ -1134,7 +1134,7 @@ static struct clk_hw_omap ipss_ick_hw = { DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops); -static struct clk emac_ick; +static struct clk_core emac_ick; static const char *emac_ick_parent_names[] = { "ipss_ick", @@ -1152,7 +1152,7 @@ static struct clk_hw_omap emac_ick_hw = { DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk emu_core_alwon_ck; +static struct clk_core emu_core_alwon_ck; static const char *emu_core_alwon_ck_parent_names[] = { "dpll3_m3x2_ck", @@ -1162,7 +1162,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm"); DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names, core_l4_ick_ops); -static struct clk emu_mpu_alwon_ck; +static struct clk_core emu_mpu_alwon_ck; static const char *emu_mpu_alwon_ck_parent_names[] = { "mpu_ck", @@ -1171,7 +1171,7 @@ static const char *emu_mpu_alwon_ck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL); DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops); -static struct clk emu_per_alwon_ck; +static struct clk_core emu_per_alwon_ck; static const char *emu_per_alwon_ck_parent_names[] = { "dpll4_m6x2_ck", @@ -1222,7 +1222,7 @@ static const struct clk_ops emu_src_ck_ops = { .disable = &omap2_clkops_disable_clkdm, }; -static struct clk emu_src_ck; +static struct clk_core emu_src_ck; static struct clk_hw_omap emu_src_ck_hw = { .hw = { @@ -1241,7 +1241,7 @@ DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -1255,7 +1255,7 @@ static struct clk_hw_omap fac_ick_hw = { DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk fshostusb_fck; +static struct clk_core fshostusb_fck; static const char *fshostusb_fck_parent_names[] = { "core_48m_fck", @@ -1273,7 +1273,7 @@ static struct clk_hw_omap fshostusb_fck_hw = { DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ck; +static struct clk_core gfx_l3_ck; static struct clk_hw_omap gfx_l3_ck_hw = { .hw = { @@ -1292,7 +1292,7 @@ DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0, OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk gfx_cg1_ck; +static struct clk_core gfx_cg1_ck; static const char *gfx_cg1_ck_parent_names[] = { "gfx_l3_fck", @@ -1310,7 +1310,7 @@ static struct clk_hw_omap gfx_cg1_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_cg2_ck; +static struct clk_core gfx_cg2_ck; static struct clk_hw_omap gfx_cg2_ck_hw = { .hw = { @@ -1324,7 +1324,7 @@ static struct clk_hw_omap gfx_cg2_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ick; +static struct clk_core gfx_l3_ick; static const char *gfx_l3_ick_parent_names[] = { "gfx_l3_ck", @@ -1333,7 +1333,7 @@ static const char *gfx_l3_ick_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm"); DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops); -static struct clk wkup_32k_fck; +static struct clk_core wkup_32k_fck; static const char *wkup_32k_fck_parent_names[] = { "omap_32k_fck", @@ -1342,7 +1342,7 @@ static const char *wkup_32k_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio1_dbck; +static struct clk_core gpio1_dbck; static const char *gpio1_dbck_parent_names[] = { "wkup_32k_fck", @@ -1359,12 +1359,12 @@ static struct clk_hw_omap gpio1_dbck_hw = { DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wkup_l4_ick; +static struct clk_core wkup_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops); -static struct clk gpio1_ick; +static struct clk_core gpio1_ick; static const char *gpio1_ick_parent_names[] = { "wkup_l4_ick", @@ -1382,13 +1382,13 @@ static struct clk_hw_omap gpio1_ick_hw = { DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk per_32k_alwon_fck; +static struct clk_core per_32k_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio2_dbck; +static struct clk_core gpio2_dbck; static const char *gpio2_dbck_parent_names[] = { "per_32k_alwon_fck", @@ -1405,12 +1405,12 @@ static struct clk_hw_omap gpio2_dbck_hw = { DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk per_l4_ick; +static struct clk_core per_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm"); DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk gpio2_ick; +static struct clk_core gpio2_ick; static const char *gpio2_ick_parent_names[] = { "per_l4_ick", @@ -1428,7 +1428,7 @@ static struct clk_hw_omap gpio2_ick_hw = { DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio3_dbck; +static struct clk_core gpio3_dbck; static struct clk_hw_omap gpio3_dbck_hw = { .hw = { @@ -1441,7 +1441,7 @@ static struct clk_hw_omap gpio3_dbck_hw = { DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio3_ick; +static struct clk_core gpio3_ick; static struct clk_hw_omap gpio3_ick_hw = { .hw = { @@ -1455,7 +1455,7 @@ static struct clk_hw_omap gpio3_ick_hw = { DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio4_dbck; +static struct clk_core gpio4_dbck; static struct clk_hw_omap gpio4_dbck_hw = { .hw = { @@ -1468,7 +1468,7 @@ static struct clk_hw_omap gpio4_dbck_hw = { DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio4_ick; +static struct clk_core gpio4_ick; static struct clk_hw_omap gpio4_ick_hw = { .hw = { @@ -1482,7 +1482,7 @@ static struct clk_hw_omap gpio4_ick_hw = { DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio5_dbck; +static struct clk_core gpio5_dbck; static struct clk_hw_omap gpio5_dbck_hw = { .hw = { @@ -1495,7 +1495,7 @@ static struct clk_hw_omap gpio5_dbck_hw = { DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio5_ick; +static struct clk_core gpio5_ick; static struct clk_hw_omap gpio5_ick_hw = { .hw = { @@ -1509,7 +1509,7 @@ static struct clk_hw_omap gpio5_ick_hw = { DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio6_dbck; +static struct clk_core gpio6_dbck; static struct clk_hw_omap gpio6_dbck_hw = { .hw = { @@ -1522,7 +1522,7 @@ static struct clk_hw_omap gpio6_dbck_hw = { DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio6_ick; +static struct clk_core gpio6_ick; static struct clk_hw_omap gpio6_ick_hw = { .hw = { @@ -1536,7 +1536,7 @@ static struct clk_hw_omap gpio6_ick_hw = { DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -1565,7 +1565,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -1586,7 +1586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -1600,7 +1600,7 @@ static struct clk_hw_omap gpt11_ick_hw = { DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk gpt12_fck; +static struct clk_core gpt12_fck; static const char *gpt12_fck_parent_names[] = { "secure_32k_fck", @@ -1609,7 +1609,7 @@ static const char *gpt12_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -1630,7 +1630,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -1651,7 +1651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -1672,7 +1672,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -1693,7 +1693,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -1714,7 +1714,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -1735,7 +1735,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -1756,7 +1756,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -1777,7 +1777,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -1798,7 +1798,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -1812,7 +1812,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static const char *hdq_fck_parent_names[] = { "core_12m_fck", @@ -1830,7 +1830,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -1844,7 +1844,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk hecc_ck; +static struct clk_core hecc_ck; static struct clk_hw_omap hecc_ck_hw = { .hw = { @@ -1858,7 +1858,7 @@ static struct clk_hw_omap hecc_ck_hw = { DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_fck_am35xx; +static struct clk_core hsotgusb_fck_am35xx; static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { .hw = { @@ -1871,7 +1871,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es1; +static struct clk_core hsotgusb_ick_3430es1; static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { .hw = { @@ -1885,7 +1885,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es2; +static struct clk_core hsotgusb_ick_3430es2; static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { .hw = { @@ -1899,7 +1899,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_am35xx; +static struct clk_core hsotgusb_ick_am35xx; static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { .hw = { @@ -1913,7 +1913,7 @@ static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops); -static struct clk i2c1_fck; +static struct clk_core i2c1_fck; static struct clk_hw_omap i2c1_fck_hw = { .hw = { @@ -1927,7 +1927,7 @@ static struct clk_hw_omap i2c1_fck_hw = { DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -1941,7 +1941,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c2_fck; +static struct clk_core i2c2_fck; static struct clk_hw_omap i2c2_fck_hw = { .hw = { @@ -1955,7 +1955,7 @@ static struct clk_hw_omap i2c2_fck_hw = { DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -1969,7 +1969,7 @@ static struct clk_hw_omap i2c2_ick_hw = { DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c3_fck; +static struct clk_core i2c3_fck; static struct clk_hw_omap i2c3_fck_hw = { .hw = { @@ -1983,7 +1983,7 @@ static struct clk_hw_omap i2c3_fck_hw = { DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c3_ick; +static struct clk_core i2c3_ick; static struct clk_hw_omap i2c3_ick_hw = { .hw = { @@ -1997,7 +1997,7 @@ static struct clk_hw_omap i2c3_ick_hw = { DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk icr_ick; +static struct clk_core icr_ick; static struct clk_hw_omap icr_ick_hw = { .hw = { @@ -2011,7 +2011,7 @@ static struct clk_hw_omap icr_ick_hw = { DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk iva2_ck; +static struct clk_core iva2_ck; static const char *iva2_ck_parent_names[] = { "dpll2_m2_ck", @@ -2029,7 +2029,7 @@ static struct clk_hw_omap iva2_ck_hw = { DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops); -static struct clk mad2d_ick; +static struct clk_core mad2d_ick; static struct clk_hw_omap mad2d_ick_hw = { .hw = { @@ -2043,7 +2043,7 @@ static struct clk_hw_omap mad2d_ick_hw = { DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -2084,7 +2084,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -2098,7 +2098,7 @@ static struct clk_hw_omap mcbsp1_ick_hw = { DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk per_96m_fck; +static struct clk_core per_96m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops); @@ -2120,7 +2120,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -2141,7 +2141,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp3_ick; +static struct clk_core mcbsp3_ick; static struct clk_hw_omap mcbsp3_ick_hw = { .hw = { @@ -2162,7 +2162,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp4_ick; +static struct clk_core mcbsp4_ick; static struct clk_hw_omap mcbsp4_ick_hw = { .hw = { @@ -2183,7 +2183,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp5_ick; +static struct clk_core mcbsp5_ick; static struct clk_hw_omap mcbsp5_ick_hw = { .hw = { @@ -2197,7 +2197,7 @@ static struct clk_hw_omap mcbsp5_ick_hw = { DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static struct clk_hw_omap mcspi1_fck_hw = { .hw = { @@ -2211,7 +2211,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -2225,7 +2225,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -2239,7 +2239,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -2253,7 +2253,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi3_fck; +static struct clk_core mcspi3_fck; static struct clk_hw_omap mcspi3_fck_hw = { .hw = { @@ -2267,7 +2267,7 @@ static struct clk_hw_omap mcspi3_fck_hw = { DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi3_ick; +static struct clk_core mcspi3_ick; static struct clk_hw_omap mcspi3_ick_hw = { .hw = { @@ -2281,7 +2281,7 @@ static struct clk_hw_omap mcspi3_ick_hw = { DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi4_fck; +static struct clk_core mcspi4_fck; static struct clk_hw_omap mcspi4_fck_hw = { .hw = { @@ -2295,7 +2295,7 @@ static struct clk_hw_omap mcspi4_fck_hw = { DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi4_ick; +static struct clk_core mcspi4_ick; static struct clk_hw_omap mcspi4_ick_hw = { .hw = { @@ -2309,7 +2309,7 @@ static struct clk_hw_omap mcspi4_ick_hw = { DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs1_fck; +static struct clk_core mmchs1_fck; static struct clk_hw_omap mmchs1_fck_hw = { .hw = { @@ -2323,7 +2323,7 @@ static struct clk_hw_omap mmchs1_fck_hw = { DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs1_ick; +static struct clk_core mmchs1_ick; static struct clk_hw_omap mmchs1_ick_hw = { .hw = { @@ -2337,7 +2337,7 @@ static struct clk_hw_omap mmchs1_ick_hw = { DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs2_fck; +static struct clk_core mmchs2_fck; static struct clk_hw_omap mmchs2_fck_hw = { .hw = { @@ -2351,7 +2351,7 @@ static struct clk_hw_omap mmchs2_fck_hw = { DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs2_ick; +static struct clk_core mmchs2_ick; static struct clk_hw_omap mmchs2_ick_hw = { .hw = { @@ -2365,7 +2365,7 @@ static struct clk_hw_omap mmchs2_ick_hw = { DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs3_fck; +static struct clk_core mmchs3_fck; static struct clk_hw_omap mmchs3_fck_hw = { .hw = { @@ -2379,7 +2379,7 @@ static struct clk_hw_omap mmchs3_fck_hw = { DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs3_ick; +static struct clk_core mmchs3_ick; static struct clk_hw_omap mmchs3_ick_hw = { .hw = { @@ -2393,7 +2393,7 @@ static struct clk_hw_omap mmchs3_ick_hw = { DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk modem_fck; +static struct clk_core modem_fck; static struct clk_hw_omap modem_fck_hw = { .hw = { @@ -2407,7 +2407,7 @@ static struct clk_hw_omap modem_fck_hw = { DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -2421,7 +2421,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -2435,13 +2435,13 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk omap_192m_alwon_fck; +static struct clk_core omap_192m_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk omap_32ksync_ick; +static struct clk_core omap_32ksync_ick; static struct clk_hw_omap omap_32ksync_ick_hw = { .hw = { @@ -2466,7 +2466,7 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = { { .parent = NULL } }; -static struct clk omap_96m_alwon_fck_3630; +static struct clk_core omap_96m_alwon_fck_3630; static const char *omap_96m_alwon_fck_3630_parent_names[] = { "omap_192m_alwon_fck", @@ -2487,7 +2487,7 @@ static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = { .clksel_mask = OMAP3630_CLKSEL_96M_MASK, }; -static struct clk omap_96m_alwon_fck_3630 = { +static struct clk_core omap_96m_alwon_fck_3630 = { .name = "omap_96m_alwon_fck", .hw = &omap_96m_alwon_fck_3630_hw.hw, .parent_names = omap_96m_alwon_fck_3630_parent_names, @@ -2495,7 +2495,7 @@ static struct clk omap_96m_alwon_fck_3630 = { .ops = &omap_96m_alwon_fck_3630_ops, }; -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -2520,17 +2520,17 @@ DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk per_48m_fck; +static struct clk_core per_48m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops); -static struct clk security_l3_ick; +static struct clk_core security_l3_ick; DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL); DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static const char *pka_ick_parent_names[] = { "security_l3_ick", @@ -2552,7 +2552,7 @@ DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0, OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -2565,7 +2565,7 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sad2d_ick; +static struct clk_core sad2d_ick; static struct clk_hw_omap sad2d_ick_hw = { .hw = { @@ -2579,7 +2579,7 @@ static struct clk_hw_omap sad2d_ick_hw = { DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -2630,7 +2630,7 @@ static const char *sgx_fck_parent_names[] = { "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck", }; -static struct clk sgx_fck; +static struct clk_core sgx_fck; static const struct clk_ops sgx_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -2651,7 +2651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel, OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops); -static struct clk sgx_ick; +static struct clk_core sgx_ick; static struct clk_hw_omap sgx_ick_hw = { .hw = { @@ -2665,7 +2665,7 @@ static struct clk_hw_omap sgx_ick_hw = { DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sha11_ick; +static struct clk_core sha11_ick; static struct clk_hw_omap sha11_ick_hw = { .hw = { @@ -2678,7 +2678,7 @@ static struct clk_hw_omap sha11_ick_hw = { DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sha12_ick; +static struct clk_core sha12_ick; static struct clk_hw_omap sha12_ick_hw = { .hw = { @@ -2692,7 +2692,7 @@ static struct clk_hw_omap sha12_ick_hw = { DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk sr1_fck; +static struct clk_core sr1_fck; static struct clk_hw_omap sr1_fck_hw = { .hw = { @@ -2706,7 +2706,7 @@ static struct clk_hw_omap sr1_fck_hw = { DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr2_fck; +static struct clk_core sr2_fck; static struct clk_hw_omap sr2_fck_hw = { .hw = { @@ -2720,17 +2720,17 @@ static struct clk_hw_omap sr2_fck_hw = { DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr_l4_ick; +static struct clk_core sr_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_ick_3430es1; +static struct clk_core ssi_ick_3430es1; static const char *ssi_ick_3430es1_parent_names[] = { "ssi_l4_ick", @@ -2748,7 +2748,7 @@ static struct clk_hw_omap ssi_ick_3430es1_hw = { DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops); -static struct clk ssi_ick_3430es2; +static struct clk_core ssi_ick_3430es2; static struct clk_hw_omap ssi_ick_3430es2_hw = { .hw = { @@ -2813,7 +2813,7 @@ DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1", DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2", &ssi_ssr_fck_3430es2, 0x0, 1, 2); -static struct clk sys_clkout1; +static struct clk_core sys_clkout1; static const char *sys_clkout1_parent_names[] = { "osc_sys_ck", @@ -2843,7 +2843,7 @@ DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0, OMAP3430_CLKSEL_TRACECLK_SHIFT, OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk ts_fck; +static struct clk_core ts_fck; static struct clk_hw_omap ts_fck_hw = { .hw = { @@ -2856,7 +2856,7 @@ static struct clk_hw_omap ts_fck_hw = { DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -2870,7 +2870,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -2884,7 +2884,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -2898,7 +2898,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -2912,7 +2912,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static const char *uart3_fck_parent_names[] = { "per_48m_fck", @@ -2930,7 +2930,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -2944,7 +2944,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_fck; +static struct clk_core uart4_fck; static struct clk_hw_omap uart4_fck_hw = { .hw = { @@ -2958,7 +2958,7 @@ static struct clk_hw_omap uart4_fck_hw = { DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart4_fck_am35xx; +static struct clk_core uart4_fck_am35xx; static struct clk_hw_omap uart4_fck_am35xx_hw = { .hw = { @@ -2972,7 +2972,7 @@ static struct clk_hw_omap uart4_fck_am35xx_hw = { DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart4_ick; +static struct clk_core uart4_ick; static struct clk_hw_omap uart4_ick_hw = { .hw = { @@ -2986,7 +2986,7 @@ static struct clk_hw_omap uart4_ick_hw = { DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_ick_am35xx; +static struct clk_core uart4_ick_am35xx; static struct clk_hw_omap uart4_ick_am35xx_hw = { .hw = { @@ -3023,7 +3023,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel, &clkhwops_iclk_wait, usb_l4_ick_parent_names, ssi_ssr_fck_3430es1_ops); -static struct clk usbhost_120m_fck; +static struct clk_core usbhost_120m_fck; static const char *usbhost_120m_fck_parent_names[] = { "dpll5_m2_ck", @@ -3041,7 +3041,7 @@ static struct clk_hw_omap usbhost_120m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_48m_fck; +static struct clk_core usbhost_48m_fck; static struct clk_hw_omap usbhost_48m_fck_hw = { .hw = { @@ -3055,7 +3055,7 @@ static struct clk_hw_omap usbhost_48m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_ick; +static struct clk_core usbhost_ick; static struct clk_hw_omap usbhost_ick_hw = { .hw = { @@ -3069,7 +3069,7 @@ static struct clk_hw_omap usbhost_ick_hw = { DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk usbtll_fck; +static struct clk_core usbtll_fck; static struct clk_hw_omap usbtll_fck_hw = { .hw = { @@ -3083,7 +3083,7 @@ static struct clk_hw_omap usbtll_fck_hw = { DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbtll_ick; +static struct clk_core usbtll_ick; static struct clk_hw_omap usbtll_ick_hw = { .hw = { @@ -3124,7 +3124,7 @@ static const char *usim_fck_parent_names[] = { "omap_96m_fck", "dpll5_m2_ck", "sys_ck", }; -static struct clk usim_fck; +static struct clk_core usim_fck; static const struct clk_ops usim_fck_ops = { .enable = &omap2_dflt_clk_enable, @@ -3142,7 +3142,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel, OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait, usim_fck_parent_names, usim_fck_ops); -static struct clk usim_ick; +static struct clk_core usim_ick; static struct clk_hw_omap usim_ick_hw = { .hw = { @@ -3156,7 +3156,7 @@ static struct clk_hw_omap usim_ick_hw = { DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk vpfe_fck; +static struct clk_core vpfe_fck; static const char *vpfe_fck_parent_names[] = { "pclk_ck", @@ -3172,7 +3172,7 @@ static struct clk_hw_omap vpfe_fck_hw = { DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops); -static struct clk vpfe_ick; +static struct clk_core vpfe_ick; static struct clk_hw_omap vpfe_ick_hw = { .hw = { @@ -3186,12 +3186,12 @@ static struct clk_hw_omap vpfe_ick_hw = { DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk wdt1_fck; +static struct clk_core wdt1_fck; DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -3205,7 +3205,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt2_fck; +static struct clk_core wdt2_fck; static struct clk_hw_omap wdt2_fck_hw = { .hw = { @@ -3219,7 +3219,7 @@ static struct clk_hw_omap wdt2_fck_hw = { DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wdt2_ick; +static struct clk_core wdt2_ick; static struct clk_hw_omap wdt2_ick_hw = { .hw = { @@ -3233,7 +3233,7 @@ static struct clk_hw_omap wdt2_ick_hw = { DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt3_fck; +static struct clk_core wdt3_fck; static struct clk_hw_omap wdt3_fck_hw = { .hw = { @@ -3247,7 +3247,7 @@ static struct clk_hw_omap wdt3_fck_hw = { DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk wdt3_ick; +static struct clk_core wdt3_ick; static struct clk_hw_omap wdt3_ick_hw = { .hw = { @@ -3661,10 +3661,10 @@ int __init omap3xxx_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&osc_sys_ck) / 1000000), - (clk_get_rate(&osc_sys_ck) / 100000) % 10, - (clk_get_rate(&core_ck) / 1000000), - (clk_get_rate(&arm_fck) / 1000000)); + (clk_provider_get_rate(&osc_sys_ck) / 1000000), + (clk_provider_get_rate(&osc_sys_ck) / 100000) % 10, + (clk_provider_get_rate(&core_ck) / 1000000), + (clk_provider_get_rate(&arm_fck) / 1000000)); /* * Lock DPLL5 -- here only until other device init code can @@ -3674,8 +3674,8 @@ int __init omap3xxx_clk_init(void) omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ - sdrc_ick_p = clk_get(NULL, "sdrc_ick"); - arm_fck_p = clk_get(NULL, "arm_fck"); + sdrc_ick_p = clk_provider_get(NULL, "sdrc_ick"); + arm_fck_p = clk_provider_get(NULL, "arm_fck"); return 0; } diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 82572e2..28a6d42 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -22,7 +22,7 @@ /** * _allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. The DPLL will enter low-power * stop when its downstream clocks are gated. No return value. @@ -39,7 +39,7 @@ static void _allow_idle(struct clk_hw_omap *clk) /** * _deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 59cf310..6723d916 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -48,7 +48,7 @@ static struct clk_hw_omap *dpll_core_ck; * Returns the CORE_CLK rate. CORE_CLK can have one of three rate * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz * (the latter is unusual). This currently should be called with - * struct clk *dpll_ck, which is a composite clock of dpll_ck and + * struct clk_core *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ unsigned long omap2xxx_clk_get_core_rate(void) @@ -179,7 +179,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, /** * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck - * @clk: struct clk *dpll_ck + * @clk: struct clk_core *dpll_ck * * Store a local copy of @clk in dpll_core_ck so other code can query * the core rate without having to clk_get(), which can sleep. Must diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 85e0b0c0..67014e1 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -198,14 +198,14 @@ void omap2xxx_clkt_vps_check_bootloader_rates(void) */ void omap2xxx_clkt_vps_late_init(void) { - struct clk *c; + struct clk_core *c; - c = clk_get(NULL, "sys_ck"); + c = clk_provider_get(NULL, "sys_ck"); if (IS_ERR(c)) { WARN(1, "could not locate sys_ck\n"); } else { - sys_ck_rate = clk_get_rate(c); - clk_put(c); + sys_ck_rate = clk_provider_get_rate(c); + __clk_put(c); } } @@ -230,7 +230,7 @@ void omap2xxx_clkt_vps_init(void) { struct clk_init_data init = { NULL }; struct clk_hw_omap *hw = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name = "mpu_ck"; struct clk_lookup *lookup = NULL; diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index eb69acf..9e96363 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -38,7 +38,7 @@ /** * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Program the DPLL M2 divider with the rounded target rate. Returns diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 7ee2610..b4796b3 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -51,15 +51,15 @@ /** * _get_clksel_by_parent() - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for + * @clk: OMAP struct clk_core ptr to inspect + * @src_clk: OMAP struct clk_core ptr of the parent clk to search for * * Scan the struct clksel array associated with the clock to find * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, - struct clk *src_clk) + struct clk_core *src_clk) { const struct clksel *clks; @@ -82,7 +82,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, /** * _write_clksel_reg() - program a clock's clksel register in hardware - * @clk: struct clk * to program + * @clk: struct clk_core * to program * @v: clksel bitfield value to program (with LSB at bit 0) * * Shift the clksel register bitfield value @v to its appropriate @@ -107,10 +107,10 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) /** * _clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @field_val: register field value to find * - * Given a struct clk of a rate-selectable clksel clock, and a register field + * Given a struct clk_core of a rate-selectable clksel clock, and a register field * value to search for, find the corresponding clock divisor. The register * field value should be pre-masked and shifted down so the LSB is at bit 0 * before calling. Returns 0 on error or returns the actual integer divisor @@ -120,7 +120,7 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; parent = __clk_get_parent(clk->hw.clk); @@ -149,10 +149,10 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) /** * _divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @div: integer divisor to search for * - * Given a struct clk of a rate-selectable clksel clock, and a clock + * Given a struct clk_core of a rate-selectable clksel clock, and a clock * divisor, find the corresponding register field value. Returns the * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. @@ -161,7 +161,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; /* should never happen */ WARN_ON(div == 0); @@ -191,7 +191,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) /** * _read_divisor() - get current divisor applied to parent clock (from hdwr) - * @clk: OMAP struct clk to use. + * @clk: OMAP struct clk_core to use. * * Read the current divisor register value for @clk that is programmed * into the hardware, convert it into the actual divisor value, and @@ -215,7 +215,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk) /** * omap2_clksel_round_rate_div() - find divisor for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * @new_div: ptr to where we should store the divisor * @@ -233,7 +233,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, const struct clksel *clks; const struct clksel_rate *clkr; u32 last_div = 0; - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; const char *clk_name; @@ -286,7 +286,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, /* * Clocktype interface functions to the OMAP clock code - * (i.e., those used in struct clk field function pointers, etc.) + * (i.e., those used in struct clk_core field function pointers, etc.) */ /** @@ -309,7 +309,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) const struct clksel *clks; const struct clksel_rate *clkr; u32 r, found = 0; - struct clk *parent; + struct clk_core *parent; const char *clk_name; int ret = 0, f = 0; @@ -345,11 +345,11 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) /** - * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field - * @clk: struct clk * + * omap2_clksel_recalc() - function ptr to pass via struct clk_core .recalc field + * @clk: struct clk_core * * * This function is intended to be called only by the clock framework. - * Each clksel clock should have its struct clk .recalc field set to this + * Each clksel clock should have its struct clk_core .recalc field set to this * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ @@ -376,7 +376,7 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * * This function is intended to be called only by the clock framework. @@ -396,7 +396,7 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, /** * omap2_clksel_set_rate() - program clock rate in hardware - * @clk: struct clk * to program rate + * @clk: struct clk_core * to program rate * @rate: target rate to program * * This function is intended to be called only by the clock framework. @@ -435,7 +435,7 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, } /* - * Clksel parent setting function - not passed in struct clk function + * Clksel parent setting function - not passed in struct clk_core function * pointer - instead, the OMAP clock code currently assumes that any * parent-setting clock is a clksel clock, and calls * omap2_clksel_set_parent() by default @@ -443,8 +443,8 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap2_clksel_set_parent() - change a clock's parent clock - * @clk: struct clk * of the child clock - * @new_parent: struct clk * of the new parent clock + * @clk: struct clk_core * of the child clock + * @new_parent: struct clk_core * of the new parent clock * * This function is intended to be called only by the clock framework. * Change the parent clock of clock @clk to @new_parent. This is diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index f251a14..36f263d 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -56,7 +56,7 @@ /* * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test + * @clk: DPLL struct clk_core to test * @n: divider value (N) to test * * Tests whether a particular divider @n will result in a valid DPLL @@ -215,7 +215,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - /* Reparent the struct clk in case the dpll is in bypass */ + /* Reparent the struct clk_core in case the dpll is in bypass */ if (_omap2_dpll_is_in_bypass(v)) return 1; @@ -224,7 +224,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) /** * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL + * @clk: struct clk_core * of a DPLL * * DPLLs can be locked or bypassed - basically, enabled or disabled. * When locked, the DPLL output depends on the M and N values. When @@ -270,7 +270,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) /** * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL + * @clk: struct clk_core * for a DPLL * @target_rate: desired DPLL clock rate * * Given a DPLL and a desired target rate, round the target rate to a diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 500530d..ab341e4 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -142,7 +142,7 @@ static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, /** * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module + * @clk: struct clk_core * belonging to the module * * If the necessary clocks for the OMAP hardware IP block that * corresponds to clock @clk are enabled, then wait for the module to @@ -181,7 +181,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use * - * Convert a clockdomain name stored in a struct clk 'clk' into a + * Convert a clockdomain name stored in a struct clk_core 'clk' into a * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ @@ -222,7 +222,7 @@ void __init omap2_clk_disable_clkdm_control(void) /** * omap2_clk_dflt_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of + * @clk: struct clk_core * to find the companion clock of * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in * @other_bit: u8 ** to return the companion clock bit shift in * @@ -258,7 +258,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, /** * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk - * @clk: struct clk * to find IDLEST info for + * @clk: struct clk_core * to find IDLEST info for * @idlest_reg: void __iomem ** to return the CM_IDLEST va in * @idlest_bit: u8 * to return the CM_IDLEST bit shift in * @idlest_val: u8 * to return the idle status indicator @@ -502,14 +502,14 @@ __setup("mpurate=", omap_clk_setup); /** * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock - * @clk: struct clk * to initialize + * @clk: struct clk_core * to initialize * * Add an OMAP clock @clk to the internal list of OMAP clocks. Used * temporarily for autoidle handling, until this support can be * integrated into the common clock framework code in some way. No * return value. */ -void omap2_init_clk_hw_omap_clocks(struct clk *clk) +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk) { struct clk_hw_omap *c; @@ -566,11 +566,11 @@ int omap2_clk_disable_autoidle_all(void) /** * omap2_clk_deny_idle - disable autoidle on an OMAP clock - * @clk: struct clk * to disable autoidle for + * @clk: struct clk_core * to disable autoidle for * * Disable autoidle on an OMAP clock. */ -int omap2_clk_deny_idle(struct clk *clk) +int omap2_clk_deny_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -585,11 +585,11 @@ int omap2_clk_deny_idle(struct clk *clk) /** * omap2_clk_allow_idle - enable autoidle on an OMAP clock - * @clk: struct clk * to enable autoidle for + * @clk: struct clk_core * to enable autoidle for * * Enable autoidle on an OMAP clock. */ -int omap2_clk_allow_idle(struct clk *clk) +int omap2_clk_allow_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -614,12 +614,12 @@ int omap2_clk_allow_idle(struct clk *clk) */ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) { - struct clk *init_clk; + struct clk_core *init_clk; int i; for (i = 0; i < num_clocks; i++) { - init_clk = clk_get(NULL, clk_names[i]); - clk_prepare_enable(init_clk); + init_clk = clk_provider_get(NULL, clk_names[i]); + clk_provider_prepare_enable(init_clk); } } @@ -655,31 +655,31 @@ void __init omap_clocks_register(struct omap_clk oclks[], int cnt) * the OPP layer. XXX This is intended to be handled by the OPP layer * code in the near future and should be removed from the clock code. * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects - * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name + * the rate, -ENOENT if the struct clk_core referred to by @mpurate_ck_name * cannot be found, or 0 upon success. */ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) { - struct clk *mpurate_ck; + struct clk_core *mpurate_ck; int r; if (!mpurate) return -EINVAL; - mpurate_ck = clk_get(NULL, mpurate_ck_name); + mpurate_ck = clk_provider_get(NULL, mpurate_ck_name); if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) return -ENOENT; - r = clk_set_rate(mpurate_ck, mpurate); + r = clk_provider_set_rate(mpurate_ck, mpurate); if (r < 0) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", mpurate_ck_name, mpurate, r); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return 0; } @@ -700,27 +700,27 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name) { - struct clk *hfclkin_ck, *core_ck, *mpu_ck; + struct clk_core *hfclkin_ck, *core_ck, *mpu_ck; unsigned long hfclkin_rate; - mpu_ck = clk_get(NULL, mpu_ck_name); + mpu_ck = clk_provider_get(NULL, mpu_ck_name); if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) return; - core_ck = clk_get(NULL, core_ck_name); + core_ck = clk_provider_get(NULL, core_ck_name); if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) return; - hfclkin_ck = clk_get(NULL, hfclkin_ck_name); + hfclkin_ck = clk_provider_get(NULL, hfclkin_ck_name); if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) return; - hfclkin_rate = clk_get_rate(hfclkin_ck); + hfclkin_rate = clk_provider_get_rate(hfclkin_ck); pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), - (clk_get_rate(core_ck) / 1000000), - (clk_get_rate(mpu_ck) / 1000000)); + (clk_provider_get_rate(core_ck) / 1000000), + (clk_provider_get_rate(mpu_ck) / 1000000)); } /** diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 4592a27..7068684 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -40,7 +40,7 @@ struct omap_clk { struct clockdomain; #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -50,7 +50,7 @@ struct clockdomain; #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ _clkops_name, _flags) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -70,7 +70,7 @@ struct clockdomain; #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ _clksel_reg, _clksel_mask, \ _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -86,7 +86,7 @@ struct clockdomain; _clksel_reg, _clksel_mask, \ _enable_reg, _enable_bit, \ _hwops, _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -142,14 +142,14 @@ struct clksel_rate { /** * struct clksel - available parent clocks, and a pointer to their divisors - * @parent: struct clk * to a possible parent clock + * @parent: struct clk_core * to a possible parent clock * @rates: available divisors for this parent clock * * A struct clksel is always associated with one or more struct clks * and one or more struct clksel_rates. */ struct clksel { - struct clk *parent; + struct clk_core *parent; const struct clksel_rate *rates; }; @@ -208,8 +208,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); int omap2_clk_enable_autoidle_all(void); -int omap2_clk_allow_idle(struct clk *clk); -int omap2_clk_deny_idle(struct clk *clk); +int omap2_clk_allow_idle(struct clk_core *clk); +int omap2_clk_deny_idle(struct clk_core *clk); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -247,7 +247,7 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; -extern struct clk dummy_ck; +extern struct clk_core dummy_ck; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 0b02b41..17abc81 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -37,7 +37,7 @@ #define DPLL5_FREQ_FOR_USBHOST 120000000 /* needed by omap3_core_dpll_m2_set_rate() */ -struct clk *sdrc_ick_p, *arm_fck_p; +struct clk_core *sdrc_ick_p, *arm_fck_p; int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -56,20 +56,20 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, void __init omap3_clk_lock_dpll5(void) { - struct clk *dpll5_clk; - struct clk *dpll5_m2_clk; + struct clk_core *dpll5_clk; + struct clk_core *dpll5_m2_clk; - dpll5_clk = clk_get(NULL, "dpll5_ck"); - clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_prepare_enable(dpll5_clk); + dpll5_clk = clk_provider_get(NULL, "dpll5_ck"); + clk_provider_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); + clk_provider_prepare_enable(dpll5_clk); /* Program dpll5_m2_clk divider for no division */ - dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_prepare_enable(dpll5_m2_clk); - clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); + dpll5_m2_clk = clk_provider_get(NULL, "dpll5_m2_ck"); + clk_provider_prepare_enable(dpll5_m2_clk); + clk_provider_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - clk_disable_unprepare(dpll5_m2_clk); - clk_disable_unprepare(dpll5_clk); + clk_provider_disable_unprepare(dpll5_m2_clk); + clk_provider_disable_unprepare(dpll5_clk); return; } diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 78d9f56..063fbf1 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -12,8 +12,8 @@ int omap3xxx_clk_init(void); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); -extern struct clk *sdrc_ick_p; -extern struct clk *arm_fck_p; +extern struct clk_core *sdrc_ick_p; +extern struct clk_core *arm_fck_p; extern const struct clkops clkops_noncore_dpll_ops; diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index ef4d21b..31e3e79 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -119,7 +119,7 @@ const struct clksel_rate div31_1to31_rates[] = { static struct clk_ops dummy_ck_ops = {}; -struct clk dummy_ck = { +struct clk_core dummy_ck = { .name = "dummy_clk", .ops = &dummy_ck_ops, .flags = CLK_IS_BASIC, diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 2da3b5e..ce0971c 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1141,7 +1141,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) /** * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the enabled downstream clock + * @clk: struct clk_core * of the enabled downstream clock * * Increment the usecount of the clockdomain @clkdm and ensure that it * is awake before @clk is enabled. Intended to be called by @@ -1152,7 +1152,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) * by on-chip processors. Returns -EINVAL if passed null pointers; * returns 0 upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk) { /* * XXX Rewrite this code to maintain a list of enabled @@ -1168,7 +1168,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) /** * clkdm_clk_disable - remove an enabled downstream clock from this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the disabled downstream clock + * @clk: struct clk_core * of the disabled downstream clock * * Decrement the usecount of this clockdomain @clkdm when @clk is * disabled. Intended to be called by clk_disable() code. If the @@ -1178,7 +1178,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0 * upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk) { if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 82c37b1..f1a2cad 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -207,8 +207,8 @@ int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep_nolock(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk); +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 0f9e479..94b3232 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -524,7 +524,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_prepare_enable(oc->_clk); + clk_provider_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -551,7 +551,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_disable_unprepare(oc->_clk); + clk_provider_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index ac3d789..dfbead1 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -288,7 +288,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) /* * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @freqsel: FREQSEL value to set * * Program the DPLL with the last M, N values calculated, and wait for @@ -410,7 +410,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw) struct clk_hw_omap *clk = to_clk_hw_omap(hw); int r; struct dpll_data *dd; - struct clk *parent; + struct clk_core *parent; dd = clk->dpll_data; if (!dd) @@ -461,7 +461,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) /** * omap3_noncore_dpll_set_rate - set non-core DPLL rate - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Set the DPLL CLKOUT to the target rate. If the DPLL can enter @@ -474,7 +474,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct clk *new_parent = NULL; + struct clk_core *new_parent = NULL; unsigned long rrate; u16 freqsel = 0; struct dpll_data *dd; @@ -493,15 +493,15 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __func__, __clk_get_name(hw->clk)); __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); + clk_provider_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; - clk_disable(dd->clk_bypass); + clk_provider_disable(dd->clk_bypass); __clk_unprepare(dd->clk_bypass); } else { __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); + clk_provider_enable(dd->clk_ref); /* XXX this check is probably pointless in the CCF context */ if (dd->last_rounded_rate != rate) { @@ -530,7 +530,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; - clk_disable(dd->clk_ref); + clk_provider_disable(dd->clk_ref); __clk_unprepare(dd->clk_ref); } /* @@ -540,7 +540,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, * stuff is inherited for free */ - if (!ret && clk_get_parent(hw->clk) != new_parent) + if (!ret && clk_provider_get_parent(hw->clk) != new_parent) __clk_reparent(hw->clk, new_parent); return 0; @@ -550,10 +550,10 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap3_dpll_autoidle_read - read a DPLL's autoidle bits - * @clk: struct clk * of the DPLL to read + * @clk: struct clk_core * of the DPLL to read * * Return the DPLL's autoidle bits, shifted down to bit 0. Returns - * -EINVAL if passed a null pointer or if the struct clk does not + * -EINVAL if passed a null pointer or if the struct clk_core does not * appear to refer to a DPLL. */ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) @@ -578,7 +578,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) /** * omap3_dpll_allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. This automatic idle mode * switching takes effect only when the DPLL is locked, at least on @@ -612,7 +612,7 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk) /** * omap3_dpll_deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ @@ -642,7 +642,7 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk) static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) { struct clk_hw_omap *pclk = NULL; - struct clk *parent; + struct clk_core *parent; /* Walk up the parents of clk, looking for a DPLL */ do { diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 4613f1e..e6d24a2 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -124,7 +124,7 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to compute the rate for + * @clk: struct clk_core * of the DPLL to compute the rate for * * Compute the output rate for the OMAP4 DPLL represented by @clk. * Takes the REGM4XEN bit into consideration, which is needed for the @@ -156,7 +156,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, /** * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to round a rate for + * @clk: struct clk_core * of the DPLL to round a rate for * @target_rate: the desired rate of the DPLL * * Compute the rate that would be programmed into the DPLL hardware diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index b4ac3af..e7ea6ba 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -34,7 +34,7 @@ #include "cm3xxx.h" #include "cm-regbits-34xx.h" -static struct clk *mcbsp_iclks[5]; +static struct clk_core *mcbsp_iclks[5]; static int omap3_enable_st_clock(unsigned int id, bool enable) { @@ -98,7 +98,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); pdata->enable_st_clock = omap3_enable_st_clock; sprintf(clk_name, "mcbsp%d_ick", id); - mcbsp_iclks[id] = clk_get(NULL, clk_name); + mcbsp_iclks[id] = clk_provider_get(NULL, clk_name); count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index fbe8cf0..350abb0 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -47,7 +47,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, const char *clk_name) { - struct clk *r; + struct clk_core *r; struct clk_lookup *l; if (!clk_alias || !clk_name) @@ -55,15 +55,15 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name); - r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); + r = clk_provider_get_sys(dev_name(&od->pdev->dev), clk_alias); if (!IS_ERR(r)) { dev_warn(&od->pdev->dev, "alias %s already exists\n", clk_alias); - clk_put(r); + __clk_put(r); return; } - r = clk_get(NULL, clk_name); + r = clk_provider_get(NULL, clk_name); if (IS_ERR(r)) { dev_err(&od->pdev->dev, "clk_get for %s failed\n", clk_name); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 6c074f3..67b6635 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -753,7 +753,7 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) } /** - * _init_main_clk - get a struct clk * for the the hwmod's main functional clk + * _init_main_clk - get a struct clk_core * for the the hwmod's main functional clk * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh _clk (main @@ -767,7 +767,7 @@ static int _init_main_clk(struct omap_hwmod *oh) if (!oh->main_clk) return 0; - oh->_clk = clk_get(NULL, oh->main_clk); + oh->_clk = clk_provider_get(NULL, oh->main_clk); if (IS_ERR(oh->_clk)) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", oh->name, oh->main_clk); @@ -781,7 +781,7 @@ static int _init_main_clk(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oh->_clk); + clk_provider_prepare(oh->_clk); if (!_get_clkdm(oh)) pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", @@ -791,7 +791,7 @@ static int _init_main_clk(struct omap_hwmod *oh) } /** - * _init_interface_clks - get a struct clk * for the the hwmod's interface clks + * _init_interface_clks - get a struct clk_core * for the the hwmod's interface clks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh OCP slave interface @@ -801,7 +801,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) { struct omap_hwmod_ocp_if *os; struct list_head *p; - struct clk *c; + struct clk_core *c; int i = 0; int ret = 0; @@ -812,7 +812,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) if (!os->clk) continue; - c = clk_get(NULL, os->clk); + c = clk_provider_get(NULL, os->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", oh->name, os->clk); @@ -828,14 +828,14 @@ static int _init_interface_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(os->_clk); + clk_provider_prepare(os->_clk); } return ret; } /** - * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks + * _init_opt_clk - get a struct clk_core * for the the hwmod's optional clocks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk @@ -844,12 +844,12 @@ static int _init_interface_clks(struct omap_hwmod *oh) static int _init_opt_clks(struct omap_hwmod *oh) { struct omap_hwmod_opt_clk *oc; - struct clk *c; + struct clk_core *c; int i; int ret = 0; for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { - c = clk_get(NULL, oc->clk); + c = clk_provider_get(NULL, oc->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", oh->name, oc->clk); @@ -865,7 +865,7 @@ static int _init_opt_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oc->_clk); + clk_provider_prepare(oc->_clk); } return ret; @@ -887,7 +887,7 @@ static int _enable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); if (oh->_clk) - clk_enable(oh->_clk); + clk_provider_enable(oh->_clk); p = oh->slave_ports.next; @@ -895,7 +895,7 @@ static int _enable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -918,7 +918,7 @@ static int _disable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); if (oh->_clk) - clk_disable(oh->_clk); + clk_provider_disable(oh->_clk); p = oh->slave_ports.next; @@ -926,7 +926,7 @@ static int _disable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_disable(os->_clk); + clk_provider_disable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -945,7 +945,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_enable(oc->_clk); + clk_provider_enable(oc->_clk); } } @@ -960,7 +960,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: disable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_disable(oc->_clk); + clk_provider_disable(oc->_clk); } } @@ -2585,7 +2585,7 @@ static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) /* XXX omap_iclk_deny_idle(c); */ } else { /* XXX omap_iclk_allow_idle(c); */ - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } } @@ -3389,7 +3389,7 @@ static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) * Initialize and set up a single hwmod. Intended to be used for a * small number of early devices, such as the timer IP blocks used for * the scheduler clock. Must be called after omap2_clk_init(). - * Resolves the struct clk names to struct clk pointers for each + * Resolves the struct clk_core names to struct clk_core pointers for each * registered omap_hwmod. Also calls _setup() on each hwmod. Returns * -EINVAL upon error or 0 upon success. */ @@ -3418,7 +3418,7 @@ int __init omap_hwmod_setup_one(const char *oh_name) * * Initialize and set up all IP blocks registered with the hwmod code. * Must be called after omap2_clk_init(). Resolves the struct clk - * names to struct clk pointers for each registered omap_hwmod. Also + * names to struct clk_core pointers for each registered omap_hwmod. Also * calls _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) @@ -3785,7 +3785,7 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, */ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { - struct clk *c; + struct clk_core *c; struct omap_hwmod_ocp_if *oi; struct clockdomain *clkdm; struct clk_hw_omap *clk; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0f97d63..46ffd06 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -207,7 +207,7 @@ struct omap_hwmod_rst_info { * struct omap_hwmod_opt_clk - optional clocks used by this hwmod * @role: "sys", "32k", "tv", etc -- for use in clk_get() * @clk: opt clock: OMAP clock name - * @_clk: pointer to the struct clk (filled in at runtime) + * @_clk: pointer to the struct clk_core (filled in at runtime) * * The module's interface clock and main functional clock should not * be added as optional clocks. @@ -215,7 +215,7 @@ struct omap_hwmod_rst_info { struct omap_hwmod_opt_clk { const char *role; const char *clk; - struct clk *_clk; + struct clk_core *_clk; }; @@ -289,7 +289,7 @@ struct omap_hwmod_addr_space { * @slave: struct omap_hwmod that responds to OCP transactions on this link * @addr: address space associated with this link * @clk: interface clock: OMAP clock name - * @_clk: pointer to the interface struct clk (filled in at runtime) + * @_clk: pointer to the interface struct clk_core (filled in at runtime) * @fw: interface firewall data * @width: OCP data width * @user: initiators using this interface (see OCP_USER_* macros above) @@ -306,7 +306,7 @@ struct omap_hwmod_ocp_if { struct omap_hwmod *slave; struct omap_hwmod_addr_space *addr; const char *clk; - struct clk *_clk; + struct clk_core *_clk; union { struct omap_hwmod_omap2_firewall omap2; } fw; @@ -611,7 +611,7 @@ struct omap_hwmod_link { * @sdma_reqs: ptr to an array of System DMA request IDs * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name - * @_clk: pointer to the main struct clk (filled in at runtime) + * @_clk: pointer to the main struct clk_core (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @voltdm: pointer to voltage domain (filled in at runtime) * @dev_attr: arbitrary device attributes that can be passed to the driver @@ -653,7 +653,7 @@ struct omap_hwmod { struct omap_hwmod_omap4_prcm omap4; } prcm; const char *main_clk; - struct clk *_clk; + struct clk_core *_clk; struct omap_hwmod_opt_clk *opt_clks; char *clkdm_name; struct clockdomain *clkdm; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index fe01c5a..56e5e77 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -60,7 +60,7 @@ static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, static struct powerdomain *mpu_pwrdm, *core_pwrdm; static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; -static struct clk *osc_ck, *emul_ck; +static struct clk_core *osc_ck, *emul_ck; static int omap2_enter_full_retention(void) { @@ -71,7 +71,7 @@ static int omap2_enter_full_retention(void) * oscillator itself it will be disabled if/when we enter retention * mode. */ - clk_disable(osc_ck); + clk_provider_disable(osc_ck); /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ @@ -101,7 +101,7 @@ static int omap2_enter_full_retention(void) no_sleep: omap2_gpio_resume_after_idle(); - clk_enable(osc_ck); + clk_provider_enable(osc_ck); /* clear CORE wake-up events */ omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); @@ -287,17 +287,17 @@ int __init omap2_pm_init(void) pr_err("PM: gfx_clkdm not found\n"); - osc_ck = clk_get(NULL, "osc_ck"); + osc_ck = clk_provider_get(NULL, "osc_ck"); if (IS_ERR(osc_ck)) { printk(KERN_ERR "could not get osc_ck\n"); return -ENODEV; } if (cpu_is_omap242x()) { - emul_ck = clk_get(NULL, "emul_ck"); + emul_ck = clk_provider_get(NULL, "emul_ck"); if (IS_ERR(emul_ck)) { printk(KERN_ERR "could not get emul_ck\n"); - clk_put(osc_ck); + __clk_put(osc_ck); return -ENODEV; } } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 6bbb7b5..6be2d2d 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -62,7 +62,7 @@ void __init orion5x_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; void __init clk_init(void) { diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index ed415dc..9398452 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -32,17 +32,17 @@ void __init shmobile_clk_workaround(const struct clk_name *clks, int nr_clks, bool enable) { const struct clk_name *clkn; - struct clk *clk; + struct clk_core *clk; unsigned int i; for (i = 0; i < nr_clks; ++i) { clkn = clks + i; - clk = clk_get(NULL, clkn->clk); + clk = clk_provider_get(NULL, clkn->clk); if (!IS_ERR(clk)) { clk_register_clkdev(clk, clkn->con_id, clkn->dev_id); if (enable) - clk_prepare_enable(clk); - clk_put(clk); + clk_provider_prepare_enable(clk); + __clk_put(clk); } } } @@ -53,7 +53,7 @@ void __init shmobile_clk_workaround(const struct clk_name *clks, #include "clock.h" #include "common.h" -unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) +unsigned long shmobile_fixed_ratio_clk_recalc(struct clk_core *clk) { struct clk_ratio *p = clk->priv; @@ -75,13 +75,13 @@ int __init shmobile_clk_init(void) return 0; } -int __clk_get(struct clk *clk) +int __clk_get(struct clk_core *clk) { return 1; } EXPORT_SYMBOL(__clk_get); -void __clk_put(struct clk *clk) +void __clk_put(struct clk_core *clk) { } EXPORT_SYMBOL(__clk_put); diff --git a/arch/arm/mach-shmobile/clock.h b/arch/arm/mach-shmobile/clock.h index 31b6417..a77e81b 100644 --- a/arch/arm/mach-shmobile/clock.h +++ b/arch/arm/mach-shmobile/clock.h @@ -17,7 +17,7 @@ void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks, /* legacy clock implementation */ struct clk; -unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk); +unsigned long shmobile_fixed_ratio_clk_recalc(struct clk_core *clk); extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops; /* clock ratio */ @@ -33,7 +33,7 @@ static struct clk_ratio name ##_ratio = { \ } #define SH_FIXED_RATIO_CLKg(name, p, r) \ -struct clk name = { \ +struct clk_core name = { \ .parent = &p, \ .ops = &shmobile_fixed_ratio_clk_ops,\ .priv = &r ## _ratio, \ diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c index 2c2754e..f0d73be 100644 --- a/arch/arm/mach-vexpress/spc.c +++ b/arch/arm/mach-vexpress/spc.c @@ -523,7 +523,7 @@ static struct clk_ops clk_spc_ops = { .set_rate = spc_set_rate, }; -static struct clk *ve_spc_clk_register(struct device *cpu_dev) +static struct clk_core *ve_spc_clk_register(struct device *cpu_dev) { struct clk_init_data init; struct clk_spc *spc; @@ -548,7 +548,7 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev) static int __init ve_spc_clk_init(void) { int cpu; - struct clk *clk; + struct clk_core *clk; if (!info) return 0; /* Continue only if SPC is initialised */ diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 961b593..7bf2fe6 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -27,7 +27,7 @@ /* Create a clkdev entry for a given device/clk */ void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk) + struct clk_core *clk) { struct clk_lookup *cl; @@ -40,7 +40,7 @@ void __init orion_clkdev_add(const char *con_id, const char *dev_id, Kirkwood has gated clocks for some of its peripherals, so creates its own clkdev entries. For all the other orion devices, create clkdev entries to the tclk. */ -void __init orion_clkdev_init(struct clk *tclk) +void __init orion_clkdev_init(struct clk_core *tclk) { orion_clkdev_add(NULL, "orion_spi.0", tclk); orion_clkdev_add(NULL, "orion_spi.1", tclk); @@ -78,10 +78,10 @@ static void fill_resources(struct platform_device *device, /***************************************************************************** * UART ****************************************************************************/ -static unsigned long __init uart_get_clk_rate(struct clk *clk) +static unsigned long __init uart_get_clk_rate(struct clk_core *clk) { - clk_prepare_enable(clk); - return clk_get_rate(clk); + clk_provider_prepare_enable(clk); + return clk_provider_get_rate(clk); } static void __init uart_complete( @@ -91,7 +91,7 @@ static void __init uart_complete( void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { data->mapbase = mapbase; data->membase = membase; @@ -125,7 +125,7 @@ static struct platform_device orion_uart0 = { void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources, membase, mapbase, irq, clk); @@ -153,7 +153,7 @@ static struct platform_device orion_uart1 = { void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources, membase, mapbase, irq, clk); @@ -181,7 +181,7 @@ static struct platform_device orion_uart2 = { void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources, membase, mapbase, irq, clk); @@ -209,7 +209,7 @@ static struct platform_device orion_uart3 = { void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, membase, mapbase, irq, clk); diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index d9a24f6..44f1bbe 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -18,22 +18,22 @@ struct mv_sata_platform_data; void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); @@ -107,7 +107,7 @@ void __init orion_crypto_init(unsigned long mapbase, unsigned long irq); void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk); + struct clk_core *clk); -void __init orion_clkdev_init(struct clk *tclk); +void __init orion_clkdev_init(struct clk_core *tclk); #endif diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index 6eb614a..81afe83 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c @@ -70,7 +70,7 @@ enum { }; /* data required for the OF clock provider registration */ -static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; +static struct clk_core *clks[MPC512x_CLK_LAST_PRIVATE]; static struct clk_onecell_data clk_data; /* CCM register access */ @@ -218,12 +218,12 @@ static bool soc_has_mclk_mux0_canin(void) /* common clk API wrappers {{{ */ /* convenience wrappers around the common clk API */ -static inline struct clk *mpc512x_clk_fixed(const char *name, int rate) +static inline struct clk_core *mpc512x_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mpc512x_clk_factor( +static inline struct clk_core *mpc512x_clk_factor( const char *name, const char *parent_name, int mul, int div) { @@ -234,7 +234,7 @@ static inline struct clk *mpc512x_clk_factor( mul, div); } -static inline struct clk *mpc512x_clk_divider( +static inline struct clk_core *mpc512x_clk_divider( const char *name, const char *parent_name, u8 clkflags, u32 __iomem *reg, u8 pos, u8 len, int divflags) { @@ -242,7 +242,7 @@ static inline struct clk *mpc512x_clk_divider( reg, pos, len, divflags, &clklock); } -static inline struct clk *mpc512x_clk_divtable( +static inline struct clk_core *mpc512x_clk_divtable( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos, u8 len, const struct clk_div_table *divtab) @@ -255,7 +255,7 @@ static inline struct clk *mpc512x_clk_divtable( divtab, &clklock); } -static inline struct clk *mpc512x_clk_gated( +static inline struct clk_core *mpc512x_clk_gated( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos) { @@ -266,7 +266,7 @@ static inline struct clk *mpc512x_clk_gated( reg, pos, 0, &clklock); } -static inline struct clk *mpc512x_clk_muxed(const char *name, +static inline struct clk_core *mpc512x_clk_muxed(const char *name, const char **parent_names, int parent_count, u32 __iomem *reg, u8 pos, u8 len) { @@ -422,7 +422,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, int *sys_mul, int *sys_div, int *ips_div) { - struct clk *osc_clk; + struct clk_core *osc_clk; int calc_freq; /* fetch mul/div factors from the hardware */ @@ -432,7 +432,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, *ips_div = get_bit_field(&clkregs->scfr1, 23, 3); /* lookup the oscillator clock for its rate */ - osc_clk = of_clk_get_by_name(np, "osc"); + osc_clk = of_clk_provider_get_by_name(np, "osc"); /* * either descend from OSC to REF (and in bypassing verify the @@ -444,7 +444,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, */ if (!IS_ERR(osc_clk)) { clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); - calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); + calc_freq = clk_provider_get_rate(clks[MPC512x_CLK_REF]); calc_freq *= *sys_mul; calc_freq /= *sys_div; calc_freq /= 2; @@ -647,8 +647,8 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx) * - MCLK 0 enabled * - MCLK 1 from MCLK DIV */ - div = clk_get_rate(clks[MPC512x_CLK_SYS]); - div /= clk_get_rate(clks[MPC512x_CLK_IPS]); + div = clk_provider_get_rate(clks[MPC512x_CLK_SYS]); + div /= clk_provider_get_rate(clks[MPC512x_CLK_IPS]); out_be32(mccr_reg, (0 << 16)); out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17)); out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17)); @@ -925,12 +925,12 @@ static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq) * claimed by any peripheral driver, to not have the clock * subsystem disable them late at startup */ - clk_prepare_enable(clks[MPC512x_CLK_DUMMY]); - clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ - clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ - clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ - clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ - clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DUMMY]); + clk_provider_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ + clk_provider_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ } /* @@ -969,9 +969,9 @@ static void mpc5121_clk_provide_migration_support(void) * has attached to bridges, otherwise the PCI clock remains * unused and so it gets disabled */ - clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ + clk_provider_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci")) - clk_prepare_enable(clks[MPC512x_CLK_PCI]); + clk_provider_prepare_enable(clks[MPC512x_CLK_PCI]); } /* @@ -988,8 +988,8 @@ static void mpc5121_clk_provide_migration_support(void) } while (0) #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \ - struct clk *clk; \ - clk = of_clk_get_by_name(np, clkname); \ + struct clk_core *clk; \ + clk = of_clk_provider_get_by_name(np, clkname); \ if (IS_ERR(clk)) { \ clk = clkitem; \ clk_register_clkdev(clk, clkname, devname); \ @@ -999,7 +999,7 @@ static void mpc5121_clk_provide_migration_support(void) pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \ clkname, devname, clk); \ } else { \ - clk_put(clk); \ + __clk_put(clk); \ } \ } while (0) @@ -1090,7 +1090,7 @@ static void mpc5121_clk_provide_backwards_compat(void) * workaround obsolete */ if (did_register & DID_REG_I2C) - clk_prepare_enable(clks[MPC512x_CLK_I2C]); + clk_provider_prepare_enable(clks[MPC512x_CLK_I2C]); FOR_NODES("fsl,mpc5121-diu") { NODE_PREP; diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 59fa3cc..11bcdb1 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -138,7 +138,7 @@ static const struct clk_ops main_osc_ops = { .is_prepared = clk_main_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -147,7 +147,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, { int ret; struct clk_main_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !parent_name) @@ -192,7 +192,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; const char *name = np->name; const char *parent_name; @@ -291,7 +291,7 @@ static const struct clk_ops main_rc_osc_ops = { .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_rc_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -299,7 +299,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, { int ret; struct clk_main_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !frequency) @@ -340,7 +340,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; u32 frequency = 0; u32 accuracy = 0; @@ -424,13 +424,13 @@ static const struct clk_ops rm9200_main_ops = { .recalc_rate = clk_rm9200_main_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_rm9200_main(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_rm9200_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -462,7 +462,7 @@ at91_clk_register_rm9200_main(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -555,7 +555,7 @@ static const struct clk_ops sam9x5_main_ops = { .get_parent = clk_sam9x5_main_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_main(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -564,7 +564,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, { int ret; struct clk_sam9x5_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name) @@ -607,7 +607,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; unsigned int irq; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index c1af80b..95ae1b6 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -131,7 +131,7 @@ static const struct clk_ops master_ops = { .get_parent = clk_master_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, const char *name, int num_parents, const char **parent_names, @@ -140,7 +140,7 @@ at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, { int ret; struct clk_master *master; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !num_parents || !parent_names) @@ -216,7 +216,7 @@ static void __init of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc, const struct clk_master_layout *layout) { - struct clk *clk; + struct clk_core *clk; int num_parents; int i; unsigned int irq; diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 597fed4..cdf8e8a 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -100,12 +100,12 @@ static const struct clk_ops peripheral_ops = { .is_enabled = clk_peripheral_is_enabled, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id) { struct clk_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX) @@ -134,7 +134,7 @@ at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) { - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; int shift = 0; @@ -309,13 +309,13 @@ static const struct clk_ops sam9x5_peripheral_ops = { .set_rate = clk_sam9x5_peripheral_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id, const struct clk_range *range) { struct clk_sam9x5_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name) @@ -352,7 +352,7 @@ of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type) { int num; u32 id; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name; struct device_node *periphclknp; diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index cf6ed02..0d22f65f 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -297,14 +297,14 @@ static const struct clk_ops pll_ops = { .set_rate = clk_pll_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; int offset = PLL_REG(id); @@ -474,7 +474,7 @@ of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc, { u32 id; unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; struct clk_pll_characteristics *characteristics; diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index ea22656..f8204d8 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -79,12 +79,12 @@ static const struct clk_ops plldiv_ops = { .set_rate = clk_plldiv_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_plldiv *plldiv; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); @@ -111,7 +111,7 @@ at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, static void __init of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 62e2509..b72e98c 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -57,9 +57,9 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, static long clk_programmable_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { - struct clk *parent = NULL; + struct clk_core *parent = NULL; long best_rate = -EINVAL; unsigned long parent_rate; unsigned long tmp_rate; @@ -169,14 +169,14 @@ static const struct clk_ops programmable_ops = { .set_rate = clk_programmable_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_programmable(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout) { struct clk_programmable *prog; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (id > PROG_ID_MAX) @@ -229,7 +229,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc, int num; u32 id; int i; - struct clk *clk; + struct clk_core *clk; int num_parents; const char *parent_names[PROG_SOURCE_MAX]; const char *name; diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index 0300c46..d50fe02 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -117,7 +117,7 @@ static const struct clk_ops slow_osc_ops = { .is_prepared = clk_slow_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const char *parent_name, @@ -125,7 +125,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, bool bypass) { struct clk_slow_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_name) @@ -159,7 +159,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 startup; @@ -229,7 +229,7 @@ static const struct clk_ops slow_rc_osc_ops = { .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_rc_osc(void __iomem *sckcr, const char *name, unsigned long frequency, @@ -237,7 +237,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, unsigned long startup) { struct clk_slow_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name) @@ -269,7 +269,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; u32 frequency = 0; u32 accuracy = 0; u32 startup = 0; @@ -327,14 +327,14 @@ static const struct clk_ops sam9x5_slow_ops = { .get_parent = clk_sam9x5_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_slow(void __iomem *sckcr, const char *name, const char **parent_names, int num_parents) { struct clk_sam9x5_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_names || !num_parents) @@ -364,7 +364,7 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; @@ -401,14 +401,14 @@ static const struct clk_ops sam9260_slow_ops = { .get_parent = clk_sam9260_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9260_slow(struct at91_pmc *pmc, const char *name, const char **parent_names, int num_parents) { struct clk_sam9260_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -440,7 +440,7 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc, void __init of_at91sam9260_clk_slow_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index 144d47e..8820b84 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -113,12 +113,12 @@ static const struct clk_ops at91sam9x5_smd_ops = { .set_rate = at91sam9x5_clk_smd_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_smd *smd; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; smd = kzalloc(sizeof(*smd), GFP_KERNEL); @@ -144,7 +144,7 @@ at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[SMD_SOURCE_MAX]; diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 8c96307..770d9bf 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -99,12 +99,12 @@ static const struct clk_ops system_ops = { .is_prepared = clk_system_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_system(struct at91_pmc *pmc, const char *name, const char *parent_name, u8 id, int irq) { struct clk_system *sys; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; @@ -153,7 +153,7 @@ of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc) int num; int irq = 0; u32 id; - struct clk *clk; + struct clk_core *clk; const char *name; struct device_node *sysclknp; const char *parent_name; diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 7d1d26a..246989c 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -162,12 +162,12 @@ static const struct clk_ops at91sam9n12_usb_ops = { .set_rate = at91sam9x5_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -190,12 +190,12 @@ at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, return clk; } -static struct clk * __init +static struct clk_core * __init at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -295,12 +295,12 @@ static const struct clk_ops at91rm9200_usb_ops = { .set_rate = at91rm9200_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name, const u32 *divisors) { struct at91rm9200_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -327,7 +327,7 @@ at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[USB_SOURCE_MAX]; @@ -355,7 +355,7 @@ void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -375,7 +375,7 @@ void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, void __init of_at91rm9200_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 divisors[4] = {0, 0, 0, 0}; diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index ae3263b..0502050 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -92,13 +92,13 @@ static const struct clk_ops utmi_ops = { .recalc_rate = clk_utmi_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name) { int ret; struct clk_utmi *utmi; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; utmi = kzalloc(sizeof(*utmi), GFP_KERNEL); @@ -132,7 +132,7 @@ static void __init of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc) { unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c index e5aeded..122e7b0 100644 --- a/drivers/clk/bcm/clk-kona-setup.c +++ b/drivers/clk/bcm/clk-kona-setup.c @@ -697,7 +697,7 @@ static void bcm_clk_teardown(struct kona_clk *bcm_clk) bcm_clk->type = bcm_clk_none; } -static void kona_clk_teardown(struct clk *clk) +static void kona_clk_teardown(struct clk_core *clk) { struct clk_hw *hw; struct kona_clk *bcm_clk; @@ -716,10 +716,10 @@ static void kona_clk_teardown(struct clk *clk) bcm_clk_teardown(bcm_clk); } -struct clk *kona_clk_setup(struct kona_clk *bcm_clk) +struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk) { struct clk_init_data *init_data = &bcm_clk->init_data; - struct clk *clk = NULL; + struct clk_core *clk = NULL; switch (bcm_clk->type) { case bcm_clk_peri: diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c index 95af2e6..a301aa9 100644 --- a/drivers/clk/bcm/clk-kona.c +++ b/drivers/clk/bcm/clk-kona.c @@ -1032,11 +1032,11 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate, } static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *best_parent_rate, struct clk **best_parent) + unsigned long *best_parent_rate, struct clk_core **best_parent) { struct kona_clk *bcm_clk = to_kona_clk(hw); - struct clk *clk = hw->clk; - struct clk *current_parent; + struct clk_core *clk = hw->clk; + struct clk_core *current_parent; unsigned long parent_rate; unsigned long best_delta; unsigned long best_rate; @@ -1053,14 +1053,14 @@ static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, return kona_peri_clk_round_rate(hw, rate, best_parent_rate); /* Unless we can do better, stick with current parent */ - current_parent = clk_get_parent(clk); + current_parent = clk_provider_get_parent(clk); parent_rate = __clk_get_rate(current_parent); best_rate = kona_peri_clk_round_rate(hw, rate, &parent_rate); best_delta = abs(best_rate - rate); /* Check whether any other parent clock can produce a better result */ for (which = 0; which < parent_count; which++) { - struct clk *parent = clk_get_parent_by_index(clk, which); + struct clk_core *parent = clk_get_parent_by_index(clk, which); unsigned long delta; unsigned long other_rate; @@ -1260,7 +1260,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu) { unsigned long flags; unsigned int which; - struct clk **clks = ccu->clk_data.clks; + struct clk_core **clks = ccu->clk_data.clks; bool success = true; flags = ccu_lock(ccu); diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h index 2537b30..c2d0152 100644 --- a/drivers/clk/bcm/clk-kona.h +++ b/drivers/clk/bcm/clk-kona.h @@ -508,7 +508,7 @@ extern u64 scaled_div_max(struct bcm_clk_div *div); extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths); -extern struct clk *kona_clk_setup(struct kona_clk *bcm_clk); +extern struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk); extern void __init kona_dt_ccu_setup(struct ccu_data *ccu, struct device_node *node); extern bool __init kona_ccu_init(struct ccu_data *ccu); diff --git a/drivers/clk/berlin/berlin2-avpll.c b/drivers/clk/berlin/berlin2-avpll.c index fd0f26c..488d986 100644 --- a/drivers/clk/berlin/berlin2-avpll.c +++ b/drivers/clk/berlin/berlin2-avpll.c @@ -188,7 +188,7 @@ static const struct clk_ops berlin2_avpll_vco_ops = { .recalc_rate = berlin2_avpll_vco_recalc_rate, }; -struct clk * __init berlin2_avpll_vco_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags) { @@ -364,7 +364,7 @@ static const struct clk_ops berlin2_avpll_channel_ops = { */ static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 }; -struct clk * __init berlin2_avpll_channel_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags) { diff --git a/drivers/clk/berlin/berlin2-avpll.h b/drivers/clk/berlin/berlin2-avpll.h index a37f506..216eee7 100644 --- a/drivers/clk/berlin/berlin2-avpll.h +++ b/drivers/clk/berlin/berlin2-avpll.h @@ -24,11 +24,11 @@ struct clk; #define BERLIN2_AVPLL_BIT_QUIRK BIT(0) #define BERLIN2_AVPLL_SCRAMBLE_QUIRK BIT(1) -struct clk * __init +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags); -struct clk * __init +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags); diff --git a/drivers/clk/berlin/berlin2-div.c b/drivers/clk/berlin/berlin2-div.c index 81ff97f..c673082 100644 --- a/drivers/clk/berlin/berlin2-div.c +++ b/drivers/clk/berlin/berlin2-div.c @@ -234,7 +234,7 @@ static const struct clk_ops berlin2_div_mux_ops = { .get_parent = berlin2_div_get_parent, }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-div.h b/drivers/clk/berlin/berlin2-div.h index 15e3384..3ddb87a 100644 --- a/drivers/clk/berlin/berlin2-div.h +++ b/drivers/clk/berlin/berlin2-div.h @@ -80,7 +80,7 @@ struct berlin2_div_data { u8 div_flags; }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-pll.c b/drivers/clk/berlin/berlin2-pll.c index bdc506b..b7a3016 100644 --- a/drivers/clk/berlin/berlin2-pll.c +++ b/drivers/clk/berlin/berlin2-pll.c @@ -91,7 +91,7 @@ static const struct clk_ops berlin2_pll_ops = { .recalc_rate = berlin2_pll_recalc_rate, }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags) diff --git a/drivers/clk/berlin/berlin2-pll.h b/drivers/clk/berlin/berlin2-pll.h index 8831ce2..6b6a6ed 100644 --- a/drivers/clk/berlin/berlin2-pll.h +++ b/drivers/clk/berlin/berlin2-pll.h @@ -29,7 +29,7 @@ struct berlin2_pll_map { u8 divsel_shift; }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags); diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c index 4c81e09..1329721 100644 --- a/drivers/clk/berlin/bg2.c +++ b/drivers/clk/berlin/bg2.c @@ -93,7 +93,7 @@ */ #define MAX_CLKS 41 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -504,7 +504,7 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = { static void __init berlin2_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; u8 avpll_flags = 0; int n; @@ -513,16 +513,16 @@ static void __init berlin2_clock_setup(struct device_node *np) return; /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } - clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]); + clk = of_clk_provider_get_by_name(np, clk_names[VIDEO_EXT0]); if (!IS_ERR(clk)) { clk_names[VIDEO_EXT0] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c index 748da9b..0b251bd 100644 --- a/drivers/clk/berlin/bg2q.c +++ b/drivers/clk/berlin/bg2q.c @@ -47,7 +47,7 @@ #define REG_SDIO1XIN_CLKCTL 0x015c #define MAX_CLKS 27 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -293,7 +293,7 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = { static void __init berlin2q_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; int n; gbase = of_iomap(np, 0); @@ -311,10 +311,10 @@ static void __init berlin2q_clock_setup(struct device_node *np) } /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 1127ee4..4b64834 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -489,7 +489,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) const char *parent_name; const char *clk_name; struct resource *mem; - struct clk *clk; + struct clk_core *clk; if (!pdev->dev.of_node) return -ENODEV; diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c index d2f1e11..3dc6e58 100644 --- a/drivers/clk/clk-axm5516.c +++ b/drivers/clk/clk-axm5516.c @@ -532,7 +532,7 @@ MODULE_DEVICE_TABLE(of, axmclk_match_table); struct axmclk_priv { struct clk_onecell_data onecell; - struct clk *clks[]; + struct clk_core *clks[]; }; static int axmclk_probe(struct platform_device *pdev) @@ -541,7 +541,7 @@ static int axmclk_probe(struct platform_device *pdev) struct resource *res; int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct regmap *regmap; size_t num_clks; struct axmclk_priv *priv; diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c index 6b950ca..f25e85e 100644 --- a/drivers/clk/clk-bcm2835.c +++ b/drivers/clk/clk-bcm2835.c @@ -29,7 +29,7 @@ */ void __init bcm2835_init_clocks(void) { - struct clk *clk; + struct clk_core *clk; int ret; clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT, diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index b9355da..a812a56 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -57,14 +57,14 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_composite *composite = to_clk_composite(hw); const struct clk_ops *rate_ops = composite->rate_ops; const struct clk_ops *mux_ops = composite->mux_ops; struct clk_hw *rate_hw = composite->rate_hw; struct clk_hw *mux_hw = composite->mux_hw; - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; long tmp_rate, best_rate = 0; unsigned long rate_diff; @@ -80,7 +80,7 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, *best_parent_p = NULL; if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) { - *best_parent_p = clk_get_parent(mux_hw->clk); + *best_parent_p = clk_provider_get_parent(mux_hw->clk); *best_parent_rate = __clk_get_rate(*best_parent_p); return rate_ops->round_rate(rate_hw, rate, @@ -181,14 +181,14 @@ static void clk_composite_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } -struct clk *clk_register_composite(struct device *dev, const char *name, +struct clk_core *clk_register_composite(struct device *dev, const char *name, const char **parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct clk_composite *composite; struct clk_ops *clk_composite_ops; diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index d36a7b3..a7d3a48 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -20,7 +20,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) { struct of_phandle_args clkspec; int index, rc, num_parents; - struct clk *clk, *pclk; + struct clk_core *clk, *pclk; num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", "#clock-cells"); @@ -63,16 +63,16 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) goto err; } - rc = clk_set_parent(clk, pclk); + rc = clk_provider_set_parent(clk, pclk); if (rc < 0) pr_err("clk: failed to reparent %s to %s: %d\n", __clk_get_name(clk), __clk_get_name(pclk), rc); - clk_put(clk); - clk_put(pclk); + __clk_put(clk); + __clk_put(pclk); } return 0; err: - clk_put(pclk); + __clk_put(pclk); return rc; } @@ -82,7 +82,7 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) struct property *prop; const __be32 *cur; int rc, index = 0; - struct clk *clk; + struct clk_core *clk; u32 rate; of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) { @@ -106,11 +106,11 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) return PTR_ERR(clk); } - rc = clk_set_rate(clk, rate); + rc = clk_provider_set_rate(clk, rate); if (rc < 0) pr_err("clk: couldn't set %s clock rate: %d\n", __clk_get_name(clk), rc); - clk_put(clk); + __clk_put(clk); } index++; } diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 18a9de2..3c78139 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -366,14 +366,14 @@ const struct clk_ops clk_divider_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_divider_ro_ops); -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -429,7 +429,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_divider(struct device *dev, const char *name, +struct clk_core *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock) @@ -453,7 +453,7 @@ EXPORT_SYMBOL_GPL(clk_register_divider); * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ -struct clk *clk_register_divider_table(struct device *dev, const char *name, +struct clk_core *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c index bac2ddf..26e0485 100644 --- a/drivers/clk/clk-efm32gg.c +++ b/drivers/clk/clk-efm32gg.c @@ -16,7 +16,7 @@ #define CMU_HFPERCLKEN0 0x44 -static struct clk *clk[37]; +static struct clk_core *clk[37]; static struct clk_onecell_data clk_data = { .clks = clk, .clk_num = ARRAY_SIZE(clk), diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index d9e3f67..ae1fef0 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -65,13 +65,13 @@ struct clk_ops clk_fixed_factor_ops = { }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { struct clk_fixed_factor *fix; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fix = kmalloc(sizeof(*fix), GFP_KERNEL); if (!fix) { @@ -105,7 +105,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_factor); */ void __init of_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index 0fc56ab..56c0ced 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -56,12 +56,12 @@ EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, +struct clk_core *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy) { struct clk_fixed_rate *fixed; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate fixed-rate clock */ @@ -99,7 +99,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy); * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate) { @@ -114,7 +114,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate); */ void of_fixed_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; u32 rate; u32 accuracy = 0; diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index ede685c..8104683 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -96,14 +96,14 @@ const struct clk_ops clk_fractional_divider_ops = { }; EXPORT_SYMBOL_GPL(clk_fractional_divider_ops); -struct clk *clk_register_fractional_divider(struct device *dev, +struct clk_core *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock) { struct clk_fractional_divider *fd; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fd = kzalloc(sizeof(*fd), GFP_KERNEL); if (!fd) { diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 4a58c55..429d302 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -118,13 +118,13 @@ EXPORT_SYMBOL_GPL(clk_gate_ops); * @clk_gate_flags: gate-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_gate(struct device *dev, const char *name, +struct clk_core *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clk_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 2e7e9d9..cad2fba 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -271,10 +271,10 @@ static const struct clk_ops periclk_ops = { .set_rate = clk_periclk_set_rate, }; -static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops) +static __init struct clk_core *hb_clk_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct hb_clk *hb_clk; const char *clk_name = node->name; const char *parent_name; @@ -330,8 +330,8 @@ CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init); static void __init hb_a9bus_init(struct device_node *node) { - struct clk *clk = hb_clk_init(node, &a9bclk_ops); - clk_prepare_enable(clk); + struct clk_core *clk = hb_clk_init(node, &a9bclk_ops); + clk_provider_prepare_enable(clk); } CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init); diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c index f20b750..796043c 100644 --- a/drivers/clk/clk-ls1x.c +++ b/drivers/clk/clk-ls1x.c @@ -48,11 +48,11 @@ static const struct clk_ops ls1x_pll_clk_ops = { .recalc_rate = ls1x_pll_recalc_rate, }; -static struct clk * __init clk_register_pll(struct device *dev, +static struct clk_core * __init clk_register_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags) { struct clk_hw *hw; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the divider */ @@ -80,32 +80,32 @@ static struct clk * __init clk_register_pll(struct device *dev, void __init ls1x_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk = clk_register_divider(NULL, "cpu_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT, DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "cpu", NULL); clk = clk_register_divider(NULL, "dc_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "dc", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "ahb", NULL); clk_register_clkdev(clk, "stmmaceth", NULL); clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "apb", NULL); clk_register_clkdev(clk, "serial8250", NULL); } diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 3d7e8dd..42fa43a 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -112,10 +112,10 @@ static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = { }, }; -static struct clk *max77686_clk_register(struct device *dev, +static struct clk_core *max77686_clk_register(struct device *dev, struct max77686_clk *max77686) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *hw = &max77686->hw; clk = clk_register(dev, hw); @@ -138,10 +138,10 @@ static int max77686_clk_probe(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct max77686_clk *max77686_clks[MAX77686_CLKS_NUM]; - struct clk **clocks; + struct clk_core **clocks; int i, ret; - clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk *) + clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * MAX77686_CLKS_NUM, GFP_KERNEL); if (!clocks) return -ENOMEM; @@ -203,7 +203,7 @@ err_clocks: static int max77686_clk_remove(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); - struct clk **clocks = platform_get_drvdata(pdev); + struct clk_core **clocks = platform_get_drvdata(pdev); int i; if (iodev->dev->of_node) diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c index 30a3b69..c503c09 100644 --- a/drivers/clk/clk-moxart.c +++ b/drivers/clk/clk-moxart.c @@ -18,7 +18,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *ref_clk; + struct clk_core *clk, *ref_clk; unsigned int mul; const char *name = node->name; const char *parent_name; @@ -35,7 +35,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) mul = readl(base + 0x30) >> 3 & 0x3f; iounmap(base); - ref_clk = of_clk_get(node, 0); + ref_clk = of_clk_provider_get(node, 0); if (IS_ERR(ref_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; @@ -56,7 +56,7 @@ CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock", void __init moxart_of_apb_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *pll_clk; + struct clk_core *clk, *pll_clk; unsigned int div, val; unsigned int div_idx[] = { 2, 3, 4, 6, 8}; const char *name = node->name; @@ -78,7 +78,7 @@ void __init moxart_of_apb_clk_init(struct device_node *node) val = 0; div = div_idx[val] * 2; - pll_clk = of_clk_get(node, 0); + pll_clk = of_clk_provider_get(node, 0); if (IS_ERR(pll_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 4f96ff3..2879053 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -113,13 +113,13 @@ const struct clk_ops clk_mux_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_mux_ro_ops); -struct clk *clk_register_mux_table(struct device *dev, const char *name, +struct clk_core *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; u8 width = 0; @@ -165,7 +165,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, } EXPORT_SYMBOL_GPL(clk_register_mux_table); -struct clk *clk_register_mux(struct device *dev, const char *name, +struct clk_core *clk_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock) diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 05e04ce..5d87366 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -254,11 +254,11 @@ static const struct clk_ops pll_clk_ops = { .recalc_rate = pll_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init pll_clk_register(struct device *dev, const char *name, const char *parent_name, u32 id) { - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll; struct clk_init_data init; @@ -346,11 +346,11 @@ static const struct clk_ops src_clk_ops = { .recalc_rate = src_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init src_clk_register(struct device *dev, const char *name, const char *parent_name, u8 id) { - struct clk *clk; + struct clk_core *clk; struct clk_src *sclk; struct clk_init_data init; @@ -510,7 +510,7 @@ module_init(nomadik_src_clk_init_debugfs); static void __init of_nomadik_pll_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 pll_id; @@ -533,7 +533,7 @@ CLK_OF_DECLARE(nomadik_pll_clk, static void __init of_nomadik_hclk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; @@ -557,7 +557,7 @@ CLK_OF_DECLARE(nomadik_hclk_clk, static void __init of_nomadik_src_clk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 clk_id; diff --git a/drivers/clk/clk-nspire.c b/drivers/clk/clk-nspire.c index a378db7..e9c43f4 100644 --- a/drivers/clk/clk-nspire.c +++ b/drivers/clk/clk-nspire.c @@ -69,7 +69,7 @@ static void __init nspire_ahbdiv_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; struct nspire_clk_info info; @@ -111,7 +111,7 @@ static void __init nspire_clk_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct nspire_clk_info info; diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c index 8e58edf..5619ee9 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-ppc-corenet.c @@ -64,7 +64,7 @@ const struct clk_ops cmux_ops = { static void __init core_mux_init(struct device_node *np) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct cmux_clk *cmux_clk; struct device_node *node; @@ -150,7 +150,7 @@ static void __init core_pll_init(struct device_node *np) int i, rc, count; const char *clk_name, *parent_name; struct clk_onecell_data *onecell_data; - struct clk **subclks; + struct clk_core **subclks; void __iomem *base; base = of_iomap(np, 0); @@ -184,7 +184,7 @@ static void __init core_pll_init(struct device_node *np) /* output clock number per PLL */ clocks_per_pll = count; - subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); + subclks = kzalloc(sizeof(struct clk_core *) * count, GFP_KERNEL); if (!subclks) { pr_err("%s: could not allocate subclks\n", __func__); goto err_map; @@ -246,7 +246,7 @@ err_map: static void __init sysclk_init(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct device_node *np = of_get_parent(node); u32 rate; diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index b7797fb..17fc7e1 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -29,7 +29,7 @@ #define s2mps11_name(a) (a->hw.init->name) -static struct clk **clk_table; +static struct clk_core **clk_table; static struct clk_onecell_data clk_data; enum { @@ -43,7 +43,7 @@ struct s2mps11_clk { struct sec_pmic_dev *iodev; struct device_node *clk_np; struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_lookup *lookup; u32 mask; unsigned int reg; @@ -174,7 +174,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev) s2mps11_clk = s2mps11_clks; - clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk *) * + clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * S2MPS11_CLKS_NUM, GFP_KERNEL); if (!clk_table) return -ENOMEM; diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 3b2a66f..57c9eb5 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -56,10 +56,10 @@ struct si5351_driver_data { struct regmap *regmap; struct clk_onecell_data onecell; - struct clk *pxtal; + struct clk_core *pxtal; const char *pxtal_name; struct clk_hw xtal; - struct clk *pclkin; + struct clk_core *pclkin; const char *pclkin_name; struct clk_hw clkin; @@ -1128,12 +1128,12 @@ static int si5351_dt_parse(struct i2c_client *client, if (!pdata) return -ENOMEM; - pdata->clk_xtal = of_clk_get(np, 0); + pdata->clk_xtal = of_clk_provider_get(np, 0); if (!IS_ERR(pdata->clk_xtal)) - clk_put(pdata->clk_xtal); - pdata->clk_clkin = of_clk_get(np, 1); + __clk_put(pdata->clk_xtal); + pdata->clk_clkin = of_clk_provider_get(np, 1); if (!IS_ERR(pdata->clk_clkin)) - clk_put(pdata->clk_clkin); + __clk_put(pdata->clk_clkin); /* * property silabs,pll-source : <num src>, [<..>] @@ -1306,7 +1306,7 @@ static int si5351_i2c_probe(struct i2c_client *client, struct si5351_platform_data *pdata; struct si5351_driver_data *drvdata; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; const char *parent_names[4]; u8 num_parents, num_clocks; int ret, n; @@ -1545,7 +1545,8 @@ static int si5351_i2c_probe(struct i2c_client *client, /* set initial clkout rate */ if (pdata->clkout[n].rate != 0) { int ret; - ret = clk_set_rate(clk, pdata->clkout[n].rate); + ret = clk_provider_set_rate(clk, + pdata->clkout[n].rate); if (ret != 0) { dev_err(&client->dev, "Cannot set rate : %d\n", ret); diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c index fc167b3..f0eec4e 100644 --- a/drivers/clk/clk-si570.c +++ b/drivers/clk/clk-si570.c @@ -407,7 +407,7 @@ static int si570_probe(struct i2c_client *client, { struct clk_si570 *data; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; u32 initial_fout, factory_fout, stability; int err; enum clk_si570_variant variant = id->driver_data; @@ -476,7 +476,7 @@ static int si570_probe(struct i2c_client *client, /* Read the requested initial output frequency from device tree */ if (!of_property_read_u32(client->dev.of_node, "clock-frequency", &initial_fout)) { - err = clk_set_rate(clk, initial_fout); + err = clk_provider_set_rate(clk, initial_fout); if (err) { of_clk_del_provider(client->dev.of_node); return err; diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c index 1ada79a..2422857 100644 --- a/drivers/clk/clk-twl6040.c +++ b/drivers/clk/clk-twl6040.c @@ -31,7 +31,7 @@ struct twl6040_clk { struct twl6040 *twl6040; struct device *dev; struct clk_hw mcpdm_fclk; - struct clk *clk; + struct clk_core *clk; int enabled; }; diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index 406bfc1..7e9ec00 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -688,7 +688,7 @@ static const struct clk_ops syscon_clk_ops = { .set_rate = syscon_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init syscon_clk_register(struct device *dev, const char *name, const char *parent_name, unsigned long flags, bool hw_ctrld, @@ -696,7 +696,7 @@ syscon_clk_register(struct device *dev, const char *name, void __iomem *en_reg, u8 en_bit, u16 clk_val) { - struct clk *clk; + struct clk_core *clk; struct clk_syscon *sclk; struct clk_init_data init; @@ -867,7 +867,7 @@ static struct u300_clock const u300_clk_lookup[] __initconst = { static void __init of_u300_syscon_clk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; void __iomem *res_reg; @@ -1110,11 +1110,11 @@ static const struct clk_ops mclk_ops = { .set_rate = mclk_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init mclk_clk_register(struct device *dev, const char *name, const char *parent_name, bool is_mspro) { - struct clk *clk; + struct clk_core *clk; struct clk_mclk *mclk; struct clk_init_data init; @@ -1141,7 +1141,7 @@ mclk_clk_register(struct device *dev, const char *name, static void __init of_u300_syscon_mclk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index 37e9288..e5fb933 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -232,7 +232,7 @@ static const struct clk_ops vt8500_gated_divisor_clk_ops = { static __init void vtwm_device_clk_init(struct device_node *node) { u32 en_reg, div_reg; - struct clk *clk; + struct clk_core *clk; struct clk_device *dev_clk; const char *clk_name = node->name; const char *parent_name; @@ -650,7 +650,7 @@ static const struct clk_ops vtwm_pll_ops = { static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c index b131041..d2d745e 100644 --- a/drivers/clk/clk-wm831x.c +++ b/drivers/clk/clk-wm831x.c @@ -25,9 +25,9 @@ struct wm831x_clk { struct clk_hw xtal_hw; struct clk_hw fll_hw; struct clk_hw clkout_hw; - struct clk *xtal; - struct clk *fll; - struct clk *clkout; + struct clk_core *xtal; + struct clk_core *fll; + struct clk_core *clkout; bool xtal_ena; }; diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index dd8a62d..ce3ed34 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -124,13 +124,13 @@ const struct clk_ops xgene_clk_pll_ops = { .recalc_rate = xgene_clk_pll_recalc_rate, }; -static struct clk *xgene_register_clk_pll(struct device *dev, +static struct clk_core *xgene_register_clk_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 pll_offset, u32 type, spinlock_t *lock) { struct xgene_clk_pll *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the APM clock structure */ @@ -166,7 +166,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev, static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; void *reg; reg = of_iomap(np, 0); @@ -395,12 +395,12 @@ const struct clk_ops xgene_clk_ops = { .round_rate = xgene_clk_round_rate, }; -static struct clk *xgene_register_clk(struct device *dev, +static struct clk_core *xgene_register_clk(struct device *dev, const char *name, const char *parent_name, struct xgene_dev_parameters *parameters, spinlock_t *lock) { struct xgene_clk *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int rc; @@ -442,7 +442,7 @@ static struct clk *xgene_register_clk(struct device *dev, static void __init xgene_devclk_init(struct device_node *np) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; struct resource res; int rc; struct xgene_dev_parameters parameters; diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h index c798138..d278572 100644 --- a/drivers/clk/clk.h +++ b/drivers/clk/clk.h @@ -10,8 +10,8 @@ */ #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) -struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); -struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec); +struct clk_core *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); +struct clk_core *__of_clk_get_from_provider(struct of_phandle_args *clkspec); void of_clk_lock(void); void of_clk_unlock(void); #endif diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 339945d..d7d3667 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -296,7 +296,7 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw, static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_mmc *mclk = to_mmc(hw); unsigned long best = 0; @@ -427,11 +427,11 @@ static struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, +static struct clk_core *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, void __iomem *base, struct device_node *np) { struct clk_mmc *mclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; mclk = kzalloc(sizeof(*mclk), GFP_KERNEL); @@ -487,7 +487,7 @@ static void __init hi3620_mmc_clk_init(struct device_node *node) if (WARN_ON(!clk_data)) return; - clk_data->clks = kzalloc(sizeof(struct clk *) * num, GFP_KERNEL); + clk_data->clks = kzalloc(sizeof(struct clk_core *) * num, GFP_KERNEL); if (!clk_data->clks) { pr_err("%s: fail to allocate mmc clk\n", __func__); return; diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index a078e84..3fcd2ba 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -42,7 +42,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, int nr_clks) { struct hisi_clock_data *clk_data; - struct clk **clk_table; + struct clk_core **clk_table; void __iomem *base; if (np) { @@ -63,7 +63,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, } clk_data->base = base; - clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); + clk_table = kzalloc(sizeof(struct clk_core *) * nr_clks, GFP_KERNEL); if (!clk_table) { pr_err("%s: could not allocate clock lookup table\n", __func__); goto err_data; @@ -81,7 +81,7 @@ err: void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -102,7 +102,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -122,7 +122,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -151,7 +151,7 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -180,7 +180,7 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -208,7 +208,7 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..f7fc4b9 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -90,7 +90,7 @@ struct hisi_gate_clock { const char *alias; }; -struct clk *hisi_register_clkgate_sep(struct device *, const char *, +struct clk_core *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, u8, spinlock_t *); diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index b03d5a7..61f7236 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -96,14 +96,14 @@ static struct clk_ops clkgate_separated_ops = { .is_enabled = clkgate_separated_is_enabled, }; -struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, +struct clk_core *hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clkgate_separated *sclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c index 86f1e36..3f7db44 100644 --- a/drivers/clk/keystone/gate.c +++ b/drivers/clk/keystone/gate.c @@ -163,7 +163,7 @@ static const struct clk_ops clk_psc_ops = { * @psc_data: platform data to configure this clock * @lock: spinlock used by this clock */ -static struct clk *clk_register_psc(struct device *dev, +static struct clk_core *clk_register_psc(struct device *dev, const char *name, const char *parent_name, struct clk_psc_data *psc_data, @@ -171,7 +171,7 @@ static struct clk *clk_register_psc(struct device *dev, { struct clk_init_data init; struct clk_psc *psc; - struct clk *clk; + struct clk_core *clk; psc = kzalloc(sizeof(*psc), GFP_KERNEL); if (!psc) @@ -204,7 +204,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) const char *clk_name = node->name; const char *parent_name; struct clk_psc_data *data; - struct clk *clk; + struct clk_core *clk; int i; data = kzalloc(sizeof(*data), GFP_KERNEL); diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 0dd8a4b..fc3156e 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -116,14 +116,14 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pllclk_recalc, }; -static struct clk *clk_register_pll(struct device *dev, +static struct clk_core *clk_register_pll(struct device *dev, const char *name, const char *parent_name, struct clk_pll_data *pll_data) { struct clk_init_data init; struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -158,7 +158,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) { struct clk_pll_data *pll_data; const char *parent_name; - struct clk *clk; + struct clk_core *clk; int i; pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL); @@ -239,7 +239,7 @@ static void __init of_pll_div_clk_init(struct device_node *node) const char *parent_name; void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; of_property_read_string(node, "clock-output-names", &clk_name); @@ -282,7 +282,7 @@ static void __init of_pll_mux_clk_init(struct device_node *node) { void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *parents[2]; const char *clk_name = node->name; diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c index d14120e..4ca8713 100644 --- a/drivers/clk/mmp/clk-apbc.c +++ b/drivers/clk/mmp/clk-apbc.c @@ -120,12 +120,12 @@ struct clk_ops clk_apbc_ops = { .unprepare = clk_apbc_unprepare, }; -struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock) { struct clk_apbc *apbc; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apbc = kzalloc(sizeof(*apbc), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c index abe182b..c24e6e7 100644 --- a/drivers/clk/mmp/clk-apmu.c +++ b/drivers/clk/mmp/clk-apmu.c @@ -66,11 +66,11 @@ struct clk_ops clk_apmu_ops = { .disable = clk_apmu_disable, }; -struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock) { struct clk_apmu *apmu; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apmu = kzalloc(sizeof(*apmu), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c index 23a56f5..0386cdd 100644 --- a/drivers/clk/mmp/clk-frac.c +++ b/drivers/clk/mmp/clk-frac.c @@ -116,14 +116,14 @@ static struct clk_ops clk_factor_ops = { .set_rate = clk_factor_set_rate, }; -struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt) { struct clk_factor *factor; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!masks) { pr_err("%s: must pass a clk_factor_mask\n", __func__); diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c index b2721ca..98bd73f 100644 --- a/drivers/clk/mmp/clk-mmp2.c +++ b/drivers/clk/mmp/clk-mmp2.c @@ -77,8 +77,8 @@ static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"}; void __init mmp2_clk_init(void) { - struct clk *clk; - struct clk *vctcxo; + struct clk_core *clk; + struct clk_core *vctcxo; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -192,7 +192,7 @@ void __init mmp2_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(clk, 14745600); + clk_provider_set_rate(clk, 14745600); clk_register_clkdev(clk, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "vctcxo", @@ -251,7 +251,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -262,7 +262,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -273,7 +273,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", @@ -284,7 +284,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.3", NULL); clk = mmp_clk_register_apbc("uart3", "uart3_mux", diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c index 014396b..e4f50ab 100644 --- a/drivers/clk/mmp/clk-pxa168.c +++ b/drivers/clk/mmp/clk-pxa168.c @@ -68,8 +68,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa168_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -159,7 +159,7 @@ void __init pxa168_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -202,7 +202,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -213,7 +213,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -224,7 +224,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c index 9efc6a4..b5c215e 100644 --- a/drivers/clk/mmp/clk-pxa910.c +++ b/drivers/clk/mmp/clk-pxa910.c @@ -66,8 +66,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa910_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbcp_base; @@ -164,7 +164,7 @@ void __init pxa910_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -207,7 +207,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -218,7 +218,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -229,7 +229,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h index ab86dd4..1477e61 100644 --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h @@ -20,15 +20,15 @@ struct clk_factor_tbl { unsigned int den; }; -extern struct clk *mmp_clk_register_pll2(const char *name, +extern struct clk_core *mmp_clk_register_pll2(const char *name, const char *parent_name, unsigned long flags); -extern struct clk *mmp_clk_register_apbc(const char *name, +extern struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock); -extern struct clk *mmp_clk_register_apmu(const char *name, +extern struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock); -extern struct clk *mmp_clk_register_factor(const char *name, +extern struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt); diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index d1e5863..1be15c4 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -238,7 +238,7 @@ mvebu_corediv_clk_init(struct device_node *node, { struct clk_init_data init; struct clk_corediv *corediv; - struct clk **clks; + struct clk_core **clks; void __iomem *base; const char *parent_name; const char *clk_name; @@ -253,7 +253,7 @@ mvebu_corediv_clk_init(struct device_node *node, clk_data.clk_num = soc_desc->ndescs; /* clks holds the clock array */ - clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), + clks = kcalloc(clk_data.clk_num, sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clks)) goto err_unmap; diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c index 3821a88..59a40c7 100644 --- a/drivers/clk/mvebu/clk-cpu.c +++ b/drivers/clk/mvebu/clk-cpu.c @@ -40,7 +40,7 @@ struct cpu_clk { void __iomem *pmu_dfs; }; -static struct clk **clks; +static struct clk_core **clks; static struct clk_onecell_data clk_data; @@ -195,8 +195,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) for_each_node_by_type(dn, "cpu") { struct clk_init_data init; - struct clk *clk; - struct clk *parent_clk; + struct clk_core *clk; + struct clk_core *parent_clk; char *clk_name = kzalloc(5, GFP_KERNEL); int cpu, err; @@ -208,7 +208,7 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out; sprintf(clk_name, "cpu%d", cpu); - parent_clk = of_clk_get(node, 0); + parent_clk = of_clk_provider_get(node, 0); cpuclk[cpu].parent_name = __clk_get_name(parent_clk); cpuclk[cpu].clk_name = clk_name; diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 25ceccf..7e6c320 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -43,7 +43,7 @@ void __init mvebu_coreclk_setup(struct device_node *np, /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; - clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { iounmap(base); @@ -91,13 +91,13 @@ void __init mvebu_coreclk_setup(struct device_node *np, struct clk_gating_ctrl { spinlock_t lock; - struct clk **gates; + struct clk_core **gates; int num_gates; }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) -static struct clk *clk_gating_get_src( +static struct clk_core *clk_gating_get_src( struct of_phandle_args *clkspec, void *data) { struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data; @@ -119,7 +119,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, const struct clk_gating_soc_desc *desc) { struct clk_gating_ctrl *ctrl; - struct clk *clk; + struct clk_core *clk; void __iomem *base; const char *default_parent = NULL; int n; @@ -128,10 +128,10 @@ void __init mvebu_clk_gating_setup(struct device_node *np, if (WARN_ON(!base)) return; - clk = of_clk_get(np, 0); + clk = of_clk_provider_get(np, 0); if (!IS_ERR(clk)) { default_parent = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); @@ -145,7 +145,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, n++; ctrl->num_gates = n; - ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), + ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!ctrl->gates)) goto gates_out; diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c index 90e1da9..57f93e5 100644 --- a/drivers/clk/mxs/clk-div.c +++ b/drivers/clk/mxs/clk-div.c @@ -74,11 +74,11 @@ static struct clk_ops clk_div_ops = { .set_rate = clk_div_set_rate, }; -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_div *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; div = kzalloc(sizeof(*div), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c index e6aa6b5..87083e4 100644 --- a/drivers/clk/mxs/clk-frac.c +++ b/drivers/clk/mxs/clk-frac.c @@ -108,11 +108,11 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; frac = kzalloc(sizeof(*frac), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 9fc9359..fc7fdf2 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -94,7 +94,7 @@ enum imx23_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx23_clk clks_init_on[] __initdata = { @@ -171,7 +171,7 @@ static void __init mx23_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init); diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index a6c3501..083add7 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -148,7 +148,7 @@ enum imx28_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx28_clk clks_init_on[] __initdata = { @@ -250,6 +250,6 @@ static void __init mx28_clocks_init(struct device_node *np) clk_register_clkdev(clks[enet_out], NULL, "enet_out"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init); diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c index fadae41..8e29d79 100644 --- a/drivers/clk/mxs/clk-pll.c +++ b/drivers/clk/mxs/clk-pll.c @@ -86,11 +86,11 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate) { struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 4adeed6..ad1aa00 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -125,11 +125,11 @@ static const struct clk_ops clk_ref_ops = { .set_rate = clk_ref_set_rate, }; -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_ref *ref; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; ref = kzalloc(sizeof(*ref), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h index ef10ad9..b258ea5 100644 --- a/drivers/clk/mxs/clk.h +++ b/drivers/clk/mxs/clk.h @@ -23,24 +23,24 @@ extern spinlock_t mxs_lock; int mxs_clk_wait(void __iomem *reg, u8 shift); -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate); -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -static inline struct clk *mxs_clk_fixed(const char *name, int rate) +static inline struct clk_core *mxs_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mxs_clk_gate(const char *name, +static inline struct clk_core *mxs_clk_gate(const char *name, const char *parent_name, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, @@ -48,7 +48,7 @@ static inline struct clk *mxs_clk_gate(const char *name, &mxs_lock); } -static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *mxs_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parent_names, int num_parents) { return clk_register_mux(NULL, name, parent_names, num_parents, @@ -56,7 +56,7 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, reg, shift, width, 0, &mxs_lock); } -static inline struct clk *mxs_clk_fixed_factor(const char *name, +static inline struct clk_core *mxs_clk_fixed_factor(const char *name, const char *parent_name, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent_name, diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index b638c58..59f118c 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -375,7 +375,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -402,7 +402,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg *rcg = to_clk_rcg(hw); @@ -410,7 +410,7 @@ static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, } static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); @@ -418,7 +418,7 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, } static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg *rcg = to_clk_rcg(hw); const struct freq_tbl *f = rcg->freq_tbl; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index cd185d5..6aac1ec 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -188,7 +188,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -219,7 +219,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -372,7 +372,7 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, } static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -423,7 +423,7 @@ const struct clk_ops clk_edp_pixel_ops = { EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -485,14 +485,14 @@ static const struct frac_entry frac_table_pixel[] = { }; static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); unsigned long request, src_rate; int delta = 100000; const struct freq_tbl *f = rcg->freq_tbl; const struct frac_entry *frac = frac_table_pixel; - struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src); + struct clk_core *parent = *p = clk_get_parent_by_index(hw->clk, f->src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; @@ -519,7 +519,7 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, int delta = 100000; u32 mask = BIT(rcg->hid_width) - 1; u32 hid_div; - struct clk *parent = clk_get_parent_by_index(hw->clk, f.src); + struct clk_core *parent = clk_get_parent_by_index(hw->clk, f.src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; diff --git a/drivers/clk/qcom/clk-regmap.c b/drivers/clk/qcom/clk-regmap.c index a58ba39..2a98040 100644 --- a/drivers/clk/qcom/clk-regmap.c +++ b/drivers/clk/qcom/clk-regmap.c @@ -101,7 +101,7 @@ EXPORT_SYMBOL_GPL(clk_disable_regmap); * clk_regmap struct via this function so that the regmap is initialized * and so that the clock is registered with the common clock framework. */ -struct clk *devm_clk_register_regmap(struct device *dev, +struct clk_core *devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) { if (dev && dev_get_regmap(dev, NULL)) diff --git a/drivers/clk/qcom/clk-regmap.h b/drivers/clk/qcom/clk-regmap.h index 491a63d..89258cb 100644 --- a/drivers/clk/qcom/clk-regmap.h +++ b/drivers/clk/qcom/clk-regmap.h @@ -39,7 +39,7 @@ struct clk_regmap { int clk_is_enabled_regmap(struct clk_hw *hw); int clk_enable_regmap(struct clk_hw *hw); void clk_disable_regmap(struct clk_hw *hw); -struct clk * +struct clk_core * devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk); #endif diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index eeb3eea..afd40ea 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -24,7 +24,7 @@ struct qcom_cc { struct qcom_reset_controller reset; struct clk_onecell_data data; - struct clk *clks[]; + struct clk_core *clks[]; }; struct regmap * @@ -48,9 +48,9 @@ int qcom_cc_really_probe(struct platform_device *pdev, { int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct clk_onecell_data *data; - struct clk **clks; + struct clk_core **clks; struct qcom_reset_controller *reset; struct qcom_cc *cc; size_t num_clks = desc->num_clks; diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c index 0c4b727..2d41fdb 100644 --- a/drivers/clk/qcom/gcc-msm8660.c +++ b/drivers/clk/qcom/gcc-msm8660.c @@ -2718,7 +2718,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); static int gcc_msm8660_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; /* Temporary until RPM clocks supported */ diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 007534f..ed8f8f5 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -3488,7 +3488,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table); static int gcc_msm8960_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; const struct of_device_id *match; diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 7af7c18..8326b1f 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -2699,7 +2699,7 @@ static void msm8974_pro_clock_override(void) static int gcc_msm8974_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; bool pro; const struct of_device_id *id; diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 2e80a21..bb60d61 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -505,7 +505,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) int ret = 0; u32 val; struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); - struct clk *clk = hw->clk; + struct clk_core *clk = hw->clk; int num_parents = __clk_get_num_parents(hw->clk); /* @@ -517,7 +517,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) * needs to be on at what time. */ for (i = 0; i < num_parents; i++) { - ret = clk_prepare_enable(clk_get_parent_by_index(clk, i)); + ret = clk_provider_prepare_enable(clk_get_parent_by_index(clk, i)); if (ret) goto err; } @@ -546,7 +546,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) err: for (i--; i >= 0; i--) - clk_disable_unprepare(clk_get_parent_by_index(clk, i)); + clk_provider_disable_unprepare(clk_get_parent_by_index(clk, i)); return ret; } diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index f2a1c7a..3b82a43 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -297,7 +297,7 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { * Common registering of pll clocks */ -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, +struct clk_core *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, @@ -308,7 +308,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, struct clk_init_data init; struct rockchip_clk_pll *pll; struct clk_mux *pll_mux; - struct clk *pll_clk, *mux_clk; + struct clk_core *pll_clk, *mux_clk; char pll_name[20]; int ret; @@ -377,7 +377,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, goto err_pll; } - ret = clk_notifier_register(pll_clk, &pll->clk_nb); + ret = clk_provider_notifier_register(pll_clk, &pll->clk_nb); if (ret) { pr_err("%s: failed to register clock notifier for %s : %d\n", __func__, name, ret); @@ -417,7 +417,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, return mux_clk; err_mux: - ret = clk_notifier_unregister(pll_clk, &pll->clk_nb); + ret = clk_provider_notifier_unregister(pll_clk, &pll->clk_nb); if (ret) { pr_err("%s: could not unregister clock notifier in error path : %d\n", __func__, ret); diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index a83a6d8..89b2a17 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { static void __init rk3188_common_clk_init(struct device_node *np) { void __iomem *reg_base; - struct clk *clk; + struct clk_core *clk; reg_base = of_iomap(np, 0); if (!reg_base) { diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 0d8c6c5..f52f73e 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -683,7 +683,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { static void __init rk3288_clk_init(struct device_node *np) { void __iomem *reg_base; - struct clk *clk; + struct clk_core *clk; reg_base = of_iomap(np, 0); if (!reg_base) { diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c index 4cf838d5..faa8dfa 100644 --- a/drivers/clk/rockchip/clk-rockchip.c +++ b/drivers/clk/rockchip/clk-rockchip.c @@ -54,7 +54,7 @@ static void __init rk2928_gate_clk_init(struct device_node *node) if (!clk_data) return; - clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc(qty * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 278cf9d..66d6348 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -37,7 +37,7 @@ * * sometimes without one of those components. */ -struct clk *rockchip_clk_register_branch(const char *name, +struct clk_core *rockchip_clk_register_branch(const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, @@ -45,7 +45,7 @@ struct clk *rockchip_clk_register_branch(const char *name, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) { - struct clk *clk; + struct clk_core *clk; struct clk_mux *mux = NULL; struct clk_gate *gate = NULL; struct clk_divider *div = NULL; @@ -104,7 +104,7 @@ struct clk *rockchip_clk_register_branch(const char *name, } static DEFINE_SPINLOCK(clk_lock); -static struct clk **clk_table; +static struct clk_core **clk_table; static void __iomem *reg_base; static struct clk_onecell_data clk_data; static struct device_node *cru_node; @@ -117,7 +117,7 @@ void __init rockchip_clk_init(struct device_node *np, void __iomem *base, cru_node = np; grf = ERR_PTR(-EPROBE_DEFER); - clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); + clk_table = kcalloc(nr_clks, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_table) pr_err("%s: could not allocate clock lookup table\n", __func__); @@ -133,7 +133,7 @@ struct regmap *rockchip_clk_get_grf(void) return grf; } -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) +void rockchip_clk_add_lookup(struct clk_core *clk, unsigned int id) { if (clk_table && id) clk_table[id] = clk; @@ -142,7 +142,7 @@ void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) { - struct clk *clk; + struct clk_core *clk; int idx; for (idx = 0; idx < nr_pll; idx++, list++) { @@ -165,7 +165,7 @@ void __init rockchip_clk_register_branches( struct rockchip_clk_branch *list, unsigned int nr_clk) { - struct clk *clk = NULL; + struct clk_core *clk = NULL; unsigned int idx; unsigned long flags; diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 887cbde..8d761ba 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -113,7 +113,7 @@ struct rockchip_pll_clock { .rate_table = _rtable, \ } -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, +struct clk_core *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int con_offset, int grf_lock_offset, int lock_shift, int reg_mode, int mode_shift, @@ -324,7 +324,7 @@ struct rockchip_clk_branch { void rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); struct regmap *rockchip_clk_get_grf(void); -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id); +void rockchip_clk_add_lookup(struct clk_core *clk, unsigned int id); void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list, unsigned int nr_clk); void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list, diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 13eae14c..f5639bf 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -26,7 +26,7 @@ enum exynos_audss_clk_type { }; static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; +static struct clk_core **clk_table; static void __iomem *reg_base; static struct clk_onecell_data clk_data; @@ -83,7 +83,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; const char *sclk_pcm_p = "sclk_pcm0"; - struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; + struct clk_core *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; const struct of_device_id *match; enum exynos_audss_clk_type variant; @@ -100,7 +100,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + sizeof(struct clk_core *) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -111,8 +111,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) else clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1; - pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); - pll_in = devm_clk_get(&pdev->dev, "pll_in"); + pll_ref = devm_clk_provider_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_provider_get(&pdev->dev, "pll_in"); if (!IS_ERR(pll_ref)) mout_audss_p[0] = __clk_get_name(pll_ref); if (!IS_ERR(pll_in)) @@ -122,8 +122,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); - cdclk = devm_clk_get(&pdev->dev, "cdclk"); - sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + cdclk = devm_clk_provider_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_provider_get(&pdev->dev, "sclk_audio"); if (!IS_ERR(cdclk)) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) @@ -161,7 +161,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); - sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + sclk_pcm_in = devm_clk_provider_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 3a7cb25..50eea66 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -30,7 +30,7 @@ struct exynos_clkout { struct clk_mux mux; spinlock_t slock; struct clk_onecell_data data; - struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS]; + struct clk_core *clk_table[EXYNOS_CLKOUT_NR_CLKS]; void __iomem *reg; u32 pmu_debug_save; }; @@ -57,7 +57,7 @@ static struct syscore_ops exynos_clkout_syscore_ops = { static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) { const char *parent_names[EXYNOS_CLKOUT_PARENTS]; - struct clk *parents[EXYNOS_CLKOUT_PARENTS]; + struct clk_core *parents[EXYNOS_CLKOUT_PARENTS]; int parent_count; int ret; int i; @@ -73,7 +73,7 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) char name[] = "clkoutXX"; snprintf(name, sizeof(name), "clkout%d", i); - parents[i] = of_clk_get_by_name(node, name); + parents[i] = of_clk_provider_get_by_name(node, name); if (IS_ERR(parents[i])) { parent_names[i] = "none"; continue; @@ -125,7 +125,7 @@ err_unmap: clks_put: for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) if (!IS_ERR(parents[i])) - clk_put(parents[i]); + __clk_put(parents[i]); free_clkout: kfree(clkout); diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ac163d7..9a2270b 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1230,19 +1230,19 @@ static unsigned long exynos4_get_xom(void) static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) { struct samsung_fixed_rate_clock fclk; - struct clk *clk; + struct clk_core *clk; unsigned long finpll_f = 24000000; char *parent_name; unsigned int xom = exynos4_get_xom(); parent_name = xom & 1 ? "xusbxti" : "xxti"; - clk = clk_get(NULL, parent_name); + clk = clk_provider_get(NULL, parent_name); if (IS_ERR(clk)) { pr_err("%s: failed to lookup parent clock %s, assuming " "fin_pll clock frequency is 24MHz\n", __func__, parent_name); } else { - finpll_f = clk_get_rate(clk); + finpll_f = clk_provider_get_rate(clk); } fclk.id = CLK_FIN_PLL; diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..aaf234a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -910,12 +910,12 @@ static const struct clk_ops samsung_pll2550x_clk_ops = { .recalc_rate = samsung_pll2550x_recalc_rate, }; -struct clk * __init samsung_clk_register_pll2550x(const char *name, +struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset) { struct samsung_clk_pll2550x *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -1149,7 +1149,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, void __iomem *base) { struct samsung_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int ret, len; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..81af344 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -97,7 +97,7 @@ struct samsung_pll_rate_table { unsigned int vsel; }; -extern struct clk * __init samsung_clk_register_pll2550x(const char *name, +extern struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset); diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c index 0449cc0..05354bd 100644 --- a/drivers/clk/samsung/clk-s3c2410-dclk.c +++ b/drivers/clk/samsung/clk-s3c2410-dclk.c @@ -87,12 +87,12 @@ const struct clk_ops s3c24xx_clkout_ops = { .determine_rate = __clk_mux_determine_rate, }; -struct clk *s3c24xx_register_clkout(struct device *dev, const char *name, +struct clk_core *s3c24xx_register_clkout(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u8 shift, u32 mask) { struct s3c24xx_clkout *clkout; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the clkout */ @@ -237,7 +237,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk; struct resource *mem; - struct clk **clk_table; + struct clk_core **clk_table; struct s3c24xx_dclk_drv_data *dclk_variant; int ret, i; @@ -251,7 +251,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) spin_lock_init(&s3c24xx_dclk->dclk_lock); clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * DCLK_MAX_CLKS, + sizeof(struct clk_core *) * DCLK_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -329,21 +329,21 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) s3c24xx_dclk->dclk1_div_change_nb.notifier_call = s3c24xx_dclk1_div_notify; - ret = clk_notifier_register(clk_table[DIV_DCLK0], - &s3c24xx_dclk->dclk0_div_change_nb); + ret = clk_provider_notifier_register(clk_table[DIV_DCLK0], + &s3c24xx_dclk->dclk0_div_change_nb); if (ret) goto err_clk_register; - ret = clk_notifier_register(clk_table[DIV_DCLK1], - &s3c24xx_dclk->dclk1_div_change_nb); + ret = clk_provider_notifier_register(clk_table[DIV_DCLK1], + &s3c24xx_dclk->dclk1_div_change_nb); if (ret) goto err_dclk_notify; return 0; err_dclk_notify: - clk_notifier_unregister(clk_table[DIV_DCLK0], - &s3c24xx_dclk->dclk0_div_change_nb); + clk_provider_notifier_unregister(clk_table[DIV_DCLK0], + &s3c24xx_dclk->dclk0_div_change_nb); err_clk_register: for (i = 0; i < DCLK_MAX_CLKS; i++) if (clk_table[i] && !IS_ERR(clk_table[i])) @@ -355,13 +355,13 @@ err_clk_register: static int s3c24xx_dclk_remove(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); - struct clk **clk_table = s3c24xx_dclk->clk_data.clks; + struct clk_core **clk_table = s3c24xx_dclk->clk_data.clks; int i; - clk_notifier_unregister(clk_table[DIV_DCLK1], - &s3c24xx_dclk->dclk1_div_change_nb); - clk_notifier_unregister(clk_table[DIV_DCLK0], - &s3c24xx_dclk->dclk0_div_change_nb); + clk_provider_notifier_unregister(clk_table[DIV_DCLK1], + &s3c24xx_dclk->dclk1_div_change_nb); + clk_provider_notifier_unregister(clk_table[DIV_DCLK0], + &s3c24xx_dclk->dclk0_div_change_nb); for (i = 0; i < DCLK_MAX_CLKS; i++) clk_unregister(clk_table[i]); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index deab84d..68133fa 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -52,14 +52,14 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks) { struct samsung_clk_provider *ctx; - struct clk **clk_table; + struct clk_core **clk_table; int i; ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); if (!ctx) panic("could not allocate clock provider context.\n"); - clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); + clk_table = kcalloc(nr_clks, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_table) panic("could not allocate clock lookup table\n"); @@ -85,7 +85,7 @@ void __init samsung_clk_of_add_provider(struct device_node *np, } /* add a clock instance to the clock lookup table used for dt based lookup */ -void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, +void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk_core *clk, unsigned int id) { if (ctx->clk_data.clks && id) @@ -97,7 +97,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; if (!ctx->clk_data.clks) { @@ -130,7 +130,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -159,7 +159,7 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -180,7 +180,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, struct samsung_mux_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -212,7 +212,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, struct samsung_div_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -251,7 +251,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, struct samsung_gate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -303,7 +303,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, /* utility function to get the rate of a specified clock */ unsigned long _get_rate(const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = __clk_lookup(clk_name); if (!clk) { @@ -311,5 +311,5 @@ unsigned long _get_rate(const char *clk_name) return 0; } - return clk_get_rate(clk); + return clk_provider_get_rate(clk); } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 66ab36b..a13c8b2 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -336,7 +336,7 @@ extern void __init samsung_clk_of_register_fixed_ext( const struct of_device_id *clk_matches); extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, - struct clk *clk, unsigned int id); + struct clk_core *clk, unsigned int id); extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index f065f69..c6712fb 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -119,7 +119,7 @@ static void __init cpg_div6_clock_init(struct device_node *np) struct div6_clock *clock; const char *parent_name; const char *name; - struct clk *clk; + struct clk_core *clk; int ret; clock = kzalloc(sizeof(*clock), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-emev2.c b/drivers/clk/shmobile/clk-emev2.c index 6c7c929..2e3a45b 100644 --- a/drivers/clk/shmobile/clk-emev2.c +++ b/drivers/clk/shmobile/clk-emev2.c @@ -71,7 +71,7 @@ static void __init emev2_smu_init(void) static void __init emev2_smu_clkdiv_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; @@ -89,7 +89,7 @@ CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv", static void __init emev2_smu_gclk_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c index 2d2fe77..2659676 100644 --- a/drivers/clk/shmobile/clk-mstp.c +++ b/drivers/clk/shmobile/clk-mstp.c @@ -121,13 +121,13 @@ static const struct clk_ops cpg_mstp_clock_ops = { .is_enabled = cpg_mstp_clock_is_enabled, }; -static struct clk * __init +static struct clk_core * __init cpg_mstp_clock_register(const char *name, const char *parent_name, unsigned int index, struct mstp_clock_group *group) { struct clk_init_data init; struct mstp_clock *clock; - struct clk *clk; + struct clk_core *clk; clock = kzalloc(sizeof(*clock), GFP_KERNEL); if (!clock) { @@ -157,7 +157,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) { struct mstp_clock_group *group; const char *idxname; - struct clk **clks; + struct clk_core **clks; unsigned int i; group = kzalloc(sizeof(*group), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-r8a7740.c b/drivers/clk/shmobile/clk-r8a7740.c index 1e2eaae..8889e6a 100644 --- a/drivers/clk/shmobile/clk-r8a7740.c +++ b/drivers/clk/shmobile/clk-r8a7740.c @@ -61,7 +61,7 @@ static const struct clk_div_table div4_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, const char *name) { @@ -147,7 +147,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, static void __init r8a7740_cpg_clocks_init(struct device_node *np) { struct r8a7740_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -180,7 +180,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c index 652ecac..96b51b1 100644 --- a/drivers/clk/shmobile/clk-r8a7779.c +++ b/drivers/clk/shmobile/clk-r8a7779.c @@ -90,7 +90,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, const struct cpg_clk_config *config, unsigned int plla_mult, const char *name) @@ -124,7 +124,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) { const struct cpg_clk_config *config; struct r8a7779_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i, plla_mult; int num_clks; @@ -153,7 +153,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index dff7f79..d8bdeb8 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -133,12 +133,12 @@ static const struct clk_ops cpg_z_clk_ops = { .set_rate = cpg_z_clk_set_rate, }; -static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) +static struct clk_core * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) { static const char *parent_name = "pll0"; struct clk_init_data init; struct cpg_z_clk *zclk; - struct clk *clk; + struct clk_core *clk; zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); if (!zclk) @@ -212,7 +212,7 @@ static const struct clk_div_table cpg_sd01_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, const struct cpg_pll_config *config, const char *name) @@ -279,7 +279,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) { const struct cpg_pll_config *config; struct rcar_gen2_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -312,7 +312,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c index 7e68e86..414e20e 100644 --- a/drivers/clk/shmobile/clk-rz.c +++ b/drivers/clk/shmobile/clk-rz.c @@ -28,7 +28,7 @@ struct rz_cpg { * Initialization */ -static struct clk * __init +static struct clk_core * __init rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) { u32 val; @@ -67,7 +67,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static void __init rz_cpg_clocks_init(struct device_node *np) { struct rz_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned i; int num_clks; @@ -86,7 +86,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/sirf/clk-atlas6.c b/drivers/clk/sirf/clk-atlas6.c index d63b76c..9cce269 100644 --- a/drivers/clk/sirf/clk-atlas6.c +++ b/drivers/clk/sirf/clk-atlas6.c @@ -113,7 +113,7 @@ static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *atlas6_clks[maxclk]; +static struct clk_core *atlas6_clks[maxclk]; static void __init atlas6_clk_init(struct device_node *np) { diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c index 37af51c..05f5040 100644 --- a/drivers/clk/sirf/clk-common.c +++ b/drivers/clk/sirf/clk-common.c @@ -165,9 +165,9 @@ static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, * SiRF SoC has not cpu clock control, * So bypass to it's parent pll. */ - struct clk *parent_clk = clk_get_parent(hw->clk); - struct clk *pll_parent_clk = clk_get_parent(parent_clk); - unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); + struct clk_core *pll_parent_clk = clk_provider_get_parent(parent_clk); + unsigned long pll_parent_rate = clk_provider_get_rate(pll_parent_clk); return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate); } @@ -178,7 +178,7 @@ static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, * SiRF SoC has not cpu clock control, * So return the parent pll rate. */ - struct clk *parent_clk = clk_get_parent(hw->clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); return __clk_get_rate(parent_clk); } @@ -403,34 +403,34 @@ static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int ret1, ret2; - struct clk *cur_parent; + struct clk_core *cur_parent; - if (rate == clk_get_rate(clk_pll1.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + if (rate == clk_provider_get_rate(clk_pll1.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll2.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + if (rate == clk_provider_get_rate(clk_pll2.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll3.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); + if (rate == clk_provider_get_rate(clk_pll3.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll3.hw.clk); return ret1; } - cur_parent = clk_get_parent(hw->clk); + cur_parent = clk_provider_get_parent(hw->clk); /* switch to tmp pll before setting parent clock's rate */ if (cur_parent == clk_pll1.hw.clk) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); BUG_ON(ret1); } - ret2 = clk_set_rate(clk_pll1.hw.clk, rate); + ret2 = clk_provider_set_rate(clk_pll1.hw.clk, rate); - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret2 ? ret2 : ret1; } diff --git a/drivers/clk/sirf/clk-prima2.c b/drivers/clk/sirf/clk-prima2.c index 6968e2e..751187b 100644 --- a/drivers/clk/sirf/clk-prima2.c +++ b/drivers/clk/sirf/clk-prima2.c @@ -112,7 +112,7 @@ static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *prima2_clks[maxclk]; +static struct clk_core *prima2_clks[maxclk]; static void __init prima2_clk_init(struct device_node *np) { diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index dd3a78c..e3a6fe6 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -188,7 +188,7 @@ static void __init __socfpga_gate_init(struct device_node *node, u32 div_reg[3]; u32 clk_phase[2]; u32 fixed_div; - struct clk *clk; + struct clk_core *clk; struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 46531c3..a63be19 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -53,7 +53,7 @@ static __init void __socfpga_periph_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index de6da95..4ed91a4 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -81,11 +81,11 @@ static struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static __init struct clk *__socfpga_pll_init(struct device_node *node, +static __init struct clk_core *__socfpga_pll_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c index bdfb442..18334c3 100644 --- a/drivers/clk/spear/clk-aux-synth.c +++ b/drivers/clk/spear/clk-aux-synth.c @@ -134,14 +134,14 @@ static struct clk_ops clk_aux_ops = { .set_rate = clk_aux_set_rate, }; -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk) { struct clk_aux *aux; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); @@ -177,7 +177,7 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name, goto free_aux; if (gate_name) { - struct clk *tgate_clk; + struct clk_core *tgate_clk; tgate_clk = clk_register_gate(NULL, gate_name, aux_name, CLK_SET_RATE_PARENT, reg, diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c index dffd4ce..bce2c0e 100644 --- a/drivers/clk/spear/clk-frac-synth.c +++ b/drivers/clk/spear/clk-frac-synth.c @@ -122,13 +122,13 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *clk_register_frac(const char *name, const char *parent_name, +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c index 1afc18c..f8e13f3 100644 --- a/drivers/clk/spear/clk-gpt-synth.c +++ b/drivers/clk/spear/clk-gpt-synth.c @@ -111,13 +111,13 @@ static struct clk_ops clk_gpt_ops = { .set_rate = clk_gpt_set_rate, }; -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_gpt *gpt; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c index 1b9b65b..226f2ec 100644 --- a/drivers/clk/spear/clk-vco-pll.c +++ b/drivers/clk/spear/clk-vco-pll.c @@ -272,16 +272,16 @@ static struct clk_ops clk_vco_ops = { .set_rate = clk_vco_set_rate, }; -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk) + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk) { struct clk_vco *vco; struct clk_pll *pll; - struct clk *vco_clk, *tpll_clk, *tvco_gate_clk; + struct clk_core *vco_clk, *tpll_clk, *tvco_gate_clk; struct clk_init_data vco_init, pll_init; const char **vco_parent_name; diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h index 9317376..777322e 100644 --- a/drivers/clk/spear/clk.h +++ b/drivers/clk/spear/clk.h @@ -110,22 +110,22 @@ typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, int index); /* clk register routines */ -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); -struct clk *clk_register_frac(const char *name, const char *parent_name, + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk); +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk); + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk); long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index 4daa597..1e95410 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c @@ -385,7 +385,7 @@ static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c index 5a5c664..f42965c 100644 --- a/drivers/clk/spear/spear1340_clock.c +++ b/drivers/clk/spear/spear1340_clock.c @@ -442,7 +442,7 @@ static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", void __init spear1340_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index bb5f387..5b8d659 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c @@ -140,7 +140,7 @@ static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", #ifdef CONFIG_MACH_SPEAR300 static void __init spear300_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 1, 1); @@ -170,7 +170,7 @@ static inline void spear300_clk_init(void) { } #ifdef CONFIG_MACH_SPEAR310 static void __init spear310_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 1); @@ -246,9 +246,9 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; static void __init spear320_clk_init(void __iomem *soc_config_base, - struct clk *ras_apb_clk) + struct clk_core *ras_apb_clk) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, CLK_IS_ROOT, 125000000); @@ -344,7 +344,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, 0, &_lock); clk_register_clkdev(clk, NULL, "a3000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -353,7 +353,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a4000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -384,12 +384,12 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, clk_register_clkdev(clk, NULL, "60100000.serial"); } #else -static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } +static inline void spear320_clk_init(void __iomem *sb, struct clk_core *rc) { } #endif void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) { - struct clk *clk, *clk1, *ras_apb_clk; + struct clk_core *clk, *clk1, *ras_apb_clk; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index 4f649c9..db946f7 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c @@ -116,7 +116,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = { void __init spear6xx_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c index 2282cef..699f7a1 100644 --- a/drivers/clk/st/clk-flexgen.c +++ b/drivers/clk/st/clk-flexgen.c @@ -163,12 +163,12 @@ static const struct clk_ops flexgen_ops = { .set_rate = flexgen_set_rate, }; -struct clk *clk_register_flexgen(const char *name, +struct clk_core *clk_register_flexgen(const char *name, const char **parent_names, u8 num_parents, void __iomem *reg, spinlock_t *lock, u32 idx, unsigned long flexgen_flags) { struct flexgen *fgxbar; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; u32 xbar_shift; void __iomem *xbar_reg, *fdiv_reg; @@ -223,8 +223,8 @@ struct clk *clk_register_flexgen(const char *name, else pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); return clk; } @@ -283,7 +283,7 @@ void __init st_of_flexgen_setup(struct device_node *np) goto err; } - clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), + clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; @@ -293,7 +293,7 @@ void __init st_of_flexgen_setup(struct device_node *np) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index af94ed8..ceda1f2 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -614,13 +614,13 @@ static const struct clk_ops st_quadfs_pll_c32_ops = { .set_rate = quadfs_pll_fs660c32_set_rate, }; -static struct clk * __init st_clk_register_quadfs_pll( +static struct clk_core * __init st_clk_register_quadfs_pll( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, spinlock_t *lock) { struct st_clk_quadfs_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -1018,13 +1018,13 @@ static const struct clk_ops st_quadfs_ops = { .recalc_rate = quadfs_recalc_rate, }; -static struct clk * __init st_clk_register_quadfs_fsynth( +static struct clk_core * __init st_clk_register_quadfs_fsynth( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, spinlock_t *lock) { struct st_clk_quadfs_fsynth *fs; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -1102,7 +1102,7 @@ static void __init st_of_create_quadfs_fsynths( return; clk_data->clk_num = QUADFS_MAX_CHAN; - clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *), + clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { @@ -1111,7 +1111,7 @@ static void __init st_of_create_quadfs_fsynths( } for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -1136,8 +1136,8 @@ static void __init st_of_create_quadfs_fsynths( clk_data->clks[fschan] = clk; pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); } } @@ -1147,7 +1147,7 @@ static void __init st_of_create_quadfs_fsynths( static void __init st_of_quadfs_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *pll_name, *clk_parent_name; void __iomem *reg; spinlock_t *lock; @@ -1181,8 +1181,8 @@ static void __init st_of_quadfs_setup(struct device_node *np) else pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); st_of_create_quadfs_fsynths(np, pll_name, (struct clkgen_quadfs_data *)match->data, diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c index 79dc40b..d2a951f 100644 --- a/drivers/clk/st/clkgen-mux.c +++ b/drivers/clk/st/clkgen-mux.c @@ -215,7 +215,7 @@ static const struct clk_ops clkgena_divmux_ops = { /** * clk_register_genamux - register a genamux clock with the clock framework */ -struct clk *clk_register_genamux(const char *name, +struct clk_core *clk_register_genamux(const char *name, const char **parent_names, u8 num_parents, void __iomem *reg, const struct clkgena_divmux_data *muxdata, @@ -227,7 +227,7 @@ struct clk *clk_register_genamux(const char *name, const int mux_width = 2; const int divider_width = 5; struct clkgena_divmux *genamux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int i; @@ -280,8 +280,8 @@ struct clk *clk_register_genamux(const char *name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); err: return clk; } @@ -413,14 +413,14 @@ void __init st_of_clkgena_divmux_setup(struct device_node *np) goto err; clk_data->clk_num = data->num_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -490,7 +490,7 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) const struct of_device_id *match; void __iomem *reg; const char *parent_name, *clk_name; - struct clk *clk; + struct clk_core *clk; struct clkgena_prediv_data *data; match = of_match_node(clkgena_prediv_of_match, np); @@ -522,8 +522,8 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) of_clk_add_provider(np, of_clk_src_simple_get, clk); pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); return; } @@ -625,7 +625,7 @@ static struct of_device_id mux_of_match[] = { void __init st_of_clkgen_mux_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; void __iomem *reg; const char **parents; int num_parents; @@ -662,8 +662,8 @@ void __init st_of_clkgen_mux_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); of_clk_add_provider(np, of_clk_src_simple_get, clk); @@ -726,14 +726,14 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) goto err; clk_data->clk_num = VCC_MAX_CHANNELS; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; struct clk_gate *gate; struct clk_divider *div; @@ -796,8 +796,8 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); clk_data->clks[i] = clk; } diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index 29769d7..32bac02 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -390,13 +390,13 @@ static const struct clk_ops st_pll1200c32_ops = { .recalc_rate = recalc_stm_pll1200c32, }; -static struct clk * __init clkgen_pll_register(const char *parent_name, +static struct clk_core * __init clkgen_pll_register(const char *parent_name, struct clkgen_pll_data *pll_data, void __iomem *reg, const char *clk_name) { struct clkgen_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -422,16 +422,16 @@ static struct clk * __init clkgen_pll_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } -static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, +static struct clk_core * __init clkgen_c65_lsdiv_register(const char *parent_name, const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2); if (IS_ERR(clk)) @@ -439,8 +439,8 @@ static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -484,7 +484,7 @@ static void __init clkgena_c65_pll_setup(struct device_node *np) return; clk_data->clk_num = num_pll_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) @@ -543,14 +543,14 @@ err: CLK_OF_DECLARE(clkgena_c65_plls, "st,clkgena-plls-c65", clkgena_c65_pll_setup); -static struct clk * __init clkgen_odf_register(const char *parent_name, +static struct clk_core * __init clkgen_odf_register(const char *parent_name, void * __iomem reg, struct clkgen_pll_data *pll_data, int odf, spinlock_t *odf_lock, const char *odf_name) { - struct clk *clk; + struct clk_core *clk; unsigned long flags; struct clk_gate *gate; struct clk_divider *div; @@ -588,8 +588,8 @@ static struct clk * __init clkgen_odf_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -640,7 +640,7 @@ static struct of_device_id c32_pll_of_match[] = { static void __init clkgen_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name, *pll_name; void __iomem *pll_base; int num_odfs, odf; @@ -676,14 +676,14 @@ static void __init clkgen_c32_pll_setup(struct device_node *np) return; clk_data->clk_num = num_odfs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (odf = 0; odf < num_odfs; odf++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -723,7 +723,7 @@ static struct of_device_id c32_gpu_pll_of_match[] = { static void __init clkgengpu_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; const char *clk_name; diff --git a/drivers/clk/sunxi/clk-a10-hosc.c b/drivers/clk/sunxi/clk-a10-hosc.c index 0481d5d..c5e4c41 100644 --- a/drivers/clk/sunxi/clk-a10-hosc.c +++ b/drivers/clk/sunxi/clk-a10-hosc.c @@ -25,7 +25,7 @@ static DEFINE_SPINLOCK(hosc_lock); static void __init sun4i_osc_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_fixed_rate *fixed; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c index 5296fd6..63c7dd5 100644 --- a/drivers/clk/sunxi/clk-a20-gmac.c +++ b/drivers/clk/sunxi/clk-a20-gmac.c @@ -55,7 +55,7 @@ static DEFINE_SPINLOCK(gmac_lock); static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_mux *mux; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c index 2057c8a..bb2d4b2 100644 --- a/drivers/clk/sunxi/clk-factors.c +++ b/drivers/clk/sunxi/clk-factors.c @@ -79,9 +79,9 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate, static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { - struct clk *clk = hw->clk, *parent, *best_parent = NULL; + struct clk_core *clk = hw->clk, *parent, *best_parent = NULL; int i, num_parents; unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c index e10d052..f29b06e 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c @@ -74,7 +74,7 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev) /* Worst-case size approximation and memory allocation */ ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE); clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1), - sizeof(struct clk *), GFP_KERNEL); + sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) return -ENOMEM; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c index 1fa2337..5e4649e 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0.c @@ -35,7 +35,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev) const char *clk_parent; struct resource *r; void __iomem *reg; - struct clk *clk; + struct clk_core *clk; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, r); diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c index eca8ca0..984d5d0 100644 --- a/drivers/clk/sunxi/clk-sun6i-ar100.c +++ b/drivers/clk/sunxi/clk-sun6i-ar100.c @@ -46,7 +46,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw, static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { int nparents = __clk_get_num_parents(hw->clk); long best_rate = -EINVAL; @@ -57,7 +57,7 @@ static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, for (i = 0; i < nparents; i++) { unsigned long parent_rate; unsigned long tmp_rate; - struct clk *parent; + struct clk_core *parent; unsigned long div; int shift; @@ -176,7 +176,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev) struct clk_init_data init; struct ar100_clk *ar100; struct resource *r; - struct clk *clk; + struct clk_core *clk; int nparents; int i; diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c index 1f5ba9b..fa308fd 100644 --- a/drivers/clk/sunxi/clk-sun8i-apb0.c +++ b/drivers/clk/sunxi/clk-sun8i-apb0.c @@ -26,7 +26,7 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev) const char *clk_parent; struct resource *r; void __iomem *reg; - struct clk *clk; + struct clk_core *clk; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, r); diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index b654b7b..44c4470 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -403,7 +403,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, * clk_sunxi_mmc_phase_control() - configures MMC clock phase control */ -void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output) +void clk_sunxi_mmc_phase_control(struct clk_core *clk, u8 sample, u8 output) { #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) @@ -582,10 +582,10 @@ static const struct factors_data sun7i_a20_out_data __initconst = { .getter = sun7i_a20_get_out_factors, }; -static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, +static struct clk_core * __init sunxi_factors_clk_setup(struct device_node *node, const struct factors_data *data) { - struct clk *clk; + struct clk_core *clk; struct clk_factors *factors; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; @@ -695,7 +695,7 @@ static const struct mux_data sun4i_apb1_mux_data __initconst = { static void __init sunxi_mux_clk_setup(struct device_node *node, struct mux_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parents[SUNXI_MAX_PARENTS]; void __iomem *reg; @@ -777,7 +777,7 @@ static const struct div_data sun6i_a31_apb2_div_data __initconst = { static void __init sunxi_divider_clk_setup(struct device_node *node, struct div_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *clk_parent; void __iomem *reg; @@ -976,7 +976,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) return; - clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; @@ -1078,7 +1078,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, struct clk_onecell_data *clk_data; const char *parent; const char *clk_name; - struct clk **clks, *pclk; + struct clk_core **clks, *pclk; struct clk_hw *gate_hw, *rate_hw; const struct clk_ops *rate_ops; struct clk_gate *gate = NULL; @@ -1291,10 +1291,10 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks) /* Protect the clocks that needs to stay on */ for (i = 0; i < nclocks; i++) { - struct clk *clk = clk_get(NULL, clocks[i]); + struct clk_core *clk = clk_provider_get(NULL, clocks[i]); if (!IS_ERR(clk)) - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); } } diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c index c0f7843..53c3488 100644 --- a/drivers/clk/tegra/clk-audio-sync.c +++ b/drivers/clk/tegra/clk-audio-sync.c @@ -54,12 +54,12 @@ const struct clk_ops tegra_clk_sync_source_ops = { .recalc_rate = clk_sync_source_recalc_rate, }; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long rate, unsigned long max_rate) { struct tegra_clk_sync_source *sync; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; sync = kzalloc(sizeof(*sync), GFP_KERNEL); if (!sync) { diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 290f9c1..7a1212b7 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -147,13 +147,13 @@ const struct clk_ops tegra_clk_frac_div_ops = { .round_rate = clk_frac_div_round_rate, }; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock) { struct tegra_clk_frac_div *divider; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; divider = kzalloc(sizeof(*divider), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 0aa8830..61f5d55 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -128,12 +128,12 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .disable = clk_periph_disable, }; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt) { struct tegra_clk_periph_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *pregs; diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 9e899c18..ea26de3 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -138,13 +138,13 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = { .set_rate = clk_periph_set_rate, }; -static struct clk *_tegra_clk_register_periph(const char *name, +static struct clk_core *_tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *bank; bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); @@ -186,7 +186,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, return clk; } -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) @@ -195,7 +195,7 @@ struct clk *tegra_clk_register_periph(const char *name, periph, clk_base, offset, flags); } -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset) diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 3598987..49ae7b1 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -87,13 +87,13 @@ const struct clk_ops tegra_clk_pll_out_ops = { .disable = clk_pll_out_disable, }; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags, spinlock_t *lock) { struct tegra_clk_pll_out *pll_out; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c7c6d8f..cb61b7d 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -729,7 +729,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) static int clk_plle_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); struct tegra_clk_pll_freq_table sel; u32 val; int err; @@ -1033,7 +1033,7 @@ static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, state = clk_pll_is_enabled(hw); if (state) { - if (rate != clk_get_rate(hw->clk)) { + if (rate != clk_provider_get_rate(hw->clk)) { pr_err("%s: Cannot change active PLLM\n", __func__); ret = -EINVAL; goto out; @@ -1285,7 +1285,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) u32 val; int ret; unsigned long flags = 0; - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) return -EINVAL; @@ -1430,7 +1430,7 @@ static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, return pll; } -static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, +static struct clk_core *_tegra_clk_register_pll(struct tegra_clk_pll *pll, const char *name, const char *parent_name, unsigned long flags, const struct clk_ops *ops) { @@ -1448,13 +1448,13 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, return clk_register(NULL, &pll->hw); } -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1479,13 +1479,13 @@ static struct div_nmp pll_e_nmp = { .divp_width = PLLE_BASE_DIVP_WIDTH, }; -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1550,14 +1550,14 @@ static const struct clk_ops tegra_clk_plle_tegra114_ops = { }; -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; int err; u32 val, val_iddq; @@ -1603,7 +1603,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, @@ -1611,7 +1611,7 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, { u32 val; struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; @@ -1649,14 +1649,14 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; if (!pll_params->pdiv_tohw) @@ -1688,13 +1688,13 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { - struct clk *parent, *clk; + struct clk_core *parent, *clk; struct pdiv_map *p_tohw = pll_params->pdiv_tohw; struct tegra_clk_pll *pll; struct tegra_clk_pll_freq_table cfg; @@ -1762,14 +1762,14 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 val, val_aux; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1812,13 +1812,13 @@ static const struct clk_ops tegra_clk_pllss_ops = { .set_rate = clk_pllxc_set_rate, }; -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; struct tegra_clk_pll_freq_table cfg; unsigned long parent_rate; u32 val; diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 2fd924d..e843d20 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -127,13 +127,13 @@ const struct clk_ops tegra_clk_super_ops = { .set_parent = clk_super_set_parent, }; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock) { struct tegra_clk_super_mux *super; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; super = kzalloc(sizeof(*super), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c index 5c38aab..484a900 100644 --- a/drivers/clk/tegra/clk-tegra-audio.c +++ b/drivers/clk/tegra/clk-tegra-audio.c @@ -128,8 +128,8 @@ void __init tegra_audio_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_a_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; /* PLLA */ diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index f3b7738..503e261 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -36,8 +36,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, unsigned long *osc_freq, unsigned long *pll_ref_freq) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; u32 val, pll_ref_div; unsigned osc_idx; @@ -81,8 +81,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* clk_32k */ dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 37f32c4..125dfa2 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -585,8 +585,8 @@ static void __init periph_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { struct tegra_clk_periph_regs *bank; @@ -615,8 +615,8 @@ static void __init gate_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { struct tegra_periph_init_data *data; @@ -640,8 +640,8 @@ static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c index 08b21c1..2ff427a 100644 --- a/drivers/clk/tegra/clk-tegra-pmc.c +++ b/drivers/clk/tegra/clk-tegra-pmc.c @@ -82,8 +82,8 @@ static struct pmc_clk_init_data pmc_clks[] = { void __init tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index feb3201..e6224c4 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -53,8 +53,8 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", static void __init tegra_sclk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* SCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); @@ -99,8 +99,8 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* CCLKG */ dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index f760f31..68efd84 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -936,14 +936,14 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = { [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, }; -static struct clk **clks; +static struct clk_core **clks; static unsigned long osc_freq; static unsigned long pll_ref_freq; static int __init tegra114_osc_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; u32 val, pll_ref_div; val = readl_relaxed(clk_base + OSC_CTRL); @@ -973,7 +973,7 @@ static int __init tegra114_osc_clk_init(void __iomem *clk_base) static void __init tegra114_fixed_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; /* clk_32k */ clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, @@ -1078,7 +1078,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, @@ -1200,7 +1200,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = { static __init void tegra114_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; struct tegra_periph_init_data *data; int i; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 9525c68..43f0632 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1017,7 +1017,7 @@ static struct tegra_devclk devclks[] __initdata = { { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, }; -static struct clk **clks; +static struct clk_core **clks; static void tegra124_utmi_param_configure(void __iomem *clk_base) { @@ -1104,7 +1104,7 @@ static void tegra124_utmi_param_configure(void __iomem *clk_base) static __init void tegra124_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; /* xusb_ss_div2 */ clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, @@ -1148,7 +1148,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index dace2b1..6783355 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -162,7 +162,7 @@ static void __iomem *pmc_base; _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { { 12000000, 600000000, 600, 12, 0, 8 }, @@ -633,7 +633,7 @@ static unsigned int tegra20_get_pll_ref_div(void) static void tegra20_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, @@ -713,7 +713,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void tegra20_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* CCLK */ clk = tegra_clk_register_super_mux("cclk", cclk_parents, @@ -738,7 +738,7 @@ static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", static void __init tegra20_audio_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* audio */ clk = clk_register_mux(NULL, "audio_mux", audio_parents, @@ -800,7 +800,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* ac97 */ @@ -871,7 +871,7 @@ static void __init tegra20_periph_clk_init(void) static void __init tegra20_osc_clk_init(void) { - struct clk *clk; + struct clk_core *clk; unsigned long input_freq; unsigned int pll_ref_div; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 5bbacd0..5a03645 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -205,7 +205,7 @@ static DEFINE_SPINLOCK(pll_d_lock); _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; /* * Structure defining the fields for USB UTMI clocks Parameters. @@ -921,7 +921,7 @@ static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; static void __init tegra30_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, @@ -1012,7 +1012,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void __init tegra30_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* * Clock input to cclk_g divided from pll_p using @@ -1134,7 +1134,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra30_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* dsia */ diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index f87c609..e90432c 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -69,7 +69,7 @@ struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; int *periph_clk_enb_refcnt; static int periph_banks; -static struct clk **clks; +static struct clk_core **clks; static int clk_num; static struct clk_onecell_data clk_data; @@ -165,7 +165,7 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } -struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) +struct clk_core ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; @@ -179,7 +179,7 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) periph_banks = banks; - clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); + clks = kzalloc(num * sizeof(struct clk_core *), GFP_KERNEL); if (!clks) kfree(periph_clk_enb_refcnt); @@ -189,9 +189,9 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) } void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; dup_list->clk_id < clk_max; dup_list++) { clk = clks[dup_list->clk_id]; @@ -201,9 +201,9 @@ void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, } void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; tbl->clk_id < clk_max; tbl++) { clk = clks[tbl->clk_id]; @@ -211,8 +211,8 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, return; if (tbl->parent_id < clk_max) { - struct clk *parent = clks[tbl->parent_id]; - if (clk_set_parent(clk, parent)) { + struct clk_core *parent = clks[tbl->parent_id]; + if (clk_provider_set_parent(clk, parent)) { pr_err("%s: Failed to set parent %s of %s\n", __func__, __clk_get_name(parent), __clk_get_name(clk)); @@ -221,7 +221,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->rate) - if (clk_set_rate(clk, tbl->rate)) { + if (clk_provider_set_rate(clk, tbl->rate)) { pr_err("%s: Failed to set rate %lu of %s\n", __func__, tbl->rate, __clk_get_name(clk)); @@ -229,7 +229,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->state) - if (clk_prepare_enable(clk)) { + if (clk_provider_prepare_enable(clk)) { pr_err("%s: Failed to enable %s\n", __func__, __clk_get_name(clk)); WARN_ON(1); @@ -286,7 +286,7 @@ void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num) } } -struct clk ** __init tegra_lookup_dt_id(int clk_id, +struct clk_core ** __init tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk) { if (tegra_clk[clk_id].present) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 16ec8d6..3093aa4 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -39,7 +39,7 @@ struct tegra_clk_sync_source { extern const struct clk_ops tegra_clk_sync_source_ops; extern int *periph_clk_enb_refcnt; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long fixed_rate, unsigned long max_rate); /** @@ -82,7 +82,7 @@ struct tegra_clk_frac_div { #define TEGRA_DIVIDER_UART BIT(3) extern const struct clk_ops tegra_clk_frac_div_ops; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); @@ -258,47 +258,47 @@ struct tegra_clk_pll { extern const struct clk_ops tegra_clk_pll_ops; extern const struct clk_ops tegra_clk_plle_ops; -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock, unsigned long parent_rate); -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); @@ -325,7 +325,7 @@ struct tegra_clk_pll_out { #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) extern const struct clk_ops tegra_clk_pll_out_ops; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, spinlock_t *lock); @@ -394,7 +394,7 @@ struct tegra_clk_periph_gate { #define TEGRA_PERIPH_NO_GATE BIT(5) extern const struct clk_ops tegra_clk_periph_gate_ops; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt); @@ -427,11 +427,11 @@ struct tegra_clk_periph { #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 extern const struct clk_ops tegra_clk_periph_ops; -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags); -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset); @@ -540,7 +540,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) extern const struct clk_ops tegra_clk_super_ops; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); @@ -590,15 +590,15 @@ struct tegra_devclk { }; void tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); struct tegra_clk_periph_regs *get_reg_bank(int clkid); -struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); +struct clk_core **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); -struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); +struct clk_core **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); void tegra_add_of_provider(struct device_node *np); void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index 72d9727..a162c21 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -135,10 +135,10 @@ static void __init omap_clk_register_apll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *ad = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - ad->clk_ref = of_clk_get(node, 0); - ad->clk_bypass = of_clk_get(node, 1); + ad->clk_ref = of_clk_provider_get(node, 0); + ad->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) { pr_debug("clk-ref or clk-bypass for %s not ready, retry\n", @@ -332,7 +332,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) struct dpll_data *ad = NULL; struct clk_hw_omap *clk_hw = NULL; struct clk_init_data *init = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name; u32 val; diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c index c808ab3..a48fe6f 100644 --- a/drivers/clk/ti/clk-2xxx.c +++ b/drivers/clk/ti/clk-2xxx.c @@ -237,10 +237,10 @@ static int __init omap2xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "dpll_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "mpu_ck")) / 1000000)); return 0; } diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 028b337..0988f1e 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -121,7 +121,7 @@ static const char *enable_init_clks[] = { int __init am33xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am33xx_clks); @@ -139,12 +139,12 @@ int __init am33xx_dt_clk_init(void) * oscillator clock. */ - clk1 = clk_get_sys(NULL, "sys_clkin_ck"); - clk2 = clk_get_sys(NULL, "timer3_fck"); - clk_set_parent(clk2, clk1); + clk1 = clk_provider_get_sys(NULL, "sys_clkin_ck"); + clk2 = clk_provider_get_sys(NULL, "timer3_fck"); + clk_provider_set_parent(clk2, clk1); - clk2 = clk_get_sys(NULL, "timer6_fck"); - clk_set_parent(clk2, clk1); + clk2 = clk_provider_get_sys(NULL, "timer6_fck"); + clk_provider_set_parent(clk2, clk1); /* * The On-Chip 32K RC Osc clock is not an accurate clock-source as per * the design/spec, so as a result, for example, timer which supposed @@ -152,9 +152,9 @@ int __init am33xx_dt_clk_init(void) * not expected by any use-case, so change WDT1 clock source to PRCM * 32KHz clock. */ - clk1 = clk_get_sys(NULL, "wdt1_fck"); - clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "wdt1_fck"); + clk2 = clk_provider_get_sys(NULL, "clkdiv32k_ick"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 0d1750a..58ef20e 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -365,10 +365,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "core_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "arm_fck")) / 1000000)); if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) omap3_clk_lock_dpll5(); diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 3795fce..1277452 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -116,7 +116,7 @@ static struct ti_dt_clk am43xx_clks[] = { int __init am43xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am43xx_clks); @@ -132,9 +132,9 @@ int __init am43xx_dt_clk_init(void) * By selecting dpll_core_m5_ck as the clocksource fixes this issue. * In AM335x dpll_core_m5_ck is the default clocksource. */ - clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); - clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "cpsw_cpts_rft_clk"); + clk2 = clk_provider_get_sys(NULL, "dpll_core_m5_ck"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 02517a8..1adc399 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -281,7 +281,7 @@ static struct ti_dt_clk omap44xx_clks[] = { int __init omap4xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap44xx_clks); @@ -291,8 +291,8 @@ int __init omap4xxx_dt_clk_init(void) * Lock USB DPLL on OMAP4 devices so that the L3INIT power * domain can transition to retention state when not in use. */ - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); @@ -302,12 +302,12 @@ int __init omap4xxx_dt_clk_init(void) * locking the ABE DPLL on boot. * Lock the ABE DPLL in any case to avoid issues with audio. */ - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_refclk_mux_ck"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 5e18399..5b603b5 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -225,34 +225,35 @@ static struct ti_dt_clk omap54xx_clks[] = { int __init omap5xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap54xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_clk_mux"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_m2x2_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); + rc = clk_provider_set_rate(abe_dpll, + OMAP5_DPLL_ABE_DEFFREQ * 2); if (rc) pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ / 2); if (rc) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 62ac8f6..9dba0bb 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -307,39 +307,39 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + struct clk_core *abe_dpll_mux, *sys_clkin2, *dpll_ck; ti_dt_clocks_register(dra7xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); - sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); - dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_mux = clk_provider_get_sys(NULL, "abe_dpll_sys_clk_mux"); + sys_clkin2 = clk_provider_get_sys(NULL, "sys_clkin2"); + dpll_ck = clk_provider_get_sys(NULL, "dpll_abe_ck"); - rc = clk_set_parent(abe_dpll_mux, sys_clkin2); + rc = clk_provider_set_parent(abe_dpll_mux, sys_clkin2); if (!rc) - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2); + dpll_ck = clk_provider_get_sys(NULL, "dpll_abe_m2x2_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2); if (rc) pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); + dpll_ck = clk_provider_get_sys(NULL, "dpll_gmac_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); if (rc) pr_err("%s: failed to configure GMAC DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); + dpll_ck = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); + dpll_ck = clk_provider_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ / 2); if (rc) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index 4a65b41..029a0d3 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c @@ -40,7 +40,7 @@ struct dra7_atl_clock_info; struct dra7_atl_desc { - struct clk *clk; + struct clk_core *clk; struct clk_hw hw; struct dra7_atl_clock_info *cinfo; int id; @@ -165,7 +165,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) struct dra7_atl_desc *clk_hw = NULL; struct clk_init_data init = { 0 }; const char **parent_names = NULL; - struct clk *clk; + struct clk_core *clk; clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); if (!clk_hw) { @@ -233,7 +233,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) char prop[5]; struct dra7_atl_desc *cdesc; struct of_phandle_args clkspec; - struct clk *clk; + struct clk_core *clk; int rc; rc = of_parse_phandle_with_args(node, "ti,provided-clocks", diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index b1a6f71..d88a70d0 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -41,7 +41,7 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) { struct ti_dt_clk *c; struct device_node *node; - struct clk *clk; + struct clk_core *clk; struct of_phandle_args clkspec; for (c = oclks; c->node_name != NULL; c++) { diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index f1e0038..6bc75d8 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -26,7 +26,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *clk_hw; const char *clkdm_name = node->name; int i; @@ -35,7 +35,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells"); for (i = 0; i < num_clks; i++) { - clk = of_clk_get(node, i); + clk = of_clk_provider_get(node, i); if (__clk_get_flags(clk) & CLK_IS_BASIC) { pr_warn("can't setup clkdm for basic clk %s\n", __clk_get_name(clk)); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index 19d8980..2cbee34 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -119,7 +119,7 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) static void __init ti_clk_register_composite(struct clk_hw *hw, struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); struct component_clk *comp; int num_parents = 0; diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index e6aa10d..1c41515 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -246,7 +246,7 @@ const struct clk_ops ti_clk_divider_ops = { .set_rate = ti_clk_divider_set_rate, }; -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, @@ -254,7 +254,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -434,7 +434,7 @@ static int __init ti_clk_divider_populate(struct device_node *node, */ static void __init of_ti_divider_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; u8 clk_divider_flags = 0; diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 79791e1..e1f74cc 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -128,10 +128,10 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *dd = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - dd->clk_ref = of_clk_get(node, 0); - dd->clk_bypass = of_clk_get(node, 1); + dd->clk_ref = of_clk_provider_get(node, 0); + dd->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) { pr_debug("clk-ref or clk-bypass missing for %s, retry later\n", @@ -175,7 +175,7 @@ static void ti_clk_register_dpll_x2(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *name = node->name; diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c index c2c8a28..2aa2701 100644 --- a/drivers/clk/ti/fixed-factor.c +++ b/drivers/clk/ti/fixed-factor.c @@ -33,7 +33,7 @@ */ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index b326d27..dd1b813 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -94,7 +94,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *clk_name = node->name; diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c index 9c3e8c4..e2f2bc0 100644 --- a/drivers/clk/ti/interface.c +++ b/drivers/clk/ti/interface.c @@ -34,7 +34,7 @@ static const struct clk_ops ti_interface_clk_ops = { static void __init _of_ti_interface_clk_setup(struct device_node *node, const struct clk_hw_omap_ops *ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *parent_name; diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index e9d650e..7456198 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -104,14 +104,14 @@ const struct clk_ops ti_clk_mux_ops = { .determine_rate = __clk_mux_determine_rate, }; -static struct clk *_register_mux(struct device *dev, const char *name, +static struct clk_core *_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the mux */ @@ -152,7 +152,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, */ static void of_mux_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; void __iomem *reg; int num_parents; const char **parent_names; diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c index e7bd62c..dabb8e6 100644 --- a/drivers/clk/ux500/abx500-clk.c +++ b/drivers/clk/ux500/abx500-clk.c @@ -23,7 +23,7 @@ static int ab8500_reg_clks(struct device *dev) { int ret; - struct clk *clk; + struct clk_core *clk; const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"}; u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1}; diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c index bd4769a..7eb055f 100644 --- a/drivers/clk/ux500/clk-prcc.c +++ b/drivers/clk/ux500/clk-prcc.c @@ -92,7 +92,7 @@ static struct clk_ops clk_prcc_kclk_ops = { .is_enabled = clk_prcc_is_enabled, }; -static struct clk *clk_reg_prcc(const char *name, +static struct clk_core *clk_reg_prcc(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -101,7 +101,7 @@ static struct clk *clk_reg_prcc(const char *name, { struct clk_prcc *clk; struct clk_init_data clk_prcc_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcc: %s invalid arguments passed\n", __func__); @@ -142,7 +142,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -152,7 +152,7 @@ struct clk *clk_reg_prcc_pclk(const char *name, &clk_prcc_pclk_ops); } -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index e2d63bc..bac54c9 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -243,7 +243,7 @@ static struct clk_ops clk_prcmu_opp_volt_scalable_ops = { .set_rate = clk_prcmu_set_rate, }; -static struct clk *clk_reg_prcmu(const char *name, +static struct clk_core *clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -252,7 +252,7 @@ static struct clk *clk_reg_prcmu(const char *name, { struct clk_prcmu *clk; struct clk_init_data clk_prcmu_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcmu: %s invalid arguments passed\n", __func__); @@ -292,7 +292,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -302,7 +302,7 @@ struct clk *clk_reg_prcmu_scalable(const char *name, &clk_prcmu_scalable_ops); } -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -311,7 +311,7 @@ struct clk *clk_reg_prcmu_gate(const char *name, &clk_prcmu_gate_ops); } -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -321,7 +321,7 @@ struct clk *clk_reg_prcmu_scalable_rate(const char *name, &clk_prcmu_scalable_rate_ops); } -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -330,7 +330,7 @@ struct clk *clk_reg_prcmu_rate(const char *name, &clk_prcmu_rate_ops); } -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -339,7 +339,7 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name, &clk_prcmu_opp_gate_ops); } -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c index e364c9d..dc6608a 100644 --- a/drivers/clk/ux500/clk-sysctrl.c +++ b/drivers/clk/ux500/clk-sysctrl.c @@ -114,7 +114,7 @@ static struct clk_ops clk_sysctrl_set_parent_ops = { .get_parent = clk_sysctrl_get_parent, }; -static struct clk *clk_reg_sysctrl(struct device *dev, +static struct clk_core *clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, @@ -128,7 +128,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, { struct clk_sysctrl *clk; struct clk_init_data clk_sysctrl_init; - struct clk *clk_reg; + struct clk_core *clk_reg; int i; if (!dev) @@ -176,7 +176,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, return clk_reg; } -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -193,7 +193,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, flags, &clk_sysctrl_gate_ops); } -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -212,7 +212,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, &clk_sysctrl_gate_fixed_rate_ops); } -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h index a2bb92d..da40a2d 100644 --- a/drivers/clk/ux500/clk.h +++ b/drivers/clk/ux500/clk.h @@ -14,52 +14,52 @@ #include <linux/device.h> #include <linux/types.h> -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -68,7 +68,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -78,7 +78,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 80069c3..8a2b4bc 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -19,7 +19,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, { struct prcmu_fw_version *fw_version; const char *sgaclk_parent = NULL; - struct clk *clk; + struct clk_core *clk; /* Clock sources */ clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c index 7b55ef8..afda303 100644 --- a/drivers/clk/ux500/u8500_of_clk.c +++ b/drivers/clk/ux500/u8500_of_clk.c @@ -18,9 +18,9 @@ #define PRCC_NUM_PERIPH_CLUSTERS 6 #define PRCC_PERIPHS_PER_CLUSTER 32 -static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; -static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; -static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcmu_clk[PRCMU_NUM_CLKS]; +static struct clk_core *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; #define PRCC_SHOW(clk, base, bit) \ clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] @@ -29,10 +29,10 @@ static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_C #define PRCC_KCLK_STORE(clk, base, bit) \ prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk -static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, +static struct clk_core *ux500_twocell_get(struct of_phandle_args *clkspec, void *data) { - struct clk **clk_data = data; + struct clk_core **clk_data = data; unsigned int base, bit; if (clkspec->args_count != 2) @@ -61,7 +61,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, struct device_node *np = NULL; struct device_node *child = NULL; const char *sgaclk_parent = NULL; - struct clk *clk, *rtc_clk, *twd_clk; + struct clk_core *clk, *rtc_clk, *twd_clk; if (of_have_populated_dt()) np = of_find_matching_node(NULL, u8500_clk_of_match); diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c index 20c8add..897daf6 100644 --- a/drivers/clk/ux500/u8540_clk.c +++ b/drivers/clk/ux500/u8540_clk.c @@ -17,7 +17,7 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, u32 clkrst5_base, u32 clkrst6_base) { - struct clk *clk; + struct clk_core *clk; /* Clock sources. */ /* Fixed ClockGen */ diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index bc96f10..8df4acc 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -121,13 +121,13 @@ static const struct clk_ops icst_ops = { .set_rate = icst_set_rate, }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, void __iomem *base) { - struct clk *clk; + struct clk_core *clk; struct clk_icst *icst; struct clk_init_data init; struct icst_params *pclone; diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h index 04e6f0a..ede867b 100644 --- a/drivers/clk/versatile/clk-icst.h +++ b/drivers/clk/versatile/clk-icst.h @@ -13,7 +13,7 @@ struct clk_icst_desc { u32 lock_offset; }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c index 1cc1330..6b35629 100644 --- a/drivers/clk/versatile/clk-impd1.c +++ b/drivers/clk/versatile/clk-impd1.c @@ -21,18 +21,18 @@ struct impd1_clk { char *pclkname; - struct clk *pclk; + struct clk_core *pclk; char *vco1name; - struct clk *vco1clk; + struct clk_core *vco1clk; char *vco2name; - struct clk *vco2clk; - struct clk *mmciclk; + struct clk_core *vco2clk; + struct clk_core *mmciclk; char *uartname; - struct clk *uartclk; + struct clk_core *uartclk; char *spiname; - struct clk *spiclk; + struct clk_core *spiclk; char *scname; - struct clk *scclk; + struct clk_core *scclk; struct clk_lookup *clks[15]; }; @@ -87,8 +87,8 @@ static const struct clk_icst_desc impd1_icst2_desc = { void integrator_impd1_clk_init(void __iomem *base, unsigned int id) { struct impd1_clk *imc; - struct clk *clk; - struct clk *pclk; + struct clk_core *clk; + struct clk_core *pclk; int i; if (id > 3) { diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c index c8b5231..4fa61b3 100644 --- a/drivers/clk/versatile/clk-realview.c +++ b/drivers/clk/versatile/clk-realview.c @@ -50,7 +50,7 @@ static const struct clk_icst_desc __initdata realview_osc4_desc = { */ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176) { - struct clk *clk; + struct clk_core *clk; /* APB clock dummy */ clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); diff --git a/drivers/clk/versatile/clk-sp810.c b/drivers/clk/versatile/clk-sp810.c index c6e86a9..9256d25 100644 --- a/drivers/clk/versatile/clk-sp810.c +++ b/drivers/clk/versatile/clk-sp810.c @@ -25,7 +25,7 @@ struct clk_sp810; struct clk_sp810_timerclken { struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_sp810 *sp810; int channel; }; @@ -36,8 +36,8 @@ struct clk_sp810 { void __iomem *base; spinlock_t lock; struct clk_sp810_timerclken timerclken[4]; - struct clk *refclk; - struct clk *timclk; + struct clk_core *refclk; + struct clk_core *timclk; }; static u8 clk_sp810_timerclken_get_parent(struct clk_hw *hw) @@ -79,29 +79,31 @@ static int clk_sp810_timerclken_prepare(struct clk_hw *hw) { struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - struct clk *old_parent = __clk_get_parent(hw->clk); - struct clk *new_parent; + struct clk_core *old_parent = __clk_get_parent(hw->clk); + struct clk_core *new_parent; if (!sp810->refclk) - sp810->refclk = of_clk_get(sp810->node, sp810->refclk_index); + sp810->refclk = of_clk_provider_get(sp810->node, + sp810->refclk_index); if (!sp810->timclk) - sp810->timclk = of_clk_get(sp810->node, sp810->timclk_index); + sp810->timclk = of_clk_provider_get(sp810->node, + sp810->timclk_index); if (WARN_ON(IS_ERR(sp810->refclk) || IS_ERR(sp810->timclk))) return -ENOENT; /* Select fastest parent */ - if (clk_get_rate(sp810->refclk) > clk_get_rate(sp810->timclk)) + if (clk_provider_get_rate(sp810->refclk) > clk_provider_get_rate(sp810->timclk)) new_parent = sp810->refclk; else new_parent = sp810->timclk; /* Switch the parent if necessary */ if (old_parent != new_parent) { - clk_prepare(new_parent); - clk_set_parent(hw->clk, new_parent); - clk_unprepare(old_parent); + clk_provider_prepare(new_parent); + clk_provider_set_parent(hw->clk, new_parent); + clk_provider_unprepare(old_parent); } return 0; @@ -112,8 +114,8 @@ static void clk_sp810_timerclken_unprepare(struct clk_hw *hw) struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - clk_put(sp810->timclk); - clk_put(sp810->refclk); + __clk_put(sp810->timclk); + __clk_put(sp810->refclk); } static const struct clk_ops clk_sp810_timerclken_ops = { @@ -123,7 +125,7 @@ static const struct clk_ops clk_sp810_timerclken_ops = { .set_parent = clk_sp810_timerclken_set_parent, }; -static struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, +static struct clk_core *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, void *data) { struct clk_sp810 *sp810 = data; diff --git a/drivers/clk/versatile/clk-versatile.c b/drivers/clk/versatile/clk-versatile.c index a76981e..08ce5af 100644 --- a/drivers/clk/versatile/clk-versatile.c +++ b/drivers/clk/versatile/clk-versatile.c @@ -60,7 +60,7 @@ static const struct clk_icst_desc versatile_auxosc_desc __initconst = { static void __init cm_osc_setup(struct device_node *np, const struct clk_icst_desc *desc) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c index 529a59c..c9e175f 100644 --- a/drivers/clk/versatile/clk-vexpress-osc.c +++ b/drivers/clk/versatile/clk-vexpress-osc.c @@ -73,7 +73,7 @@ static int vexpress_osc_probe(struct platform_device *pdev) struct clk_lookup *cl = pdev->dev.platform_data; /* Non-DT lookup */ struct clk_init_data init; struct vexpress_osc *osc; - struct clk *clk; + struct clk_core *clk; u32 range[2]; osc = devm_kzalloc(&pdev->dev, sizeof(*osc), GFP_KERNEL); diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c index 2d5e1b4..e77f3d5 100644 --- a/drivers/clk/versatile/clk-vexpress.c +++ b/drivers/clk/versatile/clk-vexpress.c @@ -17,7 +17,7 @@ #include <linux/err.h> #include <linux/vexpress.h> -static struct clk *vexpress_sp810_timerclken[4]; +static struct clk_core *vexpress_sp810_timerclken[4]; static DEFINE_SPINLOCK(vexpress_sp810_lock); static void __init vexpress_sp810_init(void __iomem *base) @@ -54,7 +54,7 @@ static const char * const vexpress_clk_24mhz_periphs[] __initconst = { void __init vexpress_clk_init(void __iomem *sp810_base) { - struct clk *clk; + struct clk_core *clk; int i; clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, @@ -77,7 +77,7 @@ void __init vexpress_clk_init(void __iomem *sp810_base) vexpress_sp810_init(sp810_base); for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++) - WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk)); + WARN_ON(clk_provider_set_parent(vexpress_sp810_timerclken[i], clk)); WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0], "v2m-timer0", "sp804")); diff --git a/drivers/clk/x86/clk-lpt.c b/drivers/clk/x86/clk-lpt.c index 812f83f..1b4a5e1 100644 --- a/drivers/clk/x86/clk-lpt.c +++ b/drivers/clk/x86/clk-lpt.c @@ -21,7 +21,7 @@ static int lpt_clk_probe(struct platform_device *pdev) { struct lpss_clk_data *drvdata; - struct clk *clk; + struct clk_core *clk; drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 246cf12..0efdd9a 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -67,8 +67,8 @@ enum zynq_clk { i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; -static struct clk *ps_clk; -static struct clk *clks[clk_max]; +static struct clk_core *ps_clk; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(armpll_lock); @@ -108,7 +108,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, const char **parents, int enable) { - struct clk *clk; + struct clk_core *clk; u32 enable_reg; char *mux_name; char *div0_name; @@ -154,7 +154,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); enable_reg = clk_readl(fclk_gate_reg) & 1; if (enable && !enable_reg) { - if (clk_prepare_enable(clks[fclk])) + if (clk_provider_prepare_enable(clks[fclk])) pr_warn("%s: FCLK%u enable failed\n", __func__, fclk - fclk0); } @@ -181,7 +181,7 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, const char *clk_name1, void __iomem *clk_ctrl, const char **parents, unsigned int two_gates) { - struct clk *clk; + struct clk_core *clk; char *mux_name; char *div_name; spinlock_t *lock; @@ -222,7 +222,7 @@ static void __init zynq_clk_setup(struct device_node *np) int i; u32 tmp; int ret; - struct clk *clk; + struct clk_core *clk; char *clk_name; unsigned int fclk_enable = 0; const char *clk_output_name[clk_max]; @@ -333,13 +333,13 @@ static void __init zynq_clk_setup(struct device_node *np) CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr2x]); + clk_provider_prepare_enable(clks[ddr2x]); clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr3x]); + clk_provider_prepare_enable(clks[ddr3x]); clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | @@ -351,7 +351,7 @@ static void __init zynq_clk_setup(struct device_node *np) clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, &dciclk_lock); - clk_prepare_enable(clks[dci]); + clk_provider_prepare_enable(clks[dci]); /* Peripheral clocks */ for (i = fclk0; i <= fclk3; i++) { @@ -505,10 +505,10 @@ static void __init zynq_clk_setup(struct device_node *np) /* leave debug clocks in the state the bootloader set them up to */ tmp = clk_readl(SLCR_DBG_CLK_CTRL); if (tmp & DBG_CLK_CTRL_CLKACT_TRC) - if (clk_prepare_enable(clks[dbg_trc])) + if (clk_provider_prepare_enable(clks[dbg_trc])) pr_warn("%s: trace clk enable failed\n", __func__); if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) - if (clk_prepare_enable(clks[dbg_apb])) + if (clk_provider_prepare_enable(clks[dbg_apb])) pr_warn("%s: debug APB clk enable failed\n", __func__); /* One gated clock for all APER clocks. */ diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c index cec9759..5176f65 100644 --- a/drivers/clk/zynq/pll.c +++ b/drivers/clk/zynq/pll.c @@ -193,12 +193,12 @@ static const struct clk_ops zynq_pll_ops = { * @lock Register lock * Returns handle to the registered clock. */ -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock) { struct zynq_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 reg; const char *parent_arr[1] = {parent}; unsigned long flags = 0; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c index 902d768..9616f7d 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c @@ -24,7 +24,7 @@ struct hdmi_phy_8960 { struct hdmi_phy base; struct hdmi *hdmi; struct clk_hw pll_hw; - struct clk *pll; + struct clk_core *pll; unsigned long pixclk; }; #define to_hdmi_phy_8960(x) container_of(x, struct hdmi_phy_8960, base) diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index 2620c48..c2461af 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -215,7 +215,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) { - ret = clk_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); + ret = clk_provider_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); if (ret < 0) return ret; } @@ -225,7 +225,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, return 0; if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret; } @@ -254,7 +254,7 @@ static int __fimc_pipeline_close(struct exynos_media_pipeline *ep) /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret == -ENXIO ? 0 : ret; } @@ -954,7 +954,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) while (--i >= 0) { if (IS_ERR(fmd->camclk[i].clock)) continue; - clk_put(fmd->camclk[i].clock); + __clk_put(fmd->camclk[i].clock); fmd->camclk[i].clock = ERR_PTR(-EINVAL); } @@ -962,7 +962,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_WBCLKS; i++) { if (IS_ERR(fmd->wbclk[i])) continue; - clk_put(fmd->wbclk[i]); + __clk_put(fmd->wbclk[i]); fmd->wbclk[i] = ERR_PTR(-EINVAL); } } @@ -971,7 +971,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) { struct device *dev = &fmd->pdev->dev; char clk_name[32]; - struct clk *clock; + struct clk_core *clock; int i, ret = 0; for (i = 0; i < FIMC_MAX_CAMCLKS; i++) @@ -979,7 +979,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_CAMCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { dev_err(dev, "Failed to get clock: %s\n", clk_name); @@ -1001,7 +1001,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = CLK_IDX_WB_B; i < FIMC_MAX_WBCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "pxl_async%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { v4l2_err(&fmd->v4l2_dev, "Failed to get clock: %s\n", clk_name); diff --git a/drivers/media/platform/exynos4-is/media-dev.h b/drivers/media/platform/exynos4-is/media-dev.h index 0321454..79e4b42 100644 --- a/drivers/media/platform/exynos4-is/media-dev.h +++ b/drivers/media/platform/exynos4-is/media-dev.h @@ -72,7 +72,7 @@ struct fimc_csis_info { }; struct fimc_camclk_info { - struct clk *clock; + struct clk_core *clock; int use_count; unsigned long frequency; }; @@ -124,7 +124,7 @@ struct fimc_md { struct fimc_sensor_info sensor[FIMC_MAX_SENSORS]; int num_sensors; struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS]; - struct clk *wbclk[FIMC_MAX_WBCLKS]; + struct clk_core *wbclk[FIMC_MAX_WBCLKS]; struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS]; struct fimc_dev *fimc[FIMC_MAX_DEVS]; struct fimc_is *fimc_is; @@ -141,7 +141,7 @@ struct fimc_md { } pinctl; struct cam_clk_provider { - struct clk *clks[FIMC_MAX_CAMCLKS]; + struct clk_core *clks[FIMC_MAX_CAMCLKS]; struct clk_onecell_data clk_data; struct device_node *of_node; struct cam_clk camclk[FIMC_MAX_CAMCLKS]; diff --git a/drivers/staging/imx-drm/imx-tve.c b/drivers/staging/imx-drm/imx-tve.c index c628fcd..bf3caad 100644 --- a/drivers/staging/imx-drm/imx-tve.c +++ b/drivers/staging/imx-drm/imx-tve.c @@ -121,10 +121,10 @@ struct imx_tve { struct regmap *regmap; struct regulator *dac_reg; struct i2c_adapter *ddc; - struct clk *clk; - struct clk *di_sel_clk; + struct clk_core *clk; + struct clk_core *di_sel_clk; struct clk_hw clk_hw_di; - struct clk *di_clk; + struct clk_core *di_clk; int vsync_pin; int hsync_pin; }; @@ -149,7 +149,7 @@ static void tve_enable(struct imx_tve *tve) if (!tve->enabled) { tve->enabled = true; - clk_prepare_enable(tve->clk); + clk_provider_prepare_enable(tve->clk); ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_IPU_CLK_EN | TVE_EN, TVE_IPU_CLK_EN | TVE_EN); @@ -176,7 +176,7 @@ static void tve_disable(struct imx_tve *tve) tve->enabled = false; ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_IPU_CLK_EN | TVE_EN, 0); - clk_disable_unprepare(tve->clk); + clk_provider_disable_unprepare(tve->clk); } } @@ -251,12 +251,12 @@ static int imx_tve_connector_mode_valid(struct drm_connector *connector, unsigned long rate; /* pixel clock with 2x oversampling */ - rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; + rate = clk_provider_round_rate(tve->clk, 2000UL * mode->clock) / 2000; if (rate == mode->clock) return MODE_OK; /* pixel clock without oversampling */ - rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; + rate = clk_provider_round_rate(tve->clk, 1000UL * mode->clock) / 1000; if (rate == mode->clock) return MODE_OK; @@ -325,13 +325,13 @@ static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, * and enable 4x oversampling for lower resolutions */ rate = 2000UL * mode->clock; - clk_set_rate(tve->clk, rate); - rounded_rate = clk_get_rate(tve->clk); + clk_provider_set_rate(tve->clk, rate); + rounded_rate = clk_provider_get_rate(tve->clk); if (rounded_rate >= rate) div = 2; - clk_set_rate(tve->di_clk, rounded_rate / div); + clk_provider_set_rate(tve->di_clk, rounded_rate / div); - ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); + ret = clk_provider_set_parent(tve->di_sel_clk, tve->di_clk); if (ret < 0) { dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", ret); @@ -643,7 +643,7 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data) return ret; } - tve->clk = devm_clk_get(dev, "tve"); + tve->clk = devm_clk_provider_get(dev, "tve"); if (IS_ERR(tve->clk)) { dev_err(dev, "failed to get high speed tve clock: %ld\n", PTR_ERR(tve->clk)); @@ -651,7 +651,7 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data) } /* this is the IPU DI clock input selector, can be parented to tve_di */ - tve->di_sel_clk = devm_clk_get(dev, "di_sel"); + tve->di_sel_clk = devm_clk_provider_get(dev, "di_sel"); if (IS_ERR(tve->di_sel_clk)) { dev_err(dev, "failed to get ipu di mux clock: %ld\n", PTR_ERR(tve->di_sel_clk)); diff --git a/include/asm-generic/clkdev.h b/include/asm-generic/clkdev.h index 90a32a6..16d43d9 100644 --- a/include/asm-generic/clkdev.h +++ b/include/asm-generic/clkdev.h @@ -17,8 +17,8 @@ struct clk; -static inline int __clk_get(struct clk *clk) { return 1; } -static inline void __clk_put(struct clk *clk) { } +static inline int __clk_get(struct clk_core *clk) { return 1; } +static inline void __clk_put(struct clk_core *clk) { } static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) { diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index e8d8a35..6b9e6b4 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -22,8 +22,8 @@ * @mult_div1_reg: register containing the DPLL M and N bitfields * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input + * @clk_bypass: struct clk_core pointer to the clock's bypass clock input + * @clk_ref: struct clk_core pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() @@ -68,8 +68,8 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; + struct clk_core *clk_bypass; + struct clk_core *clk_ref; void __iomem *control_reg; u32 enable_mask; unsigned long last_rounded_rate; @@ -251,7 +251,7 @@ extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) -void omap2_init_clk_hw_omap_clocks(struct clk *clk); +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h index a990a59..6c35291 100644 --- a/include/linux/clk/zynq.h +++ b/include/linux/clk/zynq.h @@ -25,7 +25,7 @@ void zynq_clock_init(void); -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock); #endif diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index a947ab8..4b34c69 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -107,8 +107,8 @@ struct si5351_clkout_config { * @clkout: array of clkout configuration */ struct si5351_platform_data { - struct clk *clk_xtal; - struct clk *clk_clkin; + struct clk_core *clk_xtal; + struct clk_core *clk_clkin; enum si5351_pll_src pll_src[2]; struct si5351_clkout_config clkout[8]; }; -- 1.9.3

1 0

[alsa-devel] [PATCH 0/6] HD-audio cleanup patches
by Takashi Iwai 18 Aug '14

18 Aug '14

Hi, below is a series of cleanup patches for HD-audio, targeted for 3.18. Most of them are pretty trivial, just removing the unnecessary codes or replacing with the helper functions. Some resulted in relatively large rewrites with tables, and LOC slightly grows, but the actual code size is reduced by that. [PATCH 1/6] ALSA: hda - Remove obsoleted snd_hda_check_board_config() [PATCH 2/6] ALSA: hda - Remove obsoleted EXPORT_SYMBOL_HDA() macro [PATCH 3/6] ALSA: hda/realtek - Optimize alc888_coef_init() [PATCH 4/6] ALSA: hda/realtek - Use alc_write_coef_idx() in [PATCH 5/6] ALSA: hda/realtek - Add alc_update_coef*_idx() helper [PATCH 6/6] ALSA: hda/realtek - Use tables for batch COEF Takashi

1 6

[alsa-devel] [PATCH] ASoC: fsl-asrc: Convert to use regmap framework's endianness method.
by Xiubo Li 18 Aug '14

18 Aug '14

Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> --- This is depended on the following regmap framework patches, which have just been merged into linux-next tree: https://lkml.org/lkml/2014/7/15/6 https://lkml.org/lkml/2014/7/15/5 https://lkml.org/lkml/2014/7/15/7 Documentation/devicetree/bindings/sound/fsl,asrc.txt | 10 +++++++--- sound/soc/fsl/fsl_asrc.c | 6 +----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index b93362a..791f372 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -26,9 +26,12 @@ Required properties: "ipg" Peripheral clock to driver module. "asrck_<0-f>" Clock sources for input and output clock. - - big-endian : If this property is absent, the little endian mode - will be in use as default. Otherwise, the big endian - mode will be in use for all the device registers. + - big-endian : If this property is absent, the native endian mode + (same with CPU) will be in use as default. Otherwise, + the big endian mode will be in use for all the device + registers. + See Documentation/devicetree/bindings/regmap/regmap.txt + for more detail. - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. @@ -56,5 +59,6 @@ asrc: asrc@02034000 { "txa", "txb", "txc"; fsl,asrc-rate = <48000>; fsl,asrc-width = <16>; + big-endian; status = "okay"; }; diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c index 8221104..3b14531 100644 --- a/sound/soc/fsl/fsl_asrc.c +++ b/sound/soc/fsl/fsl_asrc.c @@ -684,7 +684,7 @@ static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) } } -static struct regmap_config fsl_asrc_regmap_config = { +static const struct regmap_config fsl_asrc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -802,10 +802,6 @@ static int fsl_asrc_probe(struct platform_device *pdev) asrc_priv->paddr = res->start; - /* Register regmap and let it prepare core clock */ - if (of_property_read_bool(np, "big-endian")) - fsl_asrc_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG; - asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, &fsl_asrc_regmap_config); if (IS_ERR(asrc_priv->regmap)) { -- 1.8.5

4 5

Re: [alsa-devel] [v4 05/12] ASoC: Intel: mrfld: add bytes control for modules
by Mark Brown 18 Aug '14

18 Aug '14

On Mon, Aug 18, 2014 at 03:45:15PM +0530, Subhransu S. Prusty wrote: > On Mon, Aug 18, 2014 at 11:06:09AM +0530, Subhransu S. Prusty wrote: > > > I wouldn't expect an info call to be allocating anything - why is it > > > doing that? It's not looking at the alocated data except to see if the > > > allocation succeeded. What happens if someone manages to do a get or > > > set without having first done an info and why aren't we doing any > > > allocation on initialisation? > > Will move after control initialization. > As I have to initialize the params, and if it's done in probe after > control creation, it's required to iterate over the controls list and > match certain pattern to find the control and then initialize. This doesn't > look elegant. Instead I would prefer adding an init callback in the control > to do this operation. What do you recommend? Something like that sounds reasonable, or doing it when writing to the control - the point is that info() is a terrible place to do this for the reasons outline above.

1 0

Re: [alsa-devel] [v4 05/12] ASoC: Intel: mrfld: add bytes control for modules
by Mark Brown 18 Aug '14

18 Aug '14

On Mon, Aug 18, 2014 at 11:06:09AM +0530, Subhransu S. Prusty wrote: > On Wed, Aug 13, 2014 at 09:00:12PM +0100, Mark Brown wrote: > > > + default: > > > + pr_err("Invalid Input- algo type:%d\n", bc->type); > > dev_err(). > We are using pr_err() in all the error conditions for our driver. If it is > really required to change, we can submit a single patch to change to > dev_err() once the patches are merged. Better yet, submit the fix first. It's definitely better practice not to use pr_ when you have a device.

1 0

[alsa-devel] [PATCH] ASoC: core: fix .info for SND_SOC_BYTES_TLV
by Vinod Koul 18 Aug '14

18 Aug '14

From: Subhransu S. Prusty <subhransu.s.prusty(a)intel.com> Commit 7523a271 - "ASoC: core: add a helper for extended byte controls using TLV" introduced support for TLV byte controls but had a typo for the info function, so fix the same Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty(a)intel.com> Signed-off-by: Vinod Koul <vinod.koul(a)intel.com> --- include/sound/soc.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/sound/soc.h b/include/sound/soc.h index be6ecae..c83a334 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -277,7 +277,7 @@ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE | \ SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ .tlv.c = (snd_soc_bytes_tlv_callback), \ - .info = snd_soc_info_bytes_ext, \ + .info = snd_soc_bytes_info_ext, \ .private_value = (unsigned long)&(struct soc_bytes_ext) \ {.max = xcount, .get = xhandler_get, .put = xhandler_put, } } #define SOC_SINGLE_XR_SX(xname, xregbase, xregcount, xnbits, \ -- 1.7.0.4

2 1

[alsa-devel] [PATCH v3 0/2] mfd: arizona: add support for INn_MODE register control using platform data
by Inha Song 18 Aug '14

18 Aug '14

This patch series add support for INn_MODE register control using platform data. Each input signal path can be configurated either as a Analogue or Digital using the INn_MODE registers. Changes for v3 - Change to use of_property_read_u32_array - Fix a few typos - Update commit message Changes for v2 - Change to support - Update commit message - Update document content for more clarity Inha Song (2): mfd: arizona: Add support for INn_Mode register control mfd: arizona: Update DT binding to support INn_MODE init_data Documentation/devicetree/bindings/mfd/arizona.txt | 8 ++++++++ drivers/mfd/arizona-core.c | 8 +++++++- 2 files changed, 15 insertions(+), 1 deletion(-) -- 2.0.0.390.gcb682f8

1 0

Re: [alsa-devel] [v4 05/12] ASoC: Intel: mrfld: add bytes control for modules
by Subhransu S. Prusty 18 Aug '14

18 Aug '14

On Mon, Aug 18, 2014 at 11:06:09AM +0530, Subhransu S. Prusty wrote: > On Wed, Aug 13, 2014 at 09:00:12PM +0100, Mark Brown wrote: > > On Mon, Aug 04, 2014 at 03:15:56PM +0530, Subhransu S. Prusty wrote: > > > > > From: Vinod Koul <vinod.koul(a)intel.com> > > > > > +static int sst_algo_bytes_ctl_info(struct snd_kcontrol *kcontrol, > > > + struct snd_ctl_elem_info *uinfo) > > > +{ > > > + struct sst_algo_control *bc = (void *)kcontrol->private_value; > > > + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); > > > + > > > + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; > > > + uinfo->count = bc->max; > > > + > > > + /* allocate space to cache the algo parameters in the driver */ > > > + if (bc->params == NULL) { > > > + bc->params = devm_kzalloc(component->dev, bc->max, GFP_KERNEL); > > > + if (bc->params == NULL) > > > + return -ENOMEM; > > > + } > > > + return 0; > > > +} > > > > I wouldn't expect an info call to be allocating anything - why is it > > doing that? It's not looking at the alocated data except to see if the > > allocation succeeded. What happens if someone manages to do a get or > > set without having first done an info and why aren't we doing any > > allocation on initialisation? > > Will move after control initialization. As I have to initialize the params, and if it's done in probe after control creation, it's required to iterate over the controls list and match certain pattern to find the control and then initialize. This doesn't look elegant. Instead I would prefer adding an init callback in the control to do this operation. What do you recommend? --

1 0

[alsa-devel] [PATCH] ALSA: hda - restore the gpio led after resume
by Hui Wang 18 Aug '14

18 Aug '14

On some HP laptops, the mute led is controlled by codec gpio. When some machine resume from s3/s4, the codec gpio data will be cleared to 0 by BIOS: Before suspend: IO[3]: enable=1, dir=1, wake=0, sticky=0, data=1, unsol=0 After resume: IO[3]: enable=1, dir=1, wake=0, sticky=0, data=0, unsol=0 To skip the AFG node to enter S3 can't fix this problem. A workaround is to restore the gpio data when the system resume back from s3/s4. It is safe even on the machines without this problem. BugLink: https://bugs.launchpad.net/bugs/1358116 Tested-by: Franz Hsieh <franz.hsieh(a)canonical.com> Cc: stable(a)vger.kernel.org Signed-off-by: Hui Wang <hui.wang(a)canonical.com> --- sound/pci/hda/patch_realtek.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index b32ce08..9c49bf5 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -3432,6 +3432,12 @@ static unsigned int led_power_filter(struct hda_codec *codec, (nid != spec->mute_led_nid && nid != spec->cap_mute_led_nid)) return power_state; + if (nid == codec->afg && power_state == AC_PWRST_D0 && spec->gpio_led) { + snd_hda_codec_write(codec, codec->afg, 0, AC_VERB_SET_GPIO_DATA, + spec->gpio_led); + return power_state; + } + /* Set pin ctl again, it might have just been set to 0 */ snd_hda_set_pin_ctl(codec, nid, snd_hda_codec_get_pin_target(codec, nid)); -- 1.9.1

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[alsa-devel] [PATCH 0/4] Convert to use regmap framework's endianness method.
by Xiubo Li 18 Aug '14

18 Aug '14

Xiubo Li (4): ASoC: fsl-spdif: Convert to use regmap framework's endianness method. ASoC: fsl-esai: Convert to use regmap framework's endianness method. ASoC: fsl-sai: Convert to use regmap framework's endianness method. ASoC: fsl-sai: rename big_endian_data to is_msb_first. Documentation/devicetree/bindings/sound/fsl-sai.txt | 16 ++++++++-------- sound/soc/fsl/fsl_esai.c | 3 --- sound/soc/fsl/fsl_sai.c | 10 +++------- sound/soc/fsl/fsl_sai.h | 3 +-- sound/soc/fsl/fsl_spdif.c | 3 --- 5 files changed, 12 insertions(+), 23 deletions(-) -- 1.8.5

1 4

[alsa-devel] [v4 00/12] Add mrfld DSP topology and widgets
by Subhransu S. Prusty 18 Aug '14

18 Aug '14

This patch series adds DPCM and DAPM widgets to handle DSP topology in the SST platform driver for merrifield. Changes in v4: Removed print messages for kzalloc failure as per review comments from Takashi. Subhransu S. Prusty (2): ASoC: Intel: mrfld: set private data for cpu-dai ASoC: Export dapm_kcontrol_get_value Vinod Koul (10): ASoC: Intel: mfld-pcm: add FE and BE ops ASoC: intel: mfld-pcm: don't call trigger ops to DSP for internal streams ASoC: Intel: add mrfld DSP defines ASoC: Intel: mrfld: add bytes control for modules ASoC: Intel: mrfld: add the gain controls ASoC: Intel: mfld-pcm: add control for powering up/down dsp ASoC: Intel: mrfld: add DSP core controls ASoC: Intel: mrfld: add the DSP DAPM widgets ASoC: Intel: mfld-pcm: add the fe & be dai ops ASoC: Intel: mrfld: add the DSP mixers include/sound/soc-dapm.h | 1 + sound/soc/intel/Makefile | 3 +- sound/soc/intel/sst-atom-controls.c | 1256 +++++++++++++++++++++++++++++++ sound/soc/intel/sst-atom-controls.h | 844 ++++++++++++++++++++- sound/soc/intel/sst-mfld-platform-pcm.c | 192 ++++- sound/soc/intel/sst-mfld-platform.h | 8 + sound/soc/soc-dapm.c | 3 +- 7 files changed, 2269 insertions(+), 38 deletions(-) create mode 100644 sound/soc/intel/sst-atom-controls.c -- 1.9.0

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Re: [alsa-devel] [v4 10/12] ASoC: Intel: mrfld: add the DSP DAPM widgets
by Mark Brown 18 Aug '14

18 Aug '14

On Thu, Aug 14, 2014 at 03:51:56PM +0530, Subhransu S. Prusty wrote: > On Wed, Aug 13, 2014 at 09:14:54PM +0100, Mark Brown wrote: > > On Mon, Aug 04, 2014 at 03:16:01PM +0530, Subhransu S. Prusty wrote: > > > + pr_debug("%s: widget = %s\n", __func__, w->name); > > > + for (i = 0; i < w->num_kcontrols; i++) { > > > + if (dapm_kcontrol_get_value(w->kcontrols[i])) { > > > + mc = (struct soc_mixer_control *)(w->kcontrols[i])->private_value; > > > + val |= 1 << mc->shift; > > > + } > > > + } > > All my concerns about this still stand - using something called > > _get_value() to do something other than read the control value (which > > this does - it uses it as a boolean then does something else to read the > > value) which doesn't seem good. > I think this can be optimized. This need a bit of rework in the code, but > need to check. But this would need an assumption that the controls are > created in order. > for (i = 0; i < w->num_kcontrols; i++) { > if (dapm_kcontrol_get_value(w->kcontrols[i])) { > val |= 1 << i; > } > Is this ok? No, that doesn't seem safe. Why not read the data from the control - if we were calling a function which returned the value that'd be much clearer.

2 1

Re: [alsa-devel] [PATCH] ASoC: Intel: Add merrifield machine driver
by Mark Brown 18 Aug '14

18 Aug '14

On Sun, Aug 17, 2014 at 07:50:28PM +0530, Subhransu S. Prusty wrote: > On Tue, Aug 12, 2014 at 10:48:22PM +0100, Mark Brown wrote: > > Look at what wm8994_vmid_mode() does... > If I understand correctly need to move this enabling/disabling of VMID > to wm8994_vmid_mode(). No, it's exactly what wm8994_vmid_mode() is there to do already - putting the device into WM8994_VMID_FORCE forces VMID on.

2 1

[alsa-devel] [PATCH 0/6] Fix `sparse` warnings
by Lars-Peter Clausen 17 Aug '14

17 Aug '14

This patch series contains a set of fixes for warnings generated by the sparse tool when building the ASoC tree. None of them are critical and the generated code before and after the patch is the same in all cases. The reason for still fixing them is that it makes it easier to recognize new and potentially serious warnings/errors. With this series applied at least on x86 and ARM a allyesconfig on the ASoC tree builds almost without errors or warnings from sparse. The only remaining warnings are the following two: sound/soc/soc-core.c:108:25: warning: Variable length array is used. sound/soc/soc-core.c:109:29: warning: Variable length array is used. These are part of the legacy ASoC IO code that is deprecated and schedulded for removal in the near future so there is not too much motivation for fixing them. - Lars Lars-Peter Clausen (6): ASoC: edma-pcm: Include edma-pcm.h ASoC: odrodix2_max98090: Make non exported symbols static ASoC: rcar: Use && instead of & for boolean expressions ASoC: sh: Fix dma direction type ASoC: samsung idma: Add proper annotation for casting iomem pointers ASoC: ab8500-codec: Drop bank prefix from AB8500_GPIO_DIR4_REG register define sound/soc/codecs/ab8500-codec.c | 11 +++++------ sound/soc/davinci/edma-pcm.c | 2 ++ sound/soc/samsung/idma.c | 4 ++-- sound/soc/samsung/odroidx2_max98090.c | 4 ++-- sound/soc/sh/fsi.c | 7 ++++++- sound/soc/sh/rcar/gen.c | 2 +- 6 files changed, 18 insertions(+), 12 deletions(-) -- 1.8.0

2 12

Re: [alsa-devel] [PATCH] ASoC: Intel: Add merrifield machine driver
by Mark Brown 17 Aug '14

17 Aug '14

On Tue, Aug 12, 2014 at 11:36:09AM +0530, Subhransu S. Prusty wrote: > On Tue, Jul 29, 2014 at 08:50:43PM +0100, Mark Brown wrote: > > On Thu, Jul 17, 2014 at 05:43:45PM +0530, Subhransu S. Prusty wrote: > > > + /* Force enable VMID to avoid cold latency constraints */ > > > + snd_soc_dapm_force_enable_pin(&card->dapm, "VMID"); > > > + snd_soc_dapm_sync(&card->dapm); > > This looks like you're open coding a version of wm8994_vmid_mode(). > > Though that might need some tuning for systems that really have no > > single ended outputs. > VMID has a larget settling time. Keep it ON here to avoid the delay. Any > better way of doing this? Look at what wm8994_vmid_mode() does...

2 1

[alsa-devel] [PATCH] ASoC: dmic: Add to SND_SOC_ALL_CODECS
by Lars-Peter Clausen 17 Aug '14

17 Aug '14

Improve build coverage of the dmic driver. Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> --- sound/soc/codecs/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 8838838e..e514e98 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -56,6 +56,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_DA7213 if I2C select SND_SOC_DA732X if I2C select SND_SOC_DA9055 if I2C + select SND_SOC_DMIC select SND_SOC_BT_SCO select SND_SOC_ISABELLE if I2C select SND_SOC_JZ4740_CODEC -- 1.8.0

2 1

[alsa-devel] [PATCH] ASoC: Use dev_set_name() instead of init_name
by Lars-Peter Clausen 17 Aug '14

17 Aug '14

init_name is basically a hack and should only be used for statically allocated device structs. For dynamically allocated devices dev_set_name() should be used. Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> --- sound/soc/soc-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index d4bfd4a..889f4e3 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -1325,7 +1325,7 @@ static int soc_post_component_init(struct snd_soc_pcm_runtime *rtd, device_initialize(rtd->dev); rtd->dev->parent = rtd->card->dev; rtd->dev->release = rtd_release; - rtd->dev->init_name = name; + dev_set_name(rtd->dev, "%s", name); dev_set_drvdata(rtd->dev, rtd); mutex_init(&rtd->pcm_mutex); INIT_LIST_HEAD(&rtd->dpcm[SNDRV_PCM_STREAM_PLAYBACK].be_clients); -- 1.8.0

2 1

[alsa-devel] the wav jumps on Raspberry, do you think ...
by Carpon frédéric 17 Aug '14

17 Aug '14

Hello, thank for your response and corrections of the topic "minimal_playback.c " from http://equalarea.com/paul/alsa-audio.html There are good tutorials too : http://home.roadrunner.com/~jgglatt/tech/linuxapi.htm http://jan.newmarch.name/LinuxSound/Sampled/Alsa/ On the raspberry, with ArchLinux, the jan.newmarch version and aplay command make the wav jumps for the beginning and sometimes in the middle of the wav music. Do you think it comes from the raspberry’s « bcm2835 ALSA » audio chipset or the arm processor efficiency or other things ? Thank You for your help

1 0

[alsa-devel] [PATCH RESEND v11 0/3] Add ES8328 audio codec
by Sean Cross 17 Aug '14

17 Aug '14

This patchset adds support for the Everest Semi ES8328 audio codec, used in the Novena open source laptop. It also adds support for using the es8328 on IMX boards. We write a machine driver rather than using simple-card because the machine driver needs to support regulators for the speaker amps and as well as supporting headphone jacks, in addition to the i.MX audmux routing. Changes since v10: - Minor documentation reformatting - Minor spacing reformatting in sound/soc/fsl/imx-audio-es8328.c Changes since v9: - Minor formatting corrections - Rework DAPM registers in es8328.h. DAPM widgets use offsets, and the v9 patch turned snd_soc_write() calls into widgets without converting from i2c masks to offsets first. - Rename DAC and ADC PLL to DLL, to reflect latest documentation. Changes since v8: - For the mclk ratios, move from an array to a lookup table, and rename the variable to be clearer. - Move all CHIPPOWER accesses into DAPM supplies. - Fix sloppy compile problems introduced in v8. - Shut down clocks and supplies on suspend, and enable them on resume. - Remove double set of ES8328_MASTERMODE_MSC. Changes since v7: - We now fetch the regulators in the device-level probe rather than in the ASoC-level probe. Changes since v6: - Minor clarification of AUDMUX in imx-audio-es8328.txt - Use u32 instead of int in imx-es8328.c for int-mux and ext-mux - Bounds checking on mux-int-port and mux-ext-port in imx-es8328.c - Remove NULL checks before calling of_node_put() Changes since v5: - Removed empty imx_set_frequency function from imx-es8328.c - Move the clock from imx-audio-es8328 to the es8328 codec itself - Add support for 2x (22.5792 MHz) and 1x (11.2896 MHz) source clocks - Restore registers on resume - Document pins for ES8328, including input pins Changes since v4: - Simplify clock handling and use assigned-clock-parents - Move the codec regulator from the machine driver to the codec - Specify all four regulators, and require their presence - Fix audio recording, such that it enables the PGA Changes since v3: - Add OF bindings for everest,es8328 - Add back in patch to add everest as a vendor prefix - Give clocks more generic names - Document required clocks in DT bindings document Changes since v2: - Change deemph to a bool, and update based on sample rate - Replace value enums with regular enums - Break SPI and I2C drivers into their own modules - Rename everest,es8328 to es8328 as the module wasn't getting detected. Because of this, the patch to vendor-prefixes.txt has been dropped. Changes since v1: - Rename HP/Speaker to OUT1/OUT2 - Use DAPM widgets for startup/shutdown - Add regulator support to machine driver Sean Cross (3): devicetree: bindings: Add Everest Semicodunctor ASoC: add es8328 codec driver ASoC: fsl: add imx-es8328 machine driver Documentation/devicetree/bindings/sound/es8328.txt | 38 ++ .../devicetree/bindings/sound/imx-audio-es8328.txt | 60 ++ .../devicetree/bindings/vendor-prefixes.txt | 1 + sound/soc/codecs/Kconfig | 13 + sound/soc/codecs/Makefile | 6 + sound/soc/codecs/es8328-i2c.c | 60 ++ sound/soc/codecs/es8328-spi.c | 49 ++ sound/soc/codecs/es8328.c | 756 +++++++++++++++++++++ sound/soc/codecs/es8328.h | 314 +++++++++ sound/soc/fsl/Kconfig | 14 + sound/soc/fsl/Makefile | 2 + sound/soc/fsl/imx-es8328.c | 232 +++++++ 12 files changed, 1545 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/es8328.txt create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-es8328.txt create mode 100644 sound/soc/codecs/es8328-i2c.c create mode 100644 sound/soc/codecs/es8328-spi.c create mode 100644 sound/soc/codecs/es8328.c create mode 100644 sound/soc/codecs/es8328.h create mode 100644 sound/soc/fsl/imx-es8328.c -- 2.0.0

2 5

[alsa-devel] [PATCH] ASoC: rt5670: add clock source selection controls
by bardliao＠realtek.com 16 Aug '14

16 Aug '14

From: Bard Liao <bardliao(a)realtek.com> We can select the clock source of some digital widgets in rt5670. This patch adds the controls of those selections. Signed-off-by: Bard Liao <bardliao(a)realtek.com> --- sound/soc/codecs/rt5670.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/sound/soc/codecs/rt5670.c b/sound/soc/codecs/rt5670.c index 879d42e..91987e1 100644 --- a/sound/soc/codecs/rt5670.c +++ b/sound/soc/codecs/rt5670.c @@ -430,6 +430,105 @@ static const SOC_ENUM_SINGLE_DECL(rt5670_if2_dac_enum, RT5670_DIG_INF1_DATA, static const SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_enum, RT5670_DIG_INF1_DATA, RT5670_IF2_ADC_SEL_SFT, rt5670_data_select); +static const char * const rt5670_asrc_clk_source[] = { + "clk_sysy_div_out", "clk_i2s1_track", "clk_i2s2_track", + "clk_i2s3_track", "clk_i2s4_track", "clk_sys2", "clk_sys3", + "clk_sys4", "clk_sys5" +}; + +static const SOC_ENUM_SINGLE_DECL(rt5670_da_sto_asrc_enum, RT5670_ASRC_2, + 12, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_da_monol_asrc_enum, RT5670_ASRC_2, + 8, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_da_monor_asrc_enum, RT5670_ASRC_2, + 4, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_ad_sto1_asrc_enum, RT5670_ASRC_2, + 0, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_up_filter_asrc_enum, RT5670_ASRC_3, + 12, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_down_filter_asrc_enum, RT5670_ASRC_3, + 8, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_ad_monol_asrc_enum, RT5670_ASRC_3, + 4, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_ad_monor_asrc_enum, RT5670_ASRC_3, + 0, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_ad_sto2_asrc_enum, RT5670_ASRC_5, + 12, rt5670_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5670_dsp_asrc_enum, RT5670_DSP_CLK, + 0, rt5670_asrc_clk_source); + +static int rt5670_clk_sel_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + unsigned int u_bit = 0, p_bit = 0; + struct soc_enum *em = + (struct soc_enum *)kcontrol->private_value; + + switch (em->reg) { + case RT5670_ASRC_2: + switch (em->shift_l) { + case 0: + u_bit = 0x8; + p_bit = RT5670_PWR_ADC_S1F; + break; + case 4: + u_bit = 0x100; + p_bit = RT5670_PWR_DAC_MF_R; + break; + case 8: + u_bit = 0x200; + p_bit = RT5670_PWR_DAC_MF_L; + break; + case 12: + u_bit = 0x400; + p_bit = RT5670_PWR_DAC_S1F; + break; + } + break; + case RT5670_ASRC_3: + switch (em->shift_l) { + case 0: + u_bit = 0x1; + p_bit = RT5670_PWR_ADC_MF_R; + break; + case 4: + u_bit = 0x2; + p_bit = RT5670_PWR_ADC_MF_L; + break; + } + break; + case RT5670_ASRC_5: + u_bit = 0x4; + p_bit = RT5670_PWR_ADC_S2F; + break; + } + + if (u_bit || p_bit) { + switch (ucontrol->value.integer.value[0]) { + case 1 ... 4: /*enable*/ + if (snd_soc_read(codec, RT5670_PWR_DIG2) & p_bit) + snd_soc_update_bits(codec, + RT5670_ASRC_1, u_bit, u_bit); + break; + default: /*disable*/ + snd_soc_update_bits(codec, RT5670_ASRC_1, u_bit, 0); + break; + } + } + + return snd_soc_put_enum_double(kcontrol, ucontrol); +} + static const struct snd_kcontrol_new rt5670_snd_controls[] = { /* Headphone Output Volume */ SOC_DOUBLE("HP Playback Switch", RT5670_HP_VOL, @@ -482,6 +581,24 @@ static const struct snd_kcontrol_new rt5670_snd_controls[] = { SOC_ENUM("ADC IF2 Data Switch", rt5670_if2_adc_enum), SOC_ENUM("DAC IF2 Data Switch", rt5670_if2_dac_enum), + + SOC_ENUM_EXT("DA STO Clk Sel", rt5670_da_sto_asrc_enum, + snd_soc_get_enum_double, rt5670_clk_sel_put), + SOC_ENUM_EXT("DA MONOL Clk Sel", rt5670_da_monol_asrc_enum, + snd_soc_get_enum_double, rt5670_clk_sel_put), + SOC_ENUM_EXT("DA MONOR Clk Sel", rt5670_da_monor_asrc_enum, + snd_soc_get_enum_double, rt5670_clk_sel_put), + SOC_ENUM_EXT("AD STO1 Clk Sel", rt5670_ad_sto1_asrc_enum, + snd_soc_get_enum_double, rt5670_clk_sel_put), + SOC_ENUM_EXT("AD MONOL Clk Sel", rt5670_ad_monol_asrc_enum, + snd_soc_get_enum_double, rt5670_clk_sel_put), + SOC_ENUM_EXT("AD MONOR Clk Sel", rt5670_ad_monor_asrc_enum, + snd_soc_get_enum_double, rt5670_clk_sel_put), + SOC_ENUM("UP Clk Sel", rt5670_up_filter_asrc_enum), + SOC_ENUM("DOWN Clk Sel", rt5670_down_filter_asrc_enum), + SOC_ENUM_EXT("AD STO2 Clk Sel", rt5670_ad_sto2_asrc_enum, + snd_soc_get_enum_double, rt5670_clk_sel_put), + SOC_ENUM("DSP Clk Sel", rt5670_dsp_asrc_enum), }; /** -- 1.8.1.1.439.g50a6b54

2 1

[alsa-devel] [PATCH 1/3] ASoC: rt5677: Remove the redundant definition in head file
by Oder Chiou 16 Aug '14

16 Aug '14

The patch removes the redundant definition in head file Signed-off-by: Oder Chiou <oder_chiou(a)realtek.com> --- sound/soc/codecs/rt5677.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index 08252e7..863393e 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1393,13 +1393,6 @@ #define RT5677_DSP_IB_9_L (0x1 << 1) #define RT5677_DSP_IB_9_L_SFT 1 -/* Debug String Length */ -#define RT5677_REG_DISP_LEN 23 - -#define RT5677_NO_JACK BIT(0) -#define RT5677_HEADSET_DET BIT(1) -#define RT5677_HEADPHO_DET BIT(2) - /* System Clock Source */ enum { RT5677_SCLK_S_MCLK, -- 1.8.1.1.439.g50a6b54

2 5

[alsa-devel] [PATCH/RFC] ASoC: Drop const from struct snd_soc_dai_link *of_node members
by Sylwester Nawrocki 16 Aug '14

16 Aug '14

Dropping the const qualifiers prevents "passing argument 1 of ‘of_node_put’ discards ‘const’ qualifier from pointer target type" type warnings when compiling the code dropping reference to cpu_of_node, codec_of_node or platform_of_node with with an of_node_put() function call. This lets us to avoid casting to struct device_node * or caching variables internally in drivers just to be able to properly drop a reference to the OF node on clean up paths. Signed-off-by: Sylwester Nawrocki <s.nawrocki(a)samsung.com> --- include/sound/soc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/sound/soc.h b/include/sound/soc.h index ed9e2d7..a8d4b79 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -881,7 +881,7 @@ struct snd_soc_dai_link { * only for codec to codec links, or systems using device tree. */ const char *cpu_name; - const struct device_node *cpu_of_node; + struct device_node *cpu_of_node; /* * You MAY specify the DAI name of the CPU DAI. If this information is * omitted, the CPU-side DAI is matched using .cpu_name/.cpu_of_node @@ -893,7 +893,7 @@ struct snd_soc_dai_link { * DT/OF node, but not both. */ const char *codec_name; - const struct device_node *codec_of_node; + struct device_node *codec_of_node; /* You MUST specify the DAI name within the codec */ const char *codec_dai_name; /* @@ -902,7 +902,7 @@ struct snd_soc_dai_link { * do not need a platform. */ const char *platform_name; - const struct device_node *platform_of_node; + struct device_node *platform_of_node; int be_id; /* optional ID for machine driver BE identification */ const struct snd_soc_pcm_stream *params; -- 1.7.9.5

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[alsa-devel] [PATCH 1/2 v2] ASoC: Add HA (HEAD acoustics) DSP codec driver template
by Stefan Roese 16 Aug '14

16 Aug '14

This codec driver template represents an I2C controlled multichannel audio codec that has many typical ASoC codec driver features like volume controls, mixer stages, mux selection, output power control, in-codec audio routings, codec bias management and DAI link configuration. This driver is based on an early version provided by Jarkko Nikula. Signed-off-by: Jarkko Nikula <jarkko.nikula(a)bitmer.com> Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Thorsten Eisbein <thorsten.eisbein(a)head-acoustics.de> Cc: Lars-Peter Clausen <lars(a)metafoo.de> Cc: Mark Brown <broonie(a)kernel.org> --- v2: - Added/changed copyright line - Changed authorship (as suggested by Jarkko the original author) - Added Thorsten as maintainer - Remove ha_dsp_hw_params() and ha_dsp_set_dai_fmt() as its not used (only needed for CODEC as clock master which is currently not suported). - Removed some unneeded include files - "const char *const foo" used instead of "const char *foo" - SOC_MIXER_ARRAY() helper macro used - Removed ha_dsp_set_bias_level() and use default implementation - Use codec->dev instead of codec->dev->parent in dev_get_regmap() - Added CODEC reset to probe - Remove "ret" in ha_dsp_i2c_probe() sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/ha-dsp.c | 333 ++++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/ha-dsp.h | 50 +++++++ 4 files changed, 389 insertions(+) create mode 100644 sound/soc/codecs/ha-dsp.c create mode 100644 sound/soc/codecs/ha-dsp.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index f0e8401..f357988 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -51,6 +51,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_DA732X if I2C select SND_SOC_DA9055 if I2C select SND_SOC_BT_SCO + select SND_SOC_HA_DSP if I2C select SND_SOC_ISABELLE if I2C select SND_SOC_JZ4740_CODEC select SND_SOC_LM4857 if I2C @@ -343,6 +344,9 @@ config SND_SOC_BT_SCO config SND_SOC_DMIC tristate +config SND_SOC_HA_DSP + tristate + config SND_SOC_HDMI_CODEC tristate "HDMI stub CODEC" diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 3c4d275..f296bec 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -39,6 +39,7 @@ snd-soc-da732x-objs := da732x.o snd-soc-da9055-objs := da9055.o snd-soc-bt-sco-objs := bt-sco.o snd-soc-dmic-objs := dmic.o +snd-soc-ha-dsp-objs := ha-dsp.o snd-soc-isabelle-objs := isabelle.o snd-soc-jz4740-codec-objs := jz4740.o snd-soc-l3-objs := l3.o @@ -190,6 +191,7 @@ obj-$(CONFIG_SND_SOC_DA732X) += snd-soc-da732x.o obj-$(CONFIG_SND_SOC_DA9055) += snd-soc-da9055.o obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o +obj-$(CONFIG_SND_SOC_HA_DSP) += snd-soc-ha-dsp.o obj-$(CONFIG_SND_SOC_ISABELLE) += snd-soc-isabelle.o obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o diff --git a/sound/soc/codecs/ha-dsp.c b/sound/soc/codecs/ha-dsp.c new file mode 100644 index 0000000..5a3c7ef --- /dev/null +++ b/sound/soc/codecs/ha-dsp.c @@ -0,0 +1,333 @@ +/* + * ha-dsp.c -- HA DSP ALSA SoC Audio driver + * + * Copyright 2011-2014 HEAD acoustics GmbH + * + * Authors: + * Jarkko Nikula <jarkko.nikula(a)bitmer.com> + * Stefan Roese <sr(a)denx.de> + * Thorsten Eisbein <thorsten.eisbein(a)head-acoustics.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * Maintainer: Thorsten Eisbein <thorsten.eisbein(a)head-acoustics.de> + */ + +#include <linux/module.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> + +#include "ha-dsp.h" + +/* Reset default register values for soc-cache */ +static const struct reg_default ha_dsp_reg_defaults[] = { + { 0x00, 0x00 }, + { 0x01, 0x55 }, + { 0x02, 0x55 }, + { 0x03, 0x00 }, + { 0x04, 0x00 }, + { 0x05, 0x00 }, + { 0x06, 0x00 }, + { 0x07, 0x00 }, + { 0x08, 0x02 }, + { 0x09, 0x02 }, + { 0x0a, 0x02 }, + { 0x0b, 0x02 }, + { 0x0c, 0x02 }, + { 0x0d, 0x02 }, + { 0x0e, 0x02 }, + { 0x0f, 0x02 }, +}; + +/* DSP mode selection */ +static const char *const ha_dsp_mode_texts[] = {"Mode 1", "Mode 2"}; +static SOC_ENUM_SINGLE_DECL(ha_dsp_mode_enum, HA_DSP_CTRL, 0, + ha_dsp_mode_texts); + +/* Monitor output mux selection */ +static const char *const ha_dsp_monitor_texts[] = {"Off", "ADC", "DAC"}; +static SOC_ENUM_SINGLE_DECL(ha_dsp_monitor_enum, HA_DSP_CTRL, 1, + ha_dsp_monitor_texts); + +static const struct snd_kcontrol_new ha_dsp_monitor_control = + SOC_DAPM_ENUM("Route", ha_dsp_monitor_enum); + +/* Output mixers */ +static const struct snd_kcontrol_new ha_dsp_out1_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT1_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT1_CTRL, 2, 1, 0), +}; +static const struct snd_kcontrol_new ha_dsp_out2_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT2_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT2_CTRL, 2, 1, 0), +}; +static const struct snd_kcontrol_new ha_dsp_out3_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT3_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT3_CTRL, 2, 1, 0), +}; +static const struct snd_kcontrol_new ha_dsp_out4_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT4_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT4_CTRL, 2, 1, 0), +}; +static const struct snd_kcontrol_new ha_dsp_out5_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT5_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT5_CTRL, 2, 1, 0), +}; +static const struct snd_kcontrol_new ha_dsp_out6_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT6_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT6_CTRL, 2, 1, 0), +}; +static const struct snd_kcontrol_new ha_dsp_out7_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT7_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT1_CTRL, 2, 1, 0), +}; +static const struct snd_kcontrol_new ha_dsp_out8_mixer_controls[] = { + SOC_DAPM_SINGLE("DAC Switch", HA_DSP_OUT8_CTRL, 1, 1, 0), + SOC_DAPM_SINGLE("IN Bypass Switch", HA_DSP_OUT8_CTRL, 2, 1, 0), +}; + +static const struct snd_kcontrol_new ha_dsp_snd_controls[] = { + SOC_SINGLE("ADC Capture Volume", + HA_DSP_ADC_VOL, 0, 0x7f, 0), + SOC_SINGLE("ADC Capture Switch", + HA_DSP_ADC_VOL, 7, 0x01, 1), + + SOC_SINGLE("PCM Playback Volume", + HA_DSP_DAC_VOL, 0, 0x7f, 0), + SOC_SINGLE("PCM Playback Switch", + HA_DSP_DAC_VOL, 7, 0x01, 1), + + SOC_ENUM("DSP Mode", ha_dsp_mode_enum), +}; + +static const struct snd_soc_dapm_widget ha_dsp_widgets[] = { + SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0), + + SOC_MIXER_ARRAY("OUT1 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out1_mixer_controls), + SOC_MIXER_ARRAY("OUT2 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out2_mixer_controls), + SOC_MIXER_ARRAY("OUT3 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out3_mixer_controls), + SOC_MIXER_ARRAY("OUT4 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out4_mixer_controls), + SOC_MIXER_ARRAY("OUT5 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out5_mixer_controls), + SOC_MIXER_ARRAY("OUT6 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out6_mixer_controls), + SOC_MIXER_ARRAY("OUT7 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out7_mixer_controls), + SOC_MIXER_ARRAY("OUT8 Mixer", SND_SOC_NOPM, 0, 0, + ha_dsp_out8_mixer_controls), + + SND_SOC_DAPM_PGA("OUT1 PGA", HA_DSP_OUT1_CTRL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OUT2 PGA", HA_DSP_OUT2_CTRL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OUT3 PGA", HA_DSP_OUT3_CTRL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OUT4 PGA", HA_DSP_OUT4_CTRL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OUT5 PGA", HA_DSP_OUT5_CTRL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OUT6 PGA", HA_DSP_OUT6_CTRL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OUT7 PGA", HA_DSP_OUT7_CTRL, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OUT8 PGA", HA_DSP_OUT8_CTRL, 0, 0, NULL, 0), + + SND_SOC_DAPM_MUX("Monitor Out Mux", SND_SOC_NOPM, 0, 0, + &ha_dsp_monitor_control), + + /* Input pins */ + SND_SOC_DAPM_INPUT("IN1"), + SND_SOC_DAPM_INPUT("IN2"), + SND_SOC_DAPM_INPUT("IN3"), + SND_SOC_DAPM_INPUT("IN4"), + SND_SOC_DAPM_INPUT("IN5"), + SND_SOC_DAPM_INPUT("IN6"), + SND_SOC_DAPM_INPUT("IN7"), + SND_SOC_DAPM_INPUT("IN8"), + + /* Output pins */ + SND_SOC_DAPM_OUTPUT("OUT1"), + SND_SOC_DAPM_OUTPUT("OUT2"), + SND_SOC_DAPM_OUTPUT("OUT3"), + SND_SOC_DAPM_OUTPUT("OUT4"), + SND_SOC_DAPM_OUTPUT("OUT5"), + SND_SOC_DAPM_OUTPUT("OUT6"), + SND_SOC_DAPM_OUTPUT("OUT7"), + SND_SOC_DAPM_OUTPUT("OUT8"), + SND_SOC_DAPM_OUTPUT("MONITOR"), +}; + +static const struct snd_soc_dapm_route ha_dsp_routes[] = { + /* Inputs to ADC */ + {"ADC", NULL, "IN1"}, + {"ADC", NULL, "IN2"}, + {"ADC", NULL, "IN3"}, + {"ADC", NULL, "IN4"}, + {"ADC", NULL, "IN5"}, + {"ADC", NULL, "IN6"}, + {"ADC", NULL, "IN7"}, + {"ADC", NULL, "IN8"}, + + /* DAC and input bypass paths to outputs */ + {"OUT1 Mixer", "DAC Switch", "DAC"}, + {"OUT1 Mixer", "IN Bypass Switch", "IN1"}, + {"OUT1 PGA", NULL, "OUT1 Mixer"}, + {"OUT1", NULL, "OUT1 PGA"}, + + {"OUT2 Mixer", "DAC Switch", "DAC"}, + {"OUT2 Mixer", "IN Bypass Switch", "IN2"}, + {"OUT2 PGA", NULL, "OUT2 Mixer"}, + {"OUT2", NULL, "OUT2 PGA"}, + + {"OUT3 Mixer", "DAC Switch", "DAC"}, + {"OUT3 Mixer", "IN Bypass Switch", "IN3"}, + {"OUT3 PGA", NULL, "OUT3 Mixer"}, + {"OUT3", NULL, "OUT3 PGA"}, + + {"OUT4 Mixer", "DAC Switch", "DAC"}, + {"OUT4 Mixer", "IN Bypass Switch", "IN4"}, + {"OUT4 PGA", NULL, "OUT4 Mixer"}, + {"OUT4", NULL, "OUT4 PGA"}, + + {"OUT5 Mixer", "DAC Switch", "DAC"}, + {"OUT5 Mixer", "IN Bypass Switch", "IN5"}, + {"OUT5 PGA", NULL, "OUT5 Mixer"}, + {"OUT5", NULL, "OUT5 PGA"}, + + {"OUT6 Mixer", "DAC Switch", "DAC"}, + {"OUT6 Mixer", "IN Bypass Switch", "IN6"}, + {"OUT6 PGA", NULL, "OUT6 Mixer"}, + {"OUT6", NULL, "OUT6 PGA"}, + + {"OUT7 Mixer", "DAC Switch", "DAC"}, + {"OUT7 Mixer", "IN Bypass Switch", "IN7"}, + {"OUT7 PGA", NULL, "OUT7 Mixer"}, + {"OUT7", NULL, "OUT7 PGA"}, + + {"OUT8 Mixer", "DAC Switch", "DAC"}, + {"OUT8 Mixer", "IN Bypass Switch", "IN8"}, + {"OUT8 PGA", NULL, "OUT8 Mixer"}, + {"OUT8", NULL, "OUT8 PGA"}, + + /* Monitor output */ + {"Monitor Out Mux", "ADC", "ADC"}, + {"Monitor Out Mux", "DAC", "DAC"}, + {"MONITOR", NULL, "Monitor Out Mux"}, +}; + +static struct snd_soc_dai_driver ha_dsp_dai = { + .name = "ha-dsp-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 16, + .rates = SNDRV_PCM_RATE_8000_96000, + /* We use only 32 Bits for Audio */ + .formats = SNDRV_PCM_FMTBIT_S32_LE, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 16, + .rates = SNDRV_PCM_RATE_8000_96000, + /* We use only 32 Bits for Audio */ + .formats = SNDRV_PCM_FMTBIT_S32_LE, + }, +}; + +static int ha_dsp_probe(struct snd_soc_codec *codec) +{ + int ret; + + codec->control_data = dev_get_regmap(codec->dev, NULL); + ret = snd_soc_codec_set_cache_io(codec, codec->control_data); + if (ret != 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + return ret; + } + + snd_soc_write(codec, HA_DSP_CTRL, HA_DSP_SW_RESET); + + return 0; +} + +static int ha_dsp_remove(struct snd_soc_codec *codec) +{ + snd_soc_write(codec, HA_DSP_CTRL, HA_DSP_SW_RESET); + + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_ha_dsp = { + .probe = ha_dsp_probe, + .remove = ha_dsp_remove, + + .controls = ha_dsp_snd_controls, + .num_controls = ARRAY_SIZE(ha_dsp_snd_controls), + .dapm_widgets = ha_dsp_widgets, + .num_dapm_widgets = ARRAY_SIZE(ha_dsp_widgets), + .dapm_routes = ha_dsp_routes, + .num_dapm_routes = ARRAY_SIZE(ha_dsp_routes), +}; + +static const struct regmap_config ha_dsp_regmap = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = 0x0f, + .reg_defaults = ha_dsp_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(ha_dsp_reg_defaults), + .cache_type = REGCACHE_RBTREE, +}; + +static int ha_dsp_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct regmap *regmap; + + regmap = devm_regmap_init_i2c(client, &ha_dsp_regmap); + if (IS_ERR(regmap)) { + dev_err(&client->dev, "Failed to create regmap: %ld\n", + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + return snd_soc_register_codec(&client->dev, &soc_codec_dev_ha_dsp, + &ha_dsp_dai, 1); +} + +static int ha_dsp_i2c_remove(struct i2c_client *client) +{ + snd_soc_unregister_codec(&client->dev); + + return 0; +} + +/* + * This name/ID is neded to match the DT node for the codec + */ +static const struct i2c_device_id ha_dsp_i2c_id[] = { + { "ha-dsp-audio", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ha_dsp_i2c_id); + +static struct i2c_driver ha_dsp_i2c_driver = { + .driver = { + .name = "ha-dsp-codec", + .owner = THIS_MODULE, + }, + .probe = ha_dsp_i2c_probe, + .remove = ha_dsp_i2c_remove, + .id_table = ha_dsp_i2c_id, +}; + +module_i2c_driver(ha_dsp_i2c_driver); + +MODULE_DESCRIPTION("ASoC HA DSP driver"); +MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula(a)bitmer.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/ha-dsp.h b/sound/soc/codecs/ha-dsp.h new file mode 100644 index 0000000..6622f8a --- /dev/null +++ b/sound/soc/codecs/ha-dsp.h @@ -0,0 +1,50 @@ +/* + * ha-dsp.h -- HA DSP ALSA SoC Audio driver + * + * Copyright 2011-2014 HEAD acoustics GmbH + * + * Author: Jarkko Nikula <jhnikula(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +#ifndef __HA_DSP_H__ +#define __HA_DSP_H__ + +/* Registers */ + +/* + * Bit 2-1: Monitor output selection: Off, ADC, DAC + * Bit 0: DSP Mode + */ +#define HA_DSP_CTRL 0x00 + +/* + * Bit 7: Mute + * Bit 6-0: Volume + */ +#define HA_DSP_DAC_VOL 0x01 +#define HA_DSP_ADC_VOL 0x02 + +/* + * Bit 2: INx Bypass to OUTx Switch + * Bit 1: DAC to OUTx switch + * Bit 0: Output power + */ +#define HA_DSP_OUT1_CTRL 0x08 +#define HA_DSP_OUT2_CTRL 0x09 +#define HA_DSP_OUT3_CTRL 0x0a +#define HA_DSP_OUT4_CTRL 0x0b +#define HA_DSP_OUT5_CTRL 0x0c +#define HA_DSP_OUT6_CTRL 0x0d +#define HA_DSP_OUT7_CTRL 0x0e +#define HA_DSP_OUT8_CTRL 0x0f + +/* Register bits and values */ + +/* HA_DSP_CTRL */ +#define HA_DSP_SW_RESET 0xff + +#endif -- 1.9.2

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[alsa-devel] [PATCH v3] ASoC: tda998x: add a codec to the HDMI transmitter
by Jean-Francois Moine 16 Aug '14

16 Aug '14

This patch adds a CODEC function to the NXP TDA998x HDMI transmitter. The CODEC handles both I2S and S/PDIF input and does dynamic input switch in the TDA998x I2C driver on start/stop audio streaming. Signed-off-by: Jean-Francois Moine <moinejf(a)free.fr> --- v3: fix bad rate (Andrew Jackson) v2: check double stream start (Mark Brown) --- .../devicetree/bindings/drm/i2c/tda998x.txt | 13 ++ drivers/gpu/drm/i2c/Makefile | 2 +- drivers/gpu/drm/i2c/tda998x_codec.c | 247 +++++++++++++++++++++ drivers/gpu/drm/i2c/tda998x_drv.c | 74 ++++-- drivers/gpu/drm/i2c/tda998x_drv.h | 32 +++ include/drm/i2c/tda998x.h | 1 + 6 files changed, 348 insertions(+), 21 deletions(-) create mode 100644 drivers/gpu/drm/i2c/tda998x_codec.c create mode 100644 drivers/gpu/drm/i2c/tda998x_drv.h diff --git a/Documentation/devicetree/bindings/drm/i2c/tda998x.txt b/Documentation/devicetree/bindings/drm/i2c/tda998x.txt index d7df01c..7ce4eac 100644 --- a/Documentation/devicetree/bindings/drm/i2c/tda998x.txt +++ b/Documentation/devicetree/bindings/drm/i2c/tda998x.txt @@ -15,6 +15,15 @@ Optional properties: - video-ports: 24 bits value which defines how the video controller output is wired to the TDA998x input - default: <0x230145> + - audio-ports: one or two values corresponding to entries in + the audio-port-names property. + + - audio-port-names: must contain "i2s", "spdif" entries + matching entries in the audio-ports property. + + - #sound-dai-cells: must be set to <1> for use with the simple-card. + The DAI 0 is the I2S input and the DAI 1 is the S/PDIF input. + Example: tda998x: hdmi-encoder { @@ -24,4 +33,8 @@ Example: interrupts = <27 2>; /* falling edge */ pinctrl-0 = <&pmx_camera>; pinctrl-names = "default"; + + audio-ports = <0x03>, <0x04>; + audio-port-names = "i2s", "spdif"; + #sound-dai-cells = <1>; }; diff --git a/drivers/gpu/drm/i2c/Makefile b/drivers/gpu/drm/i2c/Makefile index 43aa33b..f2d625c 100644 --- a/drivers/gpu/drm/i2c/Makefile +++ b/drivers/gpu/drm/i2c/Makefile @@ -6,5 +6,5 @@ obj-$(CONFIG_DRM_I2C_CH7006) += ch7006.o sil164-y := sil164_drv.o obj-$(CONFIG_DRM_I2C_SIL164) += sil164.o -tda998x-y := tda998x_drv.o +tda998x-y := tda998x_drv.o tda998x_codec.o obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o diff --git a/drivers/gpu/drm/i2c/tda998x_codec.c b/drivers/gpu/drm/i2c/tda998x_codec.c new file mode 100644 index 0000000..e22f974 --- /dev/null +++ b/drivers/gpu/drm/i2c/tda998x_codec.c @@ -0,0 +1,247 @@ +/* + * ALSA SoC TDA998X CODEC + * + * Copyright (C) 2014 Jean-Francois Moine + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <sound/soc.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <linux/of.h> +#include <linux/i2c.h> +#include <drm/drm_encoder_slave.h> +#include <drm/i2c/tda998x.h> + +#include "tda998x_drv.h" + +#define TDA998X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static int tda_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct tda998x_priv *priv = snd_soc_codec_get_drvdata(dai->codec); + u8 *eld = priv->eld; + struct snd_pcm_runtime *runtime = substream->runtime; + u8 *sad; + int sad_count; + unsigned eld_ver, mnl, rate_mask; + unsigned max_channels, fmt; + u64 formats; + struct snd_pcm_hw_constraint_list *rate_constraints = + &priv->rate_constraints; + static const u32 hdmi_rates[] = { + 32000, 44100, 48000, 88200, 96000, 176400, 192000 + }; + + /* check if streaming is already active */ + if (priv->dai_id != AFMT_NO_AUDIO) + return -EBUSY; + priv->dai_id = dai->id; + + if (!eld) + return 0; + + /* adjust the hw params from the ELD (EDID) */ + eld_ver = eld[0] >> 3; + if (eld_ver != 2 && eld_ver != 31) + return 0; + + mnl = eld[4] & 0x1f; + if (mnl > 16) + return 0; + + sad_count = eld[5] >> 4; + sad = eld + 20 + mnl; + + /* Start from the basic audio settings */ + max_channels = 2; + rate_mask = 0; + fmt = 0; + while (sad_count--) { + switch (sad[0] & 0x78) { + case 0x08: /* PCM */ + max_channels = max(max_channels, (sad[0] & 7) + 1u); + rate_mask |= sad[1]; + fmt |= sad[2] & 0x07; + break; + } + sad += 3; + } + + /* set the constraints */ + rate_constraints->list = hdmi_rates; + rate_constraints->count = ARRAY_SIZE(hdmi_rates); + rate_constraints->mask = rate_mask; + snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + rate_constraints); + + formats = 0; + if (fmt & 1) + formats |= SNDRV_PCM_FMTBIT_S16_LE; + if (fmt & 2) + formats |= SNDRV_PCM_FMTBIT_S20_3LE; + if (fmt & 4) + formats |= SNDRV_PCM_FMTBIT_S24_LE; + snd_pcm_hw_constraint_mask64(runtime, + SNDRV_PCM_HW_PARAM_FORMAT, + formats); + + snd_pcm_hw_constraint_minmax(runtime, + SNDRV_PCM_HW_PARAM_CHANNELS, + 1, max_channels); + return 0; +} + +static int tda_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct tda998x_priv *priv = snd_soc_codec_get_drvdata(dai->codec); + + /* Requires an attached display */ + if (!priv->encoder->crtc) + return -ENODEV; + + /* if same input and same parameters, do not do a full switch */ + if (dai->id == priv->params.audio_format && + params_format(params) == priv->audio_sample_format) { + tda998x_audio_start(priv, 0); + return 0; + } + priv->params.audio_format = dai->id; + priv->audio_sample_format = params_format(params); + priv->params.audio_cfg = + priv->audio_ports[dai->id == AFMT_I2S ? 0 : 1]; + tda998x_audio_start(priv, 1); + return 0; +} + +static void tda_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct tda998x_priv *priv = snd_soc_codec_get_drvdata(dai->codec); + + tda998x_audio_stop(priv); + priv->dai_id = AFMT_NO_AUDIO; +} + +static const struct snd_soc_dai_ops tda_ops = { + .startup = tda_startup, + .hw_params = tda_hw_params, + .shutdown = tda_shutdown, +}; + +static struct snd_soc_dai_driver tda998x_dai[] = { + { + .name = "i2s-hifi", + .id = AFMT_I2S, + .playback = { + .stream_name = "HDMI I2S Playback", + .channels_min = 1, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .rate_min = 5512, + .rate_max = 192000, + .formats = TDA998X_FORMATS, + }, + .ops = &tda_ops, + }, + { + .name = "spdif-hifi", + .id = AFMT_SPDIF, + .playback = { + .stream_name = "HDMI SPDIF Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .rate_min = 22050, + .rate_max = 192000, + .formats = TDA998X_FORMATS, + }, + .ops = &tda_ops, + }, +}; + +static const struct snd_soc_dapm_widget tda_widgets[] = { + SND_SOC_DAPM_OUTPUT("hdmi-out"), +}; +static const struct snd_soc_dapm_route tda_routes[] = { + { "hdmi-out", NULL, "HDMI I2S Playback" }, + { "hdmi-out", NULL, "HDMI SPDIF Playback" }, +}; + +static int tda_probe(struct snd_soc_codec *codec) +{ + struct i2c_client *i2c_client = to_i2c_client(codec->dev); + struct tda998x_priv *priv = i2c_get_clientdata(i2c_client); + struct device_node *np = codec->dev->of_node; + int i, j, ret; + const char *p; + + if (!priv) + return -ENODEV; + snd_soc_codec_set_drvdata(codec, priv); + + if (!np) + return 0; + + /* get the audio input ports*/ + for (i = 0; i < 2; i++) { + u32 port; + + ret = of_property_read_u32_index(np, "audio-ports", i, &port); + if (ret) { + if (i == 0) + dev_err(codec->dev, + "bad or missing audio-ports\n"); + break; + } + ret = of_property_read_string_index(np, "audio-port-names", + i, &p); + if (ret) { + dev_err(codec->dev, + "missing audio-port-names[%d]\n", i); + break; + } + if (strcmp(p, "i2s") == 0) { + j = 0; + } else if (strcmp(p, "spdif") == 0) { + j = 1; + } else { + dev_err(codec->dev, + "bad audio-port-names '%s'\n", p); + break; + } + priv->audio_ports[j] = port; + } + return 0; +} + +static const struct snd_soc_codec_driver soc_codec_tda998x = { + .probe = tda_probe, + .dapm_widgets = tda_widgets, + .num_dapm_widgets = ARRAY_SIZE(tda_widgets), + .dapm_routes = tda_routes, + .num_dapm_routes = ARRAY_SIZE(tda_routes), +}; + +int tda998x_codec_register(struct device *dev) +{ + return snd_soc_register_codec(dev, + &soc_codec_tda998x, + tda998x_dai, ARRAY_SIZE(tda998x_dai)); +} + +void tda998x_codec_unregister(struct device *dev) +{ + snd_soc_unregister_codec(dev); +} diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index 240c331..7e9f9dc 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -21,6 +21,7 @@ #include <linux/module.h> #include <linux/irq.h> #include <sound/asoundef.h> +#include <sound/pcm_params.h> #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> @@ -28,24 +29,9 @@ #include <drm/drm_edid.h> #include <drm/i2c/tda998x.h> -#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) +#include "tda998x_drv.h" -struct tda998x_priv { - struct i2c_client *cec; - struct i2c_client *hdmi; - uint16_t rev; - uint8_t current_page; - int dpms; - bool is_hdmi_sink; - u8 vip_cntrl_0; - u8 vip_cntrl_1; - u8 vip_cntrl_2; - struct tda998x_encoder_params params; - - wait_queue_head_t wq_edid; - volatile int wq_edid_wait; - struct drm_encoder *encoder; -}; +#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) @@ -640,12 +626,11 @@ static void tda998x_configure_audio(struct tda998x_priv *priv, struct drm_display_mode *mode, struct tda998x_encoder_params *p) { - uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv; + uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv, aclk; uint32_t n; /* Enable audio ports */ reg_write(priv, REG_ENA_AP, p->audio_cfg); - reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg); /* Set audio input source */ switch (p->audio_format) { @@ -654,13 +639,28 @@ tda998x_configure_audio(struct tda998x_priv *priv, clksel_aip = AIP_CLKSEL_AIP_SPDIF; clksel_fs = AIP_CLKSEL_FS_FS64SPDIF; cts_n = CTS_N_M(3) | CTS_N_K(3); + aclk = 0; /* no clock */ break; case AFMT_I2S: reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); clksel_aip = AIP_CLKSEL_AIP_I2S; clksel_fs = AIP_CLKSEL_FS_ACLK; - cts_n = CTS_N_M(3) | CTS_N_K(3); + /* with I2S input, the CTS_N predivider depends on + * the sample width */ + switch (priv->audio_sample_format) { + case SNDRV_PCM_FORMAT_S16_LE: + cts_n = CTS_N_M(3) | CTS_N_K(1); + break; + case SNDRV_PCM_FORMAT_S24_LE: + cts_n = CTS_N_M(3) | CTS_N_K(2); + break; + default: + case SNDRV_PCM_FORMAT_S32_LE: + cts_n = CTS_N_M(3) | CTS_N_K(3); + break; + } + aclk = 1; /* clock enable */ break; default: @@ -672,6 +672,7 @@ tda998x_configure_audio(struct tda998x_priv *priv, reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | AIP_CNTRL_0_ACR_MAN); /* auto CTS */ reg_write(priv, REG_CTS_N, cts_n); + reg_write(priv, REG_ENA_ACLK, aclk); /* * Audio input somehow depends on HDMI line rate which is @@ -728,6 +729,24 @@ tda998x_configure_audio(struct tda998x_priv *priv, tda998x_write_aif(priv, p); } +/* tda998x codec interface */ +void tda998x_audio_start(struct tda998x_priv *priv, + int full) +{ + struct tda998x_encoder_params *p = &priv->params; + + if (!full) { + reg_write(priv, REG_ENA_AP, p->audio_cfg); + return; + } + tda998x_configure_audio(priv, &priv->encoder->crtc->hwmode, p); +} + +void tda998x_audio_stop(struct tda998x_priv *priv) +{ + reg_write(priv, REG_ENA_AP, 0); +} + /* DRM encoder functions */ static void @@ -1149,6 +1168,11 @@ tda998x_encoder_get_modes(struct drm_encoder *encoder, drm_mode_connector_update_edid_property(connector, edid); n = drm_add_edid_modes(connector, edid); priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); + + /* keep the EDID as ELD for the audio subsystem */ + drm_edid_to_eld(connector, edid); + priv->eld = connector->eld; + kfree(edid); } @@ -1191,6 +1215,8 @@ tda998x_encoder_destroy(struct drm_encoder *encoder) if (priv->hdmi->irq) free_irq(priv->hdmi->irq, priv); + tda998x_codec_unregister(&priv->hdmi->dev); + if (priv->cec) i2c_unregister_device(priv->cec); kfree(priv); @@ -1239,10 +1265,15 @@ tda998x_encoder_init(struct i2c_client *client, if (!priv) return -ENOMEM; + i2c_set_clientdata(client, priv); + priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); + priv->params.audio_frame[1] = 1; /* channels - 1 */ + priv->params.audio_sample_rate = 48000; /* 48kHz */ + priv->current_page = 0xff; priv->hdmi = client; priv->cec = i2c_new_dummy(client->adapter, 0x34); @@ -1340,6 +1371,9 @@ tda998x_encoder_init(struct i2c_client *client, /* enable EDID read irq: */ reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); + /* register the audio CODEC */ + tda998x_codec_register(&client->dev); + if (!np) return 0; /* non-DT */ diff --git a/drivers/gpu/drm/i2c/tda998x_drv.h b/drivers/gpu/drm/i2c/tda998x_drv.h new file mode 100644 index 0000000..e6c8dd5 --- /dev/null +++ b/drivers/gpu/drm/i2c/tda998x_drv.h @@ -0,0 +1,32 @@ +/* tda998x private data */ + +struct tda998x_priv { + struct i2c_client *cec; + struct i2c_client *hdmi; + uint16_t rev; + uint8_t current_page; + int dpms; + bool is_hdmi_sink; + u8 vip_cntrl_0; + u8 vip_cntrl_1; + u8 vip_cntrl_2; + struct tda998x_encoder_params params; + + wait_queue_head_t wq_edid; + volatile int wq_edid_wait; + struct drm_encoder *encoder; + + u8 audio_ports[2]; + int audio_sample_format; + int dai_id; /* DAI ID when streaming active */ + + u8 *eld; + + struct snd_pcm_hw_constraint_list rate_constraints; +}; + +int tda998x_codec_register(struct device *dev); +void tda998x_codec_unregister(struct device *dev); + +void tda998x_audio_start(struct tda998x_priv *priv, int full); +void tda998x_audio_stop(struct tda998x_priv *priv); diff --git a/include/drm/i2c/tda998x.h b/include/drm/i2c/tda998x.h index 3e419d9..31757df 100644 --- a/include/drm/i2c/tda998x.h +++ b/include/drm/i2c/tda998x.h @@ -20,6 +20,7 @@ struct tda998x_encoder_params { u8 audio_frame[6]; enum { + AFMT_NO_AUDIO = 0, AFMT_SPDIF, AFMT_I2S } audio_format; -- 2.0.1

3 2

[alsa-devel] [PATCH RFC] ASoC: fsl: Add Freescale Generic ASoC Sound Card with ASRC support
by Nicolin Chen 16 Aug '14

16 Aug '14

The Freescale Generic ASoC Sound Card is a general ASoC DAI Link driver that can be used, ideally, for all Freescale CPU DAI drivers and external CODECs. The idea of this generic sound card is a bit like ASoC Simple Card. However, for Freescale SoCs (especially those released in recent years), most of them have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And this is a specific feature that might be painstakingly controlled and merged into the Simple Card driver. So having this driver will allow all Freescale SoC users to benefit from the simplification to support a new card and the capability of wide sample rates support through ASRC. The driver is initially designed for sound card using I2S or PCM DAI formats. However, it's also possible to merge those non-I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, into this card as long as the merge will not break the original function and as long as there is something redundant that can be abstracted along with I2S type sound cards. As an initial version, it only supports three cards that I can test: imx-audio-cs42888, a new card that links ESAI with CS42888 CODEC imx-audio-sgtl5000, just like the old imx-sgtl5000.c driver imx-audio-wm8962, just like the old imx-wm8962.c driver The driver is also compatible with the old Device Tree bindings of WM8962 and SGTL5000. So we may consider to remove those two drivers after this driver is totally enabled. (It needs to be added into defconfig) Signed-off-by: Nicolin Chen <nicoleotsuka(a)gmail.com> --- .../devicetree/bindings/sound/fsl-asoc-card.txt | 82 +++ sound/soc/fsl/Kconfig | 16 + sound/soc/fsl/Makefile | 2 + sound/soc/fsl/fsl-asoc-card.c | 573 +++++++++++++++++++++ 4 files changed, 673 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/fsl-asoc-card.txt create mode 100644 sound/soc/fsl/fsl-asoc-card.c diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt new file mode 100644 index 0000000..a96774c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt @@ -0,0 +1,82 @@ +Freescale Generic ASoC Sound Card with ASRC support + +The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale +SoCs connecting with external CODECs. + +The idea of this generic sound card is a bit like ASoC Simple Card. However, +for Freescale SoCs (especially those released in recent years), most of them +have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And +this is a specific feature that might be painstakingly controlled and merged +into the Simple Card. + +So having this generic sound card allows all Freescale SoC users to benefit +from the simplification of a new card support and the capability of the wide +sample rates support through ASRC. + +Note: The card is initially designed for those sound cards who use I2S and + PCM DAI formats. However, it'll be also possible to support those non + I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as long + as the driver has been properly upgraded. + + +The compatible list for this generic sound card currently: + "fsl,imx-audio-cs42888" + + "fsl,imx-audio-wm8962" + (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt) + + "fsl,imx-audio-sgtl5000" + (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt) + +Required properties: + + - compatible : Contains one of entries in the compatible list. + + - model : The user-visible name of this sound complex + + - audio-cpu : The phandle of an CPU DAI controller + + - audio-codec : The phandle of an audio codec + + - audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. There're a few pre-designed board connectors: + * Line Out Jack + * Line In Jack + * Headphone Jack + * Mic Jack + * Ext Spk + * AMIC (stands for Analog Microphone Jack) + * DMIC (stands for Digital Microphone Jack) + + Note: The "Mic Jack" and "AMIC" are redundant while + coexsiting in order to support the old bindings + of wm8962 and sgtl5000. + +Optional properties: + + - audio-asrc : The phandle of ASRC. It can be absent if there's no + need to add ASRC support via DPCM. + +Example: +sound-cs42888 { + compatible = "fsl,imx-audio-cs42888"; + model = "cs42888-audio"; + audio-cpu = <&esai>; + audio-asrc = <&asrc>; + audio-codec = <&cs42888>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; +}; diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 2fb8a43..b55bf36 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -58,6 +58,22 @@ config SND_SOC_FSL_ESAI config SND_SOC_FSL_UTILS tristate +config SND_SOC_FSL_ASOC_CARD + tristate "Generic ASoC Sound Card with ASRC support" + depends on OF && I2C + select SND_SOC_IMX_PCM_DMA + select SND_SOC_FSL_ESAI + select SND_SOC_FSL_SAI + select SND_SOC_FSL_SSI + select SND_SOC_CS42XX8_I2C + select SND_SOC_SGTL5000 + select SND_SOC_WM8962 + help + ALSA SoC Audio support with ASRC feature for Freescale SoCs that have + ESAI/SAI/SSI and connect with external CODECs such as WM8962, CS42888 + and SGTL5000. + Say Y if you want to add support for Freescale Generic ASoC Sound Card. + config SND_SOC_IMX_PCM_DMA tristate select SND_SOC_GENERIC_DMAENGINE_PCM diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile index 9ff5926..8f6d84e 100644 --- a/sound/soc/fsl/Makefile +++ b/sound/soc/fsl/Makefile @@ -11,6 +11,7 @@ snd-soc-p1022-rdk-objs := p1022_rdk.o obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o # Freescale SSI/DMA/SAI/SPDIF Support +snd-soc-fsl-asoc-card-objs := fsl-asoc-card.o snd-soc-fsl-asrc-objs := fsl_asrc.o fsl_asrc_dma.o snd-soc-fsl-sai-objs := fsl_sai.o snd-soc-fsl-ssi-y := fsl_ssi.o @@ -19,6 +20,7 @@ snd-soc-fsl-spdif-objs := fsl_spdif.o snd-soc-fsl-esai-objs := fsl_esai.o snd-soc-fsl-utils-objs := fsl_utils.o snd-soc-fsl-dma-objs := fsl_dma.o +obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc.o obj-$(CONFIG_SND_SOC_FSL_SAI) += snd-soc-fsl-sai.o obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o diff --git a/sound/soc/fsl/fsl-asoc-card.c b/sound/soc/fsl/fsl-asoc-card.c new file mode 100644 index 0000000..cf3f1f4 --- /dev/null +++ b/sound/soc/fsl/fsl-asoc-card.c @@ -0,0 +1,573 @@ +/* + * Freescale Generic ASoC Sound Card driver with ASRC + * + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Author: Nicolin Chen <nicoleotsuka(a)gmail.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/clk.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> + +#include "fsl_esai.h" +#include "fsl_sai.h" +#include "imx-audmux.h" + +#include "../codecs/sgtl5000.h" +#include "../codecs/wm8962.h" + +#define RX 0 +#define TX 1 + +/* Default DAI format without Master and Slave flag */ +#define DAI_FMT_BASE (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF) + +/** + * CODEC private data + * + * @mclk_freq: Clock rate of MCLK + * @mclk_id: MCLK (or main clock) id for set_sysclk() + * @fll_id: FLL (or secordary clock) id for set_sysclk() + * @pll_id: PLL id for set_pll() + */ +struct codec_priv { + unsigned long mclk_freq; + u32 mclk_id; + u32 fll_id; + u32 pll_id; +}; + +/** + * CPU private data + * + * @sysclk_freq[2]: SYSCLK rates for set_sysclk() + * @sysclk_dir[2]: SYSCLK directions for set_sysclk() + * @sysclk_id[2]: SYSCLK ids for set_sysclk() + * + * Note: [1] for tx and [0] for rx + */ +struct cpu_priv { + unsigned long sysclk_freq[2]; + u32 sysclk_dir[2]; + u32 sysclk_id[2]; +}; + +/** + * Freescale Generic ASOC card private data + * + * @dai_link[3]: DAI link structure including normal one and DPCM link + * @pdev: platform device pointer + * @codec_priv: CODEC private data + * @cpu_priv: CPU private data + * @card: ASoC card structure + * @sample_rate: Current sample rate + * @sample_format: Current sample format + * @asrc_rate: ASRC sample rate used by Back-Ends + * @asrc_format: ASRC sample format used by Back-Ends + * @dai_fmt: DAI format between CPU and CODEC + * @name: Card name + */ + +struct fsl_asoc_card_priv { + struct snd_soc_dai_link dai_link[3]; + struct platform_device *pdev; + struct codec_priv codec_priv; + struct cpu_priv cpu_priv; + struct snd_soc_card card; + u32 sample_rate; + u32 sample_format; + u32 asrc_rate; + u32 asrc_format; + u32 dai_fmt; + char name[32]; +}; + +/** + * This dapm route map exsits for DPCM link only. + * The other routes shall go through Device Tree. + */ +static const struct snd_soc_dapm_route audio_map[] = { + {"CPU-Playback", NULL, "ASRC-Playback"}, + {"Playback", NULL, "CPU-Playback"}, + {"ASRC-Capture", NULL, "CPU-Capture"}, + {"CPU-Capture", NULL, "Capture"}, +}; + +/* Add all possible widgets into here without being redundant */ +static const struct snd_soc_dapm_widget fsl_asoc_card_dapm_widgets[] = { + SND_SOC_DAPM_LINE("Line Out Jack", NULL), + SND_SOC_DAPM_LINE("Line In Jack", NULL), + SND_SOC_DAPM_HP("Headphone Jack", NULL), + SND_SOC_DAPM_SPK("Ext Spk", NULL), + SND_SOC_DAPM_MIC("Mic Jack", NULL), + SND_SOC_DAPM_MIC("AMIC", NULL), + SND_SOC_DAPM_MIC("DMIC", NULL), +}; + +static int fsl_asoc_card_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(rtd->card); + bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; + struct cpu_priv *cpu_priv = &priv->cpu_priv; + struct device *dev = rtd->card->dev; + int ret; + + priv->sample_rate = params_rate(params); + priv->sample_format = params_format(params); + + if (priv->card.set_bias_level) + return 0; + + /* Specific configurations of DAIs starts from here */ + ret = snd_soc_dai_set_sysclk(rtd->cpu_dai, cpu_priv->sysclk_id[tx], + cpu_priv->sysclk_freq[tx], + cpu_priv->sysclk_dir[tx]); + if (ret) { + dev_err(dev, "failed to set sysclk for cpu dai\n"); + return ret; + } + + return 0; +} + +static struct snd_soc_ops fsl_asoc_card_ops = { + .hw_params = fsl_asoc_card_hw_params, +}; + +static int be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(rtd->card); + struct snd_interval *rate; + struct snd_mask *mask; + + rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); + rate->max = rate->min = priv->asrc_rate; + + mask = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); + snd_mask_none(mask); + snd_mask_set(mask, priv->asrc_format); + + return 0; +} + +static struct snd_soc_dai_link fsl_asoc_card_dai[] = { + /* Default ASoC DAI Link*/ + { + .name = "HiFi", + .stream_name = "HiFi", + .ops = &fsl_asoc_card_ops, + }, + /* DPCM Link between Front-End and Back-End (Optional) */ + { + .name = "HiFi-ASRC-FE", + .stream_name = "HiFi-ASRC-FE", + .codec_name = "snd-soc-dummy", + .codec_dai_name = "snd-soc-dummy-dai", + .dpcm_playback = 1, + .dpcm_capture = 1, + .dynamic = 1, + }, + { + .name = "HiFi-ASRC-BE", + .stream_name = "HiFi-ASRC-BE", + .platform_name = "snd-soc-dummy", + .be_hw_params_fixup = be_hw_params_fixup, + .ops = &fsl_asoc_card_ops, + .dpcm_playback = 1, + .dpcm_capture = 1, + .no_pcm = 1, + }, +}; + +static int fsl_asoc_card_set_bias_level(struct snd_soc_card *card, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level) +{ + struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(card); + struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai; + struct codec_priv *codec_priv = &priv->codec_priv; + struct device *dev = card->dev; + unsigned int pll_out; + int ret; + + if (dapm->dev != codec_dai->dev) + return 0; + + switch (level) { + case SND_SOC_BIAS_PREPARE: + if (dapm->bias_level != SND_SOC_BIAS_STANDBY) + break; + + if (priv->sample_format == SNDRV_PCM_FORMAT_S24_LE) + pll_out = priv->sample_rate * 384; + else + pll_out = priv->sample_rate * 256; + + ret = snd_soc_dai_set_pll(codec_dai, codec_priv->pll_id, + codec_priv->mclk_id, + codec_priv->mclk_freq, pll_out); + if (ret) { + dev_err(dev, "failed to start FLL: %d\n", ret); + return ret; + } + + ret = snd_soc_dai_set_sysclk(codec_dai, codec_priv->fll_id, + pll_out, SND_SOC_CLOCK_IN); + if (ret) { + dev_err(dev, "failed to set SYSCLK: %d\n", ret); + return ret; + } + break; + + case SND_SOC_BIAS_STANDBY: + if (dapm->bias_level != SND_SOC_BIAS_PREPARE) + break; + + ret = snd_soc_dai_set_sysclk(codec_dai, codec_priv->mclk_id, + codec_priv->mclk_freq, + SND_SOC_CLOCK_IN); + if (ret) { + dev_err(dev, "failed to switch away from FLL: %d\n", ret); + return ret; + } + + ret = snd_soc_dai_set_pll(codec_dai, codec_priv->pll_id, 0, 0, 0); + if (ret) { + dev_err(dev, "failed to stop FLL: %d\n", ret); + return ret; + } + break; + + default: + break; + } + + return 0; +} + +static int fsl_asoc_card_audmux_init(struct device_node *np, + struct fsl_asoc_card_priv *priv) +{ + struct device *dev = &priv->pdev->dev; + u32 int_ptcr = 0, ext_ptcr = 0; + int int_port, ext_port; + int ret; + + ret = of_property_read_u32(np, "mux-int-port", &int_port); + if (ret) { + dev_err(dev, "mux-int-port missing or invalid\n"); + return ret; + } + ret = of_property_read_u32(np, "mux-ext-port", &ext_port); + if (ret) { + dev_err(dev, "mux-ext-port missing or invalid\n"); + return ret; + } + + /* + * The port numbering in the hardware manual starts at 1, while + * the AUDMUX API expects it starts at 0. + */ + int_port--; + ext_port--; + + /* + * Use asynchronous mode (6 wires) for all cases. + * If only 4 wires are needed, just set SSI into + * synchronous mode and enable 4 PADs in IOMUX. + */ + switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + int_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | ext_port) | + IMX_AUDMUX_V2_PTCR_RCSEL(8 | ext_port) | + IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) | + IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) | + IMX_AUDMUX_V2_PTCR_RFSDIR | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR; + break; + case SND_SOC_DAIFMT_CBM_CFS: + int_ptcr = IMX_AUDMUX_V2_PTCR_RCSEL(8 | ext_port) | + IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR; + ext_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | int_port) | + IMX_AUDMUX_V2_PTCR_TFSEL(int_port) | + IMX_AUDMUX_V2_PTCR_RFSDIR | + IMX_AUDMUX_V2_PTCR_TFSDIR; + break; + case SND_SOC_DAIFMT_CBS_CFM: + int_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | ext_port) | + IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) | + IMX_AUDMUX_V2_PTCR_RFSDIR | + IMX_AUDMUX_V2_PTCR_TFSDIR; + ext_ptcr = IMX_AUDMUX_V2_PTCR_RCSEL(8 | int_port) | + IMX_AUDMUX_V2_PTCR_TCSEL(int_port) | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR; + break; + case SND_SOC_DAIFMT_CBS_CFS: + ext_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | int_port) | + IMX_AUDMUX_V2_PTCR_RCSEL(8 | int_port) | + IMX_AUDMUX_V2_PTCR_TFSEL(int_port) | + IMX_AUDMUX_V2_PTCR_TCSEL(int_port) | + IMX_AUDMUX_V2_PTCR_RFSDIR | + IMX_AUDMUX_V2_PTCR_RCLKDIR | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR; + break; + default: + return -EINVAL; + } + + /* Asynchronous mode can not be set along with RCLKDIR */ + ret = imx_audmux_v2_configure_port(int_port, 0, + IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port)); + if (ret) { + dev_err(dev, "audmux internal port setup failed\n"); + return ret; + } + + ret = imx_audmux_v2_configure_port(int_port, int_ptcr, + IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port)); + if (ret) { + dev_err(dev, "audmux internal port setup failed\n"); + return ret; + } + + ret = imx_audmux_v2_configure_port(ext_port, 0, + IMX_AUDMUX_V2_PDCR_RXDSEL(int_port)); + if (ret) { + dev_err(dev, "audmux external port setup failed\n"); + return ret; + } + + ret = imx_audmux_v2_configure_port(ext_port, ext_ptcr, + IMX_AUDMUX_V2_PDCR_RXDSEL(int_port)); + if (ret) { + dev_err(dev, "audmux external port setup failed\n"); + return ret; + } + + return 0; +} + +static int fsl_asoc_card_late_probe(struct snd_soc_card *card) +{ + struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(card); + struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai; + struct codec_priv *codec_priv = &priv->codec_priv; + struct device *dev = card->dev; + int ret; + + ret = snd_soc_dai_set_sysclk(codec_dai, codec_priv->mclk_id, + codec_priv->mclk_freq, SND_SOC_CLOCK_IN); + if (ret) { + dev_err(dev, "failed to set sysclk in %s\n", __func__); + return ret; + } + + return 0; +} + +static int fsl_asoc_card_probe(struct platform_device *pdev) +{ + struct device_node *cpu_np, *codec_np, *asrc_np; + struct device_node *np = pdev->dev.of_node; + struct platform_device *asrc_pdev = NULL; + struct platform_device *cpu_pdev; + struct fsl_asoc_card_priv *priv; + struct i2c_client *codec_dev; + struct clk *codec_clk; + u32 width; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + cpu_np = of_parse_phandle(np, "audio-cpu", 0); + /* Give a chance to old DT binding */ + if (!cpu_np) + cpu_np = of_parse_phandle(np, "ssi-controller", 0); + codec_np = of_parse_phandle(np, "audio-codec", 0); + if (!cpu_np || !codec_np) { + dev_err(&pdev->dev, "phandle missing or invalid\n"); + ret = -EINVAL; + goto fail; + } + + cpu_pdev = of_find_device_by_node(cpu_np); + if (!cpu_pdev) { + dev_err(&pdev->dev, "failed to find CPU DAI device\n"); + ret = -EINVAL; + goto fail; + } + + codec_dev = of_find_i2c_device_by_node(codec_np); + if (!codec_dev) { + dev_err(&pdev->dev, "failed to find codec platform device\n"); + ret = -EINVAL; + goto fail; + } + + asrc_np = of_parse_phandle(np, "audio-asrc", 0); + if (asrc_np) + asrc_pdev = of_find_device_by_node(asrc_np); + + /* Get the MCLK rate only, and leave it controlled by CODEC drivers */ + codec_clk = clk_get(&codec_dev->dev, NULL); + if (!IS_ERR(codec_clk)) { + priv->codec_priv.mclk_freq = clk_get_rate(codec_clk); + clk_put(codec_clk); + } + + /* Default sample rate and format, will be updated in hw_params() */ + priv->sample_rate = 44100; + priv->sample_format = SNDRV_PCM_FORMAT_S16_LE; + + /* Assign a default DAI format, and allow each card to overwrite it */ + priv->dai_fmt = DAI_FMT_BASE; + + /* Diversify the card configurations */ + if (of_device_is_compatible(np, "fsl,imx-audio-cs42888")) { + priv->card.set_bias_level = NULL; + priv->cpu_priv.sysclk_freq[TX] = priv->codec_priv.mclk_freq; + priv->cpu_priv.sysclk_freq[RX] = priv->codec_priv.mclk_freq; + priv->cpu_priv.sysclk_dir[TX] = SND_SOC_CLOCK_OUT; + priv->cpu_priv.sysclk_dir[RX] = SND_SOC_CLOCK_OUT; + priv->dai_fmt |= SND_SOC_DAIFMT_CBS_CFS; + } else if (of_device_is_compatible(np, "fsl,imx-audio-sgtl5000")) { + priv->codec_priv.mclk_id = SGTL5000_SYSCLK; + priv->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM; + } else if (of_device_is_compatible(np, "fsl,imx-audio-wm8962")) { + priv->card.set_bias_level = fsl_asoc_card_set_bias_level; + priv->codec_priv.mclk_id = WM8962_SYSCLK_MCLK; + priv->codec_priv.fll_id = WM8962_SYSCLK_FLL; + priv->codec_priv.pll_id = WM8962_FLL; + priv->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM; + } else { + dev_err(&pdev->dev, "unknown Device Tree compatible\n"); + return -EINVAL; + } + + /* Common settings for corresponding Freescale CPU DAI driver */ + if (strstr(cpu_np->name, "ssi")) { + /* Only SSI needs to configure AUDMUX */ + ret = fsl_asoc_card_audmux_init(np, priv); + if (ret) { + dev_err(&pdev->dev, "failed to init audmux\n"); + goto fail; + } + } else if (strstr(cpu_np->name, "esai")) { + priv->cpu_priv.sysclk_id[1] = ESAI_HCKT_EXTAL; + priv->cpu_priv.sysclk_id[0] = ESAI_HCKR_EXTAL; + } else if (strstr(cpu_np->name, "sai")) { + priv->cpu_priv.sysclk_id[1] = FSL_SAI_CLK_MAST1; + priv->cpu_priv.sysclk_id[0] = FSL_SAI_CLK_MAST1; + } + + sprintf(priv->name, "%s-audio", codec_dev->name); + + /* Initialize sound card */ + priv->pdev = pdev; + priv->card.dev = &pdev->dev; + priv->card.name = priv->name; + priv->card.dai_link = priv->dai_link; + priv->card.dapm_routes = audio_map; + priv->card.late_probe = fsl_asoc_card_late_probe; + priv->card.num_dapm_routes = ARRAY_SIZE(audio_map); + priv->card.dapm_widgets = fsl_asoc_card_dapm_widgets; + priv->card.num_dapm_widgets = ARRAY_SIZE(fsl_asoc_card_dapm_widgets); + + memcpy(priv->dai_link, fsl_asoc_card_dai, + sizeof(struct snd_soc_dai_link) * ARRAY_SIZE(priv->dai_link)); + + /* Normal DAI Link */ + priv->dai_link[0].cpu_of_node = cpu_np; + priv->dai_link[0].codec_of_node = codec_np; + priv->dai_link[0].codec_dai_name = codec_dev->name; + priv->dai_link[0].platform_of_node = cpu_np; + priv->dai_link[0].dai_fmt = priv->dai_fmt; + priv->card.num_links = 1; + + if (asrc_pdev) { + /* DPCM DAI Links only if ASRC exsits */ + priv->dai_link[1].cpu_of_node = asrc_np; + priv->dai_link[1].platform_of_node = asrc_np; + priv->dai_link[2].codec_dai_name = codec_dev->name; + priv->dai_link[2].codec_of_node = codec_np; + priv->dai_link[2].cpu_of_node = cpu_np; + priv->dai_link[2].dai_fmt = priv->dai_fmt; + priv->card.num_links = 3; + + ret = of_property_read_u32(asrc_np, "fsl,asrc-rate", + &priv->asrc_rate); + if (ret) { + dev_err(&pdev->dev, "failed to get output rate\n"); + ret = -EINVAL; + goto fail; + } + + ret = of_property_read_u32(asrc_np, "fsl,asrc-width", &width); + if (ret) { + dev_err(&pdev->dev, "failed to get output rate\n"); + ret = -EINVAL; + goto fail; + } + + if (width == 24) + priv->asrc_format = SNDRV_PCM_FORMAT_S24_LE; + else + priv->asrc_format = SNDRV_PCM_FORMAT_S16_LE; + } + + /* Finish card registering */ + platform_set_drvdata(pdev, priv); + snd_soc_card_set_drvdata(&priv->card, priv); + + ret = devm_snd_soc_register_card(&pdev->dev, &priv->card); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); + +fail: + of_node_put(codec_np); + of_node_put(asrc_np); + of_node_put(cpu_np); + + return ret; +} + +static const struct of_device_id fsl_asoc_card_dt_ids[] = { + { .compatible = "fsl,imx-audio-cs42888", }, + { .compatible = "fsl,imx-audio-sgtl5000", }, + { .compatible = "fsl,imx-audio-wm8962", }, + {} +}; + +static struct platform_driver fsl_asoc_card_driver = { + .probe = fsl_asoc_card_probe, + .driver = { + .name = "fsl-asoc-card", + .pm = &snd_soc_pm_ops, + .of_match_table = fsl_asoc_card_dt_ids, + }, +}; +module_platform_driver(fsl_asoc_card_driver); + +MODULE_DESCRIPTION("Freescale Generic ASoC Sound Card driver with ASRC"); +MODULE_AUTHOR("Nicolin Chen <nicoleotsuka(a)gmail.com>"); +MODULE_ALIAS("platform:fsl-asoc-card"); +MODULE_LICENSE("GPL"); -- 1.8.4

2 1

[alsa-devel] [PATCH] ASoC: rt5645: add clock source selection controls
by bardliao＠realtek.com 16 Aug '14

16 Aug '14

From: Bard Liao <bardliao(a)realtek.com> We can select the clock source of some digital widgets in rt5645. This patch adds the controls of those selections. Signed-off-by: Bard Liao <bardliao(a)realtek.com> --- sound/soc/codecs/rt5645.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c index a7762d0..e8e30b7 100644 --- a/sound/soc/codecs/rt5645.c +++ b/sound/soc/codecs/rt5645.c @@ -440,6 +440,89 @@ static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum, RT5645_TDM_CTRL_1, 8, rt5645_tdm_adc_data_select); +static const char * const rt5645_asrc_clk_source[] = { + "clk_sysy_div_out", "clk_i2s1_track", "clk_i2s2_track", + "clk_i2s3_track", "clk_i2s4_track", "clk_sys2", "clk_sys3", + "clk_sys4", "clk_sys5" +}; + +static const SOC_ENUM_SINGLE_DECL(rt5645_da_sto_asrc_enum, RT5645_ASRC_2, + 12, rt5645_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5645_da_monol_asrc_enum, RT5645_ASRC_2, + 8, rt5645_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5645_da_monor_asrc_enum, RT5645_ASRC_2, + 4, rt5645_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5645_ad_sto1_asrc_enum, RT5645_ASRC_2, + 0, rt5645_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5645_ad_monol_asrc_enum, RT5645_ASRC_3, + 4, rt5645_asrc_clk_source); + +static const SOC_ENUM_SINGLE_DECL(rt5645_ad_monor_asrc_enum, RT5645_ASRC_3, + 0, rt5645_asrc_clk_source); + +static int rt5645_clk_sel_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + unsigned int u_bit = 0, p_bit = 0; + struct soc_enum *em = + (struct soc_enum *)kcontrol->private_value; + + switch (em->reg) { + case RT5645_ASRC_2: + switch (em->shift_l) { + case 0: + u_bit = 0x8; + p_bit = RT5645_PWR_ADC_S1F; + break; + case 4: + u_bit = 0x100; + p_bit = RT5645_PWR_DAC_MF_R; + break; + case 8: + u_bit = 0x200; + p_bit = RT5645_PWR_DAC_MF_L; + break; + case 12: + u_bit = 0x400; + p_bit = RT5645_PWR_DAC_S1F; + break; + } + break; + case RT5645_ASRC_3: + switch (em->shift_l) { + case 0: + u_bit = 0x1; + p_bit = RT5645_PWR_ADC_MF_R; + break; + case 4: + u_bit = 0x2; + p_bit = RT5645_PWR_ADC_MF_L; + break; + } + break; + } + + if (u_bit || p_bit) { + switch (ucontrol->value.integer.value[0]) { + case 1 ... 4: /*enable*/ + if (snd_soc_read(codec, RT5645_PWR_DIG2) & p_bit) + snd_soc_update_bits(codec, + RT5645_ASRC_1, u_bit, u_bit); + break; + default: /*disable*/ + snd_soc_update_bits(codec, RT5645_ASRC_1, u_bit, 0); + break; + } + } + + return snd_soc_put_enum_double(kcontrol, ucontrol); +} + static const struct snd_kcontrol_new rt5645_snd_controls[] = { /* Speaker Output Volume */ SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, @@ -511,6 +594,20 @@ static const struct snd_kcontrol_new rt5645_snd_controls[] = { SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0), SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0), SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0), + + /* Clock Source Selection*/ + SOC_ENUM_EXT("DA STO Clk Sel", rt5645_da_sto_asrc_enum, + snd_soc_get_enum_double, rt5645_clk_sel_put), + SOC_ENUM_EXT("DA MONOL Clk Sel", rt5645_da_monol_asrc_enum, + snd_soc_get_enum_double, rt5645_clk_sel_put), + SOC_ENUM_EXT("DA MONOR Clk Sel", rt5645_da_monor_asrc_enum, + snd_soc_get_enum_double, rt5645_clk_sel_put), + SOC_ENUM_EXT("AD STO1 Clk Sel", rt5645_ad_sto1_asrc_enum, + snd_soc_get_enum_double, rt5645_clk_sel_put), + SOC_ENUM_EXT("AD MONOL Clk Sel", rt5645_ad_monol_asrc_enum, + snd_soc_get_enum_double, rt5645_clk_sel_put), + SOC_ENUM_EXT("AD MONOR Clk Sel", rt5645_ad_monor_asrc_enum, + snd_soc_get_enum_double, rt5645_clk_sel_put), }; /** -- 1.8.1.1.439.g50a6b54

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[alsa-devel] A minimal playback program does't work on my system
by Carpon frédéric 16 Aug '14

16 Aug '14

Hello, Yesterday i have written. I answer to everybody. I am new and I don't know if there is special rule. Note : It would be good to have a forum to see the messages and answers in a pretty form. the programme in c comes from http://equalarea.com/paul/alsa-audio.html you can download it at https://mon-partage.fr/f/uvyw39wo/ To answer to Michael i have sound in my HDMI with that : >speaker-test -c2 -D hw:0,0 so i did that >gcc -o minimal_playback minimal_playback.c -lasound (warning comes) and >./minimal_playback "plughw:0,0" and i have this result : >Error of segmentation Where i can an exemple with the possibility to do something like that : >./minimal_playback "plughw:0,0" "mywave.wav" Thank you for your help

3 4

[alsa-devel] Alsa on Mac os x
by Carpon frédéric 16 Aug '14

16 Aug '14

Hello , i have looked for an installation of alsa on mac but i don't see. I am afraid if the package Linux would destroy fonctionality with his makefile. Do you know a tutorial to install it, configure for mac ? Thank You for your help

2 1

[alsa-devel] [GIT PULL] ASoC fixes for v3.17
by Mark Brown 16 Aug '14

16 Aug '14

The following changes since commit ae34a78c430c37c06404f032fb04e51315204281: Merge remote-tracking branch 'asoc/topic/wm8985' into asoc-next (2014-08-04 16:32:25 +0100) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git asoc-v3.17-rc1 for you to fetch changes up to 7c063edee6855a2489f995578f6c7a4ab0ddfe07: Merge remote-tracking branches 'asoc/fix/arizona', 'asoc/fix/fsl', 'asoc/fix/fsl-esai', 'asoc/fix/intel', 'asoc/fix/mcasp' and 'asoc/fix/pxa' into asoc-linus (2014-08-15 12:51:29 +0100) ---------------------------------------------------------------- ASoC: Fixes for v3.17 Nothing too exciting here, a bunch of driver fixes that came along since the initial pull request but none that really stand our and a warning fix in the core. ---------------------------------------------------------------- Daniel Mack (1): ASoC: pxa-ssp: drop SNDRV_PCM_FMTBIT_S24_LE Geert Uytterhoeven (1): ASoC: dapm: Fix uninitialized variable in snd_soc_dapm_get_enum_double() Jarkko Nikula (4): ASoC: Intel: Update Baytrail ADSP firmware name ASoC: Intel: Merge Baytrail ADSP suspend_noirq into suspend_late ASoC: Intel: Wait Baytrail ADSP boot at resume_early stage ASoC: Intel: Restore Baytrail ADSP streams only when ADSP was in reset Jyri Sarha (1): ASoC: mcasp: Fix implicit BLCK divider setting Mark Brown (8): MAINTAINERS: Add i.MX maintainers and paths to Freescale ASoC entry ASoC: pcm512x: Correct Digital Playback control names Merge tag 'asoc-v3.16-rc1' into asoc-linus Merge tag 'asoc-v3.16-rc5' into asoc-linus Merge tag 'asoc-v3.17' into asoc-linus Merge remote-tracking branch 'asoc/fix/dapm' into asoc-linus Merge remote-tracking branch 'asoc/fix/pcm512x' into asoc-linus Merge remote-tracking branches 'asoc/fix/arizona', 'asoc/fix/fsl', 'asoc/fix/fsl-esai', 'asoc/fix/intel', 'asoc/fix/mcasp' and 'asoc/fix/pxa' into asoc-linus Nikesh Oswal (1): ASoC: arizona: Fix TDM slot length handling in arizona_hw_params Shengjiu Wang (1): ASoC: fsl-esai: Revert .xlate_tdm_slot_mask() support MAINTAINERS | 3 +++ sound/soc/codecs/arizona.c | 6 ++++-- sound/soc/codecs/pcm512x.c | 4 ++-- sound/soc/davinci/davinci-mcasp.c | 14 ++++++++++--- sound/soc/fsl/Kconfig | 1 - sound/soc/fsl/fsl_esai.c | 2 -- sound/soc/intel/sst-acpi.c | 4 ++-- sound/soc/intel/sst-baytrail-ipc.c | 10 +-------- sound/soc/intel/sst-baytrail-ipc.h | 1 - sound/soc/intel/sst-baytrail-pcm.c | 43 +++++++++++++------------------------- sound/soc/pxa/pxa-ssp.c | 4 +--- sound/soc/soc-dapm.c | 12 ++++++----- 12 files changed, 46 insertions(+), 58 deletions(-)

2 1

[alsa-devel] [PATCH] ALSA: hda/realtek - Avoid setting wrong COEF on ALC269 & co
by Takashi Iwai 15 Aug '14

15 Aug '14

ALC269 & co have many vendor-specific setups with COEF verbs. However, some verbs seem specific to some codec versions and they result in the codec stalling. Typically, such a case can be avoided by checking the return value from reading a COEF. If the return value is -1, it implies that the COEF is invalid, thus it shouldn't be written. This patch adds the invalid COEF checks in appropriate places accessing ALC269 and its variants. The patch actually fixes the resume problem on Acer AO725 laptop. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=52181 Tested-by: Francesco Muzio <muziofg(a)gmail.com> Cc: <stable(a)vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_realtek.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 6b38ec3c6e57..b32ce086d2e0 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -181,6 +181,8 @@ static void alc_fix_pll(struct hda_codec *codec) spec->pll_coef_idx); val = snd_hda_codec_read(codec, spec->pll_nid, 0, AC_VERB_GET_PROC_COEF, 0); + if (val == -1) + return; snd_hda_codec_write(codec, spec->pll_nid, 0, AC_VERB_SET_COEF_INDEX, spec->pll_coef_idx); snd_hda_codec_write(codec, spec->pll_nid, 0, AC_VERB_SET_PROC_COEF, @@ -2806,6 +2808,8 @@ static void alc286_shutup(struct hda_codec *codec) static void alc269vb_toggle_power_output(struct hda_codec *codec, int power_up) { int val = alc_read_coef_idx(codec, 0x04); + if (val == -1) + return; if (power_up) val |= 1 << 11; else @@ -5311,27 +5315,30 @@ static void alc269_fill_coef(struct hda_codec *codec) if ((alc_get_coef0(codec) & 0x00ff) == 0x017) { val = alc_read_coef_idx(codec, 0x04); /* Power up output pin */ - alc_write_coef_idx(codec, 0x04, val | (1<<11)); + if (val != -1) + alc_write_coef_idx(codec, 0x04, val | (1<<11)); } if ((alc_get_coef0(codec) & 0x00ff) == 0x018) { val = alc_read_coef_idx(codec, 0xd); - if ((val & 0x0c00) >> 10 != 0x1) { + if (val != -1 && (val & 0x0c00) >> 10 != 0x1) { /* Capless ramp up clock control */ alc_write_coef_idx(codec, 0xd, val | (1<<10)); } val = alc_read_coef_idx(codec, 0x17); - if ((val & 0x01c0) >> 6 != 0x4) { + if (val != -1 && (val & 0x01c0) >> 6 != 0x4) { /* Class D power on reset */ alc_write_coef_idx(codec, 0x17, val | (1<<7)); } } val = alc_read_coef_idx(codec, 0xd); /* Class D */ - alc_write_coef_idx(codec, 0xd, val | (1<<14)); + if (val != -1) + alc_write_coef_idx(codec, 0xd, val | (1<<14)); val = alc_read_coef_idx(codec, 0x4); /* HP */ - alc_write_coef_idx(codec, 0x4, val | (1<<11)); + if (val != -1) + alc_write_coef_idx(codec, 0x4, val | (1<<11)); } /* -- 2.0.4

1 0

[alsa-devel] [PATCH] pcm: 2nd round of pcm_misc DSD fixes
by Jurgen Kramer 15 Aug '14

15 Aug '14

Functions 'snd_pcm_format_silence_64' and 'snd_pcm_format_size' also need to be able to handle the DSD formats. Signed-off-by: Jurgen Kramer <gtmkramer(a)xs4all.nl> --- src/pcm/pcm_misc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/pcm/pcm_misc.c b/src/pcm/pcm_misc.c index 24d52f9..c52e7bf 100644 --- a/src/pcm/pcm_misc.c +++ b/src/pcm/pcm_misc.c @@ -317,11 +317,13 @@ ssize_t snd_pcm_format_size(snd_pcm_format_t format, size_t samples) switch (format) { case SNDRV_PCM_FORMAT_S8: case SNDRV_PCM_FORMAT_U8: + case SNDRV_PCM_FORMAT_DSD_U8: return samples; case SNDRV_PCM_FORMAT_S16_LE: case SNDRV_PCM_FORMAT_S16_BE: case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_U16_BE: + case SNDRV_PCM_FORMAT_DSD_U16_LE: return samples * 2; case SNDRV_PCM_FORMAT_S18_3LE: case SNDRV_PCM_FORMAT_S18_3BE: @@ -387,6 +389,8 @@ u_int64_t snd_pcm_format_silence_64(snd_pcm_format_t format) case SNDRV_PCM_FORMAT_S20_3BE: case SNDRV_PCM_FORMAT_S18_3LE: case SNDRV_PCM_FORMAT_S18_3BE: + case SNDRV_PCM_FORMAT_DSD_U8: + case SNDRV_PCM_FORMAT_DSD_U16_LE: return 0; case SNDRV_PCM_FORMAT_U8: return 0x8080808080808080ULL; -- 1.9.3

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[alsa-devel] [PATCH v2] ASoC: tas2552: Add DAPM calls for amp and PLL
by Dan Murphy 15 Aug '14

15 Aug '14

Add DAPM calls to enable/disable the Class D amp. Also add a DAPM call to turn off the PLL upon the stream completing. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- v2 - Added proper audio routing map for ClassD and PLL enable/disable - https://patchwork.kernel.org/patch/4586831/ sound/soc/codecs/tas2552.c | 68 +++++++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 20 deletions(-) diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c index 23b3296..1ed57a7 100644 --- a/sound/soc/codecs/tas2552.c +++ b/sound/soc/codecs/tas2552.c @@ -78,6 +78,43 @@ struct tas2552_data { unsigned int mclk; }; +/* Input mux controls */ +static const char *tas2552_input_texts[] = { + "Digital", "Analog" +}; + +static SOC_ENUM_SINGLE_DECL(tas2552_input_mux_enum, TAS2552_CFG_3, 7, + tas2552_input_texts); + +static const struct snd_kcontrol_new tas2552_input_mux_control[] = { + SOC_DAPM_ENUM("Input selection", tas2552_input_mux_enum) +}; + +static const struct snd_soc_dapm_widget tas2552_dapm_widgets[] = +{ + SND_SOC_DAPM_INPUT("IN"), + + /* MUX Controls */ + SND_SOC_DAPM_MUX("Input selection", SND_SOC_NOPM, 0, 0, + tas2552_input_mux_control), + + SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_OUT_DRV("ClassD", TAS2552_CFG_2, 7, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL", TAS2552_CFG_2, 3, 0, NULL, 0), + + SND_SOC_DAPM_OUTPUT("OUT") +}; + +static const struct snd_soc_dapm_route tas2552_audio_map[] = { + {"DAC", NULL, "DAC IN"}, + {"Input selection", "Digital", "DAC"}, + {"Input selection", "Analog", "IN"}, + {"ClassD", NULL, "Input selection"}, + {"OUT", NULL, "ClassD"}, + {"ClassD", NULL, "PLL"}, +}; + static void tas2552_sw_shutdown(struct tas2552_data *tas_data, int sw_shutdown) { u8 cfg1_reg; @@ -101,10 +138,6 @@ static int tas2552_hw_params(struct snd_pcm_substream *substream, int d; u8 p, j; - /* Turn on Class D amplifier */ - snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_CLASSD_EN_MASK, - TAS2552_CLASSD_EN); - if (!tas2552->mclk) return -EINVAL; @@ -147,9 +180,6 @@ static int tas2552_hw_params(struct snd_pcm_substream *substream, } - snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, - TAS2552_PLL_ENABLE); - return 0; } @@ -269,19 +299,10 @@ static const struct dev_pm_ops tas2552_pm = { NULL) }; -static void tas2552_shutdown(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct snd_soc_codec *codec = dai->codec; - - snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0); -} - static struct snd_soc_dai_ops tas2552_speaker_dai_ops = { .hw_params = tas2552_hw_params, .set_sysclk = tas2552_set_dai_sysclk, .set_fmt = tas2552_set_dai_fmt, - .shutdown = tas2552_shutdown, .digital_mute = tas2552_mute, }; @@ -294,7 +315,7 @@ static struct snd_soc_dai_driver tas2552_dai[] = { { .name = "tas2552-amplifier", .playback = { - .stream_name = "Speaker", + .stream_name = "Playback", .channels_min = 2, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_192000, @@ -312,6 +333,7 @@ static DECLARE_TLV_DB_SCALE(dac_tlv, -7, 100, 24); static const struct snd_kcontrol_new tas2552_snd_controls[] = { SOC_SINGLE_TLV("Speaker Driver Playback Volume", TAS2552_PGA_GAIN, 0, 0x1f, 1, dac_tlv), + SOC_DAPM_SINGLE("Playback AMP", SND_SOC_NOPM, 0, 1, 0), }; static const struct reg_default tas2552_init_regs[] = { @@ -321,6 +343,7 @@ static const struct reg_default tas2552_init_regs[] = { static int tas2552_codec_probe(struct snd_soc_codec *codec) { struct tas2552_data *tas2552 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret; tas2552->codec = codec; @@ -362,9 +385,14 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec) goto patch_fail; } - snd_soc_write(codec, TAS2552_CFG_2, TAS2552_CLASSD_EN | - TAS2552_BOOST_EN | TAS2552_APT_EN | - TAS2552_LIM_EN); + snd_soc_write(codec, TAS2552_CFG_2, TAS2552_BOOST_EN | + TAS2552_APT_EN | TAS2552_LIM_EN); + + snd_soc_dapm_new_controls(dapm, tas2552_dapm_widgets, + ARRAY_SIZE(tas2552_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, tas2552_audio_map, + ARRAY_SIZE(tas2552_audio_map)); + return 0; patch_fail: -- 1.7.9.5

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[alsa-devel] [PATCH v3 00/14] Rework OMAP4+ HDMI audio support
by Jyri Sarha 14 Aug '14

14 Aug '14

Question to ASoC maintainers: Do feel it is Ok to put ASoC code outside sound/soc the way I do in these patches (in patch 0006 particularly)? The patches are based on: git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux.git for-next The base, the patches, and couple of additional not-to-be-merged omap2plus_defconfig patches can be found here: git://git.ti.com/~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-fe… omap-hdmi-audio Changes since v2 version of the patches: - Add "OMAPDSS: hdmi_common: hdmi_compute_acr is needed for OMAP5 HDMI audio too" - Fix "OMAPDSS: hdmi: Make hdmi structure public". There was no need to make "core"-member a pointer. - Make functional division between hdmi_audio.c and hdmi[45].c more clear. hdmi_audio.c does not touch anything but "audio"-member in omap_hdmi struct that is stored in drvdata. The patch set fixes OMAP4+ HDMI audio. The structure of the implementation looks a bit different than before. Instead of creating a driver specific API for a separate ASoC component driver to connect to, this implementation integrates an the ASoC cpu-dai component driver into the HDMI driver. Also the other ASoC component drivers needed for operational audio are automatically registered by the HDMI driver. There is no need to add anything to the device tree as long as the nodes needed for HDMI video are there. Big part of the HDMI audio code is still unchanged and there is a need for a cleanup there. Also there is still probably something wrong with speaker mapping of multi-channel streams. I will get back to cleaning up these issues later. Best regards, Jyri Jyri Sarha (14): ARM: OMAP2+: Remove non working OMAP HDMI audio initialization OMAPDSS: hdmi.h: Add HDMI_AUDIO_LAYOUT_6CH enum value OMAPDSS: hdmi_common: hdmi_compute_acr is needed for OMAP5 HDMI audio too OMAPDSS: hdmi_wp: Add function for getting audio dma address OMAPDSS: hdmi: Make hdmi structure public OMAPDSS: hdmi_audio: Integrated ASoC DAI component driver implementation OMAPDSS: Kconfig: Update OMAP4_DSS_HDMI_AUDIO option OMAPDSS: hdmi4: Register HDMI audio ASoC drivers from HDMI driver OMAPDSS: Kconfig: Update OMAP5_DSS_HDMI_AUDIO option OMAPDSS: hdmi5: Register HDMI audio ASoC drivers from HDMI driver ASoC: omap: Remove obsolete HDMI audio code and Kconfig options OMAPDSS: hdmi4: Remove callbacks for an external ASoC DAI driver OMAPDSS: hdmi5: Remove callbacks for an external ASoC DAI driver OMAPDSS: Remove all references to obsolete HDMI audio callbacks arch/arm/mach-omap2/devices.c | 28 -- .../fbdev/omap2/displays-new/connector-hdmi.c | 99 ------ .../fbdev/omap2/displays-new/encoder-tpd12s015.c | 56 --- drivers/video/fbdev/omap2/dss/Kconfig | 29 +- drivers/video/fbdev/omap2/dss/Makefile | 1 + drivers/video/fbdev/omap2/dss/hdmi.h | 61 +++- drivers/video/fbdev/omap2/dss/hdmi4.c | 231 +++++-------- drivers/video/fbdev/omap2/dss/hdmi5.c | 213 +++++------- drivers/video/fbdev/omap2/dss/hdmi_audio.c | 298 ++++++++++++++++ drivers/video/fbdev/omap2/dss/hdmi_common.c | 2 +- drivers/video/fbdev/omap2/dss/hdmi_wp.c | 6 + include/video/omapdss.h | 31 -- sound/soc/omap/Kconfig | 13 - sound/soc/omap/Makefile | 4 - sound/soc/omap/omap-hdmi-card.c | 87 ----- sound/soc/omap/omap-hdmi.c | 364 -------------------- sound/soc/omap/omap-hdmi.h | 38 -- 17 files changed, 567 insertions(+), 994 deletions(-) create mode 100644 drivers/video/fbdev/omap2/dss/hdmi_audio.c delete mode 100644 sound/soc/omap/omap-hdmi-card.c delete mode 100644 sound/soc/omap/omap-hdmi.c delete mode 100644 sound/soc/omap/omap-hdmi.h -- 1.7.9.5

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[alsa-devel] [PATCH] ASoC: rt286: Add API to set supported jack type
by bardliao＠realtek.com 14 Aug '14

14 Aug '14

From: Bard Liao <bardliao(a)realtek.com> RT286 need to configure the jack type (combo or non-combo) according to the HW design. This function is given a easy way to set the correct jacy type for those without platform data supported. Signed-off-by: Bard Liao <bardliao(a)realtek.com> --- sound/soc/codecs/rt286.c | 33 +++++++++++++++++++++++++++++++++ sound/soc/codecs/rt286.h | 7 +++++++ 2 files changed, 40 insertions(+) diff --git a/sound/soc/codecs/rt286.c b/sound/soc/codecs/rt286.c index e4f6102..dd6b454 100644 --- a/sound/soc/codecs/rt286.c +++ b/sound/soc/codecs/rt286.c @@ -414,6 +414,39 @@ int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) } EXPORT_SYMBOL_GPL(rt286_mic_detect); +/** + * rt286_set_jack_type - Configure the HW supported jack type + * + * @codec: RT286 codec + * @type: supported jack type + * + * RT286 need to configure the jack type (combo or non-combo) according to the + * HW design. This function is given a easy way to set the correct jacy type + * for those without platform data supported. + */ +void rt286_set_jack_type(struct snd_soc_codec *codec, + enum rt286_jack_type type) +{ + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + + if (RT286_TYPE_COMBO == type) + rt286->pdata.cbj_en = true; + else + rt286->pdata.cbj_en = false; + + if (!rt286->pdata.cbj_en) { + regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000); + regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816); + regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000); + regmap_update_bits(rt286->regmap, + RT286_CBJ_CTRL1, 0xf000, 0xb000); + } else { + regmap_update_bits(rt286->regmap, + RT286_CBJ_CTRL1, 0xf000, 0x5000); + } +} +EXPORT_SYMBOL_GPL(rt286_set_jack_type); + static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); diff --git a/sound/soc/codecs/rt286.h b/sound/soc/codecs/rt286.h index b539b73..2b1cbe6 100644 --- a/sound/soc/codecs/rt286.h +++ b/sound/soc/codecs/rt286.h @@ -192,7 +192,14 @@ enum { RT286_AIFS, }; +enum rt286_jack_type { + RT286_TYPE_COMBO, + RT286_TYPE_NONCOMBO, +}; + int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack); +void rt286_set_jack_type(struct snd_soc_codec *codec, + enum rt286_jack_type type); #endif /* __RT286_H__ */ -- 1.8.1.1.439.g50a6b54

4 7

[alsa-devel] A Minimal Playback Program does't work on my system
by Carpon frédéric 14 Aug '14

14 Aug '14

Hello, I am new System : Raspberry Linux: ArchLinuxArm I would like to run this exemple of A Minimal Playback Program from here : Howto use the ALSA API from the page Tutorials for application developers but there is a bug : i have done > pacman -sy > pacman -s alsa-utils to install the last alas-utils done gcc exemple.c -lasound (warning comes) and ./a.out my_file.wav and the result is : "AlSA lib pcm.2239:(and_pcm_open_noupdate) Unknown PCM my_file.wav " cannot open audio device my_file.wav (No such file or directory) Can you help me please ?

3 2

[alsa-devel] [PATCH 0/5] Introduce a managed function for gpio_request_array
by Himangi Saraogi 14 Aug '14

14 Aug '14

This patchset intoduces a new managed interface devm_gpio_request_array, adds it in the documentation and its declaration in the gpio.h include file. Some cases of gpio_request_array are changed to devm_gpio_request_array. Himangi Saraogi (5): gpiolib: devres: Introduce the function devm_request_gpio_array ASoC: wm1250-ev1: Use devm_gpio_request_array ASoC: pxa: Use devm_gpio_request_array ASoC: pxa: e800_wm9712: Introduce the use of devm_gpio_request_array ASoC: pxa/hx4700: Introduce the use of devm_gpio_request_array Documentation/driver-model/devres.txt | 1 + drivers/gpio/devres.c | 21 +++++++++++++++++++++ include/linux/gpio.h | 2 ++ sound/soc/codecs/wm1250-ev1.c | 24 +++++------------------- sound/soc/pxa/e740_wm9705.c | 9 +++------ sound/soc/pxa/e800_wm9712.c | 9 +++------ sound/soc/pxa/hx4700.c | 12 +++--------- 7 files changed, 38 insertions(+), 40 deletions(-) -- 1.9.1

6 16

[alsa-devel] [PATCH v6 3/6] clk: Move all drivers to use internal API
by Tomeu Vizoso 14 Aug '14

14 Aug '14

In preparation to change the public API to return a per-user clk structure, remove any usage of this public API from the clock implementations. The reason for having this in a separate commit from the one that introduces the implementation of the new functions is to separate the changes generated with Coccinelle from the rest, and keep the patches' size reasonable. Signed-off-by: Tomeu Vizoso <tomeu.vizoso(a)collabora.com> Tested-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> --- v6: * Re-run script on latest clk-next --- arch/arm/mach-dove/common.c | 10 +- arch/arm/mach-imx/clk-busy.c | 8 +- arch/arm/mach-imx/clk-fixup-div.c | 4 +- arch/arm/mach-imx/clk-fixup-mux.c | 4 +- arch/arm/mach-imx/clk-gate2.c | 4 +- arch/arm/mach-imx/clk-imx1.c | 2 +- arch/arm/mach-imx/clk-imx21.c | 2 +- arch/arm/mach-imx/clk-imx25.c | 8 +- arch/arm/mach-imx/clk-imx27.c | 4 +- arch/arm/mach-imx/clk-imx31.c | 10 +- arch/arm/mach-imx/clk-imx35.c | 22 +- arch/arm/mach-imx/clk-imx51-imx53.c | 77 +++--- arch/arm/mach-imx/clk-imx6q.c | 38 +-- arch/arm/mach-imx/clk-imx6sl.c | 13 +- arch/arm/mach-imx/clk-imx6sx.c | 97 ++++--- arch/arm/mach-imx/clk-pfd.c | 4 +- arch/arm/mach-imx/clk-pllv1.c | 4 +- arch/arm/mach-imx/clk-pllv2.c | 4 +- arch/arm/mach-imx/clk-pllv3.c | 4 +- arch/arm/mach-imx/clk-vf610.c | 42 +-- arch/arm/mach-imx/clk.c | 8 +- arch/arm/mach-imx/clk.h | 38 +-- arch/arm/mach-kirkwood/common.c | 22 +- arch/arm/mach-msm/clock-pcom.c | 2 +- arch/arm/mach-mv78xx0/common.c | 2 +- arch/arm/mach-omap2/cclock2420_data.c | 168 ++++++------ arch/arm/mach-omap2/cclock2430_data.c | 186 ++++++------- arch/arm/mach-omap2/cclock3xxx_data.c | 370 +++++++++++++------------- arch/arm/mach-omap2/clkt2xxx_dpll.c | 4 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 4 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 2 +- arch/arm/mach-omap2/clkt_clksel.c | 46 ++-- arch/arm/mach-omap2/clkt_dpll.c | 8 +- arch/arm/mach-omap2/clock.c | 52 ++-- arch/arm/mach-omap2/clock.h | 20 +- arch/arm/mach-omap2/clock3xxx.c | 22 +- arch/arm/mach-omap2/clock3xxx.h | 4 +- arch/arm/mach-omap2/clock_common_data.c | 2 +- arch/arm/mach-omap2/clockdomain.c | 8 +- arch/arm/mach-omap2/clockdomain.h | 4 +- arch/arm/mach-omap2/display.c | 4 +- arch/arm/mach-omap2/dpll3xxx.c | 28 +- arch/arm/mach-omap2/dpll44xx.c | 4 +- arch/arm/mach-omap2/mcbsp.c | 4 +- arch/arm/mach-omap2/omap_device.c | 8 +- arch/arm/mach-omap2/omap_hwmod.c | 42 +-- arch/arm/mach-omap2/omap_hwmod.h | 12 +- arch/arm/mach-omap2/pm24xx.c | 12 +- arch/arm/mach-orion5x/common.c | 2 +- arch/arm/plat-orion/common.c | 20 +- arch/arm/plat-orion/include/plat/common.h | 12 +- arch/powerpc/platforms/512x/clock-commonclk.c | 48 ++-- drivers/clk/at91/clk-main.c | 24 +- drivers/clk/at91/clk-master.c | 6 +- drivers/clk/at91/clk-peripheral.c | 12 +- drivers/clk/at91/clk-pll.c | 6 +- drivers/clk/at91/clk-plldiv.c | 6 +- drivers/clk/at91/clk-programmable.c | 10 +- drivers/clk/at91/clk-slow.c | 24 +- drivers/clk/at91/clk-smd.c | 6 +- drivers/clk/at91/clk-system.c | 6 +- drivers/clk/at91/clk-usb.c | 18 +- drivers/clk/at91/clk-utmi.c | 6 +- drivers/clk/bcm/clk-kona-setup.c | 6 +- drivers/clk/bcm/clk-kona.c | 12 +- drivers/clk/bcm/clk-kona.h | 2 +- drivers/clk/berlin/berlin2-avpll.c | 4 +- drivers/clk/berlin/berlin2-avpll.h | 4 +- drivers/clk/berlin/berlin2-div.c | 2 +- drivers/clk/berlin/berlin2-div.h | 2 +- drivers/clk/berlin/berlin2-pll.c | 2 +- drivers/clk/berlin/berlin2-pll.h | 2 +- drivers/clk/berlin/bg2.c | 12 +- drivers/clk/berlin/bg2q.c | 8 +- drivers/clk/clk-axi-clkgen.c | 2 +- drivers/clk/clk-axm5516.c | 4 +- drivers/clk/clk-bcm2835.c | 2 +- drivers/clk/clk-composite.c | 10 +- drivers/clk/clk-conf.c | 16 +- drivers/clk/clk-divider.c | 8 +- drivers/clk/clk-efm32gg.c | 2 +- drivers/clk/clk-fixed-factor.c | 6 +- drivers/clk/clk-fixed-rate.c | 8 +- drivers/clk/clk-fractional-divider.c | 4 +- drivers/clk/clk-gate.c | 4 +- drivers/clk/clk-highbank.c | 8 +- drivers/clk/clk-ls1x.c | 16 +- drivers/clk/clk-max77686.c | 10 +- drivers/clk/clk-moxart.c | 8 +- drivers/clk/clk-mux.c | 6 +- drivers/clk/clk-nomadik.c | 14 +- drivers/clk/clk-nspire.c | 4 +- drivers/clk/clk-ppc-corenet.c | 8 +- drivers/clk/clk-s2mps11.c | 6 +- drivers/clk/clk-si5351.c | 17 +- drivers/clk/clk-si570.c | 4 +- drivers/clk/clk-twl6040.c | 2 +- drivers/clk/clk-u300.c | 12 +- drivers/clk/clk-vt8500.c | 4 +- drivers/clk/clk-wm831x.c | 6 +- drivers/clk/clk-xgene.c | 12 +- drivers/clk/clk.h | 4 +- drivers/clk/hisilicon/clk-hi3620.c | 8 +- drivers/clk/hisilicon/clk.c | 16 +- drivers/clk/hisilicon/clk.h | 2 +- drivers/clk/hisilicon/clkgate-separated.c | 4 +- drivers/clk/keystone/gate.c | 6 +- drivers/clk/keystone/pll.c | 10 +- drivers/clk/mmp/clk-apbc.c | 4 +- drivers/clk/mmp/clk-apmu.c | 4 +- drivers/clk/mmp/clk-frac.c | 4 +- drivers/clk/mmp/clk-mmp2.c | 14 +- drivers/clk/mmp/clk-pxa168.c | 12 +- drivers/clk/mmp/clk-pxa910.c | 12 +- drivers/clk/mmp/clk.h | 8 +- drivers/clk/mvebu/clk-corediv.c | 4 +- drivers/clk/mvebu/clk-cpu.c | 8 +- drivers/clk/mvebu/common.c | 14 +- drivers/clk/mxs/clk-div.c | 4 +- drivers/clk/mxs/clk-frac.c | 4 +- drivers/clk/mxs/clk-imx23.c | 4 +- drivers/clk/mxs/clk-imx28.c | 4 +- drivers/clk/mxs/clk-pll.c | 4 +- drivers/clk/mxs/clk-ref.c | 4 +- drivers/clk/mxs/clk.h | 16 +- drivers/clk/qcom/clk-rcg.c | 8 +- drivers/clk/qcom/clk-rcg2.c | 14 +- drivers/clk/qcom/clk-regmap.c | 2 +- drivers/clk/qcom/clk-regmap.h | 2 +- drivers/clk/qcom/common.c | 6 +- drivers/clk/qcom/gcc-msm8660.c | 2 +- drivers/clk/qcom/gcc-msm8960.c | 2 +- drivers/clk/qcom/gcc-msm8974.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 6 +- drivers/clk/rockchip/clk-rockchip.c | 2 +- drivers/clk/samsung/clk-exynos-audss.c | 16 +- drivers/clk/samsung/clk-exynos4.c | 6 +- drivers/clk/samsung/clk-pll.c | 6 +- drivers/clk/samsung/clk-pll.h | 2 +- drivers/clk/samsung/clk-s3c2410-dclk.c | 10 +- drivers/clk/samsung/clk.c | 22 +- drivers/clk/samsung/clk.h | 2 +- drivers/clk/shmobile/clk-div6.c | 2 +- drivers/clk/shmobile/clk-emev2.c | 4 +- drivers/clk/shmobile/clk-mstp.c | 6 +- drivers/clk/shmobile/clk-r8a7740.c | 6 +- drivers/clk/shmobile/clk-r8a7779.c | 6 +- drivers/clk/shmobile/clk-rcar-gen2.c | 10 +- drivers/clk/shmobile/clk-rz.c | 6 +- drivers/clk/sirf/clk-atlas6.c | 2 +- drivers/clk/sirf/clk-common.c | 30 +-- drivers/clk/sirf/clk-prima2.c | 2 +- drivers/clk/socfpga/clk-gate.c | 2 +- drivers/clk/socfpga/clk-periph.c | 2 +- drivers/clk/socfpga/clk-pll.c | 4 +- drivers/clk/spear/clk-aux-synth.c | 8 +- drivers/clk/spear/clk-frac-synth.c | 4 +- drivers/clk/spear/clk-gpt-synth.c | 4 +- drivers/clk/spear/clk-vco-pll.c | 8 +- drivers/clk/spear/clk.h | 14 +- drivers/clk/spear/spear1310_clock.c | 2 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/clk/spear/spear3xx_clock.c | 16 +- drivers/clk/spear/spear6xx_clock.c | 2 +- drivers/clk/st/clkgen-fsyn.c | 22 +- drivers/clk/st/clkgen-mux.c | 32 +-- drivers/clk/st/clkgen-pll.c | 34 +-- drivers/clk/sunxi/clk-a10-hosc.c | 2 +- drivers/clk/sunxi/clk-a20-gmac.c | 2 +- drivers/clk/sunxi/clk-factors.c | 4 +- drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 2 +- drivers/clk/sunxi/clk-sun6i-apb0.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 6 +- drivers/clk/sunxi/clk-sunxi.c | 18 +- drivers/clk/tegra/clk-audio-sync.c | 4 +- drivers/clk/tegra/clk-divider.c | 4 +- drivers/clk/tegra/clk-periph-gate.c | 4 +- drivers/clk/tegra/clk-periph.c | 8 +- drivers/clk/tegra/clk-pll-out.c | 4 +- drivers/clk/tegra/clk-pll.c | 40 +-- drivers/clk/tegra/clk-super.c | 4 +- drivers/clk/tegra/clk-tegra-audio.c | 4 +- drivers/clk/tegra/clk-tegra-fixed.c | 8 +- drivers/clk/tegra/clk-tegra-periph.c | 12 +- drivers/clk/tegra/clk-tegra-pmc.c | 4 +- drivers/clk/tegra/clk-tegra-super-gen4.c | 8 +- drivers/clk/tegra/clk-tegra114.c | 10 +- drivers/clk/tegra/clk-tegra124.c | 6 +- drivers/clk/tegra/clk-tegra20.c | 12 +- drivers/clk/tegra/clk-tegra30.c | 8 +- drivers/clk/tegra/clk.c | 24 +- drivers/clk/tegra/clk.h | 38 +-- drivers/clk/ti/apll.c | 8 +- drivers/clk/ti/clk-2xxx.c | 8 +- drivers/clk/ti/clk-33xx.c | 18 +- drivers/clk/ti/clk-3xxx.c | 8 +- drivers/clk/ti/clk-43xx.c | 8 +- drivers/clk/ti/clk-44xx.c | 16 +- drivers/clk/ti/clk-54xx.c | 25 +- drivers/clk/ti/clk-7xx.c | 24 +- drivers/clk/ti/clk-dra7-atl.c | 6 +- drivers/clk/ti/clk.c | 2 +- drivers/clk/ti/clockdomain.c | 4 +- drivers/clk/ti/composite.c | 2 +- drivers/clk/ti/divider.c | 6 +- drivers/clk/ti/dpll.c | 8 +- drivers/clk/ti/fixed-factor.c | 2 +- drivers/clk/ti/gate.c | 2 +- drivers/clk/ti/interface.c | 2 +- drivers/clk/ti/mux.c | 6 +- drivers/clk/ux500/abx500-clk.c | 2 +- drivers/clk/ux500/clk-prcc.c | 8 +- drivers/clk/ux500/clk-prcmu.c | 16 +- drivers/clk/ux500/clk-sysctrl.c | 10 +- drivers/clk/ux500/clk.h | 22 +- drivers/clk/ux500/u8500_clk.c | 2 +- drivers/clk/ux500/u8500_of_clk.c | 12 +- drivers/clk/ux500/u8540_clk.c | 2 +- drivers/clk/versatile/clk-icst.c | 4 +- drivers/clk/versatile/clk-icst.h | 2 +- drivers/clk/versatile/clk-impd1.c | 18 +- drivers/clk/versatile/clk-integrator.c | 2 +- drivers/clk/versatile/clk-realview.c | 2 +- drivers/clk/versatile/clk-sp810.c | 30 ++- drivers/clk/versatile/clk-vexpress-osc.c | 2 +- drivers/clk/versatile/clk-vexpress.c | 6 +- drivers/clk/x86/clk-lpt.c | 2 +- drivers/clk/zynq/clkc.c | 22 +- drivers/clk/zynq/pll.c | 4 +- drivers/media/platform/exynos4-is/media-dev.c | 16 +- drivers/media/platform/exynos4-is/media-dev.h | 6 +- include/asm-generic/clkdev.h | 4 +- include/linux/clk/ti.h | 10 +- include/linux/clk/zynq.h | 2 +- include/linux/platform_data/si5351.h | 4 +- 236 files changed, 1538 insertions(+), 1501 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 0d1a892..4d95685 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -71,9 +71,9 @@ void __init dove_map_io(void) static int dove_tclk; static DEFINE_SPINLOCK(gating_lock); -static struct clk *tclk; +static struct clk_core *tclk; -static struct clk __init *dove_register_gate(const char *name, +static struct clk_core __init *dove_register_gate(const char *name, const char *parent, u8 bit_idx) { return clk_register_gate(NULL, name, parent, 0, @@ -83,9 +83,9 @@ static struct clk __init *dove_register_gate(const char *name, static void __init dove_clk_init(void) { - struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; - struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; - struct clk *xor0, *xor1, *ge, *gephy; + struct clk_core *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; + struct clk_core *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; + struct clk_core *xor0, *xor1, *ge, *gephy; tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, dove_tclk); diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c index 4bb1bc4..e4161ed 100644 --- a/arch/arm/mach-imx/clk-busy.c +++ b/arch/arm/mach-imx/clk-busy.c @@ -78,12 +78,12 @@ static struct clk_ops clk_busy_divider_ops = { .set_rate = clk_busy_divider_set_rate, }; -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift) { struct clk_busy_divider *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); @@ -152,12 +152,12 @@ static struct clk_ops clk_busy_mux_ops = { .set_parent = clk_busy_mux_set_parent, }; -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents) { struct clk_busy_mux *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c index 21db020..8a62bfd 100644 --- a/arch/arm/mach-imx/clk-fixup-div.c +++ b/arch/arm/mach-imx/clk-fixup-div.c @@ -92,12 +92,12 @@ static const struct clk_ops clk_fixup_div_ops = { .set_rate = clk_fixup_div_set_rate, }; -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)) { struct clk_fixup_div *fixup_div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c index 0d40b35..e29dc62 100644 --- a/arch/arm/mach-imx/clk-fixup-mux.c +++ b/arch/arm/mach-imx/clk-fixup-mux.c @@ -71,12 +71,12 @@ static const struct clk_ops clk_fixup_mux_ops = { .set_parent = clk_fixup_mux_set_parent, }; -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)) { struct clk_fixup_mux *fixup_mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 4ba587d..80f53d7 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -97,14 +97,14 @@ static struct clk_ops clk_gate2_ops = { .is_enabled = clk_gate2_is_enabled, }; -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) { struct clk_gate2 *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 7f739be..94b7cfa 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -50,7 +50,7 @@ enum imx1_clks { usbd_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; int __init mx1_clocks_init(unsigned long fref) { diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index bdc2e46..1fc76c5 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -62,7 +62,7 @@ enum imx21_clks { gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; /* * must be called very early to get information about the diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index ae578c0..3772eb1 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -89,7 +89,7 @@ enum mx25_clks { wdt_ipg, cko_div, cko_sel, cko, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static int __init __mx25_clocks_init(unsigned long osc_rate) { @@ -229,10 +229,10 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) pr_err("i.MX25 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - clk_prepare_enable(clk[emi_ahb]); + clk_provider_prepare_enable(clk[emi_ahb]); /* Clock source for gpt must be derived from AHB */ - clk_set_parent(clk[per5_sel], clk[ahb]); + clk_provider_set_parent(clk[per5_sel], clk[ahb]); clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); @@ -241,7 +241,7 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) * Let's initially set up CLKO parent as ipg, since this configuration * is used on some imx25 board designs to clock the audio codec. */ - clk_set_parent(clk[cko_sel], clk[ipg]); + clk_provider_set_parent(clk[cko_sel], clk[ipg]); return 0; } diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 317a662..071fe2b 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -86,7 +86,7 @@ enum mx27_clks { rtic_ahb_gate, mshc_baud_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; int __init mx27_clocks_init(unsigned long fref) @@ -278,7 +278,7 @@ int __init mx27_clocks_init(unsigned long fref) mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); - clk_prepare_enable(clk[emi_ahb_gate]); + clk_provider_prepare_enable(clk[emi_ahb_gate]); imx_print_silicon_rev("i.MX27", mx27_revision()); diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index 4a9de08..3db06ac 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -45,7 +45,7 @@ enum mx31_clks { gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; int __init mx31_clocks_init(unsigned long fref) @@ -180,11 +180,11 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); clk_register_clkdev(clk[iim_gate], "iim", NULL); - clk_set_parent(clk[csi], clk[upll]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[iim_gate]); + clk_provider_set_parent(clk[csi], clk[upll]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[iim_gate]); mx31_revision(); - clk_disable_unprepare(clk[iim_gate]); + clk_provider_disable_unprepare(clk[iim_gate]); mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index 71c86a2..4433d08 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -67,7 +67,7 @@ enum mx35_clks { gpu2d_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; int __init mx35_clocks_init(void) { @@ -100,7 +100,7 @@ int __init mx35_clocks_init(void) else clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); - if (clk_get_rate(clk[arm]) > 400000000) + if (clk_provider_get_rate(clk[arm]) > 400000000) hsp_div = hsp_div_532; else hsp_div = hsp_div_400; @@ -261,14 +261,14 @@ int __init mx35_clocks_init(void) clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); clk_register_clkdev(clk[admux_gate], "audmux", NULL); - clk_prepare_enable(clk[spba_gate]); - clk_prepare_enable(clk[gpio1_gate]); - clk_prepare_enable(clk[gpio2_gate]); - clk_prepare_enable(clk[gpio3_gate]); - clk_prepare_enable(clk[iim_gate]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[max_gate]); - clk_prepare_enable(clk[iomuxc_gate]); + clk_provider_prepare_enable(clk[spba_gate]); + clk_provider_prepare_enable(clk[gpio1_gate]); + clk_provider_prepare_enable(clk[gpio2_gate]); + clk_provider_prepare_enable(clk[gpio3_gate]); + clk_provider_prepare_enable(clk[iim_gate]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[max_gate]); + clk_provider_prepare_enable(clk[iomuxc_gate]); /* * SCC is needed to boot via mmc after a watchdog reset. The clock code @@ -276,7 +276,7 @@ int __init mx35_clocks_init(void) * handled here and not needed for mmc) and IIM (which is enabled * unconditionally above). */ - clk_prepare_enable(clk[scc_gate]); + clk_provider_prepare_enable(clk[scc_gate]); imx_print_silicon_rev("i.MX35", mx35_revision()); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 21d2b11..88894cd 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -83,7 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_ static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; -static struct clk *clk[IMX5_CLK_END]; +static struct clk_core *clk[IMX5_CLK_END]; static struct clk_onecell_data clk_data; static void __init mx5_clocks_common_init(unsigned long rate_ckil, @@ -298,26 +298,28 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1"); /* Set SDHC parents to be PLL2 */ - clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); - clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], + clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], + clk[IMX5_CLK_PLL2_SW]); /* move usb phy clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); - - clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); - clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_SPBA]); - clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); - clk_prepare_enable(clk[IMX5_CLK_TMAX1]); - clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ - clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ + clk_provider_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); + + clk_provider_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); + clk_provider_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_SPBA]); + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX1]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ } static void __init mx50_clocks_init(struct device_node *np) @@ -361,15 +363,15 @@ static void __init mx50_clocks_init(struct device_node *np) mx5_clocks_common_init(0, 0, 0, 0); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt")); } @@ -447,18 +449,19 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3"); /* set the usboh3 parent to pll2_sw */ - clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_USBOH3_SEL], + clk[IMX5_CLK_PLL2_SW]); /* set SDHC root clock to 166.25MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); /* System timer */ mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX51", mx51_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); /* * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no @@ -571,18 +574,18 @@ static void __init mx53_clocks_init(struct device_node *np) clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3"); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); /* move can bus clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); + clk_provider_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX53", mx53_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt")); } diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 8e795de..ccd1aa0 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -110,7 +110,7 @@ enum mx6q_clks { lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; static enum mx6q_clks const clks_init_on[] __initconst = { @@ -448,50 +448,50 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { - clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); - clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); } - clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); - clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); - clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); - clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); + clk_provider_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); + clk_provider_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); + clk_provider_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); + clk_provider_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, * We can not get the 100MHz from the pll2_pfd0_352m. * So choose pll2_pfd2_396m as enfc_sel's parent. */ - clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); + clk_provider_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); + clk_provider_prepare_enable(clk[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clk[usbphy1_gate]); - clk_prepare_enable(clk[usbphy2_gate]); + clk_provider_prepare_enable(clk[usbphy1_gate]); + clk_provider_prepare_enable(clk[usbphy2_gate]); } /* * Let's initially set up CLKO with OSC24M, since this configuration * is widely used by imx6q board designs to clock audio codec. */ - ret = clk_set_parent(clk[cko2_sel], clk[osc]); + ret = clk_provider_set_parent(clk[cko2_sel], clk[osc]); if (!ret) - ret = clk_set_parent(clk[cko], clk[cko2]); + ret = clk_provider_set_parent(clk[cko], clk[cko2]); if (ret) pr_warn("failed to set up CLKO: %d\n", ret); /* Audio-related clocks configuration */ - clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); + clk_provider_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) - clk_set_parent(clk[lvds1_sel], clk[sata_ref]); + clk_provider_set_parent(clk[lvds1_sel], clk[sata_ref]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index 5408ca7..29e5d3c 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -79,7 +79,7 @@ static struct clk_div_table video_div_table[] = { { } }; -static struct clk *clks[IMX6SL_CLK_END]; +static struct clk_core *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; static void __iomem *ccm_base; static void __iomem *anatop_base; @@ -361,7 +361,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); /* Ensure the AHB clk is at 132MHz. */ - ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); + ret = clk_provider_set_rate(clks[IMX6SL_CLK_AHB], 132000000); if (ret) pr_warn("%s: failed to set AHB clock rate %d!\n", __func__, ret); @@ -371,15 +371,16 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) * usecount and enabling/disabling of parent PLLs. */ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); } /* Audio-related clocks configuration */ - clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + clk_provider_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], + clks[IMX6SL_CLK_PLL3_PFD3]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 72f8902..81ee7f6 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -82,7 +82,7 @@ static const char *lvds_sels[] = { "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", }; -static struct clk *clks[IMX6SX_CLK_CLK_END]; +static struct clk_core *clks[IMX6SX_CLK_CLK_END]; static struct clk_onecell_data clk_data; static int const clks_init_on[] __initconst = { @@ -133,12 +133,14 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); - clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); + clks[IMX6SX_CLK_CKIL] = of_clk_provider_get_by_name(ccm_node, "ckil"); + clks[IMX6SX_CLK_OSC] = of_clk_provider_get_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); - clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); + clks[IMX6SX_CLK_IPP_DI0] = of_clk_provider_get_by_name(ccm_node, + "ipp_di0"); + clks[IMX6SX_CLK_IPP_DI1] = of_clk_provider_get_by_name(ccm_node, + "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); base = of_iomap(np, 0); @@ -455,65 +457,80 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); } /* Set the default 132MHz for EIM module */ - clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); + clk_provider_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); /* set parent clock for LCDIF1 pixel clock */ - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], + clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], + clks[IMX6SX_CLK_LCDIF1_PODF]); /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ - if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) pr_err("Failed to set pcie bus parent clk.\n"); - if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) pr_err("Failed to set pcie parent clk.\n"); /* * Init enet system AHB clock, set to 200Mhz * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB */ - clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]); - clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); - clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); - clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_SEL], + clks[IMX6SX_CLK_ENET_PODF]); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); /* Audio clocks */ - clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); - - clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); - - clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); - clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); - - clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); - - clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); + + clk_provider_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SSI1_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI2_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI3_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); + + clk_provider_set_parent(clks[IMX6SX_CLK_ESAI_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); /* Set parent clock for vadc */ - clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_parent(clks[IMX6SX_CLK_VID_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); /* default parent of can_sel clock is invalid, manually set it here */ - clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); + clk_provider_set_parent(clks[IMX6SX_CLK_CAN_SEL], + clks[IMX6SX_CLK_PLL3_60M]); /* Update gpu clock from default 528M to 720M */ - clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); - clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c index 0b0f6f6..8f7590a 100644 --- a/arch/arm/mach-imx/clk-pfd.c +++ b/arch/arm/mach-imx/clk-pfd.c @@ -128,11 +128,11 @@ static const struct clk_ops clk_pfd_ops = { .is_enabled = clk_pfd_is_enabled, }; -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_pfd *pfd; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index d21d14c..fbe33f3 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -97,11 +97,11 @@ static struct clk_ops clk_pllv1_ops = { .recalc_rate = clk_pllv1_recalc_rate, }; -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base) { struct clk_pllv1 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kmalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c index 20889d5..7882848 100644 --- a/arch/arm/mach-imx/clk-pllv2.c +++ b/arch/arm/mach-imx/clk-pllv2.c @@ -237,11 +237,11 @@ static struct clk_ops clk_pllv2_ops = { .set_rate = clk_pllv2_set_rate, }; -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base) { struct clk_pllv2 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index 6136405..3edcfdc 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -320,13 +320,13 @@ static const struct clk_ops clk_pllv3_enet_ops = { .recalc_rate = clk_pllv3_enet_recalc_rate, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) { struct clk_pllv3 *pll; const struct clk_ops *ops; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index 22dc3ee..b383e96 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -95,7 +95,7 @@ static struct clk_div_table pll4_main_div_table[] = { { } }; -static struct clk *clk[VF610_CLK_END]; +static struct clk_core *clk[VF610_CLK_END]; static struct clk_onecell_data clk_data; static void __init vf610_clocks_init(struct device_node *ccm_node) @@ -303,20 +303,32 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); - clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_QSPI0_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_QSPI1_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_SAI0_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI1_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI2_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI3_SEL], + clk[VF610_CLK_AUDIO_EXT]); /* Add the clocks to provider list */ clk_data.clks = clk; diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index edc35df..d776fe1 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c @@ -7,10 +7,10 @@ DEFINE_SPINLOCK(imx_ccm_lock); -static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) +static struct clk_core * __init imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; - struct clk *clk = ERR_PTR(-ENODEV); + struct clk_core *clk = ERR_PTR(-ENODEV); char *path; path = kasprintf(GFP_KERNEL, "/clocks/%s", name); @@ -27,10 +27,10 @@ static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) return clk; } -struct clk * __init imx_obtain_fixed_clock( +struct clk_core * __init imx_obtain_fixed_clock( const char *name, unsigned long rate) { - struct clk *clk; + struct clk_core *clk; clk = imx_obtain_fixed_clock_from_dt(name); if (IS_ERR(clk)) diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index e29f6eb..421af46 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -8,10 +8,10 @@ extern spinlock_t imx_ccm_lock; extern void imx_cscmr1_fixup(u32 *val); -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base); enum imx_pllv3_type { @@ -22,26 +22,26 @@ enum imx_pllv3_type { IMX_PLLV3_ENET, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); -struct clk * imx_obtain_fixed_clock( +struct clk_core * imx_obtain_fixed_clock( const char *name, unsigned long rate); -static inline struct clk *imx_clk_gate2(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock, NULL); } -static inline struct clk *imx_clk_gate2_shared(const char *name, +static inline struct clk_core *imx_clk_gate2_shared(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) { @@ -49,38 +49,38 @@ static inline struct clk *imx_clk_gate2_shared(const char *name, shift, 0, &imx_ccm_lock, share_count); } -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift); -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents); -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)); -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)); -static inline struct clk *imx_clk_fixed(const char *name, int rate) +static inline struct clk_core *imx_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *imx_clk_divider(const char *name, const char *parent, +static inline struct clk_core *imx_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_divider_flags(const char *name, +static inline struct clk_core *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) { @@ -88,14 +88,14 @@ static inline struct clk *imx_clk_divider_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_gate(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { return clk_register_mux(NULL, name, parents, num_parents, @@ -103,7 +103,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux_flags(const char *name, +static inline struct clk_core *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, unsigned long flags) { @@ -112,7 +112,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } -static inline struct clk *imx_clk_fixed_factor(const char *name, +static inline struct clk_core *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent, diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 255f33a..b87a92e 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -159,7 +159,7 @@ static void clk_gate_fn_disable(struct clk_hw *hw) static struct clk_ops clk_gate_fn_ops; -static struct clk __init *clk_register_gate_fn(struct device *dev, +static struct clk_core __init *clk_register_gate_fn(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, @@ -167,7 +167,7 @@ static struct clk __init *clk_register_gate_fn(struct device *dev, void (*fn_en)(void), void (*fn_dis)(void)) { struct clk_gate_fn *gate_fn; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL); @@ -208,15 +208,15 @@ static struct clk __init *clk_register_gate_fn(struct device *dev, } static DEFINE_SPINLOCK(gating_lock); -static struct clk *tclk; +static struct clk_core *tclk; -static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) +static struct clk_core __init *kirkwood_register_gate(const char *name, u8 bit_idx) { return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, bit_idx, 0, &gating_lock); } -static struct clk __init *kirkwood_register_gate_fn(const char *name, +static struct clk_core __init *kirkwood_register_gate_fn(const char *name, u8 bit_idx, void (*fn_en)(void), void (*fn_dis)(void)) @@ -225,12 +225,12 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name, bit_idx, 0, &gating_lock, fn_en, fn_dis); } -static struct clk *ge0, *ge1; +static struct clk_core *ge0, *ge1; void __init kirkwood_clk_init(void) { - struct clk *runit, *sata0, *sata1, *usb0, *sdio; - struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio; + struct clk_core *runit, *sata0, *sata1, *usb0, *sdio; + struct clk_core *crypto, *xor0, *xor1, *pex0, *pex1, *audio; tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, kirkwood_tclk); @@ -278,7 +278,7 @@ void __init kirkwood_clk_init(void) /* Marvell says runit is used by SPI, UART, NAND, TWSI, ..., * so should never be gated. */ - clk_prepare_enable(runit); + clk_provider_prepare_enable(runit); } /***************************************************************************** @@ -300,7 +300,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) IRQ_KIRKWOOD_GE00_ERR, 1600); /* The interface forgets the MAC address assigned by u-boot if the clock is turned off, so claim the clk now. */ - clk_prepare_enable(ge0); + clk_provider_prepare_enable(ge0); } @@ -312,7 +312,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, IRQ_KIRKWOOD_GE01_ERR, 1600); - clk_prepare_enable(ge1); + clk_provider_prepare_enable(ge1); } diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index 9a80449..14352c4 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -132,7 +132,7 @@ static int msm_clock_pcom_probe(struct platform_device *pdev) for (i = 0; i < pdata->num_lookups; i++) { const struct clk_pcom_desc *desc = &pdata->lookup[i]; - struct clk *c; + struct clk_core *c; struct clk_pcom *p; struct clk_hw *hw; struct clk_init_data init; diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index e6ac679..fee2643 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -164,7 +164,7 @@ void __init mv78xx0_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; static void __init clk_init(void) { diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 3662f4d..59d6323 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -57,7 +57,7 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +static struct clk_core osc_ck; static const struct clk_ops osc_ck_ops = { .recalc_rate = &omap2_osc_clk_recalc, @@ -69,7 +69,7 @@ static struct clk_hw_omap osc_ck_hw = { }, }; -static struct clk osc_ck = { +static struct clk_core osc_ck = { .name = "osc_ck", .ops = &osc_ck_ops, .hw = &osc_ck_hw.hw, @@ -78,7 +78,7 @@ static struct clk osc_ck = { DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +static struct clk_core sys_ck; static const char *sys_ck_parent_names[] = { "osc_ck", @@ -105,7 +105,7 @@ static struct dpll_data dpll_dd = { .max_divider = 16, }; -static struct clk dpll_ck; +static struct clk_core dpll_ck; static const char *dpll_ck_parent_names[] = { "sys_ck", @@ -130,7 +130,7 @@ static struct clk_hw_omap dpll_ck_hw = { DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll_ck", @@ -153,7 +153,7 @@ DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk aes_ick; +static struct clk_core aes_ick; static const char *aes_ick_parent_names[] = { "l4_ck", @@ -178,7 +178,7 @@ static struct clk_hw_omap aes_ick_hw = { DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk apll54_ck; +static struct clk_core apll54_ck; static const struct clk_ops apll54_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -200,7 +200,7 @@ static struct clk_hw_omap apll54_ck_hw = { DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); -static struct clk apll96_ck; +static struct clk_core apll96_ck; static const struct clk_ops apll96_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -222,7 +222,7 @@ static struct clk_hw_omap apll96_ck_hw = { DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); -static struct clk func_96m_ck; +static struct clk_core func_96m_ck; static const char *func_96m_ck_parent_names[] = { "apll96_ck", @@ -231,7 +231,7 @@ static const char *func_96m_ck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); -static struct clk cam_fck; +static struct clk_core cam_fck; static const char *cam_fck_parent_names[] = { "func_96m_ck", @@ -248,7 +248,7 @@ static struct clk_hw_omap cam_fck_hw = { DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -262,7 +262,7 @@ static struct clk_hw_omap cam_ick_hw = { DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk des_ick; +static struct clk_core des_ick; static struct clk_hw_omap des_ick_hw = { .hw = { @@ -358,7 +358,7 @@ static const char *dss1_fck_parent_names[] = { "sys_ck", "core_ck", }; -static struct clk dss1_fck; +static struct clk_core dss1_fck; static const struct clk_ops dss1_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -407,7 +407,7 @@ static const char *func_48m_ck_parent_names[] = { "apll96_ck", "alt_ck", }; -static struct clk func_48m_ck; +static struct clk_core func_48m_ck; static const struct clk_ops func_48m_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -456,7 +456,7 @@ DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); -static struct clk dss_54m_fck; +static struct clk_core dss_54m_fck; static const char *dss_54m_fck_parent_names[] = { "func_54m_ck", @@ -474,7 +474,7 @@ static struct clk_hw_omap dss_54m_fck_hw = { DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); -static struct clk dss_ick; +static struct clk_core dss_ick; static struct clk_hw_omap dss_ick_hw = { .hw = { @@ -488,7 +488,7 @@ static struct clk_hw_omap dss_ick_hw = { DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk eac_fck; +static struct clk_core eac_fck; static struct clk_hw_omap eac_fck_hw = { .hw = { @@ -502,7 +502,7 @@ static struct clk_hw_omap eac_fck_hw = { DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk eac_ick; +static struct clk_core eac_ick; static struct clk_hw_omap eac_ick_hw = { .hw = { @@ -516,7 +516,7 @@ static struct clk_hw_omap eac_ick_hw = { DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk emul_ck; +static struct clk_core emul_ck; static struct clk_hw_omap emul_ck_hw = { .hw = { @@ -531,7 +531,7 @@ DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); -static struct clk fac_fck; +static struct clk_core fac_fck; static const char *fac_fck_parent_names[] = { "func_12m_ck", @@ -549,7 +549,7 @@ static struct clk_hw_omap fac_fck_hw = { DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -586,7 +586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, gfx_2d_fck_parent_names, dsp_fck_ops); -static struct clk gfx_ick; +static struct clk_core gfx_ick; static const char *gfx_ick_parent_names[] = { "core_l3_ck", @@ -604,7 +604,7 @@ static struct clk_hw_omap gfx_ick_hw = { DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk gpios_fck; +static struct clk_core gpios_fck; static const char *gpios_fck_parent_names[] = { "func_32k_ck", @@ -622,7 +622,7 @@ static struct clk_hw_omap gpios_fck_hw = { DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk gpios_ick; +static struct clk_core gpios_ick; static const char *gpios_ick_parent_names[] = { "sys_ck", @@ -640,7 +640,7 @@ static struct clk_hw_omap gpios_ick_hw = { DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -678,7 +678,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -699,7 +699,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -720,7 +720,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -753,7 +753,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, gpt1_fck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -774,7 +774,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -795,7 +795,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -816,7 +816,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -837,7 +837,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -858,7 +858,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -879,7 +879,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -900,7 +900,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -921,7 +921,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -935,7 +935,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static struct clk_hw_omap hdq_fck_hw = { .hw = { @@ -949,7 +949,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -963,7 +963,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c1_fck; +static struct clk_core i2c1_fck; static struct clk_hw_omap i2c1_fck_hw = { .hw = { @@ -977,7 +977,7 @@ static struct clk_hw_omap i2c1_fck_hw = { DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -991,7 +991,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c2_fck; +static struct clk_core i2c2_fck; static struct clk_hw_omap i2c2_fck_hw = { .hw = { @@ -1005,7 +1005,7 @@ static struct clk_hw_omap i2c2_fck_hw = { DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -1026,7 +1026,7 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, dsp_fck_parent_names, dsp_fck_ops); -static struct clk iva1_mpu_int_ifck; +static struct clk_core iva1_mpu_int_ifck; static const char *iva1_mpu_int_ifck_parent_names[] = { "iva1_ifck", @@ -1054,7 +1054,7 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = { DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, iva1_mpu_int_ifck_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -1095,7 +1095,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -1116,7 +1116,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -1130,7 +1130,7 @@ static struct clk_hw_omap mcbsp2_ick_hw = { DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static const char *mcspi1_fck_parent_names[] = { "func_48m_ck", @@ -1148,7 +1148,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -1162,7 +1162,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -1176,7 +1176,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -1190,7 +1190,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mmc_fck; +static struct clk_core mmc_fck; static struct clk_hw_omap mmc_fck_hw = { .hw = { @@ -1204,7 +1204,7 @@ static struct clk_hw_omap mmc_fck_hw = { DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mmc_ick; +static struct clk_core mmc_ick; static struct clk_hw_omap mmc_ick_hw = { .hw = { @@ -1223,7 +1223,7 @@ DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_wdt_fck; +static struct clk_core mpu_wdt_fck; static struct clk_hw_omap mpu_wdt_fck_hw = { .hw = { @@ -1237,7 +1237,7 @@ static struct clk_hw_omap mpu_wdt_fck_hw = { DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk mpu_wdt_ick; +static struct clk_core mpu_wdt_ick; static struct clk_hw_omap mpu_wdt_ick_hw = { .hw = { @@ -1251,7 +1251,7 @@ static struct clk_hw_omap mpu_wdt_ick_hw = { DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -1265,7 +1265,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -1279,7 +1279,7 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -1294,7 +1294,7 @@ static struct clk_hw_omap omapctrl_ick_hw = { DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static struct clk_hw_omap pka_ick_hw = { .hw = { @@ -1308,7 +1308,7 @@ static struct clk_hw_omap pka_ick_hw = { DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -1322,12 +1322,12 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk sdma_fck; +static struct clk_core sdma_fck; DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); -static struct clk sdma_ick; +static struct clk_core sdma_ick; static struct clk_hw_omap sdma_ick_hw = { .hw = { @@ -1341,7 +1341,7 @@ static struct clk_hw_omap sdma_ick_hw = { DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -1356,7 +1356,7 @@ static struct clk_hw_omap sdrc_ick_hw = { DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sha_ick; +static struct clk_core sha_ick; static struct clk_hw_omap sha_ick_hw = { .hw = { @@ -1370,7 +1370,7 @@ static struct clk_hw_omap sha_ick_hw = { DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; static struct clk_hw_omap ssi_l4_ick_hw = { .hw = { @@ -1411,7 +1411,7 @@ DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, ssi_ssr_sst_fck_parent_names, dsp_fck_ops); -static struct clk sync_32k_ick; +static struct clk_core sync_32k_ick; static struct clk_hw_omap sync_32k_ick_hw = { .hw = { @@ -1477,7 +1477,7 @@ DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -1491,7 +1491,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -1505,7 +1505,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -1519,7 +1519,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -1533,7 +1533,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static struct clk_hw_omap uart3_fck_hw = { .hw = { @@ -1547,7 +1547,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -1561,7 +1561,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk usb_fck; +static struct clk_core usb_fck; static struct clk_hw_omap usb_fck_hw = { .hw = { @@ -1598,7 +1598,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, usb_l4_ick_parent_names, dsp_fck_ops); -static struct clk virt_prcm_set; +static struct clk_core virt_prcm_set; static const char *virt_prcm_set_parent_names[] = { "mpu_ck", @@ -1649,7 +1649,7 @@ DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, vlynq_fck_parent_names, dss1_fck_ops); -static struct clk vlynq_ick; +static struct clk_core vlynq_ick; static struct clk_hw_omap vlynq_ick_hw = { .hw = { @@ -1663,7 +1663,7 @@ static struct clk_hw_omap vlynq_ick_hw = { DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -1677,7 +1677,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk wdt3_fck; +static struct clk_core wdt3_fck; static struct clk_hw_omap wdt3_fck_hw = { .hw = { @@ -1691,7 +1691,7 @@ static struct clk_hw_omap wdt3_fck_hw = { DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk wdt3_ick; +static struct clk_core wdt3_ick; static struct clk_hw_omap wdt3_ick_hw = { .hw = { @@ -1705,7 +1705,7 @@ static struct clk_hw_omap wdt3_ick_hw = { DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk wdt4_fck; +static struct clk_core wdt4_fck; static struct clk_hw_omap wdt4_fck_hw = { .hw = { @@ -1719,7 +1719,7 @@ static struct clk_hw_omap wdt4_fck_hw = { DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk wdt4_ick; +static struct clk_core wdt4_ick; static struct clk_hw_omap wdt4_ick_hw = { .hw = { @@ -1922,10 +1922,10 @@ int __init omap2420_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); + (clk_provider_get_rate(&sys_ck) / 1000000), + (clk_provider_get_rate(&sys_ck) / 100000) % 10, + (clk_provider_get_rate(&dpll_ck) / 1000000), + (clk_provider_get_rate(&mpu_ck) / 1000000)); return 0; } diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index 5e4b037..19d0361 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -55,7 +55,7 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +static struct clk_core osc_ck; static const struct clk_ops osc_ck_ops = { .enable = &omap2_enable_osc_ck, @@ -69,7 +69,7 @@ static struct clk_hw_omap osc_ck_hw = { }, }; -static struct clk osc_ck = { +static struct clk_core osc_ck = { .name = "osc_ck", .ops = &osc_ck_ops, .hw = &osc_ck_hw.hw, @@ -78,7 +78,7 @@ static struct clk osc_ck = { DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +static struct clk_core sys_ck; static const char *sys_ck_parent_names[] = { "osc_ck", @@ -105,7 +105,7 @@ static struct dpll_data dpll_dd = { .max_divider = 16, }; -static struct clk dpll_ck; +static struct clk_core dpll_ck; static const char *dpll_ck_parent_names[] = { "sys_ck", @@ -130,7 +130,7 @@ static struct clk_hw_omap dpll_ck_hw = { DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll_ck", @@ -153,7 +153,7 @@ DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk aes_ick; +static struct clk_core aes_ick; static const char *aes_ick_parent_names[] = { "l4_ck", @@ -178,7 +178,7 @@ static struct clk_hw_omap aes_ick_hw = { DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk apll54_ck; +static struct clk_core apll54_ck; static const struct clk_ops apll54_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -200,7 +200,7 @@ static struct clk_hw_omap apll54_ck_hw = { DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); -static struct clk apll96_ck; +static struct clk_core apll96_ck; static const struct clk_ops apll96_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -230,7 +230,7 @@ DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); -static struct clk cam_fck; +static struct clk_core cam_fck; static const char *cam_fck_parent_names[] = { "func_96m_ck", @@ -247,7 +247,7 @@ static struct clk_hw_omap cam_fck_hw = { DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -261,7 +261,7 @@ static struct clk_hw_omap cam_ick_hw = { DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk des_ick; +static struct clk_core des_ick; static struct clk_hw_omap des_ick_hw = { .hw = { @@ -292,7 +292,7 @@ static const char *dsp_fck_parent_names[] = { "core_ck", }; -static struct clk dsp_fck; +static struct clk_core dsp_fck; static const struct clk_ops dsp_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -387,7 +387,7 @@ static const char *func_48m_ck_parent_names[] = { "apll96_ck", "alt_ck", }; -static struct clk func_48m_ck; +static struct clk_core func_48m_ck; static const struct clk_ops func_48m_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -435,7 +435,7 @@ DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); -static struct clk dss_54m_fck; +static struct clk_core dss_54m_fck; static const char *dss_54m_fck_parent_names[] = { "func_54m_ck", @@ -453,7 +453,7 @@ static struct clk_hw_omap dss_54m_fck_hw = { DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); -static struct clk dss_ick; +static struct clk_core dss_ick; static struct clk_hw_omap dss_ick_hw = { .hw = { @@ -467,7 +467,7 @@ static struct clk_hw_omap dss_ick_hw = { DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk emul_ck; +static struct clk_core emul_ck; static struct clk_hw_omap emul_ck_hw = { .hw = { @@ -482,7 +482,7 @@ DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); -static struct clk fac_fck; +static struct clk_core fac_fck; static const char *fac_fck_parent_names[] = { "func_12m_ck", @@ -500,7 +500,7 @@ static struct clk_hw_omap fac_fck_hw = { DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -537,7 +537,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, gfx_2d_fck_parent_names, dsp_fck_ops); -static struct clk gfx_ick; +static struct clk_core gfx_ick; static const char *gfx_ick_parent_names[] = { "core_l3_ck", @@ -555,7 +555,7 @@ static struct clk_hw_omap gfx_ick_hw = { DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk gpio5_fck; +static struct clk_core gpio5_fck; static const char *gpio5_fck_parent_names[] = { "func_32k_ck", @@ -573,7 +573,7 @@ static struct clk_hw_omap gpio5_fck_hw = { DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk gpio5_ick; +static struct clk_core gpio5_ick; static struct clk_hw_omap gpio5_ick_hw = { .hw = { @@ -587,7 +587,7 @@ static struct clk_hw_omap gpio5_ick_hw = { DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk gpios_fck; +static struct clk_core gpios_fck; static struct clk_hw_omap gpios_fck_hw = { .hw = { @@ -601,7 +601,7 @@ static struct clk_hw_omap gpios_fck_hw = { DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk gpios_ick; +static struct clk_core gpios_ick; static const char *gpios_ick_parent_names[] = { "sys_ck", @@ -619,7 +619,7 @@ static struct clk_hw_omap gpios_ick_hw = { DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -657,7 +657,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -678,7 +678,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -699,7 +699,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -732,7 +732,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, gpt1_fck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -753,7 +753,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -774,7 +774,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -795,7 +795,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -816,7 +816,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -837,7 +837,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -858,7 +858,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -872,7 +872,7 @@ static struct clk_hw_omap gpt7_ick_hw = { DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk gpt8_fck; +static struct clk_core gpt8_fck; DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), @@ -881,7 +881,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -902,7 +902,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -916,7 +916,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static struct clk_hw_omap hdq_fck_hw = { .hw = { @@ -930,7 +930,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -944,7 +944,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -958,7 +958,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -972,7 +972,7 @@ static struct clk_hw_omap i2c2_ick_hw = { DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2chs1_fck; +static struct clk_core i2chs1_fck; static struct clk_hw_omap i2chs1_fck_hw = { .hw = { @@ -986,7 +986,7 @@ static struct clk_hw_omap i2chs1_fck_hw = { DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk i2chs2_fck; +static struct clk_core i2chs2_fck; static struct clk_hw_omap i2chs2_fck_hw = { .hw = { @@ -1000,7 +1000,7 @@ static struct clk_hw_omap i2chs2_fck_hw = { DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk icr_ick; +static struct clk_core icr_ick; static struct clk_hw_omap icr_ick_hw = { .hw = { @@ -1030,7 +1030,7 @@ DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, iva2_1_ick_parent_names, dsp_fck_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -1071,7 +1071,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -1092,7 +1092,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -1113,7 +1113,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp3_ick; +static struct clk_core mcbsp3_ick; static struct clk_hw_omap mcbsp3_ick_hw = { .hw = { @@ -1134,7 +1134,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp4_ick; +static struct clk_core mcbsp4_ick; static struct clk_hw_omap mcbsp4_ick_hw = { .hw = { @@ -1155,7 +1155,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp5_ick; +static struct clk_core mcbsp5_ick; static struct clk_hw_omap mcbsp5_ick_hw = { .hw = { @@ -1169,7 +1169,7 @@ static struct clk_hw_omap mcbsp5_ick_hw = { DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static const char *mcspi1_fck_parent_names[] = { "func_48m_ck", @@ -1187,7 +1187,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -1201,7 +1201,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -1215,7 +1215,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -1229,7 +1229,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi3_fck; +static struct clk_core mcspi3_fck; static struct clk_hw_omap mcspi3_fck_hw = { .hw = { @@ -1243,7 +1243,7 @@ static struct clk_hw_omap mcspi3_fck_hw = { DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi3_ick; +static struct clk_core mcspi3_ick; static struct clk_hw_omap mcspi3_ick_hw = { .hw = { @@ -1282,7 +1282,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, &clkhwops_iclk_wait, mdm_ick_parent_names, dsp_fck_ops); -static struct clk mdm_intc_ick; +static struct clk_core mdm_intc_ick; static struct clk_hw_omap mdm_intc_ick_hw = { .hw = { @@ -1296,7 +1296,7 @@ static struct clk_hw_omap mdm_intc_ick_hw = { DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mdm_osc_ck; +static struct clk_core mdm_osc_ck; static struct clk_hw_omap mdm_osc_ck_hw = { .hw = { @@ -1310,7 +1310,7 @@ static struct clk_hw_omap mdm_osc_ck_hw = { DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); -static struct clk mmchs1_fck; +static struct clk_core mmchs1_fck; static struct clk_hw_omap mmchs1_fck_hw = { .hw = { @@ -1324,7 +1324,7 @@ static struct clk_hw_omap mmchs1_fck_hw = { DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mmchs1_ick; +static struct clk_core mmchs1_ick; static struct clk_hw_omap mmchs1_ick_hw = { .hw = { @@ -1338,7 +1338,7 @@ static struct clk_hw_omap mmchs1_ick_hw = { DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mmchs2_fck; +static struct clk_core mmchs2_fck; static struct clk_hw_omap mmchs2_fck_hw = { .hw = { @@ -1352,7 +1352,7 @@ static struct clk_hw_omap mmchs2_fck_hw = { DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mmchs2_ick; +static struct clk_core mmchs2_ick; static struct clk_hw_omap mmchs2_ick_hw = { .hw = { @@ -1366,7 +1366,7 @@ static struct clk_hw_omap mmchs2_ick_hw = { DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mmchsdb1_fck; +static struct clk_core mmchsdb1_fck; static struct clk_hw_omap mmchsdb1_fck_hw = { .hw = { @@ -1380,7 +1380,7 @@ static struct clk_hw_omap mmchsdb1_fck_hw = { DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk mmchsdb2_fck; +static struct clk_core mmchsdb2_fck; static struct clk_hw_omap mmchsdb2_fck_hw = { .hw = { @@ -1399,7 +1399,7 @@ DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_wdt_fck; +static struct clk_core mpu_wdt_fck; static struct clk_hw_omap mpu_wdt_fck_hw = { .hw = { @@ -1413,7 +1413,7 @@ static struct clk_hw_omap mpu_wdt_fck_hw = { DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk mpu_wdt_ick; +static struct clk_core mpu_wdt_ick; static struct clk_hw_omap mpu_wdt_ick_hw = { .hw = { @@ -1427,7 +1427,7 @@ static struct clk_hw_omap mpu_wdt_ick_hw = { DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -1441,7 +1441,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -1455,7 +1455,7 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -1470,7 +1470,7 @@ static struct clk_hw_omap omapctrl_ick_hw = { DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static struct clk_hw_omap pka_ick_hw = { .hw = { @@ -1484,7 +1484,7 @@ static struct clk_hw_omap pka_ick_hw = { DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -1498,12 +1498,12 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk sdma_fck; +static struct clk_core sdma_fck; DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); -static struct clk sdma_ick; +static struct clk_core sdma_ick; static struct clk_hw_omap sdma_ick_hw = { .hw = { @@ -1517,7 +1517,7 @@ static struct clk_hw_omap sdma_ick_hw = { DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -1532,7 +1532,7 @@ static struct clk_hw_omap sdrc_ick_hw = { DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sha_ick; +static struct clk_core sha_ick; static struct clk_hw_omap sha_ick_hw = { .hw = { @@ -1546,7 +1546,7 @@ static struct clk_hw_omap sha_ick_hw = { DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; static struct clk_hw_omap ssi_l4_ick_hw = { .hw = { @@ -1586,7 +1586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, ssi_ssr_sst_fck_parent_names, dsp_fck_ops); -static struct clk sync_32k_ick; +static struct clk_core sync_32k_ick; static struct clk_hw_omap sync_32k_ick_hw = { .hw = { @@ -1642,7 +1642,7 @@ DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -1656,7 +1656,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -1670,7 +1670,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -1684,7 +1684,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -1698,7 +1698,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static struct clk_hw_omap uart3_fck_hw = { .hw = { @@ -1712,7 +1712,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -1726,7 +1726,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk usb_fck; +static struct clk_core usb_fck; static struct clk_hw_omap usb_fck_hw = { .hw = { @@ -1763,7 +1763,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, usb_l4_ick_parent_names, dsp_fck_ops); -static struct clk usbhs_ick; +static struct clk_core usbhs_ick; static struct clk_hw_omap usbhs_ick_hw = { .hw = { @@ -1777,7 +1777,7 @@ static struct clk_hw_omap usbhs_ick_hw = { DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk virt_prcm_set; +static struct clk_core virt_prcm_set; static const char *virt_prcm_set_parent_names[] = { "mpu_ck", @@ -1792,7 +1792,7 @@ static const struct clk_ops virt_prcm_set_ops = { DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -1806,7 +1806,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk wdt4_fck; +static struct clk_core wdt4_fck; static struct clk_hw_omap wdt4_fck_hw = { .hw = { @@ -1820,7 +1820,7 @@ static struct clk_hw_omap wdt4_fck_hw = { DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk wdt4_ick; +static struct clk_core wdt4_ick; static struct clk_hw_omap wdt4_ick_hw = { .hw = { @@ -2039,10 +2039,10 @@ int __init omap2430_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); + (clk_provider_get_rate(&sys_ck) / 1000000), + (clk_provider_get_rate(&sys_ck) / 100000) % 10, + (clk_provider_get_rate(&dpll_ck) / 1000000), + (clk_provider_get_rate(&mpu_ck) / 1000000)); return 0; } diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index eb8c75e..b593f2b 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -107,7 +107,7 @@ static struct dpll_data dpll3_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll3_ck; +static struct clk_core dpll3_ck; static const char *dpll3_ck_parent_names[] = { "sys_ck", @@ -137,7 +137,7 @@ DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll3_m2_ck", @@ -158,7 +158,7 @@ DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0, OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk security_l4_ick2; +static struct clk_core security_l4_ick2; static const char *security_l4_ick2_parent_names[] = { "l4_ick", @@ -167,7 +167,7 @@ static const char *security_l4_ick2_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL); DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops); -static struct clk aes1_ick; +static struct clk_core aes1_ick; static const char *aes1_ick_parent_names[] = { "security_l4_ick2", @@ -190,7 +190,7 @@ static struct clk_hw_omap aes1_ick_hw = { DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk core_l4_ick; +static struct clk_core core_l4_ick; static const struct clk_ops core_l4_ick_ops = { .init = &omap2_init_clk_clkdm, @@ -199,7 +199,7 @@ static const struct clk_ops core_l4_ick_ops = { DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk aes2_ick; +static struct clk_core aes2_ick; static const char *aes2_ick_parent_names[] = { "core_l4_ick", @@ -224,7 +224,7 @@ static struct clk_hw_omap aes2_ick_hw = { DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk dpll1_fck; +static struct clk_core dpll1_fck; static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -248,7 +248,7 @@ static struct dpll_data dpll1_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll1_ck; +static struct clk_core dpll1_ck; static const struct clk_ops dpll1_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -279,7 +279,7 @@ DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0, OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_ck; +static struct clk_core mpu_ck; static const char *mpu_ck_parent_names[] = { "dpll1_x2m2_ck", @@ -293,7 +293,7 @@ DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0, OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH, 0x0, NULL); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -358,7 +358,7 @@ static struct dpll_data dpll4_dd_3630 __initdata = { .flags = DPLL_J_TYPE }; -static struct clk dpll4_ck; +static struct clk_core dpll4_ck; static const struct clk_ops dpll4_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -422,7 +422,7 @@ DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m5x2_ck; +static struct clk_core dpll4_m5x2_ck; static const char *dpll4_m5x2_ck_parent_names[] = { "dpll4_m5_ck", @@ -459,7 +459,7 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m5x2_ck_3630 = { +static struct clk_core dpll4_m5x2_ck_3630 = { .name = "dpll4_m5x2_ck", .hw = &dpll4_m5x2_ck_hw.hw, .parent_names = dpll4_m5x2_ck_parent_names, @@ -468,7 +468,7 @@ static struct clk dpll4_m5x2_ck_3630 = { .flags = CLK_SET_RATE_PARENT, }; -static struct clk cam_mclk; +static struct clk_core cam_mclk; static const char *cam_mclk_parent_names[] = { "dpll4_m5x2_ck", @@ -483,7 +483,7 @@ static struct clk_hw_omap cam_mclk_hw = { .clkdm_name = "cam_clkdm", }; -static struct clk cam_mclk = { +static struct clk_core cam_mclk = { .name = "cam_mclk", .hw = &cam_mclk_hw.hw, .parent_names = cam_mclk_parent_names, @@ -512,7 +512,7 @@ DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m2x2_ck; +static struct clk_core dpll4_m2x2_ck; static const char *dpll4_m2x2_ck_parent_names[] = { "dpll4_m2_ck", @@ -531,7 +531,7 @@ static struct clk_hw_omap dpll4_m2x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m2x2_ck_3630 = { +static struct clk_core dpll4_m2x2_ck_3630 = { .name = "dpll4_m2x2_ck", .hw = &dpll4_m2x2_ck_hw.hw, .parent_names = dpll4_m2x2_ck_parent_names, @@ -539,7 +539,7 @@ static struct clk dpll4_m2x2_ck_3630 = { .ops = &dpll4_m5x2_ck_3630_ops, }; -static struct clk omap_96m_alwon_fck; +static struct clk_core omap_96m_alwon_fck; static const char *omap_96m_alwon_fck_parent_names[] = { "dpll4_m2x2_ck", @@ -549,7 +549,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk cm_96m_fck; +static struct clk_core cm_96m_fck; static const char *cm_96m_fck_parent_names[] = { "omap_96m_alwon_fck", @@ -568,7 +568,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m3x2_ck; +static struct clk_core dpll4_m3x2_ck; static const char *dpll4_m3x2_ck_parent_names[] = { "dpll4_m3_ck", @@ -587,7 +587,7 @@ static struct clk_hw_omap dpll4_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m3x2_ck_3630 = { +static struct clk_core dpll4_m3x2_ck_3630 = { .name = "dpll4_m3x2_ck", .hw = &dpll4_m3x2_ck_hw.hw, .parent_names = dpll4_m3x2_ck_parent_names, @@ -651,7 +651,7 @@ static const char *omap_48m_fck_parent_names[] = { "cm_96m_fck", "sys_altclk", }; -static struct clk omap_48m_fck; +static struct clk_core omap_48m_fck; static const struct clk_ops omap_48m_fck_ops = { .recalc_rate = &omap2_clksel_recalc, @@ -672,7 +672,7 @@ DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops); DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4); -static struct clk core_12m_fck; +static struct clk_core core_12m_fck; static const char *core_12m_fck_parent_names[] = { "omap_12m_fck", @@ -681,7 +681,7 @@ static const char *core_12m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops); -static struct clk core_48m_fck; +static struct clk_core core_48m_fck; static const char *core_48m_fck_parent_names[] = { "omap_48m_fck", @@ -698,7 +698,7 @@ DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL); -static struct clk core_96m_fck; +static struct clk_core core_96m_fck; static const char *core_96m_fck_parent_names[] = { "omap_96m_fck", @@ -707,7 +707,7 @@ static const char *core_96m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops); -static struct clk core_l3_ick; +static struct clk_core core_l3_ick; static const char *core_l3_ick_parent_names[] = { "l3_ick", @@ -718,7 +718,7 @@ DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops); DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1); -static struct clk corex2_fck; +static struct clk_core corex2_fck; static const char *corex2_fck_parent_names[] = { "dpll3_m2x2_ck", @@ -727,7 +727,7 @@ static const char *corex2_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL); DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops); -static struct clk cpefuse_fck; +static struct clk_core cpefuse_fck; static struct clk_hw_omap cpefuse_fck_hw = { .hw = { @@ -740,7 +740,7 @@ static struct clk_hw_omap cpefuse_fck_hw = { DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk csi2_96m_fck; +static struct clk_core csi2_96m_fck; static const char *csi2_96m_fck_parent_names[] = { "core_96m_fck", @@ -757,7 +757,7 @@ static struct clk_hw_omap csi2_96m_fck_hw = { DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk d2d_26m_fck; +static struct clk_core d2d_26m_fck; static struct clk_hw_omap d2d_26m_fck_hw = { .hw = { @@ -771,7 +771,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = { DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk des1_ick; +static struct clk_core des1_ick; static struct clk_hw_omap des1_ick_hw = { .hw = { @@ -784,7 +784,7 @@ static struct clk_hw_omap des1_ick_hw = { DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk des2_ick; +static struct clk_core des2_ick; static struct clk_hw_omap des2_ick_hw = { .hw = { @@ -803,7 +803,7 @@ DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0, OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll2_fck; +static struct clk_core dpll2_fck; static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -828,7 +828,7 @@ static struct dpll_data dpll2_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll2_ck; +static struct clk_core dpll2_ck; static struct clk_hw_omap dpll2_ck_hw = { .hw = { @@ -857,7 +857,7 @@ DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll3_m3x2_ck; +static struct clk_core dpll3_m3x2_ck; static const char *dpll3_m3x2_ck_parent_names[] = { "dpll3_m3_ck", @@ -876,7 +876,7 @@ static struct clk_hw_omap dpll3_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll3_m3x2_ck_3630 = { +static struct clk_core dpll3_m3x2_ck_3630 = { .name = "dpll3_m3x2_ck", .hw = &dpll3_m3x2_ck_hw.hw, .parent_names = dpll3_m3x2_ck_parent_names, @@ -891,7 +891,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m4x2_ck; +static struct clk_core dpll4_m4x2_ck; static const char *dpll4_m4x2_ck_parent_names[] = { "dpll4_m4_ck", @@ -911,7 +911,7 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m4x2_ck_3630 = { +static struct clk_core dpll4_m4x2_ck_3630 = { .name = "dpll4_m4x2_ck", .hw = &dpll4_m4x2_ck_hw.hw, .parent_names = dpll4_m4x2_ck_parent_names, @@ -925,7 +925,7 @@ DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m6x2_ck; +static struct clk_core dpll4_m6x2_ck; static const char *dpll4_m6x2_ck_parent_names[] = { "dpll4_m6_ck", @@ -944,7 +944,7 @@ static struct clk_hw_omap dpll4_m6x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m6x2_ck_3630 = { +static struct clk_core dpll4_m6x2_ck_3630 = { .name = "dpll4_m6x2_ck", .hw = &dpll4_m6x2_ck_hw.hw, .parent_names = dpll4_m6x2_ck_parent_names, @@ -976,7 +976,7 @@ static struct dpll_data dpll5_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll5_ck; +static struct clk_core dpll5_ck; static struct clk_hw_omap dpll5_ck_hw = { .hw = { @@ -994,7 +994,7 @@ DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0, OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dss1_alwon_fck_3430es1; +static struct clk_core dss1_alwon_fck_3430es1; static const char *dss1_alwon_fck_3430es1_parent_names[] = { "dpll4_m4x2_ck", @@ -1013,7 +1013,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss1_alwon_fck_3430es2; +static struct clk_core dss1_alwon_fck_3430es2; static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = { .hw = { @@ -1029,7 +1029,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss2_alwon_fck; +static struct clk_core dss2_alwon_fck; static struct clk_hw_omap dss2_alwon_fck_hw = { .hw = { @@ -1042,7 +1042,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = { DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk dss_96m_fck; +static struct clk_core dss_96m_fck; static struct clk_hw_omap dss_96m_fck_hw = { .hw = { @@ -1055,7 +1055,7 @@ static struct clk_hw_omap dss_96m_fck_hw = { DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es1; +static struct clk_core dss_ick_3430es1; static struct clk_hw_omap dss_ick_3430es1_hw = { .hw = { @@ -1069,7 +1069,7 @@ static struct clk_hw_omap dss_ick_3430es1_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es2; +static struct clk_core dss_ick_3430es2; static struct clk_hw_omap dss_ick_3430es2_hw = { .hw = { @@ -1083,7 +1083,7 @@ static struct clk_hw_omap dss_ick_3430es2_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_tv_fck; +static struct clk_core dss_tv_fck; static const char *dss_tv_fck_parent_names[] = { "omap_54m_fck", @@ -1100,7 +1100,7 @@ static struct clk_hw_omap dss_tv_fck_hw = { DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops); -static struct clk emac_fck; +static struct clk_core emac_fck; static const char *emac_fck_parent_names[] = { "rmii_ck", @@ -1116,7 +1116,7 @@ static struct clk_hw_omap emac_fck_hw = { DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops); -static struct clk ipss_ick; +static struct clk_core ipss_ick; static const char *ipss_ick_parent_names[] = { "core_l3_ick", @@ -1134,7 +1134,7 @@ static struct clk_hw_omap ipss_ick_hw = { DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops); -static struct clk emac_ick; +static struct clk_core emac_ick; static const char *emac_ick_parent_names[] = { "ipss_ick", @@ -1152,7 +1152,7 @@ static struct clk_hw_omap emac_ick_hw = { DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk emu_core_alwon_ck; +static struct clk_core emu_core_alwon_ck; static const char *emu_core_alwon_ck_parent_names[] = { "dpll3_m3x2_ck", @@ -1162,7 +1162,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm"); DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names, core_l4_ick_ops); -static struct clk emu_mpu_alwon_ck; +static struct clk_core emu_mpu_alwon_ck; static const char *emu_mpu_alwon_ck_parent_names[] = { "mpu_ck", @@ -1171,7 +1171,7 @@ static const char *emu_mpu_alwon_ck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL); DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops); -static struct clk emu_per_alwon_ck; +static struct clk_core emu_per_alwon_ck; static const char *emu_per_alwon_ck_parent_names[] = { "dpll4_m6x2_ck", @@ -1222,7 +1222,7 @@ static const struct clk_ops emu_src_ck_ops = { .disable = &omap2_clkops_disable_clkdm, }; -static struct clk emu_src_ck; +static struct clk_core emu_src_ck; static struct clk_hw_omap emu_src_ck_hw = { .hw = { @@ -1241,7 +1241,7 @@ DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -1255,7 +1255,7 @@ static struct clk_hw_omap fac_ick_hw = { DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk fshostusb_fck; +static struct clk_core fshostusb_fck; static const char *fshostusb_fck_parent_names[] = { "core_48m_fck", @@ -1273,7 +1273,7 @@ static struct clk_hw_omap fshostusb_fck_hw = { DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ck; +static struct clk_core gfx_l3_ck; static struct clk_hw_omap gfx_l3_ck_hw = { .hw = { @@ -1292,7 +1292,7 @@ DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0, OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk gfx_cg1_ck; +static struct clk_core gfx_cg1_ck; static const char *gfx_cg1_ck_parent_names[] = { "gfx_l3_fck", @@ -1310,7 +1310,7 @@ static struct clk_hw_omap gfx_cg1_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_cg2_ck; +static struct clk_core gfx_cg2_ck; static struct clk_hw_omap gfx_cg2_ck_hw = { .hw = { @@ -1324,7 +1324,7 @@ static struct clk_hw_omap gfx_cg2_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ick; +static struct clk_core gfx_l3_ick; static const char *gfx_l3_ick_parent_names[] = { "gfx_l3_ck", @@ -1333,7 +1333,7 @@ static const char *gfx_l3_ick_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm"); DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops); -static struct clk wkup_32k_fck; +static struct clk_core wkup_32k_fck; static const char *wkup_32k_fck_parent_names[] = { "omap_32k_fck", @@ -1342,7 +1342,7 @@ static const char *wkup_32k_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio1_dbck; +static struct clk_core gpio1_dbck; static const char *gpio1_dbck_parent_names[] = { "wkup_32k_fck", @@ -1359,12 +1359,12 @@ static struct clk_hw_omap gpio1_dbck_hw = { DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wkup_l4_ick; +static struct clk_core wkup_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops); -static struct clk gpio1_ick; +static struct clk_core gpio1_ick; static const char *gpio1_ick_parent_names[] = { "wkup_l4_ick", @@ -1382,13 +1382,13 @@ static struct clk_hw_omap gpio1_ick_hw = { DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk per_32k_alwon_fck; +static struct clk_core per_32k_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio2_dbck; +static struct clk_core gpio2_dbck; static const char *gpio2_dbck_parent_names[] = { "per_32k_alwon_fck", @@ -1405,12 +1405,12 @@ static struct clk_hw_omap gpio2_dbck_hw = { DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk per_l4_ick; +static struct clk_core per_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm"); DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk gpio2_ick; +static struct clk_core gpio2_ick; static const char *gpio2_ick_parent_names[] = { "per_l4_ick", @@ -1428,7 +1428,7 @@ static struct clk_hw_omap gpio2_ick_hw = { DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio3_dbck; +static struct clk_core gpio3_dbck; static struct clk_hw_omap gpio3_dbck_hw = { .hw = { @@ -1441,7 +1441,7 @@ static struct clk_hw_omap gpio3_dbck_hw = { DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio3_ick; +static struct clk_core gpio3_ick; static struct clk_hw_omap gpio3_ick_hw = { .hw = { @@ -1455,7 +1455,7 @@ static struct clk_hw_omap gpio3_ick_hw = { DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio4_dbck; +static struct clk_core gpio4_dbck; static struct clk_hw_omap gpio4_dbck_hw = { .hw = { @@ -1468,7 +1468,7 @@ static struct clk_hw_omap gpio4_dbck_hw = { DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio4_ick; +static struct clk_core gpio4_ick; static struct clk_hw_omap gpio4_ick_hw = { .hw = { @@ -1482,7 +1482,7 @@ static struct clk_hw_omap gpio4_ick_hw = { DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio5_dbck; +static struct clk_core gpio5_dbck; static struct clk_hw_omap gpio5_dbck_hw = { .hw = { @@ -1495,7 +1495,7 @@ static struct clk_hw_omap gpio5_dbck_hw = { DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio5_ick; +static struct clk_core gpio5_ick; static struct clk_hw_omap gpio5_ick_hw = { .hw = { @@ -1509,7 +1509,7 @@ static struct clk_hw_omap gpio5_ick_hw = { DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio6_dbck; +static struct clk_core gpio6_dbck; static struct clk_hw_omap gpio6_dbck_hw = { .hw = { @@ -1522,7 +1522,7 @@ static struct clk_hw_omap gpio6_dbck_hw = { DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio6_ick; +static struct clk_core gpio6_ick; static struct clk_hw_omap gpio6_ick_hw = { .hw = { @@ -1536,7 +1536,7 @@ static struct clk_hw_omap gpio6_ick_hw = { DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -1565,7 +1565,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -1586,7 +1586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -1600,7 +1600,7 @@ static struct clk_hw_omap gpt11_ick_hw = { DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk gpt12_fck; +static struct clk_core gpt12_fck; static const char *gpt12_fck_parent_names[] = { "secure_32k_fck", @@ -1609,7 +1609,7 @@ static const char *gpt12_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -1630,7 +1630,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -1651,7 +1651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -1672,7 +1672,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -1693,7 +1693,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -1714,7 +1714,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -1735,7 +1735,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -1756,7 +1756,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -1777,7 +1777,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -1798,7 +1798,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -1812,7 +1812,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static const char *hdq_fck_parent_names[] = { "core_12m_fck", @@ -1830,7 +1830,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -1844,7 +1844,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk hecc_ck; +static struct clk_core hecc_ck; static struct clk_hw_omap hecc_ck_hw = { .hw = { @@ -1858,7 +1858,7 @@ static struct clk_hw_omap hecc_ck_hw = { DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_fck_am35xx; +static struct clk_core hsotgusb_fck_am35xx; static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { .hw = { @@ -1871,7 +1871,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es1; +static struct clk_core hsotgusb_ick_3430es1; static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { .hw = { @@ -1885,7 +1885,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es2; +static struct clk_core hsotgusb_ick_3430es2; static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { .hw = { @@ -1899,7 +1899,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_am35xx; +static struct clk_core hsotgusb_ick_am35xx; static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { .hw = { @@ -1913,7 +1913,7 @@ static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops); -static struct clk i2c1_fck; +static struct clk_core i2c1_fck; static struct clk_hw_omap i2c1_fck_hw = { .hw = { @@ -1927,7 +1927,7 @@ static struct clk_hw_omap i2c1_fck_hw = { DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -1941,7 +1941,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c2_fck; +static struct clk_core i2c2_fck; static struct clk_hw_omap i2c2_fck_hw = { .hw = { @@ -1955,7 +1955,7 @@ static struct clk_hw_omap i2c2_fck_hw = { DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -1969,7 +1969,7 @@ static struct clk_hw_omap i2c2_ick_hw = { DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c3_fck; +static struct clk_core i2c3_fck; static struct clk_hw_omap i2c3_fck_hw = { .hw = { @@ -1983,7 +1983,7 @@ static struct clk_hw_omap i2c3_fck_hw = { DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c3_ick; +static struct clk_core i2c3_ick; static struct clk_hw_omap i2c3_ick_hw = { .hw = { @@ -1997,7 +1997,7 @@ static struct clk_hw_omap i2c3_ick_hw = { DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk icr_ick; +static struct clk_core icr_ick; static struct clk_hw_omap icr_ick_hw = { .hw = { @@ -2011,7 +2011,7 @@ static struct clk_hw_omap icr_ick_hw = { DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk iva2_ck; +static struct clk_core iva2_ck; static const char *iva2_ck_parent_names[] = { "dpll2_m2_ck", @@ -2029,7 +2029,7 @@ static struct clk_hw_omap iva2_ck_hw = { DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops); -static struct clk mad2d_ick; +static struct clk_core mad2d_ick; static struct clk_hw_omap mad2d_ick_hw = { .hw = { @@ -2043,7 +2043,7 @@ static struct clk_hw_omap mad2d_ick_hw = { DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -2084,7 +2084,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -2098,7 +2098,7 @@ static struct clk_hw_omap mcbsp1_ick_hw = { DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk per_96m_fck; +static struct clk_core per_96m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops); @@ -2120,7 +2120,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -2141,7 +2141,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp3_ick; +static struct clk_core mcbsp3_ick; static struct clk_hw_omap mcbsp3_ick_hw = { .hw = { @@ -2162,7 +2162,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp4_ick; +static struct clk_core mcbsp4_ick; static struct clk_hw_omap mcbsp4_ick_hw = { .hw = { @@ -2183,7 +2183,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp5_ick; +static struct clk_core mcbsp5_ick; static struct clk_hw_omap mcbsp5_ick_hw = { .hw = { @@ -2197,7 +2197,7 @@ static struct clk_hw_omap mcbsp5_ick_hw = { DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static struct clk_hw_omap mcspi1_fck_hw = { .hw = { @@ -2211,7 +2211,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -2225,7 +2225,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -2239,7 +2239,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -2253,7 +2253,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi3_fck; +static struct clk_core mcspi3_fck; static struct clk_hw_omap mcspi3_fck_hw = { .hw = { @@ -2267,7 +2267,7 @@ static struct clk_hw_omap mcspi3_fck_hw = { DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi3_ick; +static struct clk_core mcspi3_ick; static struct clk_hw_omap mcspi3_ick_hw = { .hw = { @@ -2281,7 +2281,7 @@ static struct clk_hw_omap mcspi3_ick_hw = { DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi4_fck; +static struct clk_core mcspi4_fck; static struct clk_hw_omap mcspi4_fck_hw = { .hw = { @@ -2295,7 +2295,7 @@ static struct clk_hw_omap mcspi4_fck_hw = { DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi4_ick; +static struct clk_core mcspi4_ick; static struct clk_hw_omap mcspi4_ick_hw = { .hw = { @@ -2309,7 +2309,7 @@ static struct clk_hw_omap mcspi4_ick_hw = { DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs1_fck; +static struct clk_core mmchs1_fck; static struct clk_hw_omap mmchs1_fck_hw = { .hw = { @@ -2323,7 +2323,7 @@ static struct clk_hw_omap mmchs1_fck_hw = { DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs1_ick; +static struct clk_core mmchs1_ick; static struct clk_hw_omap mmchs1_ick_hw = { .hw = { @@ -2337,7 +2337,7 @@ static struct clk_hw_omap mmchs1_ick_hw = { DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs2_fck; +static struct clk_core mmchs2_fck; static struct clk_hw_omap mmchs2_fck_hw = { .hw = { @@ -2351,7 +2351,7 @@ static struct clk_hw_omap mmchs2_fck_hw = { DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs2_ick; +static struct clk_core mmchs2_ick; static struct clk_hw_omap mmchs2_ick_hw = { .hw = { @@ -2365,7 +2365,7 @@ static struct clk_hw_omap mmchs2_ick_hw = { DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs3_fck; +static struct clk_core mmchs3_fck; static struct clk_hw_omap mmchs3_fck_hw = { .hw = { @@ -2379,7 +2379,7 @@ static struct clk_hw_omap mmchs3_fck_hw = { DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs3_ick; +static struct clk_core mmchs3_ick; static struct clk_hw_omap mmchs3_ick_hw = { .hw = { @@ -2393,7 +2393,7 @@ static struct clk_hw_omap mmchs3_ick_hw = { DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk modem_fck; +static struct clk_core modem_fck; static struct clk_hw_omap modem_fck_hw = { .hw = { @@ -2407,7 +2407,7 @@ static struct clk_hw_omap modem_fck_hw = { DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -2421,7 +2421,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -2435,13 +2435,13 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk omap_192m_alwon_fck; +static struct clk_core omap_192m_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk omap_32ksync_ick; +static struct clk_core omap_32ksync_ick; static struct clk_hw_omap omap_32ksync_ick_hw = { .hw = { @@ -2466,7 +2466,7 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = { { .parent = NULL } }; -static struct clk omap_96m_alwon_fck_3630; +static struct clk_core omap_96m_alwon_fck_3630; static const char *omap_96m_alwon_fck_3630_parent_names[] = { "omap_192m_alwon_fck", @@ -2487,7 +2487,7 @@ static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = { .clksel_mask = OMAP3630_CLKSEL_96M_MASK, }; -static struct clk omap_96m_alwon_fck_3630 = { +static struct clk_core omap_96m_alwon_fck_3630 = { .name = "omap_96m_alwon_fck", .hw = &omap_96m_alwon_fck_3630_hw.hw, .parent_names = omap_96m_alwon_fck_3630_parent_names, @@ -2495,7 +2495,7 @@ static struct clk omap_96m_alwon_fck_3630 = { .ops = &omap_96m_alwon_fck_3630_ops, }; -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -2520,17 +2520,17 @@ DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk per_48m_fck; +static struct clk_core per_48m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops); -static struct clk security_l3_ick; +static struct clk_core security_l3_ick; DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL); DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static const char *pka_ick_parent_names[] = { "security_l3_ick", @@ -2552,7 +2552,7 @@ DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0, OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -2565,7 +2565,7 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sad2d_ick; +static struct clk_core sad2d_ick; static struct clk_hw_omap sad2d_ick_hw = { .hw = { @@ -2579,7 +2579,7 @@ static struct clk_hw_omap sad2d_ick_hw = { DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -2630,7 +2630,7 @@ static const char *sgx_fck_parent_names[] = { "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck", }; -static struct clk sgx_fck; +static struct clk_core sgx_fck; static const struct clk_ops sgx_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -2651,7 +2651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel, OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops); -static struct clk sgx_ick; +static struct clk_core sgx_ick; static struct clk_hw_omap sgx_ick_hw = { .hw = { @@ -2665,7 +2665,7 @@ static struct clk_hw_omap sgx_ick_hw = { DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sha11_ick; +static struct clk_core sha11_ick; static struct clk_hw_omap sha11_ick_hw = { .hw = { @@ -2678,7 +2678,7 @@ static struct clk_hw_omap sha11_ick_hw = { DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sha12_ick; +static struct clk_core sha12_ick; static struct clk_hw_omap sha12_ick_hw = { .hw = { @@ -2692,7 +2692,7 @@ static struct clk_hw_omap sha12_ick_hw = { DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk sr1_fck; +static struct clk_core sr1_fck; static struct clk_hw_omap sr1_fck_hw = { .hw = { @@ -2706,7 +2706,7 @@ static struct clk_hw_omap sr1_fck_hw = { DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr2_fck; +static struct clk_core sr2_fck; static struct clk_hw_omap sr2_fck_hw = { .hw = { @@ -2720,17 +2720,17 @@ static struct clk_hw_omap sr2_fck_hw = { DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr_l4_ick; +static struct clk_core sr_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_ick_3430es1; +static struct clk_core ssi_ick_3430es1; static const char *ssi_ick_3430es1_parent_names[] = { "ssi_l4_ick", @@ -2748,7 +2748,7 @@ static struct clk_hw_omap ssi_ick_3430es1_hw = { DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops); -static struct clk ssi_ick_3430es2; +static struct clk_core ssi_ick_3430es2; static struct clk_hw_omap ssi_ick_3430es2_hw = { .hw = { @@ -2813,7 +2813,7 @@ DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1", DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2", &ssi_ssr_fck_3430es2, 0x0, 1, 2); -static struct clk sys_clkout1; +static struct clk_core sys_clkout1; static const char *sys_clkout1_parent_names[] = { "osc_sys_ck", @@ -2843,7 +2843,7 @@ DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0, OMAP3430_CLKSEL_TRACECLK_SHIFT, OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk ts_fck; +static struct clk_core ts_fck; static struct clk_hw_omap ts_fck_hw = { .hw = { @@ -2856,7 +2856,7 @@ static struct clk_hw_omap ts_fck_hw = { DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -2870,7 +2870,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -2884,7 +2884,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -2898,7 +2898,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -2912,7 +2912,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static const char *uart3_fck_parent_names[] = { "per_48m_fck", @@ -2930,7 +2930,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -2944,7 +2944,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_fck; +static struct clk_core uart4_fck; static struct clk_hw_omap uart4_fck_hw = { .hw = { @@ -2958,7 +2958,7 @@ static struct clk_hw_omap uart4_fck_hw = { DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart4_fck_am35xx; +static struct clk_core uart4_fck_am35xx; static struct clk_hw_omap uart4_fck_am35xx_hw = { .hw = { @@ -2972,7 +2972,7 @@ static struct clk_hw_omap uart4_fck_am35xx_hw = { DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart4_ick; +static struct clk_core uart4_ick; static struct clk_hw_omap uart4_ick_hw = { .hw = { @@ -2986,7 +2986,7 @@ static struct clk_hw_omap uart4_ick_hw = { DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_ick_am35xx; +static struct clk_core uart4_ick_am35xx; static struct clk_hw_omap uart4_ick_am35xx_hw = { .hw = { @@ -3023,7 +3023,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel, &clkhwops_iclk_wait, usb_l4_ick_parent_names, ssi_ssr_fck_3430es1_ops); -static struct clk usbhost_120m_fck; +static struct clk_core usbhost_120m_fck; static const char *usbhost_120m_fck_parent_names[] = { "dpll5_m2_ck", @@ -3041,7 +3041,7 @@ static struct clk_hw_omap usbhost_120m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_48m_fck; +static struct clk_core usbhost_48m_fck; static struct clk_hw_omap usbhost_48m_fck_hw = { .hw = { @@ -3055,7 +3055,7 @@ static struct clk_hw_omap usbhost_48m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_ick; +static struct clk_core usbhost_ick; static struct clk_hw_omap usbhost_ick_hw = { .hw = { @@ -3069,7 +3069,7 @@ static struct clk_hw_omap usbhost_ick_hw = { DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk usbtll_fck; +static struct clk_core usbtll_fck; static struct clk_hw_omap usbtll_fck_hw = { .hw = { @@ -3083,7 +3083,7 @@ static struct clk_hw_omap usbtll_fck_hw = { DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbtll_ick; +static struct clk_core usbtll_ick; static struct clk_hw_omap usbtll_ick_hw = { .hw = { @@ -3124,7 +3124,7 @@ static const char *usim_fck_parent_names[] = { "omap_96m_fck", "dpll5_m2_ck", "sys_ck", }; -static struct clk usim_fck; +static struct clk_core usim_fck; static const struct clk_ops usim_fck_ops = { .enable = &omap2_dflt_clk_enable, @@ -3142,7 +3142,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel, OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait, usim_fck_parent_names, usim_fck_ops); -static struct clk usim_ick; +static struct clk_core usim_ick; static struct clk_hw_omap usim_ick_hw = { .hw = { @@ -3156,7 +3156,7 @@ static struct clk_hw_omap usim_ick_hw = { DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk vpfe_fck; +static struct clk_core vpfe_fck; static const char *vpfe_fck_parent_names[] = { "pclk_ck", @@ -3172,7 +3172,7 @@ static struct clk_hw_omap vpfe_fck_hw = { DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops); -static struct clk vpfe_ick; +static struct clk_core vpfe_ick; static struct clk_hw_omap vpfe_ick_hw = { .hw = { @@ -3186,12 +3186,12 @@ static struct clk_hw_omap vpfe_ick_hw = { DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk wdt1_fck; +static struct clk_core wdt1_fck; DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -3205,7 +3205,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt2_fck; +static struct clk_core wdt2_fck; static struct clk_hw_omap wdt2_fck_hw = { .hw = { @@ -3219,7 +3219,7 @@ static struct clk_hw_omap wdt2_fck_hw = { DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wdt2_ick; +static struct clk_core wdt2_ick; static struct clk_hw_omap wdt2_ick_hw = { .hw = { @@ -3233,7 +3233,7 @@ static struct clk_hw_omap wdt2_ick_hw = { DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt3_fck; +static struct clk_core wdt3_fck; static struct clk_hw_omap wdt3_fck_hw = { .hw = { @@ -3247,7 +3247,7 @@ static struct clk_hw_omap wdt3_fck_hw = { DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk wdt3_ick; +static struct clk_core wdt3_ick; static struct clk_hw_omap wdt3_ick_hw = { .hw = { @@ -3661,10 +3661,10 @@ int __init omap3xxx_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&osc_sys_ck) / 1000000), - (clk_get_rate(&osc_sys_ck) / 100000) % 10, - (clk_get_rate(&core_ck) / 1000000), - (clk_get_rate(&arm_fck) / 1000000)); + (clk_provider_get_rate(&osc_sys_ck) / 1000000), + (clk_provider_get_rate(&osc_sys_ck) / 100000) % 10, + (clk_provider_get_rate(&core_ck) / 1000000), + (clk_provider_get_rate(&arm_fck) / 1000000)); /* * Lock DPLL5 -- here only until other device init code can @@ -3674,8 +3674,8 @@ int __init omap3xxx_clk_init(void) omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ - sdrc_ick_p = clk_get(NULL, "sdrc_ick"); - arm_fck_p = clk_get(NULL, "arm_fck"); + sdrc_ick_p = clk_provider_get(NULL, "sdrc_ick"); + arm_fck_p = clk_provider_get(NULL, "arm_fck"); return 0; } diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 82572e2..28a6d42 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -22,7 +22,7 @@ /** * _allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. The DPLL will enter low-power * stop when its downstream clocks are gated. No return value. @@ -39,7 +39,7 @@ static void _allow_idle(struct clk_hw_omap *clk) /** * _deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 59cf310..6723d916 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -48,7 +48,7 @@ static struct clk_hw_omap *dpll_core_ck; * Returns the CORE_CLK rate. CORE_CLK can have one of three rate * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz * (the latter is unusual). This currently should be called with - * struct clk *dpll_ck, which is a composite clock of dpll_ck and + * struct clk_core *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ unsigned long omap2xxx_clk_get_core_rate(void) @@ -179,7 +179,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, /** * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck - * @clk: struct clk *dpll_ck + * @clk: struct clk_core *dpll_ck * * Store a local copy of @clk in dpll_core_ck so other code can query * the core rate without having to clk_get(), which can sleep. Must diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 85e0b0c0..67014e1 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -198,14 +198,14 @@ void omap2xxx_clkt_vps_check_bootloader_rates(void) */ void omap2xxx_clkt_vps_late_init(void) { - struct clk *c; + struct clk_core *c; - c = clk_get(NULL, "sys_ck"); + c = clk_provider_get(NULL, "sys_ck"); if (IS_ERR(c)) { WARN(1, "could not locate sys_ck\n"); } else { - sys_ck_rate = clk_get_rate(c); - clk_put(c); + sys_ck_rate = clk_provider_get_rate(c); + __clk_put(c); } } @@ -230,7 +230,7 @@ void omap2xxx_clkt_vps_init(void) { struct clk_init_data init = { NULL }; struct clk_hw_omap *hw = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name = "mpu_ck"; struct clk_lookup *lookup = NULL; diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index eb69acf..9e96363 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -38,7 +38,7 @@ /** * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Program the DPLL M2 divider with the rounded target rate. Returns diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 7ee2610..b4796b3 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -51,15 +51,15 @@ /** * _get_clksel_by_parent() - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for + * @clk: OMAP struct clk_core ptr to inspect + * @src_clk: OMAP struct clk_core ptr of the parent clk to search for * * Scan the struct clksel array associated with the clock to find * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, - struct clk *src_clk) + struct clk_core *src_clk) { const struct clksel *clks; @@ -82,7 +82,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, /** * _write_clksel_reg() - program a clock's clksel register in hardware - * @clk: struct clk * to program + * @clk: struct clk_core * to program * @v: clksel bitfield value to program (with LSB at bit 0) * * Shift the clksel register bitfield value @v to its appropriate @@ -107,10 +107,10 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) /** * _clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @field_val: register field value to find * - * Given a struct clk of a rate-selectable clksel clock, and a register field + * Given a struct clk_core of a rate-selectable clksel clock, and a register field * value to search for, find the corresponding clock divisor. The register * field value should be pre-masked and shifted down so the LSB is at bit 0 * before calling. Returns 0 on error or returns the actual integer divisor @@ -120,7 +120,7 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; parent = __clk_get_parent(clk->hw.clk); @@ -149,10 +149,10 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) /** * _divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @div: integer divisor to search for * - * Given a struct clk of a rate-selectable clksel clock, and a clock + * Given a struct clk_core of a rate-selectable clksel clock, and a clock * divisor, find the corresponding register field value. Returns the * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. @@ -161,7 +161,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; /* should never happen */ WARN_ON(div == 0); @@ -191,7 +191,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) /** * _read_divisor() - get current divisor applied to parent clock (from hdwr) - * @clk: OMAP struct clk to use. + * @clk: OMAP struct clk_core to use. * * Read the current divisor register value for @clk that is programmed * into the hardware, convert it into the actual divisor value, and @@ -215,7 +215,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk) /** * omap2_clksel_round_rate_div() - find divisor for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * @new_div: ptr to where we should store the divisor * @@ -233,7 +233,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, const struct clksel *clks; const struct clksel_rate *clkr; u32 last_div = 0; - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; const char *clk_name; @@ -286,7 +286,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, /* * Clocktype interface functions to the OMAP clock code - * (i.e., those used in struct clk field function pointers, etc.) + * (i.e., those used in struct clk_core field function pointers, etc.) */ /** @@ -309,7 +309,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) const struct clksel *clks; const struct clksel_rate *clkr; u32 r, found = 0; - struct clk *parent; + struct clk_core *parent; const char *clk_name; int ret = 0, f = 0; @@ -345,11 +345,11 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) /** - * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field - * @clk: struct clk * + * omap2_clksel_recalc() - function ptr to pass via struct clk_core .recalc field + * @clk: struct clk_core * * * This function is intended to be called only by the clock framework. - * Each clksel clock should have its struct clk .recalc field set to this + * Each clksel clock should have its struct clk_core .recalc field set to this * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ @@ -376,7 +376,7 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * * This function is intended to be called only by the clock framework. @@ -396,7 +396,7 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, /** * omap2_clksel_set_rate() - program clock rate in hardware - * @clk: struct clk * to program rate + * @clk: struct clk_core * to program rate * @rate: target rate to program * * This function is intended to be called only by the clock framework. @@ -435,7 +435,7 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, } /* - * Clksel parent setting function - not passed in struct clk function + * Clksel parent setting function - not passed in struct clk_core function * pointer - instead, the OMAP clock code currently assumes that any * parent-setting clock is a clksel clock, and calls * omap2_clksel_set_parent() by default @@ -443,8 +443,8 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap2_clksel_set_parent() - change a clock's parent clock - * @clk: struct clk * of the child clock - * @new_parent: struct clk * of the new parent clock + * @clk: struct clk_core * of the child clock + * @new_parent: struct clk_core * of the new parent clock * * This function is intended to be called only by the clock framework. * Change the parent clock of clock @clk to @new_parent. This is diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 332af92..4705275 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -67,7 +67,7 @@ /* * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test + * @clk: DPLL struct clk_core to test * @n: divider value (N) to test * * Tests whether a particular divider @n will result in a valid DPLL @@ -200,7 +200,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - /* Reparent the struct clk in case the dpll is in bypass */ + /* Reparent the struct clk_core in case the dpll is in bypass */ if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) @@ -220,7 +220,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) /** * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL + * @clk: struct clk_core * of a DPLL * * DPLLs can be locked or bypassed - basically, enabled or disabled. * When locked, the DPLL output depends on the M and N values. When @@ -278,7 +278,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) /** * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL + * @clk: struct clk_core * for a DPLL * @target_rate: desired DPLL clock rate * * Given a DPLL and a desired target rate, round the target rate to a diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 591581a..072cc41 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -145,7 +145,7 @@ static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, /** * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module + * @clk: struct clk_core * belonging to the module * * If the necessary clocks for the OMAP hardware IP block that * corresponds to clock @clk are enabled, then wait for the module to @@ -184,7 +184,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use * - * Convert a clockdomain name stored in a struct clk 'clk' into a + * Convert a clockdomain name stored in a struct clk_core 'clk' into a * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ @@ -225,7 +225,7 @@ void __init omap2_clk_disable_clkdm_control(void) /** * omap2_clk_dflt_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of + * @clk: struct clk_core * to find the companion clock of * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in * @other_bit: u8 ** to return the companion clock bit shift in * @@ -261,7 +261,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, /** * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk - * @clk: struct clk * to find IDLEST info for + * @clk: struct clk_core * to find IDLEST info for * @idlest_reg: void __iomem ** to return the CM_IDLEST va in * @idlest_bit: u8 * to return the CM_IDLEST bit shift in * @idlest_val: u8 * to return the idle status indicator @@ -511,14 +511,14 @@ __setup("mpurate=", omap_clk_setup); /** * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock - * @clk: struct clk * to initialize + * @clk: struct clk_core * to initialize * * Add an OMAP clock @clk to the internal list of OMAP clocks. Used * temporarily for autoidle handling, until this support can be * integrated into the common clock framework code in some way. No * return value. */ -void omap2_init_clk_hw_omap_clocks(struct clk *clk) +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk) { struct clk_hw_omap *c; @@ -575,11 +575,11 @@ int omap2_clk_disable_autoidle_all(void) /** * omap2_clk_deny_idle - disable autoidle on an OMAP clock - * @clk: struct clk * to disable autoidle for + * @clk: struct clk_core * to disable autoidle for * * Disable autoidle on an OMAP clock. */ -int omap2_clk_deny_idle(struct clk *clk) +int omap2_clk_deny_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -594,11 +594,11 @@ int omap2_clk_deny_idle(struct clk *clk) /** * omap2_clk_allow_idle - enable autoidle on an OMAP clock - * @clk: struct clk * to enable autoidle for + * @clk: struct clk_core * to enable autoidle for * * Enable autoidle on an OMAP clock. */ -int omap2_clk_allow_idle(struct clk *clk) +int omap2_clk_allow_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -623,12 +623,12 @@ int omap2_clk_allow_idle(struct clk *clk) */ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) { - struct clk *init_clk; + struct clk_core *init_clk; int i; for (i = 0; i < num_clocks; i++) { - init_clk = clk_get(NULL, clk_names[i]); - clk_prepare_enable(init_clk); + init_clk = clk_provider_get(NULL, clk_names[i]); + clk_provider_prepare_enable(init_clk); } } @@ -664,31 +664,31 @@ void __init omap_clocks_register(struct omap_clk oclks[], int cnt) * the OPP layer. XXX This is intended to be handled by the OPP layer * code in the near future and should be removed from the clock code. * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects - * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name + * the rate, -ENOENT if the struct clk_core referred to by @mpurate_ck_name * cannot be found, or 0 upon success. */ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) { - struct clk *mpurate_ck; + struct clk_core *mpurate_ck; int r; if (!mpurate) return -EINVAL; - mpurate_ck = clk_get(NULL, mpurate_ck_name); + mpurate_ck = clk_provider_get(NULL, mpurate_ck_name); if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) return -ENOENT; - r = clk_set_rate(mpurate_ck, mpurate); + r = clk_provider_set_rate(mpurate_ck, mpurate); if (r < 0) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", mpurate_ck_name, mpurate, r); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return 0; } @@ -709,25 +709,25 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name) { - struct clk *hfclkin_ck, *core_ck, *mpu_ck; + struct clk_core *hfclkin_ck, *core_ck, *mpu_ck; unsigned long hfclkin_rate; - mpu_ck = clk_get(NULL, mpu_ck_name); + mpu_ck = clk_provider_get(NULL, mpu_ck_name); if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) return; - core_ck = clk_get(NULL, core_ck_name); + core_ck = clk_provider_get(NULL, core_ck_name); if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) return; - hfclkin_ck = clk_get(NULL, hfclkin_ck_name); + hfclkin_ck = clk_provider_get(NULL, hfclkin_ck_name); if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) return; - hfclkin_rate = clk_get_rate(hfclkin_ck); + hfclkin_rate = clk_provider_get_rate(hfclkin_ck); pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), - (clk_get_rate(core_ck) / 1000000), - (clk_get_rate(mpu_ck) / 1000000)); + (clk_provider_get_rate(core_ck) / 1000000), + (clk_provider_get_rate(mpu_ck) / 1000000)); } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 12f54d4..05e3d5b 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -40,7 +40,7 @@ struct omap_clk { struct clockdomain; #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -50,7 +50,7 @@ struct clockdomain; #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ _clkops_name, _flags) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -70,7 +70,7 @@ struct clockdomain; #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ _clksel_reg, _clksel_mask, \ _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -86,7 +86,7 @@ struct clockdomain; _clksel_reg, _clksel_mask, \ _enable_reg, _enable_bit, \ _hwops, _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -111,7 +111,7 @@ struct clockdomain; }, \ { .parent = NULL }, \ }; \ - static struct clk _name; \ + static struct clk_core _name; \ static const char *_name##_parent_names[] = { \ _parent_name, \ }; \ @@ -167,14 +167,14 @@ struct clksel_rate { /** * struct clksel - available parent clocks, and a pointer to their divisors - * @parent: struct clk * to a possible parent clock + * @parent: struct clk_core * to a possible parent clock * @rates: available divisors for this parent clock * * A struct clksel is always associated with one or more struct clks * and one or more struct clksel_rates. */ struct clksel { - struct clk *parent; + struct clk_core *parent; const struct clksel_rate *rates; }; @@ -236,8 +236,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); int omap2_clk_enable_autoidle_all(void); -int omap2_clk_allow_idle(struct clk *clk); -int omap2_clk_deny_idle(struct clk *clk); +int omap2_clk_allow_idle(struct clk_core *clk); +int omap2_clk_deny_idle(struct clk_core *clk); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -258,7 +258,7 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; -extern struct clk dummy_ck; +extern struct clk_core dummy_ck; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 0b02b41..17abc81 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -37,7 +37,7 @@ #define DPLL5_FREQ_FOR_USBHOST 120000000 /* needed by omap3_core_dpll_m2_set_rate() */ -struct clk *sdrc_ick_p, *arm_fck_p; +struct clk_core *sdrc_ick_p, *arm_fck_p; int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -56,20 +56,20 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, void __init omap3_clk_lock_dpll5(void) { - struct clk *dpll5_clk; - struct clk *dpll5_m2_clk; + struct clk_core *dpll5_clk; + struct clk_core *dpll5_m2_clk; - dpll5_clk = clk_get(NULL, "dpll5_ck"); - clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_prepare_enable(dpll5_clk); + dpll5_clk = clk_provider_get(NULL, "dpll5_ck"); + clk_provider_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); + clk_provider_prepare_enable(dpll5_clk); /* Program dpll5_m2_clk divider for no division */ - dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_prepare_enable(dpll5_m2_clk); - clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); + dpll5_m2_clk = clk_provider_get(NULL, "dpll5_m2_ck"); + clk_provider_prepare_enable(dpll5_m2_clk); + clk_provider_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - clk_disable_unprepare(dpll5_m2_clk); - clk_disable_unprepare(dpll5_clk); + clk_provider_disable_unprepare(dpll5_m2_clk); + clk_provider_disable_unprepare(dpll5_clk); return; } diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 78d9f56..063fbf1 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -12,8 +12,8 @@ int omap3xxx_clk_init(void); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); -extern struct clk *sdrc_ick_p; -extern struct clk *arm_fck_p; +extern struct clk_core *sdrc_ick_p; +extern struct clk_core *arm_fck_p; extern const struct clkops clkops_noncore_dpll_ops; diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index ef4d21b..31e3e79 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -119,7 +119,7 @@ const struct clksel_rate div31_1to31_rates[] = { static struct clk_ops dummy_ck_ops = {}; -struct clk dummy_ck = { +struct clk_core dummy_ck = { .name = "dummy_clk", .ops = &dummy_ck_ops, .flags = CLK_IS_BASIC, diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 2da3b5e..ce0971c 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1141,7 +1141,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) /** * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the enabled downstream clock + * @clk: struct clk_core * of the enabled downstream clock * * Increment the usecount of the clockdomain @clkdm and ensure that it * is awake before @clk is enabled. Intended to be called by @@ -1152,7 +1152,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) * by on-chip processors. Returns -EINVAL if passed null pointers; * returns 0 upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk) { /* * XXX Rewrite this code to maintain a list of enabled @@ -1168,7 +1168,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) /** * clkdm_clk_disable - remove an enabled downstream clock from this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the disabled downstream clock + * @clk: struct clk_core * of the disabled downstream clock * * Decrement the usecount of this clockdomain @clkdm when @clk is * disabled. Intended to be called by clk_disable() code. If the @@ -1178,7 +1178,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0 * upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk) { if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 82c37b1..f1a2cad 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -207,8 +207,8 @@ int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep_nolock(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk); +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 0f9e479..94b3232 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -524,7 +524,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_prepare_enable(oc->_clk); + clk_provider_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -551,7 +551,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_disable_unprepare(oc->_clk); + clk_provider_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37..9c70696 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -291,7 +291,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) /* * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @freqsel: FREQSEL value to set * * Program the DPLL with the last M, N values calculated, and wait for @@ -413,7 +413,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw) struct clk_hw_omap *clk = to_clk_hw_omap(hw); int r; struct dpll_data *dd; - struct clk *parent; + struct clk_core *parent; dd = clk->dpll_data; if (!dd) @@ -464,7 +464,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) /** * omap3_noncore_dpll_set_rate - set non-core DPLL rate - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Set the DPLL CLKOUT to the target rate. If the DPLL can enter @@ -477,7 +477,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct clk *new_parent = NULL; + struct clk_core *new_parent = NULL; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -495,15 +495,15 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __func__, __clk_get_name(hw->clk)); __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); + clk_provider_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; - clk_disable(dd->clk_bypass); + clk_provider_disable(dd->clk_bypass); __clk_unprepare(dd->clk_bypass); } else { __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); + clk_provider_enable(dd->clk_ref); if (dd->last_rounded_rate != rate) rate = __clk_round_rate(hw->clk, rate); @@ -524,7 +524,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; - clk_disable(dd->clk_ref); + clk_provider_disable(dd->clk_ref); __clk_unprepare(dd->clk_ref); } /* @@ -534,7 +534,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, * stuff is inherited for free */ - if (!ret && clk_get_parent(hw->clk) != new_parent) + if (!ret && clk_provider_get_parent(hw->clk) != new_parent) __clk_reparent(hw->clk, new_parent); return 0; @@ -544,10 +544,10 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap3_dpll_autoidle_read - read a DPLL's autoidle bits - * @clk: struct clk * of the DPLL to read + * @clk: struct clk_core * of the DPLL to read * * Return the DPLL's autoidle bits, shifted down to bit 0. Returns - * -EINVAL if passed a null pointer or if the struct clk does not + * -EINVAL if passed a null pointer or if the struct clk_core does not * appear to refer to a DPLL. */ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) @@ -572,7 +572,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) /** * omap3_dpll_allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. This automatic idle mode * switching takes effect only when the DPLL is locked, at least on @@ -606,7 +606,7 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk) /** * omap3_dpll_deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ @@ -636,7 +636,7 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk) static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) { struct clk_hw_omap *pclk = NULL; - struct clk *parent; + struct clk_core *parent; /* Walk up the parents of clk, looking for a DPLL */ do { diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 52f9438..0a09507 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -117,7 +117,7 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to compute the rate for + * @clk: struct clk_core * of the DPLL to compute the rate for * * Compute the output rate for the OMAP4 DPLL represented by @clk. * Takes the REGM4XEN bit into consideration, which is needed for the @@ -149,7 +149,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, /** * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to round a rate for + * @clk: struct clk_core * of the DPLL to round a rate for * @target_rate: the desired rate of the DPLL * * Compute the rate that would be programmed into the DPLL hardware diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index b4ac3af..e7ea6ba 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -34,7 +34,7 @@ #include "cm3xxx.h" #include "cm-regbits-34xx.h" -static struct clk *mcbsp_iclks[5]; +static struct clk_core *mcbsp_iclks[5]; static int omap3_enable_st_clock(unsigned int id, bool enable) { @@ -98,7 +98,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); pdata->enable_st_clock = omap3_enable_st_clock; sprintf(clk_name, "mcbsp%d_ick", id); - mcbsp_iclks[id] = clk_get(NULL, clk_name); + mcbsp_iclks[id] = clk_provider_get(NULL, clk_name); count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index fbe8cf0..350abb0 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -47,7 +47,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, const char *clk_name) { - struct clk *r; + struct clk_core *r; struct clk_lookup *l; if (!clk_alias || !clk_name) @@ -55,15 +55,15 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name); - r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); + r = clk_provider_get_sys(dev_name(&od->pdev->dev), clk_alias); if (!IS_ERR(r)) { dev_warn(&od->pdev->dev, "alias %s already exists\n", clk_alias); - clk_put(r); + __clk_put(r); return; } - r = clk_get(NULL, clk_name); + r = clk_provider_get(NULL, clk_name); if (IS_ERR(r)) { dev_err(&od->pdev->dev, "clk_get for %s failed\n", clk_name); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index f7bb435..31f86bc 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -753,7 +753,7 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) } /** - * _init_main_clk - get a struct clk * for the the hwmod's main functional clk + * _init_main_clk - get a struct clk_core * for the the hwmod's main functional clk * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh _clk (main @@ -767,7 +767,7 @@ static int _init_main_clk(struct omap_hwmod *oh) if (!oh->main_clk) return 0; - oh->_clk = clk_get(NULL, oh->main_clk); + oh->_clk = clk_provider_get(NULL, oh->main_clk); if (IS_ERR(oh->_clk)) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", oh->name, oh->main_clk); @@ -781,7 +781,7 @@ static int _init_main_clk(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oh->_clk); + clk_provider_prepare(oh->_clk); if (!_get_clkdm(oh)) pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", @@ -791,7 +791,7 @@ static int _init_main_clk(struct omap_hwmod *oh) } /** - * _init_interface_clks - get a struct clk * for the the hwmod's interface clks + * _init_interface_clks - get a struct clk_core * for the the hwmod's interface clks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh OCP slave interface @@ -801,7 +801,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) { struct omap_hwmod_ocp_if *os; struct list_head *p; - struct clk *c; + struct clk_core *c; int i = 0; int ret = 0; @@ -812,7 +812,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) if (!os->clk) continue; - c = clk_get(NULL, os->clk); + c = clk_provider_get(NULL, os->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", oh->name, os->clk); @@ -828,14 +828,14 @@ static int _init_interface_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(os->_clk); + clk_provider_prepare(os->_clk); } return ret; } /** - * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks + * _init_opt_clk - get a struct clk_core * for the the hwmod's optional clocks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk @@ -844,12 +844,12 @@ static int _init_interface_clks(struct omap_hwmod *oh) static int _init_opt_clks(struct omap_hwmod *oh) { struct omap_hwmod_opt_clk *oc; - struct clk *c; + struct clk_core *c; int i; int ret = 0; for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { - c = clk_get(NULL, oc->clk); + c = clk_provider_get(NULL, oc->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", oh->name, oc->clk); @@ -865,7 +865,7 @@ static int _init_opt_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oc->_clk); + clk_provider_prepare(oc->_clk); } return ret; @@ -887,7 +887,7 @@ static int _enable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); if (oh->_clk) - clk_enable(oh->_clk); + clk_provider_enable(oh->_clk); p = oh->slave_ports.next; @@ -895,7 +895,7 @@ static int _enable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -918,7 +918,7 @@ static int _disable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); if (oh->_clk) - clk_disable(oh->_clk); + clk_provider_disable(oh->_clk); p = oh->slave_ports.next; @@ -926,7 +926,7 @@ static int _disable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_disable(os->_clk); + clk_provider_disable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -945,7 +945,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_enable(oc->_clk); + clk_provider_enable(oc->_clk); } } @@ -960,7 +960,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: disable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_disable(oc->_clk); + clk_provider_disable(oc->_clk); } } @@ -2585,7 +2585,7 @@ static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) /* XXX omap_iclk_deny_idle(c); */ } else { /* XXX omap_iclk_allow_idle(c); */ - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } } @@ -3389,7 +3389,7 @@ static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) * Initialize and set up a single hwmod. Intended to be used for a * small number of early devices, such as the timer IP blocks used for * the scheduler clock. Must be called after omap2_clk_init(). - * Resolves the struct clk names to struct clk pointers for each + * Resolves the struct clk_core names to struct clk_core pointers for each * registered omap_hwmod. Also calls _setup() on each hwmod. Returns * -EINVAL upon error or 0 upon success. */ @@ -3418,7 +3418,7 @@ int __init omap_hwmod_setup_one(const char *oh_name) * * Initialize and set up all IP blocks registered with the hwmod code. * Must be called after omap2_clk_init(). Resolves the struct clk - * names to struct clk pointers for each registered omap_hwmod. Also + * names to struct clk_core pointers for each registered omap_hwmod. Also * calls _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) @@ -3785,7 +3785,7 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, */ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { - struct clk *c; + struct clk_core *c; struct omap_hwmod_ocp_if *oi; struct clockdomain *clkdm; struct clk_hw_omap *clk; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0f97d63..46ffd06 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -207,7 +207,7 @@ struct omap_hwmod_rst_info { * struct omap_hwmod_opt_clk - optional clocks used by this hwmod * @role: "sys", "32k", "tv", etc -- for use in clk_get() * @clk: opt clock: OMAP clock name - * @_clk: pointer to the struct clk (filled in at runtime) + * @_clk: pointer to the struct clk_core (filled in at runtime) * * The module's interface clock and main functional clock should not * be added as optional clocks. @@ -215,7 +215,7 @@ struct omap_hwmod_rst_info { struct omap_hwmod_opt_clk { const char *role; const char *clk; - struct clk *_clk; + struct clk_core *_clk; }; @@ -289,7 +289,7 @@ struct omap_hwmod_addr_space { * @slave: struct omap_hwmod that responds to OCP transactions on this link * @addr: address space associated with this link * @clk: interface clock: OMAP clock name - * @_clk: pointer to the interface struct clk (filled in at runtime) + * @_clk: pointer to the interface struct clk_core (filled in at runtime) * @fw: interface firewall data * @width: OCP data width * @user: initiators using this interface (see OCP_USER_* macros above) @@ -306,7 +306,7 @@ struct omap_hwmod_ocp_if { struct omap_hwmod *slave; struct omap_hwmod_addr_space *addr; const char *clk; - struct clk *_clk; + struct clk_core *_clk; union { struct omap_hwmod_omap2_firewall omap2; } fw; @@ -611,7 +611,7 @@ struct omap_hwmod_link { * @sdma_reqs: ptr to an array of System DMA request IDs * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name - * @_clk: pointer to the main struct clk (filled in at runtime) + * @_clk: pointer to the main struct clk_core (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @voltdm: pointer to voltage domain (filled in at runtime) * @dev_attr: arbitrary device attributes that can be passed to the driver @@ -653,7 +653,7 @@ struct omap_hwmod { struct omap_hwmod_omap4_prcm omap4; } prcm; const char *main_clk; - struct clk *_clk; + struct clk_core *_clk; struct omap_hwmod_opt_clk *opt_clks; char *clkdm_name; struct clockdomain *clkdm; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988..35633c5 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -60,7 +60,7 @@ static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, static struct powerdomain *mpu_pwrdm, *core_pwrdm; static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; -static struct clk *osc_ck, *emul_ck; +static struct clk_core *osc_ck, *emul_ck; static int omap2_enter_full_retention(void) { @@ -71,7 +71,7 @@ static int omap2_enter_full_retention(void) * oscillator itself it will be disabled if/when we enter retention * mode. */ - clk_disable(osc_ck); + clk_provider_disable(osc_ck); /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ @@ -101,7 +101,7 @@ static int omap2_enter_full_retention(void) no_sleep: omap2_gpio_resume_after_idle(); - clk_enable(osc_ck); + clk_provider_enable(osc_ck); /* clear CORE wake-up events */ omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); @@ -288,17 +288,17 @@ int __init omap2_pm_init(void) pr_err("PM: gfx_clkdm not found\n"); - osc_ck = clk_get(NULL, "osc_ck"); + osc_ck = clk_provider_get(NULL, "osc_ck"); if (IS_ERR(osc_ck)) { printk(KERN_ERR "could not get osc_ck\n"); return -ENODEV; } if (cpu_is_omap242x()) { - emul_ck = clk_get(NULL, "emul_ck"); + emul_ck = clk_provider_get(NULL, "emul_ck"); if (IS_ERR(emul_ck)) { printk(KERN_ERR "could not get emul_ck\n"); - clk_put(osc_ck); + __clk_put(osc_ck); return -ENODEV; } } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 6bbb7b5..6be2d2d 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -62,7 +62,7 @@ void __init orion5x_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; void __init clk_init(void) { diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 961b593..7bf2fe6 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -27,7 +27,7 @@ /* Create a clkdev entry for a given device/clk */ void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk) + struct clk_core *clk) { struct clk_lookup *cl; @@ -40,7 +40,7 @@ void __init orion_clkdev_add(const char *con_id, const char *dev_id, Kirkwood has gated clocks for some of its peripherals, so creates its own clkdev entries. For all the other orion devices, create clkdev entries to the tclk. */ -void __init orion_clkdev_init(struct clk *tclk) +void __init orion_clkdev_init(struct clk_core *tclk) { orion_clkdev_add(NULL, "orion_spi.0", tclk); orion_clkdev_add(NULL, "orion_spi.1", tclk); @@ -78,10 +78,10 @@ static void fill_resources(struct platform_device *device, /***************************************************************************** * UART ****************************************************************************/ -static unsigned long __init uart_get_clk_rate(struct clk *clk) +static unsigned long __init uart_get_clk_rate(struct clk_core *clk) { - clk_prepare_enable(clk); - return clk_get_rate(clk); + clk_provider_prepare_enable(clk); + return clk_provider_get_rate(clk); } static void __init uart_complete( @@ -91,7 +91,7 @@ static void __init uart_complete( void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { data->mapbase = mapbase; data->membase = membase; @@ -125,7 +125,7 @@ static struct platform_device orion_uart0 = { void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources, membase, mapbase, irq, clk); @@ -153,7 +153,7 @@ static struct platform_device orion_uart1 = { void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources, membase, mapbase, irq, clk); @@ -181,7 +181,7 @@ static struct platform_device orion_uart2 = { void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources, membase, mapbase, irq, clk); @@ -209,7 +209,7 @@ static struct platform_device orion_uart3 = { void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, membase, mapbase, irq, clk); diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index d9a24f6..44f1bbe 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -18,22 +18,22 @@ struct mv_sata_platform_data; void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); @@ -107,7 +107,7 @@ void __init orion_crypto_init(unsigned long mapbase, unsigned long irq); void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk); + struct clk_core *clk); -void __init orion_clkdev_init(struct clk *tclk); +void __init orion_clkdev_init(struct clk_core *tclk); #endif diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index 6eb614a..81afe83 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c @@ -70,7 +70,7 @@ enum { }; /* data required for the OF clock provider registration */ -static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; +static struct clk_core *clks[MPC512x_CLK_LAST_PRIVATE]; static struct clk_onecell_data clk_data; /* CCM register access */ @@ -218,12 +218,12 @@ static bool soc_has_mclk_mux0_canin(void) /* common clk API wrappers {{{ */ /* convenience wrappers around the common clk API */ -static inline struct clk *mpc512x_clk_fixed(const char *name, int rate) +static inline struct clk_core *mpc512x_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mpc512x_clk_factor( +static inline struct clk_core *mpc512x_clk_factor( const char *name, const char *parent_name, int mul, int div) { @@ -234,7 +234,7 @@ static inline struct clk *mpc512x_clk_factor( mul, div); } -static inline struct clk *mpc512x_clk_divider( +static inline struct clk_core *mpc512x_clk_divider( const char *name, const char *parent_name, u8 clkflags, u32 __iomem *reg, u8 pos, u8 len, int divflags) { @@ -242,7 +242,7 @@ static inline struct clk *mpc512x_clk_divider( reg, pos, len, divflags, &clklock); } -static inline struct clk *mpc512x_clk_divtable( +static inline struct clk_core *mpc512x_clk_divtable( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos, u8 len, const struct clk_div_table *divtab) @@ -255,7 +255,7 @@ static inline struct clk *mpc512x_clk_divtable( divtab, &clklock); } -static inline struct clk *mpc512x_clk_gated( +static inline struct clk_core *mpc512x_clk_gated( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos) { @@ -266,7 +266,7 @@ static inline struct clk *mpc512x_clk_gated( reg, pos, 0, &clklock); } -static inline struct clk *mpc512x_clk_muxed(const char *name, +static inline struct clk_core *mpc512x_clk_muxed(const char *name, const char **parent_names, int parent_count, u32 __iomem *reg, u8 pos, u8 len) { @@ -422,7 +422,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, int *sys_mul, int *sys_div, int *ips_div) { - struct clk *osc_clk; + struct clk_core *osc_clk; int calc_freq; /* fetch mul/div factors from the hardware */ @@ -432,7 +432,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, *ips_div = get_bit_field(&clkregs->scfr1, 23, 3); /* lookup the oscillator clock for its rate */ - osc_clk = of_clk_get_by_name(np, "osc"); + osc_clk = of_clk_provider_get_by_name(np, "osc"); /* * either descend from OSC to REF (and in bypassing verify the @@ -444,7 +444,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, */ if (!IS_ERR(osc_clk)) { clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); - calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); + calc_freq = clk_provider_get_rate(clks[MPC512x_CLK_REF]); calc_freq *= *sys_mul; calc_freq /= *sys_div; calc_freq /= 2; @@ -647,8 +647,8 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx) * - MCLK 0 enabled * - MCLK 1 from MCLK DIV */ - div = clk_get_rate(clks[MPC512x_CLK_SYS]); - div /= clk_get_rate(clks[MPC512x_CLK_IPS]); + div = clk_provider_get_rate(clks[MPC512x_CLK_SYS]); + div /= clk_provider_get_rate(clks[MPC512x_CLK_IPS]); out_be32(mccr_reg, (0 << 16)); out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17)); out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17)); @@ -925,12 +925,12 @@ static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq) * claimed by any peripheral driver, to not have the clock * subsystem disable them late at startup */ - clk_prepare_enable(clks[MPC512x_CLK_DUMMY]); - clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ - clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ - clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ - clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ - clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DUMMY]); + clk_provider_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ + clk_provider_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ } /* @@ -969,9 +969,9 @@ static void mpc5121_clk_provide_migration_support(void) * has attached to bridges, otherwise the PCI clock remains * unused and so it gets disabled */ - clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ + clk_provider_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci")) - clk_prepare_enable(clks[MPC512x_CLK_PCI]); + clk_provider_prepare_enable(clks[MPC512x_CLK_PCI]); } /* @@ -988,8 +988,8 @@ static void mpc5121_clk_provide_migration_support(void) } while (0) #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \ - struct clk *clk; \ - clk = of_clk_get_by_name(np, clkname); \ + struct clk_core *clk; \ + clk = of_clk_provider_get_by_name(np, clkname); \ if (IS_ERR(clk)) { \ clk = clkitem; \ clk_register_clkdev(clk, clkname, devname); \ @@ -999,7 +999,7 @@ static void mpc5121_clk_provide_migration_support(void) pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \ clkname, devname, clk); \ } else { \ - clk_put(clk); \ + __clk_put(clk); \ } \ } while (0) @@ -1090,7 +1090,7 @@ static void mpc5121_clk_provide_backwards_compat(void) * workaround obsolete */ if (did_register & DID_REG_I2C) - clk_prepare_enable(clks[MPC512x_CLK_I2C]); + clk_provider_prepare_enable(clks[MPC512x_CLK_I2C]); FOR_NODES("fsl,mpc5121-diu") { NODE_PREP; diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 59fa3cc..11bcdb1 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -138,7 +138,7 @@ static const struct clk_ops main_osc_ops = { .is_prepared = clk_main_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -147,7 +147,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, { int ret; struct clk_main_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !parent_name) @@ -192,7 +192,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; const char *name = np->name; const char *parent_name; @@ -291,7 +291,7 @@ static const struct clk_ops main_rc_osc_ops = { .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_rc_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -299,7 +299,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, { int ret; struct clk_main_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !frequency) @@ -340,7 +340,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; u32 frequency = 0; u32 accuracy = 0; @@ -424,13 +424,13 @@ static const struct clk_ops rm9200_main_ops = { .recalc_rate = clk_rm9200_main_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_rm9200_main(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_rm9200_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -462,7 +462,7 @@ at91_clk_register_rm9200_main(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -555,7 +555,7 @@ static const struct clk_ops sam9x5_main_ops = { .get_parent = clk_sam9x5_main_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_main(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -564,7 +564,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, { int ret; struct clk_sam9x5_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name) @@ -607,7 +607,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; unsigned int irq; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index c1af80b..95ae1b6 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -131,7 +131,7 @@ static const struct clk_ops master_ops = { .get_parent = clk_master_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, const char *name, int num_parents, const char **parent_names, @@ -140,7 +140,7 @@ at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, { int ret; struct clk_master *master; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !num_parents || !parent_names) @@ -216,7 +216,7 @@ static void __init of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc, const struct clk_master_layout *layout) { - struct clk *clk; + struct clk_core *clk; int num_parents; int i; unsigned int irq; diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 597fed4..cdf8e8a 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -100,12 +100,12 @@ static const struct clk_ops peripheral_ops = { .is_enabled = clk_peripheral_is_enabled, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id) { struct clk_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX) @@ -134,7 +134,7 @@ at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) { - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; int shift = 0; @@ -309,13 +309,13 @@ static const struct clk_ops sam9x5_peripheral_ops = { .set_rate = clk_sam9x5_peripheral_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id, const struct clk_range *range) { struct clk_sam9x5_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name) @@ -352,7 +352,7 @@ of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type) { int num; u32 id; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name; struct device_node *periphclknp; diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index cf6ed02..0d22f65f 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -297,14 +297,14 @@ static const struct clk_ops pll_ops = { .set_rate = clk_pll_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; int offset = PLL_REG(id); @@ -474,7 +474,7 @@ of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc, { u32 id; unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; struct clk_pll_characteristics *characteristics; diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index ea22656..f8204d8 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -79,12 +79,12 @@ static const struct clk_ops plldiv_ops = { .set_rate = clk_plldiv_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_plldiv *plldiv; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); @@ -111,7 +111,7 @@ at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, static void __init of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 62e2509..b72e98c 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -57,9 +57,9 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, static long clk_programmable_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { - struct clk *parent = NULL; + struct clk_core *parent = NULL; long best_rate = -EINVAL; unsigned long parent_rate; unsigned long tmp_rate; @@ -169,14 +169,14 @@ static const struct clk_ops programmable_ops = { .set_rate = clk_programmable_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_programmable(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout) { struct clk_programmable *prog; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (id > PROG_ID_MAX) @@ -229,7 +229,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc, int num; u32 id; int i; - struct clk *clk; + struct clk_core *clk; int num_parents; const char *parent_names[PROG_SOURCE_MAX]; const char *name; diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index 0300c46..d50fe02 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -117,7 +117,7 @@ static const struct clk_ops slow_osc_ops = { .is_prepared = clk_slow_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const char *parent_name, @@ -125,7 +125,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, bool bypass) { struct clk_slow_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_name) @@ -159,7 +159,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 startup; @@ -229,7 +229,7 @@ static const struct clk_ops slow_rc_osc_ops = { .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_rc_osc(void __iomem *sckcr, const char *name, unsigned long frequency, @@ -237,7 +237,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, unsigned long startup) { struct clk_slow_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name) @@ -269,7 +269,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; u32 frequency = 0; u32 accuracy = 0; u32 startup = 0; @@ -327,14 +327,14 @@ static const struct clk_ops sam9x5_slow_ops = { .get_parent = clk_sam9x5_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_slow(void __iomem *sckcr, const char *name, const char **parent_names, int num_parents) { struct clk_sam9x5_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_names || !num_parents) @@ -364,7 +364,7 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; @@ -401,14 +401,14 @@ static const struct clk_ops sam9260_slow_ops = { .get_parent = clk_sam9260_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9260_slow(struct at91_pmc *pmc, const char *name, const char **parent_names, int num_parents) { struct clk_sam9260_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -440,7 +440,7 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc, void __init of_at91sam9260_clk_slow_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index 144d47e..8820b84 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -113,12 +113,12 @@ static const struct clk_ops at91sam9x5_smd_ops = { .set_rate = at91sam9x5_clk_smd_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_smd *smd; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; smd = kzalloc(sizeof(*smd), GFP_KERNEL); @@ -144,7 +144,7 @@ at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[SMD_SOURCE_MAX]; diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 8c96307..770d9bf 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -99,12 +99,12 @@ static const struct clk_ops system_ops = { .is_prepared = clk_system_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_system(struct at91_pmc *pmc, const char *name, const char *parent_name, u8 id, int irq) { struct clk_system *sys; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; @@ -153,7 +153,7 @@ of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc) int num; int irq = 0; u32 id; - struct clk *clk; + struct clk_core *clk; const char *name; struct device_node *sysclknp; const char *parent_name; diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 7d1d26a..246989c 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -162,12 +162,12 @@ static const struct clk_ops at91sam9n12_usb_ops = { .set_rate = at91sam9x5_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -190,12 +190,12 @@ at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, return clk; } -static struct clk * __init +static struct clk_core * __init at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -295,12 +295,12 @@ static const struct clk_ops at91rm9200_usb_ops = { .set_rate = at91rm9200_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name, const u32 *divisors) { struct at91rm9200_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -327,7 +327,7 @@ at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[USB_SOURCE_MAX]; @@ -355,7 +355,7 @@ void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -375,7 +375,7 @@ void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, void __init of_at91rm9200_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 divisors[4] = {0, 0, 0, 0}; diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index ae3263b..0502050 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -92,13 +92,13 @@ static const struct clk_ops utmi_ops = { .recalc_rate = clk_utmi_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name) { int ret; struct clk_utmi *utmi; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; utmi = kzalloc(sizeof(*utmi), GFP_KERNEL); @@ -132,7 +132,7 @@ static void __init of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc) { unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c index e5aeded..122e7b0 100644 --- a/drivers/clk/bcm/clk-kona-setup.c +++ b/drivers/clk/bcm/clk-kona-setup.c @@ -697,7 +697,7 @@ static void bcm_clk_teardown(struct kona_clk *bcm_clk) bcm_clk->type = bcm_clk_none; } -static void kona_clk_teardown(struct clk *clk) +static void kona_clk_teardown(struct clk_core *clk) { struct clk_hw *hw; struct kona_clk *bcm_clk; @@ -716,10 +716,10 @@ static void kona_clk_teardown(struct clk *clk) bcm_clk_teardown(bcm_clk); } -struct clk *kona_clk_setup(struct kona_clk *bcm_clk) +struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk) { struct clk_init_data *init_data = &bcm_clk->init_data; - struct clk *clk = NULL; + struct clk_core *clk = NULL; switch (bcm_clk->type) { case bcm_clk_peri: diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c index 95af2e6..a301aa9 100644 --- a/drivers/clk/bcm/clk-kona.c +++ b/drivers/clk/bcm/clk-kona.c @@ -1032,11 +1032,11 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate, } static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *best_parent_rate, struct clk **best_parent) + unsigned long *best_parent_rate, struct clk_core **best_parent) { struct kona_clk *bcm_clk = to_kona_clk(hw); - struct clk *clk = hw->clk; - struct clk *current_parent; + struct clk_core *clk = hw->clk; + struct clk_core *current_parent; unsigned long parent_rate; unsigned long best_delta; unsigned long best_rate; @@ -1053,14 +1053,14 @@ static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, return kona_peri_clk_round_rate(hw, rate, best_parent_rate); /* Unless we can do better, stick with current parent */ - current_parent = clk_get_parent(clk); + current_parent = clk_provider_get_parent(clk); parent_rate = __clk_get_rate(current_parent); best_rate = kona_peri_clk_round_rate(hw, rate, &parent_rate); best_delta = abs(best_rate - rate); /* Check whether any other parent clock can produce a better result */ for (which = 0; which < parent_count; which++) { - struct clk *parent = clk_get_parent_by_index(clk, which); + struct clk_core *parent = clk_get_parent_by_index(clk, which); unsigned long delta; unsigned long other_rate; @@ -1260,7 +1260,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu) { unsigned long flags; unsigned int which; - struct clk **clks = ccu->clk_data.clks; + struct clk_core **clks = ccu->clk_data.clks; bool success = true; flags = ccu_lock(ccu); diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h index 2537b30..c2d0152 100644 --- a/drivers/clk/bcm/clk-kona.h +++ b/drivers/clk/bcm/clk-kona.h @@ -508,7 +508,7 @@ extern u64 scaled_div_max(struct bcm_clk_div *div); extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths); -extern struct clk *kona_clk_setup(struct kona_clk *bcm_clk); +extern struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk); extern void __init kona_dt_ccu_setup(struct ccu_data *ccu, struct device_node *node); extern bool __init kona_ccu_init(struct ccu_data *ccu); diff --git a/drivers/clk/berlin/berlin2-avpll.c b/drivers/clk/berlin/berlin2-avpll.c index fd0f26c..488d986 100644 --- a/drivers/clk/berlin/berlin2-avpll.c +++ b/drivers/clk/berlin/berlin2-avpll.c @@ -188,7 +188,7 @@ static const struct clk_ops berlin2_avpll_vco_ops = { .recalc_rate = berlin2_avpll_vco_recalc_rate, }; -struct clk * __init berlin2_avpll_vco_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags) { @@ -364,7 +364,7 @@ static const struct clk_ops berlin2_avpll_channel_ops = { */ static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 }; -struct clk * __init berlin2_avpll_channel_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags) { diff --git a/drivers/clk/berlin/berlin2-avpll.h b/drivers/clk/berlin/berlin2-avpll.h index a37f506..216eee7 100644 --- a/drivers/clk/berlin/berlin2-avpll.h +++ b/drivers/clk/berlin/berlin2-avpll.h @@ -24,11 +24,11 @@ struct clk; #define BERLIN2_AVPLL_BIT_QUIRK BIT(0) #define BERLIN2_AVPLL_SCRAMBLE_QUIRK BIT(1) -struct clk * __init +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags); -struct clk * __init +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags); diff --git a/drivers/clk/berlin/berlin2-div.c b/drivers/clk/berlin/berlin2-div.c index 81ff97f..c673082 100644 --- a/drivers/clk/berlin/berlin2-div.c +++ b/drivers/clk/berlin/berlin2-div.c @@ -234,7 +234,7 @@ static const struct clk_ops berlin2_div_mux_ops = { .get_parent = berlin2_div_get_parent, }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-div.h b/drivers/clk/berlin/berlin2-div.h index 15e3384..3ddb87a 100644 --- a/drivers/clk/berlin/berlin2-div.h +++ b/drivers/clk/berlin/berlin2-div.h @@ -80,7 +80,7 @@ struct berlin2_div_data { u8 div_flags; }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-pll.c b/drivers/clk/berlin/berlin2-pll.c index bdc506b..b7a3016 100644 --- a/drivers/clk/berlin/berlin2-pll.c +++ b/drivers/clk/berlin/berlin2-pll.c @@ -91,7 +91,7 @@ static const struct clk_ops berlin2_pll_ops = { .recalc_rate = berlin2_pll_recalc_rate, }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags) diff --git a/drivers/clk/berlin/berlin2-pll.h b/drivers/clk/berlin/berlin2-pll.h index 8831ce2..6b6a6ed 100644 --- a/drivers/clk/berlin/berlin2-pll.h +++ b/drivers/clk/berlin/berlin2-pll.h @@ -29,7 +29,7 @@ struct berlin2_pll_map { u8 divsel_shift; }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags); diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c index 4c81e09..1329721 100644 --- a/drivers/clk/berlin/bg2.c +++ b/drivers/clk/berlin/bg2.c @@ -93,7 +93,7 @@ */ #define MAX_CLKS 41 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -504,7 +504,7 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = { static void __init berlin2_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; u8 avpll_flags = 0; int n; @@ -513,16 +513,16 @@ static void __init berlin2_clock_setup(struct device_node *np) return; /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } - clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]); + clk = of_clk_provider_get_by_name(np, clk_names[VIDEO_EXT0]); if (!IS_ERR(clk)) { clk_names[VIDEO_EXT0] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c index 748da9b..0b251bd 100644 --- a/drivers/clk/berlin/bg2q.c +++ b/drivers/clk/berlin/bg2q.c @@ -47,7 +47,7 @@ #define REG_SDIO1XIN_CLKCTL 0x015c #define MAX_CLKS 27 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -293,7 +293,7 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = { static void __init berlin2q_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; int n; gbase = of_iomap(np, 0); @@ -311,10 +311,10 @@ static void __init berlin2q_clock_setup(struct device_node *np) } /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 1127ee4..4b64834 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -489,7 +489,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) const char *parent_name; const char *clk_name; struct resource *mem; - struct clk *clk; + struct clk_core *clk; if (!pdev->dev.of_node) return -ENODEV; diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c index d2f1e11..3dc6e58 100644 --- a/drivers/clk/clk-axm5516.c +++ b/drivers/clk/clk-axm5516.c @@ -532,7 +532,7 @@ MODULE_DEVICE_TABLE(of, axmclk_match_table); struct axmclk_priv { struct clk_onecell_data onecell; - struct clk *clks[]; + struct clk_core *clks[]; }; static int axmclk_probe(struct platform_device *pdev) @@ -541,7 +541,7 @@ static int axmclk_probe(struct platform_device *pdev) struct resource *res; int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct regmap *regmap; size_t num_clks; struct axmclk_priv *priv; diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c index 6b950ca..f25e85e 100644 --- a/drivers/clk/clk-bcm2835.c +++ b/drivers/clk/clk-bcm2835.c @@ -29,7 +29,7 @@ */ void __init bcm2835_init_clocks(void) { - struct clk *clk; + struct clk_core *clk; int ret; clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT, diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index b9355da..a812a56 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -57,14 +57,14 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_composite *composite = to_clk_composite(hw); const struct clk_ops *rate_ops = composite->rate_ops; const struct clk_ops *mux_ops = composite->mux_ops; struct clk_hw *rate_hw = composite->rate_hw; struct clk_hw *mux_hw = composite->mux_hw; - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; long tmp_rate, best_rate = 0; unsigned long rate_diff; @@ -80,7 +80,7 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, *best_parent_p = NULL; if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) { - *best_parent_p = clk_get_parent(mux_hw->clk); + *best_parent_p = clk_provider_get_parent(mux_hw->clk); *best_parent_rate = __clk_get_rate(*best_parent_p); return rate_ops->round_rate(rate_hw, rate, @@ -181,14 +181,14 @@ static void clk_composite_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } -struct clk *clk_register_composite(struct device *dev, const char *name, +struct clk_core *clk_register_composite(struct device *dev, const char *name, const char **parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct clk_composite *composite; struct clk_ops *clk_composite_ops; diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index d36a7b3..a7d3a48 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -20,7 +20,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) { struct of_phandle_args clkspec; int index, rc, num_parents; - struct clk *clk, *pclk; + struct clk_core *clk, *pclk; num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", "#clock-cells"); @@ -63,16 +63,16 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) goto err; } - rc = clk_set_parent(clk, pclk); + rc = clk_provider_set_parent(clk, pclk); if (rc < 0) pr_err("clk: failed to reparent %s to %s: %d\n", __clk_get_name(clk), __clk_get_name(pclk), rc); - clk_put(clk); - clk_put(pclk); + __clk_put(clk); + __clk_put(pclk); } return 0; err: - clk_put(pclk); + __clk_put(pclk); return rc; } @@ -82,7 +82,7 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) struct property *prop; const __be32 *cur; int rc, index = 0; - struct clk *clk; + struct clk_core *clk; u32 rate; of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) { @@ -106,11 +106,11 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) return PTR_ERR(clk); } - rc = clk_set_rate(clk, rate); + rc = clk_provider_set_rate(clk, rate); if (rc < 0) pr_err("clk: couldn't set %s clock rate: %d\n", __clk_get_name(clk), rc); - clk_put(clk); + __clk_put(clk); } index++; } diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 18a9de2..3c78139 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -366,14 +366,14 @@ const struct clk_ops clk_divider_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_divider_ro_ops); -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -429,7 +429,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_divider(struct device *dev, const char *name, +struct clk_core *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock) @@ -453,7 +453,7 @@ EXPORT_SYMBOL_GPL(clk_register_divider); * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ -struct clk *clk_register_divider_table(struct device *dev, const char *name, +struct clk_core *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c index bac2ddf..26e0485 100644 --- a/drivers/clk/clk-efm32gg.c +++ b/drivers/clk/clk-efm32gg.c @@ -16,7 +16,7 @@ #define CMU_HFPERCLKEN0 0x44 -static struct clk *clk[37]; +static struct clk_core *clk[37]; static struct clk_onecell_data clk_data = { .clks = clk, .clk_num = ARRAY_SIZE(clk), diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index d9e3f67..ae1fef0 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -65,13 +65,13 @@ struct clk_ops clk_fixed_factor_ops = { }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { struct clk_fixed_factor *fix; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fix = kmalloc(sizeof(*fix), GFP_KERNEL); if (!fix) { @@ -105,7 +105,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_factor); */ void __init of_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index 0fc56ab..56c0ced 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -56,12 +56,12 @@ EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, +struct clk_core *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy) { struct clk_fixed_rate *fixed; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate fixed-rate clock */ @@ -99,7 +99,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy); * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate) { @@ -114,7 +114,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate); */ void of_fixed_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; u32 rate; u32 accuracy = 0; diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index ede685c..8104683 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -96,14 +96,14 @@ const struct clk_ops clk_fractional_divider_ops = { }; EXPORT_SYMBOL_GPL(clk_fractional_divider_ops); -struct clk *clk_register_fractional_divider(struct device *dev, +struct clk_core *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock) { struct clk_fractional_divider *fd; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fd = kzalloc(sizeof(*fd), GFP_KERNEL); if (!fd) { diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 4a58c55..429d302 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -118,13 +118,13 @@ EXPORT_SYMBOL_GPL(clk_gate_ops); * @clk_gate_flags: gate-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_gate(struct device *dev, const char *name, +struct clk_core *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clk_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 2e7e9d9..cad2fba 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -271,10 +271,10 @@ static const struct clk_ops periclk_ops = { .set_rate = clk_periclk_set_rate, }; -static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops) +static __init struct clk_core *hb_clk_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct hb_clk *hb_clk; const char *clk_name = node->name; const char *parent_name; @@ -330,8 +330,8 @@ CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init); static void __init hb_a9bus_init(struct device_node *node) { - struct clk *clk = hb_clk_init(node, &a9bclk_ops); - clk_prepare_enable(clk); + struct clk_core *clk = hb_clk_init(node, &a9bclk_ops); + clk_provider_prepare_enable(clk); } CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init); diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c index f20b750..796043c 100644 --- a/drivers/clk/clk-ls1x.c +++ b/drivers/clk/clk-ls1x.c @@ -48,11 +48,11 @@ static const struct clk_ops ls1x_pll_clk_ops = { .recalc_rate = ls1x_pll_recalc_rate, }; -static struct clk * __init clk_register_pll(struct device *dev, +static struct clk_core * __init clk_register_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags) { struct clk_hw *hw; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the divider */ @@ -80,32 +80,32 @@ static struct clk * __init clk_register_pll(struct device *dev, void __init ls1x_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk = clk_register_divider(NULL, "cpu_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT, DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "cpu", NULL); clk = clk_register_divider(NULL, "dc_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "dc", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "ahb", NULL); clk_register_clkdev(clk, "stmmaceth", NULL); clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "apb", NULL); clk_register_clkdev(clk, "serial8250", NULL); } diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 3d7e8dd..42fa43a 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -112,10 +112,10 @@ static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = { }, }; -static struct clk *max77686_clk_register(struct device *dev, +static struct clk_core *max77686_clk_register(struct device *dev, struct max77686_clk *max77686) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *hw = &max77686->hw; clk = clk_register(dev, hw); @@ -138,10 +138,10 @@ static int max77686_clk_probe(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct max77686_clk *max77686_clks[MAX77686_CLKS_NUM]; - struct clk **clocks; + struct clk_core **clocks; int i, ret; - clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk *) + clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * MAX77686_CLKS_NUM, GFP_KERNEL); if (!clocks) return -ENOMEM; @@ -203,7 +203,7 @@ err_clocks: static int max77686_clk_remove(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); - struct clk **clocks = platform_get_drvdata(pdev); + struct clk_core **clocks = platform_get_drvdata(pdev); int i; if (iodev->dev->of_node) diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c index 30a3b69..c503c09 100644 --- a/drivers/clk/clk-moxart.c +++ b/drivers/clk/clk-moxart.c @@ -18,7 +18,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *ref_clk; + struct clk_core *clk, *ref_clk; unsigned int mul; const char *name = node->name; const char *parent_name; @@ -35,7 +35,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) mul = readl(base + 0x30) >> 3 & 0x3f; iounmap(base); - ref_clk = of_clk_get(node, 0); + ref_clk = of_clk_provider_get(node, 0); if (IS_ERR(ref_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; @@ -56,7 +56,7 @@ CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock", void __init moxart_of_apb_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *pll_clk; + struct clk_core *clk, *pll_clk; unsigned int div, val; unsigned int div_idx[] = { 2, 3, 4, 6, 8}; const char *name = node->name; @@ -78,7 +78,7 @@ void __init moxart_of_apb_clk_init(struct device_node *node) val = 0; div = div_idx[val] * 2; - pll_clk = of_clk_get(node, 0); + pll_clk = of_clk_provider_get(node, 0); if (IS_ERR(pll_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 4f96ff3..2879053 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -113,13 +113,13 @@ const struct clk_ops clk_mux_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_mux_ro_ops); -struct clk *clk_register_mux_table(struct device *dev, const char *name, +struct clk_core *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; u8 width = 0; @@ -165,7 +165,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, } EXPORT_SYMBOL_GPL(clk_register_mux_table); -struct clk *clk_register_mux(struct device *dev, const char *name, +struct clk_core *clk_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock) diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 05e04ce..5d87366 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -254,11 +254,11 @@ static const struct clk_ops pll_clk_ops = { .recalc_rate = pll_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init pll_clk_register(struct device *dev, const char *name, const char *parent_name, u32 id) { - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll; struct clk_init_data init; @@ -346,11 +346,11 @@ static const struct clk_ops src_clk_ops = { .recalc_rate = src_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init src_clk_register(struct device *dev, const char *name, const char *parent_name, u8 id) { - struct clk *clk; + struct clk_core *clk; struct clk_src *sclk; struct clk_init_data init; @@ -510,7 +510,7 @@ module_init(nomadik_src_clk_init_debugfs); static void __init of_nomadik_pll_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 pll_id; @@ -533,7 +533,7 @@ CLK_OF_DECLARE(nomadik_pll_clk, static void __init of_nomadik_hclk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; @@ -557,7 +557,7 @@ CLK_OF_DECLARE(nomadik_hclk_clk, static void __init of_nomadik_src_clk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 clk_id; diff --git a/drivers/clk/clk-nspire.c b/drivers/clk/clk-nspire.c index a378db7..e9c43f4 100644 --- a/drivers/clk/clk-nspire.c +++ b/drivers/clk/clk-nspire.c @@ -69,7 +69,7 @@ static void __init nspire_ahbdiv_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; struct nspire_clk_info info; @@ -111,7 +111,7 @@ static void __init nspire_clk_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct nspire_clk_info info; diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c index 8e58edf..5619ee9 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-ppc-corenet.c @@ -64,7 +64,7 @@ const struct clk_ops cmux_ops = { static void __init core_mux_init(struct device_node *np) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct cmux_clk *cmux_clk; struct device_node *node; @@ -150,7 +150,7 @@ static void __init core_pll_init(struct device_node *np) int i, rc, count; const char *clk_name, *parent_name; struct clk_onecell_data *onecell_data; - struct clk **subclks; + struct clk_core **subclks; void __iomem *base; base = of_iomap(np, 0); @@ -184,7 +184,7 @@ static void __init core_pll_init(struct device_node *np) /* output clock number per PLL */ clocks_per_pll = count; - subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); + subclks = kzalloc(sizeof(struct clk_core *) * count, GFP_KERNEL); if (!subclks) { pr_err("%s: could not allocate subclks\n", __func__); goto err_map; @@ -246,7 +246,7 @@ err_map: static void __init sysclk_init(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct device_node *np = of_get_parent(node); u32 rate; diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index b7797fb..17fc7e1 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -29,7 +29,7 @@ #define s2mps11_name(a) (a->hw.init->name) -static struct clk **clk_table; +static struct clk_core **clk_table; static struct clk_onecell_data clk_data; enum { @@ -43,7 +43,7 @@ struct s2mps11_clk { struct sec_pmic_dev *iodev; struct device_node *clk_np; struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_lookup *lookup; u32 mask; unsigned int reg; @@ -174,7 +174,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev) s2mps11_clk = s2mps11_clks; - clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk *) * + clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * S2MPS11_CLKS_NUM, GFP_KERNEL); if (!clk_table) return -ENOMEM; diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 3b2a66f..57c9eb5 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -56,10 +56,10 @@ struct si5351_driver_data { struct regmap *regmap; struct clk_onecell_data onecell; - struct clk *pxtal; + struct clk_core *pxtal; const char *pxtal_name; struct clk_hw xtal; - struct clk *pclkin; + struct clk_core *pclkin; const char *pclkin_name; struct clk_hw clkin; @@ -1128,12 +1128,12 @@ static int si5351_dt_parse(struct i2c_client *client, if (!pdata) return -ENOMEM; - pdata->clk_xtal = of_clk_get(np, 0); + pdata->clk_xtal = of_clk_provider_get(np, 0); if (!IS_ERR(pdata->clk_xtal)) - clk_put(pdata->clk_xtal); - pdata->clk_clkin = of_clk_get(np, 1); + __clk_put(pdata->clk_xtal); + pdata->clk_clkin = of_clk_provider_get(np, 1); if (!IS_ERR(pdata->clk_clkin)) - clk_put(pdata->clk_clkin); + __clk_put(pdata->clk_clkin); /* * property silabs,pll-source : <num src>, [<..>] @@ -1306,7 +1306,7 @@ static int si5351_i2c_probe(struct i2c_client *client, struct si5351_platform_data *pdata; struct si5351_driver_data *drvdata; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; const char *parent_names[4]; u8 num_parents, num_clocks; int ret, n; @@ -1545,7 +1545,8 @@ static int si5351_i2c_probe(struct i2c_client *client, /* set initial clkout rate */ if (pdata->clkout[n].rate != 0) { int ret; - ret = clk_set_rate(clk, pdata->clkout[n].rate); + ret = clk_provider_set_rate(clk, + pdata->clkout[n].rate); if (ret != 0) { dev_err(&client->dev, "Cannot set rate : %d\n", ret); diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c index fc167b3..f0eec4e 100644 --- a/drivers/clk/clk-si570.c +++ b/drivers/clk/clk-si570.c @@ -407,7 +407,7 @@ static int si570_probe(struct i2c_client *client, { struct clk_si570 *data; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; u32 initial_fout, factory_fout, stability; int err; enum clk_si570_variant variant = id->driver_data; @@ -476,7 +476,7 @@ static int si570_probe(struct i2c_client *client, /* Read the requested initial output frequency from device tree */ if (!of_property_read_u32(client->dev.of_node, "clock-frequency", &initial_fout)) { - err = clk_set_rate(clk, initial_fout); + err = clk_provider_set_rate(clk, initial_fout); if (err) { of_clk_del_provider(client->dev.of_node); return err; diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c index 1ada79a..2422857 100644 --- a/drivers/clk/clk-twl6040.c +++ b/drivers/clk/clk-twl6040.c @@ -31,7 +31,7 @@ struct twl6040_clk { struct twl6040 *twl6040; struct device *dev; struct clk_hw mcpdm_fclk; - struct clk *clk; + struct clk_core *clk; int enabled; }; diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index 406bfc1..7e9ec00 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -688,7 +688,7 @@ static const struct clk_ops syscon_clk_ops = { .set_rate = syscon_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init syscon_clk_register(struct device *dev, const char *name, const char *parent_name, unsigned long flags, bool hw_ctrld, @@ -696,7 +696,7 @@ syscon_clk_register(struct device *dev, const char *name, void __iomem *en_reg, u8 en_bit, u16 clk_val) { - struct clk *clk; + struct clk_core *clk; struct clk_syscon *sclk; struct clk_init_data init; @@ -867,7 +867,7 @@ static struct u300_clock const u300_clk_lookup[] __initconst = { static void __init of_u300_syscon_clk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; void __iomem *res_reg; @@ -1110,11 +1110,11 @@ static const struct clk_ops mclk_ops = { .set_rate = mclk_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init mclk_clk_register(struct device *dev, const char *name, const char *parent_name, bool is_mspro) { - struct clk *clk; + struct clk_core *clk; struct clk_mclk *mclk; struct clk_init_data init; @@ -1141,7 +1141,7 @@ mclk_clk_register(struct device *dev, const char *name, static void __init of_u300_syscon_mclk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index 37e9288..e5fb933 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -232,7 +232,7 @@ static const struct clk_ops vt8500_gated_divisor_clk_ops = { static __init void vtwm_device_clk_init(struct device_node *node) { u32 en_reg, div_reg; - struct clk *clk; + struct clk_core *clk; struct clk_device *dev_clk; const char *clk_name = node->name; const char *parent_name; @@ -650,7 +650,7 @@ static const struct clk_ops vtwm_pll_ops = { static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c index b131041..d2d745e 100644 --- a/drivers/clk/clk-wm831x.c +++ b/drivers/clk/clk-wm831x.c @@ -25,9 +25,9 @@ struct wm831x_clk { struct clk_hw xtal_hw; struct clk_hw fll_hw; struct clk_hw clkout_hw; - struct clk *xtal; - struct clk *fll; - struct clk *clkout; + struct clk_core *xtal; + struct clk_core *fll; + struct clk_core *clkout; bool xtal_ena; }; diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index dd8a62d..ce3ed34 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -124,13 +124,13 @@ const struct clk_ops xgene_clk_pll_ops = { .recalc_rate = xgene_clk_pll_recalc_rate, }; -static struct clk *xgene_register_clk_pll(struct device *dev, +static struct clk_core *xgene_register_clk_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 pll_offset, u32 type, spinlock_t *lock) { struct xgene_clk_pll *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the APM clock structure */ @@ -166,7 +166,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev, static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; void *reg; reg = of_iomap(np, 0); @@ -395,12 +395,12 @@ const struct clk_ops xgene_clk_ops = { .round_rate = xgene_clk_round_rate, }; -static struct clk *xgene_register_clk(struct device *dev, +static struct clk_core *xgene_register_clk(struct device *dev, const char *name, const char *parent_name, struct xgene_dev_parameters *parameters, spinlock_t *lock) { struct xgene_clk *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int rc; @@ -442,7 +442,7 @@ static struct clk *xgene_register_clk(struct device *dev, static void __init xgene_devclk_init(struct device_node *np) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; struct resource res; int rc; struct xgene_dev_parameters parameters; diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h index c798138..d278572 100644 --- a/drivers/clk/clk.h +++ b/drivers/clk/clk.h @@ -10,8 +10,8 @@ */ #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) -struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); -struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec); +struct clk_core *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); +struct clk_core *__of_clk_get_from_provider(struct of_phandle_args *clkspec); void of_clk_lock(void); void of_clk_unlock(void); #endif diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 339945d..d7d3667 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -296,7 +296,7 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw, static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_mmc *mclk = to_mmc(hw); unsigned long best = 0; @@ -427,11 +427,11 @@ static struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, +static struct clk_core *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, void __iomem *base, struct device_node *np) { struct clk_mmc *mclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; mclk = kzalloc(sizeof(*mclk), GFP_KERNEL); @@ -487,7 +487,7 @@ static void __init hi3620_mmc_clk_init(struct device_node *node) if (WARN_ON(!clk_data)) return; - clk_data->clks = kzalloc(sizeof(struct clk *) * num, GFP_KERNEL); + clk_data->clks = kzalloc(sizeof(struct clk_core *) * num, GFP_KERNEL); if (!clk_data->clks) { pr_err("%s: fail to allocate mmc clk\n", __func__); return; diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index a078e84..3fcd2ba 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -42,7 +42,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, int nr_clks) { struct hisi_clock_data *clk_data; - struct clk **clk_table; + struct clk_core **clk_table; void __iomem *base; if (np) { @@ -63,7 +63,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, } clk_data->base = base; - clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); + clk_table = kzalloc(sizeof(struct clk_core *) * nr_clks, GFP_KERNEL); if (!clk_table) { pr_err("%s: could not allocate clock lookup table\n", __func__); goto err_data; @@ -81,7 +81,7 @@ err: void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -102,7 +102,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -122,7 +122,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -151,7 +151,7 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -180,7 +180,7 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -208,7 +208,7 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..f7fc4b9 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -90,7 +90,7 @@ struct hisi_gate_clock { const char *alias; }; -struct clk *hisi_register_clkgate_sep(struct device *, const char *, +struct clk_core *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, u8, spinlock_t *); diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index b03d5a7..61f7236 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -96,14 +96,14 @@ static struct clk_ops clkgate_separated_ops = { .is_enabled = clkgate_separated_is_enabled, }; -struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, +struct clk_core *hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clkgate_separated *sclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c index 86f1e36..3f7db44 100644 --- a/drivers/clk/keystone/gate.c +++ b/drivers/clk/keystone/gate.c @@ -163,7 +163,7 @@ static const struct clk_ops clk_psc_ops = { * @psc_data: platform data to configure this clock * @lock: spinlock used by this clock */ -static struct clk *clk_register_psc(struct device *dev, +static struct clk_core *clk_register_psc(struct device *dev, const char *name, const char *parent_name, struct clk_psc_data *psc_data, @@ -171,7 +171,7 @@ static struct clk *clk_register_psc(struct device *dev, { struct clk_init_data init; struct clk_psc *psc; - struct clk *clk; + struct clk_core *clk; psc = kzalloc(sizeof(*psc), GFP_KERNEL); if (!psc) @@ -204,7 +204,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) const char *clk_name = node->name; const char *parent_name; struct clk_psc_data *data; - struct clk *clk; + struct clk_core *clk; int i; data = kzalloc(sizeof(*data), GFP_KERNEL); diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 0dd8a4b..fc3156e 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -116,14 +116,14 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pllclk_recalc, }; -static struct clk *clk_register_pll(struct device *dev, +static struct clk_core *clk_register_pll(struct device *dev, const char *name, const char *parent_name, struct clk_pll_data *pll_data) { struct clk_init_data init; struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -158,7 +158,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) { struct clk_pll_data *pll_data; const char *parent_name; - struct clk *clk; + struct clk_core *clk; int i; pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL); @@ -239,7 +239,7 @@ static void __init of_pll_div_clk_init(struct device_node *node) const char *parent_name; void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; of_property_read_string(node, "clock-output-names", &clk_name); @@ -282,7 +282,7 @@ static void __init of_pll_mux_clk_init(struct device_node *node) { void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *parents[2]; const char *clk_name = node->name; diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c index d14120e..4ca8713 100644 --- a/drivers/clk/mmp/clk-apbc.c +++ b/drivers/clk/mmp/clk-apbc.c @@ -120,12 +120,12 @@ struct clk_ops clk_apbc_ops = { .unprepare = clk_apbc_unprepare, }; -struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock) { struct clk_apbc *apbc; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apbc = kzalloc(sizeof(*apbc), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c index abe182b..c24e6e7 100644 --- a/drivers/clk/mmp/clk-apmu.c +++ b/drivers/clk/mmp/clk-apmu.c @@ -66,11 +66,11 @@ struct clk_ops clk_apmu_ops = { .disable = clk_apmu_disable, }; -struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock) { struct clk_apmu *apmu; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apmu = kzalloc(sizeof(*apmu), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c index 23a56f5..0386cdd 100644 --- a/drivers/clk/mmp/clk-frac.c +++ b/drivers/clk/mmp/clk-frac.c @@ -116,14 +116,14 @@ static struct clk_ops clk_factor_ops = { .set_rate = clk_factor_set_rate, }; -struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt) { struct clk_factor *factor; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!masks) { pr_err("%s: must pass a clk_factor_mask\n", __func__); diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c index b2721ca..98bd73f 100644 --- a/drivers/clk/mmp/clk-mmp2.c +++ b/drivers/clk/mmp/clk-mmp2.c @@ -77,8 +77,8 @@ static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"}; void __init mmp2_clk_init(void) { - struct clk *clk; - struct clk *vctcxo; + struct clk_core *clk; + struct clk_core *vctcxo; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -192,7 +192,7 @@ void __init mmp2_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(clk, 14745600); + clk_provider_set_rate(clk, 14745600); clk_register_clkdev(clk, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "vctcxo", @@ -251,7 +251,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -262,7 +262,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -273,7 +273,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", @@ -284,7 +284,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.3", NULL); clk = mmp_clk_register_apbc("uart3", "uart3_mux", diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c index 014396b..e4f50ab 100644 --- a/drivers/clk/mmp/clk-pxa168.c +++ b/drivers/clk/mmp/clk-pxa168.c @@ -68,8 +68,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa168_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -159,7 +159,7 @@ void __init pxa168_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -202,7 +202,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -213,7 +213,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -224,7 +224,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c index 9efc6a4..b5c215e 100644 --- a/drivers/clk/mmp/clk-pxa910.c +++ b/drivers/clk/mmp/clk-pxa910.c @@ -66,8 +66,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa910_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbcp_base; @@ -164,7 +164,7 @@ void __init pxa910_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -207,7 +207,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -218,7 +218,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -229,7 +229,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h index ab86dd4..1477e61 100644 --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h @@ -20,15 +20,15 @@ struct clk_factor_tbl { unsigned int den; }; -extern struct clk *mmp_clk_register_pll2(const char *name, +extern struct clk_core *mmp_clk_register_pll2(const char *name, const char *parent_name, unsigned long flags); -extern struct clk *mmp_clk_register_apbc(const char *name, +extern struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock); -extern struct clk *mmp_clk_register_apmu(const char *name, +extern struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock); -extern struct clk *mmp_clk_register_factor(const char *name, +extern struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt); diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index d1e5863..1be15c4 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -238,7 +238,7 @@ mvebu_corediv_clk_init(struct device_node *node, { struct clk_init_data init; struct clk_corediv *corediv; - struct clk **clks; + struct clk_core **clks; void __iomem *base; const char *parent_name; const char *clk_name; @@ -253,7 +253,7 @@ mvebu_corediv_clk_init(struct device_node *node, clk_data.clk_num = soc_desc->ndescs; /* clks holds the clock array */ - clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), + clks = kcalloc(clk_data.clk_num, sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clks)) goto err_unmap; diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c index 8ebf757..225124b 100644 --- a/drivers/clk/mvebu/clk-cpu.c +++ b/drivers/clk/mvebu/clk-cpu.c @@ -30,7 +30,7 @@ struct cpu_clk { void __iomem *reg_base; }; -static struct clk **clks; +static struct clk_core **clks; static struct clk_onecell_data clk_data; @@ -127,8 +127,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) for_each_node_by_type(dn, "cpu") { struct clk_init_data init; - struct clk *clk; - struct clk *parent_clk; + struct clk_core *clk; + struct clk_core *parent_clk; char *clk_name = kzalloc(5, GFP_KERNEL); int cpu, err; @@ -140,7 +140,7 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out; sprintf(clk_name, "cpu%d", cpu); - parent_clk = of_clk_get(node, 0); + parent_clk = of_clk_provider_get(node, 0); cpuclk[cpu].parent_name = __clk_get_name(parent_clk); cpuclk[cpu].clk_name = clk_name; diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 25ceccf..7e6c320 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -43,7 +43,7 @@ void __init mvebu_coreclk_setup(struct device_node *np, /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; - clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { iounmap(base); @@ -91,13 +91,13 @@ void __init mvebu_coreclk_setup(struct device_node *np, struct clk_gating_ctrl { spinlock_t lock; - struct clk **gates; + struct clk_core **gates; int num_gates; }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) -static struct clk *clk_gating_get_src( +static struct clk_core *clk_gating_get_src( struct of_phandle_args *clkspec, void *data) { struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data; @@ -119,7 +119,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, const struct clk_gating_soc_desc *desc) { struct clk_gating_ctrl *ctrl; - struct clk *clk; + struct clk_core *clk; void __iomem *base; const char *default_parent = NULL; int n; @@ -128,10 +128,10 @@ void __init mvebu_clk_gating_setup(struct device_node *np, if (WARN_ON(!base)) return; - clk = of_clk_get(np, 0); + clk = of_clk_provider_get(np, 0); if (!IS_ERR(clk)) { default_parent = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); @@ -145,7 +145,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, n++; ctrl->num_gates = n; - ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), + ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!ctrl->gates)) goto gates_out; diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c index 90e1da9..57f93e5 100644 --- a/drivers/clk/mxs/clk-div.c +++ b/drivers/clk/mxs/clk-div.c @@ -74,11 +74,11 @@ static struct clk_ops clk_div_ops = { .set_rate = clk_div_set_rate, }; -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_div *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; div = kzalloc(sizeof(*div), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c index e6aa6b5..87083e4 100644 --- a/drivers/clk/mxs/clk-frac.c +++ b/drivers/clk/mxs/clk-frac.c @@ -108,11 +108,11 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; frac = kzalloc(sizeof(*frac), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 9fc9359..fc7fdf2 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -94,7 +94,7 @@ enum imx23_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx23_clk clks_init_on[] __initdata = { @@ -171,7 +171,7 @@ static void __init mx23_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init); diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index a6c3501..083add7 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -148,7 +148,7 @@ enum imx28_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx28_clk clks_init_on[] __initdata = { @@ -250,6 +250,6 @@ static void __init mx28_clocks_init(struct device_node *np) clk_register_clkdev(clks[enet_out], NULL, "enet_out"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init); diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c index fadae41..8e29d79 100644 --- a/drivers/clk/mxs/clk-pll.c +++ b/drivers/clk/mxs/clk-pll.c @@ -86,11 +86,11 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate) { struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 4adeed6..ad1aa00 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -125,11 +125,11 @@ static const struct clk_ops clk_ref_ops = { .set_rate = clk_ref_set_rate, }; -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_ref *ref; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; ref = kzalloc(sizeof(*ref), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h index ef10ad9..b258ea5 100644 --- a/drivers/clk/mxs/clk.h +++ b/drivers/clk/mxs/clk.h @@ -23,24 +23,24 @@ extern spinlock_t mxs_lock; int mxs_clk_wait(void __iomem *reg, u8 shift); -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate); -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -static inline struct clk *mxs_clk_fixed(const char *name, int rate) +static inline struct clk_core *mxs_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mxs_clk_gate(const char *name, +static inline struct clk_core *mxs_clk_gate(const char *name, const char *parent_name, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, @@ -48,7 +48,7 @@ static inline struct clk *mxs_clk_gate(const char *name, &mxs_lock); } -static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *mxs_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parent_names, int num_parents) { return clk_register_mux(NULL, name, parent_names, num_parents, @@ -56,7 +56,7 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, reg, shift, width, 0, &mxs_lock); } -static inline struct clk *mxs_clk_fixed_factor(const char *name, +static inline struct clk_core *mxs_clk_fixed_factor(const char *name, const char *parent_name, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent_name, diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index b638c58..59f118c 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -375,7 +375,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -402,7 +402,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg *rcg = to_clk_rcg(hw); @@ -410,7 +410,7 @@ static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, } static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); @@ -418,7 +418,7 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, } static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg *rcg = to_clk_rcg(hw); const struct freq_tbl *f = rcg->freq_tbl; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index cd185d5..6aac1ec 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -188,7 +188,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -219,7 +219,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -372,7 +372,7 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, } static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -423,7 +423,7 @@ const struct clk_ops clk_edp_pixel_ops = { EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -485,14 +485,14 @@ static const struct frac_entry frac_table_pixel[] = { }; static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); unsigned long request, src_rate; int delta = 100000; const struct freq_tbl *f = rcg->freq_tbl; const struct frac_entry *frac = frac_table_pixel; - struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src); + struct clk_core *parent = *p = clk_get_parent_by_index(hw->clk, f->src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; @@ -519,7 +519,7 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, int delta = 100000; u32 mask = BIT(rcg->hid_width) - 1; u32 hid_div; - struct clk *parent = clk_get_parent_by_index(hw->clk, f.src); + struct clk_core *parent = clk_get_parent_by_index(hw->clk, f.src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; diff --git a/drivers/clk/qcom/clk-regmap.c b/drivers/clk/qcom/clk-regmap.c index a58ba39..2a98040 100644 --- a/drivers/clk/qcom/clk-regmap.c +++ b/drivers/clk/qcom/clk-regmap.c @@ -101,7 +101,7 @@ EXPORT_SYMBOL_GPL(clk_disable_regmap); * clk_regmap struct via this function so that the regmap is initialized * and so that the clock is registered with the common clock framework. */ -struct clk *devm_clk_register_regmap(struct device *dev, +struct clk_core *devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) { if (dev && dev_get_regmap(dev, NULL)) diff --git a/drivers/clk/qcom/clk-regmap.h b/drivers/clk/qcom/clk-regmap.h index 491a63d..89258cb 100644 --- a/drivers/clk/qcom/clk-regmap.h +++ b/drivers/clk/qcom/clk-regmap.h @@ -39,7 +39,7 @@ struct clk_regmap { int clk_is_enabled_regmap(struct clk_hw *hw); int clk_enable_regmap(struct clk_hw *hw); void clk_disable_regmap(struct clk_hw *hw); -struct clk * +struct clk_core * devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk); #endif diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index eeb3eea..afd40ea 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -24,7 +24,7 @@ struct qcom_cc { struct qcom_reset_controller reset; struct clk_onecell_data data; - struct clk *clks[]; + struct clk_core *clks[]; }; struct regmap * @@ -48,9 +48,9 @@ int qcom_cc_really_probe(struct platform_device *pdev, { int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct clk_onecell_data *data; - struct clk **clks; + struct clk_core **clks; struct qcom_reset_controller *reset; struct qcom_cc *cc; size_t num_clks = desc->num_clks; diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c index 0c4b727..2d41fdb 100644 --- a/drivers/clk/qcom/gcc-msm8660.c +++ b/drivers/clk/qcom/gcc-msm8660.c @@ -2718,7 +2718,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); static int gcc_msm8660_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; /* Temporary until RPM clocks supported */ diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 007534f..ed8f8f5 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -3488,7 +3488,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table); static int gcc_msm8960_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; const struct of_device_id *match; diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 7af7c18..8326b1f 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -2699,7 +2699,7 @@ static void msm8974_pro_clock_override(void) static int gcc_msm8974_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; bool pro; const struct of_device_id *id; diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 2e80a21..bb60d61 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -505,7 +505,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) int ret = 0; u32 val; struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); - struct clk *clk = hw->clk; + struct clk_core *clk = hw->clk; int num_parents = __clk_get_num_parents(hw->clk); /* @@ -517,7 +517,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) * needs to be on at what time. */ for (i = 0; i < num_parents; i++) { - ret = clk_prepare_enable(clk_get_parent_by_index(clk, i)); + ret = clk_provider_prepare_enable(clk_get_parent_by_index(clk, i)); if (ret) goto err; } @@ -546,7 +546,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) err: for (i--; i >= 0; i--) - clk_disable_unprepare(clk_get_parent_by_index(clk, i)); + clk_provider_disable_unprepare(clk_get_parent_by_index(clk, i)); return ret; } diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c index 4cf838d5..faa8dfa 100644 --- a/drivers/clk/rockchip/clk-rockchip.c +++ b/drivers/clk/rockchip/clk-rockchip.c @@ -54,7 +54,7 @@ static void __init rk2928_gate_clk_init(struct device_node *node) if (!clk_data) return; - clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc(qty * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 13eae14c..f5639bf 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -26,7 +26,7 @@ enum exynos_audss_clk_type { }; static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; +static struct clk_core **clk_table; static void __iomem *reg_base; static struct clk_onecell_data clk_data; @@ -83,7 +83,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; const char *sclk_pcm_p = "sclk_pcm0"; - struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; + struct clk_core *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; const struct of_device_id *match; enum exynos_audss_clk_type variant; @@ -100,7 +100,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + sizeof(struct clk_core *) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -111,8 +111,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) else clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1; - pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); - pll_in = devm_clk_get(&pdev->dev, "pll_in"); + pll_ref = devm_clk_provider_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_provider_get(&pdev->dev, "pll_in"); if (!IS_ERR(pll_ref)) mout_audss_p[0] = __clk_get_name(pll_ref); if (!IS_ERR(pll_in)) @@ -122,8 +122,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); - cdclk = devm_clk_get(&pdev->dev, "cdclk"); - sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + cdclk = devm_clk_provider_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_provider_get(&pdev->dev, "sclk_audio"); if (!IS_ERR(cdclk)) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) @@ -161,7 +161,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); - sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + sclk_pcm_in = devm_clk_provider_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ac163d7..9a2270b 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1230,19 +1230,19 @@ static unsigned long exynos4_get_xom(void) static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) { struct samsung_fixed_rate_clock fclk; - struct clk *clk; + struct clk_core *clk; unsigned long finpll_f = 24000000; char *parent_name; unsigned int xom = exynos4_get_xom(); parent_name = xom & 1 ? "xusbxti" : "xxti"; - clk = clk_get(NULL, parent_name); + clk = clk_provider_get(NULL, parent_name); if (IS_ERR(clk)) { pr_err("%s: failed to lookup parent clock %s, assuming " "fin_pll clock frequency is 24MHz\n", __func__, parent_name); } else { - finpll_f = clk_get_rate(clk); + finpll_f = clk_provider_get_rate(clk); } fclk.id = CLK_FIN_PLL; diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..aaf234a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -910,12 +910,12 @@ static const struct clk_ops samsung_pll2550x_clk_ops = { .recalc_rate = samsung_pll2550x_recalc_rate, }; -struct clk * __init samsung_clk_register_pll2550x(const char *name, +struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset) { struct samsung_clk_pll2550x *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -1149,7 +1149,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, void __iomem *base) { struct samsung_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int ret, len; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..81af344 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -97,7 +97,7 @@ struct samsung_pll_rate_table { unsigned int vsel; }; -extern struct clk * __init samsung_clk_register_pll2550x(const char *name, +extern struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset); diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c index 0449cc0..70baecf 100644 --- a/drivers/clk/samsung/clk-s3c2410-dclk.c +++ b/drivers/clk/samsung/clk-s3c2410-dclk.c @@ -87,12 +87,12 @@ const struct clk_ops s3c24xx_clkout_ops = { .determine_rate = __clk_mux_determine_rate, }; -struct clk *s3c24xx_register_clkout(struct device *dev, const char *name, +struct clk_core *s3c24xx_register_clkout(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u8 shift, u32 mask) { struct s3c24xx_clkout *clkout; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the clkout */ @@ -237,7 +237,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk; struct resource *mem; - struct clk **clk_table; + struct clk_core **clk_table; struct s3c24xx_dclk_drv_data *dclk_variant; int ret, i; @@ -251,7 +251,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) spin_lock_init(&s3c24xx_dclk->dclk_lock); clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * DCLK_MAX_CLKS, + sizeof(struct clk_core *) * DCLK_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -355,7 +355,7 @@ err_clk_register: static int s3c24xx_dclk_remove(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); - struct clk **clk_table = s3c24xx_dclk->clk_data.clks; + struct clk_core **clk_table = s3c24xx_dclk->clk_data.clks; int i; clk_notifier_unregister(clk_table[DIV_DCLK1], diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index deab84d..68133fa 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -52,14 +52,14 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks) { struct samsung_clk_provider *ctx; - struct clk **clk_table; + struct clk_core **clk_table; int i; ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); if (!ctx) panic("could not allocate clock provider context.\n"); - clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); + clk_table = kcalloc(nr_clks, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_table) panic("could not allocate clock lookup table\n"); @@ -85,7 +85,7 @@ void __init samsung_clk_of_add_provider(struct device_node *np, } /* add a clock instance to the clock lookup table used for dt based lookup */ -void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, +void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk_core *clk, unsigned int id) { if (ctx->clk_data.clks && id) @@ -97,7 +97,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; if (!ctx->clk_data.clks) { @@ -130,7 +130,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -159,7 +159,7 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -180,7 +180,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, struct samsung_mux_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -212,7 +212,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, struct samsung_div_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -251,7 +251,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, struct samsung_gate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -303,7 +303,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, /* utility function to get the rate of a specified clock */ unsigned long _get_rate(const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = __clk_lookup(clk_name); if (!clk) { @@ -311,5 +311,5 @@ unsigned long _get_rate(const char *clk_name) return 0; } - return clk_get_rate(clk); + return clk_provider_get_rate(clk); } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 66ab36b..a13c8b2 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -336,7 +336,7 @@ extern void __init samsung_clk_of_register_fixed_ext( const struct of_device_id *clk_matches); extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, - struct clk *clk, unsigned int id); + struct clk_core *clk, unsigned int id); extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index f065f69..c6712fb 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -119,7 +119,7 @@ static void __init cpg_div6_clock_init(struct device_node *np) struct div6_clock *clock; const char *parent_name; const char *name; - struct clk *clk; + struct clk_core *clk; int ret; clock = kzalloc(sizeof(*clock), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-emev2.c b/drivers/clk/shmobile/clk-emev2.c index 6c7c929..2e3a45b 100644 --- a/drivers/clk/shmobile/clk-emev2.c +++ b/drivers/clk/shmobile/clk-emev2.c @@ -71,7 +71,7 @@ static void __init emev2_smu_init(void) static void __init emev2_smu_clkdiv_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; @@ -89,7 +89,7 @@ CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv", static void __init emev2_smu_gclk_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c index 2d2fe77..2659676 100644 --- a/drivers/clk/shmobile/clk-mstp.c +++ b/drivers/clk/shmobile/clk-mstp.c @@ -121,13 +121,13 @@ static const struct clk_ops cpg_mstp_clock_ops = { .is_enabled = cpg_mstp_clock_is_enabled, }; -static struct clk * __init +static struct clk_core * __init cpg_mstp_clock_register(const char *name, const char *parent_name, unsigned int index, struct mstp_clock_group *group) { struct clk_init_data init; struct mstp_clock *clock; - struct clk *clk; + struct clk_core *clk; clock = kzalloc(sizeof(*clock), GFP_KERNEL); if (!clock) { @@ -157,7 +157,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) { struct mstp_clock_group *group; const char *idxname; - struct clk **clks; + struct clk_core **clks; unsigned int i; group = kzalloc(sizeof(*group), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-r8a7740.c b/drivers/clk/shmobile/clk-r8a7740.c index 1e2eaae..8889e6a 100644 --- a/drivers/clk/shmobile/clk-r8a7740.c +++ b/drivers/clk/shmobile/clk-r8a7740.c @@ -61,7 +61,7 @@ static const struct clk_div_table div4_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, const char *name) { @@ -147,7 +147,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, static void __init r8a7740_cpg_clocks_init(struct device_node *np) { struct r8a7740_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -180,7 +180,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c index 652ecac..96b51b1 100644 --- a/drivers/clk/shmobile/clk-r8a7779.c +++ b/drivers/clk/shmobile/clk-r8a7779.c @@ -90,7 +90,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, const struct cpg_clk_config *config, unsigned int plla_mult, const char *name) @@ -124,7 +124,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) { const struct cpg_clk_config *config; struct r8a7779_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i, plla_mult; int num_clks; @@ -153,7 +153,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index dff7f79..d8bdeb8 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -133,12 +133,12 @@ static const struct clk_ops cpg_z_clk_ops = { .set_rate = cpg_z_clk_set_rate, }; -static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) +static struct clk_core * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) { static const char *parent_name = "pll0"; struct clk_init_data init; struct cpg_z_clk *zclk; - struct clk *clk; + struct clk_core *clk; zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); if (!zclk) @@ -212,7 +212,7 @@ static const struct clk_div_table cpg_sd01_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, const struct cpg_pll_config *config, const char *name) @@ -279,7 +279,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) { const struct cpg_pll_config *config; struct rcar_gen2_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -312,7 +312,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c index 7e68e86..414e20e 100644 --- a/drivers/clk/shmobile/clk-rz.c +++ b/drivers/clk/shmobile/clk-rz.c @@ -28,7 +28,7 @@ struct rz_cpg { * Initialization */ -static struct clk * __init +static struct clk_core * __init rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) { u32 val; @@ -67,7 +67,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static void __init rz_cpg_clocks_init(struct device_node *np) { struct rz_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned i; int num_clks; @@ -86,7 +86,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/sirf/clk-atlas6.c b/drivers/clk/sirf/clk-atlas6.c index d63b76c..9cce269 100644 --- a/drivers/clk/sirf/clk-atlas6.c +++ b/drivers/clk/sirf/clk-atlas6.c @@ -113,7 +113,7 @@ static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *atlas6_clks[maxclk]; +static struct clk_core *atlas6_clks[maxclk]; static void __init atlas6_clk_init(struct device_node *np) { diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c index 37af51c..05f5040 100644 --- a/drivers/clk/sirf/clk-common.c +++ b/drivers/clk/sirf/clk-common.c @@ -165,9 +165,9 @@ static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, * SiRF SoC has not cpu clock control, * So bypass to it's parent pll. */ - struct clk *parent_clk = clk_get_parent(hw->clk); - struct clk *pll_parent_clk = clk_get_parent(parent_clk); - unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); + struct clk_core *pll_parent_clk = clk_provider_get_parent(parent_clk); + unsigned long pll_parent_rate = clk_provider_get_rate(pll_parent_clk); return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate); } @@ -178,7 +178,7 @@ static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, * SiRF SoC has not cpu clock control, * So return the parent pll rate. */ - struct clk *parent_clk = clk_get_parent(hw->clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); return __clk_get_rate(parent_clk); } @@ -403,34 +403,34 @@ static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int ret1, ret2; - struct clk *cur_parent; + struct clk_core *cur_parent; - if (rate == clk_get_rate(clk_pll1.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + if (rate == clk_provider_get_rate(clk_pll1.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll2.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + if (rate == clk_provider_get_rate(clk_pll2.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll3.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); + if (rate == clk_provider_get_rate(clk_pll3.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll3.hw.clk); return ret1; } - cur_parent = clk_get_parent(hw->clk); + cur_parent = clk_provider_get_parent(hw->clk); /* switch to tmp pll before setting parent clock's rate */ if (cur_parent == clk_pll1.hw.clk) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); BUG_ON(ret1); } - ret2 = clk_set_rate(clk_pll1.hw.clk, rate); + ret2 = clk_provider_set_rate(clk_pll1.hw.clk, rate); - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret2 ? ret2 : ret1; } diff --git a/drivers/clk/sirf/clk-prima2.c b/drivers/clk/sirf/clk-prima2.c index 6968e2e..751187b 100644 --- a/drivers/clk/sirf/clk-prima2.c +++ b/drivers/clk/sirf/clk-prima2.c @@ -112,7 +112,7 @@ static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *prima2_clks[maxclk]; +static struct clk_core *prima2_clks[maxclk]; static void __init prima2_clk_init(struct device_node *np) { diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index dd3a78c..e3a6fe6 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -188,7 +188,7 @@ static void __init __socfpga_gate_init(struct device_node *node, u32 div_reg[3]; u32 clk_phase[2]; u32 fixed_div; - struct clk *clk; + struct clk_core *clk; struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 46531c3..a63be19 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -53,7 +53,7 @@ static __init void __socfpga_periph_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index de6da95..4ed91a4 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -81,11 +81,11 @@ static struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static __init struct clk *__socfpga_pll_init(struct device_node *node, +static __init struct clk_core *__socfpga_pll_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c index bdfb442..18334c3 100644 --- a/drivers/clk/spear/clk-aux-synth.c +++ b/drivers/clk/spear/clk-aux-synth.c @@ -134,14 +134,14 @@ static struct clk_ops clk_aux_ops = { .set_rate = clk_aux_set_rate, }; -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk) { struct clk_aux *aux; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); @@ -177,7 +177,7 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name, goto free_aux; if (gate_name) { - struct clk *tgate_clk; + struct clk_core *tgate_clk; tgate_clk = clk_register_gate(NULL, gate_name, aux_name, CLK_SET_RATE_PARENT, reg, diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c index dffd4ce..bce2c0e 100644 --- a/drivers/clk/spear/clk-frac-synth.c +++ b/drivers/clk/spear/clk-frac-synth.c @@ -122,13 +122,13 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *clk_register_frac(const char *name, const char *parent_name, +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c index 1afc18c..f8e13f3 100644 --- a/drivers/clk/spear/clk-gpt-synth.c +++ b/drivers/clk/spear/clk-gpt-synth.c @@ -111,13 +111,13 @@ static struct clk_ops clk_gpt_ops = { .set_rate = clk_gpt_set_rate, }; -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_gpt *gpt; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c index 1b9b65b..226f2ec 100644 --- a/drivers/clk/spear/clk-vco-pll.c +++ b/drivers/clk/spear/clk-vco-pll.c @@ -272,16 +272,16 @@ static struct clk_ops clk_vco_ops = { .set_rate = clk_vco_set_rate, }; -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk) + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk) { struct clk_vco *vco; struct clk_pll *pll; - struct clk *vco_clk, *tpll_clk, *tvco_gate_clk; + struct clk_core *vco_clk, *tpll_clk, *tvco_gate_clk; struct clk_init_data vco_init, pll_init; const char **vco_parent_name; diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h index 9317376..777322e 100644 --- a/drivers/clk/spear/clk.h +++ b/drivers/clk/spear/clk.h @@ -110,22 +110,22 @@ typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, int index); /* clk register routines */ -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); -struct clk *clk_register_frac(const char *name, const char *parent_name, + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk); +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk); + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk); long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index 4daa597..1e95410 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c @@ -385,7 +385,7 @@ static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c index 5a5c664..f42965c 100644 --- a/drivers/clk/spear/spear1340_clock.c +++ b/drivers/clk/spear/spear1340_clock.c @@ -442,7 +442,7 @@ static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", void __init spear1340_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index bb5f387..5b8d659 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c @@ -140,7 +140,7 @@ static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", #ifdef CONFIG_MACH_SPEAR300 static void __init spear300_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 1, 1); @@ -170,7 +170,7 @@ static inline void spear300_clk_init(void) { } #ifdef CONFIG_MACH_SPEAR310 static void __init spear310_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 1); @@ -246,9 +246,9 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; static void __init spear320_clk_init(void __iomem *soc_config_base, - struct clk *ras_apb_clk) + struct clk_core *ras_apb_clk) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, CLK_IS_ROOT, 125000000); @@ -344,7 +344,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, 0, &_lock); clk_register_clkdev(clk, NULL, "a3000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -353,7 +353,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a4000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -384,12 +384,12 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, clk_register_clkdev(clk, NULL, "60100000.serial"); } #else -static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } +static inline void spear320_clk_init(void __iomem *sb, struct clk_core *rc) { } #endif void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) { - struct clk *clk, *clk1, *ras_apb_clk; + struct clk_core *clk, *clk1, *ras_apb_clk; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index 4f649c9..db946f7 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c @@ -116,7 +116,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = { void __init spear6xx_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index af94ed8..ceda1f2 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -614,13 +614,13 @@ static const struct clk_ops st_quadfs_pll_c32_ops = { .set_rate = quadfs_pll_fs660c32_set_rate, }; -static struct clk * __init st_clk_register_quadfs_pll( +static struct clk_core * __init st_clk_register_quadfs_pll( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, spinlock_t *lock) { struct st_clk_quadfs_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -1018,13 +1018,13 @@ static const struct clk_ops st_quadfs_ops = { .recalc_rate = quadfs_recalc_rate, }; -static struct clk * __init st_clk_register_quadfs_fsynth( +static struct clk_core * __init st_clk_register_quadfs_fsynth( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, spinlock_t *lock) { struct st_clk_quadfs_fsynth *fs; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -1102,7 +1102,7 @@ static void __init st_of_create_quadfs_fsynths( return; clk_data->clk_num = QUADFS_MAX_CHAN; - clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *), + clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { @@ -1111,7 +1111,7 @@ static void __init st_of_create_quadfs_fsynths( } for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -1136,8 +1136,8 @@ static void __init st_of_create_quadfs_fsynths( clk_data->clks[fschan] = clk; pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); } } @@ -1147,7 +1147,7 @@ static void __init st_of_create_quadfs_fsynths( static void __init st_of_quadfs_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *pll_name, *clk_parent_name; void __iomem *reg; spinlock_t *lock; @@ -1181,8 +1181,8 @@ static void __init st_of_quadfs_setup(struct device_node *np) else pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); st_of_create_quadfs_fsynths(np, pll_name, (struct clkgen_quadfs_data *)match->data, diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c index 79dc40b..d2a951f 100644 --- a/drivers/clk/st/clkgen-mux.c +++ b/drivers/clk/st/clkgen-mux.c @@ -215,7 +215,7 @@ static const struct clk_ops clkgena_divmux_ops = { /** * clk_register_genamux - register a genamux clock with the clock framework */ -struct clk *clk_register_genamux(const char *name, +struct clk_core *clk_register_genamux(const char *name, const char **parent_names, u8 num_parents, void __iomem *reg, const struct clkgena_divmux_data *muxdata, @@ -227,7 +227,7 @@ struct clk *clk_register_genamux(const char *name, const int mux_width = 2; const int divider_width = 5; struct clkgena_divmux *genamux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int i; @@ -280,8 +280,8 @@ struct clk *clk_register_genamux(const char *name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); err: return clk; } @@ -413,14 +413,14 @@ void __init st_of_clkgena_divmux_setup(struct device_node *np) goto err; clk_data->clk_num = data->num_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -490,7 +490,7 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) const struct of_device_id *match; void __iomem *reg; const char *parent_name, *clk_name; - struct clk *clk; + struct clk_core *clk; struct clkgena_prediv_data *data; match = of_match_node(clkgena_prediv_of_match, np); @@ -522,8 +522,8 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) of_clk_add_provider(np, of_clk_src_simple_get, clk); pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); return; } @@ -625,7 +625,7 @@ static struct of_device_id mux_of_match[] = { void __init st_of_clkgen_mux_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; void __iomem *reg; const char **parents; int num_parents; @@ -662,8 +662,8 @@ void __init st_of_clkgen_mux_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); of_clk_add_provider(np, of_clk_src_simple_get, clk); @@ -726,14 +726,14 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) goto err; clk_data->clk_num = VCC_MAX_CHANNELS; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; struct clk_gate *gate; struct clk_divider *div; @@ -796,8 +796,8 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); clk_data->clks[i] = clk; } diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index 29769d7..32bac02 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -390,13 +390,13 @@ static const struct clk_ops st_pll1200c32_ops = { .recalc_rate = recalc_stm_pll1200c32, }; -static struct clk * __init clkgen_pll_register(const char *parent_name, +static struct clk_core * __init clkgen_pll_register(const char *parent_name, struct clkgen_pll_data *pll_data, void __iomem *reg, const char *clk_name) { struct clkgen_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -422,16 +422,16 @@ static struct clk * __init clkgen_pll_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } -static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, +static struct clk_core * __init clkgen_c65_lsdiv_register(const char *parent_name, const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2); if (IS_ERR(clk)) @@ -439,8 +439,8 @@ static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -484,7 +484,7 @@ static void __init clkgena_c65_pll_setup(struct device_node *np) return; clk_data->clk_num = num_pll_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) @@ -543,14 +543,14 @@ err: CLK_OF_DECLARE(clkgena_c65_plls, "st,clkgena-plls-c65", clkgena_c65_pll_setup); -static struct clk * __init clkgen_odf_register(const char *parent_name, +static struct clk_core * __init clkgen_odf_register(const char *parent_name, void * __iomem reg, struct clkgen_pll_data *pll_data, int odf, spinlock_t *odf_lock, const char *odf_name) { - struct clk *clk; + struct clk_core *clk; unsigned long flags; struct clk_gate *gate; struct clk_divider *div; @@ -588,8 +588,8 @@ static struct clk * __init clkgen_odf_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -640,7 +640,7 @@ static struct of_device_id c32_pll_of_match[] = { static void __init clkgen_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name, *pll_name; void __iomem *pll_base; int num_odfs, odf; @@ -676,14 +676,14 @@ static void __init clkgen_c32_pll_setup(struct device_node *np) return; clk_data->clk_num = num_odfs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (odf = 0; odf < num_odfs; odf++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -723,7 +723,7 @@ static struct of_device_id c32_gpu_pll_of_match[] = { static void __init clkgengpu_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; const char *clk_name; diff --git a/drivers/clk/sunxi/clk-a10-hosc.c b/drivers/clk/sunxi/clk-a10-hosc.c index 0481d5d..c5e4c41 100644 --- a/drivers/clk/sunxi/clk-a10-hosc.c +++ b/drivers/clk/sunxi/clk-a10-hosc.c @@ -25,7 +25,7 @@ static DEFINE_SPINLOCK(hosc_lock); static void __init sun4i_osc_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_fixed_rate *fixed; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c index 5296fd6..63c7dd5 100644 --- a/drivers/clk/sunxi/clk-a20-gmac.c +++ b/drivers/clk/sunxi/clk-a20-gmac.c @@ -55,7 +55,7 @@ static DEFINE_SPINLOCK(gmac_lock); static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_mux *mux; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c index 2057c8a..bb2d4b2 100644 --- a/drivers/clk/sunxi/clk-factors.c +++ b/drivers/clk/sunxi/clk-factors.c @@ -79,9 +79,9 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate, static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { - struct clk *clk = hw->clk, *parent, *best_parent = NULL; + struct clk_core *clk = hw->clk, *parent, *best_parent = NULL; int i, num_parents; unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c index e10d052..f29b06e 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c @@ -74,7 +74,7 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev) /* Worst-case size approximation and memory allocation */ ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE); clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1), - sizeof(struct clk *), GFP_KERNEL); + sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) return -ENOMEM; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c index 1fa2337..5e4649e 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0.c @@ -35,7 +35,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev) const char *clk_parent; struct resource *r; void __iomem *reg; - struct clk *clk; + struct clk_core *clk; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, r); diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c index eca8ca0..984d5d0 100644 --- a/drivers/clk/sunxi/clk-sun6i-ar100.c +++ b/drivers/clk/sunxi/clk-sun6i-ar100.c @@ -46,7 +46,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw, static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { int nparents = __clk_get_num_parents(hw->clk); long best_rate = -EINVAL; @@ -57,7 +57,7 @@ static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, for (i = 0; i < nparents; i++) { unsigned long parent_rate; unsigned long tmp_rate; - struct clk *parent; + struct clk_core *parent; unsigned long div; int shift; @@ -176,7 +176,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev) struct clk_init_data init; struct ar100_clk *ar100; struct resource *r; - struct clk *clk; + struct clk_core *clk; int nparents; int i; diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index b654b7b..44c4470 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -403,7 +403,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, * clk_sunxi_mmc_phase_control() - configures MMC clock phase control */ -void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output) +void clk_sunxi_mmc_phase_control(struct clk_core *clk, u8 sample, u8 output) { #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) @@ -582,10 +582,10 @@ static const struct factors_data sun7i_a20_out_data __initconst = { .getter = sun7i_a20_get_out_factors, }; -static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, +static struct clk_core * __init sunxi_factors_clk_setup(struct device_node *node, const struct factors_data *data) { - struct clk *clk; + struct clk_core *clk; struct clk_factors *factors; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; @@ -695,7 +695,7 @@ static const struct mux_data sun4i_apb1_mux_data __initconst = { static void __init sunxi_mux_clk_setup(struct device_node *node, struct mux_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parents[SUNXI_MAX_PARENTS]; void __iomem *reg; @@ -777,7 +777,7 @@ static const struct div_data sun6i_a31_apb2_div_data __initconst = { static void __init sunxi_divider_clk_setup(struct device_node *node, struct div_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *clk_parent; void __iomem *reg; @@ -976,7 +976,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) return; - clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; @@ -1078,7 +1078,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, struct clk_onecell_data *clk_data; const char *parent; const char *clk_name; - struct clk **clks, *pclk; + struct clk_core **clks, *pclk; struct clk_hw *gate_hw, *rate_hw; const struct clk_ops *rate_ops; struct clk_gate *gate = NULL; @@ -1291,10 +1291,10 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks) /* Protect the clocks that needs to stay on */ for (i = 0; i < nclocks; i++) { - struct clk *clk = clk_get(NULL, clocks[i]); + struct clk_core *clk = clk_provider_get(NULL, clocks[i]); if (!IS_ERR(clk)) - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); } } diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c index c0f7843..53c3488 100644 --- a/drivers/clk/tegra/clk-audio-sync.c +++ b/drivers/clk/tegra/clk-audio-sync.c @@ -54,12 +54,12 @@ const struct clk_ops tegra_clk_sync_source_ops = { .recalc_rate = clk_sync_source_recalc_rate, }; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long rate, unsigned long max_rate) { struct tegra_clk_sync_source *sync; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; sync = kzalloc(sizeof(*sync), GFP_KERNEL); if (!sync) { diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 290f9c1..7a1212b7 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -147,13 +147,13 @@ const struct clk_ops tegra_clk_frac_div_ops = { .round_rate = clk_frac_div_round_rate, }; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock) { struct tegra_clk_frac_div *divider; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; divider = kzalloc(sizeof(*divider), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 5070153..5aaedd3 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -127,12 +127,12 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .disable = clk_periph_disable, }; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt) { struct tegra_clk_periph_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *pregs; diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 9e899c18..ea26de3 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -138,13 +138,13 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = { .set_rate = clk_periph_set_rate, }; -static struct clk *_tegra_clk_register_periph(const char *name, +static struct clk_core *_tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *bank; bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); @@ -186,7 +186,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, return clk; } -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) @@ -195,7 +195,7 @@ struct clk *tegra_clk_register_periph(const char *name, periph, clk_base, offset, flags); } -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset) diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 3598987..49ae7b1 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -87,13 +87,13 @@ const struct clk_ops tegra_clk_pll_out_ops = { .disable = clk_pll_out_disable, }; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags, spinlock_t *lock) { struct tegra_clk_pll_out *pll_out; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c7c6d8f..cb61b7d 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -729,7 +729,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) static int clk_plle_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); struct tegra_clk_pll_freq_table sel; u32 val; int err; @@ -1033,7 +1033,7 @@ static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, state = clk_pll_is_enabled(hw); if (state) { - if (rate != clk_get_rate(hw->clk)) { + if (rate != clk_provider_get_rate(hw->clk)) { pr_err("%s: Cannot change active PLLM\n", __func__); ret = -EINVAL; goto out; @@ -1285,7 +1285,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) u32 val; int ret; unsigned long flags = 0; - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) return -EINVAL; @@ -1430,7 +1430,7 @@ static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, return pll; } -static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, +static struct clk_core *_tegra_clk_register_pll(struct tegra_clk_pll *pll, const char *name, const char *parent_name, unsigned long flags, const struct clk_ops *ops) { @@ -1448,13 +1448,13 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, return clk_register(NULL, &pll->hw); } -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1479,13 +1479,13 @@ static struct div_nmp pll_e_nmp = { .divp_width = PLLE_BASE_DIVP_WIDTH, }; -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1550,14 +1550,14 @@ static const struct clk_ops tegra_clk_plle_tegra114_ops = { }; -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; int err; u32 val, val_iddq; @@ -1603,7 +1603,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, @@ -1611,7 +1611,7 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, { u32 val; struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; @@ -1649,14 +1649,14 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; if (!pll_params->pdiv_tohw) @@ -1688,13 +1688,13 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { - struct clk *parent, *clk; + struct clk_core *parent, *clk; struct pdiv_map *p_tohw = pll_params->pdiv_tohw; struct tegra_clk_pll *pll; struct tegra_clk_pll_freq_table cfg; @@ -1762,14 +1762,14 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 val, val_aux; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1812,13 +1812,13 @@ static const struct clk_ops tegra_clk_pllss_ops = { .set_rate = clk_pllxc_set_rate, }; -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; struct tegra_clk_pll_freq_table cfg; unsigned long parent_rate; u32 val; diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 2fd924d..e843d20 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -127,13 +127,13 @@ const struct clk_ops tegra_clk_super_ops = { .set_parent = clk_super_set_parent, }; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock) { struct tegra_clk_super_mux *super; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; super = kzalloc(sizeof(*super), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c index 5c38aab..484a900 100644 --- a/drivers/clk/tegra/clk-tegra-audio.c +++ b/drivers/clk/tegra/clk-tegra-audio.c @@ -128,8 +128,8 @@ void __init tegra_audio_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_a_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; /* PLLA */ diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index f3b7738..503e261 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -36,8 +36,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, unsigned long *osc_freq, unsigned long *pll_ref_freq) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; u32 val, pll_ref_div; unsigned osc_idx; @@ -81,8 +81,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* clk_32k */ dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 37f32c4..125dfa2 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -585,8 +585,8 @@ static void __init periph_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { struct tegra_clk_periph_regs *bank; @@ -615,8 +615,8 @@ static void __init gate_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { struct tegra_periph_init_data *data; @@ -640,8 +640,8 @@ static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c index 08b21c1..2ff427a 100644 --- a/drivers/clk/tegra/clk-tegra-pmc.c +++ b/drivers/clk/tegra/clk-tegra-pmc.c @@ -82,8 +82,8 @@ static struct pmc_clk_init_data pmc_clks[] = { void __init tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index feb3201..e6224c4 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -53,8 +53,8 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", static void __init tegra_sclk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* SCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); @@ -99,8 +99,8 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* CCLKG */ dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index f760f31..68efd84 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -936,14 +936,14 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = { [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, }; -static struct clk **clks; +static struct clk_core **clks; static unsigned long osc_freq; static unsigned long pll_ref_freq; static int __init tegra114_osc_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; u32 val, pll_ref_div; val = readl_relaxed(clk_base + OSC_CTRL); @@ -973,7 +973,7 @@ static int __init tegra114_osc_clk_init(void __iomem *clk_base) static void __init tegra114_fixed_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; /* clk_32k */ clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, @@ -1078,7 +1078,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, @@ -1200,7 +1200,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = { static __init void tegra114_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; struct tegra_periph_init_data *data; int i; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 9525c68..43f0632 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1017,7 +1017,7 @@ static struct tegra_devclk devclks[] __initdata = { { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, }; -static struct clk **clks; +static struct clk_core **clks; static void tegra124_utmi_param_configure(void __iomem *clk_base) { @@ -1104,7 +1104,7 @@ static void tegra124_utmi_param_configure(void __iomem *clk_base) static __init void tegra124_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; /* xusb_ss_div2 */ clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, @@ -1148,7 +1148,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index dace2b1..6783355 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -162,7 +162,7 @@ static void __iomem *pmc_base; _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { { 12000000, 600000000, 600, 12, 0, 8 }, @@ -633,7 +633,7 @@ static unsigned int tegra20_get_pll_ref_div(void) static void tegra20_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, @@ -713,7 +713,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void tegra20_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* CCLK */ clk = tegra_clk_register_super_mux("cclk", cclk_parents, @@ -738,7 +738,7 @@ static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", static void __init tegra20_audio_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* audio */ clk = clk_register_mux(NULL, "audio_mux", audio_parents, @@ -800,7 +800,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* ac97 */ @@ -871,7 +871,7 @@ static void __init tegra20_periph_clk_init(void) static void __init tegra20_osc_clk_init(void) { - struct clk *clk; + struct clk_core *clk; unsigned long input_freq; unsigned int pll_ref_div; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 8b10c38..801bb61 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -202,7 +202,7 @@ static DEFINE_SPINLOCK(pll_d_lock); _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; /* * Structure defining the fields for USB UTMI clocks Parameters. @@ -918,7 +918,7 @@ static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; static void __init tegra30_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, @@ -1009,7 +1009,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void __init tegra30_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* * Clock input to cclk_g divided from pll_p using @@ -1131,7 +1131,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra30_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* dsia */ diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index bf452b6..daae4f7a 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -68,7 +68,7 @@ struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; int *periph_clk_enb_refcnt; static int periph_banks; -static struct clk **clks; +static struct clk_core **clks; static int clk_num; static struct clk_onecell_data clk_data; @@ -164,7 +164,7 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } -struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) +struct clk_core ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; @@ -178,7 +178,7 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) periph_banks = banks; - clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); + clks = kzalloc(num * sizeof(struct clk_core *), GFP_KERNEL); if (!clks) kfree(periph_clk_enb_refcnt); @@ -188,9 +188,9 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) } void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; dup_list->clk_id < clk_max; dup_list++) { clk = clks[dup_list->clk_id]; @@ -200,9 +200,9 @@ void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, } void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; tbl->clk_id < clk_max; tbl++) { clk = clks[tbl->clk_id]; @@ -210,8 +210,8 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, return; if (tbl->parent_id < clk_max) { - struct clk *parent = clks[tbl->parent_id]; - if (clk_set_parent(clk, parent)) { + struct clk_core *parent = clks[tbl->parent_id]; + if (clk_provider_set_parent(clk, parent)) { pr_err("%s: Failed to set parent %s of %s\n", __func__, __clk_get_name(parent), __clk_get_name(clk)); @@ -220,7 +220,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->rate) - if (clk_set_rate(clk, tbl->rate)) { + if (clk_provider_set_rate(clk, tbl->rate)) { pr_err("%s: Failed to set rate %lu of %s\n", __func__, tbl->rate, __clk_get_name(clk)); @@ -228,7 +228,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->state) - if (clk_prepare_enable(clk)) { + if (clk_provider_prepare_enable(clk)) { pr_err("%s: Failed to enable %s\n", __func__, __clk_get_name(clk)); WARN_ON(1); @@ -285,7 +285,7 @@ void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num) } } -struct clk ** __init tegra_lookup_dt_id(int clk_id, +struct clk_core ** __init tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk) { if (tegra_clk[clk_id].present) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 16ec8d6..3093aa4 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -39,7 +39,7 @@ struct tegra_clk_sync_source { extern const struct clk_ops tegra_clk_sync_source_ops; extern int *periph_clk_enb_refcnt; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long fixed_rate, unsigned long max_rate); /** @@ -82,7 +82,7 @@ struct tegra_clk_frac_div { #define TEGRA_DIVIDER_UART BIT(3) extern const struct clk_ops tegra_clk_frac_div_ops; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); @@ -258,47 +258,47 @@ struct tegra_clk_pll { extern const struct clk_ops tegra_clk_pll_ops; extern const struct clk_ops tegra_clk_plle_ops; -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock, unsigned long parent_rate); -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); @@ -325,7 +325,7 @@ struct tegra_clk_pll_out { #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) extern const struct clk_ops tegra_clk_pll_out_ops; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, spinlock_t *lock); @@ -394,7 +394,7 @@ struct tegra_clk_periph_gate { #define TEGRA_PERIPH_NO_GATE BIT(5) extern const struct clk_ops tegra_clk_periph_gate_ops; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt); @@ -427,11 +427,11 @@ struct tegra_clk_periph { #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 extern const struct clk_ops tegra_clk_periph_ops; -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags); -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset); @@ -540,7 +540,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) extern const struct clk_ops tegra_clk_super_ops; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); @@ -590,15 +590,15 @@ struct tegra_devclk { }; void tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); struct tegra_clk_periph_regs *get_reg_bank(int clkid); -struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); +struct clk_core **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); -struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); +struct clk_core **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); void tegra_add_of_provider(struct device_node *np); void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index 72d9727..a162c21 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -135,10 +135,10 @@ static void __init omap_clk_register_apll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *ad = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - ad->clk_ref = of_clk_get(node, 0); - ad->clk_bypass = of_clk_get(node, 1); + ad->clk_ref = of_clk_provider_get(node, 0); + ad->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) { pr_debug("clk-ref or clk-bypass for %s not ready, retry\n", @@ -332,7 +332,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) struct dpll_data *ad = NULL; struct clk_hw_omap *clk_hw = NULL; struct clk_init_data *init = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name; u32 val; diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c index c808ab3..a48fe6f 100644 --- a/drivers/clk/ti/clk-2xxx.c +++ b/drivers/clk/ti/clk-2xxx.c @@ -237,10 +237,10 @@ static int __init omap2xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "dpll_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "mpu_ck")) / 1000000)); return 0; } diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 028b337..0988f1e 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -121,7 +121,7 @@ static const char *enable_init_clks[] = { int __init am33xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am33xx_clks); @@ -139,12 +139,12 @@ int __init am33xx_dt_clk_init(void) * oscillator clock. */ - clk1 = clk_get_sys(NULL, "sys_clkin_ck"); - clk2 = clk_get_sys(NULL, "timer3_fck"); - clk_set_parent(clk2, clk1); + clk1 = clk_provider_get_sys(NULL, "sys_clkin_ck"); + clk2 = clk_provider_get_sys(NULL, "timer3_fck"); + clk_provider_set_parent(clk2, clk1); - clk2 = clk_get_sys(NULL, "timer6_fck"); - clk_set_parent(clk2, clk1); + clk2 = clk_provider_get_sys(NULL, "timer6_fck"); + clk_provider_set_parent(clk2, clk1); /* * The On-Chip 32K RC Osc clock is not an accurate clock-source as per * the design/spec, so as a result, for example, timer which supposed @@ -152,9 +152,9 @@ int __init am33xx_dt_clk_init(void) * not expected by any use-case, so change WDT1 clock source to PRCM * 32KHz clock. */ - clk1 = clk_get_sys(NULL, "wdt1_fck"); - clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "wdt1_fck"); + clk2 = clk_provider_get_sys(NULL, "clkdiv32k_ick"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 0d1750a..58ef20e 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -365,10 +365,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "core_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "arm_fck")) / 1000000)); if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) omap3_clk_lock_dpll5(); diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 3795fce..1277452 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -116,7 +116,7 @@ static struct ti_dt_clk am43xx_clks[] = { int __init am43xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am43xx_clks); @@ -132,9 +132,9 @@ int __init am43xx_dt_clk_init(void) * By selecting dpll_core_m5_ck as the clocksource fixes this issue. * In AM335x dpll_core_m5_ck is the default clocksource. */ - clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); - clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "cpsw_cpts_rft_clk"); + clk2 = clk_provider_get_sys(NULL, "dpll_core_m5_ck"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 02517a8..1adc399 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -281,7 +281,7 @@ static struct ti_dt_clk omap44xx_clks[] = { int __init omap4xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap44xx_clks); @@ -291,8 +291,8 @@ int __init omap4xxx_dt_clk_init(void) * Lock USB DPLL on OMAP4 devices so that the L3INIT power * domain can transition to retention state when not in use. */ - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); @@ -302,12 +302,12 @@ int __init omap4xxx_dt_clk_init(void) * locking the ABE DPLL on boot. * Lock the ABE DPLL in any case to avoid issues with audio. */ - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_refclk_mux_ck"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 5e18399..5b603b5 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -225,34 +225,35 @@ static struct ti_dt_clk omap54xx_clks[] = { int __init omap5xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap54xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_clk_mux"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_m2x2_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); + rc = clk_provider_set_rate(abe_dpll, + OMAP5_DPLL_ABE_DEFFREQ * 2); if (rc) pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ / 2); if (rc) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 09dbe38..f4ce89b 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -307,34 +307,34 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + struct clk_core *abe_dpll_mux, *sys_clkin2, *dpll_ck; ti_dt_clocks_register(dra7xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); - sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); - dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_mux = clk_provider_get_sys(NULL, "abe_dpll_sys_clk_mux"); + sys_clkin2 = clk_provider_get_sys(NULL, "sys_clkin2"); + dpll_ck = clk_provider_get_sys(NULL, "dpll_abe_ck"); - rc = clk_set_parent(abe_dpll_mux, sys_clkin2); + rc = clk_provider_set_parent(abe_dpll_mux, sys_clkin2); if (!rc) - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); + dpll_ck = clk_provider_get_sys(NULL, "dpll_gmac_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); if (rc) pr_err("%s: failed to configure GMAC DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); + dpll_ck = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); + dpll_ck = clk_provider_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ / 2); if (rc) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index 4a65b41..029a0d3 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c @@ -40,7 +40,7 @@ struct dra7_atl_clock_info; struct dra7_atl_desc { - struct clk *clk; + struct clk_core *clk; struct clk_hw hw; struct dra7_atl_clock_info *cinfo; int id; @@ -165,7 +165,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) struct dra7_atl_desc *clk_hw = NULL; struct clk_init_data init = { 0 }; const char **parent_names = NULL; - struct clk *clk; + struct clk_core *clk; clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); if (!clk_hw) { @@ -233,7 +233,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) char prop[5]; struct dra7_atl_desc *cdesc; struct of_phandle_args clkspec; - struct clk *clk; + struct clk_core *clk; int rc; rc = of_parse_phandle_with_args(node, "ti,provided-clocks", diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index b1a6f71..d88a70d0 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -41,7 +41,7 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) { struct ti_dt_clk *c; struct device_node *node; - struct clk *clk; + struct clk_core *clk; struct of_phandle_args clkspec; for (c = oclks; c->node_name != NULL; c++) { diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index f1e0038..6bc75d8 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -26,7 +26,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *clk_hw; const char *clkdm_name = node->name; int i; @@ -35,7 +35,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells"); for (i = 0; i < num_clks; i++) { - clk = of_clk_get(node, i); + clk = of_clk_provider_get(node, i); if (__clk_get_flags(clk) & CLK_IS_BASIC) { pr_warn("can't setup clkdm for basic clk %s\n", __clk_get_name(clk)); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index 19d8980..2cbee34 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -119,7 +119,7 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) static void __init ti_clk_register_composite(struct clk_hw *hw, struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); struct component_clk *comp; int num_parents = 0; diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index e6aa10d..1c41515 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -246,7 +246,7 @@ const struct clk_ops ti_clk_divider_ops = { .set_rate = ti_clk_divider_set_rate, }; -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, @@ -254,7 +254,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -434,7 +434,7 @@ static int __init ti_clk_divider_populate(struct device_node *node, */ static void __init of_ti_divider_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; u8 clk_divider_flags = 0; diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 79791e1..e1f74cc 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -128,10 +128,10 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *dd = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - dd->clk_ref = of_clk_get(node, 0); - dd->clk_bypass = of_clk_get(node, 1); + dd->clk_ref = of_clk_provider_get(node, 0); + dd->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) { pr_debug("clk-ref or clk-bypass missing for %s, retry later\n", @@ -175,7 +175,7 @@ static void ti_clk_register_dpll_x2(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *name = node->name; diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c index c2c8a28..2aa2701 100644 --- a/drivers/clk/ti/fixed-factor.c +++ b/drivers/clk/ti/fixed-factor.c @@ -33,7 +33,7 @@ */ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index b326d27..dd1b813 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -94,7 +94,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *clk_name = node->name; diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c index 9c3e8c4..e2f2bc0 100644 --- a/drivers/clk/ti/interface.c +++ b/drivers/clk/ti/interface.c @@ -34,7 +34,7 @@ static const struct clk_ops ti_interface_clk_ops = { static void __init _of_ti_interface_clk_setup(struct device_node *node, const struct clk_hw_omap_ops *ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *parent_name; diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index e9d650e..7456198 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -104,14 +104,14 @@ const struct clk_ops ti_clk_mux_ops = { .determine_rate = __clk_mux_determine_rate, }; -static struct clk *_register_mux(struct device *dev, const char *name, +static struct clk_core *_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the mux */ @@ -152,7 +152,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, */ static void of_mux_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; void __iomem *reg; int num_parents; const char **parent_names; diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c index e7bd62c..dabb8e6 100644 --- a/drivers/clk/ux500/abx500-clk.c +++ b/drivers/clk/ux500/abx500-clk.c @@ -23,7 +23,7 @@ static int ab8500_reg_clks(struct device *dev) { int ret; - struct clk *clk; + struct clk_core *clk; const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"}; u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1}; diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c index bd4769a..7eb055f 100644 --- a/drivers/clk/ux500/clk-prcc.c +++ b/drivers/clk/ux500/clk-prcc.c @@ -92,7 +92,7 @@ static struct clk_ops clk_prcc_kclk_ops = { .is_enabled = clk_prcc_is_enabled, }; -static struct clk *clk_reg_prcc(const char *name, +static struct clk_core *clk_reg_prcc(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -101,7 +101,7 @@ static struct clk *clk_reg_prcc(const char *name, { struct clk_prcc *clk; struct clk_init_data clk_prcc_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcc: %s invalid arguments passed\n", __func__); @@ -142,7 +142,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -152,7 +152,7 @@ struct clk *clk_reg_prcc_pclk(const char *name, &clk_prcc_pclk_ops); } -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index e2d63bc..bac54c9 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -243,7 +243,7 @@ static struct clk_ops clk_prcmu_opp_volt_scalable_ops = { .set_rate = clk_prcmu_set_rate, }; -static struct clk *clk_reg_prcmu(const char *name, +static struct clk_core *clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -252,7 +252,7 @@ static struct clk *clk_reg_prcmu(const char *name, { struct clk_prcmu *clk; struct clk_init_data clk_prcmu_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcmu: %s invalid arguments passed\n", __func__); @@ -292,7 +292,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -302,7 +302,7 @@ struct clk *clk_reg_prcmu_scalable(const char *name, &clk_prcmu_scalable_ops); } -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -311,7 +311,7 @@ struct clk *clk_reg_prcmu_gate(const char *name, &clk_prcmu_gate_ops); } -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -321,7 +321,7 @@ struct clk *clk_reg_prcmu_scalable_rate(const char *name, &clk_prcmu_scalable_rate_ops); } -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -330,7 +330,7 @@ struct clk *clk_reg_prcmu_rate(const char *name, &clk_prcmu_rate_ops); } -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -339,7 +339,7 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name, &clk_prcmu_opp_gate_ops); } -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c index e364c9d..dc6608a 100644 --- a/drivers/clk/ux500/clk-sysctrl.c +++ b/drivers/clk/ux500/clk-sysctrl.c @@ -114,7 +114,7 @@ static struct clk_ops clk_sysctrl_set_parent_ops = { .get_parent = clk_sysctrl_get_parent, }; -static struct clk *clk_reg_sysctrl(struct device *dev, +static struct clk_core *clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, @@ -128,7 +128,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, { struct clk_sysctrl *clk; struct clk_init_data clk_sysctrl_init; - struct clk *clk_reg; + struct clk_core *clk_reg; int i; if (!dev) @@ -176,7 +176,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, return clk_reg; } -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -193,7 +193,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, flags, &clk_sysctrl_gate_ops); } -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -212,7 +212,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, &clk_sysctrl_gate_fixed_rate_ops); } -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h index a2bb92d..da40a2d 100644 --- a/drivers/clk/ux500/clk.h +++ b/drivers/clk/ux500/clk.h @@ -14,52 +14,52 @@ #include <linux/device.h> #include <linux/types.h> -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -68,7 +68,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -78,7 +78,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 80069c3..8a2b4bc 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -19,7 +19,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, { struct prcmu_fw_version *fw_version; const char *sgaclk_parent = NULL; - struct clk *clk; + struct clk_core *clk; /* Clock sources */ clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c index 7b55ef8..afda303 100644 --- a/drivers/clk/ux500/u8500_of_clk.c +++ b/drivers/clk/ux500/u8500_of_clk.c @@ -18,9 +18,9 @@ #define PRCC_NUM_PERIPH_CLUSTERS 6 #define PRCC_PERIPHS_PER_CLUSTER 32 -static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; -static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; -static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcmu_clk[PRCMU_NUM_CLKS]; +static struct clk_core *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; #define PRCC_SHOW(clk, base, bit) \ clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] @@ -29,10 +29,10 @@ static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_C #define PRCC_KCLK_STORE(clk, base, bit) \ prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk -static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, +static struct clk_core *ux500_twocell_get(struct of_phandle_args *clkspec, void *data) { - struct clk **clk_data = data; + struct clk_core **clk_data = data; unsigned int base, bit; if (clkspec->args_count != 2) @@ -61,7 +61,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, struct device_node *np = NULL; struct device_node *child = NULL; const char *sgaclk_parent = NULL; - struct clk *clk, *rtc_clk, *twd_clk; + struct clk_core *clk, *rtc_clk, *twd_clk; if (of_have_populated_dt()) np = of_find_matching_node(NULL, u8500_clk_of_match); diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c index 20c8add..897daf6 100644 --- a/drivers/clk/ux500/u8540_clk.c +++ b/drivers/clk/ux500/u8540_clk.c @@ -17,7 +17,7 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, u32 clkrst5_base, u32 clkrst6_base) { - struct clk *clk; + struct clk_core *clk; /* Clock sources. */ /* Fixed ClockGen */ diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index bc96f10..8df4acc 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -121,13 +121,13 @@ static const struct clk_ops icst_ops = { .set_rate = icst_set_rate, }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, void __iomem *base) { - struct clk *clk; + struct clk_core *clk; struct clk_icst *icst; struct clk_init_data init; struct icst_params *pclone; diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h index 04e6f0a..ede867b 100644 --- a/drivers/clk/versatile/clk-icst.h +++ b/drivers/clk/versatile/clk-icst.h @@ -13,7 +13,7 @@ struct clk_icst_desc { u32 lock_offset; }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c index 1cc1330..6b35629 100644 --- a/drivers/clk/versatile/clk-impd1.c +++ b/drivers/clk/versatile/clk-impd1.c @@ -21,18 +21,18 @@ struct impd1_clk { char *pclkname; - struct clk *pclk; + struct clk_core *pclk; char *vco1name; - struct clk *vco1clk; + struct clk_core *vco1clk; char *vco2name; - struct clk *vco2clk; - struct clk *mmciclk; + struct clk_core *vco2clk; + struct clk_core *mmciclk; char *uartname; - struct clk *uartclk; + struct clk_core *uartclk; char *spiname; - struct clk *spiclk; + struct clk_core *spiclk; char *scname; - struct clk *scclk; + struct clk_core *scclk; struct clk_lookup *clks[15]; }; @@ -87,8 +87,8 @@ static const struct clk_icst_desc impd1_icst2_desc = { void integrator_impd1_clk_init(void __iomem *base, unsigned int id) { struct impd1_clk *imc; - struct clk *clk; - struct clk *pclk; + struct clk_core *clk; + struct clk_core *pclk; int i; if (id > 3) { diff --git a/drivers/clk/versatile/clk-integrator.c b/drivers/clk/versatile/clk-integrator.c index 734c4b8..dbcaa7b 100644 --- a/drivers/clk/versatile/clk-integrator.c +++ b/drivers/clk/versatile/clk-integrator.c @@ -39,7 +39,7 @@ static const struct clk_icst_desc __initdata cm_auxosc_desc = { static void __init of_integrator_cm_osc_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const struct clk_icst_desc *desc = &cm_auxosc_desc; const char *parent_name; diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c index c8b5231..4fa61b3 100644 --- a/drivers/clk/versatile/clk-realview.c +++ b/drivers/clk/versatile/clk-realview.c @@ -50,7 +50,7 @@ static const struct clk_icst_desc __initdata realview_osc4_desc = { */ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176) { - struct clk *clk; + struct clk_core *clk; /* APB clock dummy */ clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); diff --git a/drivers/clk/versatile/clk-sp810.c b/drivers/clk/versatile/clk-sp810.c index c6e86a9..9256d25 100644 --- a/drivers/clk/versatile/clk-sp810.c +++ b/drivers/clk/versatile/clk-sp810.c @@ -25,7 +25,7 @@ struct clk_sp810; struct clk_sp810_timerclken { struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_sp810 *sp810; int channel; }; @@ -36,8 +36,8 @@ struct clk_sp810 { void __iomem *base; spinlock_t lock; struct clk_sp810_timerclken timerclken[4]; - struct clk *refclk; - struct clk *timclk; + struct clk_core *refclk; + struct clk_core *timclk; }; static u8 clk_sp810_timerclken_get_parent(struct clk_hw *hw) @@ -79,29 +79,31 @@ static int clk_sp810_timerclken_prepare(struct clk_hw *hw) { struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - struct clk *old_parent = __clk_get_parent(hw->clk); - struct clk *new_parent; + struct clk_core *old_parent = __clk_get_parent(hw->clk); + struct clk_core *new_parent; if (!sp810->refclk) - sp810->refclk = of_clk_get(sp810->node, sp810->refclk_index); + sp810->refclk = of_clk_provider_get(sp810->node, + sp810->refclk_index); if (!sp810->timclk) - sp810->timclk = of_clk_get(sp810->node, sp810->timclk_index); + sp810->timclk = of_clk_provider_get(sp810->node, + sp810->timclk_index); if (WARN_ON(IS_ERR(sp810->refclk) || IS_ERR(sp810->timclk))) return -ENOENT; /* Select fastest parent */ - if (clk_get_rate(sp810->refclk) > clk_get_rate(sp810->timclk)) + if (clk_provider_get_rate(sp810->refclk) > clk_provider_get_rate(sp810->timclk)) new_parent = sp810->refclk; else new_parent = sp810->timclk; /* Switch the parent if necessary */ if (old_parent != new_parent) { - clk_prepare(new_parent); - clk_set_parent(hw->clk, new_parent); - clk_unprepare(old_parent); + clk_provider_prepare(new_parent); + clk_provider_set_parent(hw->clk, new_parent); + clk_provider_unprepare(old_parent); } return 0; @@ -112,8 +114,8 @@ static void clk_sp810_timerclken_unprepare(struct clk_hw *hw) struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - clk_put(sp810->timclk); - clk_put(sp810->refclk); + __clk_put(sp810->timclk); + __clk_put(sp810->refclk); } static const struct clk_ops clk_sp810_timerclken_ops = { @@ -123,7 +125,7 @@ static const struct clk_ops clk_sp810_timerclken_ops = { .set_parent = clk_sp810_timerclken_set_parent, }; -static struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, +static struct clk_core *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, void *data) { struct clk_sp810 *sp810 = data; diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c index 529a59c..c9e175f 100644 --- a/drivers/clk/versatile/clk-vexpress-osc.c +++ b/drivers/clk/versatile/clk-vexpress-osc.c @@ -73,7 +73,7 @@ static int vexpress_osc_probe(struct platform_device *pdev) struct clk_lookup *cl = pdev->dev.platform_data; /* Non-DT lookup */ struct clk_init_data init; struct vexpress_osc *osc; - struct clk *clk; + struct clk_core *clk; u32 range[2]; osc = devm_kzalloc(&pdev->dev, sizeof(*osc), GFP_KERNEL); diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c index 2d5e1b4..e77f3d5 100644 --- a/drivers/clk/versatile/clk-vexpress.c +++ b/drivers/clk/versatile/clk-vexpress.c @@ -17,7 +17,7 @@ #include <linux/err.h> #include <linux/vexpress.h> -static struct clk *vexpress_sp810_timerclken[4]; +static struct clk_core *vexpress_sp810_timerclken[4]; static DEFINE_SPINLOCK(vexpress_sp810_lock); static void __init vexpress_sp810_init(void __iomem *base) @@ -54,7 +54,7 @@ static const char * const vexpress_clk_24mhz_periphs[] __initconst = { void __init vexpress_clk_init(void __iomem *sp810_base) { - struct clk *clk; + struct clk_core *clk; int i; clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, @@ -77,7 +77,7 @@ void __init vexpress_clk_init(void __iomem *sp810_base) vexpress_sp810_init(sp810_base); for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++) - WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk)); + WARN_ON(clk_provider_set_parent(vexpress_sp810_timerclken[i], clk)); WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0], "v2m-timer0", "sp804")); diff --git a/drivers/clk/x86/clk-lpt.c b/drivers/clk/x86/clk-lpt.c index 812f83f..1b4a5e1 100644 --- a/drivers/clk/x86/clk-lpt.c +++ b/drivers/clk/x86/clk-lpt.c @@ -21,7 +21,7 @@ static int lpt_clk_probe(struct platform_device *pdev) { struct lpss_clk_data *drvdata; - struct clk *clk; + struct clk_core *clk; drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 246cf12..0efdd9a 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -67,8 +67,8 @@ enum zynq_clk { i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; -static struct clk *ps_clk; -static struct clk *clks[clk_max]; +static struct clk_core *ps_clk; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(armpll_lock); @@ -108,7 +108,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, const char **parents, int enable) { - struct clk *clk; + struct clk_core *clk; u32 enable_reg; char *mux_name; char *div0_name; @@ -154,7 +154,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); enable_reg = clk_readl(fclk_gate_reg) & 1; if (enable && !enable_reg) { - if (clk_prepare_enable(clks[fclk])) + if (clk_provider_prepare_enable(clks[fclk])) pr_warn("%s: FCLK%u enable failed\n", __func__, fclk - fclk0); } @@ -181,7 +181,7 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, const char *clk_name1, void __iomem *clk_ctrl, const char **parents, unsigned int two_gates) { - struct clk *clk; + struct clk_core *clk; char *mux_name; char *div_name; spinlock_t *lock; @@ -222,7 +222,7 @@ static void __init zynq_clk_setup(struct device_node *np) int i; u32 tmp; int ret; - struct clk *clk; + struct clk_core *clk; char *clk_name; unsigned int fclk_enable = 0; const char *clk_output_name[clk_max]; @@ -333,13 +333,13 @@ static void __init zynq_clk_setup(struct device_node *np) CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr2x]); + clk_provider_prepare_enable(clks[ddr2x]); clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr3x]); + clk_provider_prepare_enable(clks[ddr3x]); clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | @@ -351,7 +351,7 @@ static void __init zynq_clk_setup(struct device_node *np) clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, &dciclk_lock); - clk_prepare_enable(clks[dci]); + clk_provider_prepare_enable(clks[dci]); /* Peripheral clocks */ for (i = fclk0; i <= fclk3; i++) { @@ -505,10 +505,10 @@ static void __init zynq_clk_setup(struct device_node *np) /* leave debug clocks in the state the bootloader set them up to */ tmp = clk_readl(SLCR_DBG_CLK_CTRL); if (tmp & DBG_CLK_CTRL_CLKACT_TRC) - if (clk_prepare_enable(clks[dbg_trc])) + if (clk_provider_prepare_enable(clks[dbg_trc])) pr_warn("%s: trace clk enable failed\n", __func__); if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) - if (clk_prepare_enable(clks[dbg_apb])) + if (clk_provider_prepare_enable(clks[dbg_apb])) pr_warn("%s: debug APB clk enable failed\n", __func__); /* One gated clock for all APER clocks. */ diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c index cec9759..5176f65 100644 --- a/drivers/clk/zynq/pll.c +++ b/drivers/clk/zynq/pll.c @@ -193,12 +193,12 @@ static const struct clk_ops zynq_pll_ops = { * @lock Register lock * Returns handle to the registered clock. */ -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock) { struct zynq_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 reg; const char *parent_arr[1] = {parent}; unsigned long flags = 0; diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index 2620c48..c2461af 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -215,7 +215,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) { - ret = clk_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); + ret = clk_provider_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); if (ret < 0) return ret; } @@ -225,7 +225,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, return 0; if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret; } @@ -254,7 +254,7 @@ static int __fimc_pipeline_close(struct exynos_media_pipeline *ep) /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret == -ENXIO ? 0 : ret; } @@ -954,7 +954,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) while (--i >= 0) { if (IS_ERR(fmd->camclk[i].clock)) continue; - clk_put(fmd->camclk[i].clock); + __clk_put(fmd->camclk[i].clock); fmd->camclk[i].clock = ERR_PTR(-EINVAL); } @@ -962,7 +962,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_WBCLKS; i++) { if (IS_ERR(fmd->wbclk[i])) continue; - clk_put(fmd->wbclk[i]); + __clk_put(fmd->wbclk[i]); fmd->wbclk[i] = ERR_PTR(-EINVAL); } } @@ -971,7 +971,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) { struct device *dev = &fmd->pdev->dev; char clk_name[32]; - struct clk *clock; + struct clk_core *clock; int i, ret = 0; for (i = 0; i < FIMC_MAX_CAMCLKS; i++) @@ -979,7 +979,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_CAMCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { dev_err(dev, "Failed to get clock: %s\n", clk_name); @@ -1001,7 +1001,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = CLK_IDX_WB_B; i < FIMC_MAX_WBCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "pxl_async%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { v4l2_err(&fmd->v4l2_dev, "Failed to get clock: %s\n", clk_name); diff --git a/drivers/media/platform/exynos4-is/media-dev.h b/drivers/media/platform/exynos4-is/media-dev.h index 0321454..79e4b42 100644 --- a/drivers/media/platform/exynos4-is/media-dev.h +++ b/drivers/media/platform/exynos4-is/media-dev.h @@ -72,7 +72,7 @@ struct fimc_csis_info { }; struct fimc_camclk_info { - struct clk *clock; + struct clk_core *clock; int use_count; unsigned long frequency; }; @@ -124,7 +124,7 @@ struct fimc_md { struct fimc_sensor_info sensor[FIMC_MAX_SENSORS]; int num_sensors; struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS]; - struct clk *wbclk[FIMC_MAX_WBCLKS]; + struct clk_core *wbclk[FIMC_MAX_WBCLKS]; struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS]; struct fimc_dev *fimc[FIMC_MAX_DEVS]; struct fimc_is *fimc_is; @@ -141,7 +141,7 @@ struct fimc_md { } pinctl; struct cam_clk_provider { - struct clk *clks[FIMC_MAX_CAMCLKS]; + struct clk_core *clks[FIMC_MAX_CAMCLKS]; struct clk_onecell_data clk_data; struct device_node *of_node; struct cam_clk camclk[FIMC_MAX_CAMCLKS]; diff --git a/include/asm-generic/clkdev.h b/include/asm-generic/clkdev.h index 90a32a6..16d43d9 100644 --- a/include/asm-generic/clkdev.h +++ b/include/asm-generic/clkdev.h @@ -17,8 +17,8 @@ struct clk; -static inline int __clk_get(struct clk *clk) { return 1; } -static inline void __clk_put(struct clk *clk) { } +static inline int __clk_get(struct clk_core *clk) { return 1; } +static inline void __clk_put(struct clk_core *clk) { } static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) { diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index e8d8a35..6b9e6b4 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -22,8 +22,8 @@ * @mult_div1_reg: register containing the DPLL M and N bitfields * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input + * @clk_bypass: struct clk_core pointer to the clock's bypass clock input + * @clk_ref: struct clk_core pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() @@ -68,8 +68,8 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; + struct clk_core *clk_bypass; + struct clk_core *clk_ref; void __iomem *control_reg; u32 enable_mask; unsigned long last_rounded_rate; @@ -251,7 +251,7 @@ extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) -void omap2_init_clk_hw_omap_clocks(struct clk *clk); +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h index a990a59..6c35291 100644 --- a/include/linux/clk/zynq.h +++ b/include/linux/clk/zynq.h @@ -25,7 +25,7 @@ void zynq_clock_init(void); -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock); #endif diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index a947ab8..4b34c69 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -107,8 +107,8 @@ struct si5351_clkout_config { * @clkout: array of clkout configuration */ struct si5351_platform_data { - struct clk *clk_xtal; - struct clk *clk_clkin; + struct clk_core *clk_xtal; + struct clk_core *clk_clkin; enum si5351_pll_src pll_src[2]; struct si5351_clkout_config clkout[8]; }; -- 1.9.3

1 0

[alsa-devel] [PATCH v2] mfd: wm8994: declare dc servo register for wm8958 as volatile
by Nikesh Oswal 14 Aug '14

14 Aug '14

DC Servo register 57h holds the DC offset value after the hardware has completed the DC Servo Correction, so declare this register as volatile because it is changed by the hardware. Signed-off-by: Nikesh Oswal <nikesh(a)opensource.wolfsonmicro.com> --- drivers/mfd/wm8994-regmap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/wm8994-regmap.c b/drivers/mfd/wm8994-regmap.c index 2fbce9c..fa1630d 100644 --- a/drivers/mfd/wm8994-regmap.c +++ b/drivers/mfd/wm8994-regmap.c @@ -1169,6 +1169,7 @@ static bool wm8958_volatile_register(struct device *dev, unsigned int reg) case WM8958_FW_MINOR_0: case WM8958_FW_PATCH_1: case WM8958_FW_PATCH_0: + case WM8994_DC_SERVO_4: return true; default: return wm8994_volatile_register(dev, reg); -- 1.7.9.5

2 1

[alsa-devel] ASoC: of_parse_phandle techniques newbie question
by Matt Flax 14 Aug '14

14 Aug '14

Hi there, In implementing a codec/driver combination, I found that I have to re-write some of the snd_soc_dai_link with device tree related entries : http://mailman.alsa-project.org/pipermail/alsa-devel/2014-August/080034.html Can anyone explain to me why we have to do this, a little confused here ? For example : driver_dai.codec_name = NULL; driver_dai.codec_of_node = of_parse_phandle(np, ..... Why can't the codec be found from the codec_name which matches the previously probed codec ? thanks Matt

1 0

[alsa-devel] ASoC: CPU DAI samsung-i2s.0 not registered
by Matt Flax 14 Aug '14

14 Aug '14

Hi there, Any ideas why this problem is coming up when I try to load a driver ? Here is the device tree : i2s0: i2s@03830000 { compatible = "samsung,i2s-v5"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 &pdma0 9 &pdma0 8>; dma-names = "tx", "rx", "tx-sec"; clocks = <&clock_audss EXYNOS_I2S_BUS>, <&clock_audss EXYNOS_I2S_BUS>, <&clock_audss EXYNOS_SCLK_I2S>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; samsung,supports-6ch; samsung,supports-rstclr; samsung,supports-secdai; samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; }; implant: implant@0 { compatible = "bva,implant"; }; sound { compatible = "bva,implant-bva"; samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&implant>; };

3 6

Re: [alsa-devel] [v4 02/12] ASoC: Intel: mrfld: set private data for cpu-dai
by Lars-Peter Clausen 14 Aug '14

14 Aug '14

On 08/14/2014 07:36 AM, Subhransu S. Prusty wrote: > On Wed, Aug 13, 2014 at 09:50:43PM +0200, Lars-Peter Clausen wrote: >> [...] >>> +static int sst_media_dai_probe(struct snd_soc_dai *cpu_dai) >>> +{ >>> + struct sst_data *sst = dev_get_drvdata(cpu_dai->dev); >>> + >>> + snd_soc_dai_set_drvdata(cpu_dai, sst); >> >> snd_soc_dai_set_drvdata does dev_set_drvdata(dai->dev, data) >> internally, so this function does: >> >> dev_set_drvdata(cpu_dai->dev, dev_get_drvdata(cpu_dai->dev)); >> >> That's pretty much a noop. >> > > Agree. Intention was to use snd_soc_dai_* API. Anyway will remove and use > dev_get_drvdata(dai->dev) directly. > It's totally fine to use snd_soc_dai_get_drvdata() through the driver. It's just that this probe function does nothing and can be removed.

1 0

[alsa-devel] What is the command line commands to use UAC2 at USB client side?
by Xuebing Wang 14 Aug '14

14 Aug '14

Hi Community, Based on Freescale platform , I am trying to use USB Audio Class version 2.0. Host can detect this UAC2 device. At device side (after modprobe g_audio): root@imx6slevk:~# aplay -l **** List of PLAYBACK Hardware Devices **** card 0: wm8962audio [wm8962-audio], device 0: HiFi wm8962-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 1: imxspdif [imx-spdif], device 0: S/PDIF PCM Playback dit-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 2: UAC2Gadget [UAC2_Gadget], device 0: UAC2 PCM [UAC2 PCM] Subdevices: 1/1 Subdevice #0: subdevice #0 At device side, in driver/usb/gadget/Kconfig, it says before for CONFIG_USB_AUDIO ------------------------- This driver doesn't expect any real Audio codec to be present on the device - the audio streams are simply sinked to and sourced from a virtual ALSA sound card created. The user-space application may choose to do whatever it wants with the data received from the USB Host and choose to provide whatever it wants as audio data to the USB Host. ------------------------- My question is: at device side, how to configure sink/source for UAC2 virtual ALSA sound card (hw:2,0, UAC2_Gadget)? Thank you very much. Xuebing Wang

1 0

[alsa-devel] [PATCH v2 2/2] mfd: arizona: Update DT binding to support INn_MODE init_data
by Inha Song 14 Aug '14

14 Aug '14

This patch update DT binding to support INn_MODE init_data. Each input signal path can be configurated either as a Analogue or Digital using the INn_MODE registers. Signed-off-by: Inha Song <ideal.song(a)samsung.com> --- Documentation/devicetree/bindings/mfd/arizona.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index 5c7e723..b8c131e 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -42,6 +42,14 @@ Optional properties: the chip default will be used. If present exactly five values must be specified. + - wlf,inmode : A list of INn_MODE register values, where n is the number + of input signal. Each input signal path can be configurated either as a + Analogue or Digital using the INn_MODE registers. If absent, INn_MODE + registers set to 0 by default. If present, values must be specified less + than or equal to the number of input singal. If values less than the + number of input signal, elements that has not been specifed are set to 0 + by default. + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if they are being externally supplied. As covered in Documentation/devicetree/bindings/regulator/regulator.txt -- 2.0.0.390.gcb682f8

2 2

[alsa-devel] SGTL500 and its external MCLK
by jonsmirl＠gmail.com 13 Aug '14

13 Aug '14

For testing purposes I have a SGTL5000 wired up to I2S on my Allwinner A20. SGTL5000 needs an external MCLK. It attaches to it like this: sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&iis0>; And in the probe code.... (this should use a name for the clock in the DTS) sgtl5000->mclk = devm_clk_get(&client->dev, NULL); if (IS_ERR(sgtl5000->mclk)) { ret = PTR_ERR(sgtl5000->mclk); dev_err(&client->dev, "Failed to get mclock: %d\n", ret); /* Defer the probe to see if the clk will be provided later */ if (ret == -ENOENT) return -EPROBE_DEFER; return ret; } ret = clk_prepare_enable(sgtl5000->mclk); if (ret) return ret; So the sgtl5000 driver has a handle to the clock. But then the driver implements set_dai_sysclk() to get the rate. And a board specific machine driver like imx-sgtl5000.c is used to set this rate into the sgtl5000 driver. /* set codec sysclk */ static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = codec_dai->codec; struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); switch (clk_id) { case SGTL5000_SYSCLK: sgtl5000->sysclk = freq; break; default: return -EINVAL; } return 0; } Since the sgtl5000 driver has the handle to the clock, can't it just ask the clock for its rate? If it directly asked the clock for its rate it looks like this codec could be bound with simple-audio-card and not need a machine driver. -- Jon Smirl jonsmirl(a)gmail.com

3 6

[alsa-devel] [PATCH] ASoC: pxa-ssp: drop SNDRV_PCM_FMTBIT_S24_LE
by Daniel Mack 13 Aug '14

13 Aug '14

This mode is unsupported, as the DMA controller can't do zero-padding of samples. Signed-off-by: Daniel Mack <zonque(a)gmail.com> Reported-by: Johannes Stezenbach <js(a)sig21.net> Cc: Eric Miao <eric.y.miao(a)gmail.com> Cc: Mark Brown <broonie(a)kernel.org> --- sound/soc/pxa/pxa-ssp.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c index 199a8b3..2db467f 100644 --- a/sound/soc/pxa/pxa-ssp.c +++ b/sound/soc/pxa/pxa-ssp.c @@ -764,9 +764,7 @@ static int pxa_ssp_remove(struct snd_soc_dai *dai) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) -#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ - SNDRV_PCM_FMTBIT_S24_LE | \ - SNDRV_PCM_FMTBIT_S32_LE) +#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) static const struct snd_soc_dai_ops pxa_ssp_dai_ops = { .startup = pxa_ssp_startup, -- 2.0.4

2 1

[alsa-devel] [PATCH V4 0/2] refine esai for tdm support
by Shengjiu Wang 13 Aug '14

13 Aug '14

These patchs is to refine esai for tdm support. Changes for V4 - update the comments for patch 2 Changes for V3 - update the comments for patch 2 Changes for V2 - update the comments according the reviewer's suggestion - add init value for slots and change pin to pins. Shengjiu Wang (2): ASoC: fsl_esai: refine esai for TDM support Revert "ASoC: fsl-esai: Add .xlate_tdm_slot_mask() support." sound/soc/fsl/Kconfig | 1 - sound/soc/fsl/fsl_esai.c | 16 +++++++++++----- sound/soc/fsl/fsl_esai.h | 8 ++++---- 3 files changed, 15 insertions(+), 10 deletions(-) -- 1.7.9.5

3 4

[alsa-devel] Ordering in soc_pcm_hw_params()
by jonsmirl＠gmail.com 13 Aug '14

13 Aug '14

soc_pcm_hw_params() sets the parameters in this order: link, codec, cpu, platform This is tripping me up when switching between the 44100 and 48000 families. If previous song was 44100 then the codec has sysclk set to the 44100 family. Now I play a 48000 family song. codec gets new hardware params and errors out because sysclk is still in the 44100 family. I have code in the cpu set_hw_params which will switch the sysclk, but it never gets to run because the codec set_hw_params() has already errored out. Shouldn't this order be: platform, link, cpu, codec -- Jon Smirl jonsmirl(a)gmail.com

3 23

[alsa-devel] headset vs speaker
by Patrick Shirkey 13 Aug '14

13 Aug '14

Hi, How does headset detection work in general with alsa? I need to understand the Allwinner A20 SoC audio driver logic for the headset and speaker outputs. My goal is to enable standard audio playback through the headset but to allow another audio stream to playback through the speaker while the headset is connected. I have seen that it is possible with other chips like the hda_intel. Is it a hardware limitation or driver/software regulated? -- Patrick Shirkey Boost Hardware Ltd

1 0

[alsa-devel] [PATCH] ASoC: wm_hubs: Fix DC Servo readback
by Nikesh Oswal 13 Aug '14

13 Aug '14

wm_hubs is a common driver code shared by WM8958, WM1811, WM8944 and WM8993 all these codecs have the DC Servo Values either in register 57h or 59h. Current code was reading register 58h for WM8958 and WM8994 revisions 2 and 3 but looking at the data sheet the DC Servo Values are stored in register 57h for these codecs. This patch fixes it by reading the correct register for DC Servo Signed-off-by: Nikesh Oswal <nikesh(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm_hubs.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c index 916817f..95c5d71 100644 --- a/sound/soc/codecs/wm_hubs.c +++ b/sound/soc/codecs/wm_hubs.c @@ -210,9 +210,6 @@ static int wm_hubs_read_dc_servo(struct snd_soc_codec *codec, case 2: dcs_reg = WM8994_DC_SERVO_4E; break; - case 1: - dcs_reg = WM8994_DC_SERVO_READBACK; - break; default: dcs_reg = WM8993_DC_SERVO_3; break; -- 1.7.9.5

3 5

[alsa-devel] [PATCH] mfd: wm8994: declare dc servo register for wm8958 as volatile
by Nikesh Oswal 13 Aug '14

13 Aug '14

DC Servo register 57h holds the DC offset value after the hardware has completed the DC Servo Correction, so declare this register as volatile because it is changed by the hardware. Signed-off-by: Nikesh Oswal <nikesh(a)opensource.wolfsonmicro.com> --- drivers/mfd/wm8994-regmap.c | 1 + include/linux/mfd/wm8994/registers.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/mfd/wm8994-regmap.c b/drivers/mfd/wm8994-regmap.c index 2fbce9c..e775565 100644 --- a/drivers/mfd/wm8994-regmap.c +++ b/drivers/mfd/wm8994-regmap.c @@ -1169,6 +1169,7 @@ static bool wm8958_volatile_register(struct device *dev, unsigned int reg) case WM8958_FW_MINOR_0: case WM8958_FW_PATCH_1: case WM8958_FW_PATCH_0: + case WM8958_DC_SERVO: return true; default: return wm8994_volatile_register(dev, reg); diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index db8cef3..85b4fec 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h @@ -71,6 +71,7 @@ #define WM8994_DC_SERVO_1 0x54 #define WM8994_DC_SERVO_2 0x55 #define WM8994_DC_SERVO_4 0x57 +#define WM8958_DC_SERVO 0x57 #define WM8994_DC_SERVO_READBACK 0x58 #define WM8994_DC_SERVO_4E 0x59 #define WM8994_ANALOGUE_HP_1 0x60 -- 1.7.9.5

2 2

[alsa-devel] [PATCH 1/2] mfd: arizona: Add support for INn_MODE register control
by Inha Song 13 Aug '14

13 Aug '14

Some boards need to set the INn_MODE[1:0] register to change the input signal patch. This wlf,inmode property is optional. If present values must be specified by the number of ARIZONA_MAX_INPUT. Example: - wlf,inmode = <2 0 2 0>; /* IN1, IN3 use DMIC */ Signed-off-by: Inha Song <ideal.song(a)samsung.com> --- drivers/mfd/arizona-core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c index 10a0cb9..4b2eb73 100644 --- a/drivers/mfd/arizona-core.c +++ b/drivers/mfd/arizona-core.c @@ -560,6 +560,10 @@ static int arizona_of_get_core_pdata(struct arizona *arizona) ret); } + of_property_read_u32_array(arizona->dev->of_node, + "wlf,inmode", + arizona->pdata.inmode, + ARRAY_SIZE(arizona->pdata.inmode)); return 0; } -- 2.0.0.390.gcb682f8

2 3

[alsa-devel] [PATCH 8/14] ASoC: rsnd: delete unneeded test before of_node_put
by Julia Lawall 13 Aug '14

13 Aug '14

From: Julia Lawall <Julia.Lawall(a)lip6.fr> Of_node_put supports NULL as its argument, so the initial test is not necessary. Suggested by Uwe Kleine-König. The semantic patch that fixes this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e; @@ -if (e) of_node_put(e); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall(a)lip6.fr> --- sound/soc/sh/rcar/core.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c index 19f7896..1922ec5 100644 --- a/sound/soc/sh/rcar/core.c +++ b/sound/soc/sh/rcar/core.c @@ -798,10 +798,8 @@ if (name##_node) { \ mod_parse(src); mod_parse(dvc); - if (playback) - of_node_put(playback); - if (capture) - of_node_put(capture); + of_node_put(playback); + of_node_put(capture); } dai_i++;

2 1

[alsa-devel] [PATCH] ASoC: fsl_sai: Make Synchronous and Asynchronous modes exclusive
by Nicolin Chen 13 Aug '14

13 Aug '14

The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added new Device Tree bindings for Asynchronous and Synchronous modes support. However, these two shall not be present at the same time. So this patch just simply makes them exclusive so as to avoid incorrect Device Tree binding usage. Signed-off-by: Nicolin Chen <nicoleotsuka(a)gmail.com> --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 +-- sound/soc/fsl/fsl_sai.c | 7 +++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 77864f4..dc9f9c3 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -38,8 +38,7 @@ Note: default synchronous mode (sync Rx with Tx) will be used, which means both transimitter and receiver will send and receive data by following clocks of transimitter. -- fsl,sai-asynchronous will be ignored if fsl,sai-synchronous-rx property is - already present. +- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. Example: sai2: sai@40031000 { diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index ef7c758..4c9e71c 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -634,6 +634,13 @@ static int fsl_sai_probe(struct platform_device *pdev) fsl_sai_dai.symmetric_channels = 1; fsl_sai_dai.symmetric_samplebits = 1; + if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && + of_find_property(np, "fsl,sai-asynchronous", NULL)) { + /* error out if both synchronous and asynchronous are present */ + dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); + return -EINVAL; + } + if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { /* Sync Rx with Tx */ sai->synchronous[RX] = false; -- 1.8.4

2 1

[alsa-devel] [PATCH v2] ASoC: wm8994: Demux the microphone detection IRQ
by Nikesh Oswal 13 Aug '14

13 Aug '14

Current code only allows direct routing of the WM8994 microphone detection signal to a GPIO this change adds support to demux the interrupt from the main interrupt line of the codec. Signed-off-by: Nikesh Oswal <nikesh(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm8994.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 247b390..557156e 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -4089,17 +4089,23 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) switch (control->type) { case WM8994: - if (wm8994->micdet_irq) { + if (wm8994->micdet_irq) ret = request_threaded_irq(wm8994->micdet_irq, NULL, wm8994_mic_irq, IRQF_TRIGGER_RISING, "Mic1 detect", wm8994); - if (ret != 0) - dev_warn(codec->dev, - "Failed to request Mic1 detect IRQ: %d\n", - ret); - } + else + ret = wm8994_request_irq(wm8994->wm8994, + WM8994_IRQ_MIC1_DET, + wm8994_mic_irq, "Mic 1 detect", + wm8994); + + if (ret != 0) + dev_warn(codec->dev, + "Failed to request Mic1 detect IRQ: %d\n", + ret); + ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, -- 1.7.9.5

2 1

[alsa-devel] [PATCH 1/1] ASoC: sirf: usp: Add bitclock inversion support
by Rongjun Ying 13 Aug '14

13 Aug '14

Signed-off-by: Rongjun Ying <rongjun.ying(a)csr.com> --- sound/soc/sirf/sirf-usp.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/sound/soc/sirf/sirf-usp.c b/sound/soc/sirf/sirf-usp.c index 3a73037..186dc7f 100644 --- a/sound/soc/sirf/sirf-usp.c +++ b/sound/soc/sirf/sirf-usp.c @@ -100,6 +100,16 @@ static int sirf_usp_pcm_set_dai_fmt(struct snd_soc_dai *dai, return -EINVAL; } + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + usp->daifmt_format |= (fmt & SND_SOC_DAIFMT_INV_MASK); + break; + default: + return -EINVAL; + } + return 0; } @@ -177,7 +187,7 @@ static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream, shifter_len = data_len; - switch (usp->daifmt_format) { + switch (usp->daifmt_format & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL, USP_I2S_SYNC_CHG, USP_I2S_SYNC_CHG); @@ -193,6 +203,18 @@ static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + switch (usp->daifmt_format & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + regmap_update_bits(usp->regmap, USP_MODE1, + USP_RXD_ACT_EDGE_FALLING | USP_TXD_ACT_EDGE_FALLING, + USP_RXD_ACT_EDGE_FALLING); + break; + default: + return -EINVAL; + } + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) regmap_update_bits(usp->regmap, USP_TX_FRAME_CTRL, USP_TXC_DATA_LEN_MASK | USP_TXC_FRAME_LEN_MASK -- 2.0.4 Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom More information can be found at www.csr.com. Keep up to date with CSR on our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people, YouTube, www.youtube.com/user/CSRplc, Facebook, www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at www.twitter.com/CSR_plc. New for 2014, you can now access the wide range of products powered by aptX at www.aptx.com.

2 1

Re: [alsa-devel] [PATCH] ASoC: wm8962: Correct the bit offset to enable mono speaker output
by Charles Keepax 13 Aug '14

13 Aug '14

On Fri, Aug 08, 2014 at 09:55:43AM +0000, Peter Chan wrote: > I have a question about the wm8962 mono speaker mode. In SPK_MONO description at table 73, it says "When SPK_MONO is enabled, both speakers output the signal from the left channel". Does it mean only the left channel control the output in mono speaker mode? > > Thanks, > Peter > > -----Original Message----- > From: Nicolin Chen [mailto:Guangyu.Chen@freescale.com] > Sent: Friday, August 08, 2014 4:21 PM > To: Mark Brown > Cc: Nicolin Chen; alsa-devel(a)alsa-project.org; tiwai(a)suse.de; patches(a)opensource.wolfsonmicro.com; Wang Shengjiu-B02247; lgirdwood(a)gmail.com; linux-kernel(a)vger.kernel.org; CHAN Peter-B18700; ckeepax(a)opensource.wolfsonmicro.com; rf(a)opensource.wolfsonmicro.com > Subject: Re: [alsa-devel] [PATCH] ASoC: wm8962: Correct the bit offset to enable mono speaker output > > On Thu, Aug 07, 2014 at 05:58:36PM +0100, Mark Brown wrote: > > On Thu, Aug 07, 2014 at 07:55:49PM +0800, Nicolin Chen wrote: > > > As WM8962 datasheet describes for SPK_MONO bit of R51: When SPK_MONO > > > is set to '1', both speakers output the signal from the left channel. > > > > > So for mono speaker widget, we shall enable Left Channel whose > > > enable bit is 6 instead of 7 (Right Channel). > > > > > > This patches just simply corrects the bit offset. > > > > > spkmixl, ARRAY_SIZE(spkmixl)), SND_SOC_DAPM_MUX_E("Speaker > > > PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, > > > out_pga_event, SND_SOC_DAPM_POST_PMU), > > > -SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, > > > NULL, 0), > > > +SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 6, 0, > > > +NULL, 0), > > > SND_SOC_DAPM_OUTPUT("SPKOUT"), > > > }; > > > > Someone who's name I'd need to look up submitted an identical fix off > > list recently - I checked the datasheet and it seems that in mono mode > > the speaker output actually wants both left and right channels active > > so there is a bug here but this isn't the fix. > > I rechecked the datasheet and found that the hardware needs to tie both outputs and enable both bits. So the patch should be invalid. > > But our customer reported that they did try to set both SPKOUTR_ENA and SPKOUTL_ENA bits in mono mode but the sound is lousy. If setting SPKOUTR_ENA alone, the speaker has no sound. Only setting SPKOUTL_ENA bit get the correct speaker output in mono mode. >From the wording of "tie both outputs together" in the datasheet I would assume that means both should be fed the same audio? Was this done? I will try to give the hardware guys here a shout and see if I can get some clarification on mono mode on this device. Thanks, Charles

3 3

[alsa-devel] [PATCH v5 3/6] clk: Move all drivers to use internal API
by Tomeu Vizoso 13 Aug '14

13 Aug '14

In preparation to change the public API to return a per-user clk structure, remove any usage of this public API from the clock implementations. The reason for having this in a separate commit from the one that introduces the implementation of the new functions is to separate the changes generated with Coccinelle from the rest, and keep the patches' size reasonable. Signed-off-by: Tomeu Vizoso <tomeu.vizoso(a)collabora.com> --- arch/arm/mach-dove/common.c | 10 +- arch/arm/mach-imx/clk-busy.c | 8 +- arch/arm/mach-imx/clk-fixup-div.c | 4 +- arch/arm/mach-imx/clk-fixup-mux.c | 4 +- arch/arm/mach-imx/clk-gate2.c | 4 +- arch/arm/mach-imx/clk-imx1.c | 2 +- arch/arm/mach-imx/clk-imx21.c | 2 +- arch/arm/mach-imx/clk-imx25.c | 8 +- arch/arm/mach-imx/clk-imx27.c | 4 +- arch/arm/mach-imx/clk-imx31.c | 10 +- arch/arm/mach-imx/clk-imx35.c | 22 +- arch/arm/mach-imx/clk-imx51-imx53.c | 77 +++--- arch/arm/mach-imx/clk-imx6q.c | 38 +-- arch/arm/mach-imx/clk-imx6sl.c | 13 +- arch/arm/mach-imx/clk-imx6sx.c | 97 ++++--- arch/arm/mach-imx/clk-pfd.c | 4 +- arch/arm/mach-imx/clk-pllv1.c | 4 +- arch/arm/mach-imx/clk-pllv2.c | 4 +- arch/arm/mach-imx/clk-pllv3.c | 4 +- arch/arm/mach-imx/clk-vf610.c | 42 +-- arch/arm/mach-imx/clk.c | 8 +- arch/arm/mach-imx/clk.h | 38 +-- arch/arm/mach-kirkwood/common.c | 22 +- arch/arm/mach-msm/clock-pcom.c | 2 +- arch/arm/mach-mv78xx0/common.c | 2 +- arch/arm/mach-omap2/cclock2420_data.c | 168 ++++++------ arch/arm/mach-omap2/cclock2430_data.c | 186 ++++++------- arch/arm/mach-omap2/cclock3xxx_data.c | 370 +++++++++++++------------- arch/arm/mach-omap2/clkt2xxx_dpll.c | 4 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 4 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 2 +- arch/arm/mach-omap2/clkt_clksel.c | 46 ++-- arch/arm/mach-omap2/clkt_dpll.c | 8 +- arch/arm/mach-omap2/clock.c | 52 ++-- arch/arm/mach-omap2/clock.h | 20 +- arch/arm/mach-omap2/clock3xxx.c | 22 +- arch/arm/mach-omap2/clock3xxx.h | 4 +- arch/arm/mach-omap2/clock_common_data.c | 2 +- arch/arm/mach-omap2/clockdomain.c | 8 +- arch/arm/mach-omap2/clockdomain.h | 4 +- arch/arm/mach-omap2/display.c | 4 +- arch/arm/mach-omap2/dpll3xxx.c | 28 +- arch/arm/mach-omap2/dpll44xx.c | 4 +- arch/arm/mach-omap2/mcbsp.c | 4 +- arch/arm/mach-omap2/omap_device.c | 8 +- arch/arm/mach-omap2/omap_hwmod.c | 42 +-- arch/arm/mach-omap2/omap_hwmod.h | 12 +- arch/arm/mach-omap2/pm24xx.c | 12 +- arch/arm/mach-orion5x/common.c | 2 +- arch/arm/plat-orion/common.c | 20 +- arch/arm/plat-orion/include/plat/common.h | 12 +- arch/powerpc/platforms/512x/clock-commonclk.c | 48 ++-- drivers/clk/at91/clk-main.c | 24 +- drivers/clk/at91/clk-master.c | 6 +- drivers/clk/at91/clk-peripheral.c | 12 +- drivers/clk/at91/clk-pll.c | 6 +- drivers/clk/at91/clk-plldiv.c | 6 +- drivers/clk/at91/clk-programmable.c | 10 +- drivers/clk/at91/clk-slow.c | 24 +- drivers/clk/at91/clk-smd.c | 6 +- drivers/clk/at91/clk-system.c | 6 +- drivers/clk/at91/clk-usb.c | 18 +- drivers/clk/at91/clk-utmi.c | 6 +- drivers/clk/bcm/clk-kona-setup.c | 6 +- drivers/clk/bcm/clk-kona.c | 12 +- drivers/clk/bcm/clk-kona.h | 2 +- drivers/clk/berlin/berlin2-avpll.c | 4 +- drivers/clk/berlin/berlin2-avpll.h | 4 +- drivers/clk/berlin/berlin2-div.c | 2 +- drivers/clk/berlin/berlin2-div.h | 2 +- drivers/clk/berlin/berlin2-pll.c | 2 +- drivers/clk/berlin/berlin2-pll.h | 2 +- drivers/clk/berlin/bg2.c | 12 +- drivers/clk/berlin/bg2q.c | 8 +- drivers/clk/clk-axi-clkgen.c | 2 +- drivers/clk/clk-axm5516.c | 4 +- drivers/clk/clk-bcm2835.c | 2 +- drivers/clk/clk-composite.c | 6 +- drivers/clk/clk-divider.c | 8 +- drivers/clk/clk-efm32gg.c | 2 +- drivers/clk/clk-fixed-factor.c | 6 +- drivers/clk/clk-fixed-rate.c | 8 +- drivers/clk/clk-fractional-divider.c | 4 +- drivers/clk/clk-gate.c | 4 +- drivers/clk/clk-highbank.c | 8 +- drivers/clk/clk-ls1x.c | 16 +- drivers/clk/clk-max77686.c | 10 +- drivers/clk/clk-moxart.c | 8 +- drivers/clk/clk-mux.c | 6 +- drivers/clk/clk-nomadik.c | 14 +- drivers/clk/clk-nspire.c | 4 +- drivers/clk/clk-ppc-corenet.c | 8 +- drivers/clk/clk-s2mps11.c | 6 +- drivers/clk/clk-si5351.c | 17 +- drivers/clk/clk-si570.c | 4 +- drivers/clk/clk-twl6040.c | 2 +- drivers/clk/clk-u300.c | 12 +- drivers/clk/clk-vt8500.c | 4 +- drivers/clk/clk-wm831x.c | 6 +- drivers/clk/clk-xgene.c | 12 +- drivers/clk/clk.h | 4 +- drivers/clk/hisilicon/clk-hi3620.c | 8 +- drivers/clk/hisilicon/clk.c | 16 +- drivers/clk/hisilicon/clk.h | 2 +- drivers/clk/hisilicon/clkgate-separated.c | 4 +- drivers/clk/keystone/gate.c | 6 +- drivers/clk/keystone/pll.c | 10 +- drivers/clk/mmp/clk-apbc.c | 4 +- drivers/clk/mmp/clk-apmu.c | 4 +- drivers/clk/mmp/clk-frac.c | 4 +- drivers/clk/mmp/clk-mmp2.c | 14 +- drivers/clk/mmp/clk-pxa168.c | 12 +- drivers/clk/mmp/clk-pxa910.c | 12 +- drivers/clk/mmp/clk.h | 8 +- drivers/clk/mvebu/clk-corediv.c | 4 +- drivers/clk/mvebu/clk-cpu.c | 8 +- drivers/clk/mvebu/common.c | 14 +- drivers/clk/mxs/clk-div.c | 4 +- drivers/clk/mxs/clk-frac.c | 4 +- drivers/clk/mxs/clk-imx23.c | 4 +- drivers/clk/mxs/clk-imx28.c | 4 +- drivers/clk/mxs/clk-pll.c | 4 +- drivers/clk/mxs/clk-ref.c | 4 +- drivers/clk/mxs/clk.h | 16 +- drivers/clk/qcom/clk-rcg.c | 6 +- drivers/clk/qcom/clk-rcg2.c | 14 +- drivers/clk/qcom/clk-regmap.c | 2 +- drivers/clk/qcom/clk-regmap.h | 2 +- drivers/clk/qcom/common.c | 6 +- drivers/clk/qcom/gcc-msm8660.c | 2 +- drivers/clk/qcom/gcc-msm8960.c | 2 +- drivers/clk/qcom/gcc-msm8974.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 6 +- drivers/clk/rockchip/clk-rockchip.c | 2 +- drivers/clk/samsung/clk-exynos-audss.c | 16 +- drivers/clk/samsung/clk-exynos4.c | 6 +- drivers/clk/samsung/clk-pll.c | 6 +- drivers/clk/samsung/clk-pll.h | 2 +- drivers/clk/samsung/clk-s3c2410-dclk.c | 10 +- drivers/clk/samsung/clk.c | 22 +- drivers/clk/samsung/clk.h | 2 +- drivers/clk/shmobile/clk-div6.c | 2 +- drivers/clk/shmobile/clk-emev2.c | 4 +- drivers/clk/shmobile/clk-mstp.c | 6 +- drivers/clk/shmobile/clk-r8a7740.c | 6 +- drivers/clk/shmobile/clk-r8a7779.c | 6 +- drivers/clk/shmobile/clk-rcar-gen2.c | 10 +- drivers/clk/shmobile/clk-rz.c | 6 +- drivers/clk/sirf/clk-atlas6.c | 2 +- drivers/clk/sirf/clk-common.c | 30 +-- drivers/clk/sirf/clk-prima2.c | 2 +- drivers/clk/socfpga/clk-gate.c | 2 +- drivers/clk/socfpga/clk-periph.c | 2 +- drivers/clk/socfpga/clk-pll.c | 4 +- drivers/clk/spear/clk-aux-synth.c | 8 +- drivers/clk/spear/clk-frac-synth.c | 4 +- drivers/clk/spear/clk-gpt-synth.c | 4 +- drivers/clk/spear/clk-vco-pll.c | 8 +- drivers/clk/spear/clk.h | 14 +- drivers/clk/spear/spear1310_clock.c | 2 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/clk/spear/spear3xx_clock.c | 16 +- drivers/clk/spear/spear6xx_clock.c | 2 +- drivers/clk/st/clkgen-fsyn.c | 22 +- drivers/clk/st/clkgen-mux.c | 32 +-- drivers/clk/st/clkgen-pll.c | 34 +-- drivers/clk/sunxi/clk-a10-hosc.c | 2 +- drivers/clk/sunxi/clk-a20-gmac.c | 2 +- drivers/clk/sunxi/clk-factors.c | 4 +- drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 2 +- drivers/clk/sunxi/clk-sun6i-apb0.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 6 +- drivers/clk/sunxi/clk-sunxi.c | 18 +- drivers/clk/tegra/clk-audio-sync.c | 4 +- drivers/clk/tegra/clk-divider.c | 4 +- drivers/clk/tegra/clk-periph-gate.c | 4 +- drivers/clk/tegra/clk-periph.c | 8 +- drivers/clk/tegra/clk-pll-out.c | 4 +- drivers/clk/tegra/clk-pll.c | 40 +-- drivers/clk/tegra/clk-super.c | 4 +- drivers/clk/tegra/clk-tegra-audio.c | 4 +- drivers/clk/tegra/clk-tegra-fixed.c | 8 +- drivers/clk/tegra/clk-tegra-periph.c | 12 +- drivers/clk/tegra/clk-tegra-pmc.c | 4 +- drivers/clk/tegra/clk-tegra-super-gen4.c | 8 +- drivers/clk/tegra/clk-tegra114.c | 10 +- drivers/clk/tegra/clk-tegra124.c | 6 +- drivers/clk/tegra/clk-tegra20.c | 12 +- drivers/clk/tegra/clk-tegra30.c | 8 +- drivers/clk/tegra/clk.c | 24 +- drivers/clk/tegra/clk.h | 38 +-- drivers/clk/ti/apll.c | 8 +- drivers/clk/ti/clk-2xxx.c | 8 +- drivers/clk/ti/clk-33xx.c | 18 +- drivers/clk/ti/clk-3xxx.c | 8 +- drivers/clk/ti/clk-43xx.c | 8 +- drivers/clk/ti/clk-44xx.c | 16 +- drivers/clk/ti/clk-54xx.c | 25 +- drivers/clk/ti/clk-7xx.c | 16 +- drivers/clk/ti/clk-dra7-atl.c | 6 +- drivers/clk/ti/clk.c | 2 +- drivers/clk/ti/clockdomain.c | 4 +- drivers/clk/ti/composite.c | 2 +- drivers/clk/ti/divider.c | 6 +- drivers/clk/ti/dpll.c | 8 +- drivers/clk/ti/fixed-factor.c | 2 +- drivers/clk/ti/gate.c | 2 +- drivers/clk/ti/interface.c | 2 +- drivers/clk/ti/mux.c | 6 +- drivers/clk/ux500/abx500-clk.c | 2 +- drivers/clk/ux500/clk-prcc.c | 8 +- drivers/clk/ux500/clk-prcmu.c | 16 +- drivers/clk/ux500/clk-sysctrl.c | 10 +- drivers/clk/ux500/clk.h | 22 +- drivers/clk/ux500/u8500_clk.c | 2 +- drivers/clk/ux500/u8500_of_clk.c | 12 +- drivers/clk/ux500/u8540_clk.c | 2 +- drivers/clk/versatile/clk-icst.c | 4 +- drivers/clk/versatile/clk-icst.h | 2 +- drivers/clk/versatile/clk-impd1.c | 18 +- drivers/clk/versatile/clk-integrator.c | 2 +- drivers/clk/versatile/clk-realview.c | 2 +- drivers/clk/versatile/clk-sp810.c | 30 ++- drivers/clk/versatile/clk-vexpress-osc.c | 2 +- drivers/clk/versatile/clk-vexpress.c | 6 +- drivers/clk/x86/clk-lpt.c | 2 +- drivers/clk/zynq/clkc.c | 22 +- drivers/clk/zynq/pll.c | 4 +- drivers/media/platform/exynos4-is/media-dev.c | 16 +- drivers/media/platform/exynos4-is/media-dev.h | 6 +- include/asm-generic/clkdev.h | 4 +- include/linux/clk/ti.h | 10 +- include/linux/clk/zynq.h | 2 +- include/linux/platform_data/si5351.h | 4 +- 235 files changed, 1523 insertions(+), 1486 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 0d1a892..4d95685 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -71,9 +71,9 @@ void __init dove_map_io(void) static int dove_tclk; static DEFINE_SPINLOCK(gating_lock); -static struct clk *tclk; +static struct clk_core *tclk; -static struct clk __init *dove_register_gate(const char *name, +static struct clk_core __init *dove_register_gate(const char *name, const char *parent, u8 bit_idx) { return clk_register_gate(NULL, name, parent, 0, @@ -83,9 +83,9 @@ static struct clk __init *dove_register_gate(const char *name, static void __init dove_clk_init(void) { - struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; - struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; - struct clk *xor0, *xor1, *ge, *gephy; + struct clk_core *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; + struct clk_core *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; + struct clk_core *xor0, *xor1, *ge, *gephy; tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, dove_tclk); diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c index 4bb1bc4..e4161ed 100644 --- a/arch/arm/mach-imx/clk-busy.c +++ b/arch/arm/mach-imx/clk-busy.c @@ -78,12 +78,12 @@ static struct clk_ops clk_busy_divider_ops = { .set_rate = clk_busy_divider_set_rate, }; -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift) { struct clk_busy_divider *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); @@ -152,12 +152,12 @@ static struct clk_ops clk_busy_mux_ops = { .set_parent = clk_busy_mux_set_parent, }; -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents) { struct clk_busy_mux *busy; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; busy = kzalloc(sizeof(*busy), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c index 21db020..8a62bfd 100644 --- a/arch/arm/mach-imx/clk-fixup-div.c +++ b/arch/arm/mach-imx/clk-fixup-div.c @@ -92,12 +92,12 @@ static const struct clk_ops clk_fixup_div_ops = { .set_rate = clk_fixup_div_set_rate, }; -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)) { struct clk_fixup_div *fixup_div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c index 0d40b35..e29dc62 100644 --- a/arch/arm/mach-imx/clk-fixup-mux.c +++ b/arch/arm/mach-imx/clk-fixup-mux.c @@ -71,12 +71,12 @@ static const struct clk_ops clk_fixup_mux_ops = { .set_parent = clk_fixup_mux_set_parent, }; -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)) { struct clk_fixup_mux *fixup_mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (!fixup) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 84acdfd..d78f409 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -108,14 +108,14 @@ static struct clk_ops clk_gate2_ops = { .is_enabled = clk_gate2_is_enabled, }; -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) { struct clk_gate2 *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 7f739be..94b7cfa 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -50,7 +50,7 @@ enum imx1_clks { usbd_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; int __init mx1_clocks_init(unsigned long fref) { diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index bdc2e46..1fc76c5 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -62,7 +62,7 @@ enum imx21_clks { gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; /* * must be called very early to get information about the diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index ae578c0..3772eb1 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -89,7 +89,7 @@ enum mx25_clks { wdt_ipg, cko_div, cko_sel, cko, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static int __init __mx25_clocks_init(unsigned long osc_rate) { @@ -229,10 +229,10 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) pr_err("i.MX25 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - clk_prepare_enable(clk[emi_ahb]); + clk_provider_prepare_enable(clk[emi_ahb]); /* Clock source for gpt must be derived from AHB */ - clk_set_parent(clk[per5_sel], clk[ahb]); + clk_provider_set_parent(clk[per5_sel], clk[ahb]); clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); @@ -241,7 +241,7 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) * Let's initially set up CLKO parent as ipg, since this configuration * is used on some imx25 board designs to clock the audio codec. */ - clk_set_parent(clk[cko_sel], clk[ipg]); + clk_provider_set_parent(clk[cko_sel], clk[ipg]); return 0; } diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 317a662..071fe2b 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -86,7 +86,7 @@ enum mx27_clks { rtic_ahb_gate, mshc_baud_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; int __init mx27_clocks_init(unsigned long fref) @@ -278,7 +278,7 @@ int __init mx27_clocks_init(unsigned long fref) mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); - clk_prepare_enable(clk[emi_ahb_gate]); + clk_provider_prepare_enable(clk[emi_ahb_gate]); imx_print_silicon_rev("i.MX27", mx27_revision()); diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index 4a9de08..3db06ac 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -45,7 +45,7 @@ enum mx31_clks { gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; int __init mx31_clocks_init(unsigned long fref) @@ -180,11 +180,11 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); clk_register_clkdev(clk[iim_gate], "iim", NULL); - clk_set_parent(clk[csi], clk[upll]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[iim_gate]); + clk_provider_set_parent(clk[csi], clk[upll]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[iim_gate]); mx31_revision(); - clk_disable_unprepare(clk[iim_gate]); + clk_provider_disable_unprepare(clk[iim_gate]); mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index 71c86a2..4433d08 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -67,7 +67,7 @@ enum mx35_clks { gpu2d_gate, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; int __init mx35_clocks_init(void) { @@ -100,7 +100,7 @@ int __init mx35_clocks_init(void) else clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); - if (clk_get_rate(clk[arm]) > 400000000) + if (clk_provider_get_rate(clk[arm]) > 400000000) hsp_div = hsp_div_532; else hsp_div = hsp_div_400; @@ -261,14 +261,14 @@ int __init mx35_clocks_init(void) clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); clk_register_clkdev(clk[admux_gate], "audmux", NULL); - clk_prepare_enable(clk[spba_gate]); - clk_prepare_enable(clk[gpio1_gate]); - clk_prepare_enable(clk[gpio2_gate]); - clk_prepare_enable(clk[gpio3_gate]); - clk_prepare_enable(clk[iim_gate]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[max_gate]); - clk_prepare_enable(clk[iomuxc_gate]); + clk_provider_prepare_enable(clk[spba_gate]); + clk_provider_prepare_enable(clk[gpio1_gate]); + clk_provider_prepare_enable(clk[gpio2_gate]); + clk_provider_prepare_enable(clk[gpio3_gate]); + clk_provider_prepare_enable(clk[iim_gate]); + clk_provider_prepare_enable(clk[emi_gate]); + clk_provider_prepare_enable(clk[max_gate]); + clk_provider_prepare_enable(clk[iomuxc_gate]); /* * SCC is needed to boot via mmc after a watchdog reset. The clock code @@ -276,7 +276,7 @@ int __init mx35_clocks_init(void) * handled here and not needed for mmc) and IIM (which is enabled * unconditionally above). */ - clk_prepare_enable(clk[scc_gate]); + clk_provider_prepare_enable(clk[scc_gate]); imx_print_silicon_rev("i.MX35", mx35_revision()); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 21d2b11..88894cd 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -83,7 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_ static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; -static struct clk *clk[IMX5_CLK_END]; +static struct clk_core *clk[IMX5_CLK_END]; static struct clk_onecell_data clk_data; static void __init mx5_clocks_common_init(unsigned long rate_ckil, @@ -298,26 +298,28 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1"); /* Set SDHC parents to be PLL2 */ - clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); - clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], + clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], + clk[IMX5_CLK_PLL2_SW]); /* move usb phy clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); - - clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); - clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); - clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_SPBA]); - clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ - clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); - clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); - clk_prepare_enable(clk[IMX5_CLK_TMAX1]); - clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ - clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ + clk_provider_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); + + clk_provider_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); + clk_provider_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); + clk_provider_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_SPBA]); + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX1]); + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ + clk_provider_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ } static void __init mx50_clocks_init(struct device_node *np) @@ -361,15 +363,15 @@ static void __init mx50_clocks_init(struct device_node *np) mx5_clocks_common_init(0, 0, 0, 0); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt")); } @@ -447,18 +449,19 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3"); /* set the usboh3 parent to pll2_sw */ - clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); + clk_provider_set_parent(clk[IMX5_CLK_USBOH3_SEL], + clk[IMX5_CLK_PLL2_SW]); /* set SDHC root clock to 166.25MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); /* System timer */ mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX51", mx51_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); /* * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no @@ -571,18 +574,18 @@ static void __init mx53_clocks_init(struct device_node *np) clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3"); /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); - clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); + clk_provider_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); /* move can bus clk to 24MHz */ - clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); + clk_provider_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); - clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); + clk_provider_prepare_enable(clk[IMX5_CLK_IIM_GATE]); imx_print_silicon_rev("i.MX53", mx53_revision()); - clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); + clk_provider_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); - r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); - clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); + r = clk_provider_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); + clk_provider_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt")); } diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 8556c78..59a001a 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -110,7 +110,7 @@ enum mx6q_clks { lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max }; -static struct clk *clk[clk_max]; +static struct clk_core *clk[clk_max]; static struct clk_onecell_data clk_data; static enum mx6q_clks const clks_init_on[] __initconst = { @@ -448,50 +448,50 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { - clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); - clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); } - clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); - clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); - clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); - clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); - clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); + clk_provider_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); + clk_provider_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); + clk_provider_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); + clk_provider_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); + clk_provider_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, * We can not get the 100MHz from the pll2_pfd0_352m. * So choose pll2_pfd2_396m as enfc_sel's parent. */ - clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); + clk_provider_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); + clk_provider_prepare_enable(clk[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clk[usbphy1_gate]); - clk_prepare_enable(clk[usbphy2_gate]); + clk_provider_prepare_enable(clk[usbphy1_gate]); + clk_provider_prepare_enable(clk[usbphy2_gate]); } /* * Let's initially set up CLKO with OSC24M, since this configuration * is widely used by imx6q board designs to clock audio codec. */ - ret = clk_set_parent(clk[cko2_sel], clk[osc]); + ret = clk_provider_set_parent(clk[cko2_sel], clk[osc]); if (!ret) - ret = clk_set_parent(clk[cko], clk[cko2]); + ret = clk_provider_set_parent(clk[cko], clk[cko2]); if (ret) pr_warn("failed to set up CLKO: %d\n", ret); /* Audio-related clocks configuration */ - clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); + clk_provider_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) - clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]); + clk_provider_set_parent(clk[lvds1_sel], clk[sata_ref_100m]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index 5408ca7..29e5d3c 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -79,7 +79,7 @@ static struct clk_div_table video_div_table[] = { { } }; -static struct clk *clks[IMX6SL_CLK_END]; +static struct clk_core *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; static void __iomem *ccm_base; static void __iomem *anatop_base; @@ -361,7 +361,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); /* Ensure the AHB clk is at 132MHz. */ - ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); + ret = clk_provider_set_rate(clks[IMX6SL_CLK_AHB], 132000000); if (ret) pr_warn("%s: failed to set AHB clock rate %d!\n", __func__, ret); @@ -371,15 +371,16 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) * usecount and enabling/disabling of parent PLLs. */ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); } /* Audio-related clocks configuration */ - clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + clk_provider_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], + clks[IMX6SL_CLK_PLL3_PFD3]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 72f8902..81ee7f6 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -82,7 +82,7 @@ static const char *lvds_sels[] = { "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", }; -static struct clk *clks[IMX6SX_CLK_CLK_END]; +static struct clk_core *clks[IMX6SX_CLK_CLK_END]; static struct clk_onecell_data clk_data; static int const clks_init_on[] __initconst = { @@ -133,12 +133,14 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); - clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); + clks[IMX6SX_CLK_CKIL] = of_clk_provider_get_by_name(ccm_node, "ckil"); + clks[IMX6SX_CLK_OSC] = of_clk_provider_get_by_name(ccm_node, "osc"); /* ipp_di clock is external input */ - clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); - clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); + clks[IMX6SX_CLK_IPP_DI0] = of_clk_provider_get_by_name(ccm_node, + "ipp_di0"); + clks[IMX6SX_CLK_IPP_DI1] = of_clk_provider_get_by_name(ccm_node, + "ipp_di1"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); base = of_iomap(np, 0); @@ -455,65 +457,80 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); + clk_provider_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); } /* Set the default 132MHz for EIM module */ - clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); + clk_provider_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); /* set parent clock for LCDIF1 pixel clock */ - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], + clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], + clks[IMX6SX_CLK_LCDIF1_PODF]); /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ - if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M])) pr_err("Failed to set pcie bus parent clk.\n"); - if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) + if (clk_provider_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI])) pr_err("Failed to set pcie parent clk.\n"); /* * Init enet system AHB clock, set to 200Mhz * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB */ - clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); - clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]); - clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); - clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); - clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], + clks[IMX6SX_CLK_PLL2_PFD2]); + clk_provider_set_parent(clks[IMX6SX_CLK_ENET_SEL], + clks[IMX6SX_CLK_ENET_PODF]); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); + clk_provider_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); /* Audio clocks */ - clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); - - clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); - - clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); - clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); - - clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); - clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); - - clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); + + clk_provider_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); + + clk_provider_set_parent(clks[IMX6SX_CLK_SSI1_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI2_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_parent(clks[IMX6SX_CLK_SSI3_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); + clk_provider_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); + + clk_provider_set_parent(clks[IMX6SX_CLK_ESAI_SEL], + clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_provider_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); /* Set parent clock for vadc */ - clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); + clk_provider_set_parent(clks[IMX6SX_CLK_VID_SEL], + clks[IMX6SX_CLK_PLL3_USB_OTG]); /* default parent of can_sel clock is invalid, manually set it here */ - clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); + clk_provider_set_parent(clks[IMX6SX_CLK_CAN_SEL], + clks[IMX6SX_CLK_PLL3_60M]); /* Update gpu clock from default 528M to 720M */ - clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); - clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); + clk_provider_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], + clks[IMX6SX_CLK_PLL3_PFD0]); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c index 0b0f6f6..8f7590a 100644 --- a/arch/arm/mach-imx/clk-pfd.c +++ b/arch/arm/mach-imx/clk-pfd.c @@ -128,11 +128,11 @@ static const struct clk_ops clk_pfd_ops = { .is_enabled = clk_pfd_is_enabled, }; -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_pfd *pfd; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index d21d14c..fbe33f3 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -97,11 +97,11 @@ static struct clk_ops clk_pllv1_ops = { .recalc_rate = clk_pllv1_recalc_rate, }; -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base) { struct clk_pllv1 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kmalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c index 20889d5..7882848 100644 --- a/arch/arm/mach-imx/clk-pllv2.c +++ b/arch/arm/mach-imx/clk-pllv2.c @@ -237,11 +237,11 @@ static struct clk_ops clk_pllv2_ops = { .set_rate = clk_pllv2_set_rate, }; -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base) { struct clk_pllv2 *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index 6136405..3edcfdc 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -320,13 +320,13 @@ static const struct clk_ops clk_pllv3_enet_ops = { .recalc_rate = clk_pllv3_enet_recalc_rate, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) { struct clk_pllv3 *pll; const struct clk_ops *ops; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index 22dc3ee..b383e96 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -95,7 +95,7 @@ static struct clk_div_table pll4_main_div_table[] = { { } }; -static struct clk *clk[VF610_CLK_END]; +static struct clk_core *clk[VF610_CLK_END]; static struct clk_onecell_data clk_data; static void __init vf610_clocks_init(struct device_node *ccm_node) @@ -303,20 +303,32 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); - clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_QSPI0_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_QSPI1_SEL], + clk[VF610_CLK_PLL1_PFD4]); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); + clk_provider_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], + clk_provider_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); + + clk_provider_set_parent(clk[VF610_CLK_SAI0_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI1_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI2_SEL], + clk[VF610_CLK_AUDIO_EXT]); + clk_provider_set_parent(clk[VF610_CLK_SAI3_SEL], + clk[VF610_CLK_AUDIO_EXT]); /* Add the clocks to provider list */ clk_data.clks = clk; diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index edc35df..d776fe1 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c @@ -7,10 +7,10 @@ DEFINE_SPINLOCK(imx_ccm_lock); -static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) +static struct clk_core * __init imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; - struct clk *clk = ERR_PTR(-ENODEV); + struct clk_core *clk = ERR_PTR(-ENODEV); char *path; path = kasprintf(GFP_KERNEL, "/clocks/%s", name); @@ -27,10 +27,10 @@ static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) return clk; } -struct clk * __init imx_obtain_fixed_clock( +struct clk_core * __init imx_obtain_fixed_clock( const char *name, unsigned long rate) { - struct clk *clk; + struct clk_core *clk; clk = imx_obtain_fixed_clock_from_dt(name); if (IS_ERR(clk)) diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index e29f6eb..421af46 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -8,10 +8,10 @@ extern spinlock_t imx_ccm_lock; extern void imx_cscmr1_fixup(u32 *val); -struct clk *imx_clk_pllv1(const char *name, const char *parent, +struct clk_core *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); -struct clk *imx_clk_pllv2(const char *name, const char *parent, +struct clk_core *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base); enum imx_pllv3_type { @@ -22,26 +22,26 @@ enum imx_pllv3_type { IMX_PLLV3_ENET, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, +struct clk_core *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk_core *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); -struct clk * imx_obtain_fixed_clock( +struct clk_core * imx_obtain_fixed_clock( const char *name, unsigned long rate); -static inline struct clk *imx_clk_gate2(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock, NULL); } -static inline struct clk *imx_clk_gate2_shared(const char *name, +static inline struct clk_core *imx_clk_gate2_shared(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) { @@ -49,38 +49,38 @@ static inline struct clk *imx_clk_gate2_shared(const char *name, shift, 0, &imx_ccm_lock, share_count); } -struct clk *imx_clk_pfd(const char *name, const char *parent_name, +struct clk_core *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, +struct clk_core *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift); -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, +struct clk_core *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents); -struct clk *imx_clk_fixup_divider(const char *name, const char *parent, +struct clk_core *imx_clk_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)); -struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, +struct clk_core *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, void (*fixup)(u32 *val)); -static inline struct clk *imx_clk_fixed(const char *name, int rate) +static inline struct clk_core *imx_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *imx_clk_divider(const char *name, const char *parent, +static inline struct clk_core *imx_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_divider_flags(const char *name, +static inline struct clk_core *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) { @@ -88,14 +88,14 @@ static inline struct clk *imx_clk_divider_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_gate(const char *name, const char *parent, +static inline struct clk_core *imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { return clk_register_mux(NULL, name, parents, num_parents, @@ -103,7 +103,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, width, 0, &imx_ccm_lock); } -static inline struct clk *imx_clk_mux_flags(const char *name, +static inline struct clk_core *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, unsigned long flags) { @@ -112,7 +112,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } -static inline struct clk *imx_clk_fixed_factor(const char *name, +static inline struct clk_core *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent, diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 255f33a..b87a92e 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -159,7 +159,7 @@ static void clk_gate_fn_disable(struct clk_hw *hw) static struct clk_ops clk_gate_fn_ops; -static struct clk __init *clk_register_gate_fn(struct device *dev, +static struct clk_core __init *clk_register_gate_fn(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, @@ -167,7 +167,7 @@ static struct clk __init *clk_register_gate_fn(struct device *dev, void (*fn_en)(void), void (*fn_dis)(void)) { struct clk_gate_fn *gate_fn; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL); @@ -208,15 +208,15 @@ static struct clk __init *clk_register_gate_fn(struct device *dev, } static DEFINE_SPINLOCK(gating_lock); -static struct clk *tclk; +static struct clk_core *tclk; -static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) +static struct clk_core __init *kirkwood_register_gate(const char *name, u8 bit_idx) { return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, bit_idx, 0, &gating_lock); } -static struct clk __init *kirkwood_register_gate_fn(const char *name, +static struct clk_core __init *kirkwood_register_gate_fn(const char *name, u8 bit_idx, void (*fn_en)(void), void (*fn_dis)(void)) @@ -225,12 +225,12 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name, bit_idx, 0, &gating_lock, fn_en, fn_dis); } -static struct clk *ge0, *ge1; +static struct clk_core *ge0, *ge1; void __init kirkwood_clk_init(void) { - struct clk *runit, *sata0, *sata1, *usb0, *sdio; - struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio; + struct clk_core *runit, *sata0, *sata1, *usb0, *sdio; + struct clk_core *crypto, *xor0, *xor1, *pex0, *pex1, *audio; tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, kirkwood_tclk); @@ -278,7 +278,7 @@ void __init kirkwood_clk_init(void) /* Marvell says runit is used by SPI, UART, NAND, TWSI, ..., * so should never be gated. */ - clk_prepare_enable(runit); + clk_provider_prepare_enable(runit); } /***************************************************************************** @@ -300,7 +300,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) IRQ_KIRKWOOD_GE00_ERR, 1600); /* The interface forgets the MAC address assigned by u-boot if the clock is turned off, so claim the clk now. */ - clk_prepare_enable(ge0); + clk_provider_prepare_enable(ge0); } @@ -312,7 +312,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, IRQ_KIRKWOOD_GE01_ERR, 1600); - clk_prepare_enable(ge1); + clk_provider_prepare_enable(ge1); } diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index 9a80449..14352c4 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -132,7 +132,7 @@ static int msm_clock_pcom_probe(struct platform_device *pdev) for (i = 0; i < pdata->num_lookups; i++) { const struct clk_pcom_desc *desc = &pdata->lookup[i]; - struct clk *c; + struct clk_core *c; struct clk_pcom *p; struct clk_hw *hw; struct clk_init_data init; diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index e6ac679..fee2643 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -164,7 +164,7 @@ void __init mv78xx0_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; static void __init clk_init(void) { diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 3662f4d..59d6323 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -57,7 +57,7 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +static struct clk_core osc_ck; static const struct clk_ops osc_ck_ops = { .recalc_rate = &omap2_osc_clk_recalc, @@ -69,7 +69,7 @@ static struct clk_hw_omap osc_ck_hw = { }, }; -static struct clk osc_ck = { +static struct clk_core osc_ck = { .name = "osc_ck", .ops = &osc_ck_ops, .hw = &osc_ck_hw.hw, @@ -78,7 +78,7 @@ static struct clk osc_ck = { DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +static struct clk_core sys_ck; static const char *sys_ck_parent_names[] = { "osc_ck", @@ -105,7 +105,7 @@ static struct dpll_data dpll_dd = { .max_divider = 16, }; -static struct clk dpll_ck; +static struct clk_core dpll_ck; static const char *dpll_ck_parent_names[] = { "sys_ck", @@ -130,7 +130,7 @@ static struct clk_hw_omap dpll_ck_hw = { DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll_ck", @@ -153,7 +153,7 @@ DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk aes_ick; +static struct clk_core aes_ick; static const char *aes_ick_parent_names[] = { "l4_ck", @@ -178,7 +178,7 @@ static struct clk_hw_omap aes_ick_hw = { DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk apll54_ck; +static struct clk_core apll54_ck; static const struct clk_ops apll54_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -200,7 +200,7 @@ static struct clk_hw_omap apll54_ck_hw = { DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); -static struct clk apll96_ck; +static struct clk_core apll96_ck; static const struct clk_ops apll96_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -222,7 +222,7 @@ static struct clk_hw_omap apll96_ck_hw = { DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); -static struct clk func_96m_ck; +static struct clk_core func_96m_ck; static const char *func_96m_ck_parent_names[] = { "apll96_ck", @@ -231,7 +231,7 @@ static const char *func_96m_ck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); -static struct clk cam_fck; +static struct clk_core cam_fck; static const char *cam_fck_parent_names[] = { "func_96m_ck", @@ -248,7 +248,7 @@ static struct clk_hw_omap cam_fck_hw = { DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -262,7 +262,7 @@ static struct clk_hw_omap cam_ick_hw = { DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk des_ick; +static struct clk_core des_ick; static struct clk_hw_omap des_ick_hw = { .hw = { @@ -358,7 +358,7 @@ static const char *dss1_fck_parent_names[] = { "sys_ck", "core_ck", }; -static struct clk dss1_fck; +static struct clk_core dss1_fck; static const struct clk_ops dss1_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -407,7 +407,7 @@ static const char *func_48m_ck_parent_names[] = { "apll96_ck", "alt_ck", }; -static struct clk func_48m_ck; +static struct clk_core func_48m_ck; static const struct clk_ops func_48m_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -456,7 +456,7 @@ DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); -static struct clk dss_54m_fck; +static struct clk_core dss_54m_fck; static const char *dss_54m_fck_parent_names[] = { "func_54m_ck", @@ -474,7 +474,7 @@ static struct clk_hw_omap dss_54m_fck_hw = { DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); -static struct clk dss_ick; +static struct clk_core dss_ick; static struct clk_hw_omap dss_ick_hw = { .hw = { @@ -488,7 +488,7 @@ static struct clk_hw_omap dss_ick_hw = { DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk eac_fck; +static struct clk_core eac_fck; static struct clk_hw_omap eac_fck_hw = { .hw = { @@ -502,7 +502,7 @@ static struct clk_hw_omap eac_fck_hw = { DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk eac_ick; +static struct clk_core eac_ick; static struct clk_hw_omap eac_ick_hw = { .hw = { @@ -516,7 +516,7 @@ static struct clk_hw_omap eac_ick_hw = { DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk emul_ck; +static struct clk_core emul_ck; static struct clk_hw_omap emul_ck_hw = { .hw = { @@ -531,7 +531,7 @@ DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); -static struct clk fac_fck; +static struct clk_core fac_fck; static const char *fac_fck_parent_names[] = { "func_12m_ck", @@ -549,7 +549,7 @@ static struct clk_hw_omap fac_fck_hw = { DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -586,7 +586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, gfx_2d_fck_parent_names, dsp_fck_ops); -static struct clk gfx_ick; +static struct clk_core gfx_ick; static const char *gfx_ick_parent_names[] = { "core_l3_ck", @@ -604,7 +604,7 @@ static struct clk_hw_omap gfx_ick_hw = { DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk gpios_fck; +static struct clk_core gpios_fck; static const char *gpios_fck_parent_names[] = { "func_32k_ck", @@ -622,7 +622,7 @@ static struct clk_hw_omap gpios_fck_hw = { DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk gpios_ick; +static struct clk_core gpios_ick; static const char *gpios_ick_parent_names[] = { "sys_ck", @@ -640,7 +640,7 @@ static struct clk_hw_omap gpios_ick_hw = { DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -678,7 +678,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -699,7 +699,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -720,7 +720,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -753,7 +753,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, gpt1_fck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -774,7 +774,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -795,7 +795,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -816,7 +816,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -837,7 +837,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -858,7 +858,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -879,7 +879,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -900,7 +900,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -921,7 +921,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -935,7 +935,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static struct clk_hw_omap hdq_fck_hw = { .hw = { @@ -949,7 +949,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -963,7 +963,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c1_fck; +static struct clk_core i2c1_fck; static struct clk_hw_omap i2c1_fck_hw = { .hw = { @@ -977,7 +977,7 @@ static struct clk_hw_omap i2c1_fck_hw = { DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -991,7 +991,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c2_fck; +static struct clk_core i2c2_fck; static struct clk_hw_omap i2c2_fck_hw = { .hw = { @@ -1005,7 +1005,7 @@ static struct clk_hw_omap i2c2_fck_hw = { DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -1026,7 +1026,7 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, dsp_fck_parent_names, dsp_fck_ops); -static struct clk iva1_mpu_int_ifck; +static struct clk_core iva1_mpu_int_ifck; static const char *iva1_mpu_int_ifck_parent_names[] = { "iva1_ifck", @@ -1054,7 +1054,7 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = { DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, iva1_mpu_int_ifck_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -1095,7 +1095,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -1116,7 +1116,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -1130,7 +1130,7 @@ static struct clk_hw_omap mcbsp2_ick_hw = { DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static const char *mcspi1_fck_parent_names[] = { "func_48m_ck", @@ -1148,7 +1148,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -1162,7 +1162,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -1176,7 +1176,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -1190,7 +1190,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mmc_fck; +static struct clk_core mmc_fck; static struct clk_hw_omap mmc_fck_hw = { .hw = { @@ -1204,7 +1204,7 @@ static struct clk_hw_omap mmc_fck_hw = { DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mmc_ick; +static struct clk_core mmc_ick; static struct clk_hw_omap mmc_ick_hw = { .hw = { @@ -1223,7 +1223,7 @@ DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_wdt_fck; +static struct clk_core mpu_wdt_fck; static struct clk_hw_omap mpu_wdt_fck_hw = { .hw = { @@ -1237,7 +1237,7 @@ static struct clk_hw_omap mpu_wdt_fck_hw = { DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk mpu_wdt_ick; +static struct clk_core mpu_wdt_ick; static struct clk_hw_omap mpu_wdt_ick_hw = { .hw = { @@ -1251,7 +1251,7 @@ static struct clk_hw_omap mpu_wdt_ick_hw = { DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -1265,7 +1265,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -1279,7 +1279,7 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -1294,7 +1294,7 @@ static struct clk_hw_omap omapctrl_ick_hw = { DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static struct clk_hw_omap pka_ick_hw = { .hw = { @@ -1308,7 +1308,7 @@ static struct clk_hw_omap pka_ick_hw = { DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -1322,12 +1322,12 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk sdma_fck; +static struct clk_core sdma_fck; DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); -static struct clk sdma_ick; +static struct clk_core sdma_ick; static struct clk_hw_omap sdma_ick_hw = { .hw = { @@ -1341,7 +1341,7 @@ static struct clk_hw_omap sdma_ick_hw = { DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -1356,7 +1356,7 @@ static struct clk_hw_omap sdrc_ick_hw = { DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sha_ick; +static struct clk_core sha_ick; static struct clk_hw_omap sha_ick_hw = { .hw = { @@ -1370,7 +1370,7 @@ static struct clk_hw_omap sha_ick_hw = { DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; static struct clk_hw_omap ssi_l4_ick_hw = { .hw = { @@ -1411,7 +1411,7 @@ DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, ssi_ssr_sst_fck_parent_names, dsp_fck_ops); -static struct clk sync_32k_ick; +static struct clk_core sync_32k_ick; static struct clk_hw_omap sync_32k_ick_hw = { .hw = { @@ -1477,7 +1477,7 @@ DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -1491,7 +1491,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -1505,7 +1505,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -1519,7 +1519,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -1533,7 +1533,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static struct clk_hw_omap uart3_fck_hw = { .hw = { @@ -1547,7 +1547,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -1561,7 +1561,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk usb_fck; +static struct clk_core usb_fck; static struct clk_hw_omap usb_fck_hw = { .hw = { @@ -1598,7 +1598,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, usb_l4_ick_parent_names, dsp_fck_ops); -static struct clk virt_prcm_set; +static struct clk_core virt_prcm_set; static const char *virt_prcm_set_parent_names[] = { "mpu_ck", @@ -1649,7 +1649,7 @@ DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, vlynq_fck_parent_names, dss1_fck_ops); -static struct clk vlynq_ick; +static struct clk_core vlynq_ick; static struct clk_hw_omap vlynq_ick_hw = { .hw = { @@ -1663,7 +1663,7 @@ static struct clk_hw_omap vlynq_ick_hw = { DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -1677,7 +1677,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk wdt3_fck; +static struct clk_core wdt3_fck; static struct clk_hw_omap wdt3_fck_hw = { .hw = { @@ -1691,7 +1691,7 @@ static struct clk_hw_omap wdt3_fck_hw = { DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk wdt3_ick; +static struct clk_core wdt3_ick; static struct clk_hw_omap wdt3_ick_hw = { .hw = { @@ -1705,7 +1705,7 @@ static struct clk_hw_omap wdt3_ick_hw = { DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk wdt4_fck; +static struct clk_core wdt4_fck; static struct clk_hw_omap wdt4_fck_hw = { .hw = { @@ -1719,7 +1719,7 @@ static struct clk_hw_omap wdt4_fck_hw = { DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk wdt4_ick; +static struct clk_core wdt4_ick; static struct clk_hw_omap wdt4_ick_hw = { .hw = { @@ -1922,10 +1922,10 @@ int __init omap2420_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); + (clk_provider_get_rate(&sys_ck) / 1000000), + (clk_provider_get_rate(&sys_ck) / 100000) % 10, + (clk_provider_get_rate(&dpll_ck) / 1000000), + (clk_provider_get_rate(&mpu_ck) / 1000000)); return 0; } diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index 5e4b037..19d0361 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -55,7 +55,7 @@ DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); -static struct clk osc_ck; +static struct clk_core osc_ck; static const struct clk_ops osc_ck_ops = { .enable = &omap2_enable_osc_ck, @@ -69,7 +69,7 @@ static struct clk_hw_omap osc_ck_hw = { }, }; -static struct clk osc_ck = { +static struct clk_core osc_ck = { .name = "osc_ck", .ops = &osc_ck_ops, .hw = &osc_ck_hw.hw, @@ -78,7 +78,7 @@ static struct clk osc_ck = { DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); -static struct clk sys_ck; +static struct clk_core sys_ck; static const char *sys_ck_parent_names[] = { "osc_ck", @@ -105,7 +105,7 @@ static struct dpll_data dpll_dd = { .max_divider = 16, }; -static struct clk dpll_ck; +static struct clk_core dpll_ck; static const char *dpll_ck_parent_names[] = { "sys_ck", @@ -130,7 +130,7 @@ static struct clk_hw_omap dpll_ck_hw = { DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll_ck", @@ -153,7 +153,7 @@ DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk aes_ick; +static struct clk_core aes_ick; static const char *aes_ick_parent_names[] = { "l4_ck", @@ -178,7 +178,7 @@ static struct clk_hw_omap aes_ick_hw = { DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk apll54_ck; +static struct clk_core apll54_ck; static const struct clk_ops apll54_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -200,7 +200,7 @@ static struct clk_hw_omap apll54_ck_hw = { DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); -static struct clk apll96_ck; +static struct clk_core apll96_ck; static const struct clk_ops apll96_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -230,7 +230,7 @@ DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); -static struct clk cam_fck; +static struct clk_core cam_fck; static const char *cam_fck_parent_names[] = { "func_96m_ck", @@ -247,7 +247,7 @@ static struct clk_hw_omap cam_fck_hw = { DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -261,7 +261,7 @@ static struct clk_hw_omap cam_ick_hw = { DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk des_ick; +static struct clk_core des_ick; static struct clk_hw_omap des_ick_hw = { .hw = { @@ -292,7 +292,7 @@ static const char *dsp_fck_parent_names[] = { "core_ck", }; -static struct clk dsp_fck; +static struct clk_core dsp_fck; static const struct clk_ops dsp_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -387,7 +387,7 @@ static const char *func_48m_ck_parent_names[] = { "apll96_ck", "alt_ck", }; -static struct clk func_48m_ck; +static struct clk_core func_48m_ck; static const struct clk_ops func_48m_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -435,7 +435,7 @@ DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); -static struct clk dss_54m_fck; +static struct clk_core dss_54m_fck; static const char *dss_54m_fck_parent_names[] = { "func_54m_ck", @@ -453,7 +453,7 @@ static struct clk_hw_omap dss_54m_fck_hw = { DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); -static struct clk dss_ick; +static struct clk_core dss_ick; static struct clk_hw_omap dss_ick_hw = { .hw = { @@ -467,7 +467,7 @@ static struct clk_hw_omap dss_ick_hw = { DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk emul_ck; +static struct clk_core emul_ck; static struct clk_hw_omap emul_ck_hw = { .hw = { @@ -482,7 +482,7 @@ DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); -static struct clk fac_fck; +static struct clk_core fac_fck; static const char *fac_fck_parent_names[] = { "func_12m_ck", @@ -500,7 +500,7 @@ static struct clk_hw_omap fac_fck_hw = { DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -537,7 +537,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, gfx_2d_fck_parent_names, dsp_fck_ops); -static struct clk gfx_ick; +static struct clk_core gfx_ick; static const char *gfx_ick_parent_names[] = { "core_l3_ck", @@ -555,7 +555,7 @@ static struct clk_hw_omap gfx_ick_hw = { DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk gpio5_fck; +static struct clk_core gpio5_fck; static const char *gpio5_fck_parent_names[] = { "func_32k_ck", @@ -573,7 +573,7 @@ static struct clk_hw_omap gpio5_fck_hw = { DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk gpio5_ick; +static struct clk_core gpio5_ick; static struct clk_hw_omap gpio5_ick_hw = { .hw = { @@ -587,7 +587,7 @@ static struct clk_hw_omap gpio5_ick_hw = { DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk gpios_fck; +static struct clk_core gpios_fck; static struct clk_hw_omap gpios_fck_hw = { .hw = { @@ -601,7 +601,7 @@ static struct clk_hw_omap gpios_fck_hw = { DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk gpios_ick; +static struct clk_core gpios_ick; static const char *gpios_ick_parent_names[] = { "sys_ck", @@ -619,7 +619,7 @@ static struct clk_hw_omap gpios_ick_hw = { DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -657,7 +657,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -678,7 +678,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -699,7 +699,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -732,7 +732,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, gpt1_fck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -753,7 +753,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -774,7 +774,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -795,7 +795,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -816,7 +816,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -837,7 +837,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -858,7 +858,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -872,7 +872,7 @@ static struct clk_hw_omap gpt7_ick_hw = { DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk gpt8_fck; +static struct clk_core gpt8_fck; DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), @@ -881,7 +881,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -902,7 +902,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, dss1_fck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -916,7 +916,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static struct clk_hw_omap hdq_fck_hw = { .hw = { @@ -930,7 +930,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -944,7 +944,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -958,7 +958,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -972,7 +972,7 @@ static struct clk_hw_omap i2c2_ick_hw = { DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk i2chs1_fck; +static struct clk_core i2chs1_fck; static struct clk_hw_omap i2chs1_fck_hw = { .hw = { @@ -986,7 +986,7 @@ static struct clk_hw_omap i2chs1_fck_hw = { DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk i2chs2_fck; +static struct clk_core i2chs2_fck; static struct clk_hw_omap i2chs2_fck_hw = { .hw = { @@ -1000,7 +1000,7 @@ static struct clk_hw_omap i2chs2_fck_hw = { DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk icr_ick; +static struct clk_core icr_ick; static struct clk_hw_omap icr_ick_hw = { .hw = { @@ -1030,7 +1030,7 @@ DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, iva2_1_ick_parent_names, dsp_fck_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -1071,7 +1071,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -1092,7 +1092,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -1113,7 +1113,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp3_ick; +static struct clk_core mcbsp3_ick; static struct clk_hw_omap mcbsp3_ick_hw = { .hw = { @@ -1134,7 +1134,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp4_ick; +static struct clk_core mcbsp4_ick; static struct clk_hw_omap mcbsp4_ick_hw = { .hw = { @@ -1155,7 +1155,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, dss1_fck_ops); -static struct clk mcbsp5_ick; +static struct clk_core mcbsp5_ick; static struct clk_hw_omap mcbsp5_ick_hw = { .hw = { @@ -1169,7 +1169,7 @@ static struct clk_hw_omap mcbsp5_ick_hw = { DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static const char *mcspi1_fck_parent_names[] = { "func_48m_ck", @@ -1187,7 +1187,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -1201,7 +1201,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -1215,7 +1215,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -1229,7 +1229,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mcspi3_fck; +static struct clk_core mcspi3_fck; static struct clk_hw_omap mcspi3_fck_hw = { .hw = { @@ -1243,7 +1243,7 @@ static struct clk_hw_omap mcspi3_fck_hw = { DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk mcspi3_ick; +static struct clk_core mcspi3_ick; static struct clk_hw_omap mcspi3_ick_hw = { .hw = { @@ -1282,7 +1282,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, &clkhwops_iclk_wait, mdm_ick_parent_names, dsp_fck_ops); -static struct clk mdm_intc_ick; +static struct clk_core mdm_intc_ick; static struct clk_hw_omap mdm_intc_ick_hw = { .hw = { @@ -1296,7 +1296,7 @@ static struct clk_hw_omap mdm_intc_ick_hw = { DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mdm_osc_ck; +static struct clk_core mdm_osc_ck; static struct clk_hw_omap mdm_osc_ck_hw = { .hw = { @@ -1310,7 +1310,7 @@ static struct clk_hw_omap mdm_osc_ck_hw = { DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); -static struct clk mmchs1_fck; +static struct clk_core mmchs1_fck; static struct clk_hw_omap mmchs1_fck_hw = { .hw = { @@ -1324,7 +1324,7 @@ static struct clk_hw_omap mmchs1_fck_hw = { DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mmchs1_ick; +static struct clk_core mmchs1_ick; static struct clk_hw_omap mmchs1_ick_hw = { .hw = { @@ -1338,7 +1338,7 @@ static struct clk_hw_omap mmchs1_ick_hw = { DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mmchs2_fck; +static struct clk_core mmchs2_fck; static struct clk_hw_omap mmchs2_fck_hw = { .hw = { @@ -1352,7 +1352,7 @@ static struct clk_hw_omap mmchs2_fck_hw = { DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mmchs2_ick; +static struct clk_core mmchs2_ick; static struct clk_hw_omap mmchs2_ick_hw = { .hw = { @@ -1366,7 +1366,7 @@ static struct clk_hw_omap mmchs2_ick_hw = { DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk mmchsdb1_fck; +static struct clk_core mmchsdb1_fck; static struct clk_hw_omap mmchsdb1_fck_hw = { .hw = { @@ -1380,7 +1380,7 @@ static struct clk_hw_omap mmchsdb1_fck_hw = { DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk mmchsdb2_fck; +static struct clk_core mmchsdb2_fck; static struct clk_hw_omap mmchsdb2_fck_hw = { .hw = { @@ -1399,7 +1399,7 @@ DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_wdt_fck; +static struct clk_core mpu_wdt_fck; static struct clk_hw_omap mpu_wdt_fck_hw = { .hw = { @@ -1413,7 +1413,7 @@ static struct clk_hw_omap mpu_wdt_fck_hw = { DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk mpu_wdt_ick; +static struct clk_core mpu_wdt_ick; static struct clk_hw_omap mpu_wdt_ick_hw = { .hw = { @@ -1427,7 +1427,7 @@ static struct clk_hw_omap mpu_wdt_ick_hw = { DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -1441,7 +1441,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -1455,7 +1455,7 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -1470,7 +1470,7 @@ static struct clk_hw_omap omapctrl_ick_hw = { DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static struct clk_hw_omap pka_ick_hw = { .hw = { @@ -1484,7 +1484,7 @@ static struct clk_hw_omap pka_ick_hw = { DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -1498,12 +1498,12 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk sdma_fck; +static struct clk_core sdma_fck; DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); -static struct clk sdma_ick; +static struct clk_core sdma_ick; static struct clk_hw_omap sdma_ick_hw = { .hw = { @@ -1517,7 +1517,7 @@ static struct clk_hw_omap sdma_ick_hw = { DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -1532,7 +1532,7 @@ static struct clk_hw_omap sdrc_ick_hw = { DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); -static struct clk sha_ick; +static struct clk_core sha_ick; static struct clk_hw_omap sha_ick_hw = { .hw = { @@ -1546,7 +1546,7 @@ static struct clk_hw_omap sha_ick_hw = { DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; static struct clk_hw_omap ssi_l4_ick_hw = { .hw = { @@ -1586,7 +1586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, ssi_ssr_sst_fck_parent_names, dsp_fck_ops); -static struct clk sync_32k_ick; +static struct clk_core sync_32k_ick; static struct clk_hw_omap sync_32k_ick_hw = { .hw = { @@ -1642,7 +1642,7 @@ DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -1656,7 +1656,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -1670,7 +1670,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -1684,7 +1684,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -1698,7 +1698,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static struct clk_hw_omap uart3_fck_hw = { .hw = { @@ -1712,7 +1712,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -1726,7 +1726,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); -static struct clk usb_fck; +static struct clk_core usb_fck; static struct clk_hw_omap usb_fck_hw = { .hw = { @@ -1763,7 +1763,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, usb_l4_ick_parent_names, dsp_fck_ops); -static struct clk usbhs_ick; +static struct clk_core usbhs_ick; static struct clk_hw_omap usbhs_ick_hw = { .hw = { @@ -1777,7 +1777,7 @@ static struct clk_hw_omap usbhs_ick_hw = { DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); -static struct clk virt_prcm_set; +static struct clk_core virt_prcm_set; static const char *virt_prcm_set_parent_names[] = { "mpu_ck", @@ -1792,7 +1792,7 @@ static const struct clk_ops virt_prcm_set_ops = { DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -1806,7 +1806,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk wdt4_fck; +static struct clk_core wdt4_fck; static struct clk_hw_omap wdt4_fck_hw = { .hw = { @@ -1820,7 +1820,7 @@ static struct clk_hw_omap wdt4_fck_hw = { DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk wdt4_ick; +static struct clk_core wdt4_ick; static struct clk_hw_omap wdt4_ick_hw = { .hw = { @@ -2039,10 +2039,10 @@ int __init omap2430_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); + (clk_provider_get_rate(&sys_ck) / 1000000), + (clk_provider_get_rate(&sys_ck) / 100000) % 10, + (clk_provider_get_rate(&dpll_ck) / 1000000), + (clk_provider_get_rate(&mpu_ck) / 1000000)); return 0; } diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index eb8c75e..b593f2b 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -107,7 +107,7 @@ static struct dpll_data dpll3_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll3_ck; +static struct clk_core dpll3_ck; static const char *dpll3_ck_parent_names[] = { "sys_ck", @@ -137,7 +137,7 @@ DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk core_ck; +static struct clk_core core_ck; static const char *core_ck_parent_names[] = { "dpll3_m2_ck", @@ -158,7 +158,7 @@ DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0, OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk security_l4_ick2; +static struct clk_core security_l4_ick2; static const char *security_l4_ick2_parent_names[] = { "l4_ick", @@ -167,7 +167,7 @@ static const char *security_l4_ick2_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL); DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops); -static struct clk aes1_ick; +static struct clk_core aes1_ick; static const char *aes1_ick_parent_names[] = { "security_l4_ick2", @@ -190,7 +190,7 @@ static struct clk_hw_omap aes1_ick_hw = { DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk core_l4_ick; +static struct clk_core core_l4_ick; static const struct clk_ops core_l4_ick_ops = { .init = &omap2_init_clk_clkdm, @@ -199,7 +199,7 @@ static const struct clk_ops core_l4_ick_ops = { DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk aes2_ick; +static struct clk_core aes2_ick; static const char *aes2_ick_parent_names[] = { "core_l4_ick", @@ -224,7 +224,7 @@ static struct clk_hw_omap aes2_ick_hw = { DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk dpll1_fck; +static struct clk_core dpll1_fck; static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -248,7 +248,7 @@ static struct dpll_data dpll1_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll1_ck; +static struct clk_core dpll1_ck; static const struct clk_ops dpll1_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -279,7 +279,7 @@ DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0, OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk mpu_ck; +static struct clk_core mpu_ck; static const char *mpu_ck_parent_names[] = { "dpll1_x2m2_ck", @@ -293,7 +293,7 @@ DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0, OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH, 0x0, NULL); -static struct clk cam_ick; +static struct clk_core cam_ick; static struct clk_hw_omap cam_ick_hw = { .hw = { @@ -358,7 +358,7 @@ static struct dpll_data dpll4_dd_3630 __initdata = { .flags = DPLL_J_TYPE }; -static struct clk dpll4_ck; +static struct clk_core dpll4_ck; static const struct clk_ops dpll4_ck_ops = { .init = &omap2_init_clk_clkdm, @@ -422,7 +422,7 @@ DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m5x2_ck; +static struct clk_core dpll4_m5x2_ck; static const char *dpll4_m5x2_ck_parent_names[] = { "dpll4_m5_ck", @@ -459,7 +459,7 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m5x2_ck_3630 = { +static struct clk_core dpll4_m5x2_ck_3630 = { .name = "dpll4_m5x2_ck", .hw = &dpll4_m5x2_ck_hw.hw, .parent_names = dpll4_m5x2_ck_parent_names, @@ -468,7 +468,7 @@ static struct clk dpll4_m5x2_ck_3630 = { .flags = CLK_SET_RATE_PARENT, }; -static struct clk cam_mclk; +static struct clk_core cam_mclk; static const char *cam_mclk_parent_names[] = { "dpll4_m5x2_ck", @@ -483,7 +483,7 @@ static struct clk_hw_omap cam_mclk_hw = { .clkdm_name = "cam_clkdm", }; -static struct clk cam_mclk = { +static struct clk_core cam_mclk = { .name = "cam_mclk", .hw = &cam_mclk_hw.hw, .parent_names = cam_mclk_parent_names, @@ -512,7 +512,7 @@ DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m2x2_ck; +static struct clk_core dpll4_m2x2_ck; static const char *dpll4_m2x2_ck_parent_names[] = { "dpll4_m2_ck", @@ -531,7 +531,7 @@ static struct clk_hw_omap dpll4_m2x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m2x2_ck_3630 = { +static struct clk_core dpll4_m2x2_ck_3630 = { .name = "dpll4_m2x2_ck", .hw = &dpll4_m2x2_ck_hw.hw, .parent_names = dpll4_m2x2_ck_parent_names, @@ -539,7 +539,7 @@ static struct clk dpll4_m2x2_ck_3630 = { .ops = &dpll4_m5x2_ck_3630_ops, }; -static struct clk omap_96m_alwon_fck; +static struct clk_core omap_96m_alwon_fck; static const char *omap_96m_alwon_fck_parent_names[] = { "dpll4_m2x2_ck", @@ -549,7 +549,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk cm_96m_fck; +static struct clk_core cm_96m_fck; static const char *cm_96m_fck_parent_names[] = { "omap_96m_alwon_fck", @@ -568,7 +568,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m3x2_ck; +static struct clk_core dpll4_m3x2_ck; static const char *dpll4_m3x2_ck_parent_names[] = { "dpll4_m3_ck", @@ -587,7 +587,7 @@ static struct clk_hw_omap dpll4_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m3x2_ck_3630 = { +static struct clk_core dpll4_m3x2_ck_3630 = { .name = "dpll4_m3x2_ck", .hw = &dpll4_m3x2_ck_hw.hw, .parent_names = dpll4_m3x2_ck_parent_names, @@ -651,7 +651,7 @@ static const char *omap_48m_fck_parent_names[] = { "cm_96m_fck", "sys_altclk", }; -static struct clk omap_48m_fck; +static struct clk_core omap_48m_fck; static const struct clk_ops omap_48m_fck_ops = { .recalc_rate = &omap2_clksel_recalc, @@ -672,7 +672,7 @@ DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops); DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4); -static struct clk core_12m_fck; +static struct clk_core core_12m_fck; static const char *core_12m_fck_parent_names[] = { "omap_12m_fck", @@ -681,7 +681,7 @@ static const char *core_12m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops); -static struct clk core_48m_fck; +static struct clk_core core_48m_fck; static const char *core_48m_fck_parent_names[] = { "omap_48m_fck", @@ -698,7 +698,7 @@ DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0, OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL); -static struct clk core_96m_fck; +static struct clk_core core_96m_fck; static const char *core_96m_fck_parent_names[] = { "omap_96m_fck", @@ -707,7 +707,7 @@ static const char *core_96m_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm"); DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops); -static struct clk core_l3_ick; +static struct clk_core core_l3_ick; static const char *core_l3_ick_parent_names[] = { "l3_ick", @@ -718,7 +718,7 @@ DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops); DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1); -static struct clk corex2_fck; +static struct clk_core corex2_fck; static const char *corex2_fck_parent_names[] = { "dpll3_m2x2_ck", @@ -727,7 +727,7 @@ static const char *corex2_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL); DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops); -static struct clk cpefuse_fck; +static struct clk_core cpefuse_fck; static struct clk_hw_omap cpefuse_fck_hw = { .hw = { @@ -740,7 +740,7 @@ static struct clk_hw_omap cpefuse_fck_hw = { DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk csi2_96m_fck; +static struct clk_core csi2_96m_fck; static const char *csi2_96m_fck_parent_names[] = { "core_96m_fck", @@ -757,7 +757,7 @@ static struct clk_hw_omap csi2_96m_fck_hw = { DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk d2d_26m_fck; +static struct clk_core d2d_26m_fck; static struct clk_hw_omap d2d_26m_fck_hw = { .hw = { @@ -771,7 +771,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = { DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk des1_ick; +static struct clk_core des1_ick; static struct clk_hw_omap des1_ick_hw = { .hw = { @@ -784,7 +784,7 @@ static struct clk_hw_omap des1_ick_hw = { DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk des2_ick; +static struct clk_core des2_ick; static struct clk_hw_omap des2_ick_hw = { .hw = { @@ -803,7 +803,7 @@ DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0, OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll2_fck; +static struct clk_core dpll2_fck; static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), @@ -828,7 +828,7 @@ static struct dpll_data dpll2_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll2_ck; +static struct clk_core dpll2_ck; static struct clk_hw_omap dpll2_ck_hw = { .hw = { @@ -857,7 +857,7 @@ DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0, OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll3_m3x2_ck; +static struct clk_core dpll3_m3x2_ck; static const char *dpll3_m3x2_ck_parent_names[] = { "dpll3_m3_ck", @@ -876,7 +876,7 @@ static struct clk_hw_omap dpll3_m3x2_ck_hw = { DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll3_m3x2_ck_3630 = { +static struct clk_core dpll3_m3x2_ck_3630 = { .name = "dpll3_m3x2_ck", .hw = &dpll3_m3x2_ck_hw.hw, .parent_names = dpll3_m3x2_ck_parent_names, @@ -891,7 +891,7 @@ DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, 0, dpll4_mx_ck_div_table, NULL); -static struct clk dpll4_m4x2_ck; +static struct clk_core dpll4_m4x2_ck; static const char *dpll4_m4x2_ck_parent_names[] = { "dpll4_m4_ck", @@ -911,7 +911,7 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = { DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); -static struct clk dpll4_m4x2_ck_3630 = { +static struct clk_core dpll4_m4x2_ck_3630 = { .name = "dpll4_m4x2_ck", .hw = &dpll4_m4x2_ck_hw.hw, .parent_names = dpll4_m4x2_ck_parent_names, @@ -925,7 +925,7 @@ DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dpll4_m6x2_ck; +static struct clk_core dpll4_m6x2_ck; static const char *dpll4_m6x2_ck_parent_names[] = { "dpll4_m6_ck", @@ -944,7 +944,7 @@ static struct clk_hw_omap dpll4_m6x2_ck_hw = { DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops); -static struct clk dpll4_m6x2_ck_3630 = { +static struct clk_core dpll4_m6x2_ck_3630 = { .name = "dpll4_m6x2_ck", .hw = &dpll4_m6x2_ck_hw.hw, .parent_names = dpll4_m6x2_ck_parent_names, @@ -976,7 +976,7 @@ static struct dpll_data dpll5_dd = { .max_divider = OMAP3_MAX_DPLL_DIV, }; -static struct clk dpll5_ck; +static struct clk_core dpll5_ck; static struct clk_hw_omap dpll5_ck_hw = { .hw = { @@ -994,7 +994,7 @@ DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0, OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk dss1_alwon_fck_3430es1; +static struct clk_core dss1_alwon_fck_3430es1; static const char *dss1_alwon_fck_3430es1_parent_names[] = { "dpll4_m4x2_ck", @@ -1013,7 +1013,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss1_alwon_fck_3430es2; +static struct clk_core dss1_alwon_fck_3430es2; static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = { .hw = { @@ -1029,7 +1029,7 @@ DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, CLK_SET_RATE_PARENT); -static struct clk dss2_alwon_fck; +static struct clk_core dss2_alwon_fck; static struct clk_hw_omap dss2_alwon_fck_hw = { .hw = { @@ -1042,7 +1042,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = { DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk dss_96m_fck; +static struct clk_core dss_96m_fck; static struct clk_hw_omap dss_96m_fck_hw = { .hw = { @@ -1055,7 +1055,7 @@ static struct clk_hw_omap dss_96m_fck_hw = { DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es1; +static struct clk_core dss_ick_3430es1; static struct clk_hw_omap dss_ick_3430es1_hw = { .hw = { @@ -1069,7 +1069,7 @@ static struct clk_hw_omap dss_ick_3430es1_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_ick_3430es2; +static struct clk_core dss_ick_3430es2; static struct clk_hw_omap dss_ick_3430es2_hw = { .hw = { @@ -1083,7 +1083,7 @@ static struct clk_hw_omap dss_ick_3430es2_hw = { DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk dss_tv_fck; +static struct clk_core dss_tv_fck; static const char *dss_tv_fck_parent_names[] = { "omap_54m_fck", @@ -1100,7 +1100,7 @@ static struct clk_hw_omap dss_tv_fck_hw = { DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops); -static struct clk emac_fck; +static struct clk_core emac_fck; static const char *emac_fck_parent_names[] = { "rmii_ck", @@ -1116,7 +1116,7 @@ static struct clk_hw_omap emac_fck_hw = { DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops); -static struct clk ipss_ick; +static struct clk_core ipss_ick; static const char *ipss_ick_parent_names[] = { "core_l3_ick", @@ -1134,7 +1134,7 @@ static struct clk_hw_omap ipss_ick_hw = { DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops); -static struct clk emac_ick; +static struct clk_core emac_ick; static const char *emac_ick_parent_names[] = { "ipss_ick", @@ -1152,7 +1152,7 @@ static struct clk_hw_omap emac_ick_hw = { DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk emu_core_alwon_ck; +static struct clk_core emu_core_alwon_ck; static const char *emu_core_alwon_ck_parent_names[] = { "dpll3_m3x2_ck", @@ -1162,7 +1162,7 @@ DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm"); DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names, core_l4_ick_ops); -static struct clk emu_mpu_alwon_ck; +static struct clk_core emu_mpu_alwon_ck; static const char *emu_mpu_alwon_ck_parent_names[] = { "mpu_ck", @@ -1171,7 +1171,7 @@ static const char *emu_mpu_alwon_ck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL); DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops); -static struct clk emu_per_alwon_ck; +static struct clk_core emu_per_alwon_ck; static const char *emu_per_alwon_ck_parent_names[] = { "dpll4_m6x2_ck", @@ -1222,7 +1222,7 @@ static const struct clk_ops emu_src_ck_ops = { .disable = &omap2_clkops_disable_clkdm, }; -static struct clk emu_src_ck; +static struct clk_core emu_src_ck; static struct clk_hw_omap emu_src_ck_hw = { .hw = { @@ -1241,7 +1241,7 @@ DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk fac_ick; +static struct clk_core fac_ick; static struct clk_hw_omap fac_ick_hw = { .hw = { @@ -1255,7 +1255,7 @@ static struct clk_hw_omap fac_ick_hw = { DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk fshostusb_fck; +static struct clk_core fshostusb_fck; static const char *fshostusb_fck_parent_names[] = { "core_48m_fck", @@ -1273,7 +1273,7 @@ static struct clk_hw_omap fshostusb_fck_hw = { DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ck; +static struct clk_core gfx_l3_ck; static struct clk_hw_omap gfx_l3_ck_hw = { .hw = { @@ -1292,7 +1292,7 @@ DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0, OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk gfx_cg1_ck; +static struct clk_core gfx_cg1_ck; static const char *gfx_cg1_ck_parent_names[] = { "gfx_l3_fck", @@ -1310,7 +1310,7 @@ static struct clk_hw_omap gfx_cg1_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_cg2_ck; +static struct clk_core gfx_cg2_ck; static struct clk_hw_omap gfx_cg2_ck_hw = { .hw = { @@ -1324,7 +1324,7 @@ static struct clk_hw_omap gfx_cg2_ck_hw = { DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); -static struct clk gfx_l3_ick; +static struct clk_core gfx_l3_ick; static const char *gfx_l3_ick_parent_names[] = { "gfx_l3_ck", @@ -1333,7 +1333,7 @@ static const char *gfx_l3_ick_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm"); DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops); -static struct clk wkup_32k_fck; +static struct clk_core wkup_32k_fck; static const char *wkup_32k_fck_parent_names[] = { "omap_32k_fck", @@ -1342,7 +1342,7 @@ static const char *wkup_32k_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio1_dbck; +static struct clk_core gpio1_dbck; static const char *gpio1_dbck_parent_names[] = { "wkup_32k_fck", @@ -1359,12 +1359,12 @@ static struct clk_hw_omap gpio1_dbck_hw = { DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wkup_l4_ick; +static struct clk_core wkup_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm"); DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops); -static struct clk gpio1_ick; +static struct clk_core gpio1_ick; static const char *gpio1_ick_parent_names[] = { "wkup_l4_ick", @@ -1382,13 +1382,13 @@ static struct clk_hw_omap gpio1_ick_hw = { DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk per_32k_alwon_fck; +static struct clk_core per_32k_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); -static struct clk gpio2_dbck; +static struct clk_core gpio2_dbck; static const char *gpio2_dbck_parent_names[] = { "per_32k_alwon_fck", @@ -1405,12 +1405,12 @@ static struct clk_hw_omap gpio2_dbck_hw = { DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk per_l4_ick; +static struct clk_core per_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm"); DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk gpio2_ick; +static struct clk_core gpio2_ick; static const char *gpio2_ick_parent_names[] = { "per_l4_ick", @@ -1428,7 +1428,7 @@ static struct clk_hw_omap gpio2_ick_hw = { DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio3_dbck; +static struct clk_core gpio3_dbck; static struct clk_hw_omap gpio3_dbck_hw = { .hw = { @@ -1441,7 +1441,7 @@ static struct clk_hw_omap gpio3_dbck_hw = { DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio3_ick; +static struct clk_core gpio3_ick; static struct clk_hw_omap gpio3_ick_hw = { .hw = { @@ -1455,7 +1455,7 @@ static struct clk_hw_omap gpio3_ick_hw = { DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio4_dbck; +static struct clk_core gpio4_dbck; static struct clk_hw_omap gpio4_dbck_hw = { .hw = { @@ -1468,7 +1468,7 @@ static struct clk_hw_omap gpio4_dbck_hw = { DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio4_ick; +static struct clk_core gpio4_ick; static struct clk_hw_omap gpio4_ick_hw = { .hw = { @@ -1482,7 +1482,7 @@ static struct clk_hw_omap gpio4_ick_hw = { DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio5_dbck; +static struct clk_core gpio5_dbck; static struct clk_hw_omap gpio5_dbck_hw = { .hw = { @@ -1495,7 +1495,7 @@ static struct clk_hw_omap gpio5_dbck_hw = { DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio5_ick; +static struct clk_core gpio5_ick; static struct clk_hw_omap gpio5_ick_hw = { .hw = { @@ -1509,7 +1509,7 @@ static struct clk_hw_omap gpio5_ick_hw = { DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpio6_dbck; +static struct clk_core gpio6_dbck; static struct clk_hw_omap gpio6_dbck_hw = { .hw = { @@ -1522,7 +1522,7 @@ static struct clk_hw_omap gpio6_dbck_hw = { DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk gpio6_ick; +static struct clk_core gpio6_ick; static struct clk_hw_omap gpio6_ick_hw = { .hw = { @@ -1536,7 +1536,7 @@ static struct clk_hw_omap gpio6_ick_hw = { DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk gpmc_fck; +static struct clk_core gpmc_fck; static struct clk_hw_omap gpmc_fck_hw = { .hw = { @@ -1565,7 +1565,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt10_ick; +static struct clk_core gpt10_ick; static struct clk_hw_omap gpt10_ick_hw = { .hw = { @@ -1586,7 +1586,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt11_ick; +static struct clk_core gpt11_ick; static struct clk_hw_omap gpt11_ick_hw = { .hw = { @@ -1600,7 +1600,7 @@ static struct clk_hw_omap gpt11_ick_hw = { DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk gpt12_fck; +static struct clk_core gpt12_fck; static const char *gpt12_fck_parent_names[] = { "secure_32k_fck", @@ -1609,7 +1609,7 @@ static const char *gpt12_fck_parent_names[] = { DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk gpt12_ick; +static struct clk_core gpt12_ick; static struct clk_hw_omap gpt12_ick_hw = { .hw = { @@ -1630,7 +1630,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt1_ick; +static struct clk_core gpt1_ick; static struct clk_hw_omap gpt1_ick_hw = { .hw = { @@ -1651,7 +1651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt2_ick; +static struct clk_core gpt2_ick; static struct clk_hw_omap gpt2_ick_hw = { .hw = { @@ -1672,7 +1672,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt3_ick; +static struct clk_core gpt3_ick; static struct clk_hw_omap gpt3_ick_hw = { .hw = { @@ -1693,7 +1693,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt4_ick; +static struct clk_core gpt4_ick; static struct clk_hw_omap gpt4_ick_hw = { .hw = { @@ -1714,7 +1714,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt5_ick; +static struct clk_core gpt5_ick; static struct clk_hw_omap gpt5_ick_hw = { .hw = { @@ -1735,7 +1735,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt6_ick; +static struct clk_core gpt6_ick; static struct clk_hw_omap gpt6_ick_hw = { .hw = { @@ -1756,7 +1756,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt7_ick; +static struct clk_core gpt7_ick; static struct clk_hw_omap gpt7_ick_hw = { .hw = { @@ -1777,7 +1777,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt8_ick; +static struct clk_core gpt8_ick; static struct clk_hw_omap gpt8_ick_hw = { .hw = { @@ -1798,7 +1798,7 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel, OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait, gpt10_fck_parent_names, clkout2_src_ck_ops); -static struct clk gpt9_ick; +static struct clk_core gpt9_ick; static struct clk_hw_omap gpt9_ick_hw = { .hw = { @@ -1812,7 +1812,7 @@ static struct clk_hw_omap gpt9_ick_hw = { DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk hdq_fck; +static struct clk_core hdq_fck; static const char *hdq_fck_parent_names[] = { "core_12m_fck", @@ -1830,7 +1830,7 @@ static struct clk_hw_omap hdq_fck_hw = { DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops); -static struct clk hdq_ick; +static struct clk_core hdq_ick; static struct clk_hw_omap hdq_ick_hw = { .hw = { @@ -1844,7 +1844,7 @@ static struct clk_hw_omap hdq_ick_hw = { DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk hecc_ck; +static struct clk_core hecc_ck; static struct clk_hw_omap hecc_ck_hw = { .hw = { @@ -1858,7 +1858,7 @@ static struct clk_hw_omap hecc_ck_hw = { DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_fck_am35xx; +static struct clk_core hsotgusb_fck_am35xx; static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { .hw = { @@ -1871,7 +1871,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es1; +static struct clk_core hsotgusb_ick_3430es1; static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { .hw = { @@ -1885,7 +1885,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_3430es2; +static struct clk_core hsotgusb_ick_3430es2; static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { .hw = { @@ -1899,7 +1899,7 @@ static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops); -static struct clk hsotgusb_ick_am35xx; +static struct clk_core hsotgusb_ick_am35xx; static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { .hw = { @@ -1913,7 +1913,7 @@ static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops); -static struct clk i2c1_fck; +static struct clk_core i2c1_fck; static struct clk_hw_omap i2c1_fck_hw = { .hw = { @@ -1927,7 +1927,7 @@ static struct clk_hw_omap i2c1_fck_hw = { DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c1_ick; +static struct clk_core i2c1_ick; static struct clk_hw_omap i2c1_ick_hw = { .hw = { @@ -1941,7 +1941,7 @@ static struct clk_hw_omap i2c1_ick_hw = { DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c2_fck; +static struct clk_core i2c2_fck; static struct clk_hw_omap i2c2_fck_hw = { .hw = { @@ -1955,7 +1955,7 @@ static struct clk_hw_omap i2c2_fck_hw = { DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c2_ick; +static struct clk_core i2c2_ick; static struct clk_hw_omap i2c2_ick_hw = { .hw = { @@ -1969,7 +1969,7 @@ static struct clk_hw_omap i2c2_ick_hw = { DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk i2c3_fck; +static struct clk_core i2c3_fck; static struct clk_hw_omap i2c3_fck_hw = { .hw = { @@ -1983,7 +1983,7 @@ static struct clk_hw_omap i2c3_fck_hw = { DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk i2c3_ick; +static struct clk_core i2c3_ick; static struct clk_hw_omap i2c3_ick_hw = { .hw = { @@ -1997,7 +1997,7 @@ static struct clk_hw_omap i2c3_ick_hw = { DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk icr_ick; +static struct clk_core icr_ick; static struct clk_hw_omap icr_ick_hw = { .hw = { @@ -2011,7 +2011,7 @@ static struct clk_hw_omap icr_ick_hw = { DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk iva2_ck; +static struct clk_core iva2_ck; static const char *iva2_ck_parent_names[] = { "dpll2_m2_ck", @@ -2029,7 +2029,7 @@ static struct clk_hw_omap iva2_ck_hw = { DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops); -static struct clk mad2d_ick; +static struct clk_core mad2d_ick; static struct clk_hw_omap mad2d_ick_hw = { .hw = { @@ -2043,7 +2043,7 @@ static struct clk_hw_omap mad2d_ick_hw = { DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk mailboxes_ick; +static struct clk_core mailboxes_ick; static struct clk_hw_omap mailboxes_ick_hw = { .hw = { @@ -2084,7 +2084,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp1_ick; +static struct clk_core mcbsp1_ick; static struct clk_hw_omap mcbsp1_ick_hw = { .hw = { @@ -2098,7 +2098,7 @@ static struct clk_hw_omap mcbsp1_ick_hw = { DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk per_96m_fck; +static struct clk_core per_96m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops); @@ -2120,7 +2120,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp2_ick; +static struct clk_core mcbsp2_ick; static struct clk_hw_omap mcbsp2_ick_hw = { .hw = { @@ -2141,7 +2141,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp3_ick; +static struct clk_core mcbsp3_ick; static struct clk_hw_omap mcbsp3_ick_hw = { .hw = { @@ -2162,7 +2162,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel, OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait, mcbsp2_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp4_ick; +static struct clk_core mcbsp4_ick; static struct clk_hw_omap mcbsp4_ick_hw = { .hw = { @@ -2183,7 +2183,7 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel, OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait, mcbsp1_fck_parent_names, clkout2_src_ck_ops); -static struct clk mcbsp5_ick; +static struct clk_core mcbsp5_ick; static struct clk_hw_omap mcbsp5_ick_hw = { .hw = { @@ -2197,7 +2197,7 @@ static struct clk_hw_omap mcbsp5_ick_hw = { DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi1_fck; +static struct clk_core mcspi1_fck; static struct clk_hw_omap mcspi1_fck_hw = { .hw = { @@ -2211,7 +2211,7 @@ static struct clk_hw_omap mcspi1_fck_hw = { DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi1_ick; +static struct clk_core mcspi1_ick; static struct clk_hw_omap mcspi1_ick_hw = { .hw = { @@ -2225,7 +2225,7 @@ static struct clk_hw_omap mcspi1_ick_hw = { DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi2_fck; +static struct clk_core mcspi2_fck; static struct clk_hw_omap mcspi2_fck_hw = { .hw = { @@ -2239,7 +2239,7 @@ static struct clk_hw_omap mcspi2_fck_hw = { DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi2_ick; +static struct clk_core mcspi2_ick; static struct clk_hw_omap mcspi2_ick_hw = { .hw = { @@ -2253,7 +2253,7 @@ static struct clk_hw_omap mcspi2_ick_hw = { DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi3_fck; +static struct clk_core mcspi3_fck; static struct clk_hw_omap mcspi3_fck_hw = { .hw = { @@ -2267,7 +2267,7 @@ static struct clk_hw_omap mcspi3_fck_hw = { DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi3_ick; +static struct clk_core mcspi3_ick; static struct clk_hw_omap mcspi3_ick_hw = { .hw = { @@ -2281,7 +2281,7 @@ static struct clk_hw_omap mcspi3_ick_hw = { DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mcspi4_fck; +static struct clk_core mcspi4_fck; static struct clk_hw_omap mcspi4_fck_hw = { .hw = { @@ -2295,7 +2295,7 @@ static struct clk_hw_omap mcspi4_fck_hw = { DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk mcspi4_ick; +static struct clk_core mcspi4_ick; static struct clk_hw_omap mcspi4_ick_hw = { .hw = { @@ -2309,7 +2309,7 @@ static struct clk_hw_omap mcspi4_ick_hw = { DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs1_fck; +static struct clk_core mmchs1_fck; static struct clk_hw_omap mmchs1_fck_hw = { .hw = { @@ -2323,7 +2323,7 @@ static struct clk_hw_omap mmchs1_fck_hw = { DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs1_ick; +static struct clk_core mmchs1_ick; static struct clk_hw_omap mmchs1_ick_hw = { .hw = { @@ -2337,7 +2337,7 @@ static struct clk_hw_omap mmchs1_ick_hw = { DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs2_fck; +static struct clk_core mmchs2_fck; static struct clk_hw_omap mmchs2_fck_hw = { .hw = { @@ -2351,7 +2351,7 @@ static struct clk_hw_omap mmchs2_fck_hw = { DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs2_ick; +static struct clk_core mmchs2_ick; static struct clk_hw_omap mmchs2_ick_hw = { .hw = { @@ -2365,7 +2365,7 @@ static struct clk_hw_omap mmchs2_ick_hw = { DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk mmchs3_fck; +static struct clk_core mmchs3_fck; static struct clk_hw_omap mmchs3_fck_hw = { .hw = { @@ -2379,7 +2379,7 @@ static struct clk_hw_omap mmchs3_fck_hw = { DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mmchs3_ick; +static struct clk_core mmchs3_ick; static struct clk_hw_omap mmchs3_ick_hw = { .hw = { @@ -2393,7 +2393,7 @@ static struct clk_hw_omap mmchs3_ick_hw = { DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk modem_fck; +static struct clk_core modem_fck; static struct clk_hw_omap modem_fck_hw = { .hw = { @@ -2407,7 +2407,7 @@ static struct clk_hw_omap modem_fck_hw = { DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk mspro_fck; +static struct clk_core mspro_fck; static struct clk_hw_omap mspro_fck_hw = { .hw = { @@ -2421,7 +2421,7 @@ static struct clk_hw_omap mspro_fck_hw = { DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops); -static struct clk mspro_ick; +static struct clk_core mspro_ick; static struct clk_hw_omap mspro_ick_hw = { .hw = { @@ -2435,13 +2435,13 @@ static struct clk_hw_omap mspro_ick_hw = { DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk omap_192m_alwon_fck; +static struct clk_core omap_192m_alwon_fck; DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL); DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names, core_ck_ops); -static struct clk omap_32ksync_ick; +static struct clk_core omap_32ksync_ick; static struct clk_hw_omap omap_32ksync_ick_hw = { .hw = { @@ -2466,7 +2466,7 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = { { .parent = NULL } }; -static struct clk omap_96m_alwon_fck_3630; +static struct clk_core omap_96m_alwon_fck_3630; static const char *omap_96m_alwon_fck_3630_parent_names[] = { "omap_192m_alwon_fck", @@ -2487,7 +2487,7 @@ static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = { .clksel_mask = OMAP3630_CLKSEL_96M_MASK, }; -static struct clk omap_96m_alwon_fck_3630 = { +static struct clk_core omap_96m_alwon_fck_3630 = { .name = "omap_96m_alwon_fck", .hw = &omap_96m_alwon_fck_3630_hw.hw, .parent_names = omap_96m_alwon_fck_3630_parent_names, @@ -2495,7 +2495,7 @@ static struct clk omap_96m_alwon_fck_3630 = { .ops = &omap_96m_alwon_fck_3630_ops, }; -static struct clk omapctrl_ick; +static struct clk_core omapctrl_ick; static struct clk_hw_omap omapctrl_ick_hw = { .hw = { @@ -2520,17 +2520,17 @@ DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0, OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk per_48m_fck; +static struct clk_core per_48m_fck; DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm"); DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops); -static struct clk security_l3_ick; +static struct clk_core security_l3_ick; DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL); DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops); -static struct clk pka_ick; +static struct clk_core pka_ick; static const char *pka_ick_parent_names[] = { "security_l3_ick", @@ -2552,7 +2552,7 @@ DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0, OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk rng_ick; +static struct clk_core rng_ick; static struct clk_hw_omap rng_ick_hw = { .hw = { @@ -2565,7 +2565,7 @@ static struct clk_hw_omap rng_ick_hw = { DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sad2d_ick; +static struct clk_core sad2d_ick; static struct clk_hw_omap sad2d_ick_hw = { .hw = { @@ -2579,7 +2579,7 @@ static struct clk_hw_omap sad2d_ick_hw = { DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sdrc_ick; +static struct clk_core sdrc_ick; static struct clk_hw_omap sdrc_ick_hw = { .hw = { @@ -2630,7 +2630,7 @@ static const char *sgx_fck_parent_names[] = { "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck", }; -static struct clk sgx_fck; +static struct clk_core sgx_fck; static const struct clk_ops sgx_fck_ops = { .init = &omap2_init_clk_clkdm, @@ -2651,7 +2651,7 @@ DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel, OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops); -static struct clk sgx_ick; +static struct clk_core sgx_ick; static struct clk_hw_omap sgx_ick_hw = { .hw = { @@ -2665,7 +2665,7 @@ static struct clk_hw_omap sgx_ick_hw = { DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops); -static struct clk sha11_ick; +static struct clk_core sha11_ick; static struct clk_hw_omap sha11_ick_hw = { .hw = { @@ -2678,7 +2678,7 @@ static struct clk_hw_omap sha11_ick_hw = { DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops); -static struct clk sha12_ick; +static struct clk_core sha12_ick; static struct clk_hw_omap sha12_ick_hw = { .hw = { @@ -2692,7 +2692,7 @@ static struct clk_hw_omap sha12_ick_hw = { DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk sr1_fck; +static struct clk_core sr1_fck; static struct clk_hw_omap sr1_fck_hw = { .hw = { @@ -2706,7 +2706,7 @@ static struct clk_hw_omap sr1_fck_hw = { DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr2_fck; +static struct clk_core sr2_fck; static struct clk_hw_omap sr2_fck_hw = { .hw = { @@ -2720,17 +2720,17 @@ static struct clk_hw_omap sr2_fck_hw = { DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops); -static struct clk sr_l4_ick; +static struct clk_core sr_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_l4_ick; +static struct clk_core ssi_l4_ick; DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm"); DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); -static struct clk ssi_ick_3430es1; +static struct clk_core ssi_ick_3430es1; static const char *ssi_ick_3430es1_parent_names[] = { "ssi_l4_ick", @@ -2748,7 +2748,7 @@ static struct clk_hw_omap ssi_ick_3430es1_hw = { DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops); -static struct clk ssi_ick_3430es2; +static struct clk_core ssi_ick_3430es2; static struct clk_hw_omap ssi_ick_3430es2_hw = { .hw = { @@ -2813,7 +2813,7 @@ DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1", DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2", &ssi_ssr_fck_3430es2, 0x0, 1, 2); -static struct clk sys_clkout1; +static struct clk_core sys_clkout1; static const char *sys_clkout1_parent_names[] = { "osc_sys_ck", @@ -2843,7 +2843,7 @@ DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0, OMAP3430_CLKSEL_TRACECLK_SHIFT, OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static struct clk ts_fck; +static struct clk_core ts_fck; static struct clk_hw_omap ts_fck_hw = { .hw = { @@ -2856,7 +2856,7 @@ static struct clk_hw_omap ts_fck_hw = { DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops); -static struct clk uart1_fck; +static struct clk_core uart1_fck; static struct clk_hw_omap uart1_fck_hw = { .hw = { @@ -2870,7 +2870,7 @@ static struct clk_hw_omap uart1_fck_hw = { DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart1_ick; +static struct clk_core uart1_ick; static struct clk_hw_omap uart1_ick_hw = { .hw = { @@ -2884,7 +2884,7 @@ static struct clk_hw_omap uart1_ick_hw = { DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart2_fck; +static struct clk_core uart2_fck; static struct clk_hw_omap uart2_fck_hw = { .hw = { @@ -2898,7 +2898,7 @@ static struct clk_hw_omap uart2_fck_hw = { DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart2_ick; +static struct clk_core uart2_ick; static struct clk_hw_omap uart2_ick_hw = { .hw = { @@ -2912,7 +2912,7 @@ static struct clk_hw_omap uart2_ick_hw = { DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops); -static struct clk uart3_fck; +static struct clk_core uart3_fck; static const char *uart3_fck_parent_names[] = { "per_48m_fck", @@ -2930,7 +2930,7 @@ static struct clk_hw_omap uart3_fck_hw = { DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart3_ick; +static struct clk_core uart3_ick; static struct clk_hw_omap uart3_ick_hw = { .hw = { @@ -2944,7 +2944,7 @@ static struct clk_hw_omap uart3_ick_hw = { DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_fck; +static struct clk_core uart4_fck; static struct clk_hw_omap uart4_fck_hw = { .hw = { @@ -2958,7 +2958,7 @@ static struct clk_hw_omap uart4_fck_hw = { DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops); -static struct clk uart4_fck_am35xx; +static struct clk_core uart4_fck_am35xx; static struct clk_hw_omap uart4_fck_am35xx_hw = { .hw = { @@ -2972,7 +2972,7 @@ static struct clk_hw_omap uart4_fck_am35xx_hw = { DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops); -static struct clk uart4_ick; +static struct clk_core uart4_ick; static struct clk_hw_omap uart4_ick_hw = { .hw = { @@ -2986,7 +2986,7 @@ static struct clk_hw_omap uart4_ick_hw = { DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops); -static struct clk uart4_ick_am35xx; +static struct clk_core uart4_ick_am35xx; static struct clk_hw_omap uart4_ick_am35xx_hw = { .hw = { @@ -3023,7 +3023,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel, &clkhwops_iclk_wait, usb_l4_ick_parent_names, ssi_ssr_fck_3430es1_ops); -static struct clk usbhost_120m_fck; +static struct clk_core usbhost_120m_fck; static const char *usbhost_120m_fck_parent_names[] = { "dpll5_m2_ck", @@ -3041,7 +3041,7 @@ static struct clk_hw_omap usbhost_120m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_48m_fck; +static struct clk_core usbhost_48m_fck; static struct clk_hw_omap usbhost_48m_fck_hw = { .hw = { @@ -3055,7 +3055,7 @@ static struct clk_hw_omap usbhost_48m_fck_hw = { DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops); -static struct clk usbhost_ick; +static struct clk_core usbhost_ick; static struct clk_hw_omap usbhost_ick_hw = { .hw = { @@ -3069,7 +3069,7 @@ static struct clk_hw_omap usbhost_ick_hw = { DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops); -static struct clk usbtll_fck; +static struct clk_core usbtll_fck; static struct clk_hw_omap usbtll_fck_hw = { .hw = { @@ -3083,7 +3083,7 @@ static struct clk_hw_omap usbtll_fck_hw = { DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); -static struct clk usbtll_ick; +static struct clk_core usbtll_ick; static struct clk_hw_omap usbtll_ick_hw = { .hw = { @@ -3124,7 +3124,7 @@ static const char *usim_fck_parent_names[] = { "omap_96m_fck", "dpll5_m2_ck", "sys_ck", }; -static struct clk usim_fck; +static struct clk_core usim_fck; static const struct clk_ops usim_fck_ops = { .enable = &omap2_dflt_clk_enable, @@ -3142,7 +3142,7 @@ DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel, OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait, usim_fck_parent_names, usim_fck_ops); -static struct clk usim_ick; +static struct clk_core usim_ick; static struct clk_hw_omap usim_ick_hw = { .hw = { @@ -3156,7 +3156,7 @@ static struct clk_hw_omap usim_ick_hw = { DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk vpfe_fck; +static struct clk_core vpfe_fck; static const char *vpfe_fck_parent_names[] = { "pclk_ck", @@ -3172,7 +3172,7 @@ static struct clk_hw_omap vpfe_fck_hw = { DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops); -static struct clk vpfe_ick; +static struct clk_core vpfe_ick; static struct clk_hw_omap vpfe_ick_hw = { .hw = { @@ -3186,12 +3186,12 @@ static struct clk_hw_omap vpfe_ick_hw = { DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops); -static struct clk wdt1_fck; +static struct clk_core wdt1_fck; DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm"); DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops); -static struct clk wdt1_ick; +static struct clk_core wdt1_ick; static struct clk_hw_omap wdt1_ick_hw = { .hw = { @@ -3205,7 +3205,7 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt2_fck; +static struct clk_core wdt2_fck; static struct clk_hw_omap wdt2_fck_hw = { .hw = { @@ -3219,7 +3219,7 @@ static struct clk_hw_omap wdt2_fck_hw = { DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops); -static struct clk wdt2_ick; +static struct clk_core wdt2_ick; static struct clk_hw_omap wdt2_ick_hw = { .hw = { @@ -3233,7 +3233,7 @@ static struct clk_hw_omap wdt2_ick_hw = { DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops); -static struct clk wdt3_fck; +static struct clk_core wdt3_fck; static struct clk_hw_omap wdt3_fck_hw = { .hw = { @@ -3247,7 +3247,7 @@ static struct clk_hw_omap wdt3_fck_hw = { DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops); -static struct clk wdt3_ick; +static struct clk_core wdt3_ick; static struct clk_hw_omap wdt3_ick_hw = { .hw = { @@ -3661,10 +3661,10 @@ int __init omap3xxx_clk_init(void) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&osc_sys_ck) / 1000000), - (clk_get_rate(&osc_sys_ck) / 100000) % 10, - (clk_get_rate(&core_ck) / 1000000), - (clk_get_rate(&arm_fck) / 1000000)); + (clk_provider_get_rate(&osc_sys_ck) / 1000000), + (clk_provider_get_rate(&osc_sys_ck) / 100000) % 10, + (clk_provider_get_rate(&core_ck) / 1000000), + (clk_provider_get_rate(&arm_fck) / 1000000)); /* * Lock DPLL5 -- here only until other device init code can @@ -3674,8 +3674,8 @@ int __init omap3xxx_clk_init(void) omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ - sdrc_ick_p = clk_get(NULL, "sdrc_ick"); - arm_fck_p = clk_get(NULL, "arm_fck"); + sdrc_ick_p = clk_provider_get(NULL, "sdrc_ick"); + arm_fck_p = clk_provider_get(NULL, "arm_fck"); return 0; } diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 82572e2..28a6d42 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -22,7 +22,7 @@ /** * _allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. The DPLL will enter low-power * stop when its downstream clocks are gated. No return value. @@ -39,7 +39,7 @@ static void _allow_idle(struct clk_hw_omap *clk) /** * _deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 59cf310..6723d916 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -48,7 +48,7 @@ static struct clk_hw_omap *dpll_core_ck; * Returns the CORE_CLK rate. CORE_CLK can have one of three rate * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz * (the latter is unusual). This currently should be called with - * struct clk *dpll_ck, which is a composite clock of dpll_ck and + * struct clk_core *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ unsigned long omap2xxx_clk_get_core_rate(void) @@ -179,7 +179,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, /** * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck - * @clk: struct clk *dpll_ck + * @clk: struct clk_core *dpll_ck * * Store a local copy of @clk in dpll_core_ck so other code can query * the core rate without having to clk_get(), which can sleep. Must diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 85e0b0c0..67014e1 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -198,14 +198,14 @@ void omap2xxx_clkt_vps_check_bootloader_rates(void) */ void omap2xxx_clkt_vps_late_init(void) { - struct clk *c; + struct clk_core *c; - c = clk_get(NULL, "sys_ck"); + c = clk_provider_get(NULL, "sys_ck"); if (IS_ERR(c)) { WARN(1, "could not locate sys_ck\n"); } else { - sys_ck_rate = clk_get_rate(c); - clk_put(c); + sys_ck_rate = clk_provider_get_rate(c); + __clk_put(c); } } @@ -230,7 +230,7 @@ void omap2xxx_clkt_vps_init(void) { struct clk_init_data init = { NULL }; struct clk_hw_omap *hw = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name = "mpu_ck"; struct clk_lookup *lookup = NULL; diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index eb69acf..9e96363 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -38,7 +38,7 @@ /** * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Program the DPLL M2 divider with the rounded target rate. Returns diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 7ee2610..b4796b3 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -51,15 +51,15 @@ /** * _get_clksel_by_parent() - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for + * @clk: OMAP struct clk_core ptr to inspect + * @src_clk: OMAP struct clk_core ptr of the parent clk to search for * * Scan the struct clksel array associated with the clock to find * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, - struct clk *src_clk) + struct clk_core *src_clk) { const struct clksel *clks; @@ -82,7 +82,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, /** * _write_clksel_reg() - program a clock's clksel register in hardware - * @clk: struct clk * to program + * @clk: struct clk_core * to program * @v: clksel bitfield value to program (with LSB at bit 0) * * Shift the clksel register bitfield value @v to its appropriate @@ -107,10 +107,10 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) /** * _clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @field_val: register field value to find * - * Given a struct clk of a rate-selectable clksel clock, and a register field + * Given a struct clk_core of a rate-selectable clksel clock, and a register field * value to search for, find the corresponding clock divisor. The register * field value should be pre-masked and shifted down so the LSB is at bit 0 * before calling. Returns 0 on error or returns the actual integer divisor @@ -120,7 +120,7 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; parent = __clk_get_parent(clk->hw.clk); @@ -149,10 +149,10 @@ static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) /** * _divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @div: integer divisor to search for * - * Given a struct clk of a rate-selectable clksel clock, and a clock + * Given a struct clk_core of a rate-selectable clksel clock, and a clock * divisor, find the corresponding register field value. Returns the * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. @@ -161,7 +161,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; - struct clk *parent; + struct clk_core *parent; /* should never happen */ WARN_ON(div == 0); @@ -191,7 +191,7 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) /** * _read_divisor() - get current divisor applied to parent clock (from hdwr) - * @clk: OMAP struct clk to use. + * @clk: OMAP struct clk_core to use. * * Read the current divisor register value for @clk that is programmed * into the hardware, convert it into the actual divisor value, and @@ -215,7 +215,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk) /** * omap2_clksel_round_rate_div() - find divisor for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * @new_div: ptr to where we should store the divisor * @@ -233,7 +233,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, const struct clksel *clks; const struct clksel_rate *clkr; u32 last_div = 0; - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; const char *clk_name; @@ -286,7 +286,7 @@ u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, /* * Clocktype interface functions to the OMAP clock code - * (i.e., those used in struct clk field function pointers, etc.) + * (i.e., those used in struct clk_core field function pointers, etc.) */ /** @@ -309,7 +309,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) const struct clksel *clks; const struct clksel_rate *clkr; u32 r, found = 0; - struct clk *parent; + struct clk_core *parent; const char *clk_name; int ret = 0, f = 0; @@ -345,11 +345,11 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) /** - * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field - * @clk: struct clk * + * omap2_clksel_recalc() - function ptr to pass via struct clk_core .recalc field + * @clk: struct clk_core * * * This function is intended to be called only by the clock framework. - * Each clksel clock should have its struct clk .recalc field set to this + * Each clksel clock should have its struct clk_core .recalc field set to this * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ @@ -376,7 +376,7 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use + * @clk: OMAP struct clk_core to use * @target_rate: desired clock rate * * This function is intended to be called only by the clock framework. @@ -396,7 +396,7 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, /** * omap2_clksel_set_rate() - program clock rate in hardware - * @clk: struct clk * to program rate + * @clk: struct clk_core * to program rate * @rate: target rate to program * * This function is intended to be called only by the clock framework. @@ -435,7 +435,7 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, } /* - * Clksel parent setting function - not passed in struct clk function + * Clksel parent setting function - not passed in struct clk_core function * pointer - instead, the OMAP clock code currently assumes that any * parent-setting clock is a clksel clock, and calls * omap2_clksel_set_parent() by default @@ -443,8 +443,8 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap2_clksel_set_parent() - change a clock's parent clock - * @clk: struct clk * of the child clock - * @new_parent: struct clk * of the new parent clock + * @clk: struct clk_core * of the child clock + * @new_parent: struct clk_core * of the new parent clock * * This function is intended to be called only by the clock framework. * Change the parent clock of clock @clk to @new_parent. This is diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 67fd26a..c313b53 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -67,7 +67,7 @@ /* * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test + * @clk: DPLL struct clk_core to test * @n: divider value (N) to test * * Tests whether a particular divider @n will result in a valid DPLL @@ -200,7 +200,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - /* Reparent the struct clk in case the dpll is in bypass */ + /* Reparent the struct clk_core in case the dpll is in bypass */ if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) @@ -220,7 +220,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) /** * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL + * @clk: struct clk_core * of a DPLL * * DPLLs can be locked or bypassed - basically, enabled or disabled. * When locked, the DPLL output depends on the M and N values. When @@ -278,7 +278,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) /** * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL + * @clk: struct clk_core * for a DPLL * @target_rate: desired DPLL clock rate * * Given a DPLL and a desired target rate, round the target rate to a diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 591581a..072cc41 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -145,7 +145,7 @@ static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, /** * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module + * @clk: struct clk_core * belonging to the module * * If the necessary clocks for the OMAP hardware IP block that * corresponds to clock @clk are enabled, then wait for the module to @@ -184,7 +184,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use * - * Convert a clockdomain name stored in a struct clk 'clk' into a + * Convert a clockdomain name stored in a struct clk_core 'clk' into a * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ @@ -225,7 +225,7 @@ void __init omap2_clk_disable_clkdm_control(void) /** * omap2_clk_dflt_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of + * @clk: struct clk_core * to find the companion clock of * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in * @other_bit: u8 ** to return the companion clock bit shift in * @@ -261,7 +261,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, /** * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk - * @clk: struct clk * to find IDLEST info for + * @clk: struct clk_core * to find IDLEST info for * @idlest_reg: void __iomem ** to return the CM_IDLEST va in * @idlest_bit: u8 * to return the CM_IDLEST bit shift in * @idlest_val: u8 * to return the idle status indicator @@ -511,14 +511,14 @@ __setup("mpurate=", omap_clk_setup); /** * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock - * @clk: struct clk * to initialize + * @clk: struct clk_core * to initialize * * Add an OMAP clock @clk to the internal list of OMAP clocks. Used * temporarily for autoidle handling, until this support can be * integrated into the common clock framework code in some way. No * return value. */ -void omap2_init_clk_hw_omap_clocks(struct clk *clk) +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk) { struct clk_hw_omap *c; @@ -575,11 +575,11 @@ int omap2_clk_disable_autoidle_all(void) /** * omap2_clk_deny_idle - disable autoidle on an OMAP clock - * @clk: struct clk * to disable autoidle for + * @clk: struct clk_core * to disable autoidle for * * Disable autoidle on an OMAP clock. */ -int omap2_clk_deny_idle(struct clk *clk) +int omap2_clk_deny_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -594,11 +594,11 @@ int omap2_clk_deny_idle(struct clk *clk) /** * omap2_clk_allow_idle - enable autoidle on an OMAP clock - * @clk: struct clk * to enable autoidle for + * @clk: struct clk_core * to enable autoidle for * * Enable autoidle on an OMAP clock. */ -int omap2_clk_allow_idle(struct clk *clk) +int omap2_clk_allow_idle(struct clk_core *clk) { struct clk_hw_omap *c; @@ -623,12 +623,12 @@ int omap2_clk_allow_idle(struct clk *clk) */ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) { - struct clk *init_clk; + struct clk_core *init_clk; int i; for (i = 0; i < num_clocks; i++) { - init_clk = clk_get(NULL, clk_names[i]); - clk_prepare_enable(init_clk); + init_clk = clk_provider_get(NULL, clk_names[i]); + clk_provider_prepare_enable(init_clk); } } @@ -664,31 +664,31 @@ void __init omap_clocks_register(struct omap_clk oclks[], int cnt) * the OPP layer. XXX This is intended to be handled by the OPP layer * code in the near future and should be removed from the clock code. * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects - * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name + * the rate, -ENOENT if the struct clk_core referred to by @mpurate_ck_name * cannot be found, or 0 upon success. */ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) { - struct clk *mpurate_ck; + struct clk_core *mpurate_ck; int r; if (!mpurate) return -EINVAL; - mpurate_ck = clk_get(NULL, mpurate_ck_name); + mpurate_ck = clk_provider_get(NULL, mpurate_ck_name); if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) return -ENOENT; - r = clk_set_rate(mpurate_ck, mpurate); + r = clk_provider_set_rate(mpurate_ck, mpurate); if (r < 0) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", mpurate_ck_name, mpurate, r); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); - clk_put(mpurate_ck); + __clk_put(mpurate_ck); return 0; } @@ -709,25 +709,25 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name) { - struct clk *hfclkin_ck, *core_ck, *mpu_ck; + struct clk_core *hfclkin_ck, *core_ck, *mpu_ck; unsigned long hfclkin_rate; - mpu_ck = clk_get(NULL, mpu_ck_name); + mpu_ck = clk_provider_get(NULL, mpu_ck_name); if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) return; - core_ck = clk_get(NULL, core_ck_name); + core_ck = clk_provider_get(NULL, core_ck_name); if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) return; - hfclkin_ck = clk_get(NULL, hfclkin_ck_name); + hfclkin_ck = clk_provider_get(NULL, hfclkin_ck_name); if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) return; - hfclkin_rate = clk_get_rate(hfclkin_ck); + hfclkin_rate = clk_provider_get_rate(hfclkin_ck); pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), - (clk_get_rate(core_ck) / 1000000), - (clk_get_rate(mpu_ck) / 1000000)); + (clk_provider_get_rate(core_ck) / 1000000), + (clk_provider_get_rate(mpu_ck) / 1000000)); } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 12f54d4..05e3d5b 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -40,7 +40,7 @@ struct omap_clk { struct clockdomain; #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -50,7 +50,7 @@ struct clockdomain; #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ _clkops_name, _flags) \ - static struct clk _name = { \ + static struct clk_core _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ @@ -70,7 +70,7 @@ struct clockdomain; #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ _clksel_reg, _clksel_mask, \ _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -86,7 +86,7 @@ struct clockdomain; _clksel_reg, _clksel_mask, \ _enable_reg, _enable_bit, \ _hwops, _parent_names, _ops) \ - static struct clk _name; \ + static struct clk_core _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -111,7 +111,7 @@ struct clockdomain; }, \ { .parent = NULL }, \ }; \ - static struct clk _name; \ + static struct clk_core _name; \ static const char *_name##_parent_names[] = { \ _parent_name, \ }; \ @@ -167,14 +167,14 @@ struct clksel_rate { /** * struct clksel - available parent clocks, and a pointer to their divisors - * @parent: struct clk * to a possible parent clock + * @parent: struct clk_core * to a possible parent clock * @rates: available divisors for this parent clock * * A struct clksel is always associated with one or more struct clks * and one or more struct clksel_rates. */ struct clksel { - struct clk *parent; + struct clk_core *parent; const struct clksel_rate *rates; }; @@ -236,8 +236,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); int omap2_clk_enable_autoidle_all(void); -int omap2_clk_allow_idle(struct clk *clk); -int omap2_clk_deny_idle(struct clk *clk); +int omap2_clk_allow_idle(struct clk_core *clk); +int omap2_clk_deny_idle(struct clk_core *clk); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -258,7 +258,7 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; -extern struct clk dummy_ck; +extern struct clk_core dummy_ck; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 0b02b41..17abc81 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -37,7 +37,7 @@ #define DPLL5_FREQ_FOR_USBHOST 120000000 /* needed by omap3_core_dpll_m2_set_rate() */ -struct clk *sdrc_ick_p, *arm_fck_p; +struct clk_core *sdrc_ick_p, *arm_fck_p; int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -56,20 +56,20 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, void __init omap3_clk_lock_dpll5(void) { - struct clk *dpll5_clk; - struct clk *dpll5_m2_clk; + struct clk_core *dpll5_clk; + struct clk_core *dpll5_m2_clk; - dpll5_clk = clk_get(NULL, "dpll5_ck"); - clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_prepare_enable(dpll5_clk); + dpll5_clk = clk_provider_get(NULL, "dpll5_ck"); + clk_provider_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); + clk_provider_prepare_enable(dpll5_clk); /* Program dpll5_m2_clk divider for no division */ - dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_prepare_enable(dpll5_m2_clk); - clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); + dpll5_m2_clk = clk_provider_get(NULL, "dpll5_m2_ck"); + clk_provider_prepare_enable(dpll5_m2_clk); + clk_provider_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - clk_disable_unprepare(dpll5_m2_clk); - clk_disable_unprepare(dpll5_clk); + clk_provider_disable_unprepare(dpll5_m2_clk); + clk_provider_disable_unprepare(dpll5_clk); return; } diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 78d9f56..063fbf1 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -12,8 +12,8 @@ int omap3xxx_clk_init(void); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); -extern struct clk *sdrc_ick_p; -extern struct clk *arm_fck_p; +extern struct clk_core *sdrc_ick_p; +extern struct clk_core *arm_fck_p; extern const struct clkops clkops_noncore_dpll_ops; diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index ef4d21b..31e3e79 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -119,7 +119,7 @@ const struct clksel_rate div31_1to31_rates[] = { static struct clk_ops dummy_ck_ops = {}; -struct clk dummy_ck = { +struct clk_core dummy_ck = { .name = "dummy_clk", .ops = &dummy_ck_ops, .flags = CLK_IS_BASIC, diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 2da3b5e..ce0971c 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1141,7 +1141,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) /** * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the enabled downstream clock + * @clk: struct clk_core * of the enabled downstream clock * * Increment the usecount of the clockdomain @clkdm and ensure that it * is awake before @clk is enabled. Intended to be called by @@ -1152,7 +1152,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) * by on-chip processors. Returns -EINVAL if passed null pointers; * returns 0 upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk) { /* * XXX Rewrite this code to maintain a list of enabled @@ -1168,7 +1168,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) /** * clkdm_clk_disable - remove an enabled downstream clock from this clkdm * @clkdm: struct clockdomain * - * @clk: struct clk * of the disabled downstream clock + * @clk: struct clk_core * of the disabled downstream clock * * Decrement the usecount of this clockdomain @clkdm when @clk is * disabled. Intended to be called by clk_disable() code. If the @@ -1178,7 +1178,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0 * upon success or if the clockdomain is in hwsup idle mode. */ -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk) { if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 82c37b1..f1a2cad 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -207,8 +207,8 @@ int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep_nolock(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); -int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk_core *clk); +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk_core *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 0f9e479..94b3232 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -524,7 +524,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_prepare_enable(oc->_clk); + clk_provider_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -551,7 +551,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_disable_unprepare(oc->_clk); + clk_provider_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37..9c70696 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -291,7 +291,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) /* * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @freqsel: FREQSEL value to set * * Program the DPLL with the last M, N values calculated, and wait for @@ -413,7 +413,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw) struct clk_hw_omap *clk = to_clk_hw_omap(hw); int r; struct dpll_data *dd; - struct clk *parent; + struct clk_core *parent; dd = clk->dpll_data; if (!dd) @@ -464,7 +464,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) /** * omap3_noncore_dpll_set_rate - set non-core DPLL rate - * @clk: struct clk * of DPLL to set + * @clk: struct clk_core * of DPLL to set * @rate: rounded target rate * * Set the DPLL CLKOUT to the target rate. If the DPLL can enter @@ -477,7 +477,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct clk *new_parent = NULL; + struct clk_core *new_parent = NULL; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -495,15 +495,15 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __func__, __clk_get_name(hw->clk)); __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); + clk_provider_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; - clk_disable(dd->clk_bypass); + clk_provider_disable(dd->clk_bypass); __clk_unprepare(dd->clk_bypass); } else { __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); + clk_provider_enable(dd->clk_ref); if (dd->last_rounded_rate != rate) rate = __clk_round_rate(hw->clk, rate); @@ -524,7 +524,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; - clk_disable(dd->clk_ref); + clk_provider_disable(dd->clk_ref); __clk_unprepare(dd->clk_ref); } /* @@ -534,7 +534,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, * stuff is inherited for free */ - if (!ret && clk_get_parent(hw->clk) != new_parent) + if (!ret && clk_provider_get_parent(hw->clk) != new_parent) __clk_reparent(hw->clk, new_parent); return 0; @@ -544,10 +544,10 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, /** * omap3_dpll_autoidle_read - read a DPLL's autoidle bits - * @clk: struct clk * of the DPLL to read + * @clk: struct clk_core * of the DPLL to read * * Return the DPLL's autoidle bits, shifted down to bit 0. Returns - * -EINVAL if passed a null pointer or if the struct clk does not + * -EINVAL if passed a null pointer or if the struct clk_core does not * appear to refer to a DPLL. */ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) @@ -572,7 +572,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) /** * omap3_dpll_allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Enable DPLL automatic idle control. This automatic idle mode * switching takes effect only when the DPLL is locked, at least on @@ -606,7 +606,7 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk) /** * omap3_dpll_deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on + * @clk: struct clk_core * of the DPLL to operate on * * Disable DPLL automatic idle control. No return value. */ @@ -636,7 +636,7 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk) static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) { struct clk_hw_omap *pclk = NULL; - struct clk *parent; + struct clk_core *parent; /* Walk up the parents of clk, looking for a DPLL */ do { diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 52f9438..0a09507 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -117,7 +117,7 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to compute the rate for + * @clk: struct clk_core * of the DPLL to compute the rate for * * Compute the output rate for the OMAP4 DPLL represented by @clk. * Takes the REGM4XEN bit into consideration, which is needed for the @@ -149,7 +149,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, /** * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to round a rate for + * @clk: struct clk_core * of the DPLL to round a rate for * @target_rate: the desired rate of the DPLL * * Compute the rate that would be programmed into the DPLL hardware diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index b4ac3af..e7ea6ba 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -34,7 +34,7 @@ #include "cm3xxx.h" #include "cm-regbits-34xx.h" -static struct clk *mcbsp_iclks[5]; +static struct clk_core *mcbsp_iclks[5]; static int omap3_enable_st_clock(unsigned int id, bool enable) { @@ -98,7 +98,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); pdata->enable_st_clock = omap3_enable_st_clock; sprintf(clk_name, "mcbsp%d_ick", id); - mcbsp_iclks[id] = clk_get(NULL, clk_name); + mcbsp_iclks[id] = clk_provider_get(NULL, clk_name); count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index fbe8cf0..350abb0 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -47,7 +47,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, const char *clk_name) { - struct clk *r; + struct clk_core *r; struct clk_lookup *l; if (!clk_alias || !clk_name) @@ -55,15 +55,15 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name); - r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); + r = clk_provider_get_sys(dev_name(&od->pdev->dev), clk_alias); if (!IS_ERR(r)) { dev_warn(&od->pdev->dev, "alias %s already exists\n", clk_alias); - clk_put(r); + __clk_put(r); return; } - r = clk_get(NULL, clk_name); + r = clk_provider_get(NULL, clk_name); if (IS_ERR(r)) { dev_err(&od->pdev->dev, "clk_get for %s failed\n", clk_name); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 6c074f3..67b6635 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -753,7 +753,7 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) } /** - * _init_main_clk - get a struct clk * for the the hwmod's main functional clk + * _init_main_clk - get a struct clk_core * for the the hwmod's main functional clk * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh _clk (main @@ -767,7 +767,7 @@ static int _init_main_clk(struct omap_hwmod *oh) if (!oh->main_clk) return 0; - oh->_clk = clk_get(NULL, oh->main_clk); + oh->_clk = clk_provider_get(NULL, oh->main_clk); if (IS_ERR(oh->_clk)) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", oh->name, oh->main_clk); @@ -781,7 +781,7 @@ static int _init_main_clk(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oh->_clk); + clk_provider_prepare(oh->_clk); if (!_get_clkdm(oh)) pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", @@ -791,7 +791,7 @@ static int _init_main_clk(struct omap_hwmod *oh) } /** - * _init_interface_clks - get a struct clk * for the the hwmod's interface clks + * _init_interface_clks - get a struct clk_core * for the the hwmod's interface clks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh OCP slave interface @@ -801,7 +801,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) { struct omap_hwmod_ocp_if *os; struct list_head *p; - struct clk *c; + struct clk_core *c; int i = 0; int ret = 0; @@ -812,7 +812,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) if (!os->clk) continue; - c = clk_get(NULL, os->clk); + c = clk_provider_get(NULL, os->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", oh->name, os->clk); @@ -828,14 +828,14 @@ static int _init_interface_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(os->_clk); + clk_provider_prepare(os->_clk); } return ret; } /** - * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks + * _init_opt_clk - get a struct clk_core * for the the hwmod's optional clocks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk @@ -844,12 +844,12 @@ static int _init_interface_clks(struct omap_hwmod *oh) static int _init_opt_clks(struct omap_hwmod *oh) { struct omap_hwmod_opt_clk *oc; - struct clk *c; + struct clk_core *c; int i; int ret = 0; for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { - c = clk_get(NULL, oc->clk); + c = clk_provider_get(NULL, oc->clk); if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", oh->name, oc->clk); @@ -865,7 +865,7 @@ static int _init_opt_clks(struct omap_hwmod *oh) * some point where subsystems like i2c and pmic become * available. */ - clk_prepare(oc->_clk); + clk_provider_prepare(oc->_clk); } return ret; @@ -887,7 +887,7 @@ static int _enable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); if (oh->_clk) - clk_enable(oh->_clk); + clk_provider_enable(oh->_clk); p = oh->slave_ports.next; @@ -895,7 +895,7 @@ static int _enable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -918,7 +918,7 @@ static int _disable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); if (oh->_clk) - clk_disable(oh->_clk); + clk_provider_disable(oh->_clk); p = oh->slave_ports.next; @@ -926,7 +926,7 @@ static int _disable_clocks(struct omap_hwmod *oh) os = _fetch_next_ocp_if(&p, &i); if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) - clk_disable(os->_clk); + clk_provider_disable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -945,7 +945,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_enable(oc->_clk); + clk_provider_enable(oc->_clk); } } @@ -960,7 +960,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) if (oc->_clk) { pr_debug("omap_hwmod: disable %s:%s\n", oc->role, __clk_get_name(oc->_clk)); - clk_disable(oc->_clk); + clk_provider_disable(oc->_clk); } } @@ -2585,7 +2585,7 @@ static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) /* XXX omap_iclk_deny_idle(c); */ } else { /* XXX omap_iclk_allow_idle(c); */ - clk_enable(os->_clk); + clk_provider_enable(os->_clk); } } @@ -3389,7 +3389,7 @@ static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) * Initialize and set up a single hwmod. Intended to be used for a * small number of early devices, such as the timer IP blocks used for * the scheduler clock. Must be called after omap2_clk_init(). - * Resolves the struct clk names to struct clk pointers for each + * Resolves the struct clk_core names to struct clk_core pointers for each * registered omap_hwmod. Also calls _setup() on each hwmod. Returns * -EINVAL upon error or 0 upon success. */ @@ -3418,7 +3418,7 @@ int __init omap_hwmod_setup_one(const char *oh_name) * * Initialize and set up all IP blocks registered with the hwmod code. * Must be called after omap2_clk_init(). Resolves the struct clk - * names to struct clk pointers for each registered omap_hwmod. Also + * names to struct clk_core pointers for each registered omap_hwmod. Also * calls _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) @@ -3785,7 +3785,7 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, */ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { - struct clk *c; + struct clk_core *c; struct omap_hwmod_ocp_if *oi; struct clockdomain *clkdm; struct clk_hw_omap *clk; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0f97d63..46ffd06 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -207,7 +207,7 @@ struct omap_hwmod_rst_info { * struct omap_hwmod_opt_clk - optional clocks used by this hwmod * @role: "sys", "32k", "tv", etc -- for use in clk_get() * @clk: opt clock: OMAP clock name - * @_clk: pointer to the struct clk (filled in at runtime) + * @_clk: pointer to the struct clk_core (filled in at runtime) * * The module's interface clock and main functional clock should not * be added as optional clocks. @@ -215,7 +215,7 @@ struct omap_hwmod_rst_info { struct omap_hwmod_opt_clk { const char *role; const char *clk; - struct clk *_clk; + struct clk_core *_clk; }; @@ -289,7 +289,7 @@ struct omap_hwmod_addr_space { * @slave: struct omap_hwmod that responds to OCP transactions on this link * @addr: address space associated with this link * @clk: interface clock: OMAP clock name - * @_clk: pointer to the interface struct clk (filled in at runtime) + * @_clk: pointer to the interface struct clk_core (filled in at runtime) * @fw: interface firewall data * @width: OCP data width * @user: initiators using this interface (see OCP_USER_* macros above) @@ -306,7 +306,7 @@ struct omap_hwmod_ocp_if { struct omap_hwmod *slave; struct omap_hwmod_addr_space *addr; const char *clk; - struct clk *_clk; + struct clk_core *_clk; union { struct omap_hwmod_omap2_firewall omap2; } fw; @@ -611,7 +611,7 @@ struct omap_hwmod_link { * @sdma_reqs: ptr to an array of System DMA request IDs * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name - * @_clk: pointer to the main struct clk (filled in at runtime) + * @_clk: pointer to the main struct clk_core (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @voltdm: pointer to voltage domain (filled in at runtime) * @dev_attr: arbitrary device attributes that can be passed to the driver @@ -653,7 +653,7 @@ struct omap_hwmod { struct omap_hwmod_omap4_prcm omap4; } prcm; const char *main_clk; - struct clk *_clk; + struct clk_core *_clk; struct omap_hwmod_opt_clk *opt_clks; char *clkdm_name; struct clockdomain *clkdm; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988..35633c5 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -60,7 +60,7 @@ static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, static struct powerdomain *mpu_pwrdm, *core_pwrdm; static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; -static struct clk *osc_ck, *emul_ck; +static struct clk_core *osc_ck, *emul_ck; static int omap2_enter_full_retention(void) { @@ -71,7 +71,7 @@ static int omap2_enter_full_retention(void) * oscillator itself it will be disabled if/when we enter retention * mode. */ - clk_disable(osc_ck); + clk_provider_disable(osc_ck); /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ @@ -101,7 +101,7 @@ static int omap2_enter_full_retention(void) no_sleep: omap2_gpio_resume_after_idle(); - clk_enable(osc_ck); + clk_provider_enable(osc_ck); /* clear CORE wake-up events */ omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); @@ -288,17 +288,17 @@ int __init omap2_pm_init(void) pr_err("PM: gfx_clkdm not found\n"); - osc_ck = clk_get(NULL, "osc_ck"); + osc_ck = clk_provider_get(NULL, "osc_ck"); if (IS_ERR(osc_ck)) { printk(KERN_ERR "could not get osc_ck\n"); return -ENODEV; } if (cpu_is_omap242x()) { - emul_ck = clk_get(NULL, "emul_ck"); + emul_ck = clk_provider_get(NULL, "emul_ck"); if (IS_ERR(emul_ck)) { printk(KERN_ERR "could not get emul_ck\n"); - clk_put(osc_ck); + __clk_put(osc_ck); return -ENODEV; } } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 6bbb7b5..6be2d2d 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -62,7 +62,7 @@ void __init orion5x_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ -static struct clk *tclk; +static struct clk_core *tclk; void __init clk_init(void) { diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 961b593..7bf2fe6 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -27,7 +27,7 @@ /* Create a clkdev entry for a given device/clk */ void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk) + struct clk_core *clk) { struct clk_lookup *cl; @@ -40,7 +40,7 @@ void __init orion_clkdev_add(const char *con_id, const char *dev_id, Kirkwood has gated clocks for some of its peripherals, so creates its own clkdev entries. For all the other orion devices, create clkdev entries to the tclk. */ -void __init orion_clkdev_init(struct clk *tclk) +void __init orion_clkdev_init(struct clk_core *tclk) { orion_clkdev_add(NULL, "orion_spi.0", tclk); orion_clkdev_add(NULL, "orion_spi.1", tclk); @@ -78,10 +78,10 @@ static void fill_resources(struct platform_device *device, /***************************************************************************** * UART ****************************************************************************/ -static unsigned long __init uart_get_clk_rate(struct clk *clk) +static unsigned long __init uart_get_clk_rate(struct clk_core *clk) { - clk_prepare_enable(clk); - return clk_get_rate(clk); + clk_provider_prepare_enable(clk); + return clk_provider_get_rate(clk); } static void __init uart_complete( @@ -91,7 +91,7 @@ static void __init uart_complete( void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { data->mapbase = mapbase; data->membase = membase; @@ -125,7 +125,7 @@ static struct platform_device orion_uart0 = { void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources, membase, mapbase, irq, clk); @@ -153,7 +153,7 @@ static struct platform_device orion_uart1 = { void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources, membase, mapbase, irq, clk); @@ -181,7 +181,7 @@ static struct platform_device orion_uart2 = { void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources, membase, mapbase, irq, clk); @@ -209,7 +209,7 @@ static struct platform_device orion_uart3 = { void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk) + struct clk_core *clk) { uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, membase, mapbase, irq, clk); diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index d9a24f6..44f1bbe 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -18,22 +18,22 @@ struct mv_sata_platform_data; void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, - struct clk *clk); + struct clk_core *clk); void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); @@ -107,7 +107,7 @@ void __init orion_crypto_init(unsigned long mapbase, unsigned long irq); void __init orion_clkdev_add(const char *con_id, const char *dev_id, - struct clk *clk); + struct clk_core *clk); -void __init orion_clkdev_init(struct clk *tclk); +void __init orion_clkdev_init(struct clk_core *tclk); #endif diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index 6eb614a..81afe83 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c @@ -70,7 +70,7 @@ enum { }; /* data required for the OF clock provider registration */ -static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; +static struct clk_core *clks[MPC512x_CLK_LAST_PRIVATE]; static struct clk_onecell_data clk_data; /* CCM register access */ @@ -218,12 +218,12 @@ static bool soc_has_mclk_mux0_canin(void) /* common clk API wrappers {{{ */ /* convenience wrappers around the common clk API */ -static inline struct clk *mpc512x_clk_fixed(const char *name, int rate) +static inline struct clk_core *mpc512x_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mpc512x_clk_factor( +static inline struct clk_core *mpc512x_clk_factor( const char *name, const char *parent_name, int mul, int div) { @@ -234,7 +234,7 @@ static inline struct clk *mpc512x_clk_factor( mul, div); } -static inline struct clk *mpc512x_clk_divider( +static inline struct clk_core *mpc512x_clk_divider( const char *name, const char *parent_name, u8 clkflags, u32 __iomem *reg, u8 pos, u8 len, int divflags) { @@ -242,7 +242,7 @@ static inline struct clk *mpc512x_clk_divider( reg, pos, len, divflags, &clklock); } -static inline struct clk *mpc512x_clk_divtable( +static inline struct clk_core *mpc512x_clk_divtable( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos, u8 len, const struct clk_div_table *divtab) @@ -255,7 +255,7 @@ static inline struct clk *mpc512x_clk_divtable( divtab, &clklock); } -static inline struct clk *mpc512x_clk_gated( +static inline struct clk_core *mpc512x_clk_gated( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos) { @@ -266,7 +266,7 @@ static inline struct clk *mpc512x_clk_gated( reg, pos, 0, &clklock); } -static inline struct clk *mpc512x_clk_muxed(const char *name, +static inline struct clk_core *mpc512x_clk_muxed(const char *name, const char **parent_names, int parent_count, u32 __iomem *reg, u8 pos, u8 len) { @@ -422,7 +422,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, int *sys_mul, int *sys_div, int *ips_div) { - struct clk *osc_clk; + struct clk_core *osc_clk; int calc_freq; /* fetch mul/div factors from the hardware */ @@ -432,7 +432,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, *ips_div = get_bit_field(&clkregs->scfr1, 23, 3); /* lookup the oscillator clock for its rate */ - osc_clk = of_clk_get_by_name(np, "osc"); + osc_clk = of_clk_provider_get_by_name(np, "osc"); /* * either descend from OSC to REF (and in bypassing verify the @@ -444,7 +444,7 @@ static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, */ if (!IS_ERR(osc_clk)) { clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); - calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); + calc_freq = clk_provider_get_rate(clks[MPC512x_CLK_REF]); calc_freq *= *sys_mul; calc_freq /= *sys_div; calc_freq /= 2; @@ -647,8 +647,8 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx) * - MCLK 0 enabled * - MCLK 1 from MCLK DIV */ - div = clk_get_rate(clks[MPC512x_CLK_SYS]); - div /= clk_get_rate(clks[MPC512x_CLK_IPS]); + div = clk_provider_get_rate(clks[MPC512x_CLK_SYS]); + div /= clk_provider_get_rate(clks[MPC512x_CLK_IPS]); out_be32(mccr_reg, (0 << 16)); out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17)); out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17)); @@ -925,12 +925,12 @@ static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq) * claimed by any peripheral driver, to not have the clock * subsystem disable them late at startup */ - clk_prepare_enable(clks[MPC512x_CLK_DUMMY]); - clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ - clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ - clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ - clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ - clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DUMMY]); + clk_provider_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ + clk_provider_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ + clk_provider_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ + clk_provider_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ } /* @@ -969,9 +969,9 @@ static void mpc5121_clk_provide_migration_support(void) * has attached to bridges, otherwise the PCI clock remains * unused and so it gets disabled */ - clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ + clk_provider_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci")) - clk_prepare_enable(clks[MPC512x_CLK_PCI]); + clk_provider_prepare_enable(clks[MPC512x_CLK_PCI]); } /* @@ -988,8 +988,8 @@ static void mpc5121_clk_provide_migration_support(void) } while (0) #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \ - struct clk *clk; \ - clk = of_clk_get_by_name(np, clkname); \ + struct clk_core *clk; \ + clk = of_clk_provider_get_by_name(np, clkname); \ if (IS_ERR(clk)) { \ clk = clkitem; \ clk_register_clkdev(clk, clkname, devname); \ @@ -999,7 +999,7 @@ static void mpc5121_clk_provide_migration_support(void) pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \ clkname, devname, clk); \ } else { \ - clk_put(clk); \ + __clk_put(clk); \ } \ } while (0) @@ -1090,7 +1090,7 @@ static void mpc5121_clk_provide_backwards_compat(void) * workaround obsolete */ if (did_register & DID_REG_I2C) - clk_prepare_enable(clks[MPC512x_CLK_I2C]); + clk_provider_prepare_enable(clks[MPC512x_CLK_I2C]); FOR_NODES("fsl,mpc5121-diu") { NODE_PREP; diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 7333061..939c4b7 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -138,7 +138,7 @@ static const struct clk_ops main_osc_ops = { .is_prepared = clk_main_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -147,7 +147,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, { int ret; struct clk_main_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !parent_name) @@ -192,7 +192,7 @@ at91_clk_register_main_osc(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; const char *name = np->name; const char *parent_name; @@ -291,7 +291,7 @@ static const struct clk_ops main_rc_osc_ops = { .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_main_rc_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -299,7 +299,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, { int ret; struct clk_main_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !frequency) @@ -340,7 +340,7 @@ at91_clk_register_main_rc_osc(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; unsigned int irq; u32 frequency = 0; u32 accuracy = 0; @@ -423,13 +423,13 @@ static const struct clk_ops rm9200_main_ops = { .recalc_rate = clk_rm9200_main_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_rm9200_main(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_rm9200_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -461,7 +461,7 @@ at91_clk_register_rm9200_main(struct at91_pmc *pmc, void __init of_at91rm9200_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -554,7 +554,7 @@ static const struct clk_ops sam9x5_main_ops = { .get_parent = clk_sam9x5_main_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_main(struct at91_pmc *pmc, unsigned int irq, const char *name, @@ -563,7 +563,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, { int ret; struct clk_sam9x5_main *clkmain; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name) @@ -606,7 +606,7 @@ at91_clk_register_sam9x5_main(struct at91_pmc *pmc, void __init of_at91sam9x5_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; unsigned int irq; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index c1af80b..95ae1b6 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -131,7 +131,7 @@ static const struct clk_ops master_ops = { .get_parent = clk_master_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, const char *name, int num_parents, const char **parent_names, @@ -140,7 +140,7 @@ at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, { int ret; struct clk_master *master; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !irq || !name || !num_parents || !parent_names) @@ -216,7 +216,7 @@ static void __init of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc, const struct clk_master_layout *layout) { - struct clk *clk; + struct clk_core *clk; int num_parents; int i; unsigned int irq; diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 597fed4..cdf8e8a 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -100,12 +100,12 @@ static const struct clk_ops peripheral_ops = { .is_enabled = clk_peripheral_is_enabled, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id) { struct clk_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX) @@ -134,7 +134,7 @@ at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) { - struct clk *parent; + struct clk_core *parent; unsigned long parent_rate; int shift = 0; @@ -309,13 +309,13 @@ static const struct clk_ops sam9x5_peripheral_ops = { .set_rate = clk_sam9x5_peripheral_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id, const struct clk_range *range) { struct clk_sam9x5_peripheral *periph; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name || !parent_name) @@ -352,7 +352,7 @@ of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type) { int num; u32 id; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name; struct device_node *periphclknp; diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index cf6ed02..0d22f65f 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -297,14 +297,14 @@ static const struct clk_ops pll_ops = { .set_rate = clk_pll_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; int offset = PLL_REG(id); @@ -474,7 +474,7 @@ of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc, { u32 id; unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; struct clk_pll_characteristics *characteristics; diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index ea22656..f8204d8 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -79,12 +79,12 @@ static const struct clk_ops plldiv_ops = { .set_rate = clk_plldiv_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct clk_plldiv *plldiv; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); @@ -111,7 +111,7 @@ at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, static void __init of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 62e2509..b72e98c 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -57,9 +57,9 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, static long clk_programmable_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { - struct clk *parent = NULL; + struct clk_core *parent = NULL; long best_rate = -EINVAL; unsigned long parent_rate; unsigned long tmp_rate; @@ -169,14 +169,14 @@ static const struct clk_ops programmable_ops = { .set_rate = clk_programmable_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_programmable(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout) { struct clk_programmable *prog; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (id > PROG_ID_MAX) @@ -229,7 +229,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc, int num; u32 id; int i; - struct clk *clk; + struct clk_core *clk; int num_parents; const char *parent_names[PROG_SOURCE_MAX]; const char *name; diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index 0300c46..d50fe02 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -117,7 +117,7 @@ static const struct clk_ops slow_osc_ops = { .is_prepared = clk_slow_osc_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const char *parent_name, @@ -125,7 +125,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, bool bypass) { struct clk_slow_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_name) @@ -159,7 +159,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 startup; @@ -229,7 +229,7 @@ static const struct clk_ops slow_rc_osc_ops = { .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_slow_rc_osc(void __iomem *sckcr, const char *name, unsigned long frequency, @@ -237,7 +237,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, unsigned long startup) { struct clk_slow_rc_osc *osc; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name) @@ -269,7 +269,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; u32 frequency = 0; u32 accuracy = 0; u32 startup = 0; @@ -327,14 +327,14 @@ static const struct clk_ops sam9x5_slow_ops = { .get_parent = clk_sam9x5_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9x5_slow(void __iomem *sckcr, const char *name, const char **parent_names, int num_parents) { struct clk_sam9x5_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!sckcr || !name || !parent_names || !num_parents) @@ -364,7 +364,7 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, void __init of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; @@ -401,14 +401,14 @@ static const struct clk_ops sam9260_slow_ops = { .get_parent = clk_sam9260_slow_get_parent, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_sam9260_slow(struct at91_pmc *pmc, const char *name, const char **parent_names, int num_parents) { struct clk_sam9260_slow *slowck; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; if (!pmc || !name) @@ -440,7 +440,7 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc, void __init of_at91sam9260_clk_slow_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index 144d47e..8820b84 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -113,12 +113,12 @@ static const struct clk_ops at91sam9x5_smd_ops = { .set_rate = at91sam9x5_clk_smd_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_smd *smd; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; smd = kzalloc(sizeof(*smd), GFP_KERNEL); @@ -144,7 +144,7 @@ at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[SMD_SOURCE_MAX]; diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 8c96307..770d9bf 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -99,12 +99,12 @@ static const struct clk_ops system_ops = { .is_prepared = clk_system_is_prepared, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_system(struct at91_pmc *pmc, const char *name, const char *parent_name, u8 id, int irq) { struct clk_system *sys; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; int ret; @@ -153,7 +153,7 @@ of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc) int num; int irq = 0; u32 id; - struct clk *clk; + struct clk_core *clk; const char *name; struct device_node *sysclknp; const char *parent_name; diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 7d1d26a..246989c 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -162,12 +162,12 @@ static const struct clk_ops at91sam9n12_usb_ops = { .set_rate = at91sam9x5_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -190,12 +190,12 @@ at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, return clk; } -static struct clk * __init +static struct clk_core * __init at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name) { struct at91sam9x5_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -295,12 +295,12 @@ static const struct clk_ops at91rm9200_usb_ops = { .set_rate = at91rm9200_clk_usb_set_rate, }; -static struct clk * __init +static struct clk_core * __init at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, const char *parent_name, const u32 *divisors) { struct at91rm9200_clk_usb *usb; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; usb = kzalloc(sizeof(*usb), GFP_KERNEL); @@ -327,7 +327,7 @@ at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; int i; int num_parents; const char *parent_names[USB_SOURCE_MAX]; @@ -355,7 +355,7 @@ void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; @@ -375,7 +375,7 @@ void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, void __init of_at91rm9200_clk_usb_setup(struct device_node *np, struct at91_pmc *pmc) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; u32 divisors[4] = {0, 0, 0, 0}; diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index ae3263b..0502050 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -92,13 +92,13 @@ static const struct clk_ops utmi_ops = { .recalc_rate = clk_utmi_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name) { int ret; struct clk_utmi *utmi; - struct clk *clk = NULL; + struct clk_core *clk = NULL; struct clk_init_data init; utmi = kzalloc(sizeof(*utmi), GFP_KERNEL); @@ -132,7 +132,7 @@ static void __init of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc) { unsigned int irq; - struct clk *clk; + struct clk_core *clk; const char *parent_name; const char *name = np->name; diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c index e5aeded..122e7b0 100644 --- a/drivers/clk/bcm/clk-kona-setup.c +++ b/drivers/clk/bcm/clk-kona-setup.c @@ -697,7 +697,7 @@ static void bcm_clk_teardown(struct kona_clk *bcm_clk) bcm_clk->type = bcm_clk_none; } -static void kona_clk_teardown(struct clk *clk) +static void kona_clk_teardown(struct clk_core *clk) { struct clk_hw *hw; struct kona_clk *bcm_clk; @@ -716,10 +716,10 @@ static void kona_clk_teardown(struct clk *clk) bcm_clk_teardown(bcm_clk); } -struct clk *kona_clk_setup(struct kona_clk *bcm_clk) +struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk) { struct clk_init_data *init_data = &bcm_clk->init_data; - struct clk *clk = NULL; + struct clk_core *clk = NULL; switch (bcm_clk->type) { case bcm_clk_peri: diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c index 95af2e6..a301aa9 100644 --- a/drivers/clk/bcm/clk-kona.c +++ b/drivers/clk/bcm/clk-kona.c @@ -1032,11 +1032,11 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate, } static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *best_parent_rate, struct clk **best_parent) + unsigned long *best_parent_rate, struct clk_core **best_parent) { struct kona_clk *bcm_clk = to_kona_clk(hw); - struct clk *clk = hw->clk; - struct clk *current_parent; + struct clk_core *clk = hw->clk; + struct clk_core *current_parent; unsigned long parent_rate; unsigned long best_delta; unsigned long best_rate; @@ -1053,14 +1053,14 @@ static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, return kona_peri_clk_round_rate(hw, rate, best_parent_rate); /* Unless we can do better, stick with current parent */ - current_parent = clk_get_parent(clk); + current_parent = clk_provider_get_parent(clk); parent_rate = __clk_get_rate(current_parent); best_rate = kona_peri_clk_round_rate(hw, rate, &parent_rate); best_delta = abs(best_rate - rate); /* Check whether any other parent clock can produce a better result */ for (which = 0; which < parent_count; which++) { - struct clk *parent = clk_get_parent_by_index(clk, which); + struct clk_core *parent = clk_get_parent_by_index(clk, which); unsigned long delta; unsigned long other_rate; @@ -1260,7 +1260,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu) { unsigned long flags; unsigned int which; - struct clk **clks = ccu->clk_data.clks; + struct clk_core **clks = ccu->clk_data.clks; bool success = true; flags = ccu_lock(ccu); diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h index 2537b30..c2d0152 100644 --- a/drivers/clk/bcm/clk-kona.h +++ b/drivers/clk/bcm/clk-kona.h @@ -508,7 +508,7 @@ extern u64 scaled_div_max(struct bcm_clk_div *div); extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths); -extern struct clk *kona_clk_setup(struct kona_clk *bcm_clk); +extern struct clk_core *kona_clk_setup(struct kona_clk *bcm_clk); extern void __init kona_dt_ccu_setup(struct ccu_data *ccu, struct device_node *node); extern bool __init kona_ccu_init(struct ccu_data *ccu); diff --git a/drivers/clk/berlin/berlin2-avpll.c b/drivers/clk/berlin/berlin2-avpll.c index fd0f26c..488d986 100644 --- a/drivers/clk/berlin/berlin2-avpll.c +++ b/drivers/clk/berlin/berlin2-avpll.c @@ -188,7 +188,7 @@ static const struct clk_ops berlin2_avpll_vco_ops = { .recalc_rate = berlin2_avpll_vco_recalc_rate, }; -struct clk * __init berlin2_avpll_vco_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags) { @@ -364,7 +364,7 @@ static const struct clk_ops berlin2_avpll_channel_ops = { */ static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 }; -struct clk * __init berlin2_avpll_channel_register(void __iomem *base, +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags) { diff --git a/drivers/clk/berlin/berlin2-avpll.h b/drivers/clk/berlin/berlin2-avpll.h index a37f506..216eee7 100644 --- a/drivers/clk/berlin/berlin2-avpll.h +++ b/drivers/clk/berlin/berlin2-avpll.h @@ -24,11 +24,11 @@ struct clk; #define BERLIN2_AVPLL_BIT_QUIRK BIT(0) #define BERLIN2_AVPLL_SCRAMBLE_QUIRK BIT(1) -struct clk * __init +struct clk_core * __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags); -struct clk * __init +struct clk_core * __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags); diff --git a/drivers/clk/berlin/berlin2-div.c b/drivers/clk/berlin/berlin2-div.c index 81ff97f..c673082 100644 --- a/drivers/clk/berlin/berlin2-div.c +++ b/drivers/clk/berlin/berlin2-div.c @@ -234,7 +234,7 @@ static const struct clk_ops berlin2_div_mux_ops = { .get_parent = berlin2_div_get_parent, }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-div.h b/drivers/clk/berlin/berlin2-div.h index 15e3384..3ddb87a 100644 --- a/drivers/clk/berlin/berlin2-div.h +++ b/drivers/clk/berlin/berlin2-div.h @@ -80,7 +80,7 @@ struct berlin2_div_data { u8 div_flags; }; -struct clk * __init +struct clk_core * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, diff --git a/drivers/clk/berlin/berlin2-pll.c b/drivers/clk/berlin/berlin2-pll.c index bdc506b..b7a3016 100644 --- a/drivers/clk/berlin/berlin2-pll.c +++ b/drivers/clk/berlin/berlin2-pll.c @@ -91,7 +91,7 @@ static const struct clk_ops berlin2_pll_ops = { .recalc_rate = berlin2_pll_recalc_rate, }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags) diff --git a/drivers/clk/berlin/berlin2-pll.h b/drivers/clk/berlin/berlin2-pll.h index 8831ce2..6b6a6ed 100644 --- a/drivers/clk/berlin/berlin2-pll.h +++ b/drivers/clk/berlin/berlin2-pll.h @@ -29,7 +29,7 @@ struct berlin2_pll_map { u8 divsel_shift; }; -struct clk * __init +struct clk_core * __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags); diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c index 4c81e09..1329721 100644 --- a/drivers/clk/berlin/bg2.c +++ b/drivers/clk/berlin/bg2.c @@ -93,7 +93,7 @@ */ #define MAX_CLKS 41 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -504,7 +504,7 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = { static void __init berlin2_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; u8 avpll_flags = 0; int n; @@ -513,16 +513,16 @@ static void __init berlin2_clock_setup(struct device_node *np) return; /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } - clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]); + clk = of_clk_provider_get_by_name(np, clk_names[VIDEO_EXT0]); if (!IS_ERR(clk)) { clk_names[VIDEO_EXT0] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c index 748da9b..0b251bd 100644 --- a/drivers/clk/berlin/bg2q.c +++ b/drivers/clk/berlin/bg2q.c @@ -47,7 +47,7 @@ #define REG_SDIO1XIN_CLKCTL 0x015c #define MAX_CLKS 27 -static struct clk *clks[MAX_CLKS]; +static struct clk_core *clks[MAX_CLKS]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; @@ -293,7 +293,7 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = { static void __init berlin2q_clock_setup(struct device_node *np) { const char *parent_names[9]; - struct clk *clk; + struct clk_core *clk; int n; gbase = of_iomap(np, 0); @@ -311,10 +311,10 @@ static void __init berlin2q_clock_setup(struct device_node *np) } /* overwrite default clock names with DT provided ones */ - clk = of_clk_get_by_name(np, clk_names[REFCLK]); + clk = of_clk_provider_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } /* simple register PLLs */ diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 1127ee4..4b64834 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -489,7 +489,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) const char *parent_name; const char *clk_name; struct resource *mem; - struct clk *clk; + struct clk_core *clk; if (!pdev->dev.of_node) return -ENODEV; diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c index d2f1e11..3dc6e58 100644 --- a/drivers/clk/clk-axm5516.c +++ b/drivers/clk/clk-axm5516.c @@ -532,7 +532,7 @@ MODULE_DEVICE_TABLE(of, axmclk_match_table); struct axmclk_priv { struct clk_onecell_data onecell; - struct clk *clks[]; + struct clk_core *clks[]; }; static int axmclk_probe(struct platform_device *pdev) @@ -541,7 +541,7 @@ static int axmclk_probe(struct platform_device *pdev) struct resource *res; int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct regmap *regmap; size_t num_clks; struct axmclk_priv *priv; diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c index 6b950ca..f25e85e 100644 --- a/drivers/clk/clk-bcm2835.c +++ b/drivers/clk/clk-bcm2835.c @@ -29,7 +29,7 @@ */ void __init bcm2835_init_clocks(void) { - struct clk *clk; + struct clk_core *clk; int ret; clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT, diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 57a078e..e505693 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -57,7 +57,7 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_composite *composite = to_clk_composite(hw); const struct clk_ops *rate_ops = composite->rate_ops; @@ -136,14 +136,14 @@ static void clk_composite_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } -struct clk *clk_register_composite(struct device *dev, const char *name, +struct clk_core *clk_register_composite(struct device *dev, const char *name, const char **parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct clk_composite *composite; struct clk_ops *clk_composite_ops; diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 18a9de2..3c78139 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -366,14 +366,14 @@ const struct clk_ops clk_divider_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_divider_ro_ops); -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -429,7 +429,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_divider(struct device *dev, const char *name, +struct clk_core *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock) @@ -453,7 +453,7 @@ EXPORT_SYMBOL_GPL(clk_register_divider); * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ -struct clk *clk_register_divider_table(struct device *dev, const char *name, +struct clk_core *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c index bac2ddf..26e0485 100644 --- a/drivers/clk/clk-efm32gg.c +++ b/drivers/clk/clk-efm32gg.c @@ -16,7 +16,7 @@ #define CMU_HFPERCLKEN0 0x44 -static struct clk *clk[37]; +static struct clk_core *clk[37]; static struct clk_onecell_data clk_data = { .clks = clk, .clk_num = ARRAY_SIZE(clk), diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index d9e3f67..ae1fef0 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -65,13 +65,13 @@ struct clk_ops clk_fixed_factor_ops = { }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { struct clk_fixed_factor *fix; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fix = kmalloc(sizeof(*fix), GFP_KERNEL); if (!fix) { @@ -105,7 +105,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_factor); */ void __init of_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index 0fc56ab..56c0ced 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -56,12 +56,12 @@ EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, +struct clk_core *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy) { struct clk_fixed_rate *fixed; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate fixed-rate clock */ @@ -99,7 +99,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy); * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */ -struct clk *clk_register_fixed_rate(struct device *dev, const char *name, +struct clk_core *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate) { @@ -114,7 +114,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate); */ void of_fixed_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; u32 rate; u32 accuracy = 0; diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index ede685c..8104683 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -96,14 +96,14 @@ const struct clk_ops clk_fractional_divider_ops = { }; EXPORT_SYMBOL_GPL(clk_fractional_divider_ops); -struct clk *clk_register_fractional_divider(struct device *dev, +struct clk_core *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock) { struct clk_fractional_divider *fd; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; fd = kzalloc(sizeof(*fd), GFP_KERNEL); if (!fd) { diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 4a58c55..429d302 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -118,13 +118,13 @@ EXPORT_SYMBOL_GPL(clk_gate_ops); * @clk_gate_flags: gate-specific flags for this clock * @lock: shared register lock for this clock */ -struct clk *clk_register_gate(struct device *dev, const char *name, +struct clk_core *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clk_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 2e7e9d9..cad2fba 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -271,10 +271,10 @@ static const struct clk_ops periclk_ops = { .set_rate = clk_periclk_set_rate, }; -static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops) +static __init struct clk_core *hb_clk_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct hb_clk *hb_clk; const char *clk_name = node->name; const char *parent_name; @@ -330,8 +330,8 @@ CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init); static void __init hb_a9bus_init(struct device_node *node) { - struct clk *clk = hb_clk_init(node, &a9bclk_ops); - clk_prepare_enable(clk); + struct clk_core *clk = hb_clk_init(node, &a9bclk_ops); + clk_provider_prepare_enable(clk); } CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init); diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c index f20b750..796043c 100644 --- a/drivers/clk/clk-ls1x.c +++ b/drivers/clk/clk-ls1x.c @@ -48,11 +48,11 @@ static const struct clk_ops ls1x_pll_clk_ops = { .recalc_rate = ls1x_pll_recalc_rate, }; -static struct clk * __init clk_register_pll(struct device *dev, +static struct clk_core * __init clk_register_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags) { struct clk_hw *hw; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the divider */ @@ -80,32 +80,32 @@ static struct clk * __init clk_register_pll(struct device *dev, void __init ls1x_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk = clk_register_divider(NULL, "cpu_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT, DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "cpu", NULL); clk = clk_register_divider(NULL, "dc_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "dc", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll_clk", CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "ahb", NULL); clk_register_clkdev(clk, "stmmaceth", NULL); clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2); - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); clk_register_clkdev(clk, "apb", NULL); clk_register_clkdev(clk, "serial8250", NULL); } diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 3d7e8dd..42fa43a 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -112,10 +112,10 @@ static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = { }, }; -static struct clk *max77686_clk_register(struct device *dev, +static struct clk_core *max77686_clk_register(struct device *dev, struct max77686_clk *max77686) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *hw = &max77686->hw; clk = clk_register(dev, hw); @@ -138,10 +138,10 @@ static int max77686_clk_probe(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct max77686_clk *max77686_clks[MAX77686_CLKS_NUM]; - struct clk **clocks; + struct clk_core **clocks; int i, ret; - clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk *) + clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * MAX77686_CLKS_NUM, GFP_KERNEL); if (!clocks) return -ENOMEM; @@ -203,7 +203,7 @@ err_clocks: static int max77686_clk_remove(struct platform_device *pdev) { struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); - struct clk **clocks = platform_get_drvdata(pdev); + struct clk_core **clocks = platform_get_drvdata(pdev); int i; if (iodev->dev->of_node) diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c index 30a3b69..c503c09 100644 --- a/drivers/clk/clk-moxart.c +++ b/drivers/clk/clk-moxart.c @@ -18,7 +18,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *ref_clk; + struct clk_core *clk, *ref_clk; unsigned int mul; const char *name = node->name; const char *parent_name; @@ -35,7 +35,7 @@ void __init moxart_of_pll_clk_init(struct device_node *node) mul = readl(base + 0x30) >> 3 & 0x3f; iounmap(base); - ref_clk = of_clk_get(node, 0); + ref_clk = of_clk_provider_get(node, 0); if (IS_ERR(ref_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; @@ -56,7 +56,7 @@ CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock", void __init moxart_of_apb_clk_init(struct device_node *node) { static void __iomem *base; - struct clk *clk, *pll_clk; + struct clk_core *clk, *pll_clk; unsigned int div, val; unsigned int div_idx[] = { 2, 3, 4, 6, 8}; const char *name = node->name; @@ -78,7 +78,7 @@ void __init moxart_of_apb_clk_init(struct device_node *node) val = 0; div = div_idx[val] * 2; - pll_clk = of_clk_get(node, 0); + pll_clk = of_clk_provider_get(node, 0); if (IS_ERR(pll_clk)) { pr_err("%s: of_clk_get failed\n", node->full_name); return; diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 4f96ff3..2879053 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -113,13 +113,13 @@ const struct clk_ops clk_mux_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_mux_ro_ops); -struct clk *clk_register_mux_table(struct device *dev, const char *name, +struct clk_core *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; u8 width = 0; @@ -165,7 +165,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, } EXPORT_SYMBOL_GPL(clk_register_mux_table); -struct clk *clk_register_mux(struct device *dev, const char *name, +struct clk_core *clk_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock) diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 05e04ce..5d87366 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -254,11 +254,11 @@ static const struct clk_ops pll_clk_ops = { .recalc_rate = pll_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init pll_clk_register(struct device *dev, const char *name, const char *parent_name, u32 id) { - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll; struct clk_init_data init; @@ -346,11 +346,11 @@ static const struct clk_ops src_clk_ops = { .recalc_rate = src_clk_recalc_rate, }; -static struct clk * __init +static struct clk_core * __init src_clk_register(struct device *dev, const char *name, const char *parent_name, u8 id) { - struct clk *clk; + struct clk_core *clk; struct clk_src *sclk; struct clk_init_data init; @@ -510,7 +510,7 @@ module_init(nomadik_src_clk_init_debugfs); static void __init of_nomadik_pll_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 pll_id; @@ -533,7 +533,7 @@ CLK_OF_DECLARE(nomadik_pll_clk, static void __init of_nomadik_hclk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; @@ -557,7 +557,7 @@ CLK_OF_DECLARE(nomadik_hclk_clk, static void __init of_nomadik_src_clk_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; u32 clk_id; diff --git a/drivers/clk/clk-nspire.c b/drivers/clk/clk-nspire.c index a378db7..e9c43f4 100644 --- a/drivers/clk/clk-nspire.c +++ b/drivers/clk/clk-nspire.c @@ -69,7 +69,7 @@ static void __init nspire_ahbdiv_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; struct nspire_clk_info info; @@ -111,7 +111,7 @@ static void __init nspire_clk_setup(struct device_node *node, { u32 val; void __iomem *io; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct nspire_clk_info info; diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c index 8b284be..b82e7f0 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-ppc-corenet.c @@ -64,7 +64,7 @@ const struct clk_ops cmux_ops = { static void __init core_mux_init(struct device_node *np) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct cmux_clk *cmux_clk; struct device_node *node; @@ -150,7 +150,7 @@ static void __init core_pll_init(struct device_node *np) int i, rc, count; const char *clk_name, *parent_name; struct clk_onecell_data *onecell_data; - struct clk **subclks; + struct clk_core **subclks; void __iomem *base; base = of_iomap(np, 0); @@ -184,7 +184,7 @@ static void __init core_pll_init(struct device_node *np) /* output clock number per PLL */ clocks_per_pll = count; - subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); + subclks = kzalloc(sizeof(struct clk_core *) * count, GFP_KERNEL); if (!subclks) { pr_err("%s: could not allocate subclks\n", __func__); goto err_map; @@ -246,7 +246,7 @@ err_map: static void __init sysclk_init(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; struct device_node *np = of_get_parent(node); u32 rate; diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index 3757e9e..f0da3d9 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -29,7 +29,7 @@ #define s2mps11_name(a) (a->hw.init->name) -static struct clk **clk_table; +static struct clk_core **clk_table; static struct clk_onecell_data clk_data; enum { @@ -43,7 +43,7 @@ struct s2mps11_clk { struct sec_pmic_dev *iodev; struct device_node *clk_np; struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_lookup *lookup; u32 mask; bool enabled; @@ -178,7 +178,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev) s2mps11_clk = s2mps11_clks; - clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk *) * + clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk_core *) * S2MPS11_CLKS_NUM, GFP_KERNEL); if (!clk_table) return -ENOMEM; diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 3b2a66f..57c9eb5 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -56,10 +56,10 @@ struct si5351_driver_data { struct regmap *regmap; struct clk_onecell_data onecell; - struct clk *pxtal; + struct clk_core *pxtal; const char *pxtal_name; struct clk_hw xtal; - struct clk *pclkin; + struct clk_core *pclkin; const char *pclkin_name; struct clk_hw clkin; @@ -1128,12 +1128,12 @@ static int si5351_dt_parse(struct i2c_client *client, if (!pdata) return -ENOMEM; - pdata->clk_xtal = of_clk_get(np, 0); + pdata->clk_xtal = of_clk_provider_get(np, 0); if (!IS_ERR(pdata->clk_xtal)) - clk_put(pdata->clk_xtal); - pdata->clk_clkin = of_clk_get(np, 1); + __clk_put(pdata->clk_xtal); + pdata->clk_clkin = of_clk_provider_get(np, 1); if (!IS_ERR(pdata->clk_clkin)) - clk_put(pdata->clk_clkin); + __clk_put(pdata->clk_clkin); /* * property silabs,pll-source : <num src>, [<..>] @@ -1306,7 +1306,7 @@ static int si5351_i2c_probe(struct i2c_client *client, struct si5351_platform_data *pdata; struct si5351_driver_data *drvdata; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; const char *parent_names[4]; u8 num_parents, num_clocks; int ret, n; @@ -1545,7 +1545,8 @@ static int si5351_i2c_probe(struct i2c_client *client, /* set initial clkout rate */ if (pdata->clkout[n].rate != 0) { int ret; - ret = clk_set_rate(clk, pdata->clkout[n].rate); + ret = clk_provider_set_rate(clk, + pdata->clkout[n].rate); if (ret != 0) { dev_err(&client->dev, "Cannot set rate : %d\n", ret); diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c index fc167b3..f0eec4e 100644 --- a/drivers/clk/clk-si570.c +++ b/drivers/clk/clk-si570.c @@ -407,7 +407,7 @@ static int si570_probe(struct i2c_client *client, { struct clk_si570 *data; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; u32 initial_fout, factory_fout, stability; int err; enum clk_si570_variant variant = id->driver_data; @@ -476,7 +476,7 @@ static int si570_probe(struct i2c_client *client, /* Read the requested initial output frequency from device tree */ if (!of_property_read_u32(client->dev.of_node, "clock-frequency", &initial_fout)) { - err = clk_set_rate(clk, initial_fout); + err = clk_provider_set_rate(clk, initial_fout); if (err) { of_clk_del_provider(client->dev.of_node); return err; diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c index 1ada79a..2422857 100644 --- a/drivers/clk/clk-twl6040.c +++ b/drivers/clk/clk-twl6040.c @@ -31,7 +31,7 @@ struct twl6040_clk { struct twl6040 *twl6040; struct device *dev; struct clk_hw mcpdm_fclk; - struct clk *clk; + struct clk_core *clk; int enabled; }; diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index 406bfc1..7e9ec00 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -688,7 +688,7 @@ static const struct clk_ops syscon_clk_ops = { .set_rate = syscon_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init syscon_clk_register(struct device *dev, const char *name, const char *parent_name, unsigned long flags, bool hw_ctrld, @@ -696,7 +696,7 @@ syscon_clk_register(struct device *dev, const char *name, void __iomem *en_reg, u8 en_bit, u16 clk_val) { - struct clk *clk; + struct clk_core *clk; struct clk_syscon *sclk; struct clk_init_data init; @@ -867,7 +867,7 @@ static struct u300_clock const u300_clk_lookup[] __initconst = { static void __init of_u300_syscon_clk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; void __iomem *res_reg; @@ -1110,11 +1110,11 @@ static const struct clk_ops mclk_ops = { .set_rate = mclk_clk_set_rate, }; -static struct clk * __init +static struct clk_core * __init mclk_clk_register(struct device *dev, const char *name, const char *parent_name, bool is_mspro) { - struct clk *clk; + struct clk_core *clk; struct clk_mclk *mclk; struct clk_init_data init; @@ -1141,7 +1141,7 @@ mclk_clk_register(struct device *dev, const char *name, static void __init of_u300_syscon_mclk_init(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const char *parent_name; diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index 37e9288..e5fb933 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -232,7 +232,7 @@ static const struct clk_ops vt8500_gated_divisor_clk_ops = { static __init void vtwm_device_clk_init(struct device_node *node) { u32 en_reg, div_reg; - struct clk *clk; + struct clk_core *clk; struct clk_device *dev_clk; const char *clk_name = node->name; const char *parent_name; @@ -650,7 +650,7 @@ static const struct clk_ops vtwm_pll_ops = { static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct clk_pll *pll_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c index b131041..d2d745e 100644 --- a/drivers/clk/clk-wm831x.c +++ b/drivers/clk/clk-wm831x.c @@ -25,9 +25,9 @@ struct wm831x_clk { struct clk_hw xtal_hw; struct clk_hw fll_hw; struct clk_hw clkout_hw; - struct clk *xtal; - struct clk *fll; - struct clk *clkout; + struct clk_core *xtal; + struct clk_core *fll; + struct clk_core *clkout; bool xtal_ena; }; diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index dd8a62d..ce3ed34 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -124,13 +124,13 @@ const struct clk_ops xgene_clk_pll_ops = { .recalc_rate = xgene_clk_pll_recalc_rate, }; -static struct clk *xgene_register_clk_pll(struct device *dev, +static struct clk_core *xgene_register_clk_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 pll_offset, u32 type, spinlock_t *lock) { struct xgene_clk_pll *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the APM clock structure */ @@ -166,7 +166,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev, static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; void *reg; reg = of_iomap(np, 0); @@ -395,12 +395,12 @@ const struct clk_ops xgene_clk_ops = { .round_rate = xgene_clk_round_rate, }; -static struct clk *xgene_register_clk(struct device *dev, +static struct clk_core *xgene_register_clk(struct device *dev, const char *name, const char *parent_name, struct xgene_dev_parameters *parameters, spinlock_t *lock) { struct xgene_clk *apmclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int rc; @@ -442,7 +442,7 @@ static struct clk *xgene_register_clk(struct device *dev, static void __init xgene_devclk_init(struct device_node *np) { const char *clk_name = np->full_name; - struct clk *clk; + struct clk_core *clk; struct resource res; int rc; struct xgene_dev_parameters parameters; diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h index c798138..d278572 100644 --- a/drivers/clk/clk.h +++ b/drivers/clk/clk.h @@ -10,8 +10,8 @@ */ #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) -struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); -struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec); +struct clk_core *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); +struct clk_core *__of_clk_get_from_provider(struct of_phandle_args *clkspec); void of_clk_lock(void); void of_clk_unlock(void); #endif diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 339945d..d7d3667 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -296,7 +296,7 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw, static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { struct clk_mmc *mclk = to_mmc(hw); unsigned long best = 0; @@ -427,11 +427,11 @@ static struct clk_ops clk_mmc_ops = { .recalc_rate = mmc_clk_recalc_rate, }; -static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, +static struct clk_core *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, void __iomem *base, struct device_node *np) { struct clk_mmc *mclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; mclk = kzalloc(sizeof(*mclk), GFP_KERNEL); @@ -487,7 +487,7 @@ static void __init hi3620_mmc_clk_init(struct device_node *node) if (WARN_ON(!clk_data)) return; - clk_data->clks = kzalloc(sizeof(struct clk *) * num, GFP_KERNEL); + clk_data->clks = kzalloc(sizeof(struct clk_core *) * num, GFP_KERNEL); if (!clk_data->clks) { pr_err("%s: fail to allocate mmc clk\n", __func__); return; diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index a078e84..3fcd2ba 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -42,7 +42,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, int nr_clks) { struct hisi_clock_data *clk_data; - struct clk **clk_table; + struct clk_core **clk_table; void __iomem *base; if (np) { @@ -63,7 +63,7 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, } clk_data->base = base; - clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); + clk_table = kzalloc(sizeof(struct clk_core *) * nr_clks, GFP_KERNEL); if (!clk_table) { pr_err("%s: could not allocate clock lookup table\n", __func__); goto err_data; @@ -81,7 +81,7 @@ err: void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -102,7 +102,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; int i; for (i = 0; i < nums; i++) { @@ -122,7 +122,7 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -151,7 +151,7 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -180,7 +180,7 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; @@ -208,7 +208,7 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *clks, void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_core *clk; void __iomem *base = data->base; int i; diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..f7fc4b9 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -90,7 +90,7 @@ struct hisi_gate_clock { const char *alias; }; -struct clk *hisi_register_clkgate_sep(struct device *, const char *, +struct clk_core *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, u8, spinlock_t *); diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index b03d5a7..61f7236 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -96,14 +96,14 @@ static struct clk_ops clkgate_separated_ops = { .is_enabled = clkgate_separated_is_enabled, }; -struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, +struct clk_core *hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clkgate_separated *sclk; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c index 86f1e36..3f7db44 100644 --- a/drivers/clk/keystone/gate.c +++ b/drivers/clk/keystone/gate.c @@ -163,7 +163,7 @@ static const struct clk_ops clk_psc_ops = { * @psc_data: platform data to configure this clock * @lock: spinlock used by this clock */ -static struct clk *clk_register_psc(struct device *dev, +static struct clk_core *clk_register_psc(struct device *dev, const char *name, const char *parent_name, struct clk_psc_data *psc_data, @@ -171,7 +171,7 @@ static struct clk *clk_register_psc(struct device *dev, { struct clk_init_data init; struct clk_psc *psc; - struct clk *clk; + struct clk_core *clk; psc = kzalloc(sizeof(*psc), GFP_KERNEL); if (!psc) @@ -204,7 +204,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) const char *clk_name = node->name; const char *parent_name; struct clk_psc_data *data; - struct clk *clk; + struct clk_core *clk; int i; data = kzalloc(sizeof(*data), GFP_KERNEL); diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 0dd8a4b..fc3156e 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -116,14 +116,14 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pllclk_recalc, }; -static struct clk *clk_register_pll(struct device *dev, +static struct clk_core *clk_register_pll(struct device *dev, const char *name, const char *parent_name, struct clk_pll_data *pll_data) { struct clk_init_data init; struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -158,7 +158,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) { struct clk_pll_data *pll_data; const char *parent_name; - struct clk *clk; + struct clk_core *clk; int i; pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL); @@ -239,7 +239,7 @@ static void __init of_pll_div_clk_init(struct device_node *node) const char *parent_name; void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; of_property_read_string(node, "clock-output-names", &clk_name); @@ -282,7 +282,7 @@ static void __init of_pll_mux_clk_init(struct device_node *node) { void __iomem *reg; u32 shift, mask; - struct clk *clk; + struct clk_core *clk; const char *parents[2]; const char *clk_name = node->name; diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c index d14120e..4ca8713 100644 --- a/drivers/clk/mmp/clk-apbc.c +++ b/drivers/clk/mmp/clk-apbc.c @@ -120,12 +120,12 @@ struct clk_ops clk_apbc_ops = { .unprepare = clk_apbc_unprepare, }; -struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock) { struct clk_apbc *apbc; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apbc = kzalloc(sizeof(*apbc), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c index abe182b..c24e6e7 100644 --- a/drivers/clk/mmp/clk-apmu.c +++ b/drivers/clk/mmp/clk-apmu.c @@ -66,11 +66,11 @@ struct clk_ops clk_apmu_ops = { .disable = clk_apmu_disable, }; -struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock) { struct clk_apmu *apmu; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; apmu = kzalloc(sizeof(*apmu), GFP_KERNEL); diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c index 23a56f5..0386cdd 100644 --- a/drivers/clk/mmp/clk-frac.c +++ b/drivers/clk/mmp/clk-frac.c @@ -116,14 +116,14 @@ static struct clk_ops clk_factor_ops = { .set_rate = clk_factor_set_rate, }; -struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, +struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt) { struct clk_factor *factor; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!masks) { pr_err("%s: must pass a clk_factor_mask\n", __func__); diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c index b2721ca..98bd73f 100644 --- a/drivers/clk/mmp/clk-mmp2.c +++ b/drivers/clk/mmp/clk-mmp2.c @@ -77,8 +77,8 @@ static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"}; void __init mmp2_clk_init(void) { - struct clk *clk; - struct clk *vctcxo; + struct clk_core *clk; + struct clk_core *vctcxo; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -192,7 +192,7 @@ void __init mmp2_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(clk, 14745600); + clk_provider_set_rate(clk, 14745600); clk_register_clkdev(clk, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "vctcxo", @@ -251,7 +251,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -262,7 +262,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -273,7 +273,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", @@ -284,7 +284,7 @@ void __init mmp2_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); - clk_set_parent(clk, vctcxo); + clk_provider_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.3", NULL); clk = mmp_clk_register_apbc("uart3", "uart3_mux", diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c index 014396b..e4f50ab 100644 --- a/drivers/clk/mmp/clk-pxa168.c +++ b/drivers/clk/mmp/clk-pxa168.c @@ -68,8 +68,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa168_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; @@ -159,7 +159,7 @@ void __init pxa168_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -202,7 +202,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -213,7 +213,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -224,7 +224,7 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c index 9efc6a4..b5c215e 100644 --- a/drivers/clk/mmp/clk-pxa910.c +++ b/drivers/clk/mmp/clk-pxa910.c @@ -66,8 +66,8 @@ static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; void __init pxa910_clk_init(void) { - struct clk *clk; - struct clk *uart_pll; + struct clk_core *clk; + struct clk_core *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbcp_base; @@ -164,7 +164,7 @@ void __init pxa910_clk_init(void) mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); - clk_set_rate(uart_pll, 14745600); + clk_provider_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", @@ -207,7 +207,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", @@ -218,7 +218,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", @@ -229,7 +229,7 @@ void __init pxa910_clk_init(void) ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); - clk_set_parent(clk, uart_pll); + clk_provider_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h index ab86dd4..1477e61 100644 --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h @@ -20,15 +20,15 @@ struct clk_factor_tbl { unsigned int den; }; -extern struct clk *mmp_clk_register_pll2(const char *name, +extern struct clk_core *mmp_clk_register_pll2(const char *name, const char *parent_name, unsigned long flags); -extern struct clk *mmp_clk_register_apbc(const char *name, +extern struct clk_core *mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock); -extern struct clk *mmp_clk_register_apmu(const char *name, +extern struct clk_core *mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock); -extern struct clk *mmp_clk_register_factor(const char *name, +extern struct clk_core *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt); diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index d1e5863..1be15c4 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -238,7 +238,7 @@ mvebu_corediv_clk_init(struct device_node *node, { struct clk_init_data init; struct clk_corediv *corediv; - struct clk **clks; + struct clk_core **clks; void __iomem *base; const char *parent_name; const char *clk_name; @@ -253,7 +253,7 @@ mvebu_corediv_clk_init(struct device_node *node, clk_data.clk_num = soc_desc->ndescs; /* clks holds the clock array */ - clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), + clks = kcalloc(clk_data.clk_num, sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clks)) goto err_unmap; diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c index 8ebf757..225124b 100644 --- a/drivers/clk/mvebu/clk-cpu.c +++ b/drivers/clk/mvebu/clk-cpu.c @@ -30,7 +30,7 @@ struct cpu_clk { void __iomem *reg_base; }; -static struct clk **clks; +static struct clk_core **clks; static struct clk_onecell_data clk_data; @@ -127,8 +127,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) for_each_node_by_type(dn, "cpu") { struct clk_init_data init; - struct clk *clk; - struct clk *parent_clk; + struct clk_core *clk; + struct clk_core *parent_clk; char *clk_name = kzalloc(5, GFP_KERNEL); int cpu, err; @@ -140,7 +140,7 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out; sprintf(clk_name, "cpu%d", cpu); - parent_clk = of_clk_get(node, 0); + parent_clk = of_clk_provider_get(node, 0); cpuclk[cpu].parent_name = __clk_get_name(parent_clk); cpuclk[cpu].clk_name = clk_name; diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 25ceccf..7e6c320 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -43,7 +43,7 @@ void __init mvebu_coreclk_setup(struct device_node *np, /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; - clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { iounmap(base); @@ -91,13 +91,13 @@ void __init mvebu_coreclk_setup(struct device_node *np, struct clk_gating_ctrl { spinlock_t lock; - struct clk **gates; + struct clk_core **gates; int num_gates; }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) -static struct clk *clk_gating_get_src( +static struct clk_core *clk_gating_get_src( struct of_phandle_args *clkspec, void *data) { struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data; @@ -119,7 +119,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, const struct clk_gating_soc_desc *desc) { struct clk_gating_ctrl *ctrl; - struct clk *clk; + struct clk_core *clk; void __iomem *base; const char *default_parent = NULL; int n; @@ -128,10 +128,10 @@ void __init mvebu_clk_gating_setup(struct device_node *np, if (WARN_ON(!base)) return; - clk = of_clk_get(np, 0); + clk = of_clk_provider_get(np, 0); if (!IS_ERR(clk)) { default_parent = __clk_get_name(clk); - clk_put(clk); + __clk_put(clk); } ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); @@ -145,7 +145,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, n++; ctrl->num_gates = n; - ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), + ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk_core *), GFP_KERNEL); if (WARN_ON(!ctrl->gates)) goto gates_out; diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c index 90e1da9..57f93e5 100644 --- a/drivers/clk/mxs/clk-div.c +++ b/drivers/clk/mxs/clk-div.c @@ -74,11 +74,11 @@ static struct clk_ops clk_div_ops = { .set_rate = clk_div_set_rate, }; -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_div *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; div = kzalloc(sizeof(*div), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c index e6aa6b5..87083e4 100644 --- a/drivers/clk/mxs/clk-frac.c +++ b/drivers/clk/mxs/clk-frac.c @@ -108,11 +108,11 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; frac = kzalloc(sizeof(*frac), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 9fc9359..fc7fdf2 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -94,7 +94,7 @@ enum imx23_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx23_clk clks_init_on[] __initdata = { @@ -171,7 +171,7 @@ static void __init mx23_clocks_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init); diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index a6c3501..083add7 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -148,7 +148,7 @@ enum imx28_clk { clk_max }; -static struct clk *clks[clk_max]; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx28_clk clks_init_on[] __initdata = { @@ -250,6 +250,6 @@ static void __init mx28_clocks_init(struct device_node *np) clk_register_clkdev(clks[enet_out], NULL, "enet_out"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clks[clks_init_on[i]]); + clk_provider_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init); diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c index fadae41..8e29d79 100644 --- a/drivers/clk/mxs/clk-pll.c +++ b/drivers/clk/mxs/clk-pll.c @@ -86,11 +86,11 @@ static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate) { struct clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 4adeed6..ad1aa00 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -125,11 +125,11 @@ static const struct clk_ops clk_ref_ops = { .set_rate = clk_ref_set_rate, }; -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_ref *ref; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; ref = kzalloc(sizeof(*ref), GFP_KERNEL); diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h index ef10ad9..b258ea5 100644 --- a/drivers/clk/mxs/clk.h +++ b/drivers/clk/mxs/clk.h @@ -23,24 +23,24 @@ extern spinlock_t mxs_lock; int mxs_clk_wait(void __iomem *reg, u8 shift); -struct clk *mxs_clk_pll(const char *name, const char *parent_name, +struct clk_core *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate); -struct clk *mxs_clk_ref(const char *name, const char *parent_name, +struct clk_core *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx); -struct clk *mxs_clk_div(const char *name, const char *parent_name, +struct clk_core *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -struct clk *mxs_clk_frac(const char *name, const char *parent_name, +struct clk_core *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy); -static inline struct clk *mxs_clk_fixed(const char *name, int rate) +static inline struct clk_core *mxs_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); } -static inline struct clk *mxs_clk_gate(const char *name, +static inline struct clk_core *mxs_clk_gate(const char *name, const char *parent_name, void __iomem *reg, u8 shift) { return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, @@ -48,7 +48,7 @@ static inline struct clk *mxs_clk_gate(const char *name, &mxs_lock); } -static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, +static inline struct clk_core *mxs_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parent_names, int num_parents) { return clk_register_mux(NULL, name, parent_names, num_parents, @@ -56,7 +56,7 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, reg, shift, width, 0, &mxs_lock); } -static inline struct clk *mxs_clk_fixed_factor(const char *name, +static inline struct clk_core *mxs_clk_fixed_factor(const char *name, const char *parent_name, unsigned int mult, unsigned int div) { return clk_register_fixed_factor(NULL, name, parent_name, diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index abfc2b6..e7d0bfb 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -375,7 +375,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -402,7 +402,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg *rcg = to_clk_rcg(hw); @@ -410,7 +410,7 @@ static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, } static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index cd185d5..6aac1ec 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -188,7 +188,7 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate) static long _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { unsigned long clk_flags; @@ -219,7 +219,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, } static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -372,7 +372,7 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, } static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -423,7 +423,7 @@ const struct clk_ops clk_edp_pixel_ops = { EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; @@ -485,14 +485,14 @@ static const struct frac_entry frac_table_pixel[] = { }; static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *p_rate, struct clk **p) + unsigned long *p_rate, struct clk_core **p) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); unsigned long request, src_rate; int delta = 100000; const struct freq_tbl *f = rcg->freq_tbl; const struct frac_entry *frac = frac_table_pixel; - struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src); + struct clk_core *parent = *p = clk_get_parent_by_index(hw->clk, f->src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; @@ -519,7 +519,7 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, int delta = 100000; u32 mask = BIT(rcg->hid_width) - 1; u32 hid_div; - struct clk *parent = clk_get_parent_by_index(hw->clk, f.src); + struct clk_core *parent = clk_get_parent_by_index(hw->clk, f.src); for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; diff --git a/drivers/clk/qcom/clk-regmap.c b/drivers/clk/qcom/clk-regmap.c index a58ba39..2a98040 100644 --- a/drivers/clk/qcom/clk-regmap.c +++ b/drivers/clk/qcom/clk-regmap.c @@ -101,7 +101,7 @@ EXPORT_SYMBOL_GPL(clk_disable_regmap); * clk_regmap struct via this function so that the regmap is initialized * and so that the clock is registered with the common clock framework. */ -struct clk *devm_clk_register_regmap(struct device *dev, +struct clk_core *devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) { if (dev && dev_get_regmap(dev, NULL)) diff --git a/drivers/clk/qcom/clk-regmap.h b/drivers/clk/qcom/clk-regmap.h index 491a63d..89258cb 100644 --- a/drivers/clk/qcom/clk-regmap.h +++ b/drivers/clk/qcom/clk-regmap.h @@ -39,7 +39,7 @@ struct clk_regmap { int clk_is_enabled_regmap(struct clk_hw *hw); int clk_enable_regmap(struct clk_hw *hw); void clk_disable_regmap(struct clk_hw *hw); -struct clk * +struct clk_core * devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk); #endif diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 9b5a1cf..bfa36bd 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -24,7 +24,7 @@ struct qcom_cc { struct qcom_reset_controller reset; struct clk_onecell_data data; - struct clk *clks[]; + struct clk_core *clks[]; }; int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) @@ -33,9 +33,9 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) struct resource *res; int i, ret; struct device *dev = &pdev->dev; - struct clk *clk; + struct clk_core *clk; struct clk_onecell_data *data; - struct clk **clks; + struct clk_core **clks; struct regmap *regmap; struct qcom_reset_controller *reset; struct qcom_cc *cc; diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c index 0c4b727..2d41fdb 100644 --- a/drivers/clk/qcom/gcc-msm8660.c +++ b/drivers/clk/qcom/gcc-msm8660.c @@ -2718,7 +2718,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); static int gcc_msm8660_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; /* Temporary until RPM clocks supported */ diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index f4ffd91..f3bf005 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -2911,7 +2911,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table); static int gcc_msm8960_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; const struct of_device_id *match; diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 7af7c18..8326b1f 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -2699,7 +2699,7 @@ static void msm8974_pro_clock_override(void) static int gcc_msm8974_probe(struct platform_device *pdev) { - struct clk *clk; + struct clk_core *clk; struct device *dev = &pdev->dev; bool pro; const struct of_device_id *id; diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 4c449b3..b3ae958 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -458,7 +458,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) int ret = 0; u32 val; struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); - struct clk *clk = hw->clk; + struct clk_core *clk = hw->clk; int num_parents = __clk_get_num_parents(hw->clk); /* @@ -470,7 +470,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) * needs to be on at what time. */ for (i = 0; i < num_parents; i++) { - ret = clk_prepare_enable(clk_get_parent_by_index(clk, i)); + ret = clk_provider_prepare_enable(clk_get_parent_by_index(clk, i)); if (ret) goto err; } @@ -499,7 +499,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) err: for (i--; i >= 0; i--) - clk_disable_unprepare(clk_get_parent_by_index(clk, i)); + clk_provider_disable_unprepare(clk_get_parent_by_index(clk, i)); return ret; } diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c index 4cf838d5..faa8dfa 100644 --- a/drivers/clk/rockchip/clk-rockchip.c +++ b/drivers/clk/rockchip/clk-rockchip.c @@ -54,7 +54,7 @@ static void __init rk2928_gate_clk_init(struct device_node *node) if (!clk_data) return; - clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc(qty * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 13eae14c..f5639bf 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -26,7 +26,7 @@ enum exynos_audss_clk_type { }; static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; +static struct clk_core **clk_table; static void __iomem *reg_base; static struct clk_onecell_data clk_data; @@ -83,7 +83,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; const char *sclk_pcm_p = "sclk_pcm0"; - struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; + struct clk_core *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; const struct of_device_id *match; enum exynos_audss_clk_type variant; @@ -100,7 +100,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + sizeof(struct clk_core *) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -111,8 +111,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) else clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1; - pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); - pll_in = devm_clk_get(&pdev->dev, "pll_in"); + pll_ref = devm_clk_provider_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_provider_get(&pdev->dev, "pll_in"); if (!IS_ERR(pll_ref)) mout_audss_p[0] = __clk_get_name(pll_ref); if (!IS_ERR(pll_in)) @@ -122,8 +122,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); - cdclk = devm_clk_get(&pdev->dev, "cdclk"); - sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + cdclk = devm_clk_provider_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_provider_get(&pdev->dev, "sclk_audio"); if (!IS_ERR(cdclk)) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) @@ -161,7 +161,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); - sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + sclk_pcm_in = devm_clk_provider_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 7f4a473..9f42648 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1038,19 +1038,19 @@ static unsigned long exynos4_get_xom(void) static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) { struct samsung_fixed_rate_clock fclk; - struct clk *clk; + struct clk_core *clk; unsigned long finpll_f = 24000000; char *parent_name; unsigned int xom = exynos4_get_xom(); parent_name = xom & 1 ? "xusbxti" : "xxti"; - clk = clk_get(NULL, parent_name); + clk = clk_provider_get(NULL, parent_name); if (IS_ERR(clk)) { pr_err("%s: failed to lookup parent clock %s, assuming " "fin_pll clock frequency is 24MHz\n", __func__, parent_name); } else { - finpll_f = clk_get_rate(clk); + finpll_f = clk_provider_get_rate(clk); } fclk.id = CLK_FIN_PLL; diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..aaf234a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -910,12 +910,12 @@ static const struct clk_ops samsung_pll2550x_clk_ops = { .recalc_rate = samsung_pll2550x_recalc_rate, }; -struct clk * __init samsung_clk_register_pll2550x(const char *name, +struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset) { struct samsung_clk_pll2550x *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -1149,7 +1149,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, void __iomem *base) { struct samsung_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int ret, len; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..81af344 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -97,7 +97,7 @@ struct samsung_pll_rate_table { unsigned int vsel; }; -extern struct clk * __init samsung_clk_register_pll2550x(const char *name, +extern struct clk_core * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset); diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c index 0449cc0..70baecf 100644 --- a/drivers/clk/samsung/clk-s3c2410-dclk.c +++ b/drivers/clk/samsung/clk-s3c2410-dclk.c @@ -87,12 +87,12 @@ const struct clk_ops s3c24xx_clkout_ops = { .determine_rate = __clk_mux_determine_rate, }; -struct clk *s3c24xx_register_clkout(struct device *dev, const char *name, +struct clk_core *s3c24xx_register_clkout(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u8 shift, u32 mask) { struct s3c24xx_clkout *clkout; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the clkout */ @@ -237,7 +237,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk; struct resource *mem; - struct clk **clk_table; + struct clk_core **clk_table; struct s3c24xx_dclk_drv_data *dclk_variant; int ret, i; @@ -251,7 +251,7 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev) spin_lock_init(&s3c24xx_dclk->dclk_lock); clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * DCLK_MAX_CLKS, + sizeof(struct clk_core *) * DCLK_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; @@ -355,7 +355,7 @@ err_clk_register: static int s3c24xx_dclk_remove(struct platform_device *pdev) { struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); - struct clk **clk_table = s3c24xx_dclk->clk_data.clks; + struct clk_core **clk_table = s3c24xx_dclk->clk_data.clks; int i; clk_notifier_unregister(clk_table[DIV_DCLK1], diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 49629c7..59bf393 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -52,7 +52,7 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks) { struct samsung_clk_provider *ctx; - struct clk **clk_table; + struct clk_core **clk_table; int ret; int i; @@ -60,7 +60,7 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, if (!ctx) panic("could not allocate clock provider context.\n"); - clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); + clk_table = kcalloc(nr_clks, sizeof(struct clk_core *), GFP_KERNEL); if (!clk_table) panic("could not allocate clock lookup table\n"); @@ -84,7 +84,7 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, } /* add a clock instance to the clock lookup table used for dt based lookup */ -void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, +void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk_core *clk, unsigned int id) { if (ctx->clk_data.clks && id) @@ -96,7 +96,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; if (!ctx->clk_data.clks) { @@ -129,7 +129,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, struct samsung_fixed_rate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -158,7 +158,7 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -179,7 +179,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, struct samsung_mux_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -211,7 +211,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, struct samsung_div_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -250,7 +250,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, struct samsung_gate_clock *list, unsigned int nr_clk) { - struct clk *clk; + struct clk_core *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { @@ -302,7 +302,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, /* utility function to get the rate of a specified clock */ unsigned long _get_rate(const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = __clk_lookup(clk_name); if (!clk) { @@ -310,5 +310,5 @@ unsigned long _get_rate(const char *clk_name) return 0; } - return clk_get_rate(clk); + return clk_provider_get_rate(clk); } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 9693b80..33f14bb 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -334,7 +334,7 @@ extern void __init samsung_clk_of_register_fixed_ext( struct of_device_id *clk_matches); extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, - struct clk *clk, unsigned int id); + struct clk_core *clk, unsigned int id); extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, struct samsung_clock_alias *list, diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index f065f69..c6712fb 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -119,7 +119,7 @@ static void __init cpg_div6_clock_init(struct device_node *np) struct div6_clock *clock; const char *parent_name; const char *name; - struct clk *clk; + struct clk_core *clk; int ret; clock = kzalloc(sizeof(*clock), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-emev2.c b/drivers/clk/shmobile/clk-emev2.c index 6c7c929..2e3a45b 100644 --- a/drivers/clk/shmobile/clk-emev2.c +++ b/drivers/clk/shmobile/clk-emev2.c @@ -71,7 +71,7 @@ static void __init emev2_smu_init(void) static void __init emev2_smu_clkdiv_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; @@ -89,7 +89,7 @@ CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv", static void __init emev2_smu_gclk_init(struct device_node *np) { u32 reg[2]; - struct clk *clk; + struct clk_core *clk; const char *parent_name = of_clk_get_parent_name(np, 0); if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) return; diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c index 2d2fe77..2659676 100644 --- a/drivers/clk/shmobile/clk-mstp.c +++ b/drivers/clk/shmobile/clk-mstp.c @@ -121,13 +121,13 @@ static const struct clk_ops cpg_mstp_clock_ops = { .is_enabled = cpg_mstp_clock_is_enabled, }; -static struct clk * __init +static struct clk_core * __init cpg_mstp_clock_register(const char *name, const char *parent_name, unsigned int index, struct mstp_clock_group *group) { struct clk_init_data init; struct mstp_clock *clock; - struct clk *clk; + struct clk_core *clk; clock = kzalloc(sizeof(*clock), GFP_KERNEL); if (!clock) { @@ -157,7 +157,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) { struct mstp_clock_group *group; const char *idxname; - struct clk **clks; + struct clk_core **clks; unsigned int i; group = kzalloc(sizeof(*group), GFP_KERNEL); diff --git a/drivers/clk/shmobile/clk-r8a7740.c b/drivers/clk/shmobile/clk-r8a7740.c index 1e2eaae..8889e6a 100644 --- a/drivers/clk/shmobile/clk-r8a7740.c +++ b/drivers/clk/shmobile/clk-r8a7740.c @@ -61,7 +61,7 @@ static const struct clk_div_table div4_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, const char *name) { @@ -147,7 +147,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, static void __init r8a7740_cpg_clocks_init(struct device_node *np) { struct r8a7740_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -180,7 +180,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c index 652ecac..96b51b1 100644 --- a/drivers/clk/shmobile/clk-r8a7779.c +++ b/drivers/clk/shmobile/clk-r8a7779.c @@ -90,7 +90,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, const struct cpg_clk_config *config, unsigned int plla_mult, const char *name) @@ -124,7 +124,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) { const struct cpg_clk_config *config; struct r8a7779_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i, plla_mult; int num_clks; @@ -153,7 +153,7 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index dff7f79..d8bdeb8 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -133,12 +133,12 @@ static const struct clk_ops cpg_z_clk_ops = { .set_rate = cpg_z_clk_set_rate, }; -static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) +static struct clk_core * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) { static const char *parent_name = "pll0"; struct clk_init_data init; struct cpg_z_clk *zclk; - struct clk *clk; + struct clk_core *clk; zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); if (!zclk) @@ -212,7 +212,7 @@ static const struct clk_div_table cpg_sd01_div_table[] = { static u32 cpg_mode __initdata; -static struct clk * __init +static struct clk_core * __init rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, const struct cpg_pll_config *config, const char *name) @@ -279,7 +279,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) { const struct cpg_pll_config *config; struct rcar_gen2_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned int i; int num_clks; @@ -312,7 +312,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c index 7e68e86..414e20e 100644 --- a/drivers/clk/shmobile/clk-rz.c +++ b/drivers/clk/shmobile/clk-rz.c @@ -28,7 +28,7 @@ struct rz_cpg { * Initialization */ -static struct clk * __init +static struct clk_core * __init rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) { u32 val; @@ -67,7 +67,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static void __init rz_cpg_clocks_init(struct device_node *np) { struct rz_cpg *cpg; - struct clk **clks; + struct clk_core **clks; unsigned i; int num_clks; @@ -86,7 +86,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np) for (i = 0; i < num_clks; ++i) { const char *name; - struct clk *clk; + struct clk_core *clk; of_property_read_string_index(np, "clock-output-names", i, &name); diff --git a/drivers/clk/sirf/clk-atlas6.c b/drivers/clk/sirf/clk-atlas6.c index d63b76c..9cce269 100644 --- a/drivers/clk/sirf/clk-atlas6.c +++ b/drivers/clk/sirf/clk-atlas6.c @@ -113,7 +113,7 @@ static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *atlas6_clks[maxclk]; +static struct clk_core *atlas6_clks[maxclk]; static void __init atlas6_clk_init(struct device_node *np) { diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c index 37af51c..05f5040 100644 --- a/drivers/clk/sirf/clk-common.c +++ b/drivers/clk/sirf/clk-common.c @@ -165,9 +165,9 @@ static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, * SiRF SoC has not cpu clock control, * So bypass to it's parent pll. */ - struct clk *parent_clk = clk_get_parent(hw->clk); - struct clk *pll_parent_clk = clk_get_parent(parent_clk); - unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); + struct clk_core *pll_parent_clk = clk_provider_get_parent(parent_clk); + unsigned long pll_parent_rate = clk_provider_get_rate(pll_parent_clk); return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate); } @@ -178,7 +178,7 @@ static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, * SiRF SoC has not cpu clock control, * So return the parent pll rate. */ - struct clk *parent_clk = clk_get_parent(hw->clk); + struct clk_core *parent_clk = clk_provider_get_parent(hw->clk); return __clk_get_rate(parent_clk); } @@ -403,34 +403,34 @@ static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int ret1, ret2; - struct clk *cur_parent; + struct clk_core *cur_parent; - if (rate == clk_get_rate(clk_pll1.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + if (rate == clk_provider_get_rate(clk_pll1.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll2.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + if (rate == clk_provider_get_rate(clk_pll2.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); return ret1; } - if (rate == clk_get_rate(clk_pll3.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); + if (rate == clk_provider_get_rate(clk_pll3.hw.clk)) { + ret1 = clk_provider_set_parent(hw->clk, clk_pll3.hw.clk); return ret1; } - cur_parent = clk_get_parent(hw->clk); + cur_parent = clk_provider_get_parent(hw->clk); /* switch to tmp pll before setting parent clock's rate */ if (cur_parent == clk_pll1.hw.clk) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll2.hw.clk); BUG_ON(ret1); } - ret2 = clk_set_rate(clk_pll1.hw.clk, rate); + ret2 = clk_provider_set_rate(clk_pll1.hw.clk, rate); - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); + ret1 = clk_provider_set_parent(hw->clk, clk_pll1.hw.clk); return ret2 ? ret2 : ret1; } diff --git a/drivers/clk/sirf/clk-prima2.c b/drivers/clk/sirf/clk-prima2.c index 6968e2e..751187b 100644 --- a/drivers/clk/sirf/clk-prima2.c +++ b/drivers/clk/sirf/clk-prima2.c @@ -112,7 +112,7 @@ static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = { &clk_cphif.hw, }; -static struct clk *prima2_clks[maxclk]; +static struct clk_core *prima2_clks[maxclk]; static void __init prima2_clk_init(struct device_node *np) { diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index dd3a78c..e3a6fe6 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -188,7 +188,7 @@ static void __init __socfpga_gate_init(struct device_node *node, u32 div_reg[3]; u32 clk_phase[2]; u32 fixed_div; - struct clk *clk; + struct clk_core *clk; struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 46531c3..a63be19 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -53,7 +53,7 @@ static __init void __socfpga_periph_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name; diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index de6da95..4ed91a4 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -81,11 +81,11 @@ static struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static __init struct clk *__socfpga_pll_init(struct device_node *node, +static __init struct clk_core *__socfpga_pll_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_core *clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c index bdfb442..18334c3 100644 --- a/drivers/clk/spear/clk-aux-synth.c +++ b/drivers/clk/spear/clk-aux-synth.c @@ -134,14 +134,14 @@ static struct clk_ops clk_aux_ops = { .set_rate = clk_aux_set_rate, }; -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk) { struct clk_aux *aux; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); @@ -177,7 +177,7 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name, goto free_aux; if (gate_name) { - struct clk *tgate_clk; + struct clk_core *tgate_clk; tgate_clk = clk_register_gate(NULL, gate_name, aux_name, CLK_SET_RATE_PARENT, reg, diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c index dffd4ce..bce2c0e 100644 --- a/drivers/clk/spear/clk-frac-synth.c +++ b/drivers/clk/spear/clk-frac-synth.c @@ -122,13 +122,13 @@ static struct clk_ops clk_frac_ops = { .set_rate = clk_frac_set_rate, }; -struct clk *clk_register_frac(const char *name, const char *parent_name, +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_frac *frac; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c index 1afc18c..f8e13f3 100644 --- a/drivers/clk/spear/clk-gpt-synth.c +++ b/drivers/clk/spear/clk-gpt-synth.c @@ -111,13 +111,13 @@ static struct clk_ops clk_gpt_ops = { .set_rate = clk_gpt_set_rate, }; -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_gpt *gpt; - struct clk *clk; + struct clk_core *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c index 1b9b65b..226f2ec 100644 --- a/drivers/clk/spear/clk-vco-pll.c +++ b/drivers/clk/spear/clk-vco-pll.c @@ -272,16 +272,16 @@ static struct clk_ops clk_vco_ops = { .set_rate = clk_vco_set_rate, }; -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk) + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk) { struct clk_vco *vco; struct clk_pll *pll; - struct clk *vco_clk, *tpll_clk, *tvco_gate_clk; + struct clk_core *vco_clk, *tpll_clk, *tvco_gate_clk; struct clk_init_data vco_init, pll_init; const char **vco_parent_name; diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h index 9317376..777322e 100644 --- a/drivers/clk/spear/clk.h +++ b/drivers/clk/spear/clk.h @@ -110,22 +110,22 @@ typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, int index); /* clk register routines */ -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, +struct clk_core *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); -struct clk *clk_register_frac(const char *name, const char *parent_name, + u8 rtbl_cnt, spinlock_t *lock, struct clk_core **gate_clk); +struct clk_core *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned +struct clk_core *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, +struct clk_core *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk); + spinlock_t *lock, struct clk_core **pll_clk, + struct clk_core **vco_gate_clk); long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index 65894f7..31c5ccb 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c @@ -385,7 +385,7 @@ static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c index fe835c1..843ced4 100644 --- a/drivers/clk/spear/spear1340_clock.c +++ b/drivers/clk/spear/spear1340_clock.c @@ -442,7 +442,7 @@ static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", void __init spear1340_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index bb5f387..5b8d659 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c @@ -140,7 +140,7 @@ static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", #ifdef CONFIG_MACH_SPEAR300 static void __init spear300_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 1, 1); @@ -170,7 +170,7 @@ static inline void spear300_clk_init(void) { } #ifdef CONFIG_MACH_SPEAR310 static void __init spear310_clk_init(void) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 1); @@ -246,9 +246,9 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; static void __init spear320_clk_init(void __iomem *soc_config_base, - struct clk *ras_apb_clk) + struct clk_core *ras_apb_clk) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, CLK_IS_ROOT, 125000000); @@ -344,7 +344,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, 0, &_lock); clk_register_clkdev(clk, NULL, "a3000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -353,7 +353,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a4000000.serial"); /* Enforce ras_apb_clk */ - clk_set_parent(clk, ras_apb_clk); + clk_provider_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, ARRAY_SIZE(uartx_parents), @@ -384,12 +384,12 @@ static void __init spear320_clk_init(void __iomem *soc_config_base, clk_register_clkdev(clk, NULL, "60100000.serial"); } #else -static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } +static inline void spear320_clk_init(void __iomem *sb, struct clk_core *rc) { } #endif void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) { - struct clk *clk, *clk1, *ras_apb_clk; + struct clk_core *clk, *clk1, *ras_apb_clk; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index 4f649c9..db946f7 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c @@ -116,7 +116,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = { void __init spear6xx_clk_init(void __iomem *misc_base) { - struct clk *clk, *clk1; + struct clk_core *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index 4f53ee0..a27a876 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -474,13 +474,13 @@ static const struct clk_ops st_quadfs_pll_c32_ops = { .set_rate = quadfs_pll_fs660c32_set_rate, }; -static struct clk * __init st_clk_register_quadfs_pll( +static struct clk_core * __init st_clk_register_quadfs_pll( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, spinlock_t *lock) { struct st_clk_quadfs_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -875,13 +875,13 @@ static const struct clk_ops st_quadfs_ops = { .recalc_rate = quadfs_recalc_rate, }; -static struct clk * __init st_clk_register_quadfs_fsynth( +static struct clk_core * __init st_clk_register_quadfs_fsynth( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, spinlock_t *lock) { struct st_clk_quadfs_fsynth *fs; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* @@ -947,7 +947,7 @@ static void __init st_of_create_quadfs_fsynths( return; clk_data->clk_num = QUADFS_MAX_CHAN; - clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *), + clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { @@ -956,7 +956,7 @@ static void __init st_of_create_quadfs_fsynths( } for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -981,8 +981,8 @@ static void __init st_of_create_quadfs_fsynths( clk_data->clks[fschan] = clk; pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); } } @@ -992,7 +992,7 @@ static void __init st_of_create_quadfs_fsynths( static void __init st_of_quadfs_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *pll_name, *clk_parent_name; void __iomem *reg; spinlock_t *lock; @@ -1026,8 +1026,8 @@ static void __init st_of_quadfs_setup(struct device_node *np) else pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); st_of_create_quadfs_fsynths(np, pll_name, (struct clkgen_quadfs_data *)match->data, diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c index a329906..b144315 100644 --- a/drivers/clk/st/clkgen-mux.c +++ b/drivers/clk/st/clkgen-mux.c @@ -215,7 +215,7 @@ static const struct clk_ops clkgena_divmux_ops = { /** * clk_register_genamux - register a genamux clock with the clock framework */ -struct clk *clk_register_genamux(const char *name, +struct clk_core *clk_register_genamux(const char *name, const char **parent_names, u8 num_parents, void __iomem *reg, const struct clkgena_divmux_data *muxdata, @@ -227,7 +227,7 @@ struct clk *clk_register_genamux(const char *name, const int mux_width = 2; const int divider_width = 5; struct clkgena_divmux *genamux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; int i; @@ -280,8 +280,8 @@ struct clk *clk_register_genamux(const char *name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); err: return clk; } @@ -413,14 +413,14 @@ void __init st_of_clkgena_divmux_setup(struct device_node *np) goto err; clk_data->clk_num = data->num_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -490,7 +490,7 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) const struct of_device_id *match; void __iomem *reg; const char *parent_name, *clk_name; - struct clk *clk; + struct clk_core *clk; struct clkgena_prediv_data *data; match = of_match_node(clkgena_prediv_of_match, np); @@ -522,8 +522,8 @@ void __init st_of_clkgena_prediv_setup(struct device_node *np) of_clk_add_provider(np, of_clk_src_simple_get, clk); pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); return; } @@ -616,7 +616,7 @@ static struct of_device_id mux_of_match[] = { void __init st_of_clkgen_mux_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; void __iomem *reg; const char **parents; int num_parents; @@ -653,8 +653,8 @@ void __init st_of_clkgen_mux_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); of_clk_add_provider(np, of_clk_src_simple_get, clk); @@ -717,14 +717,14 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) goto err; clk_data->clk_num = VCC_MAX_CHANNELS; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (i = 0; i < clk_data->clk_num; i++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; struct clk_gate *gate; struct clk_divider *div; @@ -786,8 +786,8 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np) pr_debug("%s: parent %s rate %u\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - (unsigned int)clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + (unsigned int)clk_provider_get_rate(clk)); clk_data->clks[i] = clk; } diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index d8b9b1a..26cec54 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -342,13 +342,13 @@ static const struct clk_ops st_pll1200c32_ops = { .recalc_rate = recalc_stm_pll1200c32, }; -static struct clk * __init clkgen_pll_register(const char *parent_name, +static struct clk_core * __init clkgen_pll_register(const char *parent_name, struct clkgen_pll_data *pll_data, void __iomem *reg, const char *clk_name) { struct clkgen_pll *pll; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); @@ -374,16 +374,16 @@ static struct clk * __init clkgen_pll_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } -static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, +static struct clk_core * __init clkgen_c65_lsdiv_register(const char *parent_name, const char *clk_name) { - struct clk *clk; + struct clk_core *clk; clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2); if (IS_ERR(clk)) @@ -391,8 +391,8 @@ static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -436,7 +436,7 @@ static void __init clkgena_c65_pll_setup(struct device_node *np) return; clk_data->clk_num = num_pll_outputs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) @@ -497,14 +497,14 @@ err: CLK_OF_DECLARE(clkgena_c65_plls, "st,clkgena-plls-c65", clkgena_c65_pll_setup); -static struct clk * __init clkgen_odf_register(const char *parent_name, +static struct clk_core * __init clkgen_odf_register(const char *parent_name, void * __iomem reg, struct clkgen_pll_data *pll_data, int odf, spinlock_t *odf_lock, const char *odf_name) { - struct clk *clk; + struct clk_core *clk; unsigned long flags; struct clk_gate *gate; struct clk_divider *div; @@ -542,8 +542,8 @@ static struct clk * __init clkgen_odf_register(const char *parent_name, pr_debug("%s: parent %s rate %lu\n", __clk_get_name(clk), - __clk_get_name(clk_get_parent(clk)), - clk_get_rate(clk)); + __clk_get_name(clk_provider_get_parent(clk)), + clk_provider_get_rate(clk)); return clk; } @@ -578,7 +578,7 @@ static struct of_device_id c32_pll_of_match[] = { static void __init clkgen_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name, *pll_name; void __iomem *pll_base; int num_odfs, odf; @@ -614,14 +614,14 @@ static void __init clkgen_c32_pll_setup(struct device_node *np) return; clk_data->clk_num = num_odfs; - clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), + clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) goto err; for (odf = 0; odf < num_odfs; odf++) { - struct clk *clk; + struct clk_core *clk; const char *clk_name; if (of_property_read_string_index(np, "clock-output-names", @@ -661,7 +661,7 @@ static struct of_device_id c32_gpu_pll_of_match[] = { static void __init clkgengpu_c32_pll_setup(struct device_node *np) { const struct of_device_id *match; - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; const char *clk_name; diff --git a/drivers/clk/sunxi/clk-a10-hosc.c b/drivers/clk/sunxi/clk-a10-hosc.c index 0481d5d..c5e4c41 100644 --- a/drivers/clk/sunxi/clk-a10-hosc.c +++ b/drivers/clk/sunxi/clk-a10-hosc.c @@ -25,7 +25,7 @@ static DEFINE_SPINLOCK(hosc_lock); static void __init sun4i_osc_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_fixed_rate *fixed; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c index 633ddc4..3e58734 100644 --- a/drivers/clk/sunxi/clk-a20-gmac.c +++ b/drivers/clk/sunxi/clk-a20-gmac.c @@ -55,7 +55,7 @@ static DEFINE_SPINLOCK(gmac_lock); static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_mux *mux; struct clk_gate *gate; const char *clk_name = node->name; diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c index 3806d97..3acdda6 100644 --- a/drivers/clk/sunxi/clk-factors.c +++ b/drivers/clk/sunxi/clk-factors.c @@ -79,9 +79,9 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate, static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_p) + struct clk_core **best_parent_p) { - struct clk *clk = hw->clk, *parent, *best_parent = NULL; + struct clk_core *clk = hw->clk, *parent, *best_parent = NULL; int i, num_parents; unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c index 670f90d..727a6a2 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c @@ -50,7 +50,7 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev) clk_data->clks = devm_kzalloc(&pdev->dev, SUN6I_APB0_GATES_MAX_SIZE * - sizeof(struct clk *), + sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) return -ENOMEM; diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c index 11f17c3..241d274 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0.c @@ -35,7 +35,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev) const char *clk_parent; struct resource *r; void __iomem *reg; - struct clk *clk; + struct clk_core *clk; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, r); diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c index f73cc05..1e95eb4 100644 --- a/drivers/clk/sunxi/clk-sun6i-ar100.c +++ b/drivers/clk/sunxi/clk-sun6i-ar100.c @@ -46,7 +46,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw, static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_core **best_parent_clk) { int nparents = __clk_get_num_parents(hw->clk); long best_rate = -EINVAL; @@ -57,7 +57,7 @@ static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, for (i = 0; i < nparents; i++) { unsigned long parent_rate; unsigned long tmp_rate; - struct clk *parent; + struct clk_core *parent; unsigned long div; int shift; @@ -176,7 +176,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev) struct clk_init_data init; struct ar100_clk *ar100; struct resource *r; - struct clk *clk; + struct clk_core *clk; int nparents; int i; diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index fb2ce84..ab4c3d0 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -355,7 +355,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, * clk_sunxi_mmc_phase_control() - configures MMC clock phase control */ -void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output) +void clk_sunxi_mmc_phase_control(struct clk_core *clk, u8 sample, u8 output) { #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) @@ -516,10 +516,10 @@ static const struct factors_data sun7i_a20_out_data __initconst = { .getter = sun7i_a20_get_out_factors, }; -static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, +static struct clk_core * __init sunxi_factors_clk_setup(struct device_node *node, const struct factors_data *data) { - struct clk *clk; + struct clk_core *clk; struct clk_factors *factors; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; @@ -629,7 +629,7 @@ static const struct mux_data sun4i_apb1_mux_data __initconst = { static void __init sunxi_mux_clk_setup(struct device_node *node, struct mux_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parents[SUNXI_MAX_PARENTS]; void *reg; @@ -693,7 +693,7 @@ static const struct div_data sun6i_a31_apb2_div_data __initconst = { static void __init sunxi_divider_clk_setup(struct device_node *node, struct div_data *data) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *clk_parent; void *reg; @@ -881,7 +881,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) return; - clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk_core *), GFP_KERNEL); if (!clk_data->clks) { kfree(clk_data); return; @@ -985,7 +985,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, struct clk_onecell_data *clk_data; const char *parent; const char *clk_name; - struct clk **clks, *pclk; + struct clk_core **clks, *pclk; struct clk_hw *gate_hw, *rate_hw; const struct clk_ops *rate_ops; struct clk_gate *gate = NULL; @@ -1193,10 +1193,10 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks) /* Protect the clocks that needs to stay on */ for (i = 0; i < nclocks; i++) { - struct clk *clk = clk_get(NULL, clocks[i]); + struct clk_core *clk = clk_provider_get(NULL, clocks[i]); if (!IS_ERR(clk)) - clk_prepare_enable(clk); + clk_provider_prepare_enable(clk); } } diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c index c0f7843..53c3488 100644 --- a/drivers/clk/tegra/clk-audio-sync.c +++ b/drivers/clk/tegra/clk-audio-sync.c @@ -54,12 +54,12 @@ const struct clk_ops tegra_clk_sync_source_ops = { .recalc_rate = clk_sync_source_recalc_rate, }; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long rate, unsigned long max_rate) { struct tegra_clk_sync_source *sync; struct clk_init_data init; - struct clk *clk; + struct clk_core *clk; sync = kzalloc(sizeof(*sync), GFP_KERNEL); if (!sync) { diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 290f9c1..7a1212b7 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -147,13 +147,13 @@ const struct clk_ops tegra_clk_frac_div_ops = { .round_rate = clk_frac_div_round_rate, }; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock) { struct tegra_clk_frac_div *divider; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; divider = kzalloc(sizeof(*divider), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 5070153..5aaedd3 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -127,12 +127,12 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .disable = clk_periph_disable, }; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt) { struct tegra_clk_periph_gate *gate; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *pregs; diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 9e899c18..ea26de3 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -138,13 +138,13 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = { .set_rate = clk_periph_set_rate, }; -static struct clk *_tegra_clk_register_periph(const char *name, +static struct clk_core *_tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; struct tegra_clk_periph_regs *bank; bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); @@ -186,7 +186,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, return clk; } -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags) @@ -195,7 +195,7 @@ struct clk *tegra_clk_register_periph(const char *name, periph, clk_base, offset, flags); } -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset) diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 3598987..49ae7b1 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -87,13 +87,13 @@ const struct clk_ops tegra_clk_pll_out_ops = { .disable = clk_pll_out_disable, }; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags, spinlock_t *lock) { struct tegra_clk_pll_out *pll_out; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 637b62c..34063ed 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -723,7 +723,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) static int clk_plle_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); struct tegra_clk_pll_freq_table sel; u32 val; int err; @@ -1027,7 +1027,7 @@ static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, state = clk_pll_is_enabled(hw); if (state) { - if (rate != clk_get_rate(hw->clk)) { + if (rate != clk_provider_get_rate(hw->clk)) { pr_err("%s: Cannot change active PLLM\n", __func__); ret = -EINVAL; goto out; @@ -1279,7 +1279,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) u32 val; int ret; unsigned long flags = 0; - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_provider_get_rate(clk_provider_get_parent(hw->clk)); if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) return -EINVAL; @@ -1411,7 +1411,7 @@ static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, return pll; } -static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, +static struct clk_core *_tegra_clk_register_pll(struct tegra_clk_pll *pll, const char *name, const char *parent_name, unsigned long flags, const struct clk_ops *ops) { @@ -1429,13 +1429,13 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, return clk_register(NULL, &pll->hw); } -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1460,13 +1460,13 @@ static struct div_nmp pll_e_nmp = { .divp_width = PLLE_BASE_DIVP_WIDTH, }; -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1531,14 +1531,14 @@ static const struct clk_ops tegra_clk_plle_tegra114_ops = { }; -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; int err; u32 val, val_iddq; @@ -1584,7 +1584,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, @@ -1592,7 +1592,7 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, { u32 val; struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; @@ -1630,14 +1630,14 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; unsigned long parent_rate; if (!pll_params->pdiv_tohw) @@ -1669,13 +1669,13 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { - struct clk *parent, *clk; + struct clk_core *parent, *clk; struct pdiv_map *p_tohw = pll_params->pdiv_tohw; struct tegra_clk_pll *pll; struct tegra_clk_pll_freq_table cfg; @@ -1743,14 +1743,14 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, return clk; } -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 val, val_aux; pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; @@ -1793,13 +1793,13 @@ static const struct clk_ops tegra_clk_pllss_ops = { .set_rate = clk_pllxc_set_rate, }; -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) { struct tegra_clk_pll *pll; - struct clk *clk, *parent; + struct clk_core *clk, *parent; struct tegra_clk_pll_freq_table cfg; unsigned long parent_rate; u32 val; diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 2fd924d..e843d20 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -127,13 +127,13 @@ const struct clk_ops tegra_clk_super_ops = { .set_parent = clk_super_set_parent, }; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock) { struct tegra_clk_super_mux *super; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; super = kzalloc(sizeof(*super), GFP_KERNEL); diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c index 5c38aab..484a900 100644 --- a/drivers/clk/tegra/clk-tegra-audio.c +++ b/drivers/clk/tegra/clk-tegra-audio.c @@ -128,8 +128,8 @@ void __init tegra_audio_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_a_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; /* PLLA */ diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index f3b7738..503e261 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -36,8 +36,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, unsigned long *osc_freq, unsigned long *pll_ref_freq) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; u32 val, pll_ref_div; unsigned osc_idx; @@ -81,8 +81,8 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* clk_32k */ dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index adf6b81..dd06579 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -585,8 +585,8 @@ static void __init periph_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { struct tegra_clk_periph_regs *bank; @@ -615,8 +615,8 @@ static void __init gate_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { int i; - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { struct tegra_periph_init_data *data; @@ -640,8 +640,8 @@ static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c index 08b21c1..2ff427a 100644 --- a/drivers/clk/tegra/clk-tegra-pmc.c +++ b/drivers/clk/tegra/clk-tegra-pmc.c @@ -82,8 +82,8 @@ static struct pmc_clk_init_data pmc_clks[] = { void __init tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; int i; for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index feb3201..e6224c4 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -53,8 +53,8 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", static void __init tegra_sclk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* SCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); @@ -99,8 +99,8 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *params) { - struct clk *clk; - struct clk **dt_clk; + struct clk_core *clk; + struct clk_core **dt_clk; /* CCLKG */ dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index b9c8ba2..a16e064 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -923,14 +923,14 @@ static struct tegra_devclk devclks[] __initdata = { { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER }, }; -static struct clk **clks; +static struct clk_core **clks; static unsigned long osc_freq; static unsigned long pll_ref_freq; static int __init tegra114_osc_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; u32 val, pll_ref_div; val = readl_relaxed(clk_base + OSC_CTRL); @@ -960,7 +960,7 @@ static int __init tegra114_osc_clk_init(void __iomem *clk_base) static void __init tegra114_fixed_clk_init(void __iomem *clk_base) { - struct clk *clk; + struct clk_core *clk; /* clk_32k */ clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, @@ -1065,7 +1065,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, @@ -1181,7 +1181,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, static __init void tegra114_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; /* xusb_ss_div2 */ clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 80efe51..b77cb64 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1017,7 +1017,7 @@ static struct tegra_devclk devclks[] __initdata = { { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, }; -static struct clk **clks; +static struct clk_core **clks; static void tegra124_utmi_param_configure(void __iomem *clk_base) { @@ -1104,7 +1104,7 @@ static void tegra124_utmi_param_configure(void __iomem *clk_base) static __init void tegra124_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { - struct clk *clk; + struct clk_core *clk; /* xusb_ss_div2 */ clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, @@ -1148,7 +1148,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base, void __iomem *pmc) { u32 val; - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index dace2b1..6783355 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -162,7 +162,7 @@ static void __iomem *pmc_base; _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { { 12000000, 600000000, 600, 12, 0, 8 }, @@ -633,7 +633,7 @@ static unsigned int tegra20_get_pll_ref_div(void) static void tegra20_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, @@ -713,7 +713,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void tegra20_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* CCLK */ clk = tegra_clk_register_super_mux("cclk", cclk_parents, @@ -738,7 +738,7 @@ static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", static void __init tegra20_audio_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* audio */ clk = clk_register_mux(NULL, "audio_mux", audio_parents, @@ -800,7 +800,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* ac97 */ @@ -871,7 +871,7 @@ static void __init tegra20_periph_clk_init(void) static void __init tegra20_osc_clk_init(void) { - struct clk *clk; + struct clk_core *clk; unsigned long input_freq; unsigned int pll_ref_div; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 8b10c38..801bb61 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -202,7 +202,7 @@ static DEFINE_SPINLOCK(pll_d_lock); _clk_num, _gate_flags, \ _clk_id) -static struct clk **clks; +static struct clk_core **clks; /* * Structure defining the fields for USB UTMI clocks Parameters. @@ -918,7 +918,7 @@ static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; static void __init tegra30_pll_init(void) { - struct clk *clk; + struct clk_core *clk; /* PLLC */ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, @@ -1009,7 +1009,7 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static void __init tegra30_super_clk_init(void) { - struct clk *clk; + struct clk_core *clk; /* * Clock input to cclk_g divided from pll_p using @@ -1131,7 +1131,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra30_periph_clk_init(void) { struct tegra_periph_init_data *data; - struct clk *clk; + struct clk_core *clk; int i; /* dsia */ diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index c0a7d77..229ac1e 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -68,7 +68,7 @@ struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; int *periph_clk_enb_refcnt; static int periph_banks; -static struct clk **clks; +static struct clk_core **clks; static int clk_num; static struct clk_onecell_data clk_data; @@ -164,7 +164,7 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } -struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) +struct clk_core ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; @@ -178,7 +178,7 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) periph_banks = banks; - clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); + clks = kzalloc(num * sizeof(struct clk_core *), GFP_KERNEL); if (!clks) kfree(periph_clk_enb_refcnt); @@ -188,9 +188,9 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) } void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; dup_list->clk_id < clk_max; dup_list++) { clk = clks[dup_list->clk_id]; @@ -200,9 +200,9 @@ void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, } void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max) + struct clk_core *clks[], int clk_max) { - struct clk *clk; + struct clk_core *clk; for (; tbl->clk_id < clk_max; tbl++) { clk = clks[tbl->clk_id]; @@ -210,8 +210,8 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, return; if (tbl->parent_id < clk_max) { - struct clk *parent = clks[tbl->parent_id]; - if (clk_set_parent(clk, parent)) { + struct clk_core *parent = clks[tbl->parent_id]; + if (clk_provider_set_parent(clk, parent)) { pr_err("%s: Failed to set parent %s of %s\n", __func__, __clk_get_name(parent), __clk_get_name(clk)); @@ -220,7 +220,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->rate) - if (clk_set_rate(clk, tbl->rate)) { + if (clk_provider_set_rate(clk, tbl->rate)) { pr_err("%s: Failed to set rate %lu of %s\n", __func__, tbl->rate, __clk_get_name(clk)); @@ -228,7 +228,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, } if (tbl->state) - if (clk_prepare_enable(clk)) { + if (clk_provider_prepare_enable(clk)) { pr_err("%s: Failed to enable %s\n", __func__, __clk_get_name(clk)); WARN_ON(1); @@ -279,7 +279,7 @@ void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num) dev_clks->dev_id); } -struct clk ** __init tegra_lookup_dt_id(int clk_id, +struct clk_core ** __init tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk) { if (tegra_clk[clk_id].present) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 16ec8d6..3093aa4 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -39,7 +39,7 @@ struct tegra_clk_sync_source { extern const struct clk_ops tegra_clk_sync_source_ops; extern int *periph_clk_enb_refcnt; -struct clk *tegra_clk_register_sync_source(const char *name, +struct clk_core *tegra_clk_register_sync_source(const char *name, unsigned long fixed_rate, unsigned long max_rate); /** @@ -82,7 +82,7 @@ struct tegra_clk_frac_div { #define TEGRA_DIVIDER_UART BIT(3) extern const struct clk_ops tegra_clk_frac_div_ops; -struct clk *tegra_clk_register_divider(const char *name, +struct clk_core *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); @@ -258,47 +258,47 @@ struct tegra_clk_pll { extern const struct clk_ops tegra_clk_pll_ops; extern const struct clk_ops tegra_clk_plle_ops; -struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_plle(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllxc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllm(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllc(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllre(const char *name, const char *parent_name, void __iomem *clk_base, void __iomem *pmc, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock, unsigned long parent_rate); -struct clk *tegra_clk_register_plle_tegra114(const char *name, +struct clk_core *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); -struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, +struct clk_core *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); @@ -325,7 +325,7 @@ struct tegra_clk_pll_out { #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) extern const struct clk_ops tegra_clk_pll_out_ops; -struct clk *tegra_clk_register_pll_out(const char *name, +struct clk_core *tegra_clk_register_pll_out(const char *name, const char *parent_name, void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, spinlock_t *lock); @@ -394,7 +394,7 @@ struct tegra_clk_periph_gate { #define TEGRA_PERIPH_NO_GATE BIT(5) extern const struct clk_ops tegra_clk_periph_gate_ops; -struct clk *tegra_clk_register_periph_gate(const char *name, +struct clk_core *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt); @@ -427,11 +427,11 @@ struct tegra_clk_periph { #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 extern const struct clk_ops tegra_clk_periph_ops; -struct clk *tegra_clk_register_periph(const char *name, +struct clk_core *tegra_clk_register_periph(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset, unsigned long flags); -struct clk *tegra_clk_register_periph_nodiv(const char *name, +struct clk_core *tegra_clk_register_periph_nodiv(const char *name, const char **parent_names, int num_parents, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset); @@ -540,7 +540,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) extern const struct clk_ops tegra_clk_super_ops; -struct clk *tegra_clk_register_super_mux(const char *name, +struct clk_core *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); @@ -590,15 +590,15 @@ struct tegra_devclk { }; void tegra_init_from_table(struct tegra_clk_init_table *tbl, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, - struct clk *clks[], int clk_max); + struct clk_core *clks[], int clk_max); struct tegra_clk_periph_regs *get_reg_bank(int clkid); -struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); +struct clk_core **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); -struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); +struct clk_core **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); void tegra_add_of_provider(struct device_node *np); void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index 72d9727..a162c21 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -135,10 +135,10 @@ static void __init omap_clk_register_apll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *ad = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - ad->clk_ref = of_clk_get(node, 0); - ad->clk_bypass = of_clk_get(node, 1); + ad->clk_ref = of_clk_provider_get(node, 0); + ad->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) { pr_debug("clk-ref or clk-bypass for %s not ready, retry\n", @@ -332,7 +332,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) struct dpll_data *ad = NULL; struct clk_hw_omap *clk_hw = NULL; struct clk_init_data *init = NULL; - struct clk *clk; + struct clk_core *clk; const char *parent_name; u32 val; diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c index c808ab3..a48fe6f 100644 --- a/drivers/clk/ti/clk-2xxx.c +++ b/drivers/clk/ti/clk-2xxx.c @@ -237,10 +237,10 @@ static int __init omap2xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "dpll_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "mpu_ck")) / 1000000)); return 0; } diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 028b337..0988f1e 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -121,7 +121,7 @@ static const char *enable_init_clks[] = { int __init am33xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am33xx_clks); @@ -139,12 +139,12 @@ int __init am33xx_dt_clk_init(void) * oscillator clock. */ - clk1 = clk_get_sys(NULL, "sys_clkin_ck"); - clk2 = clk_get_sys(NULL, "timer3_fck"); - clk_set_parent(clk2, clk1); + clk1 = clk_provider_get_sys(NULL, "sys_clkin_ck"); + clk2 = clk_provider_get_sys(NULL, "timer3_fck"); + clk_provider_set_parent(clk2, clk1); - clk2 = clk_get_sys(NULL, "timer6_fck"); - clk_set_parent(clk2, clk1); + clk2 = clk_provider_get_sys(NULL, "timer6_fck"); + clk_provider_set_parent(clk2, clk1); /* * The On-Chip 32K RC Osc clock is not an accurate clock-source as per * the design/spec, so as a result, for example, timer which supposed @@ -152,9 +152,9 @@ int __init am33xx_dt_clk_init(void) * not expected by any use-case, so change WDT1 clock source to PRCM * 32KHz clock. */ - clk1 = clk_get_sys(NULL, "wdt1_fck"); - clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "wdt1_fck"); + clk2 = clk_provider_get_sys(NULL, "clkdiv32k_ick"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 0d1750a..58ef20e 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -365,10 +365,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type) ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, - (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), - (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, + (clk_provider_get_rate(clk_provider_get_sys(NULL, "core_ck")) / 1000000), + (clk_provider_get_rate(clk_provider_get_sys(NULL, "arm_fck")) / 1000000)); if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) omap3_clk_lock_dpll5(); diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 3795fce..1277452 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -116,7 +116,7 @@ static struct ti_dt_clk am43xx_clks[] = { int __init am43xx_dt_clk_init(void) { - struct clk *clk1, *clk2; + struct clk_core *clk1, *clk2; ti_dt_clocks_register(am43xx_clks); @@ -132,9 +132,9 @@ int __init am43xx_dt_clk_init(void) * By selecting dpll_core_m5_ck as the clocksource fixes this issue. * In AM335x dpll_core_m5_ck is the default clocksource. */ - clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); - clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); - clk_set_parent(clk1, clk2); + clk1 = clk_provider_get_sys(NULL, "cpsw_cpts_rft_clk"); + clk2 = clk_provider_get_sys(NULL, "dpll_core_m5_ck"); + clk_provider_set_parent(clk1, clk2); return 0; } diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 02517a8..1adc399 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -281,7 +281,7 @@ static struct ti_dt_clk omap44xx_clks[] = { int __init omap4xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap44xx_clks); @@ -291,8 +291,8 @@ int __init omap4xxx_dt_clk_init(void) * Lock USB DPLL on OMAP4 devices so that the L3INIT power * domain can transition to retention state when not in use. */ - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); @@ -302,12 +302,12 @@ int __init omap4xxx_dt_clk_init(void) * locking the ABE DPLL on boot. * Lock the ABE DPLL in any case to avoid issues with audio. */ - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_refclk_mux_ck"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 5e18399..5b603b5 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -225,34 +225,35 @@ static struct ti_dt_clk omap54xx_clks[] = { int __init omap5xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + struct clk_core *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap54xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); - sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); - rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); - abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_ref = clk_provider_get_sys(NULL, "abe_dpll_clk_mux"); + sys_32k_ck = clk_provider_get_sys(NULL, "sys_32k_ck"); + rc = clk_provider_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); + abe_dpll = clk_provider_get_sys(NULL, "dpll_abe_m2x2_ck"); if (!rc) - rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); + rc = clk_provider_set_rate(abe_dpll, + OMAP5_DPLL_ABE_DEFFREQ * 2); if (rc) pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); if (rc) pr_err("%s: failed to configure USB DPLL!\n", __func__); - usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); - rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); + usb_dpll = clk_provider_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_provider_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ / 2); if (rc) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index e158133..02e5598 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -306,24 +306,24 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + struct clk_core *abe_dpll_mux, *sys_clkin2, *dpll_ck; ti_dt_clocks_register(dra7xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); - sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); - dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); + abe_dpll_mux = clk_provider_get_sys(NULL, "abe_dpll_sys_clk_mux"); + sys_clkin2 = clk_provider_get_sys(NULL, "sys_clkin2"); + dpll_ck = clk_provider_get_sys(NULL, "dpll_abe_ck"); - rc = clk_set_parent(abe_dpll_mux, sys_clkin2); + rc = clk_provider_set_parent(abe_dpll_mux, sys_clkin2); if (!rc) - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); + dpll_ck = clk_provider_get_sys(NULL, "dpll_gmac_ck"); + rc = clk_provider_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); if (rc) pr_err("%s: failed to configure GMAC DPLL!\n", __func__); diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index 4a65b41..029a0d3 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c @@ -40,7 +40,7 @@ struct dra7_atl_clock_info; struct dra7_atl_desc { - struct clk *clk; + struct clk_core *clk; struct clk_hw hw; struct dra7_atl_clock_info *cinfo; int id; @@ -165,7 +165,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) struct dra7_atl_desc *clk_hw = NULL; struct clk_init_data init = { 0 }; const char **parent_names = NULL; - struct clk *clk; + struct clk_core *clk; clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); if (!clk_hw) { @@ -233,7 +233,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) char prop[5]; struct dra7_atl_desc *cdesc; struct of_phandle_args clkspec; - struct clk *clk; + struct clk_core *clk; int rc; rc = of_parse_phandle_with_args(node, "ti,provided-clocks", diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index b1a6f71..d88a70d0 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -41,7 +41,7 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) { struct ti_dt_clk *c; struct device_node *node; - struct clk *clk; + struct clk_core *clk; struct of_phandle_args clkspec; for (c = oclks; c->node_name != NULL; c++) { diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index f1e0038..6bc75d8 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -26,7 +26,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw *clk_hw; const char *clkdm_name = node->name; int i; @@ -35,7 +35,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells"); for (i = 0; i < num_clks; i++) { - clk = of_clk_get(node, i); + clk = of_clk_provider_get(node, i); if (__clk_get_flags(clk) & CLK_IS_BASIC) { pr_warn("can't setup clkdm for basic clk %s\n", __clk_get_name(clk)); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index 19d8980..2cbee34 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -119,7 +119,7 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) static void __init ti_clk_register_composite(struct clk_hw *hw, struct device_node *node) { - struct clk *clk; + struct clk_core *clk; struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); struct component_clk *comp; int num_parents = 0; diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index e6aa10d..1c41515 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -246,7 +246,7 @@ const struct clk_ops ti_clk_divider_ops = { .set_rate = ti_clk_divider_set_rate, }; -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk_core *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, @@ -254,7 +254,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, spinlock_t *lock) { struct clk_divider *div; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { @@ -434,7 +434,7 @@ static int __init ti_clk_divider_populate(struct device_node *node, */ static void __init of_ti_divider_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *parent_name; void __iomem *reg; u8 clk_divider_flags = 0; diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 79791e1..e1f74cc 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -128,10 +128,10 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw, { struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *dd = clk_hw->dpll_data; - struct clk *clk; + struct clk_core *clk; - dd->clk_ref = of_clk_get(node, 0); - dd->clk_bypass = of_clk_get(node, 1); + dd->clk_ref = of_clk_provider_get(node, 0); + dd->clk_bypass = of_clk_provider_get(node, 1); if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) { pr_debug("clk-ref or clk-bypass missing for %s, retry later\n", @@ -175,7 +175,7 @@ static void ti_clk_register_dpll_x2(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *name = node->name; diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c index c2c8a28..2aa2701 100644 --- a/drivers/clk/ti/fixed-factor.c +++ b/drivers/clk/ti/fixed-factor.c @@ -33,7 +33,7 @@ */ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; const char *clk_name = node->name; const char *parent_name; u32 div, mult; diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index b326d27..dd1b813 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -94,7 +94,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, const struct clk_ops *ops, const struct clk_hw_omap_ops *hw_ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *clk_name = node->name; diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c index 9c3e8c4..e2f2bc0 100644 --- a/drivers/clk/ti/interface.c +++ b/drivers/clk/ti/interface.c @@ -34,7 +34,7 @@ static const struct clk_ops ti_interface_clk_ops = { static void __init _of_ti_interface_clk_setup(struct device_node *node, const struct clk_hw_omap_ops *ops) { - struct clk *clk; + struct clk_core *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; const char *parent_name; diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index e9d650e..7456198 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -104,14 +104,14 @@ const struct clk_ops ti_clk_mux_ops = { .determine_rate = __clk_mux_determine_rate, }; -static struct clk *_register_mux(struct device *dev, const char *name, +static struct clk_core *_register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; + struct clk_core *clk; struct clk_init_data init; /* allocate the mux */ @@ -152,7 +152,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, */ static void of_mux_clk_setup(struct device_node *node) { - struct clk *clk; + struct clk_core *clk; void __iomem *reg; int num_parents; const char **parent_names; diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c index e7bd62c..dabb8e6 100644 --- a/drivers/clk/ux500/abx500-clk.c +++ b/drivers/clk/ux500/abx500-clk.c @@ -23,7 +23,7 @@ static int ab8500_reg_clks(struct device *dev) { int ret; - struct clk *clk; + struct clk_core *clk; const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"}; u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1}; diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c index bd4769a..7eb055f 100644 --- a/drivers/clk/ux500/clk-prcc.c +++ b/drivers/clk/ux500/clk-prcc.c @@ -92,7 +92,7 @@ static struct clk_ops clk_prcc_kclk_ops = { .is_enabled = clk_prcc_is_enabled, }; -static struct clk *clk_reg_prcc(const char *name, +static struct clk_core *clk_reg_prcc(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -101,7 +101,7 @@ static struct clk *clk_reg_prcc(const char *name, { struct clk_prcc *clk; struct clk_init_data clk_prcc_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcc: %s invalid arguments passed\n", __func__); @@ -142,7 +142,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, @@ -152,7 +152,7 @@ struct clk *clk_reg_prcc_pclk(const char *name, &clk_prcc_pclk_ops); } -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index e2d63bc..bac54c9 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -243,7 +243,7 @@ static struct clk_ops clk_prcmu_opp_volt_scalable_ops = { .set_rate = clk_prcmu_set_rate, }; -static struct clk *clk_reg_prcmu(const char *name, +static struct clk_core *clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -252,7 +252,7 @@ static struct clk *clk_reg_prcmu(const char *name, { struct clk_prcmu *clk; struct clk_init_data clk_prcmu_init; - struct clk *clk_reg; + struct clk_core *clk_reg; if (!name) { pr_err("clk_prcmu: %s invalid arguments passed\n", __func__); @@ -292,7 +292,7 @@ free_clk: return ERR_PTR(-ENOMEM); } -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -302,7 +302,7 @@ struct clk *clk_reg_prcmu_scalable(const char *name, &clk_prcmu_scalable_ops); } -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -311,7 +311,7 @@ struct clk *clk_reg_prcmu_gate(const char *name, &clk_prcmu_gate_ops); } -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, @@ -321,7 +321,7 @@ struct clk *clk_reg_prcmu_scalable_rate(const char *name, &clk_prcmu_scalable_rate_ops); } -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -330,7 +330,7 @@ struct clk *clk_reg_prcmu_rate(const char *name, &clk_prcmu_rate_ops); } -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) @@ -339,7 +339,7 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name, &clk_prcmu_opp_gate_ops); } -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c index e364c9d..dc6608a 100644 --- a/drivers/clk/ux500/clk-sysctrl.c +++ b/drivers/clk/ux500/clk-sysctrl.c @@ -114,7 +114,7 @@ static struct clk_ops clk_sysctrl_set_parent_ops = { .get_parent = clk_sysctrl_get_parent, }; -static struct clk *clk_reg_sysctrl(struct device *dev, +static struct clk_core *clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, @@ -128,7 +128,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, { struct clk_sysctrl *clk; struct clk_init_data clk_sysctrl_init; - struct clk *clk_reg; + struct clk_core *clk_reg; int i; if (!dev) @@ -176,7 +176,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev, return clk_reg; } -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -193,7 +193,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, flags, &clk_sysctrl_gate_ops); } -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -212,7 +212,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, &clk_sysctrl_gate_fixed_rate_ops); } -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h index a2bb92d..da40a2d 100644 --- a/drivers/clk/ux500/clk.h +++ b/drivers/clk/ux500/clk.h @@ -14,52 +14,52 @@ #include <linux/device.h> #include <linux/types.h> -struct clk *clk_reg_prcc_pclk(const char *name, +struct clk_core *clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcc_kclk(const char *name, +struct clk_core *clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable(const char *name, +struct clk_core *clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_gate(const char *name, +struct clk_core *clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_scalable_rate(const char *name, +struct clk_core *clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_prcmu_rate(const char *name, +struct clk_core *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_gate(const char *name, +struct clk_core *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags); -struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, +struct clk_core *clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags); -struct clk *clk_reg_sysctrl_gate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -68,7 +68,7 @@ struct clk *clk_reg_sysctrl_gate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, +struct clk_core *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, @@ -78,7 +78,7 @@ struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, unsigned long enable_delay_us, unsigned long flags); -struct clk *clk_reg_sysctrl_set_parent(struct device *dev, +struct clk_core *clk_reg_sysctrl_set_parent(struct device *dev, const char *name, const char **parent_names, u8 num_parents, diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 80069c3..8a2b4bc 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -19,7 +19,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, { struct prcmu_fw_version *fw_version; const char *sgaclk_parent = NULL; - struct clk *clk; + struct clk_core *clk; /* Clock sources */ clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c index 7b55ef8..afda303 100644 --- a/drivers/clk/ux500/u8500_of_clk.c +++ b/drivers/clk/ux500/u8500_of_clk.c @@ -18,9 +18,9 @@ #define PRCC_NUM_PERIPH_CLUSTERS 6 #define PRCC_PERIPHS_PER_CLUSTER 32 -static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; -static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; -static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcmu_clk[PRCMU_NUM_CLKS]; +static struct clk_core *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; +static struct clk_core *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; #define PRCC_SHOW(clk, base, bit) \ clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] @@ -29,10 +29,10 @@ static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_C #define PRCC_KCLK_STORE(clk, base, bit) \ prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk -static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, +static struct clk_core *ux500_twocell_get(struct of_phandle_args *clkspec, void *data) { - struct clk **clk_data = data; + struct clk_core **clk_data = data; unsigned int base, bit; if (clkspec->args_count != 2) @@ -61,7 +61,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, struct device_node *np = NULL; struct device_node *child = NULL; const char *sgaclk_parent = NULL; - struct clk *clk, *rtc_clk, *twd_clk; + struct clk_core *clk, *rtc_clk, *twd_clk; if (of_have_populated_dt()) np = of_find_matching_node(NULL, u8500_clk_of_match); diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c index 20c8add..897daf6 100644 --- a/drivers/clk/ux500/u8540_clk.c +++ b/drivers/clk/ux500/u8540_clk.c @@ -17,7 +17,7 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, u32 clkrst5_base, u32 clkrst6_base) { - struct clk *clk; + struct clk_core *clk; /* Clock sources. */ /* Fixed ClockGen */ diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index bc96f10..8df4acc 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -121,13 +121,13 @@ static const struct clk_ops icst_ops = { .set_rate = icst_set_rate, }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, void __iomem *base) { - struct clk *clk; + struct clk_core *clk; struct clk_icst *icst; struct clk_init_data init; struct icst_params *pclone; diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h index 04e6f0a..ede867b 100644 --- a/drivers/clk/versatile/clk-icst.h +++ b/drivers/clk/versatile/clk-icst.h @@ -13,7 +13,7 @@ struct clk_icst_desc { u32 lock_offset; }; -struct clk *icst_clk_register(struct device *dev, +struct clk_core *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, const char *name, const char *parent_name, diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c index 1cc1330..6b35629 100644 --- a/drivers/clk/versatile/clk-impd1.c +++ b/drivers/clk/versatile/clk-impd1.c @@ -21,18 +21,18 @@ struct impd1_clk { char *pclkname; - struct clk *pclk; + struct clk_core *pclk; char *vco1name; - struct clk *vco1clk; + struct clk_core *vco1clk; char *vco2name; - struct clk *vco2clk; - struct clk *mmciclk; + struct clk_core *vco2clk; + struct clk_core *mmciclk; char *uartname; - struct clk *uartclk; + struct clk_core *uartclk; char *spiname; - struct clk *spiclk; + struct clk_core *spiclk; char *scname; - struct clk *scclk; + struct clk_core *scclk; struct clk_lookup *clks[15]; }; @@ -87,8 +87,8 @@ static const struct clk_icst_desc impd1_icst2_desc = { void integrator_impd1_clk_init(void __iomem *base, unsigned int id) { struct impd1_clk *imc; - struct clk *clk; - struct clk *pclk; + struct clk_core *clk; + struct clk_core *pclk; int i; if (id > 3) { diff --git a/drivers/clk/versatile/clk-integrator.c b/drivers/clk/versatile/clk-integrator.c index 734c4b8..dbcaa7b 100644 --- a/drivers/clk/versatile/clk-integrator.c +++ b/drivers/clk/versatile/clk-integrator.c @@ -39,7 +39,7 @@ static const struct clk_icst_desc __initdata cm_auxosc_desc = { static void __init of_integrator_cm_osc_setup(struct device_node *np) { - struct clk *clk = ERR_PTR(-EINVAL); + struct clk_core *clk = ERR_PTR(-EINVAL); const char *clk_name = np->name; const struct clk_icst_desc *desc = &cm_auxosc_desc; const char *parent_name; diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c index c8b5231..4fa61b3 100644 --- a/drivers/clk/versatile/clk-realview.c +++ b/drivers/clk/versatile/clk-realview.c @@ -50,7 +50,7 @@ static const struct clk_icst_desc __initdata realview_osc4_desc = { */ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176) { - struct clk *clk; + struct clk_core *clk; /* APB clock dummy */ clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); diff --git a/drivers/clk/versatile/clk-sp810.c b/drivers/clk/versatile/clk-sp810.c index c6e86a9..9256d25 100644 --- a/drivers/clk/versatile/clk-sp810.c +++ b/drivers/clk/versatile/clk-sp810.c @@ -25,7 +25,7 @@ struct clk_sp810; struct clk_sp810_timerclken { struct clk_hw hw; - struct clk *clk; + struct clk_core *clk; struct clk_sp810 *sp810; int channel; }; @@ -36,8 +36,8 @@ struct clk_sp810 { void __iomem *base; spinlock_t lock; struct clk_sp810_timerclken timerclken[4]; - struct clk *refclk; - struct clk *timclk; + struct clk_core *refclk; + struct clk_core *timclk; }; static u8 clk_sp810_timerclken_get_parent(struct clk_hw *hw) @@ -79,29 +79,31 @@ static int clk_sp810_timerclken_prepare(struct clk_hw *hw) { struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - struct clk *old_parent = __clk_get_parent(hw->clk); - struct clk *new_parent; + struct clk_core *old_parent = __clk_get_parent(hw->clk); + struct clk_core *new_parent; if (!sp810->refclk) - sp810->refclk = of_clk_get(sp810->node, sp810->refclk_index); + sp810->refclk = of_clk_provider_get(sp810->node, + sp810->refclk_index); if (!sp810->timclk) - sp810->timclk = of_clk_get(sp810->node, sp810->timclk_index); + sp810->timclk = of_clk_provider_get(sp810->node, + sp810->timclk_index); if (WARN_ON(IS_ERR(sp810->refclk) || IS_ERR(sp810->timclk))) return -ENOENT; /* Select fastest parent */ - if (clk_get_rate(sp810->refclk) > clk_get_rate(sp810->timclk)) + if (clk_provider_get_rate(sp810->refclk) > clk_provider_get_rate(sp810->timclk)) new_parent = sp810->refclk; else new_parent = sp810->timclk; /* Switch the parent if necessary */ if (old_parent != new_parent) { - clk_prepare(new_parent); - clk_set_parent(hw->clk, new_parent); - clk_unprepare(old_parent); + clk_provider_prepare(new_parent); + clk_provider_set_parent(hw->clk, new_parent); + clk_provider_unprepare(old_parent); } return 0; @@ -112,8 +114,8 @@ static void clk_sp810_timerclken_unprepare(struct clk_hw *hw) struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; - clk_put(sp810->timclk); - clk_put(sp810->refclk); + __clk_put(sp810->timclk); + __clk_put(sp810->refclk); } static const struct clk_ops clk_sp810_timerclken_ops = { @@ -123,7 +125,7 @@ static const struct clk_ops clk_sp810_timerclken_ops = { .set_parent = clk_sp810_timerclken_set_parent, }; -static struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, +static struct clk_core *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, void *data) { struct clk_sp810 *sp810 = data; diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c index 529a59c..c9e175f 100644 --- a/drivers/clk/versatile/clk-vexpress-osc.c +++ b/drivers/clk/versatile/clk-vexpress-osc.c @@ -73,7 +73,7 @@ static int vexpress_osc_probe(struct platform_device *pdev) struct clk_lookup *cl = pdev->dev.platform_data; /* Non-DT lookup */ struct clk_init_data init; struct vexpress_osc *osc; - struct clk *clk; + struct clk_core *clk; u32 range[2]; osc = devm_kzalloc(&pdev->dev, sizeof(*osc), GFP_KERNEL); diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c index 2d5e1b4..e77f3d5 100644 --- a/drivers/clk/versatile/clk-vexpress.c +++ b/drivers/clk/versatile/clk-vexpress.c @@ -17,7 +17,7 @@ #include <linux/err.h> #include <linux/vexpress.h> -static struct clk *vexpress_sp810_timerclken[4]; +static struct clk_core *vexpress_sp810_timerclken[4]; static DEFINE_SPINLOCK(vexpress_sp810_lock); static void __init vexpress_sp810_init(void __iomem *base) @@ -54,7 +54,7 @@ static const char * const vexpress_clk_24mhz_periphs[] __initconst = { void __init vexpress_clk_init(void __iomem *sp810_base) { - struct clk *clk; + struct clk_core *clk; int i; clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, @@ -77,7 +77,7 @@ void __init vexpress_clk_init(void __iomem *sp810_base) vexpress_sp810_init(sp810_base); for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++) - WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk)); + WARN_ON(clk_provider_set_parent(vexpress_sp810_timerclken[i], clk)); WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0], "v2m-timer0", "sp804")); diff --git a/drivers/clk/x86/clk-lpt.c b/drivers/clk/x86/clk-lpt.c index 812f83f..1b4a5e1 100644 --- a/drivers/clk/x86/clk-lpt.c +++ b/drivers/clk/x86/clk-lpt.c @@ -21,7 +21,7 @@ static int lpt_clk_probe(struct platform_device *pdev) { struct lpss_clk_data *drvdata; - struct clk *clk; + struct clk_core *clk; drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 246cf12..0efdd9a 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -67,8 +67,8 @@ enum zynq_clk { i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; -static struct clk *ps_clk; -static struct clk *clks[clk_max]; +static struct clk_core *ps_clk; +static struct clk_core *clks[clk_max]; static struct clk_onecell_data clk_data; static DEFINE_SPINLOCK(armpll_lock); @@ -108,7 +108,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, const char **parents, int enable) { - struct clk *clk; + struct clk_core *clk; u32 enable_reg; char *mux_name; char *div0_name; @@ -154,7 +154,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); enable_reg = clk_readl(fclk_gate_reg) & 1; if (enable && !enable_reg) { - if (clk_prepare_enable(clks[fclk])) + if (clk_provider_prepare_enable(clks[fclk])) pr_warn("%s: FCLK%u enable failed\n", __func__, fclk - fclk0); } @@ -181,7 +181,7 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, const char *clk_name1, void __iomem *clk_ctrl, const char **parents, unsigned int two_gates) { - struct clk *clk; + struct clk_core *clk; char *mux_name; char *div_name; spinlock_t *lock; @@ -222,7 +222,7 @@ static void __init zynq_clk_setup(struct device_node *np) int i; u32 tmp; int ret; - struct clk *clk; + struct clk_core *clk; char *clk_name; unsigned int fclk_enable = 0; const char *clk_output_name[clk_max]; @@ -333,13 +333,13 @@ static void __init zynq_clk_setup(struct device_node *np) CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr2x]); + clk_provider_prepare_enable(clks[ddr2x]); clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); - clk_prepare_enable(clks[ddr3x]); + clk_provider_prepare_enable(clks[ddr3x]); clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | @@ -351,7 +351,7 @@ static void __init zynq_clk_setup(struct device_node *np) clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, &dciclk_lock); - clk_prepare_enable(clks[dci]); + clk_provider_prepare_enable(clks[dci]); /* Peripheral clocks */ for (i = fclk0; i <= fclk3; i++) { @@ -505,10 +505,10 @@ static void __init zynq_clk_setup(struct device_node *np) /* leave debug clocks in the state the bootloader set them up to */ tmp = clk_readl(SLCR_DBG_CLK_CTRL); if (tmp & DBG_CLK_CTRL_CLKACT_TRC) - if (clk_prepare_enable(clks[dbg_trc])) + if (clk_provider_prepare_enable(clks[dbg_trc])) pr_warn("%s: trace clk enable failed\n", __func__); if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) - if (clk_prepare_enable(clks[dbg_apb])) + if (clk_provider_prepare_enable(clks[dbg_apb])) pr_warn("%s: debug APB clk enable failed\n", __func__); /* One gated clock for all APER clocks. */ diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c index cec9759..5176f65 100644 --- a/drivers/clk/zynq/pll.c +++ b/drivers/clk/zynq/pll.c @@ -193,12 +193,12 @@ static const struct clk_ops zynq_pll_ops = { * @lock Register lock * Returns handle to the registered clock. */ -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock) { struct zynq_pll *pll; - struct clk *clk; + struct clk_core *clk; u32 reg; const char *parent_arr[1] = {parent}; unsigned long flags = 0; diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index 2620c48..c2461af 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -215,7 +215,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) { - ret = clk_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); + ret = clk_provider_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); if (ret < 0) return ret; } @@ -225,7 +225,7 @@ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, return 0; if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret; } @@ -254,7 +254,7 @@ static int __fimc_pipeline_close(struct exynos_media_pipeline *ep) /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) - clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); + clk_provider_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret == -ENXIO ? 0 : ret; } @@ -954,7 +954,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) while (--i >= 0) { if (IS_ERR(fmd->camclk[i].clock)) continue; - clk_put(fmd->camclk[i].clock); + __clk_put(fmd->camclk[i].clock); fmd->camclk[i].clock = ERR_PTR(-EINVAL); } @@ -962,7 +962,7 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_WBCLKS; i++) { if (IS_ERR(fmd->wbclk[i])) continue; - clk_put(fmd->wbclk[i]); + __clk_put(fmd->wbclk[i]); fmd->wbclk[i] = ERR_PTR(-EINVAL); } } @@ -971,7 +971,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) { struct device *dev = &fmd->pdev->dev; char clk_name[32]; - struct clk *clock; + struct clk_core *clock; int i, ret = 0; for (i = 0; i < FIMC_MAX_CAMCLKS; i++) @@ -979,7 +979,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = 0; i < FIMC_MAX_CAMCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { dev_err(dev, "Failed to get clock: %s\n", clk_name); @@ -1001,7 +1001,7 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) for (i = CLK_IDX_WB_B; i < FIMC_MAX_WBCLKS; i++) { snprintf(clk_name, sizeof(clk_name), "pxl_async%u", i); - clock = clk_get(dev, clk_name); + clock = clk_provider_get(dev, clk_name); if (IS_ERR(clock)) { v4l2_err(&fmd->v4l2_dev, "Failed to get clock: %s\n", clk_name); diff --git a/drivers/media/platform/exynos4-is/media-dev.h b/drivers/media/platform/exynos4-is/media-dev.h index 0321454..79e4b42 100644 --- a/drivers/media/platform/exynos4-is/media-dev.h +++ b/drivers/media/platform/exynos4-is/media-dev.h @@ -72,7 +72,7 @@ struct fimc_csis_info { }; struct fimc_camclk_info { - struct clk *clock; + struct clk_core *clock; int use_count; unsigned long frequency; }; @@ -124,7 +124,7 @@ struct fimc_md { struct fimc_sensor_info sensor[FIMC_MAX_SENSORS]; int num_sensors; struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS]; - struct clk *wbclk[FIMC_MAX_WBCLKS]; + struct clk_core *wbclk[FIMC_MAX_WBCLKS]; struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS]; struct fimc_dev *fimc[FIMC_MAX_DEVS]; struct fimc_is *fimc_is; @@ -141,7 +141,7 @@ struct fimc_md { } pinctl; struct cam_clk_provider { - struct clk *clks[FIMC_MAX_CAMCLKS]; + struct clk_core *clks[FIMC_MAX_CAMCLKS]; struct clk_onecell_data clk_data; struct device_node *of_node; struct cam_clk camclk[FIMC_MAX_CAMCLKS]; diff --git a/include/asm-generic/clkdev.h b/include/asm-generic/clkdev.h index 90a32a6..16d43d9 100644 --- a/include/asm-generic/clkdev.h +++ b/include/asm-generic/clkdev.h @@ -17,8 +17,8 @@ struct clk; -static inline int __clk_get(struct clk *clk) { return 1; } -static inline void __clk_put(struct clk *clk) { } +static inline int __clk_get(struct clk_core *clk) { return 1; } +static inline void __clk_put(struct clk_core *clk) { } static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) { diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index e8d8a35..6b9e6b4 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -22,8 +22,8 @@ * @mult_div1_reg: register containing the DPLL M and N bitfields * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input + * @clk_bypass: struct clk_core pointer to the clock's bypass clock input + * @clk_ref: struct clk_core pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() @@ -68,8 +68,8 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; + struct clk_core *clk_bypass; + struct clk_core *clk_ref; void __iomem *control_reg; u32 enable_mask; unsigned long last_rounded_rate; @@ -251,7 +251,7 @@ extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) -void omap2_init_clk_hw_omap_clocks(struct clk *clk); +void omap2_init_clk_hw_omap_clocks(struct clk_core *clk); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h index a990a59..6c35291 100644 --- a/include/linux/clk/zynq.h +++ b/include/linux/clk/zynq.h @@ -25,7 +25,7 @@ void zynq_clock_init(void); -struct clk *clk_register_zynq_pll(const char *name, const char *parent, +struct clk_core *clk_register_zynq_pll(const char *name, const char *parent, void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, spinlock_t *lock); #endif diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index a947ab8..4b34c69 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -107,8 +107,8 @@ struct si5351_clkout_config { * @clkout: array of clkout configuration */ struct si5351_platform_data { - struct clk *clk_xtal; - struct clk *clk_clkin; + struct clk_core *clk_xtal; + struct clk_core *clk_clkin; enum si5351_pll_src pll_src[2]; struct si5351_clkout_config clkout[8]; }; -- 1.9.3

2 1

[alsa-devel] [PATCH] ASoC: arizona: Fix TDM slot length handling in arizona_hw_params
by Charles Keepax 13 Aug '14

13 Aug '14

From: Nikesh Oswal <Nikesh.Oswal(a)wolfsonmicro.com> TDM slot length was set same as word length, regardless of the value received in set_tdm_slot. This patch sets the TDM slot length correctly as received in set_tdm_slot DAI callback Signed-off-by: Nikesh Oswal <Nikesh.Oswal(a)wolfsonmicro.com> Signed-off-by: Charles Keepax <ckeepax(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/arizona.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c index 2f2e91a..4dfab95 100644 --- a/sound/soc/codecs/arizona.c +++ b/sound/soc/codecs/arizona.c @@ -1278,6 +1278,8 @@ static int arizona_hw_params(struct snd_pcm_substream *substream, else rates = &arizona_48k_bclk_rates[0]; + wl = snd_pcm_format_width(params_format(params)); + if (tdm_slots) { arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n", tdm_slots, tdm_width); @@ -1285,6 +1287,7 @@ static int arizona_hw_params(struct snd_pcm_substream *substream, channels = tdm_slots; } else { bclk_target = snd_soc_params_to_bclk(params); + tdm_width = wl; } if (chan_limit && chan_limit < channels) { @@ -1319,8 +1322,7 @@ static int arizona_hw_params(struct snd_pcm_substream *substream, arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n", rates[bclk], rates[bclk] / lrclk); - wl = snd_pcm_format_width(params_format(params)); - frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl; + frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width; reconfig = arizona_aif_cfg_changed(codec, base, bclk, lrclk, frame); -- 1.7.2.5

2 1

[alsa-devel] [PATCH - pcm_jack plugin 1/1] Restore PID to jack client name when not specified explicitly
by branan＠gmail.com 12 Aug '14

12 Aug '14

From: Branan Purvine-Riley <branan(a)gmail.com> Commit 14190cd8 added a facility to explicitly name Jack clients with a 'name' option, but did so in a way that was not fully backwards-compatible with older versions of the alsa-plugins. There were two issues: 1. Re-using the magical "name" variable, which comes preloaded with the name of the PCM 2. The code assumed snd_config_get_string sets a variable to NULL if the config entry does not exist. Instead, this function leaves the variable unchanged. The result of these two errors meant that the PCM name would be treated as if it were a user-defined name, and the old code which embedded the PID would never be run This code uses a completely new variable to store the explicitly-set client name, so that the two code paths no longer collide. Signed-off-by: Branan Purvine-Riley <branan(a)gmail.com> diff --git a/jack/pcm_jack.c b/jack/pcm_jack.c index f5b7129..33f87b1 100644 --- a/jack/pcm_jack.c +++ b/jack/pcm_jack.c @@ -372,6 +372,7 @@ static int make_nonblock(int fd) } static int snd_pcm_jack_open(snd_pcm_t **pcmp, const char *name, + const char* client_name, snd_config_t *playback_conf, snd_config_t *capture_conf, snd_pcm_stream_t stream, int mode) @@ -405,14 +406,14 @@ static int snd_pcm_jack_open(snd_pcm_t **pcmp, const char *name, return -EINVAL; } - if (name == NULL) + if (client_name == NULL) err = snprintf(jack_client_name, sizeof(jack_client_name), "alsa-jack.%s%s.%d.%d", name, stream == SND_PCM_STREAM_PLAYBACK ? "P" : "C", getpid(), num++); else err = snprintf(jack_client_name, sizeof(jack_client_name), - "%s", name); + "%s", client_name); if (err >= (int)sizeof(jack_client_name)) { fprintf(stderr, "%s: WARNING: JACK client name '%s' truncated to %d characters, might not be unique\n", @@ -470,6 +471,7 @@ SND_PCM_PLUGIN_DEFINE_FUNC(jack) snd_config_iterator_t i, next; snd_config_t *playback_conf = NULL; snd_config_t *capture_conf = NULL; + const char* client_name = NULL; int err; snd_config_for_each(i, next, conf) { @@ -480,7 +482,7 @@ SND_PCM_PLUGIN_DEFINE_FUNC(jack) if (strcmp(id, "comment") == 0 || strcmp(id, "type") == 0 || strcmp(id, "hint") == 0) continue; if (strcmp(id, "name") == 0) { - snd_config_get_string(n, &name); + snd_config_get_string(n, &client_name); continue; } if (strcmp(id, "playback_ports") == 0) { @@ -503,7 +505,7 @@ SND_PCM_PLUGIN_DEFINE_FUNC(jack) return -EINVAL; } - err = snd_pcm_jack_open(pcmp, name, playback_conf, capture_conf, stream, mode); + err = snd_pcm_jack_open(pcmp, name, client_name, playback_conf, capture_conf, stream, mode); return err; } -- 2.0.4

2 1

[alsa-devel] [PATCH] sound: pci: es1968: use pci_device_id
by Sudip Mukherjee 12 Aug '14

12 Aug '14

Uses the struct pci_device_id instead of the depreciated macro DEFINE_PCI_DEVICE_TABLE. Signed-off-by: Sudip Mukherjee <sudip(a)vectorindia.org> --- sound/pci/es1968.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/es1968.c b/sound/pci/es1968.c index 5bb1cf6..a9956a7 100644 --- a/sound/pci/es1968.c +++ b/sound/pci/es1968.c @@ -570,7 +570,7 @@ struct es1968 { static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id); -static DEFINE_PCI_DEVICE_TABLE(snd_es1968_ids) = { +static const struct pci_device_id snd_es1968_ids[] = { /* Maestro 1 */ { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO }, /* Maestro 2 */ -- 1.8.1.2

2 3

[alsa-devel] [PATCH] ASoC: wm8994: register irq handler for mic1 detect
by Nikesh Oswal 12 Aug '14

12 Aug '14

Signed-off-by: Nikesh Oswal <nikesh(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm8994.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 247b390..24bcbe3 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -4099,6 +4099,15 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) dev_warn(codec->dev, "Failed to request Mic1 detect IRQ: %d\n", ret); + } else { + ret = wm8994_request_irq(wm8994->wm8994, + WM8994_IRQ_MIC1_DET, + wm8994_mic_irq, "Mic 1 detect", + wm8994); + if (ret != 0) + dev_warn(codec->dev, + "Failed to request Mic1 detect IRQ: %d\n", + ret); } ret = wm8994_request_irq(wm8994->wm8994, -- 1.7.9.5

2 1

[alsa-devel] [PATCH] gpiolib: wm8994: Fix irq offset for gpio_to_irq
by Nikesh Oswal 12 Aug '14

12 Aug '14

Earlier code was using the gpio offset as is to get the irq. For wm8994 driver the gpio related irq's starts from a fixed offset as fixed by this patch. Signed-off-by: Nikesh Oswal <nikesh(a)opensource.wolfsonmicro.com> --- drivers/gpio/gpio-wm8994.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-wm8994.c b/drivers/gpio/gpio-wm8994.c index d93b6b5..dec47c2 100644 --- a/drivers/gpio/gpio-wm8994.c +++ b/drivers/gpio/gpio-wm8994.c @@ -113,7 +113,8 @@ static int wm8994_gpio_to_irq(struct gpio_chip *chip, unsigned offset) struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip); struct wm8994 *wm8994 = wm8994_gpio->wm8994; - return regmap_irq_get_virq(wm8994->irq_data, offset); + return regmap_irq_get_virq(wm8994->irq_data, + WM8994_IRQ_GPIO(offset + 1)); } -- 1.7.9.5

1 0

[alsa-devel] [PATCHv2] ASOC add wm8973 support to wm8971
by Xavier Hsu 12 Aug '14

12 Aug '14

This patch adds support for the wm8973 codec. After the initial comments, we merged wm8973 driver into wm8971 driver. Any comments about improving the patch are welcome. Thanks. Signed-off-by: Xavier Hsu <xavier.hsu(a)linaro.org> Signed-off-by: Andy Green <andy.green(a)linaro.org> --- Documentation/devicetree/bindings/sound/wm8971.txt | 26 + sound/soc/codecs/wm8971.c | 777 +++++++++++++++++--- sound/soc/codecs/wm8971.h | 21 +- 3 files changed, 696 insertions(+), 128 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/wm8971.txt diff --git a/Documentation/devicetree/bindings/sound/wm8971.txt b/Documentation/devicetree/bindings/sound/wm8971.txt new file mode 100644 index 0000000..7313dd1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/wm8971.txt @@ -0,0 +1,26 @@ +WM8971 and WM8973 audio CODEC + +These devices support both I2C and SPI (configured with pin strapping +on the board). + +Required properties: + + - compatible : "wlf,wm8971". + "wlf,wm8973". + + - reg : the I2C address of the device for I2C, the chip select + number for SPI. + +Optional properties: + + - mclk-div : Setting the CLKDIV2 bit for dividing MCLK. + mclk-div = <0> (Default & not divide). + mclk-div = <1> (Divide by 2). + +Example: + +codec: wm8973@1a { + compatible = "wlf,wm8973"; + reg = <0x1a>; + mclk-div = <1>; +}; diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c index 09b7b42..6b1838c 100644 --- a/sound/soc/codecs/wm8971.c +++ b/sound/soc/codecs/wm8971.c @@ -7,6 +7,10 @@ * * Based on wm8753.c by Liam Girdwood * + * WM8973 support Copyright (C) 2014 Linaro, Ltd + * Author: Xavier Hsu <xavier.hsu(a)linaro.org> + * Andy Green <andy.green(a)linaro.org> + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -26,16 +30,31 @@ #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/initval.h> +#include <sound/tlv.h> #include "wm8971.h" -#define WM8971_REG_COUNT 43 +enum variant { + VARIANT_WM8971, + VARIANT_WM8973 +}; -static struct workqueue_struct *wm8971_workq = NULL; +#define WM8971_REG_COUNT 43 /* codec private data */ struct wm8971_priv { + struct regmap *regmap; + enum variant variant; unsigned int sysclk; + struct snd_pcm_hw_constraint_list *sysclk_constraints; + int playback_fs; + bool deemph; + int mclk_div; +}; + +static const u16 charge[][2] = { + [VARIANT_WM8971] = { 0xfe3e, 0x01c0 }, + [VARIANT_WM8973] = { 0x003e, 0x01f0 }, }; /* @@ -91,26 +110,53 @@ static const struct reg_default wm8971_reg_defaults[] = { #define wm8971_reset(c) snd_soc_write(c, WM8971_RESET, 0) -/* WM8971 Controls */ -static const char *wm8971_bass[] = { "Linear Control", "Adaptive Boost" }; -static const char *wm8971_bass_filter[] = { "130Hz @ 48kHz", - "200Hz @ 48kHz" }; -static const char *wm8971_treble[] = { "8kHz", "4kHz" }; -static const char *wm8971_alc_func[] = { "Off", "Right", "Left", "Stereo" }; -static const char *wm8971_ng_type[] = { "Constant PGA Gain", - "Mute ADC Output" }; -static const char *wm8971_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; -static const char *wm8971_mono_mux[] = {"Stereo", "Mono (Left)", - "Mono (Right)", "Digital Mono"}; -static const char *wm8971_dac_phase[] = { "Non Inverted", "Inverted" }; -static const char *wm8971_lline_mux[] = {"Line", "NC", "NC", "PGA", - "Differential"}; -static const char *wm8971_rline_mux[] = {"Line", "Mic", "NC", "PGA", - "Differential"}; -static const char *wm8971_lpga_sel[] = {"Line", "NC", "NC", "Differential"}; -static const char *wm8971_rpga_sel[] = {"Line", "Mic", "NC", "Differential"}; -static const char *wm8971_adcpol[] = {"Normal", "L Invert", "R Invert", - "L + R Invert"}; +/* WM8971 / 3 Controls */ +static const char *wm8971_bass[] += { "Linear Control", "Adaptive Boost" }; +static const char *wm8971_bass_filter[] += { "130Hz @ 48kHz", "200Hz @ 48kHz" }; +static const char *wm8971_treble[] += { "8kHz", "4kHz" }; +static const char *wm8971_alc_func[] += { "Off", "Right", "Left", "Stereo" }; +static const char *wm8971_ng_type[] += { "Constant PGA Gain", "Mute ADC Output" }; +static const char *wm8971_deemp[] += { "None", "32kHz", "44.1kHz", "48kHz" }; +static const char *wm8971_mono_mux[] += {"Stereo", "Mono (Left)", "Mono (Right)", "Digital Mono"}; + +/* WM8971-only */ +static const char *wm8971_dac_phase[] += { "Non Inverted", "Inverted" }; +static const char *wm8971_lline_mux[] += {"Line", "NC", "NC", "PGA", "Differential"}; +static const char *wm8971_rline_mux[] += {"Line", "Mic", "NC", "PGA", "Differential"}; +static const char *wm8971_lpga_sel[] += {"Line", "NC", "NC", "Differential"}; +static const char *wm8971_rpga_sel[] += {"Line", "Mic", "NC", "Differential"}; +static const char *wm8971_adcpol[] += {"Normal", "L Invert", "R Invert", "L + R Invert"}; + +/* WM8973-only */ +static const char const *wm8973_line_mux[] = {"Line 1", "Line 2", "Line 3", + "PGA", "Differential"}; +static const char const *wm8973_pga_sel[] = {"Line 1", "Line 2", "Line 3", + "Differential"}; +static const char const *wm8973_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut", + "ROUT1"}; +static const char const *wm8973_diff_sel[] = {"Line 1", "Line 2"}; +static const char const *wm8973_adcpol[] = {"Normal", "L Invert", "R Invert", + "L + R Invert"}; +static const char const *wm8973_3d_lc[] = { "200Hz", "500Hz" }; +static const char const *wm8973_3d_uc[] = { "2.2kHz", "1.5kHz" }; +static const char const *wm8973_3d_func[] = {"Capture", "Playback"}; + +static const int wm8973_deemph_rates[] = { 0, 32000, 44100, 48000 }; + + static const struct soc_enum wm8971_enum[] = { SOC_ENUM_SINGLE(WM8971_BASS, 7, 2, wm8971_bass), /* 0 */ @@ -136,24 +182,24 @@ static const struct snd_kcontrol_new wm8971_snd_controls[] = { SOC_DOUBLE_R("Capture Switch", WM8971_LINVOL, WM8971_RINVOL, 7, 1, 1), SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8971_LOUT1V, - WM8971_ROUT1V, 7, 1, 0), + WM8971_ROUT1V, 7, 1, 0), SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8971_LOUT2V, - WM8971_ROUT2V, 7, 1, 0), + WM8971_ROUT2V, 7, 1, 0), SOC_SINGLE("Mono Playback ZC Switch", WM8971_MOUTV, 7, 1, 0), SOC_DOUBLE_R("PCM Volume", WM8971_LDAC, WM8971_RDAC, 0, 255, 0), SOC_DOUBLE_R("Bypass Left Playback Volume", WM8971_LOUTM1, - WM8971_LOUTM2, 4, 7, 1), + WM8971_LOUTM2, 4, 7, 1), SOC_DOUBLE_R("Bypass Right Playback Volume", WM8971_ROUTM1, - WM8971_ROUTM2, 4, 7, 1), + WM8971_ROUTM2, 4, 7, 1), SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8971_MOUTM1, - WM8971_MOUTM2, 4, 7, 1), + WM8971_MOUTM2, 4, 7, 1), SOC_DOUBLE_R("Headphone Playback Volume", WM8971_LOUT1V, - WM8971_ROUT1V, 0, 127, 0), + WM8971_ROUT1V, 0, 127, 0), SOC_DOUBLE_R("Speaker Playback Volume", WM8971_LOUT2V, - WM8971_ROUT2V, 0, 127, 0), + WM8971_ROUT2V, 0, 127, 0), SOC_ENUM("Bass Boost", wm8971_enum[0]), SOC_ENUM("Bass Filter", wm8971_enum[1]), @@ -188,6 +234,224 @@ static const struct snd_kcontrol_new wm8971_snd_controls[] = { SOC_DOUBLE_R("Mic Boost", WM8971_LADCIN, WM8971_RADCIN, 4, 3, 0), }; +static int wm8973_set_deemph(struct snd_soc_codec *codec) +{ + struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); + int val = 0, i, best = 0; + + /* If we're using deemphasis select the nearest available sample + * rate. + */ + if (wm8971->deemph) { + best = 1; + for (i = 2; i < ARRAY_SIZE(wm8973_deemph_rates); i++) { + if (abs(wm8973_deemph_rates[i] - wm8971->playback_fs) < + abs(wm8973_deemph_rates[best] - + wm8971->playback_fs)) + best = i; + } + val = best << 1; + } + + dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", + best, wm8973_deemph_rates[best]); + + return snd_soc_update_bits(codec, WM8971_ADCDAC, 0x6, val); +} + +static int wm8973_get_deemph(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = wm8971->deemph; + + return 0; +} + +static int wm8973_put_deemph(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); + int deemph = ucontrol->value.enumerated.item[0]; + int ret = 0; + + if (deemph > 1) + return -EINVAL; + + mutex_lock(&codec->mutex); + if (wm8971->deemph != deemph) { + wm8971->deemph = deemph; + wm8973_set_deemph(codec); + + ret = 1; + } + mutex_unlock(&codec->mutex); + + return ret; +} + +static const DECLARE_TLV_DB_SCALE(in_vol, -1725, 75, 0); +static const DECLARE_TLV_DB_SCALE(out_vol, -6700, 91, 0); +static const DECLARE_TLV_DB_SCALE(attenuate_6db, -600, 600, 0); +static const DECLARE_TLV_DB_SCALE(dac_vol, -12700, 50, 0); +static const DECLARE_TLV_DB_SCALE(tone_vol, -600, 150, 0); +static const DECLARE_TLV_DB_SCALE(alc_tar_vol, -2850, 150, 0); +static const DECLARE_TLV_DB_SCALE(alc_max_vol, -1200, 600, 0); +static const DECLARE_TLV_DB_SCALE(adc_vol, -9700, 50, 0); +static const DECLARE_TLV_DB_SCALE(bypass_out_vol, -1500, 300, 0); + +static const SOC_ENUM_SINGLE_DECL(bass_boost, WM8971_BASS, 7, wm8971_bass); +static const SOC_ENUM_SINGLE_DECL(bass_filter, WM8971_BASS, + 6, wm8971_bass_filter); +static const SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8971_TREBLE, + 6, wm8971_treble); +static const SOC_ENUM_SINGLE_DECL(lower_cutoff, WM8973_3D, 5, wm8973_3d_lc); +static const SOC_ENUM_SINGLE_DECL(upper_cutoff, WM8973_3D, 6, wm8973_3d_uc); +static const SOC_ENUM_SINGLE_DECL(mode, WM8973_3D, 7, wm8973_3d_func); +static const SOC_ENUM_SINGLE_DECL(alc_capture_func, WM8971_ALC1, + 7, wm8971_alc_func); +static const SOC_ENUM_SINGLE_DECL(alc_capture_ngtype, WM8971_NGATE, + 1, wm8971_ng_type); +static const SOC_ENUM_SINGLE_DECL(left_line, WM8971_LOUTM1, + 0, wm8973_line_mux); +static const SOC_ENUM_SINGLE_DECL(right_line, WM8971_ROUTM1, + 0, wm8973_line_mux); +static const SOC_ENUM_SINGLE_DECL(left_pga, WM8971_LADCIN, 6, wm8973_pga_sel); +static const SOC_ENUM_SINGLE_DECL(right_pga, WM8971_RADCIN, 6, wm8973_pga_sel); +static const SOC_ENUM_SINGLE_DECL(out3, WM8971_ADCTL2, 7, wm8973_out3); +static const SOC_ENUM_SINGLE_DECL(diffmux, WM8971_ADCIN, 8, wm8973_diff_sel); +static const SOC_ENUM_SINGLE_DECL(capture_polarity, WM8971_ADCDAC, + 5, wm8973_adcpol); +static const SOC_ENUM_SINGLE_DECL(monomux, WM8971_ADCIN, 6, wm8971_mono_mux); + + +static const struct snd_kcontrol_new wm8973_snd_controls[] = { + /* Left & Right Input volume */ + SOC_DOUBLE_R_TLV("Capture Volume", WM8971_LINVOL, WM8971_RINVOL, + 0, 63, 0, in_vol), + SOC_DOUBLE_R("Capture ZC Switch", WM8971_LINVOL, WM8971_RINVOL, + 6, 1, 0), + SOC_DOUBLE_R("Capture Switch", WM8971_LINVOL, WM8971_RINVOL, 7, 1, 1), + + /* LOUT1 & ROUT1 volume */ + SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8971_LOUT1V, + WM8971_ROUT1V, 0, 127, 0, out_vol), + SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8971_LOUT1V, + WM8971_ROUT1V, 7, 1, 0), + + /* ADC & DAC control */ + SOC_SINGLE("Capture Filter Switch", WM8971_ADCDAC, 0, 1, 1), + SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0, + wm8973_get_deemph, wm8973_put_deemph), + SOC_ENUM("Capture Polarity", capture_polarity), + SOC_SINGLE_TLV("Playback 6dB Attenuate", WM8971_ADCDAC, + 7, 1, 0, attenuate_6db), + SOC_SINGLE_TLV("Capture 6dB Attenuate", WM8971_ADCDAC, + 8, 1, 0, attenuate_6db), + /* ADCDAC Bit 4 - HPOR */ + + /* Left & Right Channel Digital Volume */ + SOC_DOUBLE_R_TLV("DAC Volume", WM8971_LDAC, WM8971_RDAC, + 0, 255, 0, dac_vol), + + /* Bass Control */ + SOC_SINGLE_TLV("Bass Volume", WM8971_BASS, 0, 15, 1, tone_vol), + SOC_ENUM("Bass Boost", bass_boost), + SOC_ENUM("Bass Filter", bass_filter), + + /* Treble Control */ + SOC_SINGLE_TLV("Treble Volume", WM8971_TREBLE, 0, 15, 0, tone_vol), + SOC_ENUM("Treble Cut-off", treble_cutoff), + + /* 3D Control */ + SOC_SINGLE("3D Switch", WM8973_3D, 0, 1, 0), + SOC_SINGLE("3D Volume", WM8973_3D, 1, 15, 0), + SOC_ENUM("3D Lower Cut-off", lower_cutoff), + SOC_ENUM("3D Upper Cut-off", upper_cutoff), + SOC_ENUM("3D Mode", mode), + + /* ALC1 & ALC2 & ALC3 Control */ + SOC_SINGLE_TLV("ALC Capture Target Volume", WM8971_ALC1, + 0, 15, 0, alc_tar_vol), + SOC_SINGLE_TLV("ALC Capture Max Volume", WM8971_ALC1, + 4, 7, 0, alc_max_vol), + SOC_ENUM("ALC Capture Function", alc_capture_func), + + SOC_SINGLE("ALC Capture Hold Time", WM8971_ALC2, 0, 15, 0), + SOC_SINGLE("ALC Capture ZC Switch", WM8971_ALC2, 7, 1, 0), + + SOC_SINGLE("ALC Capture Attack Time", WM8971_ALC3, 0, 15, 0), + SOC_SINGLE("ALC Capture Decay Time", WM8971_ALC3, 4, 15, 0), + + /* Noise Gate Control */ + SOC_SINGLE("ALC Capture NG Switch", WM8971_NGATE, 0, 1, 0), + SOC_ENUM("ALC Capture NG Type", alc_capture_ngtype), + SOC_SINGLE("ALC Capture NG Threshold", WM8971_NGATE, 3, 31, 0), + + /* Left & Right ADC Digital Volume*/ + SOC_DOUBLE_R_TLV("ADC Volume", WM8971_LADC, WM8971_RADC, + 0, 255, 0, adc_vol), + + /* Additional Control 1 */ + SOC_SINGLE("ZC Timeout Switch", WM8971_ADCTL1, 0, 1, 0), + SOC_SINGLE("Playback Invert Switch", WM8971_ADCTL1, 1, 1, 0), + SOC_SINGLE("Analogue Bias", WM8971_ADCTL1, 6, 3, 0), + /* ADCTL1 Bit 2,3 - DATSEL */ + /* ADCTL1 Bit 6,7 - VSEL */ + + /* Additional Control 2 */ + SOC_SINGLE("Right Speaker Playback Invert Switch", WM8971_ADCTL2, + 4, 1, 0), + /* ADCTL2 Bit 2 - LRCM */ + SOC_SINGLE("LRCLK Switch", WM8971_ADCTL2, 2, 1, 0), + /* ADCTL2 Bit 3 - TRI */ + SOC_SINGLE("Headphone Switch POL", WM8971_ADCTL2, 5, 1, 0), + SOC_SINGLE("Headphone Switch EN", WM8971_ADCTL2, 6, 1, 0), + + /* Additional Control 3 */ + /* ADCTL3 Bit 5 - HPFLREN */ + /* ADCTL3 Bit 6 - VROI */ + /* ADCTL3 Bit 7,8 - ADCLRM */ + + /* ADC input Mode */ + /* ADCIN Bit 4 - LDCM */ + /* ADCIN Bit 5 - RDCM */ + /* ADCIN Bit 6,7 - MONOMIX */ + + /* Left & Right ADC Signal Path Control*/ + SOC_DOUBLE_R("Mic Boost", WM8971_LADCIN, WM8971_RADCIN, 4, 3, 0), + + /* Left OUT Mixer Control */ + SOC_DOUBLE_R_TLV("Bypass Left Playback Volume", WM8971_LOUTM1, + WM8971_LOUTM2, 4, 7, 1, bypass_out_vol), + + /* Right OUT Mixer Control */ + SOC_DOUBLE_R_TLV("Bypass Right Playback Volume", WM8971_ROUTM1, + WM8971_ROUTM2, 4, 7, 1, bypass_out_vol), + + /* Mono OUT Mixer Control */ + SOC_DOUBLE_R_TLV("Bypass Mono Playback Volume", WM8971_MOUTM1, + WM8971_MOUTM2, 4, 7, 1, bypass_out_vol), + + /* LOUT2 & ROUT2 volume */ + SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8971_LOUT2V, + WM8971_ROUT2V, 0, 127, 0, out_vol), + SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8971_LOUT2V, + WM8971_ROUT2V, 7, 1, 0), + + /* MONOOUT volume */ + SOC_SINGLE_TLV("Mono Playback Volume", WM8971_MOUTV, + 0, 127, 0, out_vol), + SOC_SINGLE("Mono Playback ZC Switch", WM8971_MOUTV, 7, 1, 0), + + SOC_SINGLE("Right Out 2", WM8971_PWR2, 3, 1, 0), + SOC_SINGLE("Left Out 2", WM8971_PWR2, 4, 1, 0), +}; + + /* * DAPM Controls */ @@ -219,18 +483,34 @@ SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_MOUTM2, 7, 1, 0), /* Left Line Mux */ static const struct snd_kcontrol_new wm8971_left_line_controls = SOC_DAPM_ENUM("Route", wm8971_enum[8]); +static const struct snd_kcontrol_new wm8973_left_line_controls = +SOC_DAPM_ENUM("Route", left_line); /* Right Line Mux */ static const struct snd_kcontrol_new wm8971_right_line_controls = SOC_DAPM_ENUM("Route", wm8971_enum[9]); +static const struct snd_kcontrol_new wm8973_right_line_controls = +SOC_DAPM_ENUM("Route", right_line); /* Left PGA Mux */ static const struct snd_kcontrol_new wm8971_left_pga_controls = SOC_DAPM_ENUM("Route", wm8971_enum[10]); +static const struct snd_kcontrol_new wm8973_left_pga_controls = +SOC_DAPM_ENUM("Route", left_pga); /* Right PGA Mux */ static const struct snd_kcontrol_new wm8971_right_pga_controls = SOC_DAPM_ENUM("Route", wm8971_enum[11]); +static const struct snd_kcontrol_new wm8973_right_pga_controls = +SOC_DAPM_ENUM("Route", right_pga); + +/* Out 3 Mux */ +static const struct snd_kcontrol_new wm8973_out3_controls = +SOC_DAPM_ENUM("Route", out3); + +/* Differential Mux */ +static const struct snd_kcontrol_new wm8973_diffmux_controls = +SOC_DAPM_ENUM("Route", diffmux); /* Mono ADC Mux */ static const struct snd_kcontrol_new wm8971_monomux_controls = @@ -238,14 +518,14 @@ SOC_DAPM_ENUM("Route", wm8971_enum[13]); static const struct snd_soc_dapm_widget wm8971_dapm_widgets[] = { SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, - &wm8971_left_mixer_controls[0], - ARRAY_SIZE(wm8971_left_mixer_controls)), + &wm8971_left_mixer_controls[0], + ARRAY_SIZE(wm8971_left_mixer_controls)), SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, - &wm8971_right_mixer_controls[0], - ARRAY_SIZE(wm8971_right_mixer_controls)), + &wm8971_right_mixer_controls[0], + ARRAY_SIZE(wm8971_right_mixer_controls)), SND_SOC_DAPM_MIXER("Mono Mixer", WM8971_PWR2, 2, 0, - &wm8971_mono_mixer_controls[0], - ARRAY_SIZE(wm8971_mono_mixer_controls)), + &wm8971_mono_mixer_controls[0], + ARRAY_SIZE(wm8971_mono_mixer_controls)), SND_SOC_DAPM_PGA("Right Out 2", WM8971_PWR2, 3, 0, NULL, 0), SND_SOC_DAPM_PGA("Left Out 2", WM8971_PWR2, 4, 0, NULL, 0), @@ -260,18 +540,18 @@ static const struct snd_soc_dapm_widget wm8971_dapm_widgets[] = { SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8971_PWR1, 3, 0), SND_SOC_DAPM_MUX("Left PGA Mux", WM8971_PWR1, 5, 0, - &wm8971_left_pga_controls), + &wm8971_left_pga_controls), SND_SOC_DAPM_MUX("Right PGA Mux", WM8971_PWR1, 4, 0, - &wm8971_right_pga_controls), + &wm8971_right_pga_controls), SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, - &wm8971_left_line_controls), + &wm8971_left_line_controls), SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, - &wm8971_right_line_controls), + &wm8971_right_line_controls), SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, - &wm8971_monomux_controls), + &wm8971_monomux_controls), SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, - &wm8971_monomux_controls), + &wm8971_monomux_controls), SND_SOC_DAPM_OUTPUT("LOUT1"), SND_SOC_DAPM_OUTPUT("ROUT1"), @@ -284,6 +564,69 @@ static const struct snd_soc_dapm_widget wm8971_dapm_widgets[] = { SND_SOC_DAPM_INPUT("MIC"), }; +static const struct snd_soc_dapm_widget wm8973_dapm_widgets[] = { + SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, + &wm8971_left_mixer_controls[0], + ARRAY_SIZE(wm8971_left_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, + &wm8971_right_mixer_controls[0], + ARRAY_SIZE(wm8971_right_mixer_controls)), + + SND_SOC_DAPM_MIXER("Mono Mixer", WM8971_PWR2, 2, 0, + &wm8971_mono_mixer_controls[0], + ARRAY_SIZE(wm8971_mono_mixer_controls)), + + SND_SOC_DAPM_PGA("Right Out 2", WM8971_PWR2, 3, 0, NULL, 0), + SND_SOC_DAPM_PGA("Left Out 2", WM8971_PWR2, 4, 0, NULL, 0), + SND_SOC_DAPM_PGA("Right Out 1", WM8971_PWR2, 5, 0, NULL, 0), + SND_SOC_DAPM_PGA("Left Out 1", WM8971_PWR2, 6, 0, NULL, 0), + SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8971_PWR2, 7, 0), + SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8971_PWR2, 8, 0), + + SND_SOC_DAPM_MICBIAS("Mic Bias", WM8971_PWR1, 1, 0), + SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8971_PWR1, 2, 0), + SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8971_PWR1, 3, 0), + SND_SOC_DAPM_MUX("Right PGA Mux", WM8971_PWR1, 4, 0, + &wm8973_right_pga_controls), + SND_SOC_DAPM_MUX("Left PGA Mux", WM8971_PWR1, 5, 0, + &wm8973_left_pga_controls), + + SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, + &wm8973_left_line_controls), + SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, + &wm8973_right_line_controls), + + SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, + &wm8973_out3_controls), + SND_SOC_DAPM_PGA("Out 3", WM8971_PWR2, 1, 0, NULL, 0), + + SND_SOC_DAPM_PGA("Mono Out 1", WM8971_PWR2, 2, 0, NULL, 0), + + SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, + &wm8973_diffmux_controls), + + SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, + &wm8971_monomux_controls), + SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, + &wm8971_monomux_controls), + + SND_SOC_DAPM_OUTPUT("LOUT1"), + SND_SOC_DAPM_OUTPUT("ROUT1"), + SND_SOC_DAPM_OUTPUT("LOUT2"), + SND_SOC_DAPM_OUTPUT("ROUT2"), + SND_SOC_DAPM_OUTPUT("MONO1"), + SND_SOC_DAPM_OUTPUT("OUT3"), + SND_SOC_DAPM_OUTPUT("VREF"), + + SND_SOC_DAPM_INPUT("LINPUT1"), + SND_SOC_DAPM_INPUT("LINPUT2"), + SND_SOC_DAPM_INPUT("LINPUT3"), + SND_SOC_DAPM_INPUT("RINPUT1"), + SND_SOC_DAPM_INPUT("RINPUT2"), + SND_SOC_DAPM_INPUT("RINPUT3"), +}; + static const struct snd_soc_dapm_route wm8971_dapm_routes[] = { /* left mixer */ {"Left Mixer", "Playback Switch", "Left DAC"}, @@ -361,6 +704,85 @@ static const struct snd_soc_dapm_route wm8971_dapm_routes[] = { {"Right ADC", NULL, "Right ADC Mux"}, }; +static const struct snd_soc_dapm_route wm8973_dapm_routes[] = { + {"Left Mixer", "Playback Switch", "Left DAC"}, + {"Left Mixer", "Left Bypass Switch", "Left Line Mux"}, + {"Left Mixer", "Right Playback Switch", "Right DAC"}, + {"Left Mixer", "Right Bypass Switch", "Right Line Mux"}, + + {"Right Mixer", "Left Playback Switch", "Left DAC"}, + {"Right Mixer", "Left Bypass Switch", "Left Line Mux"}, + {"Right Mixer", "Playback Switch", "Right DAC"}, + {"Right Mixer", "Right Bypass Switch", "Right Line Mux"}, + + {"Left Out 1", NULL, "Left Mixer"}, + {"LOUT1", NULL, "Left Out 1"}, + + {"Left Out 2", NULL, "Left Mixer"}, + {"LOUT2", NULL, "Left Out 2"}, + + {"Right Out 1", NULL, "Right Mixer"}, + {"ROUT1", NULL, "Right Out 1"}, + + {"Right Out 2", NULL, "Right Mixer"}, + {"ROUT2", NULL, "Right Out 2"}, + + {"Mono Mixer", "Left Playback Switch", "Left DAC"}, + {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"}, + {"Mono Mixer", "Right Playback Switch", "Right DAC"}, + {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"}, + + {"Mono Out 1", NULL, "Mono Mixer"}, + {"MONO1", NULL, "Mono Out 1"}, + + {"Out3 Mux", "VREF", "VREF"}, + {"Out3 Mux", "ROUT1 + Vol", "ROUT1"}, + {"Out3 Mux", "ROUT1", "Right Mixer"}, + {"Out3 Mux", "MonoOut", "MONO1"}, + {"Out 3", NULL, "Out3 Mux"}, + {"OUT3", NULL, "Out 3"}, + + {"Left Line Mux", "Line 1", "LINPUT1"}, + {"Left Line Mux", "Line 2", "LINPUT2"}, + {"Left Line Mux", "Line 3", "LINPUT3"}, + {"Left Line Mux", "PGA", "Left PGA Mux"}, + {"Left Line Mux", "Differential", "Differential Mux"}, + + {"Right Line Mux", "Line 1", "RINPUT1"}, + {"Right Line Mux", "Line 2", "RINPUT2"}, + {"Right Line Mux", "Line 3", "RINPUT3"}, + /* {"Right Line Mux", "Mic", "MIC"}, */ + {"Right Line Mux", "PGA", "Right PGA Mux"}, + {"Right Line Mux", "Differential", "Differential Mux"}, + + {"Left PGA Mux", "Line 1", "LINPUT1"}, + {"Left PGA Mux", "Line 2", "LINPUT2"}, + {"Left PGA Mux", "Line 3", "LINPUT3"}, + {"Left PGA Mux", "Differential", "Differential Mux"}, + + {"Right PGA Mux", "Line 1", "RINPUT1"}, + {"Right PGA Mux", "Line 2", "RINPUT2"}, + {"Right PGA Mux", "Line 3", "RINPUT3"}, + {"Right PGA Mux", "Differential", "Differential Mux"}, + + {"Differential Mux", "Line 1", "LINPUT1"}, + {"Differential Mux", "Line 1", "RINPUT1"}, + {"Differential Mux", "Line 2", "LINPUT2"}, + {"Differential Mux", "Line 2", "RINPUT2"}, + + {"Left ADC Mux", "Stereo", "Left PGA Mux"}, + {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"}, + {"Left ADC Mux", "Digital Mono", "Left PGA Mux"}, + + {"Right ADC Mux", "Stereo", "Right PGA Mux"}, + {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"}, + {"Right ADC Mux", "Digital Mono", "Right PGA Mux"}, + + {"Left ADC", NULL, "Left ADC Mux"}, + {"Right ADC", NULL, "Right ADC Mux"}, +}; + + struct _coeff_div { u32 mclk; u32 rate; @@ -430,26 +852,90 @@ static int get_coeff(int mclk, int rate) return -EINVAL; } +/* The set of rates we can generate from the above for each SYSCLK */ +static const unsigned int rates_12288[] = { + 8000, 12000, 16000, 24000, 32000, 48000, 96000 +}; + +static struct snd_pcm_hw_constraint_list constraints_12288 = { + .count = ARRAY_SIZE(rates_12288), + .list = rates_12288, +}; + +static const unsigned int rates_112896[] = { + 8000, 11025, 22050, 44100, 88200 +}; + +static struct snd_pcm_hw_constraint_list constraints_112896 = { + .count = ARRAY_SIZE(rates_112896), + .list = rates_112896, +}; + +static const unsigned int rates_18432[] = { + 8000, 12000, 16000, 24000, 32000, 48000, 96000 +}; + +static struct snd_pcm_hw_constraint_list constraints_18432 = { + .count = ARRAY_SIZE(rates_18432), + .list = rates_18432, +}; + +static const unsigned int rates_169344[] = { + 8000, 11025, 22050, 44100, 88200 +}; + +static struct snd_pcm_hw_constraint_list constraints_169344 = { + .count = ARRAY_SIZE(rates_169344), + .list = rates_169344, +}; + +static const unsigned int rates_12[] = { + 8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000, + 48000, 88235, 96000, +}; + +static struct snd_pcm_hw_constraint_list constraints_12 = { + .count = ARRAY_SIZE(rates_12), + .list = rates_12, +}; + static int wm8971_set_dai_sysclk(struct snd_soc_dai *codec_dai, - int clk_id, unsigned int freq, int dir) + int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = codec_dai->codec; struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); switch (freq) { - case 11289600: - case 12000000: case 12288000: - case 16934400: + case 24576000: + wm8971->sysclk_constraints = &constraints_12288; + break; + case 11289600: + case 22579200: + wm8971->sysclk_constraints = &constraints_112896; + break; case 18432000: - wm8971->sysclk = freq; - return 0; + wm8971->sysclk_constraints = &constraints_18432; + break; + case 16934400: + case 33868800: + wm8971->sysclk_constraints = &constraints_169344; + break; + case 12000000: + case 24000000: + wm8971->sysclk_constraints = &constraints_12; + break; + default: + return -EINVAL; } - return -EINVAL; + + wm8971->sysclk = freq; + + return 0; } static int wm8971_set_dai_fmt(struct snd_soc_dai *codec_dai, - unsigned int fmt) + unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; u16 iface = 0; @@ -507,8 +993,8 @@ static int wm8971_set_dai_fmt(struct snd_soc_dai *codec_dai, } static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); @@ -516,6 +1002,8 @@ static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream, u16 srate = snd_soc_read(codec, WM8971_SRATE) & 0x1c0; int coeff = get_coeff(wm8971->sysclk, params_rate(params)); + wm8971->playback_fs = params_rate(params); + /* bit size */ switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: @@ -531,6 +1019,8 @@ static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream, break; } + wm8973_set_deemph(codec); + /* set iface & srate */ snd_soc_write(codec, WM8971_IFACE, iface); if (coeff >= 0) @@ -553,23 +1043,31 @@ static int wm8971_mute(struct snd_soc_dai *dai, int mute) } static int wm8971_set_bias_level(struct snd_soc_codec *codec, - enum snd_soc_bias_level level) + enum snd_soc_bias_level level) { - u16 pwr_reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; + struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); + static const u16 mask[][2] = { + [VARIANT_WM8971] = { 0x00c1, 0x0140 }, + [VARIANT_WM8973] = { 0x00c2, 0x0141 }, + }; + u16 pwr_reg = snd_soc_read(codec, WM8971_PWR1) & + charge[wm8971->variant][0]; switch (level) { case SND_SOC_BIAS_ON: /* set vmid to 50k and unmute dac */ - snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x00c1); + snd_soc_write(codec, WM8971_PWR1, pwr_reg | + mask[wm8971->variant][0]); break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) - snd_soc_cache_sync(codec); + regcache_sync(wm8971->regmap); /* mute dac and set vmid to 500k, enable VREF */ - snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x0140); + snd_soc_write(codec, WM8971_PWR1, pwr_reg | + mask[wm8971->variant][1]); break; case SND_SOC_BIAS_OFF: snd_soc_write(codec, WM8971_PWR1, 0x0001); @@ -580,8 +1078,9 @@ static int wm8971_set_bias_level(struct snd_soc_codec *codec, } #define WM8971_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) #define WM8971_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE) @@ -593,74 +1092,81 @@ static const struct snd_soc_dai_ops wm8971_dai_ops = { .set_sysclk = wm8971_set_dai_sysclk, }; -static struct snd_soc_dai_driver wm8971_dai = { - .name = "wm8971-hifi", - .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = WM8971_RATES, - .formats = WM8971_FORMATS,}, - .capture = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = 2, - .rates = WM8971_RATES, - .formats = WM8971_FORMATS,}, - .ops = &wm8971_dai_ops, -}; - -static void wm8971_work(struct work_struct *work) -{ - struct snd_soc_dapm_context *dapm = - container_of(work, struct snd_soc_dapm_context, - delayed_work.work); - struct snd_soc_codec *codec = dapm->codec; - wm8971_set_bias_level(codec, codec->dapm.bias_level); -} +static struct snd_soc_dai_driver wm8971_dai[] = { + { + .name = "wm8971-hifi-playback", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8971_RATES, + .formats = WM8971_FORMATS, + }, + .ops = &wm8971_dai_ops, + }, { + .name = "wm8971-hifi-capture", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8971_RATES, + .formats = WM8971_FORMATS, + }, + .ops = &wm8971_dai_ops, + }, +}; static int wm8971_suspend(struct snd_soc_codec *codec) { + struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); + wm8971_set_bias_level(codec, SND_SOC_BIAS_OFF); + regcache_mark_dirty(wm8971->regmap); + return 0; } static int wm8971_resume(struct snd_soc_codec *codec) { + struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); u16 reg; wm8971_set_bias_level(codec, SND_SOC_BIAS_STANDBY); /* charge wm8971 caps */ - if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) { - reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; - snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); - codec->dapm.bias_level = SND_SOC_BIAS_ON; - queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work, - msecs_to_jiffies(1000)); - } + if (codec->dapm.suspend_bias_level != SND_SOC_BIAS_ON) + return 0; + + reg = snd_soc_read(codec, WM8971_PWR1) & charge[wm8971->variant][0]; + snd_soc_write(codec, WM8971_PWR1, reg | charge[wm8971->variant][1]); + codec->dapm.bias_level = SND_SOC_BIAS_ON; return 0; } static int wm8971_probe(struct snd_soc_codec *codec) { + struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); + const u32 *p; int ret = 0; u16 reg; - INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8971_work); - wm8971_workq = create_workqueue("wm8971"); - if (wm8971_workq == NULL) - return -ENOMEM; + codec->control_data = wm8971->regmap; wm8971_reset(codec); + if (codec->dev->of_node) { + p = of_get_property(codec->dev->of_node, "mclk-div", NULL); + if (p) + wm8971->mclk_div = be32_to_cpu(*p); + } + /* Master Clock Divide by 2 (0 = not div, 1 = div by 2) */ + if (wm8971->mclk_div) + snd_soc_update_bits(codec, WM8971_SRATE, 0x0040, 0x0040); /* charge output caps - set vmid to 5k for quick power up */ - reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; - snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); + reg = snd_soc_read(codec, WM8971_PWR1) & charge[wm8971->variant][0]; + snd_soc_write(codec, WM8971_PWR1, reg | charge[wm8971->variant][1]); codec->dapm.bias_level = SND_SOC_BIAS_STANDBY; - queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work, - msecs_to_jiffies(1000)); /* set the update bits */ snd_soc_update_bits(codec, WM8971_LDAC, 0x0100, 0x0100); @@ -681,24 +1187,47 @@ static int wm8971_remove(struct snd_soc_codec *codec) { wm8971_set_bias_level(codec, SND_SOC_BIAS_OFF); - if (wm8971_workq) - destroy_workqueue(wm8971_workq); return 0; } -static struct snd_soc_codec_driver soc_codec_dev_wm8971 = { - .probe = wm8971_probe, - .remove = wm8971_remove, - .suspend = wm8971_suspend, - .resume = wm8971_resume, - .set_bias_level = wm8971_set_bias_level, +struct regmap *wm8973_get_regmap(struct device *dev) +{ + struct wm8971_priv *priv = dev_get_drvdata(dev); + + return priv->regmap; +} - .controls = wm8971_snd_controls, - .num_controls = ARRAY_SIZE(wm8971_snd_controls), - .dapm_widgets = wm8971_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(wm8971_dapm_widgets), - .dapm_routes = wm8971_dapm_routes, - .num_dapm_routes = ARRAY_SIZE(wm8971_dapm_routes), +static struct snd_soc_codec_driver soc_codec_dev_wm8971[] = { + [VARIANT_WM8971] = { + .probe = wm8971_probe, + .remove = wm8971_remove, + .suspend = wm8971_suspend, + .resume = wm8971_resume, + .set_bias_level = wm8971_set_bias_level, + .get_regmap = wm8973_get_regmap, + + .controls = wm8971_snd_controls, + .num_controls = ARRAY_SIZE(wm8971_snd_controls), + .dapm_widgets = wm8971_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(wm8971_dapm_widgets), + .dapm_routes = wm8971_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(wm8971_dapm_routes), + }, + [VARIANT_WM8973] = { + .probe = wm8971_probe, + .remove = wm8971_remove, + .suspend = wm8971_suspend, + .resume = wm8971_resume, + .set_bias_level = wm8971_set_bias_level, + .get_regmap = wm8973_get_regmap, + + .controls = wm8973_snd_controls, + .num_controls = ARRAY_SIZE(wm8973_snd_controls), + .dapm_widgets = wm8973_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(wm8973_dapm_widgets), + .dapm_routes = wm8973_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(wm8973_dapm_routes), + } }; static const struct regmap_config wm8971_regmap = { @@ -715,7 +1244,6 @@ static int wm8971_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { struct wm8971_priv *wm8971; - struct regmap *regmap; int ret; wm8971 = devm_kzalloc(&i2c->dev, sizeof(struct wm8971_priv), @@ -723,14 +1251,17 @@ static int wm8971_i2c_probe(struct i2c_client *i2c, if (wm8971 == NULL) return -ENOMEM; - regmap = devm_regmap_init_i2c(i2c, &wm8971_regmap); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); + wm8971->variant = (int)id->driver_data; + + wm8971->regmap = devm_regmap_init_i2c(i2c, &wm8971_regmap); + if (IS_ERR(wm8971->regmap)) + return PTR_ERR(wm8971->regmap); i2c_set_clientdata(i2c, wm8971); ret = snd_soc_register_codec(&i2c->dev, - &soc_codec_dev_wm8971, &wm8971_dai, 1); + &soc_codec_dev_wm8971[wm8971->variant], + wm8971_dai, ARRAY_SIZE(wm8971_dai)); return ret; } @@ -742,15 +1273,23 @@ static int wm8971_i2c_remove(struct i2c_client *client) } static const struct i2c_device_id wm8971_i2c_id[] = { - { "wm8971", 0 }, + { "wm8971", VARIANT_WM8971 }, + { "wm8973", VARIANT_WM8973 }, { } }; MODULE_DEVICE_TABLE(i2c, wm8971_i2c_id); +static const struct of_device_id wm897x_dt_ids[] = { + { .compatible = "wlf,wm8971" }, + { .compatible = "wlf,wm8973" }, + { /* sentinel */ } +}; + static struct i2c_driver wm8971_i2c_driver = { .driver = { .name = "wm8971", .owner = THIS_MODULE, + .of_match_table = wm897x_dt_ids, }, .probe = wm8971_i2c_probe, .remove = wm8971_i2c_remove, @@ -762,3 +1301,5 @@ module_i2c_driver(wm8971_i2c_driver); MODULE_DESCRIPTION("ASoC WM8971 driver"); MODULE_AUTHOR("Lab126"); MODULE_LICENSE("GPL"); +MODULE_ALIAS("*wm8971*"); +MODULE_ALIAS("*wm8973*"); diff --git a/sound/soc/codecs/wm8971.h b/sound/soc/codecs/wm8971.h index f31c38f..aeab04a 100644 --- a/sound/soc/codecs/wm8971.h +++ b/sound/soc/codecs/wm8971.h @@ -22,21 +22,22 @@ #define WM8971_ADCDAC 0x05 #define WM8971_IFACE 0x07 #define WM8971_SRATE 0x08 -#define WM8971_LDAC 0x0a -#define WM8971_RDAC 0x0b -#define WM8971_BASS 0x0c +#define WM8971_LDAC 0x0a +#define WM8971_RDAC 0x0b +#define WM8971_BASS 0x0c #define WM8971_TREBLE 0x0d #define WM8971_RESET 0x0f -#define WM8971_ALC1 0x11 -#define WM8971_ALC2 0x12 -#define WM8971_ALC3 0x13 +#define WM8973_3D 0x10 +#define WM8971_ALC1 0x11 +#define WM8971_ALC2 0x12 +#define WM8971_ALC3 0x13 #define WM8971_NGATE 0x14 -#define WM8971_LADC 0x15 -#define WM8971_RADC 0x16 +#define WM8971_LADC 0x15 +#define WM8971_RADC 0x16 #define WM8971_ADCTL1 0x17 #define WM8971_ADCTL2 0x18 -#define WM8971_PWR1 0x19 -#define WM8971_PWR2 0x1a +#define WM8971_PWR1 0x19 +#define WM8971_PWR2 0x1a #define WM8971_ADCTL3 0x1b #define WM8971_ADCIN 0x1f #define WM8971_LADCIN 0x20 -- 1.7.9.5

2 1

[alsa-devel] generic i2s driver problems on an Exynos 5250 A15 board
by Matt Flax 12 Aug '14

12 Aug '14

hi there, I am writing a very generic alsa soc i2s driver for a very generic i2s device. The platform is an Exynos 5250 SoC board. Having trouble was looking for some help ... I have tried to start this driver in two ways. 1] Using the module_init/module_exit method and 2] Using the module_platform_driver approach. I have implemented the following : soc/codecs/implant.c soc/samsung/implant.c In both cases I have : static struct snd_soc_ops implant_ops = { .hw_params = implant_hw_params, }; static struct snd_soc_dai_link implant_dai = { .name = "implant", .stream_name = "IMPLANT", .cpu_dai_name = "samsung-i2s.0", .codec_dai_name = "implant-pcm", .platform_name = "samsung-i2s.0", .codec_name = "implant.0-001a", .ignore_suspend = 1, .ops = &implant_ops, }; I have setup the device tree as expected for sound@3830000 sound@3830000 { samsung,codec-type = "implant"; }; 1] Approach using module_init/module_exit static struct snd_soc_card snd_soc_machine_implant = { .name = "Implant", .owner = THIS_MODULE, .dai_link = &implant_dai, .num_links = 1, .dapm_widgets = widgets, .num_dapm_widgets = ARRAY_SIZE(widgets), .dapm_routes = audio_paths, .num_dapm_routes = ARRAY_SIZE(audio_paths), }; Here is the output of the kernel : [ 1.802645] soc-audio soc-audio: ASoC: machine Implant should use snd_soc_register_card() [ 1.802656] soc-audio soc-audio: ASoC: CPU DAI samsung-i2s.0 not registered [ 1.802679] platform soc-audio: Driver soc-audio requests probe deferral [ 2.271140] soc-audio: probe of soc-audio failed with error -22 Not sure why it fails. The only thing I know is that my driver exits the init function returning 0 (module_init(implant_init)). This appears to be correct. 2] Approach using module_platform_driver When I switch to using snd_soc_register_card with : module_platform_driver(implant_driver); static struct platform_driver implant_driver = { .driver = { .name = "implant", .owner = THIS_MODULE, }, .probe = implant_probe, .remove = implant_remove, }; I get the following from dmesg : [ 1.802430] Error: Driver 'implant' is already registered, aborting... However I don't see any of my printk statements from dmesg ... Matt

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[alsa-devel] [PATCH] ASoC: Intel: Add merrifield machine driver
by Subhransu S. Prusty 12 Aug '14

12 Aug '14

From: Vinod Koul <vinod.koul(a)intel.com> This patch adds machine driver support for merrifield platform. Patch has dependency on merrifield DSP driver. Signed-off-by: Vinod Koul <vinod.koul(a)intel.com> Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty(a)intel.com> --- Changes in v2: Removed get_codec/find_codec, instead use rtd index Using dai_fmt field of the dai_link This patch has dependency on "add mrfld DSP support". sound/soc/intel/Kconfig | 16 ++ sound/soc/intel/Makefile | 2 + sound/soc/intel/merr_dpcm_wm8958.c | 522 +++++++++++++++++++++++++++++++++++++ 3 files changed, 540 insertions(+) create mode 100644 sound/soc/intel/merr_dpcm_wm8958.c diff --git a/sound/soc/intel/Kconfig b/sound/soc/intel/Kconfig index c6fe1e498a02..5f6345a6d77e 100644 --- a/sound/soc/intel/Kconfig +++ b/sound/soc/intel/Kconfig @@ -58,3 +58,19 @@ config SND_SOC_INTEL_BYT_MAX98090_MACH help This adds audio driver for Intel Baytrail platform based boards with the MAX98090 audio codec. + +config SND_SOC_INTEL_MRFLD_WM8958_MACH + tristate "SOC Machine Audio driver for Intel Merrifield MID platform" + depends on X86 + select SND_SOC_WM8994 + select MFD_CORE + select MFD_WM8994 + select REGULATOR_WM8994 + select SND_SST_MFLD_PLATFORM + select SND_SOC_INTEL_SST + default n + help + This adds support for ASoC machine driver for Intel(R) MID Merrifield platform + used as alsa device in audio substem in Intel(R) MID devices + Say Y if you have such a device + If unsure select "N". diff --git a/sound/soc/intel/Makefile b/sound/soc/intel/Makefile index 9480b5d40e02..05da1093c777 100644 --- a/sound/soc/intel/Makefile +++ b/sound/soc/intel/Makefile @@ -25,7 +25,9 @@ obj-$(CONFIG_SND_SOC_INTEL_BAYTRAIL) += snd-soc-sst-baytrail-pcm.o snd-soc-sst-haswell-objs := haswell.o snd-soc-sst-byt-rt5640-mach-objs := byt-rt5640.o snd-soc-sst-byt-max98090-mach-objs := byt-max98090.o +snd-merr-dpcm-wm8958-objs := merr_dpcm_wm8958.o obj-$(CONFIG_SND_SOC_INTEL_HASWELL_MACH) += snd-soc-sst-haswell.o obj-$(CONFIG_SND_SOC_INTEL_BYT_RT5640_MACH) += snd-soc-sst-byt-rt5640-mach.o obj-$(CONFIG_SND_SOC_INTEL_BYT_MAX98090_MACH) += snd-soc-sst-byt-max98090-mach.o +obj-$(CONFIG_SND_SOC_INTEL_MRFLD_WM8958_MACH) += snd-merr-dpcm-wm8958.o diff --git a/sound/soc/intel/merr_dpcm_wm8958.c b/sound/soc/intel/merr_dpcm_wm8958.c new file mode 100644 index 000000000000..7ef44a3ee608 --- /dev/null +++ b/sound/soc/intel/merr_dpcm_wm8958.c @@ -0,0 +1,522 @@ +/* + * merr_dpcm_wm8958.c - ASoc DPCM Machine driver for Intel Merrfield MID platform + * + * Copyright (C) 2013-14 Intel Corp + * Author: Vinod Koul <vinod.koul(a)intel.com> + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/async.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/jack.h> +#include <linux/input.h> + +#include <linux/mfd/wm8994/core.h> +#include <linux/mfd/wm8994/registers.h> +#include <linux/mfd/wm8994/pdata.h> +#include "../codecs/wm8994.h" +#include "sst-atom-controls.h" + +/* Codec PLL output clk rate */ +#define CODEC_SYSCLK_RATE 24576000 +/* Input clock to codec at MCLK1 PIN */ +#define CODEC_IN_MCLK1_RATE 19200000 +/* Input clock to codec at MCLK2 PIN */ +#define CODEC_IN_MCLK2_RATE 32768 +/* define to select between MCLK1 and MCLK2 input to codec as its clock */ +#define CODEC_IN_MCLK1 1 +#define CODEC_IN_MCLK2 2 +#define CODEC_BE 1 + +struct mrfld_8958_mc_private { + struct snd_soc_jack jack; + int jack_retry; +}; + +/* + * Function to switch the input clock for codec, When audio is in + * progress input clock to codec will be through MCLK1 which is 19.2MHz + * while in off state input clock to codec will be through 32KHz through + * MCLK2 + * card : Sound card structure + * src : Input clock source to codec + */ +static int mrfld_8958_set_codec_clk(struct snd_soc_card *card, int src) +{ + int ret; + /* "wm8994-aif1" */ + struct snd_soc_dai *aif1_dai = card->rtd[CODEC_BE].codec_dai; + + if (!aif1_dai) + return -ENODEV; + + switch (src) { + case CODEC_IN_MCLK1: + /* Turn ON the PLL to generate required sysclk rate + * from MCLK1 */ + ret = snd_soc_dai_set_pll(aif1_dai, + WM8994_FLL1, WM8994_FLL_SRC_MCLK1, + CODEC_IN_MCLK1_RATE, CODEC_SYSCLK_RATE); + if (ret < 0) { + pr_err("Failed to start FLL: %d\n", ret); + return ret; + } + /* Switch to MCLK1 input */ + ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_FLL1, + CODEC_SYSCLK_RATE, SND_SOC_CLOCK_IN); + if (ret < 0) { + pr_err("Failed to set codec sysclk configuration %d\n", + ret); + return ret; + } + break; + case CODEC_IN_MCLK2: + /* Switch to MCLK2 */ + ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_MCLK2, + 32768, SND_SOC_CLOCK_IN); + if (ret < 0) { + pr_err("Failed to switch to MCLK2: %d", ret); + return ret; + } + /* Turn off PLL for MCLK1 */ + ret = snd_soc_dai_set_pll(aif1_dai, WM8994_FLL1, 0, 0, 0); + if (ret < 0) { + pr_err("Failed to stop the FLL: %d", ret); + return ret; + } + break; + default: + return -EINVAL; + } + return 0; +} + +static int mrfld_wm8958_set_clk(struct snd_soc_dai *codec_dai) +{ + int ret = 0; + struct snd_soc_card *card = codec_dai->card; + + pr_err("setting snd_soc_dai_set_tdm_slot\n"); + ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xf0, 0xf0, 4, 24); + if (ret < 0) { + pr_err("can't set codec pcm format %d\n", ret); + return ret; + } + + /* + * FIXME: move this to SYS_CLOCK event handler when codec driver + * dependency is clean. + */ + /* Switch to 19.2MHz MCLK1 input clock for codec */ + ret = mrfld_8958_set_codec_clk(card, CODEC_IN_MCLK1); + + return ret; +} + +static int mrfld_8958_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + + if (!strcmp(codec_dai->name, "wm8994-aif1")) + return mrfld_wm8958_set_clk(codec_dai); + return 0; +} + +static const struct snd_soc_pcm_stream mrfld_wm8958_dai_params = { + .formats = SNDRV_PCM_FMTBIT_S24_LE, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, +}; + +static int merr_codec_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("Invoked %s for dailink %s\n", __func__, rtd->dai_link->name); + + /* The DSP will covert the FE rate to 48k, stereo, 24bits */ + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + /* set SSP2 to 24-bit */ + snd_mask_set(&params->masks[SNDRV_PCM_HW_PARAM_FORMAT - + SNDRV_PCM_HW_PARAM_FIRST_MASK], + SNDRV_PCM_FORMAT_S24_LE); + return 0; +} + +static int mrfld_8958_set_bias_level(struct snd_soc_card *card, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level) +{ + int ret = 0; + /* "wm8994-aif1" */ + struct snd_soc_dai *aif1_dai = card->rtd[CODEC_BE].codec_dai; + + if (!aif1_dai) + return -ENODEV; + + if (dapm->dev != aif1_dai->dev) + return 0; + switch (level) { + case SND_SOC_BIAS_PREPARE: + if (card->dapm.bias_level == SND_SOC_BIAS_STANDBY) + + ret = mrfld_wm8958_set_clk(aif1_dai); + break; + default: + break; + } + pr_debug("%s card(%s)->bias_level %u\n", __func__, card->name, + card->dapm.bias_level); + return ret; +} + +static int mrfld_8958_set_bias_level_post(struct snd_soc_card *card, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level) +{ + int ret = 0; + /* "wm8994-aif1" */ + struct snd_soc_dai *aif1_dai = card->rtd[CODEC_BE].codec_dai; + + if (!aif1_dai) + return -ENODEV; + + if (dapm->dev != aif1_dai->dev) + return 0; + + switch (level) { + case SND_SOC_BIAS_STANDBY: + /* + * We are in standby down so */ + /* Switch to 32KHz MCLK2 input clock for codec + */ + ret = mrfld_8958_set_codec_clk(card, CODEC_IN_MCLK2); + break; + default: + break; + } + if (&card->dapm == dapm) + card->dapm.bias_level = level; + pr_debug("%s card(%s)->bias_level %u\n", __func__, card->name, + card->dapm.bias_level); + return ret; +} + +static const struct snd_soc_dapm_widget widgets[] = { + SND_SOC_DAPM_HP("Headphones", NULL), + SND_SOC_DAPM_MIC("AMIC", NULL), + SND_SOC_DAPM_MIC("DMIC", NULL), +}; + +static const struct snd_soc_dapm_route map[] = { + { "Headphones", NULL, "HPOUT1L" }, + { "Headphones", NULL, "HPOUT1R" }, + + /* + * Machine uses 2 DMICs, other configs may use more so change below + * accordingly + */ + { "DMIC1DAT", NULL, "DMIC" }, + { "DMIC2DAT", NULL, "DMIC" }, + /*{ "DMIC3DAT", NULL, "DMIC" },*/ + /*{ "DMIC4DAT", NULL, "DMIC" },*/ + + /* + * MICBIAS2 is connected as Bias for AMIC so we link it + * here. Also AMIC wires up to IN1LP pin. + * DMIC is externally connected to 1.8V rail, so no link rqd. + */ + { "AMIC", NULL, "MICBIAS2" }, + { "IN1LP", NULL, "AMIC" }, + + /* dsp map link the SWM outs to codec AIF */ + { "AIF1 Playback", NULL, "ssp2 Tx"}, + { "ssp2 Tx", NULL, "codec_out0"}, + { "ssp2 Tx", NULL, "codec_out1"}, + { "codec_in0", NULL, "ssp2 Rx" }, + { "codec_in1", NULL, "ssp2 Rx" }, + { "ssp2 Rx", NULL, "AIF1 Capture"}, + +}; + +static const struct wm8958_micd_rate micdet_rates[] = { + { 32768, true, 1, 4 }, + { 32768, false, 1, 1 }, + { 44100 * 256, true, 7, 10 }, + { 44100 * 256, false, 7, 10 }, +}; + +static int mrfld_8958_init(struct snd_soc_pcm_runtime *runtime) +{ + int ret; + struct snd_soc_card *card = runtime->card; + struct mrfld_8958_mc_private *ctx = snd_soc_card_get_drvdata(card); + /* "wm8994-aif1" */ + struct snd_soc_dai *aif1_dai = card->rtd[CODEC_BE].codec_dai; + struct snd_soc_codec *codec = aif1_dai->codec; + + if (!aif1_dai) + return -ENODEV; + + pr_debug("Entry %s\n", __func__); + + ret = snd_soc_dai_set_tdm_slot(aif1_dai, 0xf0, 0xf0, 4, 24); + if (ret < 0) { + pr_err("can't set codec pcm format %d\n", ret); + return ret; + } + + card->dapm.idle_bias_off = true; + + /* Force enable VMID to avoid cold latency constraints */ + snd_soc_dapm_force_enable_pin(&card->dapm, "VMID"); + snd_soc_dapm_sync(&card->dapm); + + if (!codec) { + pr_err("%s: we didnt find the codec pointer!\n", __func__); + return 0; + } + + ctx->jack_retry = 0; + ret = snd_soc_jack_new(codec, "Intel MID Audio Jack", + SND_JACK_HEADSET | SND_JACK_HEADPHONE | + SND_JACK_BTN_0 | SND_JACK_BTN_1, + &ctx->jack); + if (ret) { + pr_err("jack creation failed\n"); + return ret; + } + + snd_jack_set_key(ctx->jack.jack, SND_JACK_BTN_1, KEY_MEDIA); + snd_jack_set_key(ctx->jack.jack, SND_JACK_BTN_0, KEY_MEDIA); + + wm8958_mic_detect(codec, &ctx->jack, NULL, NULL, NULL, NULL); + + /* + * Micbias1 is always off, so for pm optimizations make sure the micbias1 + * discharge bit is set to floating to avoid discharge in disable state + */ + snd_soc_update_bits(codec, WM8958_MICBIAS1, WM8958_MICB1_DISCH, 0); + + return 0; +} + +static unsigned int rates_48000[] = { + 48000, +}; + +static struct snd_pcm_hw_constraint_list constraints_48000 = { + .count = ARRAY_SIZE(rates_48000), + .list = rates_48000, +}; +static int mrfld_8958_startup(struct snd_pcm_substream *substream) +{ + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &constraints_48000); +} + +static struct snd_soc_ops mrfld_8958_ops = { + .startup = mrfld_8958_startup, +}; + +static struct snd_soc_ops mrfld_8958_be_ssp2_ops = { + .hw_params = mrfld_8958_hw_params, +}; + +struct snd_soc_dai_link mrfld_8958_msic_dailink[] = { + [MERR_DPCM_AUDIO] = { + .name = "Merrifield Audio Port", + .stream_name = "Merrifield Audio", + .cpu_dai_name = "Headset-cpu-dai", + .codec_name = "snd-soc-dummy", + .codec_dai_name = "snd-soc-dummy-dai", + .platform_name = "sst-platform", + .init = mrfld_8958_init, + .ignore_suspend = 1, + .dynamic = 1, + .ops = &mrfld_8958_ops, + }, + [MERR_DPCM_COMPR] = { + .name = "Merrifield Compress Port", + .stream_name = "Merrifield Compress", + .platform_name = "sst-platform", + .cpu_dai_name = "Compress-cpu-dai", + .codec_name = "snd-soc-dummy", + .codec_dai_name = "snd-soc-dummy-dai", + .dynamic = 1, + .init = mrfld_8958_init, + }, + + /* back ends */ + { + .name = "SSP2-Codec", + .be_id = 1, + .cpu_dai_name = "ssp2-port", + .platform_name = "sst-platform", + .no_pcm = 1, + .codec_dai_name = "wm8994-aif1", + .codec_name = "wm8994-codec", + .dai_fmt = SND_SOC_DAIFMT_DSP_B | + SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS, + .be_hw_params_fixup = merr_codec_fixup, + .ignore_suspend = 1, + .ops = &mrfld_8958_be_ssp2_ops, + }, +}; + +#ifdef CONFIG_PM_SLEEP +static int snd_mrfld_8958_prepare(struct device *dev) +{ + struct snd_soc_card *card = dev_get_drvdata(dev); + struct snd_soc_codec *codec = card->rtd[CODEC_BE].codec; + struct snd_soc_dapm_context *dapm; + + pr_debug("In %s\n", __func__); + + pr_debug("found codec %s\n", codec->component.name); + dapm = &codec->dapm; + + snd_soc_dapm_disable_pin(dapm, "VMID"); + snd_soc_dapm_sync(dapm); + + snd_soc_suspend(dev); + return 0; +} + +static void snd_mrfld_8958_complete(struct device *dev) +{ + struct snd_soc_card *card = dev_get_drvdata(dev); + struct snd_soc_codec *codec = card->rtd[CODEC_BE].codec; + struct snd_soc_dapm_context *dapm; + + pr_debug("In %s\n", __func__); + + pr_debug("found codec %s\n", codec->component.name); + dapm = &codec->dapm; + + snd_soc_dapm_force_enable_pin(dapm, "VMID"); + snd_soc_dapm_sync(dapm); + + snd_soc_resume(dev); +} + +static int snd_mrfld_8958_poweroff(struct device *dev) +{ + pr_debug("In %s\n", __func__); + snd_soc_poweroff(dev); + return 0; +} +#else +#define snd_mrfld_8958_prepare NULL +#define snd_mrfld_8958_complete NULL +#define snd_mrfld_8958_poweroff NULL +#endif + +/* SoC card */ +static struct snd_soc_card snd_soc_card_mrfld = { + .name = "wm8958-audio", + .dai_link = mrfld_8958_msic_dailink, + .num_links = ARRAY_SIZE(mrfld_8958_msic_dailink), + .set_bias_level = mrfld_8958_set_bias_level, + .set_bias_level_post = mrfld_8958_set_bias_level_post, + .dapm_widgets = widgets, + .num_dapm_widgets = ARRAY_SIZE(widgets), + .dapm_routes = map, + .num_dapm_routes = ARRAY_SIZE(map), + .fully_routed = true, +}; + +static int snd_mrfld_8958_mc_probe(struct platform_device *pdev) +{ + int ret_val = 0; + struct mrfld_8958_mc_private *drv; + + pr_debug("Entry %s\n", __func__); + + drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); + if (!drv) { + pr_err("allocation failed\n"); + return -ENOMEM; + } + + /* register the soc card */ + snd_soc_card_mrfld.dev = &pdev->dev; + snd_soc_card_set_drvdata(&snd_soc_card_mrfld, drv); + ret_val = snd_soc_register_card(&snd_soc_card_mrfld); + if (ret_val) { + pr_err("snd_soc_register_card failed %d\n", ret_val); + goto unalloc; + } + platform_set_drvdata(pdev, &snd_soc_card_mrfld); + pr_info("%s successful\n", __func__); + return ret_val; + +unalloc: + return ret_val; +} + +static int snd_mrfld_8958_mc_remove(struct platform_device *pdev) +{ + struct snd_soc_card *soc_card = platform_get_drvdata(pdev); + + pr_debug("In %s\n", __func__); + snd_soc_card_set_drvdata(soc_card, NULL); + snd_soc_unregister_card(soc_card); + platform_set_drvdata(pdev, NULL); + return 0; +} + +const struct dev_pm_ops snd_mrfld_8958_mc_pm_ops = { + .prepare = snd_mrfld_8958_prepare, + .complete = snd_mrfld_8958_complete, + .poweroff = snd_mrfld_8958_poweroff, +}; + +static struct platform_driver snd_mrfld_8958_mc_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mrfld_wm8958", + .pm = &snd_mrfld_8958_mc_pm_ops, + }, + .probe = snd_mrfld_8958_mc_probe, + .remove = snd_mrfld_8958_mc_remove, +}; + +module_platform_driver(snd_mrfld_8958_mc_driver); + +MODULE_DESCRIPTION("ASoC Intel(R) Merrifield MID Machine driver"); +MODULE_AUTHOR("Vinod Koul <vinod.koul(a)intel.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:mrfld_wm8958"); -- 1.9.0

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[alsa-devel] [PATCH] ASoC: dapm: Fix uninitialized variable in snd_soc_dapm_get_enum_double()
by Geert Uytterhoeven 11 Aug '14

11 Aug '14

If soc_dapm_read() fails, reg_val will be uninitialized, and bogus values will be written later: sound/soc/soc-dapm.c: In function 'snd_soc_dapm_get_enum_double': sound/soc/soc-dapm.c:2862:15: warning: 'reg_val' may be used uninitialized in this function [-Wmaybe-uninitialized] unsigned int reg_val, val; ^ Return early on error to fix this. Introduced by commit ce0fc93ae56e2ba50ff8c220d69e4e860e889320 ("ASoC: Add DAPM support at the component level"). --- Is this correct? Please review. Signed-off-by: Geert Uytterhoeven <geert+renesas(a)glider.be> --- sound/soc/soc-dapm.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index 8348352dc2c6..177bd8639ef9 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c @@ -2860,12 +2860,14 @@ int snd_soc_dapm_get_enum_double(struct snd_kcontrol *kcontrol, struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; unsigned int reg_val, val; - int ret = 0; - if (e->reg != SND_SOC_NOPM) - ret = soc_dapm_read(dapm, e->reg, &reg_val); - else + if (e->reg != SND_SOC_NOPM) { + int ret = soc_dapm_read(dapm, e->reg, &reg_val); + if (ret) + return ret; + } else { reg_val = dapm_kcontrol_get_value(kcontrol); + } val = (reg_val >> e->shift_l) & e->mask; ucontrol->value.enumerated.item[0] = snd_soc_enum_val_to_item(e, val); @@ -2875,7 +2877,7 @@ int snd_soc_dapm_get_enum_double(struct snd_kcontrol *kcontrol, ucontrol->value.enumerated.item[1] = val; } - return ret; + return 0; } EXPORT_SYMBOL_GPL(snd_soc_dapm_get_enum_double); -- 1.9.1

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[alsa-devel] [PATCH 0/3] ASoC: Intel: Baytrail: Fix stream restore after aborted suspend
by Jarkko Nikula 11 Aug '14

11 Aug '14

It was found that resuming active stream fails on Baytrail ADSP in case of aborted suspend or when testing only partial suspend. Reason for this is that in those cases ADSP doesn't reach reset even though resume path is expecting so and fails to restart stream. This revealed that suspend and resume phases do not go together: Operating state is not the same after returning certain resume phase than it was prior entering into corresponding suspend phase. Also we unload firmware in suspend_late before putting ADSP into reset in suspend_noirq when ADSP is actually already powered down. Fix these by first rearranging and simplifying suspend/resume: Put ADSP into reset in suspend_late and bring it back in resume_late. Now only these will take care of ADSP reset and reboot and SNDRV_PCM_TRIGGER_SUSPEND/SNDRV_PCM_TRIGGER_RESUME callbacks will take care of stream stop/restart during suspend and resume phases. Then modify stream resume so that full stream reallocation and restart is done only if suspend_late was reached. Otherwise resume it by using the IPC that resumes paused stream. Jarkko Nikula (3): ASoC: Intel: Merge Baytrail ADSP suspend_noirq into suspend_late ASoC: Intel: Wait Baytrail ADSP boot at resume_early stage ASoC: Intel: Restore Baytrail ADSP streams only when ADSP was in reset sound/soc/intel/sst-baytrail-ipc.c | 10 +-------- sound/soc/intel/sst-baytrail-ipc.h | 1 - sound/soc/intel/sst-baytrail-pcm.c | 43 +++++++++++++------------------------- 3 files changed, 16 insertions(+), 38 deletions(-) -- 2.0.1

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[alsa-devel] Choosing the sysclk in simple-card looks broken to me.
by jonsmirl＠gmail.com 11 Aug '14

11 Aug '14

The problem is in asoc_simple_card_sub_parse_of() in the else case.. } else { clk = of_clk_get(node, 0); if (!IS_ERR(clk)) dai->sysclk = clk_get_rate(clk); } This is picking up the input clocks to the devices. On the cpu-dai you want to pick up the ouput mclk (my first input clock is an 80Mhz bus clock). My IIS output clock is: clock-output-names = "mclk0"; Setting clocks="" doesn't work either, it also picks up the input clock. if (of_property_read_bool(np, "clocks")) { clk = of_clk_get(np, 0); if (IS_ERR(clk)) { ret = PTR_ERR(clk); return ret; When the codec-dai bit runs it finds the input clock on the codec, which is really my cpu-dai's output clock and it gets the correct value. But then simple goes and tries to set both system clocks - my 80Mhz bus clock and the 22.5 true sysclk. And my cpu-dai barfs when it is passed a 80Mhz sysclk. How to fix? Is anyone using this feature? This needs to be fixed to pick up output clocks, not input ones. -- Jon Smirl jonsmirl(a)gmail.com

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[alsa-devel] [PATCH 2/2] mfd: arizona: Update DT binding to support INn_MODE
by Inha Song 11 Aug '14

11 Aug '14

This patch update DT binding to support INn_MODE init_data Signed-off-by: Inha Song <ideal.song(a)samsung.com> --- Documentation/devicetree/bindings/mfd/arizona.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index 5c7e723..c21a30e 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -42,6 +42,11 @@ Optional properties: the chip default will be used. If present exactly five values must be specified. + - wlf,inmode : A list of INn_MODE register values. If absent, INn_MODE register + set to 0 by default. The size of this list depends on ARIZONA_MAX_INPUT values. + ARIZONA_MAX_INPUT is defined in include/linux/mfd/arizona/pdata.h. If present, + exactly ARIZONA_MAX_INPUT values must be specified. + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if they are being externally supplied. As covered in Documentation/devicetree/bindings/regulator/regulator.txt -- 2.0.0.390.gcb682f8

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[alsa-devel] [PATCH alsa-lib 1/2] Sync include/sound/asound.h with 3.17-rc1 kernel
by Takashi Iwai 11 Aug '14

11 Aug '14

Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- include/sound/asound.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/include/sound/asound.h b/include/sound/asound.h index 519452466317..32168f7ffce3 100644 --- a/include/sound/asound.h +++ b/include/sound/asound.h @@ -93,9 +93,12 @@ enum { SNDRV_HWDEP_IFACE_SB_RC, /* SB Extigy/Audigy2NX remote control */ SNDRV_HWDEP_IFACE_HDA, /* HD-audio */ SNDRV_HWDEP_IFACE_USB_STREAM, /* direct access to usb stream */ + SNDRV_HWDEP_IFACE_FW_DICE, /* TC DICE FireWire device */ + SNDRV_HWDEP_IFACE_FW_FIREWORKS, /* Echo Audio Fireworks based device */ + SNDRV_HWDEP_IFACE_FW_BEBOB, /* BridgeCo BeBoB based device */ /* Don't forget to change the following: */ - SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_USB_STREAM + SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_BEBOB }; struct snd_hwdep_info { @@ -214,8 +217,8 @@ typedef int __bitwise snd_pcm_format_t; #define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45) /* 1 sample in 1 byte */ #define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46) /* 8 Samples in 5 bytes */ #define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47) /* 1 sample in 1 byte */ -#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48) /* 8 1-bit samples in 1 byte */ -#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49) /* 16 1-bit samples in 2 bytes */ +#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48) /* DSD, 1-byte samples DSD (x8) */ +#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49) /* DSD, 2-byte samples DSD (x16), little endian */ #define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U16_LE #ifdef SNDRV_LITTLE_ENDIAN @@ -461,7 +464,7 @@ struct snd_xfern { enum { SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0, /* gettimeofday equivalent */ SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, /* posix_clock_monotonic equivalent */ - SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, /* monotonic_raw (no NTP) */ + SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, /* monotonic_raw (no NTP) */ SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, }; @@ -820,6 +823,8 @@ typedef int __bitwise snd_ctl_elem_iface_t; #define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000) /* Off, with power */ #define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001) /* Off, without power */ +#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44 + struct snd_ctl_elem_id { unsigned int numid; /* numeric identifier, zero = invalid */ snd_ctl_elem_iface_t iface; /* interface identifier */ -- 2.0.4

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[alsa-devel] [PATCH] Fix DSD formats userland usability
by Jurgen Kramer 11 Aug '14

11 Aug '14

Support for DSD sample formats has been added a while ago. This patch makes those sample formats beter usable from userland (e.g. aplay). --- include/sound/asound.h | 4 +++- src/pcm/pcm_misc.c | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/sound/asound.h b/include/sound/asound.h index c819df4..5194524 100644 --- a/include/sound/asound.h +++ b/include/sound/asound.h @@ -214,7 +214,9 @@ typedef int __bitwise snd_pcm_format_t; #define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45) /* 1 sample in 1 byte */ #define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46) /* 8 Samples in 5 bytes */ #define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47) /* 1 sample in 1 byte */ -#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_G723_40_1B +#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48) /* 8 1-bit samples in 1 byte */ +#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49) /* 16 1-bit samples in 2 bytes */ +#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U16_LE #ifdef SNDRV_LITTLE_ENDIAN #define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE diff --git a/src/pcm/pcm_misc.c b/src/pcm/pcm_misc.c index d52160c..44bb89c 100644 --- a/src/pcm/pcm_misc.c +++ b/src/pcm/pcm_misc.c @@ -195,11 +195,13 @@ int snd_pcm_format_width(snd_pcm_format_t format) switch (format) { case SNDRV_PCM_FORMAT_S8: case SNDRV_PCM_FORMAT_U8: + case SNDRV_PCM_FORMAT_DSD_U8: return 8; case SNDRV_PCM_FORMAT_S16_LE: case SNDRV_PCM_FORMAT_S16_BE: case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_U16_BE: + case SNDRV_PCM_FORMAT_DSD_U16_LE: return 16; case SNDRV_PCM_FORMAT_S18_3LE: case SNDRV_PCM_FORMAT_S18_3BE: @@ -253,11 +255,13 @@ int snd_pcm_format_physical_width(snd_pcm_format_t format) switch (format) { case SNDRV_PCM_FORMAT_S8: case SNDRV_PCM_FORMAT_U8: + case SNDRV_PCM_FORMAT_DSD_U8: return 8; case SNDRV_PCM_FORMAT_S16_LE: case SNDRV_PCM_FORMAT_S16_BE: case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_U16_BE: + case SNDRV_PCM_FORMAT_DSD_U16_LE: return 16; case SNDRV_PCM_FORMAT_S18_3LE: case SNDRV_PCM_FORMAT_S18_3BE: -- 1.9.3

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[alsa-devel] Disabled jacks on motherboard 'Gigabyte G1 Sniper Z87' (CA0132-based)
by Swen Wenzel 11 Aug '14

11 Aug '14

Hello guys, I own the motherboard mentioned in the subject and experienced problems when I tried to get it to work. After some conversation <http://pastebin.com/HnmxuU1Q> in IRC we found out, that probably the jack I used was deactivated. I had to use the lineout jack instead of the headphone/speaker jack. However the headphone/speaker jack could be enabled to give the same output as the lineout jack with 'hda-verb'. Here is my alsa information: http://www.alsa-project.org/db/?f=8f57f0b72d65046469b8b6ce8a57ff6fe0371769 Maybe you can have a look at it. You can also always contact me if you have further questions or want me to try something out. I am also a programmer, and studied something related to computer science so you don't have to fear completely useless answers or too dumb questions. :D kind regards Swen

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[alsa-devel] [AMD OSS Driver Bug] Only 2 Channel Audio Detected on HDMI
by Mathew Nichols 10 Aug '14

10 Aug '14

Hello, Using Ubuntu Mini Kernel v.3.15.3-generic (OSS drivers) I cannot pass 7.1 LPCM and cannot bitstream HD Audio formats. XBMC only detects 2 channels. The xbmc.log only reports m_channel=FL,FR. I can also bitstream AC3 / DTS. I have worked closely with fritsch. We believe this is a kernel audio error with my GPU (AMD 5670.) The setup is dual boot and the Windows partition works correctly, as does the older Ubuntu kernel with AMD proprietary drivers. Debug information below. • Kernel log (dmesg with drm.debug=0xe):http://paste.ubuntu.com/7811317 • Driver Codec: http://paste.ubuntu.com/7811321 • xbmc.log: http://paste.ubuntu.com/7805000 Using Ubuntu Mini Kernel v.3.13.0-32-generic (AMD proprietary drivers 14.4) I CAN pass 7.1 LPCM and I can then bitstream HD Audio formats. Windows 7 also detects 7.1 LPCM @ 192khz and will bitstream all HD Audio formats. The xbmc.log reports all 8 channels for m_channels on both Ubuntu Mini and Windows 7. Debug information below. • Kernel log (dmesg with drm.debug=0xe):http://paste.ubuntu.com/7811473 • Driver Codec: http://paste.ubuntu.com/7811478 • xbmc.log: http://paste.ubuntu.com/7811488 Windows 7 with (AMD proprietary drivers 13.6): • xbmc.log: http:// <http://pastebin.com/HkFPpCiR>pastebin.com <http://pastebin.com/HkFPpCiR>/ <http://pastebin.com/HkFPpCiR>HkFPpCiR <http://pastebin.com/HkFPpCiR> Thank you for any help you can provide!

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[alsa-devel] [PATCH] ALSA: hda/ca0132 - Don't try loading firmware at resume when already failed
by Takashi Iwai 10 Aug '14

10 Aug '14

CA0132 driver tries to reload the firmware at resume. Usually this works since the firmware loader core caches the firmware contents by itself. However, if the driver failed to load the firmwares (e.g. missing files), reloading the firmware at resume goes through the actual file loading code path, and triggers a kernel WARNING like: WARNING: CPU: 10 PID:11371 at drivers/base/firmware_class.c:1105 _request_firmware+0x9ab/0x9d0() For avoiding this situation, this patch makes CA0132 skipping the f/w loading at resume when it failed at probe time. Reported-and-tested-by: Janek Kozicki <cosurgi(a)gmail.com> Cc: <stable(a)vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_ca0132.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 4f3aba78f720..5d8455e2dacd 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -4376,6 +4376,9 @@ static void ca0132_download_dsp(struct hda_codec *codec) return; /* NOP */ #endif + if (spec->dsp_state == DSP_DOWNLOAD_FAILED) + return; /* don't retry failures */ + chipio_enable_clocks(codec); spec->dsp_state = DSP_DOWNLOADING; if (!ca0132_download_dsp_images(codec)) @@ -4552,7 +4555,8 @@ static int ca0132_init(struct hda_codec *codec) struct auto_pin_cfg *cfg = &spec->autocfg; int i; - spec->dsp_state = DSP_DOWNLOAD_INIT; + if (spec->dsp_state != DSP_DOWNLOAD_FAILED) + spec->dsp_state = DSP_DOWNLOAD_INIT; spec->curr_chip_addx = INVALID_CHIP_ADDRESS; snd_hda_power_up(codec); @@ -4663,6 +4667,7 @@ static int patch_ca0132(struct hda_codec *codec) codec->spec = spec; spec->codec = codec; + spec->dsp_state = DSP_DOWNLOAD_INIT; spec->num_mixers = 1; spec->mixers[0] = ca0132_mixer; -- 2.0.4

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[alsa-devel] [PATCH] ALSA: usb-audio: fix BOSS ME-25 MIDI regression
by Clemens Ladisch 10 Aug '14

10 Aug '14

The BOSS ME-25 turns out not to have any useful descriptors in its MIDI interface, so its needs a quirk entry after all. Reported-and-tested-by: Kees van Veen <kees.vanveen(a)gmail.com> Fixes: 8e5ced83dd1c ("ALSA: usb-audio: remove superfluous Roland quirks") Cc: <stable(a)vger.kernel.org> Signed-off-by: Clemens Ladisch <clemens(a)ladisch.de> --- sound/usb/quirks-table.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h index f652b10..223c47b 100644 --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h @@ -1581,6 +1581,35 @@ } }, { + /* BOSS ME-25 */ + USB_DEVICE(0x0582, 0x0113), + .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) { + .ifnum = QUIRK_ANY_INTERFACE, + .type = QUIRK_COMPOSITE, + .data = (const struct snd_usb_audio_quirk[]) { + { + .ifnum = 0, + .type = QUIRK_AUDIO_STANDARD_INTERFACE + }, + { + .ifnum = 1, + .type = QUIRK_AUDIO_STANDARD_INTERFACE + }, + { + .ifnum = 2, + .type = QUIRK_MIDI_FIXED_ENDPOINT, + .data = & (const struct snd_usb_midi_endpoint_info) { + .out_cables = 0x0001, + .in_cables = 0x0001 + } + }, + { + .ifnum = -1 + } + } + } +}, +{ /* only 44.1 kHz works at the moment */ USB_DEVICE(0x0582, 0x0120), .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {

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[alsa-devel] [PATCH 0/2] ALSA: hda - More pop noise fixes for Dell XPS 13 9333
by Gabriele Mazzotta 10 Aug '14

10 Aug '14

Fix the pop noises that happen when the laptop is booting and when it's rebooting. Gabriele Mazzotta (2): ALSA: hda - Set internal mic as default input source on Dell XPS 13 9333 ALSA: hda - Fix pop noises on reboot for Dell XPS 13 9333 sound/pci/hda/patch_realtek.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.1.0.rc1

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[alsa-devel] fast additive copy and morph functions
by Joël Krähemann 10 Aug '14

10 Aug '14

Does someone how to do fast additive copy and morph functions? This is the header of the corresponding *.c file https://sourceforge.net/p/ags/code/HEAD/tree/src/ags/audio/ags_audio_signal… https://sourceforge.net/p/ags/code/HEAD/tree/src/ags/audio/ags_audio_signal… Your contribution will be noted in these files! best regards Joël

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[alsa-devel] [PATCH] ALSA: hda - More pop noise fixes for Dell XPS 13 9333
by Gabriele Mazzotta 08 Aug '14

08 Aug '14

On init, mic-in is always set as input source, indipendently on what is plugged in. Since setting/unsetting mic-in as input source causes a pop noise, make sure the internal microphone is selected as input source on boot. On shutdown, make sure the codec is not suspended as that would cause a pop noise. Signed-off-by: Gabriele Mazzotta <gabriele.mzt(a)gmail.com> --- sound/pci/hda/hda_codec.c | 2 ++ sound/pci/hda/hda_codec.h | 1 + sound/pci/hda/patch_realtek.c | 12 ++++++++++++ 3 files changed, 15 insertions(+) diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c index 4c20277..92d8292 100644 --- a/sound/pci/hda/hda_codec.c +++ b/sound/pci/hda/hda_codec.c @@ -5348,6 +5348,8 @@ void snd_hda_bus_reboot_notify(struct hda_bus *bus) if (!bus) return; list_for_each_entry(codec, &bus->codec_list, list) { + if (codec->resume_at_reboot) + hda_call_codec_resume(codec); if (hda_codec_is_power_on(codec) && codec->patch_ops.reboot_notify) codec->patch_ops.reboot_notify(codec); diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h index 5825aa1..5c3c66e 100644 --- a/sound/pci/hda/hda_codec.h +++ b/sound/pci/hda/hda_codec.h @@ -366,6 +366,7 @@ struct hda_codec { unsigned int cached_write:1; /* write only to caches */ unsigned int dp_mst:1; /* support DP1.2 Multi-stream transport */ unsigned int dump_coef:1; /* dump processing coefs in codec proc file */ + unsigned int resume_at_reboot:1; /* resume codec at reboot */ #ifdef CONFIG_PM unsigned int power_on :1; /* current (global) power-state */ unsigned int d3_stop_clk:1; /* support D3 operation without BCLK */ diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index b60824e..defaa2a 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -4018,8 +4018,20 @@ static void alc_fixup_dell_xps13(struct hda_codec *codec, { if (action == HDA_FIXUP_ACT_PROBE) { struct alc_spec *spec = codec->spec; + struct hda_input_mux *imux = &spec->gen.input_mux; + int i; + spec->shutup = alc_no_shutup; codec->power_filter = alc_power_filter_xps13; + codec->resume_at_reboot = 1; + + /* Make the internal mic the default input source. */ + for (i = 0; i < imux->num_items; i++) { + if (spec->gen.imux_pins[i] == 0x12) { + spec->gen.cur_mux[0] = i; + break; + } + } } } -- 2.1.0.rc1

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[alsa-devel] [PATCH] ASoC: pcm512x: Correct Digital Playback control names
by Mark Brown 08 Aug '14

08 Aug '14

From: Mark Brown <broonie(a)linaro.org> The source type should come before the direction specifier according to ControlNames.txt. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- sound/soc/codecs/pcm512x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c index 163ec3855fd4..0c8aefab404c 100644 --- a/sound/soc/codecs/pcm512x.c +++ b/sound/soc/codecs/pcm512x.c @@ -259,13 +259,13 @@ static const struct soc_enum pcm512x_veds = pcm512x_ramp_step_text); static const struct snd_kcontrol_new pcm512x_controls[] = { -SOC_DOUBLE_R_TLV("Playback Digital Volume", PCM512x_DIGITAL_VOLUME_2, +SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), SOC_DOUBLE_TLV("Playback Volume", PCM512x_ANALOG_GAIN_CTRL, PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), SOC_DOUBLE_TLV("Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), -SOC_DOUBLE("Playback Digital Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT, +SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT, PCM512x_RQMR_SHIFT, 1, 1), SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), -- 2.0.1

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[alsa-devel] [PATCH] ASoC: wm8962: Correct the bit offset to enable mono speaker output
by Nicolin Chen 08 Aug '14

08 Aug '14

As WM8962 datasheet describes for SPK_MONO bit of R51: When SPK_MONO is set to '1', both speakers output the signal from the left channel. So for mono speaker widget, we shall enable Left Channel whose enable bit is 6 instead of 7 (Right Channel). This patches just simply corrects the bit offset. Signed-off-by: Peter Chan <B18700(a)freescale.com> Signed-off-by: Nicolin Chen <nicoleotsuka(a)gmail.com> --- @Peter I cced you just to let you know that I'm merging your fix to upstream. And because you patch can't be applied to the upstream tree directly, I used my own commit with your signed-off. Thank you for the fix. sound/soc/codecs/wm8962.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 1098ae3..105deec 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -2185,7 +2185,7 @@ SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, spkmixl, ARRAY_SIZE(spkmixl)), SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, out_pga_event, SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), +SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), SND_SOC_DAPM_OUTPUT("SPKOUT"), }; -- 1.8.4

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[alsa-devel] [PATCH V3 0/2] refine esai for tdm support
by Shengjiu Wang 08 Aug '14

08 Aug '14

These patchs is to refine esai for tdm support. Changes for V3 - update the comments for patch 2 Changes for V2 - update the comments according the reviewer's suggestion - add init value for slots and change pin to pins. Shengjiu Wang (2): ASoC: fsl_esai: refine esai for TDM support Revert "ASoC: fsl-esai: Add .xlate_tdm_slot_mask() support." sound/soc/fsl/Kconfig | 1 - sound/soc/fsl/fsl_esai.c | 16 +++++++++++----- sound/soc/fsl/fsl_esai.h | 8 ++++---- 3 files changed, 15 insertions(+), 10 deletions(-) -- 1.7.9.5

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