June 2023 - Alsa-devel - mailman.alsa-project.org

[PATCH v2 0/2] Fix error check and cleanup for JH7110 TDM
by Walker Chen 09 Jun '23

09 Jun '23

Some minor issues were found during addtional testing and static analysis. The first patch fix the error check for the return value of devm_reset_control_array_get_exclusive(). The second patch drop some unused macros. Fixes: fd4762b6b5cf ("ASoC: starfive: Add JH7110 TDM driver") Changes since v1: - Fix an error check in jh7110_tdm_clk_reset_get(). - Return to use *_BIT to indicate the shift and remove some unused macros. --- v1: https://lore.kernel.org/all/20230607081439.1517-1-walker.chen@starfivetech.… Walker Chen (2): ASoC: starfive: Fix an error check in jh7110_tdm_clk_reset_get() ASoC: starfive: Remove some unused macros sound/soc/starfive/jh7110_tdm.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) -- 2.17.1

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[PATCH v1] ASoC: starfive: Cleanup and fix error check for JH7110 TDM
by Walker Chen 09 Jun '23

09 Jun '23

Some minor issues were found during addtional testing and static analysis. The patch fixed these minor issues. 1.Use BIT() macro to indicate configuration for TDM registers. 2.Fix the check for devm_reset_control_array_get_exclusive return value. The devm_reset_control_array_get_exclusive() function may return NULL if it's an optional request. If optional is intended then NULL should not be treated as an error case, but as a special kind of success case. So here the IS_ERR() is used to check better. Fixes: fd4762b6b5cf ("ASoC: starfive: Add JH7110 TDM driver") Signed-off-by: Walker Chen <walker.chen(a)starfivetech.com> --- Fix the following issue: https://lore.kernel.org/all/ZH7t6Nc+NTcGpq%2F3@moroto/ --- sound/soc/starfive/jh7110_tdm.c | 200 +++++++++++--------------------- 1 file changed, 68 insertions(+), 132 deletions(-) diff --git a/sound/soc/starfive/jh7110_tdm.c b/sound/soc/starfive/jh7110_tdm.c index 973b910d2d3e..139ff091672e 100644 --- a/sound/soc/starfive/jh7110_tdm.c +++ b/sound/soc/starfive/jh7110_tdm.c @@ -24,63 +24,33 @@ #include <sound/soc.h> #include <sound/soc-dai.h> +/* Register offsets for JH7110 TDM device */ #define TDM_PCMGBCR 0x00 - #define PCMGBCR_MASK 0x1e - #define PCMGBCR_ENABLE BIT(0) - #define PCMGBCR_TRITXEN BIT(4) - #define CLKPOL_BIT 5 - #define TRITXEN_BIT 4 - #define ELM_BIT 3 - #define SYNCM_BIT 2 - #define MS_BIT 1 #define TDM_PCMTXCR 0x04 - #define PCMTXCR_TXEN BIT(0) - #define IFL_BIT 11 - #define WL_BIT 8 - #define SSCALE_BIT 4 - #define SL_BIT 2 - #define LRJ_BIT 1 #define TDM_PCMRXCR 0x08 - #define PCMRXCR_RXEN BIT(0) - #define PCMRXCR_RXSL_MASK 0xc - #define PCMRXCR_RXSL_16BIT 0x4 - #define PCMRXCR_RXSL_32BIT 0x8 - #define PCMRXCR_SCALE_MASK 0xf0 - #define PCMRXCR_SCALE_1CH 0x10 #define TDM_PCMDIV 0x0c -#define JH7110_TDM_FIFO 0x170c0000 -#define JH7110_TDM_FIFO_DEPTH 32 +/* Bit definition for TDM_PCMGBCR */ +#define TDM_PCMGBCR_SYNCM_LONG BIT(2) +#define TDM_PCMGBCR_MS_SLAVE BIT(1) +#define TDM_PCMGBCR_EN BIT(0) -enum TDM_MASTER_SLAVE_MODE { - TDM_AS_MASTER = 0, - TDM_AS_SLAVE, -}; +/* Bit definition for TDM_PCMTXCR */ +#define TDM_PCMTXCR_LEFT_J BIT(1) +#define TDM_PCMTXCR_TXEN BIT(0) -enum TDM_CLKPOL { - /* tx raising and rx falling */ - TDM_TX_RASING_RX_FALLING = 0, - /* tx falling and rx raising */ - TDM_TX_FALLING_RX_RASING, -}; +/* Bit definition for TDM_PCMRXCR */ +#define TDM_PCMRXCR_LEFT_J BIT(1) +#define TDM_PCMRXCR_RXEN BIT(0) -enum TDM_ELM { - /* only work while SYNCM=0 */ - TDM_ELM_LATE = 0, - TDM_ELM_EARLY, -}; - -enum TDM_SYNCM { - /* short frame sync */ - TDM_SYNCM_SHORT = 0, - /* long frame sync */ - TDM_SYNCM_LONG, -}; +#define JH7110_TDM_FIFO 0x170c0000 +#define JH7110_TDM_FIFO_DEPTH 32 -enum TDM_IFL { - /* FIFO to send or received : half-1/2, Quarter-1/4 */ - TDM_FIFO_HALF = 0, - TDM_FIFO_QUARTER, +enum TDM_SL { + /* send or received slot length */ + TDM_8BIT_SLOT_LEN = 0, + TDM_16BIT_SLOT_LEN, + TDM_32BIT_SLOT_LEN, }; enum TDM_WL { @@ -92,43 +62,24 @@ enum TDM_WL { TDM_32BIT_WORD_LEN, }; -enum TDM_SL { - /* send or received slot length */ - TDM_8BIT_SLOT_LEN = 0, - TDM_16BIT_SLOT_LEN, - TDM_32BIT_SLOT_LEN, -}; - -enum TDM_LRJ { - /* left-justify or right-justify */ - TDM_RIGHT_JUSTIFY = 0, - TDM_LEFT_JUSTIFT, -}; - -struct tdm_chan_cfg { - enum TDM_IFL ifl; - enum TDM_WL wl; - unsigned char sscale; - enum TDM_SL sl; - enum TDM_LRJ lrj; - unsigned char enable; -}; - struct jh7110_tdm_dev { void __iomem *tdm_base; struct device *dev; struct clk_bulk_data clks[6]; struct reset_control *resets; - enum TDM_CLKPOL clkpolity; - enum TDM_ELM elm; - enum TDM_SYNCM syncm; - enum TDM_MASTER_SLAVE_MODE ms_mode; + /* related to PCMTXCR */ + u16 txwl; + u16 txsscale; + u16 txsl; - struct tdm_chan_cfg tx; - struct tdm_chan_cfg rx; + /* related to PCMRXCR */ + u16 rxwl; + u16 rxsscale; + u16 rxsl; u16 syncdiv; + u16 syncm; u32 samplerate; u32 pcmclk; @@ -166,13 +117,13 @@ static void jh7110_tdm_start(struct jh7110_tdm_dev *tdm, u32 data; data = jh7110_tdm_readl(tdm, TDM_PCMGBCR); - jh7110_tdm_writel(tdm, TDM_PCMGBCR, data | PCMGBCR_ENABLE); + jh7110_tdm_writel(tdm, TDM_PCMGBCR, data | TDM_PCMGBCR_EN); /* restore context */ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - jh7110_tdm_writel(tdm, TDM_PCMTXCR, tdm->saved_pcmtxcr | PCMTXCR_TXEN); + jh7110_tdm_writel(tdm, TDM_PCMTXCR, tdm->saved_pcmtxcr | TDM_PCMTXCR_TXEN); else - jh7110_tdm_writel(tdm, TDM_PCMRXCR, tdm->saved_pcmrxcr | PCMRXCR_RXEN); + jh7110_tdm_writel(tdm, TDM_PCMRXCR, tdm->saved_pcmrxcr | TDM_PCMRXCR_RXEN); } static void jh7110_tdm_stop(struct jh7110_tdm_dev *tdm, @@ -182,11 +133,11 @@ static void jh7110_tdm_stop(struct jh7110_tdm_dev *tdm, if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { val = jh7110_tdm_readl(tdm, TDM_PCMTXCR); - val &= ~PCMTXCR_TXEN; + val &= ~TDM_PCMTXCR_TXEN; jh7110_tdm_writel(tdm, TDM_PCMTXCR, val); } else { val = jh7110_tdm_readl(tdm, TDM_PCMRXCR); - val &= ~PCMRXCR_RXEN; + val &= ~TDM_PCMRXCR_RXEN; jh7110_tdm_writel(tdm, TDM_PCMRXCR, val); } } @@ -195,15 +146,15 @@ static int jh7110_tdm_syncdiv(struct jh7110_tdm_dev *tdm) { u32 sl, sscale, syncdiv; - if (tdm->rx.sl >= tdm->tx.sl) - sl = tdm->rx.sl; + if (tdm->rxsl >= tdm->txsl) + sl = tdm->rxsl; else - sl = tdm->tx.sl; + sl = tdm->txsl; - if (tdm->rx.sscale >= tdm->tx.sscale) - sscale = tdm->rx.sscale; + if (tdm->rxsscale >= tdm->txsscale) + sscale = tdm->rxsscale; else - sscale = tdm->tx.sscale; + sscale = tdm->txsscale; syncdiv = tdm->pcmclk / tdm->samplerate - 1; @@ -212,10 +163,10 @@ static int jh7110_tdm_syncdiv(struct jh7110_tdm_dev *tdm) return -EINVAL; } - if (tdm->syncm == TDM_SYNCM_LONG && - (tdm->rx.sscale <= 1 || tdm->tx.sscale <= 1) && + if (tdm->syncm == TDM_PCMGBCR_SYNCM_LONG && + (tdm->rxsscale <= 1 || tdm->txsscale <= 1) && ((syncdiv + 1) <= sl)) { - dev_err(tdm->dev, "Wrong syncdiv! It must be (syncdiv+1) > max[tx.sl, rx.sl]\n"); + dev_err(tdm->dev, "Wrong syncdiv! It must be (syncdiv+1) > max[txsl, rxsl]\n"); return -EINVAL; } @@ -233,17 +184,15 @@ static int jh7110_tdm_config(struct jh7110_tdm_dev *tdm, if (ret) return ret; - datarx = (tdm->rx.ifl << IFL_BIT) | - (tdm->rx.wl << WL_BIT) | - (tdm->rx.sscale << SSCALE_BIT) | - (tdm->rx.sl << SL_BIT) | - (tdm->rx.lrj << LRJ_BIT); + datarx = (tdm->rxwl << 8) | + (tdm->rxsscale << 4) | + (tdm->rxsl << 2) | + TDM_PCMRXCR_LEFT_J; - datatx = (tdm->tx.ifl << IFL_BIT) | - (tdm->tx.wl << WL_BIT) | - (tdm->tx.sscale << SSCALE_BIT) | - (tdm->tx.sl << SL_BIT) | - (tdm->tx.lrj << LRJ_BIT); + datatx = (tdm->txwl << 8) | + (tdm->txsscale << 4) | + (tdm->txsl << 2) | + TDM_PCMTXCR_LEFT_J; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) jh7110_tdm_writel(tdm, TDM_PCMTXCR, datatx); @@ -346,7 +295,8 @@ static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); - int chan_wl, chan_sl, chan_nr; + int chan_nr; + unsigned short chan_wl, chan_sl; unsigned int data_width; unsigned int dma_bus_width; struct snd_dmaengine_dai_dma_data *dma_data = NULL; @@ -389,15 +339,15 @@ static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream, } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - tdm->tx.wl = chan_wl; - tdm->tx.sl = chan_sl; - tdm->tx.sscale = chan_nr; + tdm->txwl = chan_wl; + tdm->txsl = chan_sl; + tdm->txsscale = chan_nr; tdm->play_dma_data.addr_width = dma_bus_width; dma_data = &tdm->play_dma_data; } else { - tdm->rx.wl = chan_wl; - tdm->rx.sl = chan_sl; - tdm->rx.sscale = chan_nr; + tdm->rxwl = chan_wl; + tdm->rxsl = chan_sl; + tdm->rxsscale = chan_nr; tdm->capture_dma_data.addr_width = dma_bus_width; dma_data = &tdm->capture_dma_data; } @@ -444,15 +394,17 @@ static int jh7110_tdm_set_dai_fmt(struct snd_soc_dai *cpu_dai, struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(cpu_dai); unsigned int gbcr; + gbcr = tdm->syncm; + /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { case SND_SOC_DAIFMT_BP_FP: /* cpu is master */ - tdm->ms_mode = TDM_AS_MASTER; + gbcr &= ~TDM_PCMGBCR_MS_SLAVE; break; case SND_SOC_DAIFMT_BC_FC: /* codec is master */ - tdm->ms_mode = TDM_AS_SLAVE; + gbcr |= TDM_PCMGBCR_MS_SLAVE; break; case SND_SOC_DAIFMT_BC_FP: case SND_SOC_DAIFMT_BP_FC: @@ -462,10 +414,6 @@ static int jh7110_tdm_set_dai_fmt(struct snd_soc_dai *cpu_dai, return -EINVAL; } - gbcr = (tdm->clkpolity << CLKPOL_BIT) | - (tdm->elm << ELM_BIT) | - (tdm->syncm << SYNCM_BIT) | - (tdm->ms_mode << MS_BIT); jh7110_tdm_writel(tdm, TDM_PCMGBCR, gbcr); return 0; @@ -537,18 +485,7 @@ static const struct snd_dmaengine_pcm_config jh7110_dmaengine_pcm_config = { static void jh7110_tdm_init_params(struct jh7110_tdm_dev *tdm) { - tdm->clkpolity = TDM_TX_RASING_RX_FALLING; - tdm->elm = TDM_ELM_LATE; - tdm->syncm = TDM_SYNCM_SHORT; - - tdm->rx.ifl = TDM_FIFO_HALF; - tdm->tx.ifl = TDM_FIFO_HALF; - tdm->rx.wl = TDM_16BIT_WORD_LEN; - tdm->tx.wl = TDM_16BIT_WORD_LEN; - tdm->rx.sscale = 2; - tdm->tx.sscale = 2; - tdm->rx.lrj = TDM_LEFT_JUSTIFT; - tdm->tx.lrj = TDM_LEFT_JUSTIFT; + tdm->syncm = 0; tdm->play_dma_data.addr = JH7110_TDM_FIFO; tdm->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; @@ -580,10 +517,9 @@ static int jh7110_tdm_clk_reset_get(struct platform_device *pdev, } tdm->resets = devm_reset_control_array_get_exclusive(&pdev->dev); - if (IS_ERR_OR_NULL(tdm->resets)) { - ret = PTR_ERR(tdm->resets); - dev_err(&pdev->dev, "Failed to get tdm resets"); - return ret; + if (IS_ERR(tdm->resets)) { + dev_err(&pdev->dev, "Failed to get tdm resets\n"); + return PTR_ERR(tdm->resets); } return 0; @@ -649,12 +585,12 @@ static int jh7110_tdm_dev_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id jh7110_tdm_of_match[] = { +static const struct of_device_id jh7110_tdm_match[] = { { .compatible = "starfive,jh7110-tdm", }, {} }; -MODULE_DEVICE_TABLE(of, jh7110_tdm_of_match); +MODULE_DEVICE_TABLE(of, jh7110_tdm_match); static const struct dev_pm_ops jh7110_tdm_pm_ops = { RUNTIME_PM_OPS(jh7110_tdm_runtime_suspend, @@ -666,7 +602,7 @@ static const struct dev_pm_ops jh7110_tdm_pm_ops = { static struct platform_driver jh7110_tdm_driver = { .driver = { .name = "jh7110-tdm", - .of_match_table = jh7110_tdm_of_match, + .of_match_table = jh7110_tdm_match, .pm = pm_ptr(&jh7110_tdm_pm_ops), }, .probe = jh7110_tdm_probe, -- 2.17.1

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[PATCH v4 00/68] clk: Make determine_rate mandatory for muxes
by Maxime Ripard 09 Jun '23

09 Jun '23

Hi, This is a follow-up to a previous series that was printing a warning when a mux has a set_parent implementation but is missing determine_rate(). The rationale is that set_parent() is very likely to be useful when changing the rate, but it's determine_rate() that takes the parenting decision. If we're missing it, then the current parent is always going to be used, and thus set_parent() will not be used. The only exception being a direct call to clk_set_parent(), but those are fairly rare compared to clk_set_rate(). Stephen then asked to promote the warning to an error, and to fix up all the muxes that are in that situation first. So here it is :) It was build-tested on x86, arm and arm64. Affected drivers have been tracked down by the following coccinelle script: virtual report @ clk_ops @ identifier ops; position p; @@ struct clk_ops ops@p = { ... }; @ has_set_parent @ identifier clk_ops.ops; identifier set_parent_f; @@ struct clk_ops ops = { .set_parent = set_parent_f, }; @ has_determine_rate @ identifier clk_ops.ops; identifier determine_rate_f; @@ struct clk_ops ops = { .determine_rate = determine_rate_f, }; @ script:python depends on report && has_set_parent && !has_determine_rate @ ops << clk_ops.ops; set_parent_f << has_set_parent.set_parent_f; p << clk_ops.p; @@ coccilib.report.print_report(p[0], "ERROR: %s has set_parent (%s)" % (ops, set_parent_f)) Berlin is the only user still matching after this series has been applied, but it's because it uses a composite clock which throws the script off. The driver has been converted and shouldn't be a problem. Let me know what you think, Maxime Signed-off-by: Maxime Ripard <maxime(a)cerno.tech> --- Changes in v4: - Switch from __clk_mux_determine_rate to a new helper - Introduced unit tests for that new helper - Fix kunit regression - Reworded most of the commit logs - Link to v3: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v3-0-9a1358472d52… Changes in v3: - Rebased on top of next-20230404 - Link to v2: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v2-0-f6736dec138e… Changes in v2: - Drop all the patches already applied - Promote the clk registration warning to an error - Make all muxes use determine_rate - Link to v1: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v1-0-f3ef80518140… --- Maxime Ripard (66): clk: Export clk_hw_forward_rate_request() clk: test: Fix type sign of rounded rate variables clk: lan966x: Remove unused round_rate hook clk: nodrv: Add a determine_rate hook clk: test: Add a determine_rate hook clk: actions: composite: Add a determine_rate hook for pass clk clk: at91: main: Add a determine_rate hook clk: at91: sckc: Add a determine_rate hook clk: berlin: div: Add a determine_rate hook clk: cdce706: Add a determine_rate hook clk: k210: pll: Add a determine_rate hook clk: k210: aclk: Add a determine_rate hook clk: k210: mux: Add a determine_rate hook clk: lmk04832: clkout: Add a determine_rate hook clk: lochnagar: Add a determine_rate hook clk: qoriq: Add a determine_rate hook clk: si5341: Add a determine_rate hook clk: stm32f4: mux: Add a determine_rate hook clk: vc5: mux: Add a determine_rate hook clk: vc5: clkout: Add a determine_rate hook clk: wm831x: clkout: Add a determine_rate hook clk: davinci: da8xx-cfgchip: Add a determine_rate hook clk: davinci: da8xx-cfgchip: Add a determine_rate hook clk: imx: busy: Add a determine_rate hook clk: imx: fixup-mux: Add a determine_rate hook clk: imx: scu: Add a determine_rate hook clk: mediatek: cpumux: Add a determine_rate hook clk: pxa: Add a determine_rate hook clk: renesas: r9a06g032: Add a determine_rate hook clk: socfpga: gate: Add a determine_rate hook clk: stm32: core: Add a determine_rate hook clk: tegra: bpmp: Add a determine_rate hook clk: tegra: super: Add a determine_rate hook clk: tegra: periph: Add a determine_rate hook clk: ux500: prcmu: Add a determine_rate hook clk: ux500: sysctrl: Add a determine_rate hook clk: versatile: sp810: Add a determine_rate hook drm/tegra: sor: Add a determine_rate hook phy: cadence: sierra: Add a determine_rate hook phy: cadence: torrent: Add a determine_rate hook phy: ti: am654-serdes: Add a determine_rate hook phy: ti: j721e-wiz: Add a determine_rate hook rtc: sun6i: Add a determine_rate hook ASoC: tlv320aic32x4: Add a determine_rate hook clk: actions: composite: div: Switch to determine_rate clk: actions: composite: fact: Switch to determine_rate clk: at91: smd: Switch to determine_rate clk: axi-clkgen: Switch to determine_rate clk: cdce706: divider: Switch to determine_rate clk: cdce706: clkout: Switch to determine_rate clk: si5341: Switch to determine_rate clk: si5351: pll: Switch to determine_rate clk: si5351: msynth: Switch to determine_rate clk: si5351: clkout: Switch to determine_rate clk: da8xx: clk48: Switch to determine_rate clk: imx: scu: Switch to determine_rate clk: ingenic: cgu: Switch to determine_rate clk: ingenic: tcu: Switch to determine_rate clk: sprd: composite: Switch to determine_rate clk: st: flexgen: Switch to determine_rate clk: stm32: composite: Switch to determine_rate clk: tegra: periph: Switch to determine_rate clk: tegra: super: Switch to determine_rate ASoC: tlv320aic32x4: pll: Switch to determine_rate ASoC: tlv320aic32x4: div: Switch to determine_rate clk: Forbid to register a mux without determine_rate Stephen Boyd (2): clk: Move no reparent case into a separate function clk: Introduce clk_hw_determine_rate_no_reparent() drivers/clk/actions/owl-composite.c | 35 ++++-- drivers/clk/at91/clk-main.c | 1 + drivers/clk/at91/clk-smd.c | 29 +++-- drivers/clk/at91/sckc.c | 1 + drivers/clk/berlin/berlin2-div.c | 1 + drivers/clk/clk-axi-clkgen.c | 14 ++- drivers/clk/clk-cdce706.c | 30 ++--- drivers/clk/clk-k210.c | 3 + drivers/clk/clk-lan966x.c | 17 --- drivers/clk/clk-lmk04832.c | 1 + drivers/clk/clk-lochnagar.c | 1 + drivers/clk/clk-qoriq.c | 1 + drivers/clk/clk-si5341.c | 19 ++-- drivers/clk/clk-si5351.c | 67 ++++++----- drivers/clk/clk-stm32f4.c | 1 + drivers/clk/clk-versaclock5.c | 2 + drivers/clk/clk-wm831x.c | 1 + drivers/clk/clk.c | 108 ++++++++++++------ drivers/clk/clk_test.c | 180 +++++++++++++++++++++++++++++- drivers/clk/davinci/da8xx-cfgchip.c | 12 +- drivers/clk/imx/clk-busy.c | 1 + drivers/clk/imx/clk-fixup-mux.c | 1 + drivers/clk/imx/clk-scu.c | 20 +++- drivers/clk/ingenic/cgu.c | 15 +-- drivers/clk/ingenic/tcu.c | 19 ++-- drivers/clk/mediatek/clk-cpumux.c | 1 + drivers/clk/pxa/clk-pxa.c | 1 + drivers/clk/renesas/r9a06g032-clocks.c | 1 + drivers/clk/socfpga/clk-gate.c | 1 + drivers/clk/sprd/composite.c | 16 ++- drivers/clk/st/clk-flexgen.c | 15 +-- drivers/clk/stm32/clk-stm32-core.c | 33 ++++-- drivers/clk/tegra/clk-bpmp.c | 1 + drivers/clk/tegra/clk-periph.c | 17 ++- drivers/clk/tegra/clk-super.c | 16 ++- drivers/clk/ux500/clk-prcmu.c | 1 + drivers/clk/ux500/clk-sysctrl.c | 1 + drivers/clk/versatile/clk-sp810.c | 1 + drivers/gpu/drm/tegra/sor.c | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 1 + drivers/phy/cadence/phy-cadence-torrent.c | 1 + drivers/phy/ti/phy-am654-serdes.c | 1 + drivers/phy/ti/phy-j721e-wiz.c | 1 + drivers/rtc/rtc-sun6i.c | 1 + include/linux/clk-provider.h | 2 + sound/soc/codecs/tlv320aic32x4-clk.c | 33 +++--- 46 files changed, 527 insertions(+), 199 deletions(-) --- base-commit: 145e5cddfe8b4bf607510b2dcf630d95f4db420f change-id: 20221018-clk-range-checks-fixes-2039f3523240 Best regards, -- Maxime Ripard <maxime(a)cerno.tech>

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[PATCH] ASoC: stac9766: fix build errors with REGMAP_AC97
by Randy Dunlap 09 Jun '23

09 Jun '23

Select REGMAP_AC97 to fix these build errors: ERROR: modpost: "regmap_ac97_default_volatile" [sound/soc/codecs/snd-soc-stac9766.ko] undefined! ERROR: modpost: "__regmap_init_ac97" [sound/soc/codecs/snd-soc-stac9766.ko] undefined! Fixes: 6bbf787bb70c ("ASoC: stac9766: Convert to regmap") Signed-off-by: Randy Dunlap <rdunlap(a)infradead.org> Cc: Lars-Peter Clausen <lars(a)metafoo.de> Cc: Mark Brown <broonie(a)kernel.org> Cc: Liam Girdwood <lgirdwood(a)gmail.com> Cc: alsa-devel(a)alsa-project.org --- sound/soc/codecs/Kconfig | 1 + 1 file changed, 1 insertion(+) diff -- a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1693,6 +1693,7 @@ config SND_SOC_STA529 config SND_SOC_STAC9766 tristate depends on SND_SOC_AC97_BUS + select REGMAP_AC97 config SND_SOC_STI_SAS tristate "codec Audio support for STI SAS codec"

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[PATCH] ASoC: max98088: clean up some inconsistent indenting
by Jiapeng Chong 08 Jun '23

08 Jun '23

No functional modification involved. sound/soc/codecs/max98088.c:316 m98088_eq_band() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5461 Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> --- sound/soc/codecs/max98088.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index fb136e2b849b..8b56ee550c09 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -310,24 +310,24 @@ static const struct regmap_config max98088_regmap = { static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai, unsigned int band, u16 *coefs) { - unsigned int eq_reg; - unsigned int i; + unsigned int eq_reg; + unsigned int i; if (WARN_ON(band > 4) || WARN_ON(dai > 1)) return; - /* Load the base register address */ - eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; + /* Load the base register address */ + eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; - /* Add the band address offset, note adjustment for word address */ - eq_reg += band * (M98088_COEFS_PER_BAND << 1); + /* Add the band address offset, note adjustment for word address */ + eq_reg += band * (M98088_COEFS_PER_BAND << 1); - /* Step through the registers and coefs */ - for (i = 0; i < M98088_COEFS_PER_BAND; i++) { - snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i])); - snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i])); - } + /* Step through the registers and coefs */ + for (i = 0; i < M98088_COEFS_PER_BAND; i++) { + snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i])); + snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i])); + } } /* -- 2.20.1.7.g153144c

2 1

[PATCH] ASoC: tegra: Simplify code around clk_get_rate() handling
by Christophe JAILLET 08 Jun '23

08 Jun '23

clk_get_rate() returns an unsigned long, so there is no point in storing it in a long, and test for negative values. So, turn 'parent_rate' into an unsigned long, simplify the sanity check, the error message and the return value, in case of error (i.e. 0). Doing so also turns 'i' and 'valid_rates' into unsigned long, but it is fine and harmless. Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- sound/soc/tegra/tegra20_i2s.c | 9 ++++----- sound/soc/tegra/tegra20_spdif.c | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c index e1a0f50969c1..d38b58305c6b 100644 --- a/sound/soc/tegra/tegra20_i2s.c +++ b/sound/soc/tegra/tegra20_i2s.c @@ -273,13 +273,12 @@ static int tegra20_i2s_filter_rates(struct snd_pcm_hw_params *params, struct snd_soc_dai *dai = rule->private; struct tegra20_i2s *i2s = dev_get_drvdata(dai->dev); struct clk *parent = clk_get_parent(i2s->clk_i2s); - long i, parent_rate, valid_rates = 0; + unsigned long i, parent_rate, valid_rates = 0; parent_rate = clk_get_rate(parent); - if (parent_rate <= 0) { - dev_err(dai->dev, "Can't get parent clock rate: %ld\n", - parent_rate); - return parent_rate ?: -EINVAL; + if (!parent_rate) { + dev_err(dai->dev, "Can't get parent clock rate\n"); + return -EINVAL; } for (i = 0; i < ARRAY_SIZE(tegra20_i2s_rates); i++) { diff --git a/sound/soc/tegra/tegra20_spdif.c b/sound/soc/tegra/tegra20_spdif.c index 86bef54dfdf2..d034803695a0 100644 --- a/sound/soc/tegra/tegra20_spdif.c +++ b/sound/soc/tegra/tegra20_spdif.c @@ -187,13 +187,12 @@ static int tegra20_spdif_filter_rates(struct snd_pcm_hw_params *params, struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev); struct clk *parent = clk_get_parent(spdif->clk_spdif_out); static const unsigned int rates[] = { 32000, 44100, 48000 }; - long i, parent_rate, valid_rates = 0; + unsigned long i, parent_rate, valid_rates = 0; parent_rate = clk_get_rate(parent); - if (parent_rate <= 0) { - dev_err(dai->dev, "Can't get parent clock rate: %ld\n", - parent_rate); - return parent_rate ?: -EINVAL; + if (!parent_rate) { + dev_err(dai->dev, "Can't get parent clock rate\n"); + return -EINVAL; } for (i = 0; i < ARRAY_SIZE(rates); i++) { -- 2.34.1

2 1

[PATCH v2 0/3] ASoC: stm32: fix dtbs_check warnings
by Olivier Moysan 08 Jun '23

08 Jun '23

Fix dtbs_check warnings in STM32MP15 DK boards Devices Trees for STM32 I2S and Cirrus CS42L51 codec. - Add OF graph port property in I2S and CS42L51 DT bindings. Fixes warnings: audio-controller@4000b000: Unevaluated properties are not allowed ('port' was unexpected) cs42l51@4a: Unevaluated properties are not allowed ('port' was unexpected) - Correct OF graph DAI audio format property for STM32MP15x Dkx I2S node Changes in v2: - Add port example in i2s and cs42l51 binding Olivier Moysan (3): ASoC: dt-bindings: stm32: document audio of graph port for i2s ASoC: dt-bindings: document audio of graph port for cs42l51 ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx .../devicetree/bindings/sound/cirrus,cs42l51.yaml | 11 +++++++++++ .../devicetree/bindings/sound/st,stm32-i2s.yaml | 11 +++++++++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 2 +- 3 files changed, 23 insertions(+), 1 deletion(-) -- 2.25.1

4 6

[PATCH] soundwire: debugfs: Add missing SCP registers
by Bard Liao 08 Jun '23

08 Jun '23

From: Uday M Bhat <uday.m.bhat(a)intel.com> SCP registers needs to be updated to accommodate additional register entries as per the Soundwire 1.2 specification. Signed-off-by: Uday M Bhat <uday.m.bhat(a)intel.com> Signed-off-by: Yong Zhi <yong.zhi(a)intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> --- drivers/soundwire/debugfs.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/soundwire/debugfs.c b/drivers/soundwire/debugfs.c index c3a1a359ee5c..d1553cb77187 100644 --- a/drivers/soundwire/debugfs.c +++ b/drivers/soundwire/debugfs.c @@ -86,10 +86,17 @@ static int sdw_slave_reg_show(struct seq_file *s_file, void *data) /* SCP registers */ ret += scnprintf(buf + ret, RD_BUF - ret, "\nSCP\n"); - for (i = SDW_SCP_INT1; i <= SDW_SCP_BANKDELAY; i++) + for (i = SDW_SCP_INT1; i <= SDW_SCP_BUS_CLOCK_BASE; i++) ret += sdw_sprintf(slave, buf, ret, i); for (i = SDW_SCP_DEVID_0; i <= SDW_SCP_DEVID_5; i++) ret += sdw_sprintf(slave, buf, ret, i); + for (i = SDW_SCP_FRAMECTRL_B0; i <= SDW_SCP_BUSCLOCK_SCALE_B0; i++) + ret += sdw_sprintf(slave, buf, ret, i); + for (i = SDW_SCP_FRAMECTRL_B1; i <= SDW_SCP_BUSCLOCK_SCALE_B1; i++) + ret += sdw_sprintf(slave, buf, ret, i); + for (i = SDW_SCP_PHY_OUT_CTRL_0; i <= SDW_SCP_PHY_OUT_CTRL_7; i++) + ret += sdw_sprintf(slave, buf, ret, i); + /* * SCP Bank 0/1 registers are read-only and cannot be -- 2.25.1

2 1

[PATCH v2 1/5] soundwire: stream: Add missing clear of alloc_slave_rt
by Charles Keepax 08 Jun '23

08 Jun '23

The current path that skips allocating the slave runtime does not clear the alloc_slave_rt flag, this is clearly incorrect. Add the missing clear, so the runtime won't be erroneously cleaned up. Fixes: f3016b891c8c ("soundwire: stream: sdw_stream_add_ functions can be called multiple times") Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Signed-off-by: Charles Keepax <ckeepax(a)opensource.cirrus.com> --- Changes since v1: - Added missing fixes tag Thanks, Charles drivers/soundwire/stream.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/soundwire/stream.c b/drivers/soundwire/stream.c index c2191c07442b0..379228f221869 100644 --- a/drivers/soundwire/stream.c +++ b/drivers/soundwire/stream.c @@ -2021,8 +2021,10 @@ int sdw_stream_add_slave(struct sdw_slave *slave, skip_alloc_master_rt: s_rt = sdw_slave_rt_find(slave, stream); - if (s_rt) + if (s_rt) { + alloc_slave_rt = false; goto skip_alloc_slave_rt; + } s_rt = sdw_slave_rt_alloc(slave, m_rt); if (!s_rt) { -- 2.30.2

3 8

[PATCH 0/5] ASoC: mt8188-mt6359: Cleanups
by AngeloGioacchino Del Regno 08 Jun '23

08 Jun '23

This series performs some cleanups to the mt8188-mt6359 driver, including usage of bitfield macros, adding definitions of register fields and some others for readability and consistency. AngeloGioacchino Del Regno (4): ASoC: mediatek: mt8188-mt6359: Compress of_device_id entries ASoC: mediatek: mt8188-mt6359: Cleanup return 0 disguised as return ret ASoC: mediatek: mt8188-mt6359: Clean up log levels ASoC: mediatek: mt8188-mt6359: Use bitfield macros for registers Dan Carpenter (1): ASoC: mediatek: mt8188-mt6359: clean up a return in codec_init sound/soc/mediatek/mt8188/mt8188-mt6359.c | 87 ++++++++++++----------- 1 file changed, 45 insertions(+), 42 deletions(-) -- 2.40.1

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