December 2015 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCH] ASoC: Intel: sst: fix the IRQ locked issue
by Jie Yang 15 Dec '15

15 Dec '15

From: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> If driver received a message that it can't handle, it won't clear the corresponding bit and unmask interrupt, this may lock the IRQ and DSP can't send message anymore. To fix the issue, we should Always update IMRX after IPC. Here we always clear the DONE/BUSY bit and unmask the IRQ source, even when IPC failures have occurred previously. Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> Modified-by: Jie Yang <yang.jie(a)intel.com> Signed-off-by: Jie Yang <yang.jie(a)intel.com> --- sound/soc/intel/haswell/sst-haswell-ipc.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/sound/soc/intel/haswell/sst-haswell-ipc.c b/sound/soc/intel/haswell/sst-haswell-ipc.c index b27f25f..ac60f13 100644 --- a/sound/soc/intel/haswell/sst-haswell-ipc.c +++ b/sound/soc/intel/haswell/sst-haswell-ipc.c @@ -778,7 +778,6 @@ static irqreturn_t hsw_irq_thread(int irq, void *context) struct sst_hsw *hsw = sst_dsp_get_thread_context(sst); struct sst_generic_ipc *ipc = &hsw->ipc; u32 ipcx, ipcd; - int handled; unsigned long flags; spin_lock_irqsave(&sst->spinlock, flags); @@ -790,34 +789,30 @@ static irqreturn_t hsw_irq_thread(int irq, void *context) if (ipcx & SST_IPCX_DONE) { /* Handle Immediate reply from DSP Core */ - handled = hsw_process_reply(hsw, ipcx); + hsw_process_reply(hsw, ipcx); - if (handled > 0) { - /* clear DONE bit - tell DSP we have completed */ - sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX, - SST_IPCX_DONE, 0); + /* clear DONE bit - tell DSP we have completed */ + sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX, + SST_IPCX_DONE, 0); - /* unmask Done interrupt */ - sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, - SST_IMRX_DONE, 0); - } + /* unmask Done interrupt */ + sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, + SST_IMRX_DONE, 0); } /* new message from DSP */ if (ipcd & SST_IPCD_BUSY) { /* Handle Notification and Delayed reply from DSP Core */ - handled = hsw_process_notification(hsw); + hsw_process_notification(hsw); /* clear BUSY bit and set DONE bit - accept new messages */ - if (handled > 0) { - sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD, - SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE); + sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD, + SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE); - /* unmask busy interrupt */ - sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, - SST_IMRX_BUSY, 0); - } + /* unmask busy interrupt */ + sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, + SST_IMRX_BUSY, 0); } spin_unlock_irqrestore(&sst->spinlock, flags); -- 2.5.0

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[alsa-devel] [PATCH 1/3] rcar: ctu: Avoid use of ret uninitialised
by Mark Brown 15 Dec '15

15 Dec '15

We use ret as the return value from the rsnd_ctu_probe() but if there are no child nodes and no errors then we will never initialize ret leading to build warnings. Ensure ret is initialized before we iterate over the child nodes to avoid this. Signed-off-by: Mark Brown <broonie(a)kernel.org> --- Perhaps this should be an error instead? It's not like it's a sensible configuration... sound/soc/sh/rcar/ctu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/sh/rcar/ctu.c b/sound/soc/sh/rcar/ctu.c index 7c1e190cd389..d53a225d19e9 100644 --- a/sound/soc/sh/rcar/ctu.c +++ b/sound/soc/sh/rcar/ctu.c @@ -111,6 +111,7 @@ int rsnd_ctu_probe(struct rsnd_priv *priv) priv->ctu = ctu; i = 0; + ret = 0; for_each_child_of_node(node, np) { ctu = rsnd_ctu_get(priv, i); -- 2.6.2

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[alsa-devel] [RFC][PATCH 00/10 v2] ALSA: dice: stabiliza packet streaming
by Takashi Sakamoto 15 Dec '15

15 Dec '15

This patchset updates my previous one: [alsa-devel] [RFC][PATCH 0/8] ALSA: dice: constrain PCM substreams to current sampling transfer frequency http://mailman.alsa-project.org/pipermail/alsa-devel/2015-November/100670.h… I hope more users to test this patchset in this developing cycle. [Background] I've frequently got private messages from owners of dice-based models since below patchset was merged to mainline: [alsa-devel] [PATCH 00/15 v5] ALSA: Enhancement for existed FireWire drivers http://mailman.alsa-project.org/pipermail/alsa-devel/2014-December/085142.h… Some of them addressed that ALSA dice driver fails to handle their models, while their experiences are not the same. The summary: * ETIMEOUT at starting streaming * detecting packet discontinuity at starting streaming * ETIMEOUT at probing snd-dice * no sound even if starting streaming This patchset is my solutions for these issues. It consists of four parts; [Patch 01] ETIMEDOUT at starting streaming means that ALSA dice driver has never received dice notification within current timeout (200 msec). This patch expands the timeout up to 2 sec. There's some disadvantages of this change in usage of ALSA PCM API, see commit comment. [Patch 02] Packet discontinuity at starting streaming means that the device fail to get constant clock signals from phase lock loop (PLL) circuit. In this case, ALSA dice driver successfully starts streaming and receives AMDTP packet from the device, therefore any dice notifications are already transferred. It's reasonable to judge that the device has a quirk to transfer the notification before set its PLL circuit steadily. This patch continue to check a register so that the device get phase lock after receiving dice notification. [Patch 03-04] When connected to IEEE 1394 bus, some models generate bus reset after appearing on bus topology. Usually, boot processing of Dice based models consists of three stages; boot loader (RedBoot) is loaded, it loads eCos, the operating system executes vendor's configurations for hardware initialization. It's reasonable to assume that bus reset occurs at each of these stages. Furthermore, I observed that ImpactTwin (TC Electronic produced) changes some registers before/after ALSA dice driver is probed with my RFC v1. This means that the hardware initialization requires a bit time. These patches postpone unit probe processing after continuous bus resets. These patches have advantages to start communication to the device after the hardware initialization. These patches may improve handling Dice II based models such as ImpactTwin and IO26 (Alesis produces). [Patch 05-10] When seeing sound/firewire/dice/dice-interface.h, Dice interface gives no ways for drivers to get all formats of AMDTP stream. Current ALSA dice driver manage to generate 'format cache' at unit probing processing, while this requires to change the state of actual clock on devices. This idea is not good because of ignoring hardware design. This idea is not good in a case that users save their favorite configuration to the device. Furthermore, this is not also good in a case that the stream format is not decided according to sampling transfer frequency only, i.e. data format of digital interface is also dominant to the stream format. These patches add limitation to constrain PCM substream at current sampling transfer frequency. As a result, userspace applications are allowed to request according to current sampling transfer frequency. When users change the frequency, they should use userspace applications with fw character devices to set it in advance. ALSA dice driver gives no way to achieve it in describes reasons. Although ALSA dice driver goes backward with these patchset, we don't beat any actual hardware designs. [Changes from RFC v1] * Patch 03-04 are newly added. This enables to handle bus reset at unit probe processing, and drops one of reasons to constrain PCM substreams at current sampling transfer frequency. * Minor arrangements Takashi Sakamoto (10): ALSA: dice: expand timeout to wait for Dice notification ALSA: dice: wait for ensuring phase lock ALSA: dice: split subaddress check from category check ALSA: dice: postpone probe processing ALSA: dice: limit to current sampling transfer frequency ALSA: dice: limit stream to current sampling transfer frequency. ALSA: dice: add MIDI ports according to current number of MIDI substreams ALSA: dice: get the number of MBLA data channel at opening PCM substream ALSA: dice: purge generating channel cache ALSA: dice: ensure phase lock before starting streaming sound/firewire/dice/dice-midi.c | 25 +++- sound/firewire/dice/dice-pcm.c | 201 ++++++++------------------- sound/firewire/dice/dice-stream.c | 84 ++++++++---- sound/firewire/dice/dice-transaction.c | 158 ++++++++++----------- sound/firewire/dice/dice.c | 242 ++++++++++++--------------------- sound/firewire/dice/dice.h | 11 +- 6 files changed, 293 insertions(+), 428 deletions(-) -- 2.5.0

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[alsa-devel] [PATCH 0/3] Yet more noise fixes for Thinkpad
by Takashi Iwai 15 Dec '15

15 Dec '15

Hi, here is a series of small patches to reduce still existing crackling noises on Thinkpad with Realtek codecs. Takashi Iwai (3): ALSA: hda - Apply click noise workaround for Thinkpads generically ALSA: hda - Set codec to D3 at reboot/shutdown on Thinkpads ALSA: hda - Add a fixup for Thinkpad X1 Carbon 2nd sound/pci/hda/patch_realtek.c | 39 +++++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 14 deletions(-) -- 2.6.4

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[alsa-devel] [PATCH] ALSA: hda - Fix headphone mic input on a few Dell ALC293 machines
by David Henningsson 15 Dec '15

15 Dec '15

These laptops support both headphone, headset and mic modes for the 3.5mm jack. Cc: stable(a)vger.kernel.org BugLink: https://bugs.launchpad.net/bugs/1526330 Signed-off-by: David Henningsson <david.henningsson(a)canonical.com> --- sound/pci/hda/patch_realtek.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 8dd2ac1..b745a72 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -4606,6 +4606,7 @@ enum { ALC288_FIXUP_DISABLE_AAMIX, ALC292_FIXUP_DELL_E7X, ALC292_FIXUP_DISABLE_AAMIX, + ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK, ALC298_FIXUP_DELL1_MIC_NO_PRESENCE, ALC275_FIXUP_DELL_XPS, ALC256_FIXUP_DELL_XPS_13_HEADPHONE_NOISE, @@ -5169,6 +5170,12 @@ static const struct hda_fixup alc269_fixups[] = { .chained = true, .chain_id = ALC269_FIXUP_DELL2_MIC_NO_PRESENCE }, + [ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc_fixup_disable_aamix, + .chained = true, + .chain_id = ALC293_FIXUP_DELL1_MIC_NO_PRESENCE + }, [ALC292_FIXUP_DELL_E7X] = { .type = HDA_FIXUP_FUNC, .v.func = alc_fixup_dell_xps13, @@ -5247,11 +5254,11 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1028, 0x06c7, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x06d9, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x06da, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE), - SND_PCI_QUIRK(0x1028, 0x06db, "Dell", ALC292_FIXUP_DISABLE_AAMIX), - SND_PCI_QUIRK(0x1028, 0x06dd, "Dell", ALC292_FIXUP_DISABLE_AAMIX), - SND_PCI_QUIRK(0x1028, 0x06de, "Dell", ALC292_FIXUP_DISABLE_AAMIX), - SND_PCI_QUIRK(0x1028, 0x06df, "Dell", ALC292_FIXUP_DISABLE_AAMIX), - SND_PCI_QUIRK(0x1028, 0x06e0, "Dell", ALC292_FIXUP_DISABLE_AAMIX), + SND_PCI_QUIRK(0x1028, 0x06db, "Dell", ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK), + SND_PCI_QUIRK(0x1028, 0x06dd, "Dell", ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK), + SND_PCI_QUIRK(0x1028, 0x06de, "Dell", ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK), + SND_PCI_QUIRK(0x1028, 0x06df, "Dell", ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK), + SND_PCI_QUIRK(0x1028, 0x06e0, "Dell", ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK), SND_PCI_QUIRK(0x1028, 0x0704, "Dell XPS 13", ALC256_FIXUP_DELL_XPS_13_HEADPHONE_NOISE), SND_PCI_QUIRK(0x1028, 0x164a, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x164b, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE), -- 1.9.1

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[alsa-devel] [PATCH 1/2] ALSA: hda - Clean up the code to check bdl_pos_adj option
by Takashi Iwai 15 Dec '15

15 Dec '15

Just a minor cleanup; instead of passing an array, pass the assigned bdl_pos_adj option value directory in struct azx. Also split the code to get the default bdl_pos_adj value for the change that will follow after this. Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/hda_controller.c | 3 +-- sound/pci/hda/hda_controller.h | 2 +- sound/pci/hda/hda_intel.c | 29 ++++++++++++++++------------- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index 22dbfa563919..10c77074b4dc 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -1050,8 +1050,7 @@ int azx_bus_init(struct azx *chip, const char *model, if (chip->get_position[0] != azx_get_pos_lpib || chip->get_position[1] != azx_get_pos_lpib) bus->core.use_posbuf = true; - if (chip->bdl_pos_adj) - bus->core.bdl_pos_adj = chip->bdl_pos_adj[chip->dev_index]; + bus->core.bdl_pos_adj = chip->bdl_pos_adj; if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR) bus->core.corbrp_self_clear = true; diff --git a/sound/pci/hda/hda_controller.h b/sound/pci/hda/hda_controller.h index c1d28a657f19..a32ec9004edd 100644 --- a/sound/pci/hda/hda_controller.h +++ b/sound/pci/hda/hda_controller.h @@ -147,7 +147,7 @@ struct azx { #endif /* flags */ - const int *bdl_pos_adj; + int bdl_pos_adj; int poll_count; unsigned int running:1; unsigned int single_cmd:1; diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index fe9bef339cea..a17bf0467edc 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -632,7 +632,7 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) /* NG - it's below the first next period boundary */ - return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; + return chip->bdl_pos_adj ? 0 : -1; azx_dev->core.start_wallclk += wallclk; return 1; /* OK, it's fine */ } @@ -1488,6 +1488,17 @@ static void azx_probe_work(struct work_struct *work) azx_probe_continue(&hda->chip); } +static int default_bdl_pos_adj(struct azx *chip) +{ + switch (chip->driver_type) { + case AZX_DRIVER_ICH: + case AZX_DRIVER_PCH: + return 1; + default: + return 32; + } +} + /* * constructor */ @@ -1541,18 +1552,10 @@ static int azx_create(struct snd_card *card, struct pci_dev *pci, chip->single_cmd = single_cmd; azx_check_snoop_available(chip); - if (bdl_pos_adj[dev] < 0) { - switch (chip->driver_type) { - case AZX_DRIVER_ICH: - case AZX_DRIVER_PCH: - bdl_pos_adj[dev] = 1; - break; - default: - bdl_pos_adj[dev] = 32; - break; - } - } - chip->bdl_pos_adj = bdl_pos_adj; + if (bdl_pos_adj[dev] < 0) + chip->bdl_pos_adj = default_bdl_pos_adj(chip); + else + chip->bdl_pos_adj = bdl_pos_adj[dev]; err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); if (err < 0) { -- 2.6.4

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[alsa-devel] [PATCH] ASoC: Atmel: ClassD: unregister codec when error occurs
by Songjun Wu 15 Dec '15

15 Dec '15

Add code to unregister codec in probe function, when the error occurs after the codec is registered. Signed-off-by: Songjun Wu <songjun.wu(a)atmel.com> --- sound/soc/atmel/atmel-classd.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/sound/soc/atmel/atmel-classd.c b/sound/soc/atmel/atmel-classd.c index dca6141..6107de9 100644 --- a/sound/soc/atmel/atmel-classd.c +++ b/sound/soc/atmel/atmel-classd.c @@ -640,8 +640,10 @@ static int atmel_classd_probe(struct platform_device *pdev) /* register sound card */ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); - if (!card) - return -ENOMEM; + if (!card) { + ret = -ENOMEM; + goto unregister_codec; + } snd_soc_card_set_drvdata(card, dd); platform_set_drvdata(pdev, card); @@ -649,16 +651,20 @@ static int atmel_classd_probe(struct platform_device *pdev) ret = atmel_classd_asoc_card_init(dev, card); if (ret) { dev_err(dev, "failed to init sound card\n"); - return ret; + goto unregister_codec; } ret = devm_snd_soc_register_card(dev, card); if (ret) { dev_err(dev, "failed to register sound card: %d\n", ret); - return ret; + goto unregister_codec; } return 0; + +unregister_codec: + snd_soc_unregister_codec(dev); + return ret; } static int atmel_classd_remove(struct platform_device *pdev) -- 1.7.9.5

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[alsa-devel] Can I stop sound from driver as system error ?
by Kuninori Morimoto 15 Dec '15

15 Dec '15

Hi I wonder can I stop sound from driver side (not from user-land) as system error during playback or capture ? How to do it if we can ? Best regards --- Kuninori Morimoto

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[alsa-devel] Intel Cherry Trail -- No sound in linux
by Zhihe Tu 14 Dec '15

14 Dec '15

Hi All, I'm trying to make the CherryTrail tablet works in ubuntu14.04.3, there's no sound at all, but it works in win8 & android. ... [ 5.463371] cht-bsw-rt5672 cht-bsw-rt5672: snd-soc-dummy-dai <-> media-cpu-dai mapping ok [ 5.463406] compress asoc: snd-soc-dummy-dai <-> compress-cpu-dai mapping ok [ 5.475786] cht-bsw-rt5672 cht-bsw-rt5672: rt5670-aif1 <-> ssp2-port mapping ok [ 5.507355] hid-generic 0003:413C:2003.0002: input,hidraw1: USB HID v1.10 Keyboard [Dell Dell USB Keyboard] on usb-0000:00:14.0-4.2/input0 [ 5.695892] Console: switching to colour frame buffer device 170x48 [ 5.712458] i915_bpo 0000:00:02.0: fb0: inteldrmfb frame buffer device [ 5.712461] i915_bpo 0000:00:02.0: registered panic notifier [ 5.725983] cfg80211: Calling CRDA to update world regulatory domain [ 5.872710] scsi 0:0:0:0: Direct-Access ASMT 2115 0 PQ: 0 ANSI: 6 [ 5.873522] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 5.875671] sd 0:0:0:0: [sda] Attached SCSI removable disk [ 5.907038] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 0 doesn't have DAPM widget!!! [ 5.922073] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 1 doesn't have DAPM widget!!! [ 5.935876] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 2 doesn't have DAPM widget!!! [ 5.949941] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 3 doesn't have DAPM widget!!! [ 5.968241] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in0_0 doesn't have DAPM widget!!! [ 5.968267] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in0_1 doesn't have DAPM widget!!! [ 5.968292] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in1_0 doesn't have DAPM widget!!! [ 5.968318] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in1_1 doesn't have DAPM widget!!! ... [ 6.617144] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 0 doesn't have DAPM widget!!! [ 6.632519] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 1 doesn't have DAPM widget!!! [ 6.647501] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 2 doesn't have DAPM widget!!! [ 6.662176] sst-mfld-platform sst-mfld-platform: Slot control: codec_out tx interleaver slot 3 doesn't have DAPM widget!!! [ 6.677049] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in0_0 doesn't have DAPM widget!!! [ 6.692739] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in0_1 doesn't have DAPM widget!!! [ 6.692765] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in1_0 doesn't have DAPM widget!!! [ 6.692792] sst-mfld-platform sst-mfld-platform: Slot control: codec_in rx deinterleaver codec_in1_1 doesn't have DAPM widget!!! [ 7.541669] init: plymouth-upstart-bridge main process ended, respawning [ 9.804555] Audio Port: ASoC: no backend DAIs enabled for Audio Port [ 10.139952] Audio Port: ASoC: no backend DAIs enabled for Audio Port [ 10.147834] Audio Port: ASoC: no backend DAIs enabled for Audio Port [ 10.159472] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 10.162179] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 10.163874] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 10.164488] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 10.165994] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 10.166626] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 10.168438] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 10.169549] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 10.171607] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 10.189856] intel_sst_acpi 808622A8:00: Alloc for str 1 pipe 0x90 [ 10.204244] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 10.205026] intel_sst_acpi 808622A8:00: Free for str 1 pipe 0x90 [ 10.215195] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 12.182265] intel_sst_acpi 808622A8:00: Alloc for str 1 pipe 0x90 [ 13.181361] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x2 [ 13.181374] intel_sst_acpi 808622A8:00: fw returned err -16 [ 14.181735] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 14.181764] intel_sst_acpi 808622A8:00: fw returned err -16 [ 15.181611] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 15.181641] intel_sst_acpi 808622A8:00: fw returned err -16 [ 16.181346] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 16.181376] intel_sst_acpi 808622A8:00: fw returned err -16 [ 16.210605] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 17.209115] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 17.209144] intel_sst_acpi 808622A8:00: fw returned err -16 [ 17.209183] intel_sst_acpi 808622A8:00: free stream returned err -19 [ 18.262035] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 18.262053] intel_sst_acpi 808622A8:00: fw returned err -16 [ 19.260719] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 19.260749] intel_sst_acpi 808622A8:00: fw returned err -16 [ 19.313903] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 19.445415] intel_sst_acpi 808622A8:00: Alloc for str 1 pipe 0x90 [ 19.445862] intel_sst_acpi 808622A8:00: FW sent error response 0x40034 [ 19.445883] intel_sst_acpi 808622A8:00: FW alloc failed ret -4 [ 19.445888] intel_sst_acpi 808622A8:00: sst_get_stream returned err -5 [ 19.445893] sst-mfld-platform sst-mfld-platform: ASoC: DAI prepare error: -5 [ 19.445898] Audio Port: ASoC: prepare FE Audio Port failed [ 20.444493] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 20.444522] intel_sst_acpi 808622A8:00: fw returned err -16 [ 21.444427] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 21.444456] intel_sst_acpi 808622A8:00: fw returned err -16 [ 22.444126] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 22.444155] intel_sst_acpi 808622A8:00: fw returned err -16 [ 23.443906] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 23.443934] intel_sst_acpi 808622A8:00: fw returned err -16 [ 23.474492] Audio Port: sst: error code = -22 [ 23.474504] snd_pcm_update_hw_ptr0: 123 callbacks suppressed [ 23.474512] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.474589] Audio Port: sst: error code = -22 [ 23.474596] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.474612] Audio Port: sst: error code = -22 [ 23.474617] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741085] Audio Port: sst: error code = -22 [ 23.741104] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741140] Audio Port: sst: error code = -22 [ 23.741147] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741206] Audio Port: sst: error code = -22 [ 23.741213] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741233] Audio Port: sst: error code = -22 [ 23.741240] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741350] Audio Port: sst: error code = -22 [ 23.741358] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741379] Audio Port: sst: error code = -22 [ 23.741385] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741427] Audio Port: sst: error code = -22 [ 23.741434] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 23.741455] Audio Port: sst: error code = -22 [ 23.785062] Audio Port: sst: error code = -22 [ 23.785108] Audio Port: sst: error code = -22 [ 23.785185] Audio Port: sst: error code = -22 [ 23.785210] Audio Port: sst: error code = -22 [ 23.785343] Audio Port: sst: error code = -22 [ 23.785367] Audio Port: sst: error code = -22 [ 23.785416] Audio Port: sst: error code = -22 [ 28.496573] snd_pcm_update_hw_ptr0: 13 callbacks suppressed [ 28.496582] cht-bsw-rt5672 cht-bsw-rt5672: BUG: , pos = -22, buffer size = 96000, period size = 48000 [ 28.496707] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 29.494259] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 29.494269] intel_sst_acpi 808622A8:00: fw returned err -16 [ 29.494284] intel_sst_acpi 808622A8:00: free stream returned err -19 [ 30.562054] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 30.562065] intel_sst_acpi 808622A8:00: fw returned err -16 [ 31.561892] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 31.561904] intel_sst_acpi 808622A8:00: fw returned err -16 [ 906.106300] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 906.249375] intel_sst_acpi 808622A8:00: Alloc for str 1 pipe 0x90 [ 907.248864] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x2 [ 907.248894] intel_sst_acpi 808622A8:00: fw returned err -16 [ 908.248393] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 908.248421] intel_sst_acpi 808622A8:00: fw returned err -16 [ 909.248611] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 909.248641] intel_sst_acpi 808622A8:00: fw returned err -16 [ 910.248108] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 910.248137] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1053.563879] isofs_fill_super: bread failed, dev=sdb1, iso_blknum=16, block=32 [ 1185.717932] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [ 1186.716247] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 1186.716277] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1186.716315] intel_sst_acpi 808622A8:00: free stream returned err -19 [ 1187.783992] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 1187.784021] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1188.783551] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 1188.783584] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1188.821911] rt5670 i2c-10EC5670:00: Sysclk is 0Hz and clock id is 2 [ 1207.389279] sst-mfld-platform sst-mfld-platform: Enter: enable=1 port_name=ssp2-port [ 1207.404620] rt5670 i2c-10EC5670:00: Sysclk is 24576000Hz and clock id is 1 [ 1207.404646] rt5670 i2c-10EC5670:00: bclk is 1536000Hz and lrck is 48000Hz [ 1207.404660] rt5670 i2c-10EC5670:00: bclk_ms is 0 and pre_div is 1 for iis 1 [ 1207.533606] intel_sst_acpi 808622A8:00: Alloc for str 1 pipe 0x90 [ 1208.535662] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x2 [ 1208.535691] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1209.535853] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [ 1209.535883] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1210.535333] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 1210.535361] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1211.535576] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [ 1211.535606] intel_sst_acpi 808622A8:00: fw returned err -16 [ 1286.976450] usb 1-4.1: USB disconnect, device number 8 [11996.101738] r8169 0000:01:00.0 eth0: link up [11996.101780] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [12019.249846] [drm:intel_pipe_update_end [i915_bpo]] *ERROR* Atomic update failure on pipe A (start=93814 end=93815) [12157.754218] [drm:intel_pipe_update_end [i915_bpo]] *ERROR* Atomic update failure on pipe A (start=102079 end=102080) [12194.085543] [drm:intel_pipe_update_end [i915_bpo]] *ERROR* Atomic update failure on pipe A (start=104247 end=104248) [13567.332608] sst-mfld-platform sst-mfld-platform: Enter: enable=0 port_name=ssp2-port [13568.332857] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x2 fw_state 0x3 [13568.332886] intel_sst_acpi 808622A8:00: fw returned err -16 [13568.332924] intel_sst_acpi 808622A8:00: free stream returned err -19 [13569.400219] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [13569.400247] intel_sst_acpi 808622A8:00: fw returned err -16 [13570.399826] intel_sst_acpi 808622A8:00: Wait timed-out condition:0x0, msg_id:0x1 fw_state 0x3 [13570.399837] intel_sst_acpi 808622A8:00: fw returned err -16 [13570.437188] rt5670 i2c-10EC5670:00: Sysclk is 0Hz and clock id is 2 >From /sys/kernel/debug/asoc/cherrytrailcraudio/, some necessary widgets are all power on, from media1_in to ssp2 Tx end with Headphone. I really don't know how to fix the sst fw error, any anyone give a look at this issue? ................ Thanks Tu __________ Information from ESET Smart Security, version of virus signature database 4468 (20090929) __________ The message was checked by ESET Smart Security. http://www.eset.com

3 7

[alsa-devel] [PATCH v3] ASoC: cs53l30: Add support for Cirrus Logic CS53L30
by me＠mx0a-001ae601.pphosted.com 14 Dec '15

14 Dec '15

From: Tim Howe <tim.howe(a)cirrus.com> Signed-off-by: Tim Howe <tim.howe(a)cirrus.com> --- .../devicetree/bindings/sound/cs53l30.txt | 21 + sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs53l30.c | 933 +++++++++++++++++++++ sound/soc/codecs/cs53l30.h | 272 ++++++ 5 files changed, 1233 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cs53l30.txt create mode 100644 sound/soc/codecs/cs53l30.c create mode 100644 sound/soc/codecs/cs53l30.h diff --git a/Documentation/devicetree/bindings/sound/cs53l30.txt b/Documentation/devicetree/bindings/sound/cs53l30.txt new file mode 100644 index 0000000..a2dff95 +++ b/Documentation/devicetree/bindings/sound/cs53l30.txt @@ -0,0 +1,21 @@ +CS53L30 audio CODEC + +Required properties: + + - compatible : "cirrus,cs53l30" + + - reg : the I2C address of the device + +Optional properties: + + - reset-gpios : a GPIO spec for the reset pin. + + +Example: + +codec: cs53l30@48 { + compatible = "cirrus,cs53l30"; + reg = <0x48>; + reset-gpios = <&gpio 54 0>; +}; + diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index b3317da..f59aa4b 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -59,6 +59,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_CS4271_SPI if SPI_MASTER select SND_SOC_CS42XX8_I2C if I2C select SND_SOC_CS4349 if I2C + select SND_SOC_CS53L30 if I2C select SND_SOC_CX20442 if TTY select SND_SOC_DA7210 if SND_SOC_I2C_AND_SPI select SND_SOC_DA7213 if I2C @@ -444,6 +445,10 @@ config SND_SOC_CS4349 tristate "Cirrus Logic CS4349 CODEC" depends on I2C +config SND_SOC_CS53L30 + tristate "Cirrus Logic CS53L30 CODEC" + depends on I2C + config SND_SOC_CX20442 tristate depends on TTY diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index cdadb9b..4f1ab1d 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -51,6 +51,7 @@ snd-soc-cs4271-spi-objs := cs4271-spi.o snd-soc-cs42xx8-objs := cs42xx8.o snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o snd-soc-cs4349-objs := cs4349.o +snd-soc-cs53l30-objs := cs53l30.o snd-soc-cx20442-objs := cx20442.o snd-soc-da7210-objs := da7210.o snd-soc-da7213-objs := da7213.o @@ -250,6 +251,7 @@ obj-$(CONFIG_SND_SOC_CS4271_SPI) += snd-soc-cs4271-spi.o obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o +obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o diff --git a/sound/soc/codecs/cs53l30.c b/sound/soc/codecs/cs53l30.c new file mode 100644 index 0000000..3d5cac9 +++ b/sound/soc/codecs/cs53l30.c @@ -0,0 +1,933 @@ +/* + * cs53l30.c -- CS53l30 ALSA Soc Audio driver + * + * Copyright 2015 Cirrus Logic, Inc. + * + * Authors: Paul Handrigan <Paul.Handrigan(a)cirrus.com>, + * Tim Howe <Tim.Howe(a)cirrus.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/gpio/consumer.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include "cs53l30.h" + +struct cs53l30_private { + struct regmap *regmap; + struct gpio_desc *reset_gpio; + u8 asp_config_ctl; + u32 mclk; +}; + +static const struct reg_default cs53l30_reg_defaults[] = { + { CS53L30_PWRCTL, THMS_PDN }, + { CS53L30_MCLKCTL, MCLK_DIV_DFLT }, + { CS53L30_INT_SR_CTL, INTERNAL_FS_DFLT }, + { CS53L30_MICBIAS_CTL, MIC_BIAS_DFLT }, + { CS53L30_ASPCFG_CTL, ASP_RATE_48K }, + { CS53L30_ASP1_CTL, ASP1_TDM_PDN }, + { CS53L30_ASP1_TDMTX_CTL1, ASP1_CHX_TX_DFLT_SLT47 }, + { CS53L30_ASP1_TDMTX_CTL2, ASP1_CHX_TX_DFLT_SLT47 }, + { CS53L30_ASP1_TDMTX_CTL3, ASP1_CHX_TX_DFLT_SLT47 }, + { CS53L30_ASP1_TDMTX_CTL4, ASP1_CHX_TX_DFLT_SLT47 }, + { CS53L30_ASP1_TDMTX_EN1, ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN2, ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN3, ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN4, ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN5, ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN6, ASP_TX_DISABLED }, + { CS53L30_ASP2_CTL, ASP2_CTRL_DFLT }, + { CS53L30_SFT_RAMP, SFT_RMP_DFLT }, + { CS53L30_LRCLK_CTL1, LRCK_CTLX_DFLT }, + { CS53L30_LRCLK_CTL2, LRCK_CTLX_DFLT }, + { CS53L30_MUTEP_CTL1, MUTEP_CTRL1_DFLT }, + { CS53L30_MUTEP_CTL2, MUTE_PDN_ULP }, + { CS53L30_INBIAS_CTL1, INBIAS_CTLX_DFLT }, + { CS53L30_INBIAS_CTL2, INBIAS_CTLX_DFLT }, + { CS53L30_DMIC1_STR_CTL, DMIC1_STEREO_DFLT }, + { CS53L30_DMIC2_STR_CTL, DMIC2_STEREO_DFLT }, + { CS53L30_ADCDMIC1_CTL1, ADC1_ON_CH_AB_IN }, + { CS53L30_ADCDMIC1_CTL2, ADC1_DMIC1_CTL2_DFLT }, + { CS53L30_ADC1_CTL3, ADC1_HPF_EN }, + { CS53L30_ADC1_NG_CTL, ADCX_ZERO_DFLT }, + { CS53L30_ADC1A_AFE_CTL, ADCX_ZERO_DFLT }, + { CS53L30_ADC1B_AFE_CTL, ADCX_ZERO_DFLT }, + { CS53L30_ADC1A_DIG_VOL, ADCX_ZERO_DFLT }, + { CS53L30_ADC1B_DIG_VOL, ADCX_ZERO_DFLT }, + { CS53L30_ADCDMIC2_CTL1, ADC2_ON_CH_AB_IN }, + { CS53L30_ADCDMIC2_CTL2, ADCX_ZERO_DFLT }, + { CS53L30_ADC2_CTL3, ADC2_HPF_EN }, + { CS53L30_ADC2_NG_CTL, ADCX_ZERO_DFLT }, + { CS53L30_ADC2A_AFE_CTL, ADCX_ZERO_DFLT }, + { CS53L30_ADC2B_AFE_CTL, ADCX_ZERO_DFLT }, + { CS53L30_ADC2A_DIG_VOL, ADCX_ZERO_DFLT }, + { CS53L30_ADC2B_DIG_VOL, ADCX_ZERO_DFLT }, + { CS53L30_INT_MASK, DEVICE_INT_MASK }, +}; + +static bool cs53l30_volatile_register(struct device *dev, unsigned int reg) +{ + if (reg == CS53L30_IS) + return true; + else + return false; +} + +static bool cs53l30_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS53L30_DEVID_AB: + case CS53L30_DEVID_CD: + case CS53L30_DEVID_E: + case CS53L30_REVID: + case CS53L30_PWRCTL: + case CS53L30_MCLKCTL: + case CS53L30_INT_SR_CTL: + case CS53L30_MICBIAS_CTL: + case CS53L30_ASPCFG_CTL: + case CS53L30_ASP1_CTL: + case CS53L30_ASP1_TDMTX_CTL1: + case CS53L30_ASP1_TDMTX_CTL2: + case CS53L30_ASP1_TDMTX_CTL3: + case CS53L30_ASP1_TDMTX_CTL4: + case CS53L30_ASP1_TDMTX_EN1: + case CS53L30_ASP1_TDMTX_EN2: + case CS53L30_ASP1_TDMTX_EN3: + case CS53L30_ASP1_TDMTX_EN4: + case CS53L30_ASP1_TDMTX_EN5: + case CS53L30_ASP1_TDMTX_EN6: + case CS53L30_ASP2_CTL: + case CS53L30_SFT_RAMP: + case CS53L30_LRCLK_CTL1: + case CS53L30_LRCLK_CTL2: + case CS53L30_MUTEP_CTL1: + case CS53L30_MUTEP_CTL2: + case CS53L30_INBIAS_CTL1: + case CS53L30_INBIAS_CTL2: + case CS53L30_DMIC1_STR_CTL: + case CS53L30_DMIC2_STR_CTL: + case CS53L30_ADCDMIC1_CTL1: + case CS53L30_ADCDMIC1_CTL2: + case CS53L30_ADC1_CTL3: + case CS53L30_ADC1_NG_CTL: + case CS53L30_ADC1A_AFE_CTL: + case CS53L30_ADC1B_AFE_CTL: + case CS53L30_ADC1A_DIG_VOL: + case CS53L30_ADC1B_DIG_VOL: + case CS53L30_ADCDMIC2_CTL1: + case CS53L30_ADCDMIC2_CTL2: + case CS53L30_ADC2_CTL3: + case CS53L30_ADC2_NG_CTL: + case CS53L30_ADC2A_AFE_CTL: + case CS53L30_ADC2B_AFE_CTL: + case CS53L30_ADC2A_DIG_VOL: + case CS53L30_ADC2B_DIG_VOL: + case CS53L30_INT_MASK: + return true; + default: + return false; + } +} + +static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2000, 0); +static DECLARE_TLV_DB_SCALE(adc_ng_boost_tlv, 0, 3000, 0); +static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0); + +static DECLARE_TLV_DB_SCALE(dig_tlv, -9600, 100, 1); + +static const char * const input1_sel_text[] = { "DMIC1 On AB In", + "DMIC1 On A In", "DMIC1 On B In", "ADC1 On AB In", "ADC1 On A In", + "ADC1 On B In", "DMIC1 Off ADC1 Off", }; + +unsigned int const input1_sel_values[] = { DMIC1_ON_CH_AB_IN, DMIC1_ON_CH_A_IN, + DMIC1_ON_CH_B_IN, ADC1_ON_CH_AB_IN, ADC1_ON_CH_A_IN, ADC1_ON_CH_B_IN, + DMIC1_OFF_ADC1_OFF, }; + +static const char * const input2_sel_text[] = { "DMIC2 On AB In", + "DMIC2 On A In", "DMIC2 On B In", "ADC2 On AB In", "ADC2 On A In", + "ADC2 On B In", "DMIC2 Off ADC2 Off", }; + +unsigned int const input2_sel_values[] = { DMIC2_ON_CH_AB_IN, DMIC2_ON_CH_A_IN, + DMIC2_ON_CH_B_IN, ADC2_ON_CH_AB_IN, ADC2_ON_CH_A_IN, ADC2_ON_CH_B_IN, + DMIC2_OFF_ADC2_OFF, }; + +static const char * const input1_route_sel_text[] = { "ADC1_SEL", + "DMIC1_SEL" }; + +static const struct soc_enum input1_route_sel_enum = + SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0, + ARRAY_SIZE(input1_route_sel_text), input1_route_sel_text); + +static SOC_VALUE_ENUM_SINGLE_DECL(input1_sel_enum, CS53L30_ADCDMIC1_CTL1, 0, + ADC1_DMIC1_PDN_MASK, input1_sel_text, input1_sel_values); + +static const struct snd_kcontrol_new input1_route_sel_mux = + SOC_DAPM_ENUM("Input 1 Route", input1_route_sel_enum); + +static const char * const input2_route_sel_text[] = { "ADC2_SEL", + "DMIC2_SEL" }; + +/* Note: CS53L30_ADCDMIC1_CTL1 CH_TYPE controls inputs 1 and 2 */ +static const struct soc_enum input2_route_sel_enum = + SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0, + ARRAY_SIZE(input2_route_sel_text), input2_route_sel_text); + +static SOC_VALUE_ENUM_SINGLE_DECL(input2_sel_enum, CS53L30_ADCDMIC2_CTL1, 0, + ADC1_DMIC1_PDN_MASK, input2_sel_text, input2_sel_values); + +static const struct snd_kcontrol_new input2_route_sel_mux = + SOC_DAPM_ENUM("Input 2 Route", input2_route_sel_enum); + +/* + * TB = 6144*(MCLK(int) scaling factor)/MCLK(internal) + * TB - Time base + * NOTE: If MCLK_INT_SCALE = 0, then TB=1 + */ +static const char * const cs53l30_ng_delay_text[] = { + "TB*50ms", "TB*100ms", "TB*150ms", "TB*200ms" }; + +static const struct soc_enum adc1_ng_delay_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, 0, + ARRAY_SIZE(cs53l30_ng_delay_text), cs53l30_ng_delay_text); + +static const struct soc_enum adc2_ng_delay_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, 0, + ARRAY_SIZE(cs53l30_ng_delay_text), cs53l30_ng_delay_text); + +/* The noise gate threshold selected will depend on NG Boost */ +static const char * const cs53l30_ng_thres_text[] = { + "-64dB/-34dB", "-66dB/-36dB", "-70dB/-40dB", "-73dB/-43dB", + "-76dB/-46dB", "-82dB/-52dB", "-58dB", "-64dB"}; + +static const struct soc_enum adc1_ng_thres_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, 2, + ARRAY_SIZE(cs53l30_ng_thres_text), cs53l30_ng_thres_text); + +static const struct soc_enum adc2_ng_thres_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, 2, + ARRAY_SIZE(cs53l30_ng_thres_text), cs53l30_ng_thres_text); + +/* ADC Preamp gain select */ +static const char * const cs53l30_preamp_gain_sel_text[] = { + "0dB", "10dB", "20dB"}; + +static const struct soc_enum adc1a_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1A_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +static const struct soc_enum adc1b_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1B_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +static const struct soc_enum adc2a_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2A_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +static const struct soc_enum adc2b_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2B_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +/* Set MIC Bias Voltage Control */ +static const char * const cs53l30_micbias_text[] = { + "HiZ", "1.8V", "2.75V"}; + +static const struct soc_enum micbias_enum = + SOC_ENUM_SINGLE(CS53L30_MICBIAS_CTL, 0, + ARRAY_SIZE(cs53l30_micbias_text), + cs53l30_micbias_text); + +/* Corner frequencies are with an Fs of 48kHz. */ +static const char * const hpf_corner_freq_text[] = { + "1.86Hz", "120Hz", "235Hz", "466Hz"}; + +static const struct soc_enum adc1_hpf_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1_CTL3, 1, + ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text); + +static const struct soc_enum adc2_hpf_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2_CTL3, 1, + ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text); + +static const struct snd_kcontrol_new cs53l30_snd_controls[] = { + SOC_SINGLE("Digital Soft-Ramp Switch", CS53L30_SFT_RAMP, 5, 1, 0), + SOC_SINGLE("ADC1 Noise Gate Ganging Switch", + CS53L30_ADC1_CTL3, 0, 1, 0), + SOC_SINGLE("ADC2 Noise Gate Ganging Switch", + CS53L30_ADC2_CTL3, 0, 1, 0), + SOC_SINGLE("ADC1A Noise Gate Enable Switch", + CS53L30_ADC1_NG_CTL, 6, 1, 0), + SOC_SINGLE("ADC1B Noise Gate Enable Switch", + CS53L30_ADC1_NG_CTL, 7, 1, 0), + SOC_SINGLE("ADC2A Noise Gate Enable Switch", + CS53L30_ADC2_NG_CTL, 6, 1, 0), + SOC_SINGLE("ADC2B Noise Gate Enable Switch", + CS53L30_ADC2_NG_CTL, 7, 1, 0), + SOC_SINGLE("ADC1 Notch Filter Switch", + CS53L30_ADCDMIC1_CTL2, 7, 1, 1), + SOC_SINGLE("ADC2 Notch Filter Switch", + CS53L30_ADCDMIC2_CTL2, 7, 1, 1), + SOC_SINGLE("ADC1A Invert Switch", + CS53L30_ADCDMIC1_CTL2, 4, 1, 0), + SOC_SINGLE("ADC1B Invert Switch", + CS53L30_ADCDMIC1_CTL2, 5, 1, 0), + SOC_SINGLE("ADC2A Invert Switch", + CS53L30_ADCDMIC2_CTL2, 4, 1, 0), + SOC_SINGLE("ADC2B Invert Switch", + CS53L30_ADCDMIC2_CTL2, 5, 1, 0), + + SOC_SINGLE_TLV("ADC1A Digital Boost Volume", + CS53L30_ADCDMIC1_CTL2, 0, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC1B Digital Boost Volume", + CS53L30_ADCDMIC1_CTL2, 1, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC2A Digital Boost Volume", + CS53L30_ADCDMIC2_CTL2, 0, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC2B Digital Boost Volume", + CS53L30_ADCDMIC2_CTL2, 1, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC1 NG Boost Volume", + CS53L30_ADC1_NG_CTL, 5, 1, 0, adc_ng_boost_tlv), + SOC_SINGLE_TLV("ADC2 NG Boost Volume", + CS53L30_ADC2_NG_CTL, 5, 1, 0, adc_ng_boost_tlv), + + SOC_ENUM("Input 1 Channel Select", input1_sel_enum), + SOC_ENUM("Input 2 Channel Select", input2_sel_enum), + + SOC_ENUM("ADC1 HPF Select", adc1_hpf_enum), + SOC_ENUM("ADC2 HPF Select", adc2_hpf_enum), + SOC_ENUM("ADC1 NG Threshold", adc1_ng_thres_enum), + SOC_ENUM("ADC2 NG Threshold", adc2_ng_thres_enum), + SOC_ENUM("ADC1 NG Delay", adc1_ng_delay_enum), + SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum), + SOC_ENUM("ADC1A Pre Amp Gain", adc1a_preamp_gain_enum), + SOC_ENUM("ADC1B Pre Amp Gain", adc1b_preamp_gain_enum), + SOC_ENUM("ADC2A Pre Amp Gain", adc2a_preamp_gain_enum), + SOC_ENUM("ADC2B Pre Amp Gain", adc2b_preamp_gain_enum), + SOC_ENUM("Mic Bias Voltage Select", micbias_enum), + + SOC_SINGLE_SX_TLV("ADC1A PGA Volume", + CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + SOC_SINGLE_SX_TLV("ADC1B PGA Volume", + CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + SOC_SINGLE_SX_TLV("ADC2A PGA Volume", + CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + SOC_SINGLE_SX_TLV("ADC2B PGA Volume", + CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + + SOC_SINGLE_SX_TLV("ADC1A Digital Volume", + CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), + SOC_SINGLE_SX_TLV("ADC1B Digital Volume", + CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), + SOC_SINGLE_SX_TLV("ADC2A Digital Volume", + CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), + SOC_SINGLE_SX_TLV("ADC2B Digital Volume", + CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), +}; + +static int cs53l30_asp_sdout_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + regmap_update_bits(priv->regmap, CS53L30_ASP1_CTL, + ASP1_3ST, 0); + break; + case SND_SOC_DAPM_POST_PMD: + regmap_update_bits(priv->regmap, CS53L30_ASP1_CTL, + ASP1_3ST, 1); + break; + default: + pr_err("Invalid event = 0x%x\n", event); + return -EINVAL; + } + + return 0; +} + +static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("IN1_DMIC1"), + SND_SOC_DAPM_INPUT("IN2"), + SND_SOC_DAPM_INPUT("IN3_DMIC2"), + SND_SOC_DAPM_INPUT("IN4"), + SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS53L30_MICBIAS_CTL, 4, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS53L30_MICBIAS_CTL, 5, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIC3 Bias", CS53L30_MICBIAS_CTL, 6, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIC4 Bias", CS53L30_MICBIAS_CTL, 7, 1, NULL, 0), + + SND_SOC_DAPM_AIF_OUT_E("ASP_SDOUT1", NULL, 0, + CS53L30_ASP1_CTL, ASP1_SDOUT_PDN, + 1, cs53l30_asp_sdout_event, + (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)), + SND_SOC_DAPM_AIF_OUT_E("ASP_SDOUT2", NULL, 0, + CS53L30_ASP2_CTL, ASP2_SDOUT_PDN, + 1, cs53l30_asp_sdout_event, + (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)), + + SND_SOC_DAPM_MUX("Input Mux 1", SND_SOC_NOPM, 0, 0, + &input1_route_sel_mux), + SND_SOC_DAPM_MUX("Input Mux 2", SND_SOC_NOPM, 0, 0, + &input2_route_sel_mux), + + SND_SOC_DAPM_ADC("ADC1A", NULL, CS53L30_ADCDMIC1_CTL1, 6, 1), + SND_SOC_DAPM_ADC("ADC1B", NULL, CS53L30_ADCDMIC1_CTL1, 7, 1), + SND_SOC_DAPM_ADC("ADC2A", NULL, CS53L30_ADCDMIC2_CTL1, 6, 1), + SND_SOC_DAPM_ADC("ADC2B", NULL, CS53L30_ADCDMIC2_CTL1, 7, 1), + SND_SOC_DAPM_ADC("DMIC1", NULL, CS53L30_ADCDMIC1_CTL1, 2, 1), + SND_SOC_DAPM_ADC("DMIC2", NULL, CS53L30_ADCDMIC2_CTL1, 2, 1), +}; + +static const struct snd_soc_dapm_route cs53l30_audio_map[] = { + + /* ADC Input Paths */ + {"ADC1A", NULL, "IN1_DMIC1"}, + {"Input Mux 1", "ADC1_SEL", "ADC1A"}, + {"ADC1B", NULL, "IN2"}, + + {"ADC2A", NULL, "IN3_DMIC2"}, + {"Input Mux 2", "ADC2_SEL", "ADC2A"}, + {"ADC2B", NULL, "IN4"}, + + /* MIC Bias Paths */ + {"ADC1A", NULL, "MIC1 Bias"}, + {"ADC1B", NULL, "MIC2 Bias"}, + {"ADC2A", NULL, "MIC3 Bias"}, + {"ADC2B", NULL, "MIC4 Bias"}, + + /* DMIC Paths */ + {"DMIC1", NULL, "IN1_DMIC1"}, + {"Input Mux 1", "DMIC1_SEL", "DMIC1"}, + + {"DMIC2", NULL, "IN3_DMIC2"}, + {"Input Mux 2", "DMIC2_SEL", "DMIC2"}, + + /* Output Paths */ + {"ASP_SDOUT1", NULL, "ADC1A" }, + {"ASP_SDOUT1", NULL, "Input Mux 1"}, + {"ASP_SDOUT1", NULL, "ADC1B"}, + + {"ASP_SDOUT2", NULL, "ADC2A"}, + {"ASP_SDOUT2", NULL, "Input Mux 2"}, + {"ASP_SDOUT2", NULL, "ADC2B"}, + + {"ASP1 Capture", NULL, "ASP_SDOUT1"}, + {"ASP2 Capture", NULL, "ASP_SDOUT2"}, +}; + +struct cs53l30_mclk_div { + u32 mclk; + u32 srate; + u8 asp_rate; + u8 internal_fs_ratio; + u8 mclk_int_scale; +}; + +static struct cs53l30_mclk_div cs53l30_mclk_coeffs[] = { + /* NOTE: Enable MCLK_INT_SCALE to save power. */ + + /* MCLK, Sample Rate, asp_rate, internal_fs_ratio, mclk_int_scale */ + {5644800, 11025, 0x4, 1, 1}, + {5644800, 22050, 0x8, 1, 1}, + {5644800, 44100, 0xC, 1, 1}, + + {6000000, 8000, 0x1, 0, 1}, + {6000000, 11025, 0x2, 0, 1}, + {6000000, 12000, 0x4, 0, 1}, + {6000000, 16000, 0x5, 0, 1}, + {6000000, 22050, 0x6, 0, 1}, + {6000000, 24000, 0x8, 0, 1}, + {6000000, 32000, 0x9, 0, 1}, + {6000000, 44100, 0xA, 0, 1}, + {6000000, 48000, 0xC, 0, 1}, + + {6144000, 8000, 0x1, 1, 1}, + {6144000, 11025, 0x2, 1, 1}, + {6144000, 12000, 0x4, 1, 1}, + {6144000, 16000, 0x5, 1, 1}, + {6144000, 22050, 0x6, 1, 1}, + {6144000, 24000, 0x8, 1, 1}, + {6144000, 32000, 0x9, 1, 1}, + {6144000, 44100, 0xA, 1, 1}, + {6144000, 48000, 0xC, 1, 1}, + + {6400000, 8000, 0x1, 1, 1}, + {6400000, 11025, 0x2, 1, 1}, + {6400000, 12000, 0x4, 1, 1}, + {6400000, 16000, 0x5, 1, 1}, + {6400000, 22050, 0x6, 1, 1}, + {6400000, 24000, 0x8, 1, 1}, + {6400000, 32000, 0x9, 1, 1}, + {6400000, 44100, 0xA, 1, 1}, + {6400000, 48000, 0xC, 1, 1}, +}; + +struct cs53l30_mclkx_div { + u32 mclkx; + u8 ratio; + u8 mclkdiv; +}; + +static struct cs53l30_mclkx_div cs53l30_mclkx_coeffs[] = { + {5644800, 1, 0}, + {6000000, 1, 0}, + {6144000, 1, 0}, + {11289600, 2, 1}, + {12288000, 2, 1}, + {12000000, 2, 1}, + {19200000, 3, 2}, +}; + +static int cs53l30_get_mclkx_coeff(int mclkx) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs53l30_mclkx_coeffs); i++) { + if (cs53l30_mclkx_coeffs[i].mclkx == mclkx) + return i; + } + return -EINVAL; +} + +static int cs53l30_get_mclk_coeff(int mclk, int srate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs53l30_mclk_coeffs); i++) { + if (cs53l30_mclk_coeffs[i].mclk == mclk && + cs53l30_mclk_coeffs[i].srate == srate) + return i; + } + return -EINVAL; + +} + +static int cs53l30_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + + int mclkx_coeff; + u32 mclk; + unsigned int mclk_ctl; + + /* MCLKX -> MCLK */ + mclkx_coeff = cs53l30_get_mclkx_coeff(freq); + if (mclkx_coeff < 0) + return mclkx_coeff; + + mclk = cs53l30_mclkx_coeffs[mclkx_coeff].mclkx / + cs53l30_mclkx_coeffs[mclkx_coeff].ratio; + + regmap_read(priv->regmap, CS53L30_MCLKCTL, &mclk_ctl); + mclk_ctl &= ~MCLK_DIV; + mclk_ctl |= cs53l30_mclkx_coeffs[mclkx_coeff].mclkdiv; + + regmap_write(priv->regmap, CS53L30_MCLKCTL, mclk_ctl); + priv->mclk = mclk; + return 0; +} + +static int cs53l30_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + unsigned int asp_config_ctl; + + regmap_read(priv->regmap, CS53L30_ASPCFG_CTL, &asp_config_ctl); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + asp_config_ctl |= ASP_MS; + break; + + case SND_SOC_DAIFMT_CBS_CFS: + asp_config_ctl &= ~ASP_MS; + break; + + default: + return -EINVAL; + } + + /* Check to see if the SCLK is inverted */ + if (fmt & (SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_IB_IF)) + asp_config_ctl |= ASP_SCLK_INV; + else + asp_config_ctl &= ~ASP_SCLK_INV; + + priv->asp_config_ctl = asp_config_ctl; + return 0; +} + +static int cs53l30_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + int mclk_coeff; + int srate = params_rate(params); + unsigned int int_sr_ctl, mclk_ctl; + + /* MCLK -> srate */ + mclk_coeff = + cs53l30_get_mclk_coeff(priv->mclk, srate); + if (mclk_coeff < 0) + return -EINVAL; + + regmap_write(priv->regmap, CS53L30_ASPCFG_CTL, priv->asp_config_ctl); + regmap_read(priv->regmap, CS53L30_INT_SR_CTL, &int_sr_ctl); + if (cs53l30_mclk_coeffs[mclk_coeff].internal_fs_ratio) + int_sr_ctl |= INTERNAL_FS_RATIO; + else + int_sr_ctl &= ~INTERNAL_FS_RATIO; + regmap_write(priv->regmap, CS53L30_INT_SR_CTL, int_sr_ctl); + + regmap_read(priv->regmap, CS53L30_MCLKCTL, &mclk_ctl); + if (cs53l30_mclk_coeffs[mclk_coeff].mclk_int_scale) + mclk_ctl |= MCLK_INT_SCALE; + else + mclk_ctl &= ~MCLK_INT_SCALE; + + regmap_write(priv->regmap, CS53L30_MCLKCTL, mclk_ctl); + priv->asp_config_ctl &= ASP_CNFG_MASK; + priv->asp_config_ctl |= (cs53l30_mclk_coeffs[mclk_coeff].asp_rate + & ASP_RATE); + regmap_write(priv->regmap, CS53L30_MCLKCTL, priv->asp_config_ctl); + + return 0; +} + +static int cs53l30_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + unsigned int reg; + int i, inter_max_check; + + switch (level) { + case SND_SOC_BIAS_ON: + break; + case SND_SOC_BIAS_PREPARE: + if (dapm->bias_level == SND_SOC_BIAS_STANDBY) + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + PDN_LP, 0); + break; + case SND_SOC_BIAS_STANDBY: + if (dapm->bias_level == SND_SOC_BIAS_OFF) { + regmap_update_bits(priv->regmap, CS53L30_MCLKCTL, + MCLK_DIS, 0); + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + PDN_ULP, 0); + msleep(50); + } else { + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + PDN_LP, PDN_LP); + } + break; + + case SND_SOC_BIAS_OFF: + regmap_update_bits(priv->regmap, CS53L30_INT_MASK, + PDN_DONE, 0); + /* If digital softramp is set, the amount of time required + * for power down increases and depends on the digital + * volume setting. + */ + + /* Set the max possible time if digsft is set */ + regmap_read(priv->regmap, CS53L30_SFT_RAMP, &reg); + if (reg & DIGSFT) + inter_max_check = PDN_POLL_MAX; + else + inter_max_check = 10; + + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + PDN_ULP, PDN_ULP); + msleep(20); /* PDN_DONE will take a min of 20ms to be set.*/ + regmap_read(priv->regmap, CS53L30_IS, &reg); /* Clr status */ + for (i = 0; i < inter_max_check; i++) { + usleep_range(1000, 1000); + msleep(1); + regmap_read(priv->regmap, CS53L30_IS, &reg); + if (reg & PDN_DONE) + break; + } + /* PDN_DONE is set. We now can disable the MCLK */ + regmap_update_bits(priv->regmap, CS53L30_INT_MASK, + PDN_DONE, PDN_DONE); + regmap_update_bits(priv->regmap, CS53L30_MCLKCTL, + MCLK_DIS, MCLK_DIS); + break; + } + dapm->bias_level = level; + + return 0; +} + +static int cs53l30_set_tristate(struct snd_soc_dai *dai, int tristate) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + + return regmap_update_bits(priv->regmap, CS53L30_ASP1_CTL, ASP1_3ST, + (ASP1_3ST_VAL(tristate) & ASP1_3ST)); +} + +unsigned int const cs53l30_src_rates[] = { + 8000, 11025, 12000, 16000, 22050, + 24000, 32000, 44100, 48000 +}; + +static struct snd_pcm_hw_constraint_list src_constraints = { + .count = ARRAY_SIZE(cs53l30_src_rates), + .list = cs53l30_src_rates, +}; + +static int cs53l30_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &src_constraints); + + return 0; +} + +/* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */ +#define CS53L30_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT) + +#define CS53L30_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +static const struct snd_soc_dai_ops cs53l30_ops = { + .startup = cs53l30_pcm_startup, + .hw_params = cs53l30_pcm_hw_params, + .set_fmt = cs53l30_set_dai_fmt, + .set_sysclk = cs53l30_set_sysclk, + .set_tristate = cs53l30_set_tristate, +}; + +static struct snd_soc_dai_driver cs53l30_dai[] = { + { + .name = "cs53l30-asp1", + .id = CS53L30_ASP1, + .capture = { + .stream_name = "ASP1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CS53L30_RATES, + .formats = CS53L30_FORMATS, + }, + .ops = &cs53l30_ops, + .symmetric_rates = 1, + }, + { + .name = "cs53l30-asp2", + .id = CS53L30_ASP2, + .capture = { + .stream_name = "ASP2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CS53L30_RATES, + .formats = CS53L30_FORMATS, + }, + .ops = &cs53l30_ops, + .symmetric_rates = 1, + } +}; + +static struct snd_soc_codec_driver soc_codec_dev_cs53l30 = { + .set_bias_level = cs53l30_set_bias_level, + + .dapm_widgets = cs53l30_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs53l30_dapm_widgets), + .dapm_routes = cs53l30_audio_map, + .num_dapm_routes = ARRAY_SIZE(cs53l30_audio_map), + + .controls = cs53l30_snd_controls, + .num_controls = ARRAY_SIZE(cs53l30_snd_controls), +}; + +static struct regmap_config cs53l30_regmap = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = CS53L30_MAX_REGISTER, + .reg_defaults = cs53l30_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(cs53l30_reg_defaults), + .volatile_reg = cs53l30_volatile_register, + .readable_reg = cs53l30_readable_register, + .cache_type = REGCACHE_RBTREE, +}; + +static int cs53l30_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct cs53l30_private *cs53l30; + int ret = 0; + unsigned int devid = 0; + unsigned int reg; + + cs53l30 = devm_kzalloc(&client->dev, + sizeof(struct cs53l30_private), GFP_KERNEL); + if (!cs53l30) { + dev_err(&client->dev, "could not allocate codec\n"); + return -ENOMEM; + } + + /* Reset the Device */ + cs53l30->reset_gpio = devm_gpiod_get_optional(&client->dev, + "reset", GPIOD_OUT_LOW); + if (IS_ERR(cs53l30->reset_gpio)) + return PTR_ERR(cs53l30->reset_gpio); + + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 1); + + i2c_set_clientdata(client, cs53l30); + + cs53l30->mclk = 0; + + cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap); + if (IS_ERR(cs53l30->regmap)) { + ret = PTR_ERR(cs53l30->regmap); + dev_err(&client->dev, "regmap_init() failed: %d\n", ret); + return ret; + } + /* initialize codec */ + ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, &reg); + devid = reg << 12; + + ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, &reg); + devid |= reg << 4; + + ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, &reg); + devid |= (reg & 0xF0) >> 4; + + if (devid != CS53L30_DEVID) { + ret = -ENODEV; + dev_err(&client->dev, + "CS53L30 Device ID (%X). Expected %X\n", + devid, CS53L30_DEVID); + return ret; + } + + ret = regmap_read(cs53l30->regmap, CS53L30_REVID, &reg); + if (ret < 0) { + dev_err(&client->dev, "Get Revision ID failed\n"); + return ret; + } + + dev_info(&client->dev, + "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF); + + ret = snd_soc_register_codec(&client->dev, + &soc_codec_dev_cs53l30, cs53l30_dai, + ARRAY_SIZE(cs53l30_dai)); + return ret; +} + +static int cs53l30_i2c_remove(struct i2c_client *client) +{ + struct cs53l30_private *cs53l30 = i2c_get_clientdata(client); + + snd_soc_unregister_codec(&client->dev); + + /* Hold down reset */ + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 0); + + return 0; +} + +#ifdef CONFIG_PM +static int cs53l30_runtime_suspend(struct device *dev) +{ + struct cs53l30_private *cs53l30 = dev_get_drvdata(dev); + + regcache_cache_only(cs53l30->regmap, true); + + /* Hold down reset */ + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 0); + + return 0; +} + +static int cs53l30_runtime_resume(struct device *dev) +{ + struct cs53l30_private *cs53l30 = dev_get_drvdata(dev); + + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 1); + + regcache_cache_only(cs53l30->regmap, false); + regcache_sync(cs53l30->regmap); + + return 0; +} +#endif + +static const struct dev_pm_ops cs53l30_runtime_pm = { + SET_RUNTIME_PM_OPS(cs53l30_runtime_suspend, cs53l30_runtime_resume, + NULL) +}; + +static const struct of_device_id cs53l30_of_match[] = { + { .compatible = "cirrus,cs53l30", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, cs53l30_of_match); + +static const struct i2c_device_id cs53l30_id[] = { + {"cs53l30", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, cs53l30_id); + +static struct i2c_driver cs53l30_i2c_driver = { + .driver = { + .name = "cs53l30", + .owner = THIS_MODULE, + }, + .id_table = cs53l30_id, + .probe = cs53l30_i2c_probe, + .remove = cs53l30_i2c_remove, + +}; + +module_i2c_driver(cs53l30_i2c_driver); + +MODULE_DESCRIPTION("ASoC CS53L30 driver"); +MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan(a)cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/cs53l30.h b/sound/soc/codecs/cs53l30.h new file mode 100644 index 0000000..f45e91f +++ b/sound/soc/codecs/cs53l30.h @@ -0,0 +1,272 @@ +/* + * ALSA SoC CS53L30 codec driver + * + * Copyright 2015 Cirrus Logic, Inc. + * + * Author: Paul Handrigan <Paul.Handrigan(a)cirrus.com>, + * Tim Howe <Tim.Howe(a)cirrus.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __CS53L30_H__ +#define __CS53L30_H__ + +/* I2C Registers */ +#define CS53L30_DEVID_AB 0x01 /* Device ID A & B [RO]. */ +#define CS53L30_DEVID_CD 0x02 /* Device ID C & D [RO]. */ +#define CS53L30_DEVID_E 0x03 /* Device ID E [RO]. */ +#define CS53L30_REVID 0x05 /* Revision ID [RO]. */ +#define CS53L30_PWRCTL 0x06 /* Power Control. */ +#define CS53L30_MCLKCTL 0x07 /* MCLK Control. */ +#define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */ +#define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */ +#define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */ +#define CS53L30_ASP1_CTL 0x0D /* ASP1 Control. */ +#define CS53L30_ASP1_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */ +#define CS53L30_ASP1_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */ +#define CS53L30_ASP1_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */ +#define CS53L30_ASP1_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */ +#define CS53L30_ASP1_TDMTX_EN1 0x12 /* ASP1 TDM TX Enable 1 */ +#define CS53L30_ASP1_TDMTX_EN2 0x13 /* ASP1 TDM TX Enable 2 */ +#define CS53L30_ASP1_TDMTX_EN3 0x14 /* ASP1 TDM TX Enable 3 */ +#define CS53L30_ASP1_TDMTX_EN4 0x15 /* ASP1 TDM TX Enable 4 */ +#define CS53L30_ASP1_TDMTX_EN5 0x16 /* ASP1 TDM TX Enable 5 */ +#define CS53L30_ASP1_TDMTX_EN6 0x17 /* ASP1 TDM TX Enable 6 */ +#define CS53L30_ASP2_CTL 0x18 /* ASP2 Control. */ +#define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */ +#define CS53L30_LRCLK_CTL1 0x1B /* LRCLK Control 1. */ +#define CS53L30_LRCLK_CTL2 0x1C /* LRCLK Control 2. */ +#define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */ +#define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */ +#define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */ +#define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */ +#define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */ +#define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */ +#define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */ +#define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */ +#define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */ +#define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */ +#define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */ +#define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */ +#define CS53L30_ADC1A_DIG_VOL 0x2B /* ADC1A Digital Volume. */ +#define CS53L30_ADC1B_DIG_VOL 0x2C /* ADC1B Digital Volume. */ +#define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */ +#define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */ +#define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */ +#define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */ +#define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */ +#define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */ +#define CS53L30_ADC2A_DIG_VOL 0x33 /* ADC2A Digital Volume. */ +#define CS53L30_ADC2B_DIG_VOL 0x34 /* ADC2B Digital Volume. */ +#define CS53L30_INT_MASK 0x35 /* Interrupt Mask. */ +#define CS53L30_IS 0x36 /* Interrupt Status. */ +#define CS53L30_MAX_REGISTER 0x36 + +/* Device ID */ +#define CS53L30_DEVID 0x53A30 + +/* PDN_DONE Poll Maximum + * If soft ramp is set it will take much longer to power down + * the system. + */ +#define PDN_POLL_MAX 900 + +/* Bitfield Definitions */ + +/* CS53L30_PWRCTL */ +#define PDN_ULP (1 << 7) +#define PDN_LP (1 << 6) +#define DISCHARGE_FILT (1 << 5) +#define THMS_PDN (1 << 4) + +/* CS53L30_MCLKCTL */ +#define MCLK_DIS (1 << 7) +#define MCLK_INT_SCALE (1 << 6) +#define DMIC_DRIVE (1 << 5) +#define MCLK_DIV (3 << 2) +#define MCLK_DIV_DFLT (1 << 2) +#define SYNC_EN (1 << 1) + +/* CS53L30_INT_SR_CTL */ +#define INTERNAL_FS_RATIO (1 << 4) +#define INTERNAL_FS_DFLT (7 << 2) +#define MCLK_19MHZ_EN (1 << 0) + +/* CS53L30_MICBIAS_CTL */ +#define MIC4_BIAS_PDN (1 << 7) +#define MIC3_BIAS_PDN (1 << 6) +#define MIC2_BIAS_PDN (1 << 5) +#define MIC1_BIAS_PDN (1 << 4) +#define VP_MIN (1 << 2) +#define MIC_BIAS_CTRL (3 << 0) +#define MIC_BIAS_ALL_PDN 0xF0 +#define MIC_BIAS_DFLT (MIC_BIAS_ALL_PDN | VP_MIN) + +/* CS53L30_ASPCFG_CTL */ +#define ASP_MS (1 << 7) +#define ASP_SCLK_INV (1 << 4) +#define ASP_RATE_48K (3 << 2) +#define ASP_RATE 0x0F +#define ASP_CNFG_MASK 0xF0 + +/* CS53L30_ASP1_CTL */ +#define ASP1_TDM_PDN (1 << 7) +#define ASP1_SDOUT_PDN (1 << 6) +#define ASP1_3ST (1 << 5) +#define SHIFT_LEFT (1 << 4) +#define ASP1_DRIVE (1 << 0) +#define ASP1_3ST_VAL(x) ((x) << 5) + +/* CS53L30_ASP1_TDMTX_CTL */ +#define ASP1_CHX_TX_STATE (1 << 7) +#define ASP1_CHX_TX_LOC 0x3F +#define ASP1_CHX_TX_DFLT_SLT47 0x2F +#define ASP_TX_DISABLED 0x00 + +/* CS53L30_ASP2_CTL */ +#define ASP2_SDOUT_PDN (1 << 6) +#define ASP2_DRIVE (1 << 0) +#define ASP2_CTRL_DFLT 0x00 + +/* CS53L30_SFT_RAMP */ +#define DIGSFT (1 << 5) +#define SFT_RMP_DFLT 0x00 + +/* CS53L30_LRCLK_CTL2 */ +#define LRCK_50_NPW (1 << 3) +#define LRCK_TPWH (7 << 0) +#define LRCK_CTLX_DFLT 0x00 + +/* CS53L30_MUTEP_CTL */ +#define MUTE_PDN_ULP (1 << 7) +#define MUTE_PDN_LP (1 << 6) +#define MUTE_M4B_PDN (1 << 4) +#define MUTE_M3B_PDN (1 << 3) +#define MUTE_M2B_PDN (1 << 2) +#define MUTE_M1B_PDN (1 << 1) +#define MUTE_MB_ALL_PDN (1 << 0) +#define MUTEP_CTRL1_DFLT 0x00 + +/* CS53L30_MUTEP_CTL2 */ +#define MUTE_PIN_POLARITY (1 << 7) +#define MUTE_ASP_TDM_PDN (1 << 6) +#define MUTE_ASP_SDOUT2_PDN (1 << 5) +#define MUTE_ASP_SDOUT1_PDN (1 << 4) +#define MUTE_ADC2B_PDN (1 << 3) +#define MUTE_ADC2A_PDN (1 << 2) +#define MUTE_ADC1B_PDN (1 << 1) +#define MUTE_ADC1A_PDN (1 << 0) + +/* CS53L30_INBIAS_CTL1 */ +#define IN4M_BIAS (3 << 6) +#define IN4P_BIAS (3 << 4) +#define IN3M_BIAS (3 << 2) +#define IN3P_BIAS (3 << 0) + +/* CS53L30_INBIAS_CTL2 */ +#define IN2M_BIAS (3 << 6) +#define IN2P_BIAS (3 << 4) +#define IN1M_BIAS (3 << 2) +#define IN1P_BIAS (3 << 0) +#define INBIAS_CTLX_DFLT 0xAA + +/* CS53L30_DMIC1_STR_CTL */ +#define DMIC1_STEREO_ENB (1 << 5) +#define DMIC1_STEREO_DFLT 0xA8 + +/* CS53L30_DMIC2_STR_CTL */ +#define DMIC2_STEREO_EN (1 << 5) +#define DMIC2_STEREO_DFLT 0xEC + +/* CS53L30_ADCDMIC1_CTL1 */ +#define ADC1B_PDN (1 << 7) +#define ADC1A_PDN (1 << 6) +#define DMIC1_PDN (1 << 2) +#define DMIC1_SCLK_DIV (1 << 1) +#define CH_TYPE (1 << 0) +#define DMIC1_ON_CH_AB_IN (CH_TYPE) +#define DMIC1_ON_CH_A_IN (ADC1B_PDN | CH_TYPE) +#define DMIC1_ON_CH_B_IN (ADC1A_PDN | CH_TYPE) +#define ADC1_ON_CH_AB_IN (DMIC1_PDN) +#define ADC1_ON_CH_A_IN (ADC1B_PDN | DMIC1_PDN) +#define ADC1_ON_CH_B_IN (ADC1A_PDN | DMIC1_PDN) +#define DMIC1_OFF_ADC1_OFF (ADC1A_PDN | ADC1B_PDN | DMIC1_PDN) +#define ADC1_DMIC1_PDN_MASK 0xFF + +/* CS53L30_ADCDMIC1_CTL2 */ +#define ADC1_NOTCH_DIS (1 << 7) +#define ADC1B_INV (1 << 5) +#define ADC1A_INV (1 << 4) +#define ADC1B_DIG_BOOST (1 << 1) +#define ADC1A_DIG_BOOST (1 << 0) +#define ADC1_DMIC1_CTL2_DFLT 0x00 + +/* CS53L30_ADC1_CTL3 */ +#define ADC1_HPF_EN (1 << 3) +#define ADC1_HPF_CF (3 << 1) +#define ADC1_NG_ALL (1 << 0) + +/* CS53L30_ADC1_NG_CTL */ +#define ADC1B_NG (1 << 7) +#define ADC1A_NG (1 << 6) +#define ADC1_NG_BOOST (1 << 5) +#define ADC1_NG_THRESH (7 << 2) +#define ADC1_NG_DELAY (3 << 0) +#define ADCX_ZERO_DFLT 0x00 + +/* CS53L30_ADC1A_AFE_CTL */ +#define ADC1A_PREAMP (3 << 6) +#define ADC1A_PGA_VOL 0x3F + +/* CS53L30_ADC1B_AFE_CTL */ +#define ADC1B_PREAMP (3 << 6) +#define ADC1B_PGA_VOL 0x3F + +/* CS53L30_ADCXX_DIG_VOL */ +#define MUTE_DIG_OUT (1 << 7) + +/* CS53L30_ADCDMIC2_CTL1 */ +#define ADC2B_PDN (1 << 7) +#define ADC2A_PDN (1 << 6) +#define DMIC2_PDN (1 << 2) +#define DMIC2_CLKDIV (1 << 1) +#define DMIC2_ON_CH_AB_IN 0x00 /* CH_TYPE must = 1 */ +#define DMIC2_ON_CH_A_IN (ADC2B_PDN) /* CH_TYPE must = 1 */ +#define DMIC2_ON_CH_B_IN (ADC2A_PDN) /* CH_TYPE must = 1 */ +#define ADC2_ON_CH_AB_IN (DMIC2_PDN) /* CH_TYPE must = 0 */ +#define ADC2_ON_CH_A_IN (ADC2B_PDN | DMIC2_PDN) /* CH_TYPE must = 0 */ +#define ADC2_ON_CH_B_IN (ADC2A_PDN | DMIC2_PDN) /* CH_TYPE must = 0 */ +#define DMIC2_OFF_ADC2_OFF (ADC2A_PDN | ADC2B_PDN | DMIC2_PDN) + +/* CS53L30_ADCDMIC2_CTL2 */ +#define ADC2_NOTCH_DIS (1 << 7) +#define ADC2B_INV (1 << 5) +#define ADC2A_INV (1 << 4) +#define ADC2B_DIG_BOOST (1 << 1) +#define ADC2A_DIG_BOOST (1 << 0) + +/* CS53L30_ADC2_CTL3 */ +#define ADC2_HPF_EN (1 << 3) +#define ADC2_HPF_CF (3 << 1) +#define ADC2_NG_ALL (1 << 0) + +/* CS53L30_INT */ +#define PDN_DONE (1 << 7) +#define THMS_TRIP (1 << 6) +#define SYNC_DONE (1 << 5) +#define ADC2B_OVFL (1 << 4) +#define ADC2A_OVFL (1 << 3) +#define ADC1B_OVFL (1 << 2) +#define ADC1A_OVFL (1 << 1) +#define MUTE_PIN (1 << 0) +#define DEVICE_INT_MASK 0xFF + +/* Serial Ports */ +#define CS53L30_ASP1 0 +#define CS53L30_ASP2 1 + +#endif /* __CS53L30_H__ */ -- 2.4.5

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