July 2014 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [RFC] question regarding codec DAI ops
by Arnaud Pouliquen 01 Jul '14

01 Jul '14

Hello, I have a platform with several audio IOs (DAC , HDMI...) and I2S In/out connectors. I'm using my codec driver but for this I2S output i used dummy codec driver with the snd-soc-dummy-dai dai. On platform side I have several instances of CPU DAI, and i'm using helpers function like snd_soc_dai_set_tdm_slot to configure associated codec DAIs. My issue is that these functions return error for my I2S output because ops functions are not implemented in dummy driver. I see 3 solutions: - implement ops in dummy drivers ( soc-utils) - return 0 instead of error when ops is not implemented ( soc-core) - Add a test in my driver on ops before calling it. First one seems the best compromise to avoid to accumulate tests in platform drivers. From your point of view, what should be best solution? BR Arnaud

2 5

[alsa-devel] [PATCH 2/2] ASoC: add driver for Rockchip RK3xxx I2S controller
by jianqun 01 Jul '14

01 Jul '14

From: Jianqun Xu <xjq(a)rock-chips.com> Add driver for I2S controller in Rockchip RK3xxx SoCs. This driver patch has been tested on the RK3288 SDK board. Signed-off-by: Jianqun Xu <xjq(a)rock-chips.com> --- sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/rockchip/Kconfig | 16 + sound/soc/rockchip/Makefile | 6 + sound/soc/rockchip/i2s.h | 222 +++++++++++++ sound/soc/rockchip/pcm.h | 14 + sound/soc/rockchip/rockchip_i2s.c | 622 +++++++++++++++++++++++++++++++++++++ sound/soc/rockchip/rockchip_pcm.c | 64 ++++ 8 files changed, 946 insertions(+) create mode 100644 sound/soc/rockchip/Kconfig create mode 100644 sound/soc/rockchip/Makefile create mode 100644 sound/soc/rockchip/i2s.h create mode 100644 sound/soc/rockchip/pcm.h create mode 100644 sound/soc/rockchip/rockchip_i2s.c create mode 100644 sound/soc/rockchip/rockchip_pcm.c diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 0060b31..0e96233 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -47,6 +47,7 @@ source "sound/soc/kirkwood/Kconfig" source "sound/soc/intel/Kconfig" source "sound/soc/mxs/Kconfig" source "sound/soc/pxa/Kconfig" +source "sound/soc/rockchip/Kconfig" source "sound/soc/samsung/Kconfig" source "sound/soc/s6000/Kconfig" source "sound/soc/sh/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 5f1df02..534714a 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/ obj-$(CONFIG_SND_SOC) += omap/ obj-$(CONFIG_SND_SOC) += kirkwood/ obj-$(CONFIG_SND_SOC) += pxa/ +obj-$(CONFIG_SND_SOC) += rockchip/ obj-$(CONFIG_SND_SOC) += samsung/ obj-$(CONFIG_SND_SOC) += s6000/ obj-$(CONFIG_SND_SOC) += sh/ diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig new file mode 100644 index 0000000..946b60c --- /dev/null +++ b/sound/soc/rockchip/Kconfig @@ -0,0 +1,16 @@ +config SND_SOC_ROCKCHIP + tristate "ASoC support for Rockchip" + depends on SND_SOC && ARCH_ROCKCHIP + select SND_SOC_GENERIC_DMAENGINE_PCM + select SND_ROCKCHIP_PCM + select SND_ROCKCHIP_I2S + help + Say Y or M if you want to add support for codecs attached to + the Rockchip SoCs' Audio interfaces. You will also need to + select the audio interfaces to support below. + +config SND_ROCKCHIP_I2S + tristate + +config SND_ROCKCHIP_PCM + tristate diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile new file mode 100644 index 0000000..0b5d47e --- /dev/null +++ b/sound/soc/rockchip/Makefile @@ -0,0 +1,6 @@ +# ROCKCHIP Platform Support +snd-soc-i2s-objs := rockchip_i2s.o +snd-soc-pcm-objs := rockchip_pcm.o + +obj-$(CONFIG_SND_ROCKCHIP_I2S) += snd-soc-i2s.o +obj-$(CONFIG_SND_ROCKCHIP_PCM) += snd-soc-pcm.o diff --git a/sound/soc/rockchip/i2s.h b/sound/soc/rockchip/i2s.h new file mode 100644 index 0000000..54a5a67 --- /dev/null +++ b/sound/soc/rockchip/i2s.h @@ -0,0 +1,222 @@ +/* + * i2s.h - ALSA IIS interface for the rockchip SoC + * + * Driver for rockchip iis audio + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/version.h> + +#ifndef _ROCKCHIP_IIS_H +#define _ROCKCHIP_IIS_H + +/* + * TXCR + * transmit operation control register +*/ +#define I2S_TXCR_RCNT_SHIFT 17 +#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) +#define I2S_TXCR_CSR_SHIFT 15 +#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) +#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) +#define I2S_TXCR_HWT BIT(14) +#define I2S_TXCR_SJM_SHIFT 12 +#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) +#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) +#define I2S_TXCR_FBM_SHIFT 11 +#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) +#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) +#define I2S_TXCR_IBM_SHIFT 9 +#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) +#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) +#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) +#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) +#define I2S_TXCR_PBM_SHIFT 7 +#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) +#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) +#define I2S_TXCR_TFS_SHIFT 5 +#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) +#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) +#define I2S_TXCR_VDW_SHIFT 0 +#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) +#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) + +/* + * RXCR + * receive operation control register +*/ +#define I2S_RXCR_HWT BIT(14) +#define I2S_RXCR_SJM_SHIFT 12 +#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) +#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) +#define I2S_RXCR_FBM_SHIFT 11 +#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) +#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) +#define I2S_RXCR_IBM_SHIFT 9 +#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) +#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) +#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) +#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) +#define I2S_RXCR_PBM_SHIFT 7 +#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) +#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) +#define I2S_RXCR_TFS_SHIFT 5 +#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) +#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) +#define I2S_RXCR_VDW_SHIFT 0 +#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) +#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) + +/* + * CKR + * clock generation register +*/ +#define I2S_CKR_MSS_SHIFT 27 +#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) +#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) +#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) +#define I2S_CKR_CKP_SHIFT 26 +#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) +#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) +#define I2S_CKR_RLP_SHIFT 25 +#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) +#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT) +#define I2S_CKR_TLP_SHIFT 24 +#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) +#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT) +#define I2S_CKR_MDIV_SHIFT 16 +#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT) +#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) +#define I2S_CKR_RSD_SHIFT 8 +#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT) +#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) +#define I2S_CKR_TSD_SHIFT 0 +#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT) +#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) + +/* + * FIFOLR + * FIFO level register +*/ +#define I2S_FIFOLR_RFL_SHIFT 24 +#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) +#define I2S_FIFOLR_TFL3_SHIFT 18 +#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) +#define I2S_FIFOLR_TFL2_SHIFT 12 +#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) +#define I2S_FIFOLR_TFL1_SHIFT 6 +#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) +#define I2S_FIFOLR_TFL0_SHIFT 0 +#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) + +/* + * DMACR + * DMA control register +*/ +#define I2S_DMACR_RDE_SHIFT 24 +#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) +#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) +#define I2S_DMACR_RDL_SHIFT 16 +#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT) +#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) +#define I2S_DMACR_TDE_SHIFT 8 +#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) +#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) +#define I2S_DMACR_TDL_SHIFT 0 +#define I2S_DMACR_TDL(x) ((x - 1) << I2S_DMACR_TDL_SHIFT) +#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) + +/* + * INTCR + * interrupt control register +*/ +#define I2S_INTCR_RFT_SHIFT 20 +#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT) +#define I2S_INTCR_RXOIC BIT(18) +#define I2S_INTCR_RXOIE_SHIFT 17 +#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) +#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT) +#define I2S_INTCR_RXFIE_SHIFT 16 +#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) +#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) +#define I2S_INTCR_TFT_SHIFT 4 +#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT) +#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) +#define I2S_INTCR_TXUIC BIT(2) +#define I2S_INTCR_TXUIE_SHIFT 1 +#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT) +#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT) + +/* + * INTSR + * interrupt status register +*/ +#define I2S_INTSR_TXEIE_SHIFT 0 +#define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT) +#define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT) +#define I2S_INTSR_RXOI_SHIFT 17 +#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) +#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) +#define I2S_INTSR_RXFI_SHIFT 16 +#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) +#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) +#define I2S_INTSR_TXUI_SHIFT 1 +#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) +#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) +#define I2S_INTSR_TXEI_SHIFT 0 +#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) +#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) + +/* + * XFER + * Transfer start register +*/ +#define I2S_XFER_RXS_SHIFT 1 +#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) +#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) +#define I2S_XFER_TXS_SHIFT 0 +#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) +#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) + +/* + * CLR + * clear SCLK domain logic register +*/ +#define I2S_CLR_RXC BIT(1) +#define I2S_CLR_TXC BIT(0) + +/* + * TXDR + * Transimt FIFO data register, write only. +*/ +#define I2S_TXDR_MASK (0xff) + +/* + * RXDR + * Receive FIFO data register, write only. +*/ +#define I2S_RXDR_MASK (0xff) + +/* Clock divider id */ +enum { + ROCKCHIP_DIV_MCLK = 0, + ROCKCHIP_DIV_BCLK, +}; + +/* I2S REGS */ +#define I2S_TXCR (0x0000) +#define I2S_RXCR (0x0004) +#define I2S_CKR (0x0008) +#define I2S_FIFOLR (0x000c) +#define I2S_DMACR (0x0010) +#define I2S_INTCR (0x0014) +#define I2S_INTSR (0x0018) +#define I2S_XFER (0x001c) +#define I2S_CLR (0x0020) +#define I2S_TXDR (0x0024) +#define I2S_RXDR (0x0028) + +#endif /* _ROCKCHIP_IIS_H */ diff --git a/sound/soc/rockchip/pcm.h b/sound/soc/rockchip/pcm.h new file mode 100644 index 0000000..c373058 --- /dev/null +++ b/sound/soc/rockchip/pcm.h @@ -0,0 +1,14 @@ +/* sound/soc/rockchip/pcm.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _ROCKCHIP_PCM_H +#define _ROCKCHIP_PCM_H + +int rockchip_pcm_platform_register(struct device *dev); +void rockchip_pcm_platform_unregister(struct device *dev); + +#endif /* _ROCKCHIP_PCM_H */ diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c new file mode 100644 index 0000000..bb52ae3 --- /dev/null +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -0,0 +1,622 @@ +/* sound/soc/rockchip/i2s.c + * + * ALSA SoC Audio Layer - Rockchip I2S Controller driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/version.h> +#include <linux/of.h> +#include <linux/of_gpio.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/spinlock.h> +#include <linux/workqueue.h> +#include <asm/dma.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/initval.h> +#include <sound/soc.h> +#include <sound/dmaengine_pcm.h> + +#include "pcm.h" +#include "i2s.h" + +#define DRV_NAME "rockchip-i2s" + +struct rk_i2s_dev { + void __iomem *regs; + struct device *dev; + + struct clk *hclk; + struct clk *clk; + + struct snd_dmaengine_dai_dma_data capture_dma_data; + struct snd_dmaengine_dai_dma_data playback_dma_data; + + bool i2s_tx_status; + bool i2s_rx_status; + + spinlock_t lock; +}; + +static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) +{ + return snd_soc_dai_get_drvdata(dai); +} + +static inline void i2s_writel(struct rk_i2s_dev *i2s, u32 value, + unsigned int offset) +{ + writel_relaxed(value, i2s->regs + offset); +} + +static inline u32 i2s_readl(struct rk_i2s_dev *i2s, unsigned int offset) +{ + return readl_relaxed(i2s->regs + offset); +} + +static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) +{ + u32 opr, xfer, clr; + unsigned long flags; + bool need_delay = false; + int try_cnt = 10; + + spin_lock_irqsave(&i2s->lock, flags); + + opr = i2s_readl(i2s, I2S_DMACR); + xfer = i2s_readl(i2s, I2S_XFER); + clr = i2s_readl(i2s, I2S_CLR); + + if (on) { + if ((opr & I2S_DMACR_TDE_ENABLE) == 0) { + opr |= I2S_DMACR_TDE_ENABLE; + i2s_writel(i2s, opr, I2S_DMACR); + } + + if ((xfer & I2S_XFER_TXS_START) == 0 || + (xfer & I2S_XFER_RXS_START) == 0) { + xfer |= I2S_XFER_TXS_START; + xfer |= I2S_XFER_RXS_START; + i2s_writel(i2s, xfer, I2S_XFER); + } + + i2s->i2s_tx_status = 1; + } else { + i2s->i2s_tx_status = 0; + + opr &= ~I2S_DMACR_TDE_ENABLE; + i2s_writel(i2s, opr, I2S_DMACR); + + if (i2s->i2s_rx_status == 0) { + xfer &= ~I2S_XFER_TXS_START; + xfer &= ~I2S_XFER_RXS_START; + i2s_writel(i2s, xfer, I2S_XFER); + + clr |= I2S_CLR_TXC; + clr |= I2S_CLR_RXC; + i2s_writel(i2s, clr, I2S_CLR); + + need_delay = true; + } + } + + spin_unlock_irqrestore(&i2s->lock, flags); + + if (need_delay) { + while (i2s_readl(i2s, I2S_CLR) && try_cnt) { + udelay(1); + try_cnt--; + } + } +} + +static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) +{ + u32 opr, xfer, clr; + unsigned long flags; + bool need_delay = false; + int try_cnt = 10; + + spin_lock_irqsave(&i2s->lock, flags); + + opr = i2s_readl(i2s, I2S_DMACR); + xfer = i2s_readl(i2s, I2S_XFER); + clr = i2s_readl(i2s, I2S_CLR); + + if (on) { + if ((opr & I2S_DMACR_RDE_ENABLE) == 0) { + opr |= I2S_DMACR_RDE_ENABLE; + i2s_writel(i2s, opr, I2S_DMACR); + } + + if ((xfer & I2S_XFER_TXS_START) == 0 || + (xfer & I2S_XFER_RXS_START) == 0) { + xfer |= I2S_XFER_TXS_START; + xfer |= I2S_XFER_RXS_START; + i2s_writel(i2s, xfer, I2S_XFER); + } + + i2s->i2s_rx_status = 1; + } else { + i2s->i2s_rx_status = 0; + + opr &= ~I2S_DMACR_RDE_ENABLE; + i2s_writel(i2s, opr, I2S_DMACR); + + if (i2s->i2s_tx_status == 0) { + xfer &= ~I2S_XFER_RXS_START; + xfer &= ~I2S_XFER_TXS_START; + i2s_writel(i2s, xfer, I2S_XFER); + + clr |= I2S_CLR_TXC; + clr |= I2S_CLR_RXC; + i2s_writel(i2s, clr, I2S_CLR); + + need_delay = true; + } + } + + spin_unlock_irqrestore(&i2s->lock, flags); + + if (need_delay) { + while (i2s_readl(i2s, I2S_CLR) && try_cnt) { + udelay(1); + try_cnt--; + } + } +} + +static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) +{ + struct rk_i2s_dev *i2s = to_info(cpu_dai); + unsigned long flags; + u32 tx_ctl, rx_ctl; + u32 iis_ckr_value; + int ret = 0; + + spin_lock_irqsave(&i2s->lock, flags); + + iis_ckr_value = i2s_readl(i2s, I2S_CKR); + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + iis_ckr_value &= ~I2S_CKR_MSS_MASK; + iis_ckr_value |= I2S_CKR_MSS_SLAVE; + break; + case SND_SOC_DAIFMT_CBS_CFS: + iis_ckr_value &= ~I2S_CKR_MSS_MASK; + iis_ckr_value |= I2S_CKR_MSS_MASTER; + break; + default: + ret = -EINVAL; + goto exit; + } + + i2s_writel(i2s, iis_ckr_value, I2S_CKR); + + tx_ctl = i2s_readl(i2s, I2S_TXCR); + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_RIGHT_J: + tx_ctl &= ~I2S_TXCR_IBM_MASK; + tx_ctl |= I2S_TXCR_IBM_RSJM; + break; + case SND_SOC_DAIFMT_LEFT_J: + tx_ctl &= ~I2S_TXCR_IBM_MASK; + tx_ctl |= I2S_TXCR_IBM_LSJM; + break; + case SND_SOC_DAIFMT_I2S: + tx_ctl &= ~I2S_TXCR_IBM_MASK; + tx_ctl |= I2S_TXCR_IBM_NORMAL; + break; + default: + ret = -EINVAL; + goto exit; + } + + i2s_writel(i2s, tx_ctl, I2S_TXCR); + + rx_ctl = i2s_readl(i2s, I2S_RXCR); + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_RIGHT_J: + rx_ctl &= ~I2S_RXCR_IBM_MASK; + rx_ctl |= I2S_RXCR_IBM_RSJM; + break; + case SND_SOC_DAIFMT_LEFT_J: + rx_ctl &= ~I2S_RXCR_IBM_MASK; + rx_ctl |= I2S_RXCR_IBM_LSJM; + break; + case SND_SOC_DAIFMT_I2S: + rx_ctl &= ~I2S_RXCR_IBM_MASK; + rx_ctl |= I2S_RXCR_IBM_NORMAL; + break; + default: + ret = -EINVAL; + goto exit; + } + + i2s_writel(i2s, rx_ctl, I2S_RXCR); + +exit: + spin_unlock_irqrestore(&i2s->lock, flags); + + return ret; +} + +static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct rk_i2s_dev *i2s = to_info(dai); + unsigned long flags; + u32 tx_ctl, rx_ctl; + u32 dmacr; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + dai->playback_dma_data = &i2s->playback_dma_data; + else + dai->capture_dma_data = &i2s->capture_dma_data; + + spin_lock_irqsave(&i2s->lock, flags); + + tx_ctl = i2s_readl(i2s, I2S_TXCR); + tx_ctl &= ~I2S_TXCR_VDW_MASK; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S8: + tx_ctl |= I2S_TXCR_VDW(8); + break; + case SNDRV_PCM_FORMAT_S16_LE: + tx_ctl |= I2S_TXCR_VDW(16); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + tx_ctl |= I2S_TXCR_VDW(20); + break; + case SNDRV_PCM_FORMAT_S24_LE: + tx_ctl |= I2S_TXCR_VDW(24); + break; + case SNDRV_PCM_FORMAT_S32_LE: + tx_ctl |= I2S_TXCR_VDW(32); + break; + } + + i2s_writel(i2s, tx_ctl, I2S_TXCR); + + rx_ctl = i2s_readl(i2s, I2S_TXCR); + rx_ctl &= ~I2S_TXCR_VDW_MASK; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S8: + rx_ctl |= I2S_TXCR_VDW(8); + break; + case SNDRV_PCM_FORMAT_S16_LE: + rx_ctl |= I2S_TXCR_VDW(16); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + rx_ctl |= I2S_TXCR_VDW(20); + break; + case SNDRV_PCM_FORMAT_S24_LE: + rx_ctl |= I2S_TXCR_VDW(24); + break; + case SNDRV_PCM_FORMAT_S32_LE: + rx_ctl |= I2S_TXCR_VDW(32); + break; + } + + i2s_writel(i2s, rx_ctl, I2S_RXCR); + + dmacr = i2s_readl(i2s, I2S_DMACR); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + dmacr = ((dmacr & ~I2S_DMACR_TDL_MASK) | + I2S_DMACR_TDL(1) | + I2S_DMACR_TDE_ENABLE); + else + dmacr = ((dmacr & ~I2S_DMACR_RDL_MASK) | + I2S_DMACR_RDL(1) | + I2S_DMACR_RDE_ENABLE); + + i2s_writel(i2s, dmacr, I2S_DMACR); + + spin_unlock_irqrestore(&i2s->lock, flags); + + return 0; +} + +static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct rk_i2s_dev *i2s = to_info(dai); + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + rockchip_snd_rxctrl(i2s, 1); + else + rockchip_snd_txctrl(i2s, 1); + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + rockchip_snd_rxctrl(i2s, 0); + else + rockchip_snd_txctrl(i2s, 0); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, + int clk_id, unsigned int freq, int dir) +{ + struct rk_i2s_dev *i2s = to_info(cpu_dai); + + clk_set_rate(i2s->clk, freq); + + return 0; +} + +static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, + int div_id, int div) +{ + struct rk_i2s_dev *i2s = to_info(cpu_dai); + unsigned long flags; + u32 reg; + int ret; + + spin_lock_irqsave(&i2s->lock, flags); + + reg = i2s_readl(i2s, I2S_CKR); + switch (div_id) { + case ROCKCHIP_DIV_BCLK: + reg &= ~I2S_CKR_TSD_MASK; + reg |= I2S_CKR_TSD(div); + reg &= ~I2S_CKR_RSD_MASK; + reg |= I2S_CKR_RSD(div); + break; + case ROCKCHIP_DIV_MCLK: + reg &= ~I2S_CKR_MDIV_MASK; + reg |= I2S_CKR_MDIV(div); + break; + default: + ret = -EINVAL; + goto exit; + } + + i2s_writel(i2s, reg, I2S_CKR); + +exit: + spin_unlock_irqrestore(&i2s->lock, flags); + + return ret; +} + +static struct snd_soc_dai_ops rockchip_i2s_dai_ops = { + .trigger = rockchip_i2s_trigger, + .hw_params = rockchip_i2s_hw_params, + .set_fmt = rockchip_i2s_set_fmt, + .set_clkdiv = rockchip_i2s_set_clkdiv, + .set_sysclk = rockchip_i2s_set_sysclk, +}; + +#define ROCKCHIP_I2S_STEREO_RATES SNDRV_PCM_RATE_8000_96000 +#define ROCKCHIP_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S8) + +struct snd_soc_dai_driver rockchip_i2s_dai[] = { + { + .name = "rockchip-i2s.0", + .id = 0, + .playback = { + .channels_min = 2, + .channels_max = 8, + .rates = ROCKCHIP_I2S_STEREO_RATES, + .formats = ROCKCHIP_I2S_FORMATS, + }, + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = ROCKCHIP_I2S_STEREO_RATES, + .formats = ROCKCHIP_I2S_FORMATS, + }, + .ops = &rockchip_i2s_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "rockchip-i2s.1", + .id = 1, + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = ROCKCHIP_I2S_STEREO_RATES, + .formats = ROCKCHIP_I2S_FORMATS, + }, + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = ROCKCHIP_I2S_STEREO_RATES, + .formats = ROCKCHIP_I2S_FORMATS, + }, + .ops = &rockchip_i2s_dai_ops, + .symmetric_rates = 1, + }, +}; + +static const struct snd_soc_component_driver rockchip_i2s_component = { + .name = DRV_NAME, +}; + +#ifdef CONFIG_PM_RUNTIME +static int i2s_runtime_suspend(struct device *dev) +{ + struct rk_i2s_dev *i2s = dev_get_drvdata(dev); + + clk_disable_unprepare(i2s->clk); + + return 0; +} + +static int i2s_runtime_resume(struct device *dev) +{ + struct rk_i2s_dev *i2s = dev_get_drvdata(dev); + + return clk_prepare_enable(i2s->clk); +} +#else +#define i2s_runtime_suspend NULL +#define i2s_runtime_resume NULL +#endif + +static int rockchip_i2s_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct rk_i2s_dev *i2s; + struct resource *res; + int ret; + + i2s = devm_kzalloc(&pdev->dev, sizeof(struct rk_i2s_dev), + GFP_KERNEL); + if (!i2s) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2s->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(i2s->regs)) { + dev_err(&pdev->dev, "Could not get I2S source, %p\n", + i2s->regs); + return PTR_ERR(i2s->regs); + } + + i2s->playback_dma_data.addr = res->start + I2S_TXDR; + i2s->playback_dma_data.addr_width = 4; + i2s->playback_dma_data.maxburst = 1; + + i2s->capture_dma_data.addr = res->start + I2S_RXDR; + i2s->capture_dma_data.addr_width = 4; + i2s->capture_dma_data.maxburst = 1; + + i2s->i2s_tx_status = false; + i2s->i2s_rx_status = false; + + spin_lock_init(&i2s->lock); + + ret = rockchip_pcm_platform_register(&pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Could not register PCM\n"); + goto err_pcm_register; + } + + /* Must success to get some clocks from dt */ + i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); + if (IS_ERR(i2s->hclk)) { + dev_err(&pdev->dev, "Could not get i2s_hclk\n"); + return PTR_ERR(i2s->hclk); + } + + i2s->clk = devm_clk_get(&pdev->dev, "i2s_clk"); + if (IS_ERR(i2s->clk)) { + dev_err(&pdev->dev, "Could not get i2s_clk\n"); + return PTR_ERR(i2s->clk); + } + + ret = clk_prepare_enable(i2s->hclk); + if (ret) { + dev_err(&pdev->dev, "Could not enable i2s_hclk\n"); + return ret; + } + + ret = clk_prepare_enable(i2s->clk); + if (ret) { + dev_err(&pdev->dev, "Could not enable i2s_clk\n"); + goto err_hclk_disable; + } + + /* Try to set the I2S Channel id from dt */ + pdev->id = of_alias_get_id(np, "i2s"); + dev_set_name(&pdev->dev, "%s.%d", + pdev->dev.driver->name, + pdev->id); + + i2s->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, i2s); + + ret = devm_snd_soc_register_component(&pdev->dev, + &rockchip_i2s_component, + &rockchip_i2s_dai[pdev->id], 1); + if (ret) { + dev_err(&pdev->dev, "Could not register DAI\n"); + goto err_clk_disable; + } + + pm_runtime_enable(&pdev->dev); + + return 0; + +err_clk_disable: + clk_disable_unprepare(i2s->clk); +err_hclk_disable: + clk_disable_unprepare(i2s->hclk); +err_pcm_register: + rockchip_pcm_platform_unregister(&pdev->dev); + + return ret; +} + +static int rockchip_i2s_remove(struct platform_device *pdev) +{ + struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); + + clk_disable_unprepare(i2s->clk); + clk_disable_unprepare(i2s->hclk); + rockchip_pcm_platform_unregister(&pdev->dev); + snd_soc_unregister_component(&pdev->dev); + + return 0; +} + +static const struct of_device_id rockchip_i2s_match[] = { + { + .compatible = "rockchip,rk3066-i2s" + }, +}; +MODULE_DEVICE_TABLE(of, rockchip_i2s_match); + +static const struct dev_pm_ops rockchip_i2s_pm_ops = { + SET_RUNTIME_PM_OPS(i2s_runtime_suspend, + i2s_runtime_resume, NULL) +}; + +static struct platform_driver rockchip_i2s_driver = { + .probe = rockchip_i2s_probe, + .remove = rockchip_i2s_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(rockchip_i2s_match), + .pm = &rockchip_i2s_pm_ops, + }, +}; +module_platform_driver(rockchip_i2s_driver); + +MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); +MODULE_AUTHOR("jianqun <jay.xu(a)rock-chips.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/rockchip/rockchip_pcm.c b/sound/soc/rockchip/rockchip_pcm.c new file mode 100644 index 0000000..454c609 --- /dev/null +++ b/sound/soc/rockchip/rockchip_pcm.c @@ -0,0 +1,64 @@ +/* sound/soc/rockchip/pcm.c + * + * ALSA SoC Audio Layer - Rockchip I2S Controller driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_gpio.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/dmaengine_pcm.h> + +#include "pcm.h" + +static const struct snd_pcm_hardware rockchip_pcm_hardware = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S20_3LE | + SNDRV_PCM_FMTBIT_S16_LE, + .channels_min = 2, + .channels_max = 8, + .buffer_bytes_max = 128*1024, + .period_bytes_min = 64, + .period_bytes_max = 2048*4, + .periods_min = 3, + .periods_max = 128, + .fifo_size = 16, +}; + +static const struct snd_dmaengine_pcm_config rockchip_dmaengine_pcm_config = { + .pcm_hardware = &rockchip_pcm_hardware, + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, + .compat_filter_fn = NULL, + .prealloc_buffer_size = PAGE_SIZE * 8, +}; + +int rockchip_pcm_platform_register(struct device *dev) +{ + return snd_dmaengine_pcm_register(dev, &rockchip_dmaengine_pcm_config, + SND_DMAENGINE_PCM_FLAG_COMPAT| + SND_DMAENGINE_PCM_FLAG_NO_RESIDUE); +} +EXPORT_SYMBOL_GPL(rockchip_pcm_platform_register); + +void rockchip_pcm_platform_unregister(struct device *dev) +{ + snd_dmaengine_pcm_unregister(dev); +} +EXPORT_SYMBOL_GPL(rockchip_pcm_platform_unregister); + +MODULE_DESCRIPTION("ROCKCHIP PCM ASoC Interface"); +MODULE_AUTHOR("jianqun <jay.xu(a)rock-chips.com>"); +MODULE_LICENSE("GPL v2"); -- 1.7.9.5

3 2

[alsa-devel] [PATCH] ICE1712: add surround71 pcm definition
by Alexander E. Patrakov 01 Jul '14

01 Jul '14

The M-Audio Delta 1010 card has 7.1 analog output, but no ready-made pcm definition to use it. Signed-off-by: Alexander E. Patrakov <patrakov(a)gmail.com> Reported-and-tested-by: Matt Zagrabelny <mzagrabe(a)d.umn.edu> --- src/conf/cards/ICE1712.conf | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/conf/cards/ICE1712.conf b/src/conf/cards/ICE1712.conf index 398fa7a..db62684 100644 --- a/src/conf/cards/ICE1712.conf +++ b/src/conf/cards/ICE1712.conf @@ -78,6 +78,7 @@ ICE1712.pcm.surround40.0 { <confdir:pcm/surround41.conf> <confdir:pcm/surround50.conf> <confdir:pcm/surround51.conf> +<confdir:pcm/surround71.conf> ICE1712.pcm.surround51.0 { @args [ CARD ] @@ -98,6 +99,27 @@ ICE1712.pcm.surround51.0 { slave.channels 10 } +ICE1712.pcm.surround71.0 { + @args [ CARD ] + @args.CARD { + type string + } + type route + ttable.0.0 1 + ttable.1.1 1 + ttable.2.2 1 + ttable.3.3 1 + ttable.4.4 1 + ttable.5.5 1 + ttable.6.6 1 + ttable.7.7 1 + slave.pcm { + type hw + card $CARD + } + slave.channels 10 +} + <confdir:pcm/iec958.conf> ICE1712.pcm.iec958.0 { -- 2.0.0

2 1

[alsa-devel] [PATCH 1/2] ALSA: trident: Remove unused variable in trident_main.c
by Sachin Kamat 01 Jul '14

01 Jul '14

'private_data' is not used in the function. Remove it. Signed-off-by: Sachin Kamat <sachin.kamat(a)samsung.com> --- sound/pci/trident/trident_main.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/sound/pci/trident/trident_main.c b/sound/pci/trident/trident_main.c index 1272c18a2544..da875dced2ef 100644 --- a/sound/pci/trident/trident_main.c +++ b/sound/pci/trident/trident_main.c @@ -3880,14 +3880,12 @@ void snd_trident_free_voice(struct snd_trident * trident, struct snd_trident_voi { unsigned long flags; void (*private_free)(struct snd_trident_voice *); - void *private_data; if (voice == NULL || !voice->use) return; snd_trident_clear_voices(trident, voice->number, voice->number); spin_lock_irqsave(&trident->voice_alloc, flags); private_free = voice->private_free; - private_data = voice->private_data; voice->private_free = NULL; voice->private_data = NULL; if (voice->pcm) -- 1.7.9.5

2 2

[alsa-devel] [PATCH (hda-emu)] Adapt to new snd_hda_calc_stream_format
by David Henningsson 01 Jul '14

01 Jul '14

Signed-off-by: David Henningsson <david.henningsson(a)canonical.com> --- configure.ac | 23 +++++++++++++++++++++++ hda-emu.c | 6 +++++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 31b31cd..fe5c0e2 100644 --- a/configure.ac +++ b/configure.ac @@ -488,6 +488,29 @@ if test "$STREAM_FORMAT_WITH_SPDIF" = "1"; then fi fi +AC_MSG_CHECKING(for snd_hda_calc_stream_format with codec) +ac_save_CFLAGS="$CFLAGS" +CFLAGS="$CFLAGS -Iinclude" +STREAM_FORMAT_WITH_CODEC= +AC_TRY_COMPILE([ +#include "hda-types.h" +#include "hda-log.h" +#include <sound/driver.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include "hda/hda_codec.h" +],[ + snd_hda_calc_stream_format(0, 0, 0, 0, 0, 0); +], + [AC_MSG_RESULT(yes); STREAM_FORMAT_WITH_CODEC="1"], + [AC_MSG_RESULT(no)], + [AC_MSG_RESULT(unknown)] +) +CFLAGS=$ac_save_CFLAGS +if test "$STREAM_FORMAT_WITH_CODEC" = "1"; then + AC_DEFINE(STREAM_FORMAT_WITH_CODEC) +fi + HAVE_COMMON_PREPARE= AC_MSG_CHECKING(for common snd_hda_codec_prepare/cleanup) if grep -q snd_hda_codec_prepare hda/hda_codec.h; then diff --git a/hda-emu.c b/hda-emu.c index b564e34..e8309d5 100644 --- a/hda-emu.c +++ b/hda-emu.c @@ -798,7 +798,11 @@ void hda_test_pcm(int id, int op, int subid, hda_log(HDA_LOG_INFO, "Prepare PCM, rate=%d, channels=%d, " "format=%d bits\n", rate, channels, format); - format_val = snd_hda_calc_stream_format(rate, channels, + format_val = snd_hda_calc_stream_format( +#if defined(STREAM_FORMAT_WITH_CODEC) + _codec, +#endif + rate, channels, get_alsa_format(format), format #if defined(INDIVIDUAL_SPDIF_CTLS) || defined(STREAM_FORMAT_WITH_SPDIF) -- 1.9.1

2 1

[alsa-devel] [PATCH v2] ASoC: tas2552: Support TI TAS2552 Amplifier
by Dan Murphy 01 Jul '14

01 Jul '14

Support the TI TAS2552 Class D amplifier. The TAS2552 is a high efficiency Class-D audio power amplifier with advanced battery current management and an integrated Class-G boost The device constantly measures the current and voltage across the load and provides a digital stream of this information. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- v2 - Address RFC comments- Added regmap, and snd_soc calls removed debug code, address checkpatch errors -https://patchwork.kernel.org/patch/4378281/ .../devicetree/bindings/sound/tas2552.txt | 22 + include/sound/tas2552-plat.h | 25 ++ sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/tas2552.c | 462 ++++++++++++++++++++ sound/soc/codecs/tas2552.h | 75 ++++ 6 files changed, 591 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/tas2552.txt create mode 100644 include/sound/tas2552-plat.h create mode 100644 sound/soc/codecs/tas2552.c create mode 100644 sound/soc/codecs/tas2552.h diff --git a/Documentation/devicetree/bindings/sound/tas2552.txt b/Documentation/devicetree/bindings/sound/tas2552.txt new file mode 100644 index 0000000..58e931b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tas2552.txt @@ -0,0 +1,22 @@ +Texas Instruments - tas2552 Codec module + +The tas2552 serial control bus communicates through I2C protocols + +Required properties: + +- compatible - "string" - One of: + "ti,tas2552" - TAS2552 + +- reg - <int> - I2C slave address + +Optional properties: + +- power-gpio - gpio pin to enable/disable the device + +Example: + +tas2552: tas2552@41 { + compatible = "ti,tas2552"; + reg = <0x41>; + power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; +}; diff --git a/include/sound/tas2552-plat.h b/include/sound/tas2552-plat.h new file mode 100644 index 0000000..c8120f2 --- /dev/null +++ b/include/sound/tas2552-plat.h @@ -0,0 +1,25 @@ +/* + * TAS2552 driver platform header + * + * Copyright (C) 2014 Texas Instruments Inc. + * + * Author: Dan Murphy <dmurphy(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef TAS2552_PLAT_H +#define TAS2552_PLAT_H + +struct tas2552_platform_data { + int power_gpio; +}; + +#endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 0b9571c..cc09261 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -99,6 +99,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_TLV320AIC32X4 if I2C select SND_SOC_TLV320AIC3X if I2C select SND_SOC_TPA6130A2 if I2C + select SND_SOC_TAS2552 if I2C select SND_SOC_TLV320DAC33 if I2C select SND_SOC_TWL4030 if TWL4030_CORE select SND_SOC_TWL6040 if TWL6040_CORE @@ -754,4 +755,8 @@ config SND_SOC_TPA6130A2 tristate "Texas Instruments TPA6130A2 headphone amplifier" depends on I2C +config SND_SOC_TAS2552 + tristate "Texas Instruments TAS2552 Mono Audio amplifier" + depends on I2C + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 1bd6e1c..33bc7228 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -162,6 +162,7 @@ snd-soc-wm-hubs-objs := wm_hubs.o # Amp snd-soc-max9877-objs := max9877.o snd-soc-tpa6130a2-objs := tpa6130a2.o +snd-soc-tas2552-objs := tas2552.o obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o @@ -325,3 +326,4 @@ obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o # Amp obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o +obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c new file mode 100644 index 0000000..228d5bb --- /dev/null +++ b/sound/soc/codecs/tas2552.c @@ -0,0 +1,462 @@ +/* + * ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier + * + * Copyright (C) 2014 Texas Instruments Inc. + * + * Author: Dan Murphy <dmurphy(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/device.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/of_gpio.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/tlv.h> +#include <sound/tas2552-plat.h> + +#include "tas2552.h" + +static struct reg_default tas2552_reg_defs[] = { + {TAS2552_CFG_1, 0x16}, + {TAS2552_CFG_3, 0x5E}, + {TAS2552_DOUT, 0x00}, + {TAS2552_OUTPUT_DATA, 0xC8}, + {TAS2552_PDM_CFG, 0x02}, + {TAS2552_PGA_GAIN, 0x10}, + {TAS2552_BOOST_PT_CTRL, 0x0F}, + {TAS2552_LIMIT_LVL_CTRL, 0x0C}, + {TAS2552_LIMIT_RATE_HYS, 0x20}, + {TAS2552_CFG_2, 0xEA}, + {TAS2552_SER_CTRL_1, 0x00}, + {TAS2552_SER_CTRL_2, 0x00}, + {TAS2552_PLL_CTRL_1, 0x10}, + {TAS2552_PLL_CTRL_2, 0x00}, + {TAS2552_PLL_CTRL_3, 0x00}, + {TAS2552_BTIP, 0x8f}, + {TAS2552_BTS_CTRL, 0x80}, + {TAS2552_LIMIT_RELEASE, 0x05}, + {TAS2552_LIMIT_INT_COUNT, 0x00}, + {TAS2552_EDGE_RATE_CTRL, 0x40}, + {TAS2552_VBAT_DATA, 0x00}, +}; + +struct tas2552_data { + struct mutex mutex; + struct snd_soc_codec *codec; + struct regmap *regmap; + struct i2c_client *tas2552_client; + unsigned char regs[TAS2552_VBAT_DATA]; + int power_gpio; + u8 power_state:1; +}; + +static int tas2552_power(struct tas2552_data *data, u8 power) +{ + int ret = 0; + + BUG_ON(data->tas2552_client == NULL); + + mutex_lock(&data->mutex); + if (power == data->power_state) + goto exit; + + if (power) { + if (data->power_gpio >= 0) + gpio_set_value(data->power_gpio, 1); + + data->power_state = 1; + } else { + if (data->power_gpio >= 0) + gpio_set_value(data->power_gpio, 0); + + data->power_state = 0; + } + +exit: + mutex_unlock(&data->mutex); + return ret; +} + +static void tas2552_sw_shutdown(struct tas2552_data *tas_data, int sw_shutdown) +{ + u8 cfg1_reg; + + if (sw_shutdown) + cfg1_reg |= (sw_shutdown << 1); + else + cfg1_reg &= ~TAS2552_SWS_MASK; + + snd_soc_update_bits(tas_data->codec, TAS2552_CFG_1, + TAS2552_SWS_MASK, cfg1_reg); +} + +static void tas2552_init(struct snd_soc_codec *codec) +{ + snd_soc_write(codec, TAS2552_CFG_1, 0x16); + snd_soc_write(codec, TAS2552_CFG_3, 0x5E); + snd_soc_write(codec, TAS2552_DOUT, 0x00); + snd_soc_write(codec, TAS2552_OUTPUT_DATA, 0xC8); + snd_soc_write(codec, TAS2552_PDM_CFG, 0x02); + snd_soc_write(codec, TAS2552_PGA_GAIN, 0x10); + snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, 0x0F); + snd_soc_write(codec, TAS2552_LIMIT_LVL_CTRL, 0x0C); + snd_soc_write(codec, TAS2552_LIMIT_RATE_HYS, 0x20); + snd_soc_write(codec, TAS2552_CFG_2, 0xEA); +} + +static int tas2552_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + u8 wclk_reg; + struct snd_soc_codec *codec = dai->codec; + + /* Setting DAC clock dividers based on substream sample rate. */ + switch (params_rate(params)) { + case 8000: + wclk_reg = TAS2552_8KHZ; + break; + case 11025: + wclk_reg = TAS2552_11_12KHZ; + break; + case 16000: + wclk_reg = TAS2552_16KHZ; + break; + case 32000: + wclk_reg = TAS2552_32KHZ; + break; + case 22050: + case 24000: + wclk_reg = TAS2552_22_24KHZ; + break; + case 44100: + case 48000: + wclk_reg = TAS2552_44_48KHZ; + break; + case 96000: + wclk_reg = TAS2552_88_96KHZ; + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, TAS2552_CFG_3, TAS2552_WCLK_MASK, wclk_reg); + + return 0; +} + +static int tas2552_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + u8 serial_format; + struct snd_soc_codec *codec = dai->codec; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + serial_format = 0x00; + break; + case SND_SOC_DAIFMT_CBS_CFM: + serial_format = TAS2552_WORD_CLK_MASK; + break; + case SND_SOC_DAIFMT_CBM_CFS: + serial_format = TAS2552_BIT_CLK_MASK; + break; + case SND_SOC_DAIFMT_CBM_CFM: + serial_format = (TAS2552_BIT_CLK_MASK | TAS2552_WORD_CLK_MASK); + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, TAS2552_SER_CTRL_1, + (TAS2552_BIT_CLK_MASK | TAS2552_WORD_CLK_MASK), + serial_format); + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + serial_format = 0x0; + break; + case SND_SOC_DAIFMT_DSP_A: + serial_format = TAS2552_DAIFMT_DSP; + break; + case SND_SOC_DAIFMT_RIGHT_J: + serial_format = TAS2552_DAIFMT_RIGHT_J; + break; + case SND_SOC_DAIFMT_LEFT_J: + serial_format = TAS2552_DAIFMT_LEFT_J; + break; + + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, TAS2552_SER_CTRL_1, TAS2552_DATA_FORMAT_MASK, + serial_format); + + return 0; +} + +static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct tas2552_data *data = dev_get_drvdata(dai->dev); + + /* Fill in the PLL control registers for J & D + * PLL_CLK = (.5 * freq * J.D) / 2^p + * Need to fill in J and D here based on incoming freq + */ + + tas2552_sw_shutdown(data, 1); + + snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0); + + snd_soc_write(codec, TAS2552_PLL_CTRL_1, 0x10); + snd_soc_write(codec, TAS2552_PLL_CTRL_2, 0x00); + snd_soc_write(codec, TAS2552_PLL_CTRL_3, 0x00); + + snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, + TAS2552_PLL_ENABLE); + + tas2552_sw_shutdown(data, 0); + + return 0; +} + +static int tas2552_mute(struct snd_soc_dai *dai, int mute) +{ + u8 cfg1_reg; + struct snd_soc_codec *codec = dai->codec; + + if (mute) + cfg1_reg |= TAS2552_MUTE_MASK; + else + cfg1_reg &= ~TAS2552_MUTE_MASK; + + snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE_MASK, cfg1_reg); + + return 0; +} + +static int tas2552_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct tas2552_data *tas2552 = snd_soc_codec_get_drvdata(codec); + + tas2552_sw_shutdown(tas2552, 1); + tas2552_power(tas2552, 1); + + /* Turn on Class D amplifier */ + snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_CLASSD_EN_MASK, + TAS2552_CLASSD_EN); + + tas2552_sw_shutdown(tas2552, 0); + + return 0; +} + +static void tas2552_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct tas2552_data *tas2552 = snd_soc_codec_get_drvdata(codec); + + tas2552_sw_shutdown(tas2552, 1); + tas2552_power(tas2552, 0); +} + +static struct snd_soc_dai_ops tas2552_speaker_dai_ops = { + .hw_params = tas2552_hw_params, + .set_sysclk = tas2552_set_dai_sysclk, + .set_fmt = tas2552_set_dai_fmt, + .startup = tas2552_startup, + .shutdown = tas2552_shutdown, + .digital_mute = tas2552_mute, +}; + +/* Formats supported by TAS2552 driver. */ +#define TAS2552_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +/* TAS2552 dai structure. */ +static struct snd_soc_dai_driver tas2552_dai[] = { + { + .name = "tas2552-amplifier", + .playback = { + .stream_name = "Speaker", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = TAS2552_FORMATS, + }, + .ops = &tas2552_speaker_dai_ops, + }, +}; + +/* + * DAC digital volumes. From -7 to 24 dB in 1 dB steps + */ +static DECLARE_TLV_DB_SCALE(dac_tlv, -7, 100, 24); + +static const struct snd_kcontrol_new tas2552_snd_controls[] = { + SOC_SINGLE_TLV("Speaker Driver Playback Volume", + TAS2552_PGA_GAIN, 0, 0x1f, 1, dac_tlv), +}; + +static int tas2552_codec_probe(struct snd_soc_codec *codec) +{ + struct tas2552_data *tas2552 = snd_soc_codec_get_drvdata(codec); + + tas2552->codec = codec; + tas2552_power(tas2552, 1); + tas2552_init(codec); + + return 0; +} + +static int tas2552_codec_remove(struct snd_soc_codec *codec) +{ + struct tas2552_data *tas2552 = snd_soc_codec_get_drvdata(codec); + + tas2552_power(tas2552, 0); + + return 0; +}; + +static struct snd_soc_codec_driver soc_codec_dev_tas2552 = { + .probe = tas2552_codec_probe, + .remove = tas2552_codec_remove, + .controls = tas2552_snd_controls, + .num_controls = ARRAY_SIZE(tas2552_snd_controls), +}; + +static const struct regmap_config tas2552_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = TAS2552_MAX_REG, + .reg_defaults = tas2552_reg_defs, + .num_reg_defaults = ARRAY_SIZE(tas2552_reg_defs), + .cache_type = REGCACHE_RBTREE, +}; + +static int tas2552_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev; + struct tas2552_data *data; + struct tas2552_platform_data *pdata = client->dev.platform_data; + struct device_node *np = client->dev.of_node; + int ret; + + dev = &client->dev; + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + if (pdata) { + data->power_gpio = pdata->power_gpio; + } else if (np) { + data->power_gpio = of_get_named_gpio(np, "enable-gpio", 0); + } else { + dev_err(dev, "Platform data not set\n"); + return -ENODEV; + } + + data->regmap = devm_regmap_init_i2c(client, &tas2552_regmap_config); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + dev_err(&client->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + data->tas2552_client = client; + data->regmap = devm_regmap_init_i2c(client, &tas2552_regmap_config); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + dev_err(&client->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + dev_set_drvdata(&client->dev, data); + + mutex_init(&data->mutex); + + if (data->power_gpio >= 0) { + ret = devm_gpio_request(dev, data->power_gpio, "tas2552 enable"); + if (ret < 0) { + dev_err(dev, "Failed to request power GPIO (%d)\n", + data->power_gpio); + goto err_gpio; + } + gpio_direction_output(data->power_gpio, 0); + } + + ret = snd_soc_register_codec(&client->dev, + &soc_codec_dev_tas2552, + tas2552_dai, ARRAY_SIZE(tas2552_dai)); + if (ret < 0) + dev_err(&client->dev, "Failed to register codec: %d\n", ret); + + return 0; + +err_gpio: + data->tas2552_client = NULL; + return ret; +} + +static int tas2552_i2c_remove(struct i2c_client *client) +{ + snd_soc_unregister_codec(&client->dev); + return 0; +} + +static const struct i2c_device_id tas2552_id[] = { + { "tas2552-codec", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tas2552_id); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id tas2552_of_match[] = { + { .compatible = "ti,tas2552", }, + {}, +}; +MODULE_DEVICE_TABLE(of, tas2552_of_match); +#endif + +static struct i2c_driver tas2552_i2c_driver = { + .driver = { + .name = "tas2552-codec", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(tas2552_of_match), + }, + .probe = tas2552_probe, + .remove = tas2552_i2c_remove, + .id_table = tas2552_id, +}; + +module_i2c_driver(tas2552_i2c_driver); + +MODULE_AUTHOR("Dan Muprhy <dmurphy(a)ti.com>"); +MODULE_DESCRIPTION("TAS2552 Audio amplifier driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/tas2552.h b/sound/soc/codecs/tas2552.h new file mode 100644 index 0000000..174c64d --- /dev/null +++ b/sound/soc/codecs/tas2552.h @@ -0,0 +1,75 @@ +/* + * ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier + * + * Copyright (C) 2014 Texas Instruments Inc. + * + * Author: Dan Murphy <dmurphy(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef __TAS2552_H__ +#define __TAS2552_H__ + +/* Register Address Map */ +#define TAS2552_DEVICE_STATUS 0x00 +#define TAS2552_CFG_1 0x01 +#define TAS2552_CFG_2 0x02 +#define TAS2552_CFG_3 0x03 +#define TAS2552_DOUT 0x04 +#define TAS2552_SER_CTRL_1 0x05 +#define TAS2552_SER_CTRL_2 0x06 +#define TAS2552_OUTPUT_DATA 0x07 +#define TAS2552_PLL_CTRL_1 0x08 +#define TAS2552_PLL_CTRL_2 0x09 +#define TAS2552_PLL_CTRL_3 0x0a +#define TAS2552_BTIP 0x0b +#define TAS2552_BTS_CTRL 0x0c +#define TAS2552_LIMIT_LVL_CTRL 0x0d +#define TAS2552_LIMIT_RATE_HYS 0x0e +#define TAS2552_LIMIT_RELEASE 0x0f +#define TAS2552_LIMIT_INT_COUNT 0x10 +#define TAS2552_PDM_CFG 0x11 +#define TAS2552_PGA_GAIN 0x12 +#define TAS2552_EDGE_RATE_CTRL 0x13 +#define TAS2552_BOOST_PT_CTRL 0x14 +#define TAS2552_VER_NUM 0x16 +#define TAS2552_VBAT_DATA 0x19 +#define TAS2552_MAX_REG 0x20 + +/* CFG1 Register Masks */ +#define TAS2552_MUTE_MASK (1 << 2) +#define TAS2552_SWS_MASK (1 << 1) +#define TAS2552_WCLK_MASK 0x07 +#define TAS2552_CLASSD_EN_MASK (1 << 7) +#define TAS2552_CLASSD_EN 0x80 + +#define TAS2552_PLL_ENABLE (1 << 3) + +/* CFG3 Register Masks */ +#define TAS2552_WORD_CLK_MASK 0x80 +#define TAS2552_BIT_CLK_MASK 0x40 +#define TAS2552_DATA_FORMAT_MASK 0x0c + +#define TAS2552_DAIFMT_DSP 0x04 +#define TAS2552_DAIFMT_RIGHT_J 0x08 +#define TAS2552_DAIFMT_LEFT_J 0x0c + +/* WCLK Dividers */ +#define TAS2552_8KHZ 0x00 +#define TAS2552_11_12KHZ 0x01 +#define TAS2552_16KHZ 0x02 +#define TAS2552_22_24KHZ 0x03 +#define TAS2552_32KHZ 0x04 +#define TAS2552_44_48KHZ 0x05 +#define TAS2552_88_96KHZ 0x06 +#define TAS2552_176_192KHZ 0x07 + +#endif -- 1.7.9.5

3 4

[alsa-devel] [PATCH 0/5] ASoC: Fix trival sparse warnings
by Lars-Peter Clausen 01 Jul '14

01 Jul '14

Hi, This series fixes a couple of trivial issues that are reported when running the sparse codechecker on the ASoC tree. - Lars Lars-Peter Clausen (5): ASoC: tlv320aic31xx: Remove duplicate const ASoC: cs42xx8: Make of match table static ASoC: omap-pcm: Include omap-pcm.h ASoC: rcar: Fix dma direction type ASoC: sh/fsi: Make one-bit bitfields unsigned sound/soc/codecs/cs42xx8.c | 2 +- sound/soc/codecs/tlv320aic31xx.c | 21 ++++++++++----------- sound/soc/omap/omap-pcm.c | 1 + sound/soc/sh/fsi.c | 12 ++++++------ sound/soc/sh/rcar/core.c | 2 +- sound/soc/sh/rcar/rsnd.h | 2 +- 6 files changed, 20 insertions(+), 20 deletions(-) -- 1.8.0

4 18

Re: [alsa-devel] Enable HP machine to enable capture mute led and output mute led
by Takashi Iwai 01 Jul '14

01 Jul '14

At Fri, 20 Jun 2014 15:55:58 +0800, Kailang wrote: > > Hi Takashi, > > Maybe you don't receive. > I repost again. Don't worry, it's been applied now. I've been off for a few days. thanks, Takashi > > BR, > Kailang > > > > Attach again. > > It include below infomations. > > Thanks. > > > >> At Wed, 18 Jun 2014 17:13:57 +0800, > >> Kailang wrote: > >>> > >>> Hi Takashi, > >>> > >>> Attach was HP mute led support patch. > >>> It use Line1 vref and Mic1 vref to control mute led for ALC282. > >>> Line1 vref to control output mute led. > >>> Mic1 vref to control input mute led. > >>> > >>> It use GPIO3 and Mic1 vref to control mute led for ALC280. > >>> GPIO3 to control output mute led. > >>> Mic1 vref to control input mute led. > >> > >> Could you include this kind of information in the patch changelog? > >> The changelog text is way too short. > >> > >>> For the DMI string for output mute led application. > >>> I already request from HP to support it in next release. > >>> > >>> HP_Mute_LED_0_A => use Mic1 vref to control mute led. > >>> Is the string right? > >>> I have tested upper string for Mic1 mute led. > >> > >> Yes, this has been working for some machines, AFAIK. > >> > >> > >> thanks, > >> > >> Takashi > >> > >> ------Please consider the environment before printing this e-mail. > [2 0001-new-hp-mute-led.patch <application/octet-stream (quoted-printable)>] >

2 1