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[alsa-devel] [PATCH] ALSA: ASoC: fix SNDCTL_DSP_SYNC support in Freescale 8610 sound drivers
by Timur Tabi 01 Aug '08

01 Aug '08

If an OSS application calls SNDCTL_DSP_SYNC, then ALSA will call the driver's _hw_params and _prepare functions again. On the Freescale MPC8610 DMA ASoC driver, this caused the DMA controller to be unneccessarily re-programmed, and apparently it doesn't like that. The DMA will then not operate when instructed. This patch relocates much of the DMA programming to fsl_dma_open(), which is called only once. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- This patch is for 2.6.27. A separate patch for ASoC V2 will be posted later. sound/soc/fsl/fsl_dma.c | 235 +++++++++++++++++++++++++---------------------- 1 files changed, 124 insertions(+), 111 deletions(-) diff --git a/sound/soc/fsl/fsl_dma.c b/sound/soc/fsl/fsl_dma.c index 7ceea2b..d2d3da9 100644 --- a/sound/soc/fsl/fsl_dma.c +++ b/sound/soc/fsl/fsl_dma.c @@ -327,14 +327,75 @@ static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, * fsl_dma_open: open a new substream. * * Each substream has its own DMA buffer. + * + * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link + * descriptors that ping-pong from one period to the next. For example, if + * there are six periods and two link descriptors, this is how they look + * before playback starts: + * + * The last link descriptor + * ____________ points back to the first + * | | + * V | + * ___ ___ | + * | |->| |->| + * |___| |___| + * | | + * | | + * V V + * _________________________________________ + * | | | | | | | The DMA buffer is + * | | | | | | | divided into 6 parts + * |______|______|______|______|______|______| + * + * and here's how they look after the first period is finished playing: + * + * ____________ + * | | + * V | + * ___ ___ | + * | |->| |->| + * |___| |___| + * | | + * |______________ + * | | + * V V + * _________________________________________ + * | | | | | | | + * | | | | | | | + * |______|______|______|______|______|______| + * + * The first link descriptor now points to the third period. The DMA + * controller is currently playing the second period. When it finishes, it + * will jump back to the first descriptor and play the third period. + * + * There are four reasons we do this: + * + * 1. The only way to get the DMA controller to automatically restart the + * transfer when it gets to the end of the buffer is to use chaining + * mode. Basic direct mode doesn't offer that feature. + * 2. We need to receive an interrupt at the end of every period. The DMA + * controller can generate an interrupt at the end of every link transfer + * (aka segment). Making each period into a DMA segment will give us the + * interrupts we need. + * 3. By creating only two link descriptors, regardless of the number of + * periods, we do not need to reallocate the link descriptors if the + * number of periods changes. + * 4. All of the audio data is still stored in a single, contiguous DMA + * buffer, which is what ALSA expects. We're just dividing it into + * contiguous parts, and creating a link descriptor for each one. */ static int fsl_dma_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct fsl_dma_private *dma_private; + struct ccsr_dma_channel __iomem *dma_channel; dma_addr_t ld_buf_phys; + u64 temp_link; /* Pointer to next link descriptor */ + u32 mr; unsigned int channel; int ret = 0; + unsigned int i; /* * Reject any DMA buffer whose size is not a multiple of the period @@ -395,68 +456,74 @@ static int fsl_dma_open(struct snd_pcm_substream *substream) snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); runtime->private_data = dma_private; + /* Program the fixed DMA controller parameters */ + + dma_channel = dma_private->dma_channel; + + temp_link = dma_private->ld_buf_phys + + sizeof(struct fsl_dma_link_descriptor); + + for (i = 0; i < NUM_DMA_LINKS; i++) { + struct fsl_dma_link_descriptor *link = &dma_private->link[i]; + + link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); + link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); + link->next = cpu_to_be64(temp_link); + + temp_link += sizeof(struct fsl_dma_link_descriptor); + } + /* The last link descriptor points to the first */ + dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); + + /* Tell the DMA controller where the first link descriptor is */ + out_be32(&dma_channel->clndar, + CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); + out_be32(&dma_channel->eclndar, + CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); + + /* The manual says the BCR must be clear before enabling EMP */ + out_be32(&dma_channel->bcr, 0); + + /* + * Program the mode register for interrupts, external master control, + * and source/destination hold. Also clear the Channel Abort bit. + */ + mr = in_be32(&dma_channel->mr) & + ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); + + /* + * We want External Master Start and External Master Pause enabled, + * because the SSI is controlling the DMA controller. We want the DMA + * controller to be set up in advance, and then we signal only the SSI + * to start transferring. + * + * We want End-Of-Segment Interrupts enabled, because this will generate + * an interrupt at the end of each segment (each link descriptor + * represents one segment). Each DMA segment is the same thing as an + * ALSA period, so this is how we get an interrupt at the end of every + * period. + * + * We want Error Interrupt enabled, so that we can get an error if + * the DMA controller is mis-programmed somehow. + */ + mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | + CCSR_DMA_MR_EMS_EN; + + /* For playback, we want the destination address to be held. For + capture, set the source address to be held. */ + mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? + CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; + + out_be32(&dma_channel->mr, mr); + return 0; } /** - * fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors. - * - * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link - * descriptors that ping-pong from one period to the next. For example, if - * there are six periods and two link descriptors, this is how they look - * before playback starts: - * - * The last link descriptor - * ____________ points back to the first - * | | - * V | - * ___ ___ | - * | |->| |->| - * |___| |___| - * | | - * | | - * V V - * _________________________________________ - * | | | | | | | The DMA buffer is - * | | | | | | | divided into 6 parts - * |______|______|______|______|______|______| - * - * and here's how they look after the first period is finished playing: - * - * ____________ - * | | - * V | - * ___ ___ | - * | |->| |->| - * |___| |___| - * | | - * |______________ - * | | - * V V - * _________________________________________ - * | | | | | | | - * | | | | | | | - * |______|______|______|______|______|______| + * fsl_dma_hw_params: continue initializing the DMA links * - * The first link descriptor now points to the third period. The DMA - * controller is currently playing the second period. When it finishes, it - * will jump back to the first descriptor and play the third period. - * - * There are four reasons we do this: - * - * 1. The only way to get the DMA controller to automatically restart the - * transfer when it gets to the end of the buffer is to use chaining - * mode. Basic direct mode doesn't offer that feature. - * 2. We need to receive an interrupt at the end of every period. The DMA - * controller can generate an interrupt at the end of every link transfer - * (aka segment). Making each period into a DMA segment will give us the - * interrupts we need. - * 3. By creating only two link descriptors, regardless of the number of - * periods, we do not need to reallocate the link descriptors if the - * number of periods changes. - * 4. All of the audio data is still stored in a single, contiguous DMA - * buffer, which is what ALSA expects. We're just dividing it into - * contiguous parts, and creating a link descriptor for each one. + * This function obtains hardware parameters about the opened stream and + * programs the DMA controller accordingly. * * Note that due to a quirk of the SSI's STX register, the target address * for the DMA operations depends on the sample size. So we don't program @@ -468,11 +535,8 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, { struct snd_pcm_runtime *runtime = substream->runtime; struct fsl_dma_private *dma_private = runtime->private_data; - struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; dma_addr_t temp_addr; /* Pointer to next period */ - u64 temp_link; /* Pointer to next link descriptor */ - u32 mr; /* Temporary variable for MR register */ unsigned int i; @@ -490,8 +554,6 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, dma_private->dma_buf_next = dma_private->dma_buf_phys; /* - * Initialize each link descriptor. - * * The actual address in STX0 (destination for playback, source for * capture) is based on the sample size, but we don't know the sample * size in this function, so we'll have to adjust that later. See @@ -507,16 +569,11 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, * buffer itself. */ temp_addr = substream->dma_buffer.addr; - temp_link = dma_private->ld_buf_phys + - sizeof(struct fsl_dma_link_descriptor); for (i = 0; i < NUM_DMA_LINKS; i++) { struct fsl_dma_link_descriptor *link = &dma_private->link[i]; link->count = cpu_to_be32(period_size); - link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); - link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); - link->next = cpu_to_be64(temp_link); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) link->source_addr = cpu_to_be32(temp_addr); @@ -524,51 +581,7 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, link->dest_addr = cpu_to_be32(temp_addr); temp_addr += period_size; - temp_link += sizeof(struct fsl_dma_link_descriptor); } - /* The last link descriptor points to the first */ - dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); - - /* Tell the DMA controller where the first link descriptor is */ - out_be32(&dma_channel->clndar, - CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); - out_be32(&dma_channel->eclndar, - CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); - - /* The manual says the BCR must be clear before enabling EMP */ - out_be32(&dma_channel->bcr, 0); - - /* - * Program the mode register for interrupts, external master control, - * and source/destination hold. Also clear the Channel Abort bit. - */ - mr = in_be32(&dma_channel->mr) & - ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); - - /* - * We want External Master Start and External Master Pause enabled, - * because the SSI is controlling the DMA controller. We want the DMA - * controller to be set up in advance, and then we signal only the SSI - * to start transfering. - * - * We want End-Of-Segment Interrupts enabled, because this will generate - * an interrupt at the end of each segment (each link descriptor - * represents one segment). Each DMA segment is the same thing as an - * ALSA period, so this is how we get an interrupt at the end of every - * period. - * - * We want Error Interrupt enabled, so that we can get an error if - * the DMA controller is mis-programmed somehow. - */ - mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | - CCSR_DMA_MR_EMS_EN; - - /* For playback, we want the destination address to be held. For - capture, set the source address to be held. */ - mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? - CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; - - out_be32(&dma_channel->mr, mr); return 0; } -- 1.5.5

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[alsa-devel] [PATCH 01/14] ASoC: Update Poodle to current ASoC API
by Mark Brown 01 Aug '08

01 Aug '08

From: Dmitry Baryshkov <dbaryshkov(a)gmail.com> Signed-off-by: Dmitry Baryshkov <dbaryshkov(a)gmail.com> Cc: Richard Purdie <rpurdie(a)rpsys.net> Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- This is a compile fix and it would therefore be good if it could be considered for merge into 2.6.27. sound/soc/pxa/poodle.c | 8 ++------ 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/sound/soc/pxa/poodle.c b/sound/soc/pxa/poodle.c index 65a4e9a..d968cf7 100644 --- a/sound/soc/pxa/poodle.c +++ b/sound/soc/pxa/poodle.c @@ -85,17 +85,13 @@ static int poodle_startup(struct snd_pcm_substream *substream) } /* we need to unmute the HP at shutdown as the mute burns power on poodle */ -static int poodle_shutdown(struct snd_pcm_substream *substream) +static void poodle_shutdown(struct snd_pcm_substream *substream) { - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_codec *codec = rtd->socdev->codec; - /* set = unmute headphone */ locomo_gpio_write(&poodle_locomo_device.dev, POODLE_LOCOMO_GPIO_MUTE_L, 1); locomo_gpio_write(&poodle_locomo_device.dev, POODLE_LOCOMO_GPIO_MUTE_R, 1); - return 0; } static int poodle_hw_params(struct snd_pcm_substream *substream, @@ -232,7 +228,7 @@ static const struct soc_enum poodle_enum[] = { SOC_ENUM_SINGLE_EXT(2, spk_function), }; -static const snd_kcontrol_new_t wm8731_poodle_controls[] = { +static const struct snd_kcontrol_new wm8731_poodle_controls[] = { SOC_ENUM_EXT("Jack Function", poodle_enum[0], poodle_get_jack, poodle_set_jack), SOC_ENUM_EXT("Speaker Function", poodle_enum[1], poodle_get_spk, -- 1.5.6.3

3 36

[alsa-devel] WM9712 Not Giving output
by Nitin Mahajan 01 Aug '08

01 Aug '08

Hello! I am using a WM9712 codec chip with the AC97 controller on AMD AU1250. Linux kernel version 2.6.24.2. I have used the WM9712 codec driver from sound/soc/codecs. This I got after applying some patch available at wolfson website. The driver comes up, Identifies the codec chip etc. While I do a playback using aplay I cannot hear anything. I probed the pin 39 of the codec chip , but nothing is coming there, how ever on the SDATAOUT of the code chip I can see the signals while I do a playback. On AC97 controller's side, I can see the DMA happening on the host processor, interrupts also coming. On the mixer front, I did unmute and set the vol to max for PCM and Headphone. I did not find any Master control with this chip. Isn't there any master control with this chip? Can some one please throw more light on the Mixer part, specific to this chip. What Mixer controls do I need to set with what values for playback and capture respectively with this chip? Thanks in advance regards -Nitin Mahajan Send instant messages to your online friends http://uk.messenger.yahoo.com

3 5

[alsa-devel] pcm_lib.c: XRUN alsa-back-porting
by Timur Tabi 01 Aug '08

01 Aug '08

A customer is reporting that he's seeing this message every now and then, but when I try to examine the kernel source code, I don't see the source of it. In fact, when I do a google search of "alsa-back-porting", I get zero hits. So maybe the customer is using some older kernel, but when I scan the git change history for sound/core/pcm_lib.c, I still don't see it. So can someone tell me what "alsa-back-porting" means, and where it comes from? -- Timur Tabi Linux kernel developer at Freescale

2 1

Re: [alsa-devel] [PATCH] Support for Terrasoniq/MUSONIK TS22 PCI card
by Takashi Iwai 01 Aug '08

01 Aug '08

At Thu, 31 Jul 2008 14:40:45 -0400, Misha Zhilin wrote: > > Added support for Terrasoniq/MUSONIK TS22 PCI card. > > Signed-off-by: Misha Zhilin <misha(a)epiphan.com> Thanks, applied now. Takashi

1 0

[alsa-devel] [PATCH: alsa-utils] iecset update for new consumer status channel bits
by Pawel MOLL 01 Aug '08

01 Aug '08

Added iecset support for some of consumer status channel bits, new in the third edition od IEC60958-3 spec. Signed-off-by: Pawel Moll <pawel.moll(a)st.com> diff --git a/iecset/iecbits.c b/iecset/iecbits.c index 8c62749..84d439b 100644 --- a/iecset/iecbits.c +++ b/iecset/iecbits.c @@ -26,17 +26,39 @@ struct category_str { }; static struct category_str con_category[] = { + { IEC958_AES1_CON_GENERAL, "general" }, + + { IEC958_AES1_CON_IEC908_CD, "CD" }, + { IEC958_AES1_CON_NON_IEC908_CD, "non-IEC908 CD" }, + { IEC958_AES1_CON_MINI_DISC, "Mini-Disc" }, + { IEC958_AES1_CON_DVD, "DVD" }, + + { IEC958_AES1_CON_PCM_CODER, "PCM coder" }, + { IEC958_AES1_CON_MIXER, "digital signal mixer" }, + { IEC958_AES1_CON_RATE_CONVERTER, "rate converter" }, + { IEC958_AES1_CON_SAMPLER, "sampler" }, + { IEC958_AES1_CON_DSP, "digital sound processor" }, + { IEC958_AES1_CON_DAT, "DAT" }, { IEC958_AES1_CON_VCR, "VCR" }, - { IEC958_AES1_CON_MICROPHONE, "microphone" }, + { IEC958_AES1_CON_DCC, "DCC" }, + { IEC958_AES1_CON_MAGNETIC_DISC, "magnetic disc" }, + + { IEC958_AES1_CON_DAB_JAPAN, "digital audio broadcast (Japan)" }, + { IEC958_AES1_CON_DAB_EUROPE, "digital audio broadcast (Europe)" }, + { IEC958_AES1_CON_DAB_USA, "digital audio broadcast (USA)" }, + { IEC958_AES1_CON_SOFTWARE, "software delivery" }, + { IEC958_AES1_CON_SYNTHESIZER, "synthesizer" }, - { IEC958_AES1_CON_RATE_CONVERTER, "rate converter" }, - { IEC958_AES1_CON_MIXER, "mixer" }, - { IEC958_AES1_CON_SAMPLER, "sampler" }, - { IEC958_AES1_CON_PCM_CODER, "PCM coder" }, - { IEC958_AES1_CON_IEC908_CD, "CD" }, - { IEC958_AES1_CON_NON_IEC908_CD, "non-IEC908 CD" }, - { IEC958_AES1_CON_GENERAL, "general" }, + { IEC958_AES1_CON_MICROPHONE, "microphone" }, + + { IEC958_AES1_CON_ADC, "ADC without copyright information" }, + + { IEC958_AES1_CON_ADC_COPYRIGHT, "ADC with copyright information" }, + + { IEC958_AES1_CON_SOLIDMEM_DIGITAL_RECORDER_PLAYER, "flash memory recorder/player" }, + + { IEC958_AES1_CON_EXPERIMENTAL, "experimental" }, }; @@ -57,14 +79,38 @@ void dump_iec958(snd_aes_iec958_t *iec) } printf("Rate: "); switch (iec->status[3] & IEC958_AES3_CON_FS) { + case IEC958_AES3_CON_FS_22050: + printf("22050 Hz\n"); + break; + case IEC958_AES3_CON_FS_24000: + printf("24000 Hz\n"); + break; + case IEC958_AES3_CON_FS_32000: + printf("32000 Hz\n"); + break; case IEC958_AES3_CON_FS_44100: printf("44100 Hz\n"); break; case IEC958_AES3_CON_FS_48000: printf("48000 Hz\n"); break; - case IEC958_AES3_CON_FS_32000: - printf("32000 Hz\n"); + case IEC958_AES3_CON_FS_88200: + printf("88200 Hz\n"); + break; + case IEC958_AES3_CON_FS_96000: + printf("96000 Hz\n"); + break; + case IEC958_AES3_CON_FS_176400: + printf("176400 Hz\n"); + break; + case IEC958_AES3_CON_FS_192000: + printf("192000 Hz\n"); + break; + case IEC958_AES3_CON_FS_768000: + printf("768000 Hz\n"); + break; + case IEC958_AES3_CON_FS_NOTID: + printf("not indicated\n"); break; default: printf("unknown\n"); diff --git a/iecset/iecset.c b/iecset/iecset.c index a2fe4d1..44c43ab 100644 --- a/iecset/iecset.c +++ b/iecset/iecset.c @@ -58,7 +58,7 @@ static struct cmdtbl cmds[] = { { "aud", IDX_NOAUDIO, CMD_BOOL_INV, "audio (common)\n\ton = audio mode, off = non-audio mode" }, { "rat", IDX_RATE, CMD_INT, - "rate (common)\n\tsample rate in Hz" }, + "rate (common)\n\tsample rate in Hz (0 = not indicated)" }, { "emp", IDX_EMP, CMD_INT, "emphasis (common)\n\t0 = none, 1 = 50/15us, 2 = CCITT" }, { "loc", IDX_UNLOCK, CMD_BOOL_INV, @@ -194,14 +194,38 @@ static int update_iec958_status(snd_aes_iec958_t *iec958, int *parms) } else { iec958->status[3] &= ~IEC958_AES3_CON_FS; switch (parms[IDX_RATE]) { + case 22050: + iec958->status[3] |= IEC958_AES3_CON_FS_22050; + break; + case 24000: + iec958->status[3] |= IEC958_AES3_CON_FS_24000; + break; + case 32000: + iec958->status[3] |= IEC958_AES3_CON_FS_32000; + break; case 44100: iec958->status[3] |= IEC958_AES3_CON_FS_44100; break; case 48000: iec958->status[3] |= IEC958_AES3_CON_FS_48000; break; - case 32000: - iec958->status[3] |= IEC958_AES3_CON_FS_32000; + case 88200: + iec958->status[3] |= IEC958_AES3_CON_FS_88200;; + break; + case 96000: + iec958->status[3] |= IEC958_AES3_CON_FS_96000; + break; + case 176400: + iec958->status[3] |= IEC958_AES3_CON_FS_176400; + break; + case 192000: + iec958->status[3] |= IEC958_AES3_CON_FS_192000; + break; + case 768000: + iec958->status[3] |= IEC958_AES3_CON_FS_768000; + break; + default: + iec958->status[3] |= IEC958_AES3_CON_FS_NOTID; break; } } -- 1.5.5.1

1 0

[alsa-devel] [PATCH: alsa-lib] IEC958 definition for consumer status channel update
by Pawel MOLL 01 Aug '08

01 Aug '08

Updated IEC958 consumer status channel definitions according to the third edition of IEC60958-3 spec. Signed-off-by: Pawel Moll <pawel.moll(a)st.com> diff --git a/include/asoundef.h b/include/asoundef.h index e780c65..c6c4eec 100644 --- a/include/asoundef.h +++ b/include/asoundef.h @@ -69,35 +69,56 @@ extern "C" { #define IEC958_AES1_PRO_USERBITS_UDEF (12<<4) /**< user defined application */ #define IEC958_AES1_CON_CATEGORY 0x7f /**< consumer category */ #define IEC958_AES1_CON_GENERAL 0x00 /**< general category */ -#define IEC958_AES1_CON_EXPERIMENTAL 0x40 /**< experimental category */ -#define IEC958_AES1_CON_SOLIDMEM_MASK 0x0f /**< ??? */ -#define IEC958_AES1_CON_SOLIDMEM_ID 0x08 /**< ??? */ -#define IEC958_AES1_CON_BROADCAST1_MASK 0x07 /**< ??? */ -#define IEC958_AES1_CON_BROADCAST1_ID 0x04 /**< ??? */ -#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07 /**< digital<->digital converter mask */ -#define IEC958_AES1_CON_DIGDIGCONV_ID 0x02 /**< digital<->digital converter id */ -#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f /**< ADC Copyright mask */ -#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x06 /**< ADC Copyright ID */ -#define IEC958_AES1_CON_ADC_MASK 0x1f /**< ADC Mask */ -#define IEC958_AES1_CON_ADC_ID 0x16 /**< ADC ID */ -#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f /**< Broadcast mask */ -#define IEC958_AES1_CON_BROADCAST2_ID 0x0e /**< Broadcast ID */ #define IEC958_AES1_CON_LASEROPT_MASK 0x07 /**< Laser-optical mask */ #define IEC958_AES1_CON_LASEROPT_ID 0x01 /**< Laser-optical ID */ -#define IEC958_AES1_CON_MUSICAL_MASK 0x07 /**< Musical device mask */ -#define IEC958_AES1_CON_MUSICAL_ID 0x05 /**< Musical device ID */ -#define IEC958_AES1_CON_MAGNETIC_MASK 0x07 /**< Magnetic device mask */ -#define IEC958_AES1_CON_MAGNETIC_ID 0x03 /**< Magnetic device ID */ #define IEC958_AES1_CON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x00) /**< IEC958 CD compatible device */ #define IEC958_AES1_CON_NON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x08) /**< non-IEC958 CD compatible device */ +#define IEC958_AES1_CON_MINI_DISC (IEC958_AES1_CON_LASEROPT_ID|0x48) /**< Mini-Disc device */ +#define IEC958_AES1_CON_DVD (IEC958_AES1_CON_LASEROPT_ID|0x18) /**< DVD device */ +#define IEC958_AES1_CON_LASTEROPT_OTHER (IEC958_AES1_CON_LASEROPT_ID|0x78) /**< Other laser-optical product */ +#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07 /**< digital<->digital converter mask */ +#define IEC958_AES1_CON_DIGDIGCONV_ID 0x02 /**< digital<->digital converter id */ #define IEC958_AES1_CON_PCM_CODER (IEC958_AES1_CON_DIGDIGCONV_ID|0x00) /**< PCM coder */ -#define IEC958_AES1_CON_SAMPLER (IEC958_AES1_CON_DIGDIGCONV_ID|0x20) /**< PCM sampler */ -#define IEC958_AES1_CON_MIXER (IEC958_AES1_CON_DIGDIGCONV_ID|0x10) /**< Mixer */ +#define IEC958_AES1_CON_MIXER (IEC958_AES1_CON_DIGDIGCONV_ID|0x10) /**< Digital signal mixer */ #define IEC958_AES1_CON_RATE_CONVERTER (IEC958_AES1_CON_DIGDIGCONV_ID|0x18) /**< Rate converter */ -#define IEC958_AES1_CON_SYNTHESIZER (IEC958_AES1_CON_MUSICAL_ID|0x00) /**< Synthesizer */ -#define IEC958_AES1_CON_MICROPHONE (IEC958_AES1_CON_MUSICAL_ID|0x08) /**< Microphone */ +#define IEC958_AES1_CON_SAMPLER (IEC958_AES1_CON_DIGDIGCONV_ID|0x20) /**< PCM sampler */ +#define IEC958_AES1_CON_DSP (IEC958_AES1_CON_DIGDIGCONV_ID|0x28) /**< Digital sound processor */ +#define IEC958_AES1_CON_DIGDIGCONV_OTHER (IEC958_AES1_CON_DIGDIGCONV_ID|0x78) /**< Other digital<->digital product */ +#define IEC958_AES1_CON_MAGNETIC_MASK 0x07 /**< Magnetic device mask */ +#define IEC958_AES1_CON_MAGNETIC_ID 0x03 /**< Magnetic device ID */ #define IEC958_AES1_CON_DAT (IEC958_AES1_CON_MAGNETIC_ID|0x00) /**< Digital Audio Tape */ #define IEC958_AES1_CON_VCR (IEC958_AES1_CON_MAGNETIC_ID|0x08) /**< Video recorder */ +#define IEC958_AES1_CON_DCC (IEC958_AES1_CON_MAGNETIC_ID|0x40) /**< Digital compact cassette */ +#define IEC958_AES1_CON_MAGNETIC_DISC (IEC958_AES1_CON_MAGNETIC_ID|0x18) /**< Magnetic disc digital audio device */ +#define IEC958_AES1_CON_MAGNETIC_OTHER (IEC958_AES1_CON_MAGNETIC_ID|0x78) /**< Other magnetic device */ +#define IEC958_AES1_CON_BROADCAST1_MASK 0x07 /**< Broadcast mask */ +#define IEC958_AES1_CON_BROADCAST1_ID 0x04 /**< Broadcast ID */ +#define IEC958_AES1_CON_DAB_JAPAN (IEC958_AES1_CON_BROADCAST1_ID|0x00) /**< Digital audio broadcast (Japan) */ +#define IEC958_AES1_CON_DAB_EUROPE (IEC958_AES1_CON_BROADCAST1_ID|0x08) /**< Digital audio broadcast (Europe) */ +#define IEC958_AES1_CON_DAB_USA (IEC958_AES1_CON_BROADCAST1_ID|0x60) /**< Digital audio broadcast (USA) */ +#define IEC958_AES1_CON_SOFTWARE (IEC958_AES1_CON_BROADCAST1_ID|0x40) /**< Electronic software delivery */ +#define IEC958_AES1_CON_IEC62105 (IEC958_AES1_CON_BROADCAST1_ID|0x20) /**< Used by another standard (IEC 62105) */ +#define IEC958_AES1_CON_BROADCAST1_OTHER (IEC958_AES1_CON_BROADCAST1_ID|0x78) /**< Other broadcast product */ +#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f /**< Broadcast alternative mask */ +#define IEC958_AES1_CON_BROADCAST2_ID 0x0e /**< Broadcast alternative ID */ +#define IEC958_AES1_CON_MUSICAL_MASK 0x07 /**< Musical device mask */ +#define IEC958_AES1_CON_MUSICAL_ID 0x05 /**< Musical device ID */ +#define IEC958_AES1_CON_SYNTHESIZER (IEC958_AES1_CON_MUSICAL_ID|0x00) /**< Synthesizer */ +#define IEC958_AES1_CON_MICROPHONE (IEC958_AES1_CON_MUSICAL_ID|0x08) /**< Microphone */ +#define IEC958_AES1_CON_MUSICAL_OTHER (IEC958_AES1_CON_MUSICAL_ID|0x78) /**< Other musical device */ +#define IEC958_AES1_CON_ADC_MASK 0x1f /**< ADC Mask */ +#define IEC958_AES1_CON_ADC_ID 0x06 /**< ADC ID */ +#define IEC958_AES1_CON_ADC (IEC958_AES1_CON_ADC_ID|0x00) /**< ADC without copyright information */ +#define IEC958_AES1_CON_ADC_OTHER (IEC958_AES1_CON_ADC_ID|0x60) /**< Other ADC product (with no copyright information) */ +#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f /**< ADC Copyright mask */ +#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x16 /**< ADC Copyright ID */ +#define IEC958_AES1_CON_ADC_COPYRIGHT (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x00) /**< ADC with copyright information */ +#define IEC958_AES1_CON_ADC_COPYRIGHT_OTHER (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x60) /**< Other ADC with copyright information product */ +#define IEC958_AES1_CON_SOLIDMEM_MASK 0x0f /**< Solid memory based products mask */ +#define IEC958_AES1_CON_SOLIDMEM_ID 0x08 /**< Solid memory based products ID */ +#define IEC958_AES1_CON_SOLIDMEM_DIGITAL_RECORDER_PLAYER (IEC958_AES1_CON_SOLIDMEM_ID|0x00) /**< Digital audio recorder and player using solid state memory */ +#define IEC958_AES1_CON_SOLIDMEM_OTHER (IEC958_AES1_CON_SOLIDMEM_ID|0x70) /**< Other solid state memory based product */ +#define IEC958_AES1_CON_EXPERIMENTAL 0x40 /**< experimental category */ #define IEC958_AES1_CON_ORIGINAL (1<<7) /**< this bits depends on the category code */ #define IEC958_AES2_PRO_SBITS (7<<0) /**< mask - sample bits */ #define IEC958_AES2_PRO_SBITS_20 (2<<0) /**< 20-bit - coordination */ @@ -115,8 +136,16 @@ extern "C" { #define IEC958_AES2_CON_CHANNEL_UNSPEC (0<<4) /**< channel number unspecified */ #define IEC958_AES3_CON_FS (15<<0) /**< mask - sample frequency */ #define IEC958_AES3_CON_FS_44100 (0<<0) /**< 44.1kHz */ +#define IEC958_AES3_CON_FS_NOTID (1<<0) /**< sample frequency non indicated */ #define IEC958_AES3_CON_FS_48000 (2<<0) /**< 48kHz */ #define IEC958_AES3_CON_FS_32000 (3<<0) /**< 32kHz */ +#define IEC958_AES3_CON_FS_22050 (4<<0) /**< 22.05kHz */ +#define IEC958_AES3_CON_FS_24000 (6<<0) /**< 24kHz */ +#define IEC958_AES3_CON_FS_88200 (8<<0) /**< 88.2kHz */ +#define IEC958_AES3_CON_FS_768000 (9<<0) /**< 768kHz */ +#define IEC958_AES3_CON_FS_96000 (10<<0) /**< 96kHz */ +#define IEC958_AES3_CON_FS_176400 (12<<0) /**< 176.4kHz */ +#define IEC958_AES3_CON_FS_192000 (14<<0) /**< 192kHz */ #define IEC958_AES3_CON_CLOCK (3<<4) /**< mask - clock accuracy */ #define IEC958_AES3_CON_CLOCK_1000PPM (0<<4) /**< 1000 ppm */ #define IEC958_AES3_CON_CLOCK_50PPM (1<<4) /**< 50 ppm */ @@ -129,6 +158,26 @@ extern "C" { #define IEC958_AES4_CON_WORDLEN_23_19 (4<<1) /**< 23-bit or 19-bit */ #define IEC958_AES4_CON_WORDLEN_24_20 (5<<1) /**< 24-bit or 20-bit */ #define IEC958_AES4_CON_WORDLEN_21_17 (6<<1) /**< 21-bit or 17-bit */ +#define IEC958_AES4_CON_ORIGFS (15<<4) /**< mask - original sample frequency */ +#define IEC958_AES4_CON_ORIGFS_NOTID (0<<4) /**< original sample frequency not indicated */ +#define IEC958_AES4_CON_ORIGFS_192000 (1<<4) /**< 192kHz */ +#define IEC958_AES4_CON_ORIGFS_12000 (2<<4) /**< 12kHz */ +#define IEC958_AES4_CON_ORIGFS_176400 (3<<4) /**< 176.4kHz */ +#define IEC958_AES4_CON_ORIGFS_96000 (5<<4) /**< 96kHz */ +#define IEC958_AES4_CON_ORIGFS_8000 (6<<4) /**< 8kHz */ +#define IEC958_AES4_CON_ORIGFS_88200 (7<<4) /**< 88.2kHz */ +#define IEC958_AES4_CON_ORIGFS_16000 (8<<4) /**< 16kHz */ +#define IEC958_AES4_CON_ORIGFS_24000 (9<<4) /**< 24kHz */ +#define IEC958_AES4_CON_ORIGFS_11025 (10<<4) /**< 11.025kHz */ +#define IEC958_AES4_CON_ORIGFS_22050 (11<<4) /**< 22.05kHz */ +#define IEC958_AES4_CON_ORIGFS_32000 (12<<4) /**< 32kHz */ +#define IEC958_AES4_CON_ORIGFS_48000 (13<<4) /**< 48kHz */ +#define IEC958_AES4_CON_ORIGFS_44100 (15<<4) /**< 44.1kHz */ +#define IEC958_AES5_CON_CGMSA (3<<0) /**< mask - CGMS-A */ +#define IEC958_AES5_CON_CGMSA_COPYFREELY (0<<0) /**< copying is permitted without restriction */ +#define IEC958_AES5_CON_CGMSA_COPYONCE (1<<0) /**< one generation of copies may be made */ +#define IEC958_AES5_CON_CGMSA_COPYNOMORE (2<<0) /**< condition not be used */ +#define IEC958_AES5_CON_CGMSA_COPYNEVER (3<<0) /**< no copying is permitted */ /** \} */ -- 1.5.5.1

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[alsa-devel] [PATCH: alsa-kernel] ALSA: IEC958 definition for consumer status channel update
by Pawel MOLL 01 Aug '08

01 Aug '08

Updated IEC958 consumer status channel definitions according to the third edition of IEC60958-3 spec. Signed-off-by: Pawel Moll <pawel.moll(a)st.com> diff --git a/include/sound/asoundef.h b/include/sound/asoundef.h index a6e0fac..20ebf32 100644 --- a/include/sound/asoundef.h +++ b/include/sound/asoundef.h @@ -60,35 +60,56 @@ #define IEC958_AES1_PRO_USERBITS_UDEF (12<<4) /* user defined application */ #define IEC958_AES1_CON_CATEGORY 0x7f #define IEC958_AES1_CON_GENERAL 0x00 -#define IEC958_AES1_CON_EXPERIMENTAL 0x40 -#define IEC958_AES1_CON_SOLIDMEM_MASK 0x0f -#define IEC958_AES1_CON_SOLIDMEM_ID 0x08 -#define IEC958_AES1_CON_BROADCAST1_MASK 0x07 -#define IEC958_AES1_CON_BROADCAST1_ID 0x04 -#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07 -#define IEC958_AES1_CON_DIGDIGCONV_ID 0x02 -#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f -#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x06 -#define IEC958_AES1_CON_ADC_MASK 0x1f -#define IEC958_AES1_CON_ADC_ID 0x16 -#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f -#define IEC958_AES1_CON_BROADCAST2_ID 0x0e #define IEC958_AES1_CON_LASEROPT_MASK 0x07 #define IEC958_AES1_CON_LASEROPT_ID 0x01 -#define IEC958_AES1_CON_MUSICAL_MASK 0x07 -#define IEC958_AES1_CON_MUSICAL_ID 0x05 -#define IEC958_AES1_CON_MAGNETIC_MASK 0x07 -#define IEC958_AES1_CON_MAGNETIC_ID 0x03 #define IEC958_AES1_CON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x00) #define IEC958_AES1_CON_NON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x08) +#define IEC958_AES1_CON_MINI_DISC (IEC958_AES1_CON_LASEROPT_ID|0x48) +#define IEC958_AES1_CON_DVD (IEC958_AES1_CON_LASEROPT_ID|0x18) +#define IEC958_AES1_CON_LASTEROPT_OTHER (IEC958_AES1_CON_LASEROPT_ID|0x78) +#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07 +#define IEC958_AES1_CON_DIGDIGCONV_ID 0x02 #define IEC958_AES1_CON_PCM_CODER (IEC958_AES1_CON_DIGDIGCONV_ID|0x00) -#define IEC958_AES1_CON_SAMPLER (IEC958_AES1_CON_DIGDIGCONV_ID|0x20) #define IEC958_AES1_CON_MIXER (IEC958_AES1_CON_DIGDIGCONV_ID|0x10) #define IEC958_AES1_CON_RATE_CONVERTER (IEC958_AES1_CON_DIGDIGCONV_ID|0x18) -#define IEC958_AES1_CON_SYNTHESIZER (IEC958_AES1_CON_MUSICAL_ID|0x00) -#define IEC958_AES1_CON_MICROPHONE (IEC958_AES1_CON_MUSICAL_ID|0x08) +#define IEC958_AES1_CON_SAMPLER (IEC958_AES1_CON_DIGDIGCONV_ID|0x20) +#define IEC958_AES1_CON_DSP (IEC958_AES1_CON_DIGDIGCONV_ID|0x28) +#define IEC958_AES1_CON_DIGDIGCONV_OTHER (IEC958_AES1_CON_DIGDIGCONV_ID|0x78) +#define IEC958_AES1_CON_MAGNETIC_MASK 0x07 +#define IEC958_AES1_CON_MAGNETIC_ID 0x03 #define IEC958_AES1_CON_DAT (IEC958_AES1_CON_MAGNETIC_ID|0x00) #define IEC958_AES1_CON_VCR (IEC958_AES1_CON_MAGNETIC_ID|0x08) +#define IEC958_AES1_CON_DCC (IEC958_AES1_CON_MAGNETIC_ID|0x40) +#define IEC958_AES1_CON_MAGNETIC_DISC (IEC958_AES1_CON_MAGNETIC_ID|0x18) +#define IEC958_AES1_CON_MAGNETIC_OTHER (IEC958_AES1_CON_MAGNETIC_ID|0x78) +#define IEC958_AES1_CON_BROADCAST1_MASK 0x07 +#define IEC958_AES1_CON_BROADCAST1_ID 0x04 +#define IEC958_AES1_CON_DAB_JAPAN (IEC958_AES1_CON_BROADCAST1_ID|0x00) +#define IEC958_AES1_CON_DAB_EUROPE (IEC958_AES1_CON_BROADCAST1_ID|0x08) +#define IEC958_AES1_CON_DAB_USA (IEC958_AES1_CON_BROADCAST1_ID|0x60) +#define IEC958_AES1_CON_SOFTWARE (IEC958_AES1_CON_BROADCAST1_ID|0x40) +#define IEC958_AES1_CON_IEC62105 (IEC958_AES1_CON_BROADCAST1_ID|0x20) +#define IEC958_AES1_CON_BROADCAST1_OTHER (IEC958_AES1_CON_BROADCAST1_ID|0x78) +#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f +#define IEC958_AES1_CON_BROADCAST2_ID 0x0e +#define IEC958_AES1_CON_MUSICAL_MASK 0x07 +#define IEC958_AES1_CON_MUSICAL_ID 0x05 +#define IEC958_AES1_CON_SYNTHESIZER (IEC958_AES1_CON_MUSICAL_ID|0x00) +#define IEC958_AES1_CON_MICROPHONE (IEC958_AES1_CON_MUSICAL_ID|0x08) +#define IEC958_AES1_CON_MUSICAL_OTHER (IEC958_AES1_CON_MUSICAL_ID|0x78) +#define IEC958_AES1_CON_ADC_MASK 0x1f +#define IEC958_AES1_CON_ADC_ID 0x06 +#define IEC958_AES1_CON_ADC (IEC958_AES1_CON_ADC_ID|0x00) +#define IEC958_AES1_CON_ADC_OTHER (IEC958_AES1_CON_ADC_ID|0x60) +#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f +#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x16 +#define IEC958_AES1_CON_ADC_COPYRIGHT (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x00) +#define IEC958_AES1_CON_ADC_COPYRIGHT_OTHER (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x60) +#define IEC958_AES1_CON_SOLIDMEM_MASK 0x0f +#define IEC958_AES1_CON_SOLIDMEM_ID 0x08 +#define IEC958_AES1_CON_SOLIDMEM_DIGITAL_RECORDER_PLAYER (IEC958_AES1_CON_SOLIDMEM_ID|0x00) +#define IEC958_AES1_CON_SOLIDMEM_OTHER (IEC958_AES1_CON_SOLIDMEM_ID|0x70) +#define IEC958_AES1_CON_EXPERIMENTAL 0x40 #define IEC958_AES1_CON_ORIGINAL (1<<7) /* this bits depends on the category code */ #define IEC958_AES2_PRO_SBITS (7<<0) /* mask - sample bits */ #define IEC958_AES2_PRO_SBITS_20 (2<<0) /* 20-bit - coordination */ @@ -106,8 +127,16 @@ #define IEC958_AES2_CON_CHANNEL_UNSPEC (0<<4) /* unspecified */ #define IEC958_AES3_CON_FS (15<<0) /* mask - sample frequency */ #define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */ +#define IEC958_AES3_CON_FS_NOTID (1<<0) /* non indicated */ #define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */ #define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */ +#define IEC958_AES3_CON_FS_22050 (4<<0) /* 22.05kHz */ +#define IEC958_AES3_CON_FS_24000 (6<<0) /* 24kHz */ +#define IEC958_AES3_CON_FS_88200 (8<<0) /* 88.2kHz */ +#define IEC958_AES3_CON_FS_768000 (9<<0) /* 768kHz */ +#define IEC958_AES3_CON_FS_96000 (10<<0) /* 96kHz */ +#define IEC958_AES3_CON_FS_176400 (12<<0) /* 176.4kHz */ +#define IEC958_AES3_CON_FS_192000 (14<<0) /* 192kHz */ #define IEC958_AES3_CON_CLOCK (3<<4) /* mask - clock accuracy */ #define IEC958_AES3_CON_CLOCK_1000PPM (0<<4) /* 1000 ppm */ #define IEC958_AES3_CON_CLOCK_50PPM (1<<4) /* 50 ppm */ @@ -120,6 +149,26 @@ #define IEC958_AES4_CON_WORDLEN_23_19 (4<<1) /* 23-bit or 19-bit */ #define IEC958_AES4_CON_WORDLEN_24_20 (5<<1) /* 24-bit or 20-bit */ #define IEC958_AES4_CON_WORDLEN_21_17 (6<<1) /* 21-bit or 17-bit */ +#define IEC958_AES4_CON_ORIGFS (15<<4) /* mask - original sample frequency */ +#define IEC958_AES4_CON_ORIGFS_NOTID (0<<4) /* not indicated */ +#define IEC958_AES4_CON_ORIGFS_192000 (1<<4) /* 192kHz */ +#define IEC958_AES4_CON_ORIGFS_12000 (2<<4) /* 12kHz */ +#define IEC958_AES4_CON_ORIGFS_176400 (3<<4) /* 176.4kHz */ +#define IEC958_AES4_CON_ORIGFS_96000 (5<<4) /* 96kHz */ +#define IEC958_AES4_CON_ORIGFS_8000 (6<<4) /* 8kHz */ +#define IEC958_AES4_CON_ORIGFS_88200 (7<<4) /* 88.2kHz */ +#define IEC958_AES4_CON_ORIGFS_16000 (8<<4) /* 16kHz */ +#define IEC958_AES4_CON_ORIGFS_24000 (9<<4) /* 24kHz */ +#define IEC958_AES4_CON_ORIGFS_11025 (10<<4) /* 11.025kHz */ +#define IEC958_AES4_CON_ORIGFS_22050 (11<<4) /* 22.05kHz */ +#define IEC958_AES4_CON_ORIGFS_32000 (12<<4) /* 32kHz */ +#define IEC958_AES4_CON_ORIGFS_48000 (13<<4) /* 48kHz */ +#define IEC958_AES4_CON_ORIGFS_44100 (15<<4) /* 44.1kHz */ +#define IEC958_AES5_CON_CGMSA (3<<0) /* mask - CGMS-A */ +#define IEC958_AES5_CON_CGMSA_COPYFREELY (0<<0) /* copying is permitted without restriction */ +#define IEC958_AES5_CON_CGMSA_COPYONCE (1<<0) /* one generation of copies may be made */ +#define IEC958_AES5_CON_CGMSA_COPYNOMORE (2<<0) /* condition not be used */ +#define IEC958_AES5_CON_CGMSA_COPYNEVER (3<<0) /* no copying is permitted */ /***************************************************************************** * * -- 1.5.5.1

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Re: [alsa-devel] [Fwd: [Alsa-user] Intel Poulsbo(SCH) chipset does not recognize Adi 1986 codec under linux]]
by Kan-I Jyo 01 Aug '08

01 Aug '08

Dear list, My original mail on this topic was posted to the alsa-user list, while I was informed that this alsa-devel list would be the right place to post. The problem I had encountered is that the Adi 1986 codec chip on my device with Poulsbo(SCH) chipset could not be recognized by the snd_hda_intel driver module. Tobin has kindly given me an advice on trying an ALSA driver that is later than 1.0.16.final. For a cross-test pupose, I have tried both the following 1.0.16 and the latest 1.0.17-rc2. [1.0.16] ftp://ftp.alsa-project.org/pub/driver/alsa-driver-1.0.16.tar.bz2 [1.0.17-rc2] ftp://ftp.alsa-project.org/pub/driver/alsa-driver-1.0.17rc2.tar.bz2 By following the guide described in the INSTALL text file in both the above two packages, I have done make and make install without a problem. Unfortunately, both these two version of ALSA driver does not recognized the Adi 1986 codec and in the dmesg output claiming that "no codecs found!". <dmesg> -- snip -- ACPI: PCI Interrupt 0000:00:1b.0[A] -> GSI 16 (level, low) -> IRQ 17 PCI: Setting latency timer of device 0000:00:1b.0 to 64 ALSA /root/alsa-driver-1.0.16/pci/hda/../../alsa-kernel/pci/hda/hda_intel.c:1887: hda-intel: no codecs found! ACPI: PCI interrupt for device 0000:00:1b.0 disabled ACPI: PCI Interrupt 0000:00:1b.0[A] -> GSI 16 (level, low) -> IRQ 17 PCI: Setting latency timer of device 0000:00:1b.0 to 64 ALSA /root/alsa-driver-1.0.17rc2/pci/hda/../../alsa-kernel/pci/hda/hda_intel.c:2142: hda-intel: no codecs found! ACPI: PCI interrupt for device 0000:00:1b.0 disabled -- snip -- I have also tried applying some module parameters like probe_mask and position_fix but with no luck. Actually, we have two machines with Poulsbo(SCH) chipset inside. The ALSA driver works fine in one(with a chipset's revision of "04") while it does not work on the other (with a chipset's revision of "06"). Here I attach the "lspci -nnvvvxxxx" result from both two machines. Any comment would be greatly appericiated. If anyone needs more information, please let me know. ---------- Forwarded message ---------- 2008/6/24 stan <ghjeold_i_mwee(a)cox.net>: > This is a response from the alsa-devel list. I forwarded your message there > as that was the more appropriate list. > > > Not sure what version of alsa driver you are using, but the driver for that > chipset was added prior to 1.0.16 final. Anything after that should work. > > Tobin > > On Mon, 2008-06-23 at 06:20 -0700, stan wrote: > > Sent to wrong list. > > email message attachment ([Alsa-user] Intel Poulsbo(SCH) chipset does not > recognize Adi 1986 codec under linux.eml) > > -------- Forwarded Message -------- > From: Kan-I Jyo <cecilhsujp(a)gmail.com> > To: alsa-user(a)lists.sourceforge.net > Subject: [Alsa-user] Intel Poulsbo(SCH) chipset does not recognize Adi 1986 > codec under linux > Date: Mon, 23 Jun 2008 20:53:42 +0900 > > Dear list, > > I have recently got a device with Intel's Poulsbo chipset and Adi 1986 > codec attatched. > > The Adi 1986 codec along with the Poulsbo chipset could been > recognized by installing the SoundMAX driver under Windows XP. > > While switching to Linux, the snd_intel_hda is loaded but the Adi 1986 > codec could not been seen and there is no "codec#0" entry under > /proc/asound/card0. > > >From what I can see from dmesg, the hda_intel module had complained > about "no codecs found!". > > <dmesg.txt> > -- snip -- > [ 93.463277] PCI: Setting latency timer of device 0000:00:1b.0 to 64 > [ 93.463286] Do fixup for Poulsbo <6>D0 or newer stepping > [ 93.463439] HDA snoop disabled, try to enable ... OK > [ 93.491624] hda-intel: no codecs found! > -- snip -- > > I have attached both output of dmesg command the "lspci -nnvvvxxx" > result along with this mail. Any comment would be greatly appreciated. > > ------------------------------------------------------------------------- > Check out the new SourceForge.net Marketplace. > It's the best place to buy or sell services for > just about anything Open Source. > http://sourceforge.net/services/buy/index.php > _______________________________________________ Alsa-user mailing list > Alsa-user(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/alsa-user > > _______________________________________________ Alsa-devel mailing list > Alsa-devel(a)alsa-project.org > http://mailman.alsa-project.org/mailman/listinfo/alsa-devel > > -- Tobin Davis > > 22. The only copy of Norton Utilities was on THAT disk??? > > --Top 100 things you don't want the sysadmin to say > > -- Sincerely, Jyo

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[alsa-devel] snd_pcm_sw_params_set_xfer_align replacement?
by Aaron J. Grier 01 Aug '08

01 Aug '08

snd_pcm_sw_params_set_xfer_align() has been deprecated but the docs don't mention what it was replaced with. I don't ever want or need partial reads and writes -- my app would actually be happiest being completely synchronous to the hardware with fixed-size buffers. any suggestions how to get ALSA to do this? -- Aaron J. Grier | "Not your ordinary poofy goof." | agrier(a)poofygoof.com

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