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[alsa-devel] [PATCH 1/5] ARM: DaVinci: ASoC: Add mcasp support for DM646x
by Naresh Medisetty 02 Apr '09

02 Apr '09

Adds driver support for the two instances of McASP on TI's DM646x. The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio application. (http://www.ti.com/litv/pdf/spruer1b). There are two instances of McASP on DM646x. The McASP0 module includes up to 4 serializers that can be individually enabled to either transmit or receive in different modes. The McASP1 module is limited with only 1 pinned-out serializer that can be enabled to only transmit in DIT mode (neither receiving in any mode nor transmitting in either Burst or TDM mode is supported). The codec on the DM646x EVM is AIC32 which is connected to Serializer0 and Serializer1 of McASP0. The McASP0 consists of transmit and receive sections that may operate synchronized, or completely independently with separate master clocks, bit clocks, and frame syncs, and using different transmit modes with different bit-stream formats. Signed-off-by: Naresh Medisetty <naresh(a)ti.com> --- This patch applies against ALSA mainline - that's the topic/asoc branch of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6.git sound/soc/davinci/Kconfig | 12 + sound/soc/davinci/Makefile | 3 + sound/soc/davinci/davinci-i2s-mcasp.c | 877 +++++++++++++++++++++++++++++++++ sound/soc/davinci/davinci-i2s-mcasp.h | 56 +++ sound/soc/davinci/davinci-pcm.h | 17 +- 5 files changed, 957 insertions(+), 8 deletions(-) create mode 100644 sound/soc/davinci/davinci-i2s-mcasp.c create mode 100644 sound/soc/davinci/davinci-i2s-mcasp.h diff --git a/sound/soc/davinci/Kconfig b/sound/soc/davinci/Kconfig index bd7392c..7f35baa 100644 --- a/sound/soc/davinci/Kconfig +++ b/sound/soc/davinci/Kconfig @@ -9,6 +9,9 @@ config SND_DAVINCI_SOC config SND_DAVINCI_SOC_I2S tristate +config SND_DAVINCI_SOC_I2S_MCASP + tristate + config SND_DAVINCI_SOC_EVM tristate "SoC Audio support for DaVinci EVM" depends on SND_DAVINCI_SOC && MACH_DAVINCI_EVM @@ -18,6 +21,15 @@ config SND_DAVINCI_SOC_EVM Say Y if you want to add support for SoC audio on TI DaVinci EVM platform. +config SND_DM6467_SOC_EVM + tristate "SoC Audio support for DaVinci DM6467 EVM" + depends on SND_DAVINCI_SOC && MACH_DAVINCI_DM6467_EVM + select SND_DAVINCI_SOC_I2S_MCASP + select SND_SOC_TLV320AIC3X + help + Say Y if you want to add support for SoC audio on TI + DaVinci DM6467 EVM platform. + config SND_DAVINCI_SOC_SFFSDR tristate "SoC Audio support for SFFSDR" depends on SND_DAVINCI_SOC && MACH_SFFSDR diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile index ca8bae1..152d59c 100644 --- a/sound/soc/davinci/Makefile +++ b/sound/soc/davinci/Makefile @@ -1,13 +1,16 @@ # DAVINCI Platform Support snd-soc-davinci-objs := davinci-pcm.o snd-soc-davinci-i2s-objs := davinci-i2s.o +snd-soc-davinci-i2s-mcasp-objs:= davinci-i2s-mcasp.o obj-$(CONFIG_SND_DAVINCI_SOC) += snd-soc-davinci.o obj-$(CONFIG_SND_DAVINCI_SOC_I2S) += snd-soc-davinci-i2s.o +obj-$(CONFIG_SND_DAVINCI_SOC_I2S_MCASP) += snd-soc-davinci-i2s-mcasp.o # DAVINCI Machine Support snd-soc-evm-objs := davinci-evm.o snd-soc-sffsdr-objs := davinci-sffsdr.o obj-$(CONFIG_SND_DAVINCI_SOC_EVM) += snd-soc-evm.o +obj-$(CONFIG_SND_DM6467_SOC_EVM) += snd-soc-evm.o obj-$(CONFIG_SND_DAVINCI_SOC_SFFSDR) += snd-soc-sffsdr.o diff --git a/sound/soc/davinci/davinci-i2s-mcasp.c b/sound/soc/davinci/davinci-i2s-mcasp.c new file mode 100644 index 0000000..6a8d520 --- /dev/null +++ b/sound/soc/davinci/davinci-i2s-mcasp.c @@ -0,0 +1,877 @@ +/* + * ALSA SoC I2S (McASP) Audio Layer for TI DAVINCI processor + * + * Author: Nirmal Pandey <n-pandey(a)ti.com>, + * Suresh Rajashekara <suresh.r(a)ti.com> + * Steve Chen, <schen@.mvista.com> + * + * Copyright: (C) 2008 MontaVista Software, Inc., <source(a)mvista.com> + * Copyright: (C) 2008 Texas Instruments, India + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/initval.h> +#include <sound/soc.h> + +#include "davinci-pcm.h" +#include "davinci-i2s-mcasp.h" + +/* + * McASP register definitions + */ +#define DAVINCI_MCASP_PID_REG 0x00 +#define DAVINCI_MCASP_PWREMUMGT_REG 0x04 + +#define DAVINCI_MCASP_PFUNC_REG 0x10 +#define DAVINCI_MCASP_PDIR_REG 0x14 +#define DAVINCI_MCASP_PDOUT_REG 0x18 +#define DAVINCI_MCASP_PDSET_REG 0x1c + +#define DAVINCI_MCASP_PDCLR_REG 0x20 + +#define DAVINCI_MCASP_TLGC_REG 0x30 +#define DAVINCI_MCASP_TLMR_REG 0x34 + +#define DAVINCI_MCASP_GBLCTL_REG 0x44 +#define DAVINCI_MCASP_AMUTE_REG 0x48 +#define DAVINCI_MCASP_LBCTL_REG 0x4c + +#define DAVINCI_MCASP_TXDITCTL_REG 0x50 + +#define DAVINCI_MCASP_GBLCTLR_REG 0x60 +#define DAVINCI_MCASP_RXMASK_REG 0x64 +#define DAVINCI_MCASP_RXFMT_REG 0x68 +#define DAVINCI_MCASP_RXFMCTL_REG 0x6c + +#define DAVINCI_MCASP_ACLKRCTL_REG 0x70 +#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74 +#define DAVINCI_MCASP_RXTDM_REG 0x78 +#define DAVINCI_MCASP_EVTCTLR_REG 0x7c + +#define DAVINCI_MCASP_RXSTAT_REG 0x80 +#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84 +#define DAVINCI_MCASP_RXCLKCHK_REG 0x88 +#define DAVINCI_MCASP_REVTCTL_REG 0x8c + +#define DAVINCI_MCASP_GBLCTLX_REG 0xa0 +#define DAVINCI_MCASP_TXMASK_REG 0xa4 +#define DAVINCI_MCASP_TXFMT_REG 0xa8 +#define DAVINCI_MCASP_TXFMCTL_REG 0xac + +#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0 +#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4 +#define DAVINCI_MCASP_TXTDM_REG 0xb8 +#define DAVINCI_MCASP_EVTCTLX_REG 0xbc + +#define DAVINCI_MCASP_TXSTAT_REG 0xc0 +#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4 +#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8 +#define DAVINCI_MCASP_XEVTCTL_REG 0xcc + +/* Left (even TDM Slot) Channel Status Register File*/ +#define DAVINCI_MCASP_DITCSRA_REG 0x100 +/* Right (odd TDM slot) Channel Status RegisterFile*/ +#define DAVINCI_MCASP_DITCSRB_REG 0x118 +/* Left (even TDM slot) User Data Register File */ +#define DAVINCI_MCASP_DITUDRA_REG 0x130 +/* Right (odd TDM Slot) User Data Register File */ +#define DAVINCI_MCASP_DITUDRB_REG 0x148 + +/* Serializer n Control Register */ +#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180 +#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \ + (n << 2)) + +/* Transmit Buffer for Serializer n */ +#define DAVINCI_MCASP_TXBUF_REG 0x200 +/* Receive Buffer for Serializer n */ +#define DAVINCI_MCASP_RXBUF_REG 0x280 + + +/* + * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management + * Register Bits + */ +#define MCASP_FREE BIT(0) +#define MCASP_SOFT BIT(1) + +/* + * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits + */ +#define AXR(n) (1<<n) +#define PFUNC_AMUTE BIT(25) +#define ACLKX BIT(26) +#define AHCLKX BIT(27) +#define AFSX BIT(28) +#define ACLKR BIT(29) +#define AHCLKR BIT(30) +#define AFSR BIT(31) + +/* + * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits + */ +#define AXR(n) (1<<n) +#define PDIR_AMUTE BIT(25) +#define ACLKX BIT(26) +#define AHCLKX BIT(27) +#define AFSX BIT(28) +#define ACLKR BIT(29) +#define AHCLKR BIT(30) +#define AFSR BIT(31) + +/* + * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits + */ +#define DITEN BIT(0) /* Transmit DIT mode enable/disable */ +#define VA BIT(2) +#define VB BIT(3) + +/* + * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits + */ +#define TXROT(val) (val) +#define TXSEL BIT(3) +#define TXSSZ(val) (val<<4) +#define TXPBIT(val) (val<<8) +#define TXPAD(val) (val<<13) +#define TXORD BIT(15) +#define FSXDLY(val) (val<<16) + +/* + * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits + */ +#define RXROT(val) (val) +#define RXSEL BIT(3) +#define RXSSZ(val) (val<<4) +#define RXPBIT(val) (val<<8) +#define RXPAD(val) (val<<13) +#define RXORD BIT(15) +#define FSRDLY(val) (val<<16) + +/* + * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits + */ +#define FSXPOL BIT(0) +#define AFSXE BIT(1) +#define FSXDUR BIT(4) +#define FSXMOD(val) (val<<7) + +/* + * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits + */ +#define FSRPOL BIT(0) +#define AFSRE BIT(1) +#define FSRDUR BIT(4) +#define FSRMOD(val) (val<<7) + +/* + * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits + */ +#define ACLKXDIV(val) (val) +#define ACLKXE BIT(5) +#define TX_ASYNC BIT(6) +#define ACLKXPOL BIT(7) + +/* + * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits + */ +#define ACLKRDIV(val) (val) +#define ACLKRE BIT(5) +#define RX_ASYNC BIT(6) +#define ACLKRPOL BIT(7) + +/* + * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control + * Register Bits + */ +#define AHCLKXDIV(val) (val) +#define AHCLKXPOL BIT(14) +#define AHCLKXE BIT(15) + +/* + * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control + * Register Bits + */ +#define AHCLKRDIV(val) (val) +#define AHCLKRPOL BIT(14) +#define AHCLKRE BIT(15) + +/* + * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits + */ +#define MODE(val) (val) +#define DISMOD(val) (val<<2) +#define TXSTATE BIT(4) +#define RXSTATE BIT(5) + +/* + * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits + */ +#define LBEN BIT(0) +#define LBORD BIT(1) +#define LBGENMODE(val) (val<<2) + +/* + * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration + */ +#define TXTDMS(n) (1<<n) + +/* + * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration + */ +#define RXTDMS(n) (1<<n) + +/* + * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits + */ +#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */ +#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */ +#define RXSERCLR BIT(2) /* Receiver Serializer Clear */ +#define RXSMRST BIT(3) /* Receiver State Machine Reset */ +#define RXFSRST BIT(4) /* Frame Sync Generator Reset */ +#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */ +#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/ + /* and Transmit Bad Clock Detect /32 Counter + Reset */ +#define TXSERCLR BIT(10) /* Transmit Serializer Clear */ +#define TXSMRST BIT(11) /* Transmitter State Machine Reset */ +#define TXFSRST BIT(12) /* Frame Sync Generator Reset */ + +/* + * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits + */ +#define MUTENA(val) (val) +#define MUTEINPOL BIT(2) +#define MUTEINENA BIT(3) +#define MUTEIN BIT(4) +#define MUTER BIT(5) +#define MUTEX BIT(6) +#define MUTEFSR BIT(7) +#define MUTEFSX BIT(8) +#define MUTEBADCLKR BIT(9) +#define MUTEBADCLKX BIT(10) +#define MUTERXDMAERR BIT(11) +#define MUTETXDMAERR BIT(12) + +/* + * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits + */ +#define RXDATADMADIS BIT(0) + +/* + * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits + */ +#define TXDATADMADIS BIT(0) + + + +#define DAVINCI_MCASP_NUM_SERIALIZER 16 + + +static inline void mcasp_set_bits(void __iomem *reg, u32 val) +{ + __raw_writel(__raw_readl(reg) | val, reg); +} + +static inline void mcasp_clr_bits(void __iomem *reg, u32 val) +{ + __raw_writel((__raw_readl(reg) & ~(val)), reg); +} + +static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask) +{ + __raw_writel((__raw_readl(reg) & ~mask) | val, reg); +} + +static inline void mcasp_set_reg(void __iomem *reg, u32 val) +{ + __raw_writel(val, reg); +} + +static inline u32 mcasp_get_reg(void __iomem *reg) +{ + return (unsigned int)__raw_readl(reg); +} + +static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val) +{ + int i = 0; + mcasp_set_bits(regs, val); + + /* programming GBLCTL needs to read back from GBLCTL and verfiy */ + /* loop count is to avoid the lock-up */ + for (i = 0; (i < 1000) && ((mcasp_get_reg(regs) & val) != val); i++); + +} + +int davinci_i2s_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + cpu_dai->dma_data = dev->dma_params[substream->stream]; + + return 0; +} + +int davinci_i2s_mcasp_probe(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + int tmp, link_cnt; + int count = 0; + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_card *card = socdev->card; + struct snd_soc_dai *cpu_dai; + struct davinci_audio_dev *dev; + struct resource *mem, *ioarea; + struct evm_snd_platform_data *parray = pdev->dev.platform_data; + struct evm_snd_platform_data *pdata; + struct davinci_pcm_dma_params *dma_data; + int ret = 0; + + for (link_cnt = 0; link_cnt < card->num_links; link_cnt++) { + mem = platform_get_resource(pdev, IORESOURCE_MEM, link_cnt); + if (!mem) { + dev_err(&pdev->dev, "no mem resource?\n"); + ret = -ENODEV; + } + ioarea = request_mem_region(mem->start, + (mem->end - mem->start) + 1, pdev->name); + if (!ioarea) { + dev_err(&pdev->dev, "Audio region already claimed\n"); + ret = -EBUSY; + } + + dev = kzalloc(sizeof(struct davinci_audio_dev) * + card->num_links, GFP_KERNEL); + if (!dev) { + return -ENOMEM; + goto err_release_region; + } + dma_data = kzalloc(sizeof(struct davinci_pcm_dma_params) * + (card->num_links << 1), GFP_KERNEL); + if (!dma_data) + goto err_release_dev; + cpu_dai = card->dai_link[link_cnt].cpu_dai; + cpu_dai->private_data = &dev[link_cnt]; + pdata = &parray[link_cnt]; + dev[link_cnt].clk = clk_get(&pdev->dev, pdata->clk_name); + + if (IS_ERR(dev[link_cnt].clk)) { + ret = -ENODEV; + goto err_release_data; + } + clk_enable(dev[link_cnt].clk); + + dev[link_cnt].base = (void __iomem *)IO_ADDRESS(mem->start); + dev[link_cnt].op_mode = pdata->op_mode; + dev[link_cnt].tdm_slots = pdata->tdm_slots; + dev[link_cnt].num_serializer = pdata->num_serializer; + dev[link_cnt].serial_dir = pdata->serial_dir; + dev[link_cnt].codec_fmt = pdata->codec_fmt; + + + dma_data[count].name = "I2S PCM Stereo out"; + dma_data[count].channel = pdata->tx_dma_ch; + dma_data[count].eventq_no = pdata->eventq_no; + dma_data[count].dma_addr = (dma_addr_t) (pdata->tx_dma_offset + + io_v2p(dev[link_cnt].base)); + dev[link_cnt].dma_params[SNDRV_PCM_STREAM_PLAYBACK] = + &dma_data[count]; + + + count++; + dma_data[count].name = "I2S PCM Stereo in"; + dma_data[count].channel = pdata->rx_dma_ch; + dma_data[count].eventq_no = pdata->eventq_no; + dma_data[count].dma_addr = (dma_addr_t)(pdata->rx_dma_offset + + io_v2p(dev[link_cnt].base)); + dev[link_cnt].dma_params[SNDRV_PCM_STREAM_CAPTURE] = + &dma_data[count]; + count++; + + } + return 0; + +err_release_data: + kfree(dma_data); +err_release_dev: + kfree(dev); +err_release_region: + for (tmp = link_cnt; tmp >= 0; tmp--) { + mem = platform_get_resource(pdev, IORESOURCE_MEM, tmp); + release_mem_region(mem->start, + (mem->end - mem->start) + 1); + } + + return ret; +} + +void davinci_i2s_mcasp_remove(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + int i; + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_card *card = socdev->card; + struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai; + struct davinci_audio_dev *dev_list = cpu_dai->private_data; + struct davinci_audio_dev *dev; + struct resource *mem; + struct davinci_pcm_dma_params *ptr; + + for (i = 0; i < card->num_links; i++) { + dev = &dev_list[i]; + clk_disable(dev->clk); + clk_put(dev->clk); + dev->clk = NULL; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, i); + release_mem_region(mem->start, (mem->end - mem->start) + 1); + } + ptr = dev_list->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; + kfree(ptr); + kfree(dev_list); +} + +void mcasp_start_rx(struct davinci_audio_dev *dev) +{ + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); + + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); + + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); +} + +void mcasp_start_tx(struct davinci_audio_dev *dev) +{ + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); + + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); +} + +static void davinci_mcasp_start(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + mcasp_start_tx(dev); + else + mcasp_start_rx(dev); +} + +void mcasp_stop_rx(struct davinci_audio_dev *dev) +{ + mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); +} + +void mcasp_stop_tx(struct davinci_audio_dev *dev) +{ + mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); +} + +static void davinci_mcasp_stop(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + mcasp_stop_tx(dev); + else + mcasp_stop_rx(dev); +} + +static int davinci_i2s_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, + unsigned int fmt) +{ + struct davinci_audio_dev *dev = cpu_dai->private_data; + void __iomem *base = dev->base; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* codec is clock and frame slave */ + mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); + mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); + + mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); + mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); + + mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26)); + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* codec is clock and frame master */ + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); + mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); + + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); + mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); + + mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26)); + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_IB_NF: + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + case SND_SOC_DAIFMT_NB_IF: + mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + case SND_SOC_DAIFMT_IB_IF: + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + case SND_SOC_DAIFMT_NB_NF: + mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int davinci_config_channel_size(struct snd_pcm_substream *substream, + int channel_size) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + u32 fmt = 0; + + switch (channel_size) { + case DAVINCI_AUDIO_WORD_8: + fmt = 0x03 << 4; + break; + + case DAVINCI_AUDIO_WORD_12: + fmt = 0x05 << 4; + break; + + case DAVINCI_AUDIO_WORD_16: + fmt = 0x07 << 4; + break; + + case DAVINCI_AUDIO_WORD_20: + fmt = 0x09 << 4; + break; + + case DAVINCI_AUDIO_WORD_24: + fmt = 0x0B << 4; + break; + + case DAVINCI_AUDIO_WORD_28: + fmt = 0x0D << 4; + break; + + case DAVINCI_AUDIO_WORD_32: + fmt = 0x0F << 4; + break; + + default: + return -1; + } + + mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, fmt, (0x0F << 4)); + mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, fmt, (0x0F << 4)); + return 0; +} + +static void davinci_hw_common_param(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + int i; + + /* Default configuration */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); + + /* All PINS as McASP */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, + TXDATADMADIS); + } else { + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG, + RXDATADMADIS); + } + + for (i = 0; i < dev->num_serializer; i++) { + mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), + dev->serial_dir[i]); + if (dev->serial_dir[i] == TX_MODE) + mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, + AXR(i)); + else if (dev->serial_dir[i] == RX_MODE) + mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, + AXR(i)); + } +} +static void davinci_hw_iis_param(struct snd_pcm_substream *substream) +{ + int i, active_slots; + u32 mask = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots; + for (i = 0; i < active_slots; i++) + mask |= (1 << i); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* bit stream is MSB first */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXE); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask); + mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD); + + if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32)) + mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, + FSXMOD(dev->tdm_slots), FSXMOD(0x1FF)); + else + printk(KERN_ERR "playback tdm slot %d not supported\n", + dev->tdm_slots); + + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); + + } else { + /* bit stream is MSB first with no delay */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, + FSRDLY(1) | RXORD); + mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, + AHCLKRE); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask); + + if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32)) + mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, + FSRMOD(dev->tdm_slots), FSRMOD(0x1FF)); + else + printk(KERN_ERR "capture tdm slot %d not supported\n", + dev->tdm_slots); + + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); + } +} + +/* S/PDIF */ +static void davinci_hw_dit_param(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + /* Set the PDIR for Serialiser as output */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX); + + /* TXMASK for 24 bits */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF); + + /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 + and LSB first */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, + TXROT(6) | TXSSZ(15)); + + /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG, + AFSXE | FSXMOD(0x180)); + + /* Set the TX tdm : for all the slots */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); + + /* Set the TX clock controls : div = 1 and internal */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, + ACLKXE | TX_ASYNC); + + mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); + + /* Only 44100 and 48000 are valid, both have the same setting */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXDIV(3)); + + /* Enable the DIT */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN); +} + +static int davinci_i2s_mcasp_hw_params( + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + struct davinci_pcm_dma_params *dma_params = + dev->dma_params[substream->stream]; + int word_length; + + davinci_hw_common_param(substream); + + if (dev->op_mode == DAVINCI_MCASP_DIT_MODE) + davinci_hw_dit_param(substream); + else + davinci_hw_iis_param(substream); + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S8: + dma_params->data_type = 1; + word_length = DAVINCI_AUDIO_WORD_8; + break; + case SNDRV_PCM_FORMAT_S16_LE: + dma_params->data_type = 2; + word_length = DAVINCI_AUDIO_WORD_16; + break; + case SNDRV_PCM_FORMAT_S32_LE: + dma_params->data_type = 4; + word_length = DAVINCI_AUDIO_WORD_32; + break; + default: + printk(KERN_WARNING "davinci-i2s: unsupported PCM format"); + return -EINVAL; + } + davinci_config_channel_size(substream, word_length); + + return 0; +} + +static int davinci_i2s_mcasp_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + davinci_mcasp_start(substream); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + davinci_mcasp_stop(substream); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static struct snd_soc_dai_ops davinci_i2s_dai_ops = { + .startup = davinci_i2s_startup, + .trigger = davinci_i2s_mcasp_trigger, + .hw_params = davinci_i2s_mcasp_hw_params, + .set_fmt = davinci_i2s_mcasp_set_dai_fmt, + +}; + +struct snd_soc_dai davinci_iis_mcasp_dai[] = { + { + .name = "davinci-i2s", + .id = 0, + .probe = davinci_i2s_mcasp_probe, + .remove = davinci_i2s_mcasp_remove, + .playback = { + .channels_min = 1, + .channels_max = 384, + .rates = DAVINCI_I2S_RATES, + .formats = SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .capture = { + .channels_min = 1, + .channels_max = 384, + .rates = DAVINCI_I2S_RATES, + .formats = SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .ops = &davinci_i2s_dai_ops, + + }, + { + .name = "davinci-dit", + .id = 1, + .playback = { + .channels_min = 1, + .channels_max = 384, + .rates = DAVINCI_I2S_RATES, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &davinci_i2s_dai_ops, + }, + +}; +EXPORT_SYMBOL_GPL(davinci_iis_mcasp_dai); + +static int __init davinci_i2s_mcasp_init(void) +{ + return snd_soc_register_dais(davinci_iis_mcasp_dai, + ARRAY_SIZE(davinci_iis_mcasp_dai)); + +} +module_init(davinci_i2s_mcasp_init); + +static void __exit davinci_i2s_mcasp_exit(void) +{ + return snd_soc_unregister_dais(davinci_iis_mcasp_dai, + ARRAY_SIZE(davinci_iis_mcasp_dai)); + +} +module_exit(davinci_i2s_mcasp_exit); + + + +MODULE_AUTHOR("Steve Chen"); +MODULE_DESCRIPTION("TI DAVINCI I2S (McASP) SoC Interface"); +MODULE_LICENSE("GPL"); + diff --git a/sound/soc/davinci/davinci-i2s-mcasp.h b/sound/soc/davinci/davinci-i2s-mcasp.h new file mode 100644 index 0000000..6469e7d --- /dev/null +++ b/sound/soc/davinci/davinci-i2s-mcasp.h @@ -0,0 +1,56 @@ +/* + * ALSA SoC I2S (McASP) Audio Layer for TI DAVINCI processor + * + * Author: Nirmal Pandey <n-pandey(a)ti.com>, + * Suresh Rajashekara <suresh.r(a)ti.com> + * Steve Chen, <schen@.mvista.com> + * + * Copyright: (C) 2008 MontaVista Software, Inc., <source(a)mvista.com> + * Copyright: (C) 2008 Texas Instruments, India + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#ifndef DAVINCI_I2S_MCASP_H +#define DAVINCI_I2S_MCASP_H + +#include <linux/io.h> +#include <mach/asp.h> +#include "davinci-pcm.h" + +extern struct snd_soc_dai davinci_iis_mcasp_dai[]; +extern struct snd_soc_dai davinci_dit_mcasp_dai; + + +#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 + +enum { + DAVINCI_AUDIO_WORD_8 = 0, + DAVINCI_AUDIO_WORD_12, + DAVINCI_AUDIO_WORD_16, + DAVINCI_AUDIO_WORD_20, + DAVINCI_AUDIO_WORD_24, + DAVINCI_AUDIO_WORD_32, + DAVINCI_AUDIO_WORD_28, /* This is only valid for McASP */ +}; + +struct davinci_audio_dev { + void __iomem *base; + int sample_rate; + struct clk *clk; + struct davinci_pcm_dma_params *dma_params[2]; + unsigned int codec_fmt; + + /* McASP specific data */ + int tdm_slots; + u8 op_mode; + u8 num_serializer; + u8 *serial_dir; +}; + + + +#endif /* DAVINCI_I2S_MCASP_H */ diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h index 62cb4eb..3cbe281 100644 --- a/sound/soc/davinci/davinci-pcm.h +++ b/sound/soc/davinci/davinci-pcm.h @@ -12,17 +12,18 @@ #ifndef _DAVINCI_PCM_H #define _DAVINCI_PCM_H +#include <mach/edma.h> +#include <mach/asp.h> + + struct davinci_pcm_dma_params { - char *name; /* stream identifier */ - int channel; /* sync dma channel ID */ - dma_addr_t dma_addr; /* device physical address for DMA */ - unsigned int data_type; /* xfer data type */ + char *name; /* stream identifier */ + int channel; /* sync dma channel ID */ + dma_addr_t dma_addr; /* device physical address for DMA */ + unsigned int data_type; /* xfer data type */ + enum dma_event_q eventq_no; /* event queue number */ }; -struct evm_snd_platform_data { - int tx_dma_ch; - int rx_dma_ch; -}; extern struct snd_soc_platform davinci_soc_platform; -- 1.5.6

2 1

[PATCH] ASoC: Implement suspend and resume operations for WM9705
by Mark Brown 02 Apr '09

02 Apr '09

Compile tested only. Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm9705.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c index 3265817..2109b50 100644 --- a/sound/soc/codecs/wm9705.c +++ b/sound/soc/codecs/wm9705.c @@ -317,6 +317,41 @@ static int wm9705_reset(struct snd_soc_codec *codec) return -EIO; } +#ifdef CONFIG_PM +static int wm9705_soc_suspend(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + soc_ac97_ops.write(codec->ac97, AC97_POWERDONW, 0xffff); + + return 0; +} + +static int wm9705_soc_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + int i, ret; + u16 *cache = codec->reg_cache; + + ret = wm9705_reset(codec); + if (ret < 0) { + printk(KERN_ERR "could not reset AC97 codec\n"); + return ret; + } + + for (i = 2; i < ARRAY_SIZE(wm9705_reg) << 1; i += 2) { + soc_ac97_ops.write(codec->ac97, i, cache[i>>1]); + } + + return 0; +} +#else +#define wm9705_soc_suspend NULL +#define wm9705_soc_resume NULL +#endif + static int wm9705_soc_probe(struct platform_device *pdev) { struct snd_soc_device *socdev = platform_get_drvdata(pdev); @@ -407,6 +442,8 @@ static int wm9705_soc_remove(struct platform_device *pdev) struct snd_soc_codec_device soc_codec_dev_wm9705 = { .probe = wm9705_soc_probe, .remove = wm9705_soc_remove, + .suspend = wm9705_soc_suspend, + .resume = wm9705_soc_resume, }; EXPORT_SYMBOL_GPL(soc_codec_dev_wm9705); -- 1.6.2.1

1 0

Re: [alsa-devel] [PATCH 3/3] ARM: DaVinci: ASoC: Add machine driver support for DM646x
by Medisetty, Naresh 02 Apr '09

02 Apr '09

Please ignore this patch since the patch number is wrong. I will re-submit the same patch with proper numbering. Regards Naresh This patch does the following: (1) Add support for the DM646x machine (2)Introduce the platform driver model to get platform data for all the machines including dm355 and dm644x. Signed-off-by: Naresh Medisetty naresh(a)ti.com --- _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source(a)linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

1 0

[PATCH] ASoC: Implement suspend and resume operations for WM9705
by Mark Brown 02 Apr '09

02 Apr '09

Compile tested only. Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm9705.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c index 3265817..0564476 100644 --- a/sound/soc/codecs/wm9705.c +++ b/sound/soc/codecs/wm9705.c @@ -317,6 +317,41 @@ static int wm9705_reset(struct snd_soc_codec *codec) return -EIO; } +#ifdef CONFIG_PM +static int wm9705_soc_suspend(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + ac97_write(codec, AC97_POWERDOWN, 0xffff); + + return 0; +} + +static int wm9705_soc_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + int i, ret; + u16 *cache = codec->reg_cache; + + ret = wm9705_reset(codec); + if (ret < 0) { + printk(KERN_ERR "could not reset AC97 codec\n"); + return ret; + } + + for (i = 2; i < ARRAY_SIZE(wm9705_reg) << 1; i += 2) { + soc_ac97_ops.write(codec->ac97, i, cache[i>>1]); + } + + return 0; +} +#else +#define wm9705_soc_suspend NULL +#define wm9705_soc_resume NULL +#endif + static int wm9705_soc_probe(struct platform_device *pdev) { struct snd_soc_device *socdev = platform_get_drvdata(pdev); @@ -407,6 +442,8 @@ static int wm9705_soc_remove(struct platform_device *pdev) struct snd_soc_codec_device soc_codec_dev_wm9705 = { .probe = wm9705_soc_probe, .remove = wm9705_soc_remove, + .suspend = wm9705_soc_suspend, + .resume = wm9705_soc_resume, }; EXPORT_SYMBOL_GPL(soc_codec_dev_wm9705); -- 1.6.2.1

1 0

[PATCH 2/2] ASoC: cs4270: add power management support
by Daniel Mack 02 Apr '09

02 Apr '09

Signed-off-by: Daniel Mack <daniel(a)caiaq.de> Cc: Timur Tabi <timur(a)freescale.com> Cc: Mark Brown <broonie(a)sirena.org.uk> --- sound/soc/codecs/cs4270.c | 59 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 58 insertions(+), 1 deletions(-) diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c index bc338df..65c68a0 100644 --- a/sound/soc/codecs/cs4270.c +++ b/sound/soc/codecs/cs4270.c @@ -18,7 +18,7 @@ * - The machine driver's 'startup' function must call * cs4270_set_dai_sysclk() with the value of MCLK. * - Only I2S and left-justified modes are supported - * - Power management is not supported + * - Power management is supported */ #include <linux/module.h> @@ -27,6 +27,7 @@ #include <sound/soc.h> #include <sound/initval.h> #include <linux/i2c.h> +#include <linux/delay.h> #include "cs4270.h" @@ -65,6 +66,8 @@ #define CS4270_PWRCTL_PDN_ADC 0x20 #define CS4270_PWRCTL_PDN_DAC 0x02 #define CS4270_PWRCTL_PDN 0x01 +#define CS4270_PWRCTL_PDN_ALL \ + (CS4270_PWRCTL_PDN_ADC | CS4270_PWRCTL_PDN_DAC | CS4270_PWRCTL_PDN) #define CS4270_MODE_SPEED_MASK 0x30 #define CS4270_MODE_1X 0x00 #define CS4270_MODE_2X 0x10 @@ -788,6 +791,58 @@ static struct i2c_device_id cs4270_id[] = { }; MODULE_DEVICE_TABLE(i2c, cs4270_id); +#ifdef CONFIG_PM + +/* This suspend/resume implementation can handle both - a simple standby + * where the codec remains powered, and a full suspend, where the voltage + * domain the codec is connected to is teared down and/or any other hardware + * reset condition is asserted. + * + * The codec's own power saving features are enabled in the suspend callback, + * and all registers are written back to the hardware when resuming. + */ + +static int cs4270_i2c_suspend(struct i2c_client *client, pm_message_t mesg) +{ + struct cs4270_private *cs4270 = i2c_get_clientdata(client); + struct snd_soc_codec *codec = &cs4270->codec; + int reg = snd_soc_read(codec, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL; + return snd_soc_write(codec, CS4270_PWRCTL, reg); +} + +static int cs4270_i2c_resume(struct i2c_client *client) +{ + struct cs4270_private *cs4270 = i2c_get_clientdata(client); + struct snd_soc_codec *codec = &cs4270->codec; + int reg; + + /* In case the device was put to hard reset during sleep, we need to + * wait 500ns here before any I2C communication. */ + ndelay(500); + + /* first restore the entire register cache ... */ + for (reg = CS4270_FIRSTREG; reg <= CS4270_LASTREG; reg++) { + u8 val = snd_soc_read(codec, reg); + + if (i2c_smbus_write_byte_data(client, reg, val)) { + dev_err(codec->dev, "i2c write failed\n"); + return -EIO; + } + } + + /* ... then disable the power-down bits */ + reg = snd_soc_read(codec, CS4270_PWRCTL); + if (reg < 0) + return reg; + + reg &= ~CS4270_PWRCTL_PDN_ALL; + return snd_soc_write(codec, CS4270_PWRCTL, reg); +} +#else +#define cs4270_i2c_suspend NULL +#define cs4270_i2c_resume NULL +#endif /* CONFIG_PM */ + /* * cs4270_i2c_driver - I2C device identification * @@ -802,6 +857,8 @@ static struct i2c_driver cs4270_i2c_driver = { .id_table = cs4270_id, .probe = cs4270_i2c_probe, .remove = cs4270_i2c_remove, + .suspend = cs4270_i2c_suspend, + .resume = cs4270_i2c_resume, }; /* -- 1.6.2.1

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[PATCH v3] ASoC: cs4270: add power management support
by Daniel Mack 02 Apr '09

02 Apr '09

Signed-off-by: Daniel Mack <daniel(a)caiaq.de> Cc: Timur Tabi <timur(a)freescale.com> Cc: Mark Brown <broonie(a)sirena.org.uk> --- sound/soc/codecs/cs4270.c | 58 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 57 insertions(+), 1 deletions(-) diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c index bc338df..4d4a45e 100644 --- a/sound/soc/codecs/cs4270.c +++ b/sound/soc/codecs/cs4270.c @@ -18,7 +18,7 @@ * - The machine driver's 'startup' function must call * cs4270_set_dai_sysclk() with the value of MCLK. * - Only I2S and left-justified modes are supported - * - Power management is not supported + * - Power management is supported */ #include <linux/module.h> @@ -27,6 +27,7 @@ #include <sound/soc.h> #include <sound/initval.h> #include <linux/i2c.h> +#include <linux/delay.h> #include "cs4270.h" @@ -65,6 +66,8 @@ #define CS4270_PWRCTL_PDN_ADC 0x20 #define CS4270_PWRCTL_PDN_DAC 0x02 #define CS4270_PWRCTL_PDN 0x01 +#define CS4270_PWRCTL_PDN_ALL \ + (CS4270_PWRCTL_PDN_ADC | CS4270_PWRCTL_PDN_DAC | CS4270_PWRCTL_PDN) #define CS4270_MODE_SPEED_MASK 0x30 #define CS4270_MODE_1X 0x00 #define CS4270_MODE_2X 0x10 @@ -788,6 +791,57 @@ static struct i2c_device_id cs4270_id[] = { }; MODULE_DEVICE_TABLE(i2c, cs4270_id); +#ifdef CONFIG_PM + +/* This suspend/resume implementation can handle both - a simple standby + * where the codec remains powered, and a full suspend, where the voltage + * domain the codec is connected to is teared down and/or any other hardware + * reset condition is asserted. + * + * The codec's own power saving features are enabled in the suspend callback, + * and all registers are written back to the hardware when resuming. + */ + +static int cs4270_i2c_suspend(struct i2c_client *client, pm_message_t mesg) +{ + struct cs4270_private *cs4270 = i2c_get_clientdata(client); + struct snd_soc_codec *codec = &cs4270->codec; + int reg = snd_soc_read(codec, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL; + + return snd_soc_write(codec, CS4270_PWRCTL, reg); +} + +static int cs4270_i2c_resume(struct i2c_client *client) +{ + struct cs4270_private *cs4270 = i2c_get_clientdata(client); + struct snd_soc_codec *codec = &cs4270->codec; + int reg; + + /* In case the device was put to hard reset during sleep, we need to + * wait 500ns here before any I2C communication. */ + ndelay(500); + + /* first restore the entire register cache ... */ + for (reg = CS4270_FIRSTREG; reg <= CS4270_LASTREG; reg++) { + u8 val = snd_soc_read(codec, reg); + + if (i2c_smbus_write_byte_data(client, reg, val)) { + dev_err(codec->dev, "i2c write failed\n"); + return -EIO; + } + } + + /* ... then disable the power-down bits */ + reg = snd_soc_read(codec, CS4270_PWRCTL); + reg &= ~CS4270_PWRCTL_PDN_ALL; + + return snd_soc_write(codec, CS4270_PWRCTL, reg); +} +#else +#define cs4270_i2c_suspend NULL +#define cs4270_i2c_resume NULL +#endif /* CONFIG_PM */ + /* * cs4270_i2c_driver - I2C device identification * @@ -802,6 +856,8 @@ static struct i2c_driver cs4270_i2c_driver = { .id_table = cs4270_id, .probe = cs4270_i2c_probe, .remove = cs4270_i2c_remove, + .suspend = cs4270_i2c_suspend, + .resume = cs4270_i2c_resume, }; /* -- 1.6.2.1

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[alsa-devel] [patch] tlv320aic3x: disable ADC/DAC while changing clock
by Daniel Glöckner 02 Apr '09

02 Apr '09

While using a tlv320aic3101 as a clock master, it often happened that the clock lines got stuck while changing the sampling rate. In a discussion with TI technical support it was suggested to shut down the ADC and DAC while there are changes being made to the clock. Following that rule resolves the problem, but merely writing the registers to switch the ADC/DAC off is not enough. One needs to poll the power status registers to wait until they have completely shut down. The aforementioned rule implies that we can not disable the PLL in stand-by bias level. Signed-off-by: Daniel Glöckner <dg(a)emlix.com> --- sound/soc/codecs/tlv320aic3x.c | 89 ++++++++++++++++++++++++++++------------ sound/soc/codecs/tlv320aic3x.h | 8 ++++ 2 files changed, 71 insertions(+), 26 deletions(-) diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index aea0cb7..4c44022 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -740,6 +740,57 @@ static int aic3x_add_widgets(struct snd_soc_codec *codec) return 0; } +static u8 aic3x_power_codec(struct snd_soc_codec *codec, u8 new) +{ + u8 val, old; + + val = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL); + old = (val & LADC_PWR_ON) ? 1 : 0; + if ((old ^ new) & 1) { + val ^= LADC_PWR_ON; + aic3x_write(codec, LINE1L_2_LADC_CTRL, val); + } + + val = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL); + old += (val & RADC_PWR_ON) ? 2 : 0; + if ((old ^ new) & 2) { + val ^= RADC_PWR_ON; + aic3x_write(codec, LINE1R_2_RADC_CTRL, val); + } + + val = aic3x_read_reg_cache(codec, DAC_PWR); + old += (val & LDAC_PWR_ON) ? 4 : 0; + old += (val & RDAC_PWR_ON) ? 8 : 0; + if ((old ^ new) & 4) + val ^= LDAC_PWR_ON; + if ((old ^ new) & 8) + val ^= RDAC_PWR_ON; + if ((old ^ new) & 12) + aic3x_write(codec, DAC_PWR, val); + + return old; +} + +static u8 aic3x_power_off_wait(struct snd_soc_codec *codec) +{ + int timeout = 1000; + u8 old, data; + old = aic3x_power_codec(codec, 0); + + do { + aic3x_read(codec, ADC_FLAGS, &data); + } while ((data & (LADC_PWR_STATUS | RADC_PWR_STATUS)) && --timeout > 0); + + do { + aic3x_read(codec, MODULE_PWR_STATUS, &data); + } while ((data & (LDAC_PWR_STATUS | RDAC_PWR_STATUS)) && --timeout > 0); + + if (timeout < 0) + printk(KERN_WARNING "aic3x: timeout waiting for ADC/DAC to shut down"); + + return old; +} + static int aic3x_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -749,9 +800,11 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, struct snd_soc_codec *codec = socdev->codec; struct aic3x_priv *aic3x = codec->private_data; int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; - u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; + u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1, state_saved; u16 pll_d = 1; + state_saved = aic3x_power_off_wait(codec); + /* select data word length */ data = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); @@ -805,8 +858,10 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, data |= (data << 4); aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); - if (bypass_pll) + if (bypass_pll) { + aic3x_power_codec(codec, state_saved); return 0; + } /* Use PLL * find an apropriate setup for j, d, r and p by iterating over @@ -847,6 +902,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, if (last_clk == 0) { printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); + aic3x_power_codec(codec, state_saved); return -EINVAL; } @@ -857,7 +913,11 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT); aic3x_write(codec, AIC3X_PLL_PROGD_REG, (pll_d & 0x3F) << PLLD_LSB_SHIFT); + data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); + aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT) + | PLL_ENABLE); + aic3x_power_codec(codec, state_saved); return 0; } @@ -951,37 +1011,14 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec, switch (level) { case SND_SOC_BIAS_ON: - /* all power is driven by DAPM system */ - if (aic3x->master) { - /* enable pll */ - reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); - aic3x_write(codec, AIC3X_PLL_PROGA_REG, - reg | PLL_ENABLE); - } break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: - /* - * all power is driven by DAPM system, - * so output power is safe if bypass was set - */ - if (aic3x->master) { - /* disable pll */ - reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); - aic3x_write(codec, AIC3X_PLL_PROGA_REG, - reg & ~PLL_ENABLE); - } break; case SND_SOC_BIAS_OFF: /* force all power off */ - reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL); - aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON); - reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL); - aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON); - - reg = aic3x_read_reg_cache(codec, DAC_PWR); - aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON)); + aic3x_power_off_wait(codec); reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON); diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h index ac827e5..0b4fedf 100644 --- a/sound/soc/codecs/tlv320aic3x.h +++ b/sound/soc/codecs/tlv320aic3x.h @@ -69,6 +69,8 @@ #define RAGC_CTRL_B 30 #define RAGC_CTRL_C 31 +/* ADC Flag register */ +#define ADC_FLAGS 34 /* DAC Power and Left High Power Output control registers */ #define DAC_PWR 37 #define HPLCOM_CFG 37 @@ -126,6 +128,8 @@ #define DACR1_2_LLOPM_VOL 85 #define LLOPM_CTRL 86 #define RLOPM_CTRL 93 +/* Module Power status register */ +#define MODULE_PWR_STATUS 94 /* GPIO/IRQ registers */ #define AIC3X_STICKY_IRQ_FLAGS_REG 96 #define AIC3X_RT_IRQ_FLAGS_REG 97 @@ -191,6 +195,10 @@ #define MONOLOPM_PWR_ON 0x01 #define LLOPM_PWR_ON 0x01 #define RLOPM_PWR_ON 0x01 +#define LADC_PWR_STATUS 0x40 +#define RADC_PWR_STATUS 0x04 +#define LDAC_PWR_STATUS 0x80 +#define RDAC_PWR_STATUS 0x40 #define INVERT_VOL(val) (0x7f - val) -- 1.6.2.107.ge47ee

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[alsa-devel] [PATCH v2 1/9] snd-atmel-ac97c: cleanup register definitions
by Hans-Christian Egtvedt 02 Apr '09

02 Apr '09

This patch will remove traces of channel B registers, since they are not used by the AC97C driver. Channel B might be used for other purposes. The driver also adds channel status bits TXEMPTY and OVRUN and a AC97C_CH_MASK macro to ease clearing a channel settings. Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt(a)atmel.com> --- sound/atmel/ac97c.h | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/sound/atmel/ac97c.h b/sound/atmel/ac97c.h index c17bd58..ecbba50 100644 --- a/sound/atmel/ac97c.h +++ b/sound/atmel/ac97c.h @@ -1,5 +1,5 @@ /* - * Register definitions for the Atmel AC97C controller + * Register definitions for Atmel AC97C * * Copyright (C) 2005-2009 Atmel Corporation * @@ -17,10 +17,6 @@ #define AC97C_CATHR 0x24 #define AC97C_CASR 0x28 #define AC97C_CAMR 0x2c -#define AC97C_CBRHR 0x30 -#define AC97C_CBTHR 0x34 -#define AC97C_CBSR 0x38 -#define AC97C_CBMR 0x3c #define AC97C_CORHR 0x40 #define AC97C_COTHR 0x44 #define AC97C_COSR 0x48 @@ -46,8 +42,10 @@ #define AC97C_MR_VRA (1 << 2) #define AC97C_CSR_TXRDY (1 << 0) +#define AC97C_CSR_TXEMPTY (1 << 1) #define AC97C_CSR_UNRUN (1 << 2) #define AC97C_CSR_RXRDY (1 << 4) +#define AC97C_CSR_OVRUN (1 << 5) #define AC97C_CSR_ENDTX (1 << 10) #define AC97C_CSR_ENDRX (1 << 14) @@ -61,11 +59,15 @@ #define AC97C_CMR_DMAEN (1 << 22) #define AC97C_SR_CAEVT (1 << 3) +#define AC97C_SR_COEVT (1 << 2) +#define AC97C_SR_WKUP (1 << 1) +#define AC97C_SR_SOF (1 << 0) +#define AC97C_CH_MASK(slot) \ + (0x7 << (3 * (AC97_SLOT_##slot - 3))) #define AC97C_CH_ASSIGN(slot, channel) \ (AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3))) #define AC97C_CHANNEL_NONE 0x0 #define AC97C_CHANNEL_A 0x1 -#define AC97C_CHANNEL_B 0x2 #endif /* __SOUND_ATMEL_AC97C_H */ -- 1.5.6.3

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[alsa-devel] [PATCH 0/7] snd-atmel-ac97c: misc fixes and error reporting
by Hans-Christian Egtvedt 02 Apr '09

02 Apr '09

This patch series contains six minor fixes and one enhancment of the snd-atmel-ac97c driver. It is based on the for-next branch in sound-2.6 git repo. The enhancment is enabling interrupts for error reporting, this might be useful if you have sound troubles (glitches) on a stressed system. -- Best regards, Hans-Christian Egtvedt

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[alsa-devel] iMac 9,1 sound
by Micah Bucy 02 Apr '09

02 Apr '09

I was able to get sound working on the new iMac by adding the following to alsa-driver-1.0.19/alsa-kernel/pci/hda/patch_realtek.c case 0x106b4900: /* iMac 9,1 */ underneath line 7013 case 0x106b1000: /* iMac 24 */ (this kept it from using the alc883 since the revision_id is 0x100103). I did find though, that using the mbp3 option is what allowed sound to work. The same issues with the macbook pro aluminum apply here. the channel must be switched to 2ch to mute built-in speakers and to 6ch to unmute. There is another issue here though. the playback from the speakers is barely audible, i'm guessing it's similar to the issue with the right speaker on the macbook pro. I'm guessing there needs to be adjustments to the pins defined. My current alsa-info resides at http://www.alsa-project.org/db/?f=5bfaadf03f7134e9ef2c3a934fb4084d36ba2d93 If there's anything else I can do to help this along, let me know. I do have the macbook pro aluminum, so I can test there as well. -Micah

1 0