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[alsa-devel] Duplicate configuration nodes
by Jochem Wichers Hoeth 07 Sep '09

07 Sep '09

Hi, Since I upgraded from alsa-lib 1.0.20 to 1.0.21 my configuration is not parsed correctly anymore: $ aplay test.wav ALSA lib conf.c:4639:(snd_config_expand) Expand error (walk): File exists Playing WAVE 'test.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Mono As a result of this error, ALSA seems to ignore the second half of HDA-Intel.conf, including the iec958 definition. I traced the "File exists" error back to snd_config_add() returning -EEXIST, while evaluating the "strings" node at line 36 of cards/HDA-Intel.conf. I verified that at that point the src node indeed has four children: two duplicates of each child node of the original strings array. I'm not exactly sure what's happening here, but I do see that the HDA-Intel.conf file (and all of its included files) are actually read *twice* by aplay. With alsa-lib 1.0.20 aplay only reads these files once. The problem seems to be related to commit 96da0c842d14b40ce8e37726b259229634b3aa21 ("Fix driver conf parsing in snd_config_hook_load_for_all_cards()"), which subtly changes the logic when the same driver is encountered for the second time. I have two cards using the HDA-Intel config (one analog and one digital). For the first card, the config is loaded without issues. But for the second card, snd_config_search(root, fdriver, &n) succeeds but snd_config_get_string(n, &driver) fails. In 1.0.20 this results in a "goto __err", skipping the actual config load. But in 1.0.21 this results in the else-branch being chosen (driver = fdriver) and next snd_config_hook_load being called. I know too little of the entire config loading process to be sure what exactly is going wrong here, but a assume that the second call to snd_config_hook_load for the same configaration file somehow eventually results in the duplicate node error in snd_config_add(). I've verified that reverting 96da0c842d14b40ce8e37726b259229634b3aa21 fixes the problem, or at least the symptoms. :-) Please let me know if you need extra information, of if you'd like me to do some more testing. Cheers, Jochem Wichers Hoeth

1 0

[alsa-devel] [PATCH] Minor WM8580 enhancements.
by jassi brar 07 Sep '09

07 Sep '09

Add more options to select clock source for various blocks in WM8580. Also, explicitly set defaults for the sake of consistency. Signed-off-by: Jassi <jassi.brar(a)samsung.com> --- sound/soc/codecs/wm8580.c | 133 +++++++++++++++++++++++++++++++++++++++++++-- sound/soc/codecs/wm8580.h | 25 +++++---- 2 files changed, 144 insertions(+), 14 deletions(-) diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index 6bded8c..276bc8e 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -95,6 +95,7 @@ /* PLLB4 (register 7h) */ #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60 +#define WM8580_PLLB4_MCLKOUTSRC_MCLK 0x00 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60 @@ -106,9 +107,16 @@ /* CLKSEL (register 8h) */ #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03 +#define WM8580_CLKSEL_DAC_CLKSEL_MCLK 0x00 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02 +#define WM8580_CLKSEL_ADC_CLKSEL_MASK 0x0c +#define WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK 0x00 +#define WM8580_CLKSEL_ADC_CLKSEL_PLLA 0x04 +#define WM8580_CLKSEL_ADC_CLKSEL_PLLB 0x08 +#define WM8580_CLKSEL_ADC_CLKSEL_MCLK 0x0c + /* AIF control 1 (registers 9h-bh) */ #define WM8580_AIF_RATE_MASK 0x7 #define WM8580_AIF_RATE_128 0x0 @@ -121,15 +129,16 @@ #define WM8580_AIF_BCLKSEL_MASK 0x18 #define WM8580_AIF_BCLKSEL_64 0x00 -#define WM8580_AIF_BCLKSEL_128 0x08 -#define WM8580_AIF_BCLKSEL_256 0x10 +#define WM8580_AIF_BCLKSEL_32 0x08 +#define WM8580_AIF_BCLKSEL_16 0x10 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18 #define WM8580_AIF_MS 0x20 #define WM8580_AIF_CLKSRC_MASK 0xc0 +#define WM8580_AIF_CLKSRC_ADCMCLK 0x00 #define WM8580_AIF_CLKSRC_PLLA 0x40 -#define WM8580_AIF_CLKSRC_PLLB 0x40 +#define WM8580_AIF_CLKSRC_PLLB 0x80 #define WM8580_AIF_CLKSRC_MCLK 0xc0 /* AIF control 2 (registers ch-eh) */ @@ -604,12 +613,13 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, switch (div) { case WM8580_CLKSRC_MCLK: - /* Input */ + reg |= WM8580_PLLB4_MCLKOUTSRC_MCLK; break; case WM8580_CLKSRC_PLLA: reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA; break; + case WM8580_CLKSRC_PLLB: reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB; break; @@ -630,6 +640,7 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, switch (div) { case WM8580_CLKSRC_MCLK: + reg |= WM8580_CLKSEL_DAC_CLKSEL_MCLK; break; case WM8580_CLKSRC_PLLA: @@ -646,6 +657,59 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, snd_soc_write(codec, WM8580_CLKSEL, reg); break; + case WM8580_ADC_CLKSEL: + reg = snd_soc_read(codec, WM8580_CLKSEL); + reg &= ~WM8580_CLKSEL_ADC_CLKSEL_MASK; + + switch (div) { + case WM8580_CLKSRC_ADCMCLK: + reg |= WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK; + break; + + case WM8580_CLKSRC_MCLK: + reg |= WM8580_CLKSEL_ADC_CLKSEL_MCLK; + break; + + case WM8580_CLKSRC_PLLA: + reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLA; + break; + + case WM8580_CLKSRC_PLLB: + reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLB; + break; + + default: + return -EINVAL; + } + snd_soc_write(codec, WM8580_CLKSEL, reg); + break; + + case WM8580_PAIF_CLKSEL: + reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id); + reg &= ~WM8580_AIF_CLKSRC_MASK; + switch (div) { + case WM8580_CLKSRC_ADCMCLK: + reg |= WM8580_AIF_CLKSRC_ADCMCLK; + break; + + case WM8580_CLKSRC_PLLA: + reg |= WM8580_AIF_CLKSRC_PLLA; + break; + + case WM8580_CLKSRC_PLLB: + reg |= WM8580_AIF_CLKSRC_PLLB; + break; + + case WM8580_CLKSRC_MCLK: + reg |= WM8580_AIF_CLKSRC_MCLK; + break; + + default: + return -EINVAL; + } + snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg); + break; + case WM8580_CLKOUTSRC: reg = snd_soc_read(codec, WM8580_PLLB4); reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK; @@ -672,6 +736,67 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, snd_soc_write(codec, WM8580_PLLB4, reg); break; + case WM8580_MCLKRATIO: + reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id); + reg &= ~WM8580_AIF_RATE_MASK; + switch(div) { + case 128: + reg |= WM8580_AIF_RATE_128; + break; + + case 192: + reg |= WM8580_AIF_RATE_192; + break; + + case 256: + reg |= WM8580_AIF_RATE_256; + break; + + case 384: + reg |= WM8580_AIF_RATE_384; + break; + + case 512: + reg |= WM8580_AIF_RATE_512; + break; + + case 768: + reg |= WM8580_AIF_RATE_768; + break; + + case 1152: + reg |= WM8580_AIF_RATE_1152; + break; + + default: + return -EINVAL; + } + snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg); + break; + + case WM8580_BCLKRATIO: + reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id); + reg &= ~WM8580_AIF_BCLKSEL_MASK; + switch(div) { + case 64: + reg |= WM8580_AIF_BCLKSEL_64; + break; + + case 32: + reg |= WM8580_AIF_BCLKSEL_32; + break; + + case 16: + reg |= WM8580_AIF_BCLKSEL_16; + break; + + default: + reg |= WM8580_AIF_BCLKSEL_SYSCLK; + break; + } + snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg); + break; + default: return -EINVAL; } diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h index 0dfb5dd..0ecdbfa 100644 --- a/sound/soc/codecs/wm8580.h +++ b/sound/soc/codecs/wm8580.h @@ -18,16 +18,21 @@ #define WM8580_PLLA 1 #define WM8580_PLLB 2 -#define WM8580_MCLK 1 -#define WM8580_DAC_CLKSEL 2 -#define WM8580_CLKOUTSRC 3 - -#define WM8580_CLKSRC_MCLK 1 -#define WM8580_CLKSRC_PLLA 2 -#define WM8580_CLKSRC_PLLB 3 -#define WM8580_CLKSRC_OSC 4 -#define WM8580_CLKSRC_NONE 5 - +#define WM8580_MCLK 1 +#define WM8580_DAC_CLKSEL 2 +#define WM8580_ADC_CLKSEL 3 +#define WM8580_PAIF_CLKSEL 4 +#define WM8580_CLKOUTSRC 5 +#define WM8580_MCLKRATIO 6 +#define WM8580_BCLKRATIO 7 + +#define WM8580_CLKSRC_ADCMCLK 0 +#define WM8580_CLKSRC_MCLK 1 +#define WM8580_CLKSRC_PLLA 2 +#define WM8580_CLKSRC_PLLB 3 +#define WM8580_CLKSRC_OSC 4 +#define WM8580_CLKSRC_NONE 5 + #define WM8580_DAI_PAIFRX 0 #define WM8580_DAI_PAIFTX 1 -- 1.6.2.5

2 8

[alsa-devel] [PATCH] ASoC: Factor out I2C 8 bit address 8 bit data I/O
by Joonyoung Shim 07 Sep '09

07 Sep '09

This patch is for the AK4671 codec driver using this format. Signed-off-by: Joonyoung Shim <jy0922.shim(a)samsung.com> --- sound/soc/soc-cache.c | 30 ++++++++++++++++++++++++++++++ 1 files changed, 30 insertions(+), 0 deletions(-) diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c index c8ceddc..404231e 100644 --- a/sound/soc/soc-cache.c +++ b/sound/soc/soc-cache.c @@ -77,6 +77,35 @@ static int snd_soc_7_9_spi_write(void *control_data, const char *data, #define snd_soc_7_9_spi_write NULL #endif +static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 *cache = codec->reg_cache; + u8 data[2]; + + BUG_ON(codec->volatile_register); + + data[0] = reg & 0xff; + data[1] = value & 0xff; + + if (reg < codec->reg_cache_size) + cache[reg] = value; + + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 *cache = codec->reg_cache; + if (reg >= codec->reg_cache_size) + return -1; + return cache[reg]; +} + static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value) { @@ -151,6 +180,7 @@ static struct { unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int); } io_types[] = { { 7, 9, snd_soc_7_9_write, snd_soc_7_9_spi_write, snd_soc_7_9_read }, + { 8, 8, snd_soc_8_8_write, NULL, snd_soc_8_8_read, NULL }, { 8, 16, snd_soc_8_16_write, NULL, snd_soc_8_16_read, snd_soc_8_16_read_i2c }, }; -- 1.6.0.4

3 5

[alsa-devel] [PATCH v2] ASoC: AK4671: add ak4671 codec driver
by Joonyoung Shim 07 Sep '09

07 Sep '09

The AK4671 is a stereo CODEC with a built-in Microphone-Amplifier, Receiver-Amplifier and Headphone-Amplifier. The datasheet for the ak4671 can find at the following url: http://www.asahi-kasei.co.jp/akm/en/product/ak4671/ak4671_f01e.pdf Signed-off-by: Joonyoung Shim <jy0922.shim(a)samsung.com> --- Change log: v2: - use soc-cache - remove unused pll_on variable - add event handler for DAC and ADC - remove unnecessary comments and PM functions - modify error handling in ak4671_register function sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/ak4671.c | 845 +++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/ak4671.h | 156 +++++++++ 4 files changed, 1007 insertions(+), 0 deletions(-) create mode 100644 sound/soc/codecs/ak4671.c create mode 100644 sound/soc/codecs/ak4671.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 0edca93..a2bb659 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -19,6 +19,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_AK4104 if SPI_MASTER select SND_SOC_AK4535 if I2C select SND_SOC_AK4642 if I2C + select SND_SOC_AK4671 if I2C select SND_SOC_CS4270 if I2C select SND_SOC_MAX9877 if I2C select SND_SOC_PCM3008 @@ -96,6 +97,9 @@ config SND_SOC_AK4535 config SND_SOC_AK4642 tristate +config SND_SOC_AK4671 + tristate + # Cirrus Logic CS4270 Codec config SND_SOC_CS4270 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index fb4af28..13f7b4f 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -6,6 +6,7 @@ snd-soc-ad73311-objs := ad73311.o snd-soc-ak4104-objs := ak4104.o snd-soc-ak4535-objs := ak4535.o snd-soc-ak4642-objs := ak4642.o +snd-soc-ak4671-objs := ak4671.o snd-soc-cs4270-objs := cs4270.o snd-soc-cx20442-objs := cx20442.o snd-soc-l3-objs := l3.o @@ -56,6 +57,7 @@ obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o obj-$(CONFIG_SND_SOC_AK4104) += snd-soc-ak4104.o obj-$(CONFIG_SND_SOC_AK4535) += snd-soc-ak4535.o obj-$(CONFIG_SND_SOC_AK4642) += snd-soc-ak4642.o +obj-$(CONFIG_SND_SOC_AK4671) += snd-soc-ak4671.o obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o diff --git a/sound/soc/codecs/ak4671.c b/sound/soc/codecs/ak4671.c new file mode 100644 index 0000000..cb6735f --- /dev/null +++ b/sound/soc/codecs/ak4671.c @@ -0,0 +1,845 @@ +/* + * ak4671.c -- audio driver for AK4671 + * + * Copyright (C) 2009 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#include "ak4671.h" + +static struct snd_soc_codec *ak4671_codec; + +/* codec private data */ +struct ak4671_priv { + struct snd_soc_codec codec; + u8 reg_cache[AK4671_CACHEREGNUM]; +}; + +/* ak4671 register cache & default register settings */ +static const u8 ak4671_reg[AK4671_CACHEREGNUM] = { + 0x00, /* AK4671_AD_DA_POWER_MANAGEMENT (0x00) */ + 0xf6, /* AK4671_PLL_MODE_SELECT0 (0x01) */ + 0x00, /* AK4671_PLL_MODE_SELECT1 (0x02) */ + 0x02, /* AK4671_FORMAT_SELECT (0x03) */ + 0x00, /* AK4671_MIC_SIGNAL_SELECT (0x04) */ + 0x55, /* AK4671_MIC_AMP_GAIN (0x05) */ + 0x00, /* AK4671_MIXING_POWER_MANAGEMENT0 (0x06) */ + 0x00, /* AK4671_MIXING_POWER_MANAGEMENT1 (0x07) */ + 0xb5, /* AK4671_OUTPUT_VOLUME_CONTROL (0x08) */ + 0x00, /* AK4671_LOUT1_SIGNAL_SELECT (0x09) */ + 0x00, /* AK4671_ROUT1_SIGNAL_SELECT (0x0a) */ + 0x00, /* AK4671_LOUT2_SIGNAL_SELECT (0x0b) */ + 0x00, /* AK4671_ROUT2_SIGNAL_SELECT (0x0c) */ + 0x00, /* AK4671_LOUT3_SIGNAL_SELECT (0x0d) */ + 0x00, /* AK4671_ROUT3_SIGNAL_SELECT (0x0e) */ + 0x00, /* AK4671_LOUT1_POWER_MANAGERMENT (0x0f) */ + 0x00, /* AK4671_LOUT2_POWER_MANAGERMENT (0x10) */ + 0x80, /* AK4671_LOUT3_POWER_MANAGERMENT (0x11) */ + 0x91, /* AK4671_LCH_INPUT_VOLUME_CONTROL (0x12) */ + 0x91, /* AK4671_RCH_INPUT_VOLUME_CONTROL (0x13) */ + 0xe1, /* AK4671_ALC_REFERENCE_SELECT (0x14) */ + 0x00, /* AK4671_DIGITAL_MIXING_CONTROL (0x15) */ + 0x00, /* AK4671_ALC_TIMER_SELECT (0x16) */ + 0x00, /* AK4671_ALC_MODE_CONTROL (0x17) */ + 0x02, /* AK4671_MODE_CONTROL1 (0x18) */ + 0x01, /* AK4671_MODE_CONTROL2 (0x19) */ + 0x18, /* AK4671_LCH_OUTPUT_VOLUME_CONTROL (0x1a) */ + 0x18, /* AK4671_RCH_OUTPUT_VOLUME_CONTROL (0x1b) */ + 0x00, /* AK4671_SIDETONE_A_CONTROL (0x1c) */ + 0x02, /* AK4671_DIGITAL_FILTER_SELECT (0x1d) */ + 0x00, /* AK4671_FIL3_COEFFICIENT0 (0x1e) */ + 0x00, /* AK4671_FIL3_COEFFICIENT1 (0x1f) */ + 0x00, /* AK4671_FIL3_COEFFICIENT2 (0x20) */ + 0x00, /* AK4671_FIL3_COEFFICIENT3 (0x21) */ + 0x00, /* AK4671_EQ_COEFFICIENT0 (0x22) */ + 0x00, /* AK4671_EQ_COEFFICIENT1 (0x23) */ + 0x00, /* AK4671_EQ_COEFFICIENT2 (0x24) */ + 0x00, /* AK4671_EQ_COEFFICIENT3 (0x25) */ + 0x00, /* AK4671_EQ_COEFFICIENT4 (0x26) */ + 0x00, /* AK4671_EQ_COEFFICIENT5 (0x27) */ + 0xa9, /* AK4671_FIL1_COEFFICIENT0 (0x28) */ + 0x1f, /* AK4671_FIL1_COEFFICIENT1 (0x29) */ + 0xad, /* AK4671_FIL1_COEFFICIENT2 (0x2a) */ + 0x20, /* AK4671_FIL1_COEFFICIENT3 (0x2b) */ + 0x00, /* AK4671_FIL2_COEFFICIENT0 (0x2c) */ + 0x00, /* AK4671_FIL2_COEFFICIENT1 (0x2d) */ + 0x00, /* AK4671_FIL2_COEFFICIENT2 (0x2e) */ + 0x00, /* AK4671_FIL2_COEFFICIENT3 (0x2f) */ + 0x00, /* AK4671_DIGITAL_FILTER_SELECT2 (0x30) */ + 0x00, /* this register not used */ + 0x00, /* AK4671_E1_COEFFICIENT0 (0x32) */ + 0x00, /* AK4671_E1_COEFFICIENT1 (0x33) */ + 0x00, /* AK4671_E1_COEFFICIENT2 (0x34) */ + 0x00, /* AK4671_E1_COEFFICIENT3 (0x35) */ + 0x00, /* AK4671_E1_COEFFICIENT4 (0x36) */ + 0x00, /* AK4671_E1_COEFFICIENT5 (0x37) */ + 0x00, /* AK4671_E2_COEFFICIENT0 (0x38) */ + 0x00, /* AK4671_E2_COEFFICIENT1 (0x39) */ + 0x00, /* AK4671_E2_COEFFICIENT2 (0x3a) */ + 0x00, /* AK4671_E2_COEFFICIENT3 (0x3b) */ + 0x00, /* AK4671_E2_COEFFICIENT4 (0x3c) */ + 0x00, /* AK4671_E2_COEFFICIENT5 (0x3d) */ + 0x00, /* AK4671_E3_COEFFICIENT0 (0x3e) */ + 0x00, /* AK4671_E3_COEFFICIENT1 (0x3f) */ + 0x00, /* AK4671_E3_COEFFICIENT2 (0x40) */ + 0x00, /* AK4671_E3_COEFFICIENT3 (0x41) */ + 0x00, /* AK4671_E3_COEFFICIENT4 (0x42) */ + 0x00, /* AK4671_E3_COEFFICIENT5 (0x43) */ + 0x00, /* AK4671_E4_COEFFICIENT0 (0x44) */ + 0x00, /* AK4671_E4_COEFFICIENT1 (0x45) */ + 0x00, /* AK4671_E4_COEFFICIENT2 (0x46) */ + 0x00, /* AK4671_E4_COEFFICIENT3 (0x47) */ + 0x00, /* AK4671_E4_COEFFICIENT4 (0x48) */ + 0x00, /* AK4671_E4_COEFFICIENT5 (0x49) */ + 0x00, /* AK4671_E5_COEFFICIENT0 (0x4a) */ + 0x00, /* AK4671_E5_COEFFICIENT1 (0x4b) */ + 0x00, /* AK4671_E5_COEFFICIENT2 (0x4c) */ + 0x00, /* AK4671_E5_COEFFICIENT3 (0x4d) */ + 0x00, /* AK4671_E5_COEFFICIENT4 (0x4e) */ + 0x00, /* AK4671_E5_COEFFICIENT5 (0x4f) */ + 0x88, /* AK4671_EQ_CONTROL_250HZ_100HZ (0x50) */ + 0x88, /* AK4671_EQ_CONTROL_3500HZ_1KHZ (0x51) */ + 0x08, /* AK4671_EQ_CONTRO_10KHZ (0x52) */ + 0x00, /* AK4671_PCM_IF_CONTROL0 (0x53) */ + 0x00, /* AK4671_PCM_IF_CONTROL1 (0x54) */ + 0x00, /* AK4671_PCM_IF_CONTROL2 (0x55) */ + 0x18, /* AK4671_DIGITAL_VOLUME_B_CONTROL (0x56) */ + 0x18, /* AK4671_DIGITAL_VOLUME_C_CONTROL (0x57) */ + 0x00, /* AK4671_SIDETONE_VOLUME_CONTROL (0x58) */ + 0x00, /* AK4671_DIGITAL_MIXING_CONTROL2 (0x59) */ + 0x00, /* AK4671_SAR_ADC_CONTROL (0x5a) */ +}; + +/* + * LOUT1/ROUT1 output volume control: + * from -24 to 6 dB in 6 dB steps (mute instead of -30 dB) + */ +static DECLARE_TLV_DB_SCALE(out1_tlv, -3000, 600, 1); + +/* + * LOUT2/ROUT2 output volume control: + * from -33 to 6 dB in 3 dB steps (mute instead of -33 dB) + */ +static DECLARE_TLV_DB_SCALE(out2_tlv, -3300, 300, 1); + +/* + * LOUT3/ROUT3 output volume control: + * from -6 to 3 dB in 3 dB steps + */ +static DECLARE_TLV_DB_SCALE(out3_tlv, -600, 300, 0); + +/* + * Mic amp gain control: + * from -15 to 30 dB in 3 dB steps + * REVISIT: The actual min value(0x01) is -12 dB and the reg value 0x00 is not + * available + */ +static DECLARE_TLV_DB_SCALE(mic_amp_tlv, -1500, 300, 0); + +static const struct snd_kcontrol_new ak4671_snd_controls[] = { + /* Common playback gain controls */ + SOC_SINGLE_TLV("Line Output1 Playback Volume", + AK4671_OUTPUT_VOLUME_CONTROL, 0, 0x6, 0, out1_tlv), + SOC_SINGLE_TLV("Headphone Output2 Playback Volume", + AK4671_OUTPUT_VOLUME_CONTROL, 4, 0xd, 0, out2_tlv), + SOC_SINGLE_TLV("Line Output3 Playback Volume", + AK4671_LOUT3_POWER_MANAGERMENT, 6, 0x3, 0, out3_tlv), + + /* Common capture gain controls */ + SOC_DOUBLE_TLV("Mic Amp Capture Volume", + AK4671_MIC_AMP_GAIN, 0, 4, 0xf, 0, mic_amp_tlv), +}; + +/* event handlers */ +static int ak4671_out2_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + u8 reg; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + reg = snd_soc_read(codec, AK4671_LOUT2_POWER_MANAGERMENT); + reg |= AK4671_MUTEN; + snd_soc_write(codec, AK4671_LOUT2_POWER_MANAGERMENT, reg); + break; + case SND_SOC_DAPM_PRE_PMD: + reg = snd_soc_read(codec, AK4671_LOUT2_POWER_MANAGERMENT); + reg &= ~AK4671_MUTEN; + snd_soc_write(codec, AK4671_LOUT2_POWER_MANAGERMENT, reg); + break; + } + + return 0; +} + +static int ak4671_pll_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + u8 reg; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + reg = snd_soc_read(codec, AK4671_PLL_MODE_SELECT1); + reg |= AK4671_PMPLL; + snd_soc_write(codec, AK4671_PLL_MODE_SELECT1, reg); + /* pll lock time: max 40ms */ + mdelay(40); + break; + case SND_SOC_DAPM_POST_PMD: + reg = snd_soc_read(codec, AK4671_PLL_MODE_SELECT1); + reg &= ~AK4671_PMPLL; + snd_soc_write(codec, AK4671_PLL_MODE_SELECT1, reg); + break; + } + + return 0; +} + +/* Output Mixers */ +static const struct snd_kcontrol_new ak4671_lout1_mixer_controls[] = { + SOC_DAPM_SINGLE("DACL", AK4671_LOUT1_SIGNAL_SELECT, 0, 1, 0), + SOC_DAPM_SINGLE("LINL1", AK4671_LOUT1_SIGNAL_SELECT, 1, 1, 0), + SOC_DAPM_SINGLE("LINL2", AK4671_LOUT1_SIGNAL_SELECT, 2, 1, 0), + SOC_DAPM_SINGLE("LINL3", AK4671_LOUT1_SIGNAL_SELECT, 3, 1, 0), + SOC_DAPM_SINGLE("LINL4", AK4671_LOUT1_SIGNAL_SELECT, 4, 1, 0), + SOC_DAPM_SINGLE("LOOPL", AK4671_LOUT1_SIGNAL_SELECT, 5, 1, 0), +}; + +static const struct snd_kcontrol_new ak4671_rout1_mixer_controls[] = { + SOC_DAPM_SINGLE("DACR", AK4671_ROUT1_SIGNAL_SELECT, 0, 1, 0), + SOC_DAPM_SINGLE("RINR1", AK4671_ROUT1_SIGNAL_SELECT, 1, 1, 0), + SOC_DAPM_SINGLE("RINR2", AK4671_ROUT1_SIGNAL_SELECT, 2, 1, 0), + SOC_DAPM_SINGLE("RINR3", AK4671_ROUT1_SIGNAL_SELECT, 3, 1, 0), + SOC_DAPM_SINGLE("RINR4", AK4671_ROUT1_SIGNAL_SELECT, 4, 1, 0), + SOC_DAPM_SINGLE("LOOPR", AK4671_ROUT1_SIGNAL_SELECT, 5, 1, 0), +}; + +static const struct snd_kcontrol_new ak4671_lout2_mixer_controls[] = { + SOC_DAPM_SINGLE("DACHL", AK4671_LOUT2_SIGNAL_SELECT, 0, 1, 0), + SOC_DAPM_SINGLE("LINH1", AK4671_LOUT2_SIGNAL_SELECT, 1, 1, 0), + SOC_DAPM_SINGLE("LINH2", AK4671_LOUT2_SIGNAL_SELECT, 2, 1, 0), + SOC_DAPM_SINGLE("LINH3", AK4671_LOUT2_SIGNAL_SELECT, 3, 1, 0), + SOC_DAPM_SINGLE("LINH4", AK4671_LOUT2_SIGNAL_SELECT, 4, 1, 0), + SOC_DAPM_SINGLE("LOOPHL", AK4671_LOUT2_SIGNAL_SELECT, 5, 1, 0), +}; + +static const struct snd_kcontrol_new ak4671_rout2_mixer_controls[] = { + SOC_DAPM_SINGLE("DACHR", AK4671_ROUT2_SIGNAL_SELECT, 0, 1, 0), + SOC_DAPM_SINGLE("RINH1", AK4671_ROUT2_SIGNAL_SELECT, 1, 1, 0), + SOC_DAPM_SINGLE("RINH2", AK4671_ROUT2_SIGNAL_SELECT, 2, 1, 0), + SOC_DAPM_SINGLE("RINH3", AK4671_ROUT2_SIGNAL_SELECT, 3, 1, 0), + SOC_DAPM_SINGLE("RINH4", AK4671_ROUT2_SIGNAL_SELECT, 4, 1, 0), + SOC_DAPM_SINGLE("LOOPHR", AK4671_ROUT2_SIGNAL_SELECT, 5, 1, 0), +}; + +static const struct snd_kcontrol_new ak4671_lout3_mixer_controls[] = { + SOC_DAPM_SINGLE("DACSL", AK4671_LOUT3_SIGNAL_SELECT, 0, 1, 0), + SOC_DAPM_SINGLE("LINS1", AK4671_LOUT3_SIGNAL_SELECT, 1, 1, 0), + SOC_DAPM_SINGLE("LINS2", AK4671_LOUT3_SIGNAL_SELECT, 2, 1, 0), + SOC_DAPM_SINGLE("LINS3", AK4671_LOUT3_SIGNAL_SELECT, 3, 1, 0), + SOC_DAPM_SINGLE("LINS4", AK4671_LOUT3_SIGNAL_SELECT, 4, 1, 0), + SOC_DAPM_SINGLE("LOOPSL", AK4671_LOUT3_SIGNAL_SELECT, 5, 1, 0), +}; + +static const struct snd_kcontrol_new ak4671_rout3_mixer_controls[] = { + SOC_DAPM_SINGLE("DACSR", AK4671_ROUT3_SIGNAL_SELECT, 0, 1, 0), + SOC_DAPM_SINGLE("RINS1", AK4671_ROUT3_SIGNAL_SELECT, 1, 1, 0), + SOC_DAPM_SINGLE("RINS2", AK4671_ROUT3_SIGNAL_SELECT, 2, 1, 0), + SOC_DAPM_SINGLE("RINS3", AK4671_ROUT3_SIGNAL_SELECT, 3, 1, 0), + SOC_DAPM_SINGLE("RINS4", AK4671_ROUT3_SIGNAL_SELECT, 4, 1, 0), + SOC_DAPM_SINGLE("LOOPSR", AK4671_ROUT3_SIGNAL_SELECT, 5, 1, 0), +}; + +/* Input MUXs */ +static const char *ak4671_lin_mux_texts[] = + {"LIN1", "LIN2", "LIN3", "LIN4"}; +static const struct soc_enum ak4671_lin_mux_enum = + SOC_ENUM_SINGLE(AK4671_MIC_SIGNAL_SELECT, 0, + ARRAY_SIZE(ak4671_lin_mux_texts), + ak4671_lin_mux_texts); +static const struct snd_kcontrol_new ak4671_lin_mux_control = + SOC_DAPM_ENUM("Route", ak4671_lin_mux_enum); + +static const char *ak4671_rin_mux_texts[] = + {"RIN1", "RIN2", "RIN3", "RIN4"}; +static const struct soc_enum ak4671_rin_mux_enum = + SOC_ENUM_SINGLE(AK4671_MIC_SIGNAL_SELECT, 2, + ARRAY_SIZE(ak4671_rin_mux_texts), + ak4671_rin_mux_texts); +static const struct snd_kcontrol_new ak4671_rin_mux_control = + SOC_DAPM_ENUM("Route", ak4671_rin_mux_enum); + +static const struct snd_soc_dapm_widget ak4671_dapm_widgets[] = { + /* Inputs */ + SND_SOC_DAPM_INPUT("LIN1"), + SND_SOC_DAPM_INPUT("RIN1"), + SND_SOC_DAPM_INPUT("LIN2"), + SND_SOC_DAPM_INPUT("RIN2"), + SND_SOC_DAPM_INPUT("LIN3"), + SND_SOC_DAPM_INPUT("RIN3"), + SND_SOC_DAPM_INPUT("LIN4"), + SND_SOC_DAPM_INPUT("RIN4"), + + /* Outputs */ + SND_SOC_DAPM_OUTPUT("LOUT1"), + SND_SOC_DAPM_OUTPUT("ROUT1"), + SND_SOC_DAPM_OUTPUT("LOUT2"), + SND_SOC_DAPM_OUTPUT("ROUT2"), + SND_SOC_DAPM_OUTPUT("LOUT3"), + SND_SOC_DAPM_OUTPUT("ROUT3"), + + /* DAC */ + SND_SOC_DAPM_DAC_E("DAC Left", "Left HiFi Playback", + AK4671_AD_DA_POWER_MANAGEMENT, 6, 0, ak4671_pll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_DAC_E("DAC Right", "Right HiFi Playback", + AK4671_AD_DA_POWER_MANAGEMENT, 7, 0, ak4671_pll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + /* ADC */ + SND_SOC_DAPM_ADC_E("ADC Left", "Left HiFi Capture", + AK4671_AD_DA_POWER_MANAGEMENT, 4, 0, ak4671_pll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_ADC_E("ADC Right", "Right HiFi Capture", + AK4671_AD_DA_POWER_MANAGEMENT, 5, 0, ak4671_pll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + /* PGA */ + SND_SOC_DAPM_PGA("LOUT2 Mix Amp", + AK4671_LOUT2_POWER_MANAGERMENT, 5, 0, NULL, 0), + SND_SOC_DAPM_PGA("ROUT2 Mix Amp", + AK4671_LOUT2_POWER_MANAGERMENT, 6, 0, NULL, 0), + + SND_SOC_DAPM_PGA("LIN1 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("RIN1 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 1, 0, NULL, 0), + SND_SOC_DAPM_PGA("LIN2 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 2, 0, NULL, 0), + SND_SOC_DAPM_PGA("RIN2 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 3, 0, NULL, 0), + SND_SOC_DAPM_PGA("LIN3 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 4, 0, NULL, 0), + SND_SOC_DAPM_PGA("RIN3 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 5, 0, NULL, 0), + SND_SOC_DAPM_PGA("LIN4 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 6, 0, NULL, 0), + SND_SOC_DAPM_PGA("RIN4 Mixing Circuit", + AK4671_MIXING_POWER_MANAGEMENT1, 7, 0, NULL, 0), + + /* Output Mixers */ + SND_SOC_DAPM_MIXER("LOUT1 Mixer", AK4671_LOUT1_POWER_MANAGERMENT, 0, 0, + &ak4671_lout1_mixer_controls[0], + ARRAY_SIZE(ak4671_lout1_mixer_controls)), + SND_SOC_DAPM_MIXER("ROUT1 Mixer", AK4671_LOUT1_POWER_MANAGERMENT, 1, 0, + &ak4671_rout1_mixer_controls[0], + ARRAY_SIZE(ak4671_rout1_mixer_controls)), + SND_SOC_DAPM_MIXER_E("LOUT2 Mixer", AK4671_LOUT2_POWER_MANAGERMENT, + 0, 0, &ak4671_lout2_mixer_controls[0], + ARRAY_SIZE(ak4671_lout2_mixer_controls), + ak4671_out2_event, + SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_MIXER_E("ROUT2 Mixer", AK4671_LOUT2_POWER_MANAGERMENT, + 1, 0, &ak4671_rout2_mixer_controls[0], + ARRAY_SIZE(ak4671_rout2_mixer_controls), + ak4671_out2_event, + SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_MIXER("LOUT3 Mixer", AK4671_LOUT3_POWER_MANAGERMENT, 0, 0, + &ak4671_lout3_mixer_controls[0], + ARRAY_SIZE(ak4671_lout3_mixer_controls)), + SND_SOC_DAPM_MIXER("ROUT3 Mixer", AK4671_LOUT3_POWER_MANAGERMENT, 1, 0, + &ak4671_rout3_mixer_controls[0], + ARRAY_SIZE(ak4671_rout3_mixer_controls)), + + /* Input MUXs */ + SND_SOC_DAPM_MUX("LIN MUX", AK4671_AD_DA_POWER_MANAGEMENT, 2, 0, + &ak4671_lin_mux_control), + SND_SOC_DAPM_MUX("RIN MUX", AK4671_AD_DA_POWER_MANAGEMENT, 3, 0, + &ak4671_rin_mux_control), + + /* Mic Power */ + SND_SOC_DAPM_MICBIAS("Mic Bias", AK4671_AD_DA_POWER_MANAGEMENT, 1, 0), +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* Outputs */ + {"LOUT1", "NULL", "LOUT1 Mixer"}, + {"ROUT1", "NULL", "ROUT1 Mixer"}, + {"LOUT2", "NULL", "LOUT2 Mix Amp"}, + {"ROUT2", "NULL", "ROUT2 Mix Amp"}, + {"LOUT3", "NULL", "LOUT3 Mixer"}, + {"ROUT3", "NULL", "ROUT3 Mixer"}, + + {"LOUT1 Mixer", "DACL", "DAC Left"}, + {"ROUT1 Mixer", "DACR", "DAC Right"}, + {"LOUT2 Mixer", "DACHL", "DAC Left"}, + {"ROUT2 Mixer", "DACHR", "DAC Right"}, + {"LOUT2 Mix Amp", "NULL", "LOUT2 Mixer"}, + {"ROUT2 Mix Amp", "NULL", "ROUT2 Mixer"}, + {"LOUT3 Mixer", "DACSL", "DAC Left"}, + {"ROUT3 Mixer", "DACSR", "DAC Right"}, + + /* Inputs */ + {"LIN MUX", "LIN1", "LIN1"}, + {"LIN MUX", "LIN2", "LIN2"}, + {"LIN MUX", "LIN3", "LIN3"}, + {"LIN MUX", "LIN4", "LIN4"}, + + {"RIN MUX", "RIN1", "RIN1"}, + {"RIN MUX", "RIN2", "RIN2"}, + {"RIN MUX", "RIN3", "RIN3"}, + {"RIN MUX", "RIN4", "RIN4"}, + + {"LIN1", NULL, "Mic Bias"}, + {"RIN1", NULL, "Mic Bias"}, + {"LIN2", NULL, "Mic Bias"}, + {"RIN2", NULL, "Mic Bias"}, + + {"ADC Left", "NULL", "LIN MUX"}, + {"ADC Right", "NULL", "RIN MUX"}, + + /* Analog Loops */ + {"LIN1 Mixing Circuit", "NULL", "LIN1"}, + {"RIN1 Mixing Circuit", "NULL", "RIN1"}, + {"LIN2 Mixing Circuit", "NULL", "LIN2"}, + {"RIN2 Mixing Circuit", "NULL", "RIN2"}, + {"LIN3 Mixing Circuit", "NULL", "LIN3"}, + {"RIN3 Mixing Circuit", "NULL", "RIN3"}, + {"LIN4 Mixing Circuit", "NULL", "LIN4"}, + {"RIN4 Mixing Circuit", "NULL", "RIN4"}, + + {"LOUT1 Mixer", "LINL1", "LIN1 Mixing Circuit"}, + {"ROUT1 Mixer", "RINR1", "RIN1 Mixing Circuit"}, + {"LOUT2 Mixer", "LINH1", "LIN1 Mixing Circuit"}, + {"ROUT2 Mixer", "RINH1", "RIN1 Mixing Circuit"}, + {"LOUT3 Mixer", "LINS1", "LIN1 Mixing Circuit"}, + {"ROUT3 Mixer", "RINS1", "RIN1 Mixing Circuit"}, + + {"LOUT1 Mixer", "LINL2", "LIN2 Mixing Circuit"}, + {"ROUT1 Mixer", "RINR2", "RIN2 Mixing Circuit"}, + {"LOUT2 Mixer", "LINH2", "LIN2 Mixing Circuit"}, + {"ROUT2 Mixer", "RINH2", "RIN2 Mixing Circuit"}, + {"LOUT3 Mixer", "LINS2", "LIN2 Mixing Circuit"}, + {"ROUT3 Mixer", "RINS2", "RIN2 Mixing Circuit"}, + + {"LOUT1 Mixer", "LINL3", "LIN3 Mixing Circuit"}, + {"ROUT1 Mixer", "RINR3", "RIN3 Mixing Circuit"}, + {"LOUT2 Mixer", "LINH3", "LIN3 Mixing Circuit"}, + {"ROUT2 Mixer", "RINH3", "RIN3 Mixing Circuit"}, + {"LOUT3 Mixer", "LINS3", "LIN3 Mixing Circuit"}, + {"ROUT3 Mixer", "RINS3", "RIN3 Mixing Circuit"}, + + {"LOUT1 Mixer", "LINL4", "LIN4 Mixing Circuit"}, + {"ROUT1 Mixer", "RINR4", "RIN4 Mixing Circuit"}, + {"LOUT2 Mixer", "LINH4", "LIN4 Mixing Circuit"}, + {"ROUT2 Mixer", "RINH4", "RIN4 Mixing Circuit"}, + {"LOUT3 Mixer", "LINS4", "LIN4 Mixing Circuit"}, + {"ROUT3 Mixer", "RINS4", "RIN4 Mixing Circuit"}, +}; + +static int ak4671_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, ak4671_dapm_widgets, + ARRAY_SIZE(ak4671_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +static int ak4671_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + u8 fs; + + fs = snd_soc_read(codec, AK4671_PLL_MODE_SELECT0); + fs &= ~AK4671_FS; + + switch (params_rate(params)) { + case 8000: + fs |= AK4671_FS_8KHZ; + break; + case 12000: + fs |= AK4671_FS_12KHZ; + break; + case 16000: + fs |= AK4671_FS_16KHZ; + break; + case 24000: + fs |= AK4671_FS_24KHZ; + break; + case 11025: + fs |= AK4671_FS_11_025KHZ; + break; + case 22050: + fs |= AK4671_FS_22_05KHZ; + break; + case 32000: + fs |= AK4671_FS_32KHZ; + break; + case 44100: + fs |= AK4671_FS_44_1KHZ; + break; + case 48000: + fs |= AK4671_FS_48KHZ; + break; + default: + return -EINVAL; + } + + snd_soc_write(codec, AK4671_PLL_MODE_SELECT0, fs); + + return 0; +} + +static int ak4671_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + u8 pll; + + pll = snd_soc_read(codec, AK4671_PLL_MODE_SELECT0); + pll &= ~AK4671_PLL; + + switch (freq) { + case 11289600: + pll |= AK4671_PLL_11_2896MHZ; + break; + case 12000000: + pll |= AK4671_PLL_12MHZ; + break; + case 12288000: + pll |= AK4671_PLL_12_288MHZ; + break; + case 13000000: + pll |= AK4671_PLL_13MHZ; + break; + case 13500000: + pll |= AK4671_PLL_13_5MHZ; + break; + case 19200000: + pll |= AK4671_PLL_19_2MHZ; + break; + case 24000000: + pll |= AK4671_PLL_24MHZ; + break; + case 26000000: + pll |= AK4671_PLL_26MHZ; + break; + case 27000000: + pll |= AK4671_PLL_27MHZ; + break; + default: + return -EINVAL; + } + + snd_soc_write(codec, AK4671_PLL_MODE_SELECT0, pll); + + return 0; +} + +static int ak4671_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = dai->codec; + u8 mode; + u8 format; + + /* set master/slave audio interface */ + mode = snd_soc_read(codec, AK4671_PLL_MODE_SELECT1); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + mode |= AK4671_M_S; + break; + case SND_SOC_DAIFMT_CBM_CFS: + mode &= ~(AK4671_M_S); + break; + default: + return -EINVAL; + } + + /* interface format */ + format = snd_soc_read(codec, AK4671_FORMAT_SELECT); + format &= ~AK4671_DIF; + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + format |= AK4671_DIF_I2S_MODE; + break; + case SND_SOC_DAIFMT_LEFT_J: + format |= AK4671_DIF_MSB_MODE; + break; + case SND_SOC_DAIFMT_DSP_A: + format |= AK4671_DIF_DSP_MODE; + format |= AK4671_BCKP; + format |= AK4671_MSBS; + break; + default: + return -EINVAL; + } + + /* set mode and format */ + snd_soc_write(codec, AK4671_PLL_MODE_SELECT1, mode); + snd_soc_write(codec, AK4671_FORMAT_SELECT, format); + + return 0; +} + +static int ak4671_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + u8 reg; + + switch (level) { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + case SND_SOC_BIAS_STANDBY: + reg = snd_soc_read(codec, AK4671_AD_DA_POWER_MANAGEMENT); + snd_soc_write(codec, AK4671_AD_DA_POWER_MANAGEMENT, + reg | AK4671_PMVCM); + break; + case SND_SOC_BIAS_OFF: + snd_soc_write(codec, AK4671_AD_DA_POWER_MANAGEMENT, 0x00); + break; + } + codec->bias_level = level; + return 0; +} + +#define AK4671_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_48000) + +#define AK4671_FORMATS SNDRV_PCM_FMTBIT_S16_LE + +static struct snd_soc_dai_ops ak4671_dai_ops = { + .hw_params = ak4671_hw_params, + .set_sysclk = ak4671_set_dai_sysclk, + .set_fmt = ak4671_set_dai_fmt, +}; + +struct snd_soc_dai ak4671_dai = { + .name = "AK4671", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = AK4671_RATES, + .formats = AK4671_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AK4671_RATES, + .formats = AK4671_FORMATS,}, + .ops = &ak4671_dai_ops, +}; +EXPORT_SYMBOL_GPL(ak4671_dai); + +static int ak4671_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + int ret = 0; + + if (ak4671_codec == NULL) { + dev_err(&pdev->dev, "Codec device not registered\n"); + return -ENODEV; + } + + socdev->card->codec = ak4671_codec; + codec = ak4671_codec; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(codec->dev, "failed to create pcms: %d\n", ret); + goto pcm_err; + } + + snd_soc_add_controls(codec, ak4671_snd_controls, + ARRAY_SIZE(ak4671_snd_controls)); + ak4671_add_widgets(codec); + + ret = snd_soc_init_card(socdev); + if (ret < 0) { + dev_err(codec->dev, "failed to register card: %d\n", ret); + goto card_err; + } + + ak4671_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + return ret; +} + +static int ak4671_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_ak4671 = { + .probe = ak4671_probe, + .remove = ak4671_remove, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_ak4671); + +static int ak4671_register(struct ak4671_priv *ak4671, + enum snd_soc_control_type control) +{ + int ret; + struct snd_soc_codec *codec = &ak4671->codec; + + if (ak4671_codec) { + dev_err(codec->dev, "Another AK4671 is registered\n"); + ret = -EINVAL; + goto err; + } + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + codec->private_data = ak4671; + codec->name = "AK4671"; + codec->owner = THIS_MODULE; + codec->bias_level = SND_SOC_BIAS_OFF; + codec->set_bias_level = ak4671_set_bias_level; + codec->dai = &ak4671_dai; + codec->num_dai = 1; + codec->reg_cache_size = AK4671_CACHEREGNUM; + codec->reg_cache = &ak4671->reg_cache; + + memcpy(codec->reg_cache, ak4671_reg, sizeof(ak4671_reg)); + + ret = snd_soc_codec_set_cache_io(codec, 8, 8, control); + if (ret < 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + goto err; + } + + ak4671_dai.dev = codec->dev; + ak4671_codec = codec; + + ret = snd_soc_register_codec(codec); + if (ret != 0) { + dev_err(codec->dev, "Failed to register codec: %d\n", ret); + goto err; + } + + ret = snd_soc_register_dai(&ak4671_dai); + if (ret != 0) { + dev_err(codec->dev, "Failed to register DAI: %d\n", ret); + goto err_codec; + } + + return 0; + +err_codec: + snd_soc_unregister_codec(codec); +err: + kfree(ak4671); + return ret; +} + +static void ak4671_unregister(struct ak4671_priv *ak4671) +{ + ak4671_set_bias_level(&ak4671->codec, SND_SOC_BIAS_OFF); + snd_soc_unregister_dai(&ak4671_dai); + snd_soc_unregister_codec(&ak4671->codec); + kfree(ak4671); + ak4671_codec = NULL; +} + +static int __devinit ak4671_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ak4671_priv *ak4671; + struct snd_soc_codec *codec; + + ak4671 = kzalloc(sizeof(struct ak4671_priv), GFP_KERNEL); + if (ak4671 == NULL) + return -ENOMEM; + + codec = &ak4671->codec; + codec->hw_write = (hw_write_t)i2c_master_send; + + i2c_set_clientdata(client, ak4671); + codec->control_data = client; + + codec->dev = &client->dev; + + return ak4671_register(ak4671, SND_SOC_I2C); +} + +static __devexit int ak4671_i2c_remove(struct i2c_client *client) +{ + struct ak4671_priv *ak4671 = i2c_get_clientdata(client); + + ak4671_unregister(ak4671); + + return 0; +} + +static const struct i2c_device_id ak4671_i2c_id[] = { + { "ak4671", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ak4671_i2c_id); + +static struct i2c_driver ak4671_i2c_driver = { + .driver = { + .name = "ak4671", + .owner = THIS_MODULE, + }, + .probe = ak4671_i2c_probe, + .remove = __devexit_p(ak4671_i2c_remove), + .id_table = ak4671_i2c_id, +}; + +static int __init ak4671_modinit(void) +{ + return i2c_add_driver(&ak4671_i2c_driver); +} +module_init(ak4671_modinit); + +static void __exit ak4671_exit(void) +{ + i2c_del_driver(&ak4671_i2c_driver); +} +module_exit(ak4671_exit); + +MODULE_DESCRIPTION("ASoC AK4671 codec driver"); +MODULE_AUTHOR("Joonyoung Shim <jy0922.shim(a)samsung.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/ak4671.h b/sound/soc/codecs/ak4671.h new file mode 100644 index 0000000..e2fad96 --- /dev/null +++ b/sound/soc/codecs/ak4671.h @@ -0,0 +1,156 @@ +/* + * ak4671.h -- audio driver for AK4671 + * + * Copyright (C) 2009 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _AK4671_H +#define _AK4671_H + +#define AK4671_AD_DA_POWER_MANAGEMENT 0x00 +#define AK4671_PLL_MODE_SELECT0 0x01 +#define AK4671_PLL_MODE_SELECT1 0x02 +#define AK4671_FORMAT_SELECT 0x03 +#define AK4671_MIC_SIGNAL_SELECT 0x04 +#define AK4671_MIC_AMP_GAIN 0x05 +#define AK4671_MIXING_POWER_MANAGEMENT0 0x06 +#define AK4671_MIXING_POWER_MANAGEMENT1 0x07 +#define AK4671_OUTPUT_VOLUME_CONTROL 0x08 +#define AK4671_LOUT1_SIGNAL_SELECT 0x09 +#define AK4671_ROUT1_SIGNAL_SELECT 0x0a +#define AK4671_LOUT2_SIGNAL_SELECT 0x0b +#define AK4671_ROUT2_SIGNAL_SELECT 0x0c +#define AK4671_LOUT3_SIGNAL_SELECT 0x0d +#define AK4671_ROUT3_SIGNAL_SELECT 0x0e +#define AK4671_LOUT1_POWER_MANAGERMENT 0x0f +#define AK4671_LOUT2_POWER_MANAGERMENT 0x10 +#define AK4671_LOUT3_POWER_MANAGERMENT 0x11 +#define AK4671_LCH_INPUT_VOLUME_CONTROL 0x12 +#define AK4671_RCH_INPUT_VOLUME_CONTROL 0x13 +#define AK4671_ALC_REFERENCE_SELECT 0x14 +#define AK4671_DIGITAL_MIXING_CONTROL 0x15 +#define AK4671_ALC_TIMER_SELECT 0x16 +#define AK4671_ALC_MODE_CONTROL 0x17 +#define AK4671_MODE_CONTROL1 0x18 +#define AK4671_MODE_CONTROL2 0x19 +#define AK4671_LCH_OUTPUT_VOLUME_CONTROL 0x1a +#define AK4671_RCH_OUTPUT_VOLUME_CONTROL 0x1b +#define AK4671_SIDETONE_A_CONTROL 0x1c +#define AK4671_DIGITAL_FILTER_SELECT 0x1d +#define AK4671_FIL3_COEFFICIENT0 0x1e +#define AK4671_FIL3_COEFFICIENT1 0x1f +#define AK4671_FIL3_COEFFICIENT2 0x20 +#define AK4671_FIL3_COEFFICIENT3 0x21 +#define AK4671_EQ_COEFFICIENT0 0x22 +#define AK4671_EQ_COEFFICIENT1 0x23 +#define AK4671_EQ_COEFFICIENT2 0x24 +#define AK4671_EQ_COEFFICIENT3 0x25 +#define AK4671_EQ_COEFFICIENT4 0x26 +#define AK4671_EQ_COEFFICIENT5 0x27 +#define AK4671_FIL1_COEFFICIENT0 0x28 +#define AK4671_FIL1_COEFFICIENT1 0x29 +#define AK4671_FIL1_COEFFICIENT2 0x2a +#define AK4671_FIL1_COEFFICIENT3 0x2b +#define AK4671_FIL2_COEFFICIENT0 0x2c +#define AK4671_FIL2_COEFFICIENT1 0x2d +#define AK4671_FIL2_COEFFICIENT2 0x2e +#define AK4671_FIL2_COEFFICIENT3 0x2f +#define AK4671_DIGITAL_FILTER_SELECT2 0x30 +#define AK4671_E1_COEFFICIENT0 0x32 +#define AK4671_E1_COEFFICIENT1 0x33 +#define AK4671_E1_COEFFICIENT2 0x34 +#define AK4671_E1_COEFFICIENT3 0x35 +#define AK4671_E1_COEFFICIENT4 0x36 +#define AK4671_E1_COEFFICIENT5 0x37 +#define AK4671_E2_COEFFICIENT0 0x38 +#define AK4671_E2_COEFFICIENT1 0x39 +#define AK4671_E2_COEFFICIENT2 0x3a +#define AK4671_E2_COEFFICIENT3 0x3b +#define AK4671_E2_COEFFICIENT4 0x3c +#define AK4671_E2_COEFFICIENT5 0x3d +#define AK4671_E3_COEFFICIENT0 0x3e +#define AK4671_E3_COEFFICIENT1 0x3f +#define AK4671_E3_COEFFICIENT2 0x40 +#define AK4671_E3_COEFFICIENT3 0x41 +#define AK4671_E3_COEFFICIENT4 0x42 +#define AK4671_E3_COEFFICIENT5 0x43 +#define AK4671_E4_COEFFICIENT0 0x44 +#define AK4671_E4_COEFFICIENT1 0x45 +#define AK4671_E4_COEFFICIENT2 0x46 +#define AK4671_E4_COEFFICIENT3 0x47 +#define AK4671_E4_COEFFICIENT4 0x48 +#define AK4671_E4_COEFFICIENT5 0x49 +#define AK4671_E5_COEFFICIENT0 0x4a +#define AK4671_E5_COEFFICIENT1 0x4b +#define AK4671_E5_COEFFICIENT2 0x4c +#define AK4671_E5_COEFFICIENT3 0x4d +#define AK4671_E5_COEFFICIENT4 0x4e +#define AK4671_E5_COEFFICIENT5 0x4f +#define AK4671_EQ_CONTROL_250HZ_100HZ 0x50 +#define AK4671_EQ_CONTROL_3500HZ_1KHZ 0x51 +#define AK4671_EQ_CONTRO_10KHZ 0x52 +#define AK4671_PCM_IF_CONTROL0 0x53 +#define AK4671_PCM_IF_CONTROL1 0x54 +#define AK4671_PCM_IF_CONTROL2 0x55 +#define AK4671_DIGITAL_VOLUME_B_CONTROL 0x56 +#define AK4671_DIGITAL_VOLUME_C_CONTROL 0x57 +#define AK4671_SIDETONE_VOLUME_CONTROL 0x58 +#define AK4671_DIGITAL_MIXING_CONTROL2 0x59 +#define AK4671_SAR_ADC_CONTROL 0x5a + +#define AK4671_CACHEREGNUM (AK4671_SAR_ADC_CONTROL + 1) + +/* Bitfield Definitions */ + +/* AK4671_AD_DA_POWER_MANAGEMENT (0x00) Fields */ +#define AK4671_PMVCM 0x01 + +/* AK4671_PLL_MODE_SELECT0 (0x01) Fields */ +#define AK4671_PLL 0x0f +#define AK4671_PLL_11_2896MHZ (4 << 0) +#define AK4671_PLL_12_288MHZ (5 << 0) +#define AK4671_PLL_12MHZ (6 << 0) +#define AK4671_PLL_24MHZ (7 << 0) +#define AK4671_PLL_19_2MHZ (8 << 0) +#define AK4671_PLL_13_5MHZ (12 << 0) +#define AK4671_PLL_27MHZ (13 << 0) +#define AK4671_PLL_13MHZ (14 << 0) +#define AK4671_PLL_26MHZ (15 << 0) +#define AK4671_FS 0xf0 +#define AK4671_FS_8KHZ (0 << 4) +#define AK4671_FS_12KHZ (1 << 4) +#define AK4671_FS_16KHZ (2 << 4) +#define AK4671_FS_24KHZ (3 << 4) +#define AK4671_FS_11_025KHZ (5 << 4) +#define AK4671_FS_22_05KHZ (7 << 4) +#define AK4671_FS_32KHZ (10 << 4) +#define AK4671_FS_48KHZ (11 << 4) +#define AK4671_FS_44_1KHZ (15 << 4) + +/* AK4671_PLL_MODE_SELECT1 (0x02) Fields */ +#define AK4671_PMPLL 0x01 +#define AK4671_M_S 0x02 + +/* AK4671_FORMAT_SELECT (0x03) Fields */ +#define AK4671_DIF 0x03 +#define AK4671_DIF_DSP_MODE (0 << 0) +#define AK4671_DIF_MSB_MODE (2 << 0) +#define AK4671_DIF_I2S_MODE (3 << 0) +#define AK4671_BCKP 0x04 +#define AK4671_MSBS 0x08 +#define AK4671_SDOD 0x10 + +/* AK4671_LOUT2_POWER_MANAGEMENT (0x10) Fields */ +#define AK4671_MUTEN 0x04 + +extern struct snd_soc_dai ak4671_dai; +extern struct snd_soc_codec_device soc_codec_dev_ak4671; + +#endif -- 1.6.0.4

2 2

[alsa-devel] [PATCH] AC97 atmel: add support for AT91(common with AVR32).
by Sedji Gaouaou 07 Sep '09

07 Sep '09

This patch add AC97 support for ATMEL AT91 boards, using the AVR32 code. It is based on Takashi git tree(sound-2.6/for-next). Regards, Sedji Signed-off-by: Sedji Gaouaou <sedji.gaouaou(a)atmel.com> --- sound/atmel/Kconfig | 2 +- sound/atmel/ac97c.c | 364 +++++++++++++++++++++++++++++++++++++-------------- 2 files changed, 268 insertions(+), 98 deletions(-) diff --git a/sound/atmel/Kconfig b/sound/atmel/Kconfig index 6c228a9..94de43a 100644 --- a/sound/atmel/Kconfig +++ b/sound/atmel/Kconfig @@ -12,7 +12,7 @@ config SND_ATMEL_AC97C tristate "Atmel AC97 Controller (AC97C) driver" select SND_PCM select SND_AC97_CODEC - depends on DW_DMAC && AVR32 + depends on (DW_DMAC && AVR32) || ARCH_AT91 help ALSA sound driver for the Atmel AC97 controller. diff --git a/sound/atmel/ac97c.c b/sound/atmel/ac97c.c index 0c0f877..379d7ea 100644 --- a/sound/atmel/ac97c.c +++ b/sound/atmel/ac97c.c @@ -13,6 +13,7 @@ #include <linux/device.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> +#include <linux/atmel_pdc.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/module.h> @@ -31,6 +32,10 @@ #include <linux/dw_dmac.h> +#include <mach/cpu.h> +#include <mach/hardware.h> +#include <mach/gpio.h> + #include "ac97c.h" enum { @@ -63,6 +68,7 @@ struct atmel_ac97c { u64 cur_format; unsigned int cur_rate; unsigned long flags; + int period; /* Serialize access to opened variable */ spinlock_t lock; void __iomem *regs; @@ -167,6 +173,7 @@ static int atmel_ac97c_playback_open(struct snd_pcm_substream *substream) mutex_lock(&opened_mutex); chip->opened++; runtime->hw = atmel_ac97c_hw; + chip->period = 0; if (chip->cur_rate) { runtime->hw.rate_min = chip->cur_rate; runtime->hw.rate_max = chip->cur_rate; @@ -186,6 +193,7 @@ static int atmel_ac97c_capture_open(struct snd_pcm_substream *substream) mutex_lock(&opened_mutex); chip->opened++; runtime->hw = atmel_ac97c_hw; + chip->period = 0; if (chip->cur_rate) { runtime->hw.rate_min = chip->cur_rate; runtime->hw.rate_max = chip->cur_rate; @@ -239,12 +247,14 @@ static int atmel_ac97c_playback_hw_params(struct snd_pcm_substream *substream, retval = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); - if (retval < 0) - return retval; - /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */ - if (retval == 1) - if (test_and_clear_bit(DMA_TX_READY, &chip->flags)) - dw_dma_cyclic_free(chip->dma.tx_chan); + if(cpu_is_at32ap7000()) { + if (retval < 0) + return retval; + /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */ + if (retval == 1) + if (test_and_clear_bit(DMA_TX_READY, &chip->flags)) + dw_dma_cyclic_free(chip->dma.tx_chan); + } /* Set restrictions to params. */ mutex_lock(&opened_mutex); @@ -263,12 +273,14 @@ static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream, retval = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); - if (retval < 0) - return retval; - /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */ - if (retval == 1) - if (test_and_clear_bit(DMA_RX_READY, &chip->flags)) - dw_dma_cyclic_free(chip->dma.rx_chan); + if(cpu_is_at32ap7000()) { + if (retval < 0) + return retval; + /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */ + if (retval == 1) + if (test_and_clear_bit(DMA_RX_READY, &chip->flags)) + dw_dma_cyclic_free(chip->dma.rx_chan); + } /* Set restrictions to params. */ mutex_lock(&opened_mutex); @@ -282,16 +294,20 @@ static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream, static int atmel_ac97c_playback_hw_free(struct snd_pcm_substream *substream) { struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); - if (test_and_clear_bit(DMA_TX_READY, &chip->flags)) - dw_dma_cyclic_free(chip->dma.tx_chan); + if(cpu_is_at32ap7000()) { + if (test_and_clear_bit(DMA_TX_READY, &chip->flags)) + dw_dma_cyclic_free(chip->dma.tx_chan); + } return snd_pcm_lib_free_pages(substream); } static int atmel_ac97c_capture_hw_free(struct snd_pcm_substream *substream) { struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); - if (test_and_clear_bit(DMA_RX_READY, &chip->flags)) - dw_dma_cyclic_free(chip->dma.rx_chan); + if(cpu_is_at32ap7000()) { + if (test_and_clear_bit(DMA_RX_READY, &chip->flags)) + dw_dma_cyclic_free(chip->dma.rx_chan); + } return snd_pcm_lib_free_pages(substream); } @@ -299,6 +315,7 @@ static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream) { struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; + int block_size = frames_to_bytes(runtime, runtime->period_size); unsigned long word = ac97c_readl(chip, OCA); int retval; @@ -324,7 +341,9 @@ static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream) switch (runtime->format) { case SNDRV_PCM_FORMAT_S16_LE: - word |= AC97C_CMR_CEM_LITTLE; + if(cpu_is_at32ap7000()) { + word |= AC97C_CMR_CEM_LITTLE; + } break; case SNDRV_PCM_FORMAT_S16_BE: /* fall through */ word &= ~(AC97C_CMR_CEM_LITTLE); @@ -363,9 +382,18 @@ static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream) dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n", runtime->rate); - if (!test_bit(DMA_TX_READY, &chip->flags)) - retval = atmel_ac97c_prepare_dma(chip, substream, - DMA_TO_DEVICE); + if(cpu_is_at32ap7000()) { + if (!test_bit(DMA_TX_READY, &chip->flags)) + retval = atmel_ac97c_prepare_dma(chip, substream, + DMA_TO_DEVICE); + } else { + /* Initialize and start the PDC */ + writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR); + writel(block_size / 2, chip->regs + ATMEL_PDC_TCR); + writel(runtime->dma_addr + block_size, + chip->regs + ATMEL_PDC_TNPR); + writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR); + } return retval; } @@ -374,6 +402,7 @@ static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream) { struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; + int block_size = frames_to_bytes(runtime, runtime->period_size); unsigned long word = ac97c_readl(chip, ICA); int retval; @@ -415,11 +444,15 @@ static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream) word |= AC97C_CSR_OVRUN; ac97c_writel(chip, CAMR, word); - /* Enable channel A event interrupt */ word = ac97c_readl(chip, IMR); word |= AC97C_SR_CAEVT; - ac97c_writel(chip, IER, word); + ac97c_writel(chip, IER, /*word*/AC97C_SR_CAEVT); + + /* Enable channel A event interrupt */ + /*word = ac97c_readl(chip, IMR); + word |= AC97C_SR_CAEVT; + ac97c_writel(chip, IER, word);*/ /* set variable rate if needed */ if (runtime->rate != 48000) { @@ -438,9 +471,18 @@ static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream) dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n", runtime->rate); - if (!test_bit(DMA_RX_READY, &chip->flags)) - retval = atmel_ac97c_prepare_dma(chip, substream, - DMA_FROM_DEVICE); + if(cpu_is_at32ap7000()) { + if (!test_bit(DMA_RX_READY, &chip->flags)) + retval = atmel_ac97c_prepare_dma(chip, substream, + DMA_FROM_DEVICE); + } else { + /* Initialize and start the PDC */ + writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR); + writel(block_size / 2, chip->regs + ATMEL_PDC_RCR); + writel(runtime->dma_addr + block_size, + chip->regs + ATMEL_PDC_RNPR); + writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR); + } return retval; } @@ -449,7 +491,7 @@ static int atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); - unsigned long camr; + unsigned long camr, ptcr = 0; int retval = 0; camr = ac97c_readl(chip, CAMR); @@ -458,15 +500,23 @@ atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */ case SNDRV_PCM_TRIGGER_RESUME: /* fall through */ case SNDRV_PCM_TRIGGER_START: - retval = dw_dma_cyclic_start(chip->dma.tx_chan); - if (retval) - goto out; - camr |= AC97C_CMR_CENA; + if(cpu_is_at32ap7000()) { + retval = dw_dma_cyclic_start(chip->dma.tx_chan); + if (retval) + goto out; + } else { + ptcr = ATMEL_PDC_TXTEN; + } + camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX; break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */ case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */ case SNDRV_PCM_TRIGGER_STOP: - dw_dma_cyclic_stop(chip->dma.tx_chan); + if(cpu_is_at32ap7000()) { + dw_dma_cyclic_stop(chip->dma.tx_chan); + } else { + ptcr = ATMEL_PDC_TXTDIS; + } if (chip->opened <= 1) camr &= ~AC97C_CMR_CENA; break; @@ -476,6 +526,8 @@ atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd) } ac97c_writel(chip, CAMR, camr); + if(!cpu_is_at32ap7000()) + writel(ptcr, chip->regs + ATMEL_PDC_PTCR); out: return retval; } @@ -484,7 +536,7 @@ static int atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); - unsigned long camr; + unsigned long camr, ptcr = 0; int retval = 0; camr = ac97c_readl(chip, CAMR); @@ -493,15 +545,24 @@ atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */ case SNDRV_PCM_TRIGGER_RESUME: /* fall through */ case SNDRV_PCM_TRIGGER_START: - retval = dw_dma_cyclic_start(chip->dma.rx_chan); - if (retval) - goto out; + if(cpu_is_at32ap7000()) { + retval = dw_dma_cyclic_start(chip->dma.rx_chan); + if (retval) + goto out; + } else { + ptcr = ATMEL_PDC_RXTEN; + } camr |= AC97C_CMR_CENA; break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */ case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */ case SNDRV_PCM_TRIGGER_STOP: - dw_dma_cyclic_stop(chip->dma.rx_chan); + if(cpu_is_at32ap7000()) { + dw_dma_cyclic_stop(chip->dma.rx_chan); + } + else { + ptcr = ATMEL_PDC_RXTDIS; + } if (chip->opened <= 1) camr &= ~AC97C_CMR_CENA; break; @@ -511,6 +572,8 @@ atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd) } ac97c_writel(chip, CAMR, camr); + if(!cpu_is_at32ap7000()) + writel(ptcr, chip->regs + ATMEL_PDC_PTCR); out: return retval; } @@ -523,7 +586,11 @@ atmel_ac97c_playback_pointer(struct snd_pcm_substream *substream) snd_pcm_uframes_t frames; unsigned long bytes; - bytes = dw_dma_get_src_addr(chip->dma.tx_chan); + if(cpu_is_at32ap7000()) { + bytes = dw_dma_get_src_addr(chip->dma.tx_chan); + } else { + bytes = readl(chip->regs + ATMEL_PDC_TPR); + } bytes -= runtime->dma_addr; frames = bytes_to_frames(runtime, bytes); @@ -540,7 +607,11 @@ atmel_ac97c_capture_pointer(struct snd_pcm_substream *substream) snd_pcm_uframes_t frames; unsigned long bytes; - bytes = dw_dma_get_dst_addr(chip->dma.rx_chan); + if(cpu_is_at32ap7000()) { + bytes = dw_dma_get_dst_addr(chip->dma.rx_chan); + } else { + bytes = readl(chip->regs + ATMEL_PDC_RPR); + } bytes -= runtime->dma_addr; frames = bytes_to_frames(runtime, bytes); @@ -578,20 +649,66 @@ static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev) u32 sr = ac97c_readl(chip, SR); u32 casr = ac97c_readl(chip, CASR); u32 cosr = ac97c_readl(chip, COSR); + u32 camr = ac97c_readl(chip, CAMR); if (sr & AC97C_SR_CAEVT) { - dev_info(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n", + struct snd_pcm_runtime *runtime; + int offset, next_period, block_size; + dev_dbg(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n", casr & AC97C_CSR_OVRUN ? " OVRUN" : "", casr & AC97C_CSR_RXRDY ? " RXRDY" : "", casr & AC97C_CSR_UNRUN ? " UNRUN" : "", casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "", casr & AC97C_CSR_TXRDY ? " TXRDY" : "", !casr ? " NONE" : ""); + if(!cpu_is_at32ap7000()) { + if ((casr & camr) & AC97C_CSR_ENDTX) { + runtime = chip->playback_substream->runtime; + block_size = frames_to_bytes(runtime, + runtime->period_size); + chip->period++; + + if (chip->period == runtime->periods) + chip->period = 0; + next_period = chip->period + 1; + if (next_period == runtime->periods) + next_period = 0; + + offset = block_size * next_period; + + writel(runtime->dma_addr + offset, + chip->regs + ATMEL_PDC_TNPR); + writel(block_size / 2, + chip->regs + ATMEL_PDC_TNCR); + + snd_pcm_period_elapsed(chip->playback_substream); + } + if ((casr & camr) & AC97C_CSR_ENDRX) { + runtime = chip->capture_substream->runtime; + block_size = frames_to_bytes(runtime, + runtime->period_size); + chip->period++; + + if (chip->period == runtime->periods) + chip->period = 0; + next_period = chip->period + 1; + if (next_period == runtime->periods) + next_period = 0; + + offset = block_size * next_period; + + writel(runtime->dma_addr + offset, + chip->regs + ATMEL_PDC_RNPR); + writel(block_size / 2, + chip->regs + ATMEL_PDC_RNCR); + snd_pcm_period_elapsed(chip->capture_substream); + } + } retval = IRQ_HANDLED; } if (sr & AC97C_SR_COEVT) { - dev_info(&chip->pdev->dev, "codec channel event%s%s%s%s%s\n", + dev_dbg(&chip->pdev->dev, "codec channel event%s%s%s%s%s\n", cosr & AC97C_CSR_OVRUN ? " OVRUN" : "", cosr & AC97C_CSR_RXRDY ? " RXRDY" : "", cosr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "", @@ -608,15 +725,50 @@ static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev) return retval; } +static struct ac97_pcm at91_ac97_pcm_defs[] __devinitdata = { + /* Playback */ + { + .exclusive = 1, + .r = { { + .slots = ((1 << AC97_SLOT_PCM_LEFT) + | (1 << AC97_SLOT_PCM_RIGHT)), + } }, + }, + /* PCM in */ + { + .stream = 1, + .exclusive = 1, + .r = { { + .slots = ((1 << AC97_SLOT_PCM_LEFT) + | (1 << AC97_SLOT_PCM_RIGHT)), + } } + }, + /* Mic in */ + { + .stream = 1, + .exclusive = 1, + .r = { { + .slots = (1<<AC97_SLOT_MIC), + } } + }, +}; + static int __devinit atmel_ac97c_pcm_new(struct atmel_ac97c *chip) { struct snd_pcm *pcm; struct snd_pcm_hardware hw = atmel_ac97c_hw; - int capture, playback, retval; + int capture, playback, retval, err; capture = test_bit(DMA_RX_CHAN_PRESENT, &chip->flags); playback = test_bit(DMA_TX_CHAN_PRESENT, &chip->flags); + if(!cpu_is_at32ap7000()) { + err = snd_ac97_pcm_assign(chip->ac97_bus, + ARRAY_SIZE(at91_ac97_pcm_defs), + at91_ac97_pcm_defs); + if (err) + return err; + } retval = snd_pcm_new(chip->card, chip->card->shortname, chip->pdev->id, playback, capture, &pcm); if (retval) @@ -775,7 +927,12 @@ static int __devinit atmel_ac97c_probe(struct platform_device *pdev) return -ENXIO; } - pclk = clk_get(&pdev->dev, "pclk"); + if(cpu_is_at32ap7000()) { + pclk = clk_get(&pdev->dev, "pclk"); + } else { + pclk = clk_get(&pdev->dev, "ac97_clk"); + } + if (IS_ERR(pclk)) { dev_dbg(&pdev->dev, "no peripheral clock\n"); return PTR_ERR(pclk); @@ -844,44 +1001,51 @@ static int __devinit atmel_ac97c_probe(struct platform_device *pdev) goto err_ac97_bus; } - if (pdata->rx_dws.dma_dev) { - struct dw_dma_slave *dws = &pdata->rx_dws; - dma_cap_mask_t mask; + if(cpu_is_at32ap7000()) { + if (pdata->rx_dws.dma_dev) { + struct dw_dma_slave *dws = &pdata->rx_dws; + dma_cap_mask_t mask; - dws->rx_reg = regs->start + AC97C_CARHR + 2; + dws->rx_reg = regs->start + AC97C_CARHR + 2; - dma_cap_zero(mask); - dma_cap_set(DMA_SLAVE, mask); + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); - chip->dma.rx_chan = dma_request_channel(mask, filter, dws); + chip->dma.rx_chan = dma_request_channel(mask, filter, dws); - dev_info(&chip->pdev->dev, "using %s for DMA RX\n", + dev_info(&chip->pdev->dev, "using %s for DMA RX\n", dev_name(&chip->dma.rx_chan->dev->device)); - set_bit(DMA_RX_CHAN_PRESENT, &chip->flags); - } + set_bit(DMA_RX_CHAN_PRESENT, &chip->flags); + } - if (pdata->tx_dws.dma_dev) { - struct dw_dma_slave *dws = &pdata->tx_dws; - dma_cap_mask_t mask; + if (pdata->tx_dws.dma_dev) { + struct dw_dma_slave *dws = &pdata->tx_dws; + dma_cap_mask_t mask; - dws->tx_reg = regs->start + AC97C_CATHR + 2; + dws->tx_reg = regs->start + AC97C_CATHR + 2; - dma_cap_zero(mask); - dma_cap_set(DMA_SLAVE, mask); + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); - chip->dma.tx_chan = dma_request_channel(mask, filter, dws); + chip->dma.tx_chan = dma_request_channel(mask, filter, dws); - dev_info(&chip->pdev->dev, "using %s for DMA TX\n", - dev_name(&chip->dma.tx_chan->dev->device)); - set_bit(DMA_TX_CHAN_PRESENT, &chip->flags); - } + dev_info(&chip->pdev->dev, "using %s for DMA TX\n", + dev_name(&chip->dma.tx_chan->dev->device)); + set_bit(DMA_TX_CHAN_PRESENT, &chip->flags); + } - if (!test_bit(DMA_RX_CHAN_PRESENT, &chip->flags) && - !test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) { - dev_dbg(&pdev->dev, "DMA not available\n"); - retval = -ENODEV; - goto err_dma; - } + if (!test_bit(DMA_RX_CHAN_PRESENT, &chip->flags) && + !test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) { + dev_dbg(&pdev->dev, "DMA not available\n"); + retval = -ENODEV; + goto err_dma; + } + } else { + /* Just pretend that we have DMA channel(for at91 i is actually + * the PDC */ + set_bit(DMA_RX_CHAN_PRESENT, &chip->flags); + set_bit(DMA_TX_CHAN_PRESENT, &chip->flags); + } retval = atmel_ac97c_pcm_new(chip); if (retval) { @@ -897,20 +1061,22 @@ static int __devinit atmel_ac97c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, card); - dev_info(&pdev->dev, "Atmel AC97 controller at 0x%p\n", - chip->regs); + dev_info(&pdev->dev, "Atmel AC97 controller at 0x%p, irq = %d\n", + chip->regs, irq); return 0; err_dma: - if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags)) - dma_release_channel(chip->dma.rx_chan); - if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) - dma_release_channel(chip->dma.tx_chan); - clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags); - clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags); - chip->dma.rx_chan = NULL; - chip->dma.tx_chan = NULL; + if(cpu_is_at32ap7000()) { + if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags)) + dma_release_channel(chip->dma.rx_chan); + if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) + dma_release_channel(chip->dma.tx_chan); + clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags); + clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags); + chip->dma.rx_chan = NULL; + chip->dma.tx_chan = NULL; + } err_ac97_bus: snd_card_set_dev(card, NULL); @@ -934,12 +1100,13 @@ static int atmel_ac97c_suspend(struct platform_device *pdev, pm_message_t msg) struct snd_card *card = platform_get_drvdata(pdev); struct atmel_ac97c *chip = card->private_data; - if (test_bit(DMA_RX_READY, &chip->flags)) - dw_dma_cyclic_stop(chip->dma.rx_chan); - if (test_bit(DMA_TX_READY, &chip->flags)) - dw_dma_cyclic_stop(chip->dma.tx_chan); + if(cpu_is_at32ap7000()) { + if (test_bit(DMA_RX_READY, &chip->flags)) + dw_dma_cyclic_stop(chip->dma.rx_chan); + if (test_bit(DMA_TX_READY, &chip->flags)) + dw_dma_cyclic_stop(chip->dma.tx_chan); + } clk_disable(chip->pclk); - return 0; } @@ -949,11 +1116,12 @@ static int atmel_ac97c_resume(struct platform_device *pdev) struct atmel_ac97c *chip = card->private_data; clk_enable(chip->pclk); - if (test_bit(DMA_RX_READY, &chip->flags)) - dw_dma_cyclic_start(chip->dma.rx_chan); - if (test_bit(DMA_TX_READY, &chip->flags)) - dw_dma_cyclic_start(chip->dma.tx_chan); - + if(cpu_is_at32ap7000()) { + if (test_bit(DMA_RX_READY, &chip->flags)) + dw_dma_cyclic_start(chip->dma.rx_chan); + if (test_bit(DMA_TX_READY, &chip->flags)) + dw_dma_cyclic_start(chip->dma.tx_chan); + } return 0; } #else @@ -978,14 +1146,16 @@ static int __devexit atmel_ac97c_remove(struct platform_device *pdev) iounmap(chip->regs); free_irq(chip->irq, chip); - if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags)) - dma_release_channel(chip->dma.rx_chan); - if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) - dma_release_channel(chip->dma.tx_chan); - clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags); - clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags); - chip->dma.rx_chan = NULL; - chip->dma.tx_chan = NULL; + if(cpu_is_at32ap7000()) { + if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags)) + dma_release_channel(chip->dma.rx_chan); + if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) + dma_release_channel(chip->dma.tx_chan); + clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags); + clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags); + chip->dma.rx_chan = NULL; + chip->dma.tx_chan = NULL; + } snd_card_set_dev(card, NULL); snd_card_free(card); -- 1.5.3.7

2 9

Re: [alsa-devel] Patch for au88x0 driver. Fix audacious issue and add auto reset in case of hardware ADB ctrl failure.
by Raymond Yau 07 Sep '09

07 Sep '09

On Thursday 03 September 2009 21:10, Manuel Jander wrote: > does anybody still have a AU88x0 card ? I know they are quite ancient > now, but if anyone could give the attached patch a try ? Would be > nice. > I made the patch against linux-2.6.30.4 > http://micro.homelinux.net/~mjander/au88x0.diff.gz <http://micro.homelinux.net/%7Emjander/au88x0.diff.gz> > > Best Regards, > Manuel Which version of audaicous (1.5.x or 2.1) are you testing ? (alsa-gapless or alsa-ng plugin) au88x0 most likely cannot support 1 sample per period because of the FIFO as described in patent 6167465. if you look at the source code of alsa-ng and alsa-gapless plugin both of them use the own way to calculate the buffer size instead of using snd_pcm_hw_params_get_buffer_size() http://hg.atheme.org/audacious-plugins/file/2c0a9bba77d7/src/alsa-ng/alsa-c… CHECK_FAIL (snd_pcm_hw_params_set_access (pcm_handle, hwparams, SND_PCM_ACCESS_RW_INTERLEAVED), "snd_pcm_hw_params_set_access"); CHECK_FAIL (snd_pcm_hw_params_set_format (pcm_handle, hwparams, afmt), "snd_pcm_hw_params_set_format"); CHECK_FAIL (snd_pcm_hw_params_set_channels (pcm_handle, hwparams, nch), "snd_pcm_hw_params_set_channels"); CHECK_FAIL (snd_pcm_hw_params_set_rate (pcm_handle, hwparams, rate, 0), "snd_pcm_hw_params_set_rate"); CHECK_FAIL (snd_pcm_hw_params (pcm_handle, hwparams), "snd_pcm_hw_params"); bitwidth = snd_pcm_format_physical_width(afmt); bps = (rate * bitwidth * nch) >> 3; buf_size = MAX(aud_cfg->output_buffer_size, 100); ringbuf_size = buf_size * bps / 1000; How do you get the "ADB Ctrl failure" error ? There are two main problem of the au88x0 driver 1) alsa is unable to calculate the correct value for the three functions snd_pcm_hw_params_set_buffer_time_near() , snd_pcm_hw_params_set_period_time_near() and snd_pcm_set_params() https://bugtrack.alsa-project.org/alsa-bug/view.php?id=1724 Test case : alsa-lib/test/pcm_min.c ( change default to hw:0,0 ) Real world case: gstreamer and winealsa.drv 2) unable to recover when the number of available src is not enough (FATAL: ResManager: resource type 1 exhaust) https://bugtrack.alsa-project.org/alsa-bug/view.php?id=2228 test case : running application to use 15 src ( 7 stereo and one mono stream ) and open another stereo stream

1 0

[alsa-devel] [PATCH - Realtek HD-audio codec 1/1] ALSA: hda/realtek: Added support for CLEVO M540R subsystem, 6 channel + digital
by ddiaz＠cenditel.gob.ve 06 Sep '09

06 Sep '09

The model clevo-m540r was created with 6-channel and digital support. All functions verified except spdif. Tested with a VIT D2000 laptop which has: [lspci extract] Audio device [0403]: Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] (rev 03) Subsystem: CLEVO/KAPOK Computer Device [1558:5409] [/proc/asound/card0/codec\#0 header] Codec: Realtek ALC883 Address: 0 Function Id: 0x1 Vendor Id: 0x10ec0883 Subsystem Id: 0x15585409 Revision Id: 0x100002 Signed-off-by: Dhionel Diaz <ddiaz(a)cenditel.gob.ve> --- sound/pci/hda/patch_realtek.c | 77 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 77 insertions(+), 0 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index f3d186a..32faaac 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -232,6 +232,7 @@ enum { ALC888_3ST_HP, ALC888_6ST_DELL, ALC883_MITAC, + ALC883_CLEVO_M540R, ALC883_CLEVO_M720, ALC883_FUJITSU_PI2515, ALC888_FUJITSU_XA3530, @@ -6657,6 +6658,52 @@ static struct hda_channel_mode alc882_3ST_6ch_modes[3] = { #define alc883_3ST_6ch_modes alc882_3ST_6ch_modes /* + * 2ch mode + */ +static struct hda_verb alc883_3ST_ch2_clevo_init[] = { + { 0x15, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP }, + { 0x18, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, + { 0x18, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE }, + { 0x1a, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_IN }, + { 0x1a, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE }, + { } /* end */ +}; + +/* + * 4ch mode + */ +static struct hda_verb alc883_3ST_ch4_clevo_init[] = { + { 0x15, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, + { 0x18, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, + { 0x18, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE }, + { 0x1a, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, + { 0x1a, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE }, + { 0x1a, AC_VERB_SET_CONNECT_SEL, 0x01 }, + { } /* end */ +}; + +/* + * 6ch mode + */ +static struct hda_verb alc883_3ST_ch6_clevo_init[] = { + { 0x15, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, + { 0x18, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, + { 0x18, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE }, + { 0x18, AC_VERB_SET_CONNECT_SEL, 0x02 }, + { 0x1a, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, + { 0x1a, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE }, + { 0x1a, AC_VERB_SET_CONNECT_SEL, 0x01 }, + { } /* end */ +}; + +static struct hda_channel_mode alc883_3ST_6ch_clevo_modes[3] = { + { 2, alc883_3ST_ch2_clevo_init }, + { 4, alc883_3ST_ch4_clevo_init }, + { 6, alc883_3ST_ch6_clevo_init }, +}; + + +/* * 6ch mode */ static struct hda_verb alc882_sixstack_ch6_init[] = { @@ -8134,6 +8181,22 @@ static struct hda_verb alc883_mitac_verbs[] = { { } /* end */ }; +static struct hda_verb alc883_clevo_m540r_verbs[] = { + /* HP */ + {0x15, AC_VERB_SET_CONNECT_SEL, 0x00}, + {0x15, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP}, + /* Int speaker */ + /*{0x14, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP},*/ + + /* enable unsolicited event */ + /* + {0x15, AC_VERB_SET_UNSOLICITED_ENABLE, ALC880_HP_EVENT | AC_USRSP_EN}, + {0x18, AC_VERB_SET_UNSOLICITED_ENABLE, ALC880_MIC_EVENT | AC_USRSP_EN}, + */ + + { } /* end */ +}; + static struct hda_verb alc883_clevo_m720_verbs[] = { /* HP */ {0x15, AC_VERB_SET_CONNECT_SEL, 0x00}, @@ -8670,6 +8733,7 @@ static const char *alc882_models[ALC882_MODEL_LAST] = { [ALC888_3ST_HP] = "3stack-hp", [ALC888_6ST_DELL] = "6stack-dell", [ALC883_MITAC] = "mitac", + [ALC883_CLEVO_M540R] = "clevo-m540r", [ALC883_CLEVO_M720] = "clevo-m720", [ALC883_FUJITSU_PI2515] = "fujitsu-pi2515", [ALC888_FUJITSU_XA3530] = "fujitsu-xa3530", @@ -8776,6 +8840,7 @@ static struct snd_pci_quirk alc882_cfg_tbl[] = { SND_PCI_QUIRK(0x147b, 0x1083, "Abit IP35-PRO", ALC883_6ST_DIG), SND_PCI_QUIRK(0x1558, 0x0721, "Clevo laptop M720R", ALC883_CLEVO_M720), SND_PCI_QUIRK(0x1558, 0x0722, "Clevo laptop M720SR", ALC883_CLEVO_M720), + SND_PCI_QUIRK(0x1558, 0x5409, "Clevo laptop M540R", ALC883_CLEVO_M540R), SND_PCI_QUIRK_VENDOR(0x1558, "Clevo laptop", ALC883_LAPTOP_EAPD), SND_PCI_QUIRK(0x15d9, 0x8780, "Supermicro PDSBA", ALC883_3ST_6ch), /* SND_PCI_QUIRK(0x161f, 0x2054, "Arima W820", ALC882_ARIMA), */ @@ -9264,6 +9329,18 @@ static struct alc_config_preset alc882_presets[] = { .channel_mode = alc883_3ST_2ch_modes, .input_mux = &alc883_capture_source, }, + [ALC883_CLEVO_M540R] = { + .mixers = { alc883_3ST_6ch_mixer, alc883_chmode_mixer }, + .init_verbs = { alc883_init_verbs, alc883_clevo_m540r_verbs }, + .num_dacs = ARRAY_SIZE(alc883_dac_nids), + .dac_nids = alc883_dac_nids, + .dig_out_nid = ALC883_DIGOUT_NID, + .dig_in_nid = ALC883_DIGIN_NID, + .num_channel_mode = ARRAY_SIZE(alc883_3ST_6ch_clevo_modes), + .channel_mode = alc883_3ST_6ch_clevo_modes, + .need_dac_fix = 1, + .input_mux = &alc883_capture_source, + }, [ALC883_CLEVO_M720] = { .mixers = { alc883_clevo_m720_mixer }, .init_verbs = { alc883_init_verbs, alc883_clevo_m720_verbs }, -- 1.6.3.3

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[alsa-devel] Bug-Report: IDT 92HD75B3X5 - Headphone jacks not working
by Ronald Schmitt 06 Sep '09

06 Sep '09

Problem: Headphone-Jacks are not working. There is no sound output and the built-in speakers don't shut down when plugging a headphone in. Tried several model options with snd-hda-intel options, with "model=hp-dv5" at least I get all speakers working, but still no headphones. System: Hardware: HP Pavilion DV7 2140 Notebook Audio device: Intel Corporation 82801I (ICH9 Family) HD Audio Controller (rev 03) card 0: Intel [HDA Intel], device 0: STAC92xx Analog [STAC92xx Analog] Codec: IDT 92HD75B3X5 Kernel: 2.6.30 upload=true&script=true&cardinfo= !!################################ !!ALSA Information Script v 0.4.58 !!################################ !!Script ran on: Fri Sep 4 10:58:37 UTC 2009 !!Linux Distribution !!------------------ Arch Linux \r (\n) (\l) !!DMI Information !!--------------- Manufacturer: Hewlett-Packard Product Name: HP Pavilion dv7 Notebook PC !!Kernel Information !!------------------ Kernel release: 2.6.30-ARCH Operating System: GNU/Linux Architecture: x86_64 Processor: Intel(R) Core(TM)2 Quad CPU Q9000 @ 2.00GHz SMP Enabled: Yes !!ALSA Version !!------------ Driver version: 1.0.20 Library version: 1.0.20 Utilities version: 1.0.20 !!Loaded ALSA modules !!------------------- snd_hda_intel snd_hda_intel !!Sound Servers on this system !!---------------------------- ESound Daemon: Installed - Yes (/usr/bin/esd) Running - No Jack: Installed - Yes (/usr/bin/jackd) Running - No !!Soundcards recognised by ALSA !!----------------------------- 0 [Intel ]: HDA-Intel - HDA Intel HDA Intel at 0xda100000 irq 22 1 [HDMI ]: HDA-Intel - HDA ATI HDMI HDA ATI HDMI at 0xda010000 irq 17 !!PCI Soundcards installed in the system !!-------------------------------------- 00:1b.0 Audio device: Intel Corporation 82801I (ICH9 Family) HD Audio Controller (rev 03) 01:00.1 Audio device: ATI Technologies Inc R700 Audio Device [Radeon HD 4000 Series] !!Advanced information - PCI Vendor/Device/Susbsystem ID's !!-------------------------------------------------------- 00:1b.0 0403: 8086:293e (rev 03) Subsystem: 103c:3624 -- 01:00.1 0403: 1002:aa38 Subsystem: 103c:3624 !!Modprobe options (Sound related) !!-------------------------------- snd-hda-intel: model=hp-dv5 !!Loaded sound module options !!-------------------------- !!Module: snd_hda_intel bdl_pos_adj : 1,32,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 enable : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y enable_msi : 0 id : <NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL> index : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 model : hp-dv5,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL> position_fix : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 power_save : 0 power_save_controller : Y probe_mask : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 probe_only : N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N single_cmd : N !!Module: snd_hda_intel bdl_pos_adj : 1,32,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 enable : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y enable_msi : 0 id : <NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL> index : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 model : hp-dv5,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL>,<NULL> position_fix : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 power_save : 0 power_save_controller : Y probe_mask : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 probe_only : N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N single_cmd : N !!HDA-Intel Codec information !!--------------------------- --startcollapse-- Codec: IDT 92HD75B3X5 Address: 0 Function Id: 0x1 Vendor Id: 0x111d7603 Subsystem Id: 0x103c3624 Revision Id: 0x100202 No Modem Function Group found Default PCM: rates [0x7e0]: 44100 48000 88200 96000 176400 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Default Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Default Amp-Out caps: ofs=0x7f, nsteps=0x7f, stepsize=0x02, mute=1 GPIO: io=8, o=0, i=0, unsolicited=1, wake=1 IO[0]: enable=1, dir=1, wake=0, sticky=0, data=1, unsol=0 IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[2]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[3]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[4]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[5]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[6]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[7]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 Power-Map: 0x00 Analog Loopback: 0x00 Node 0x0a [Pin Complex] wcaps 0x400181: Stereo Pincap 0x0000001c: OUT HP Detect Pin Default 0x40f100f0: [N/A] Other at Ext N/A Conn = 1/8, Color = Unknown DefAssociation = 0xf, Sequence = 0x0 Pin-ctls: 0x00: Unsolicited: tag=00, enabled=0 Connection: 3 0x10 0x11 0x17* Node 0x0b [Pin Complex] wcaps 0x400081: Stereo Pincap 0x00001724: IN Detect Vref caps: HIZ 50 GRD 80 Pin Default 0x02a11020: [Jack] Mic at Ext Front Conn = 1/8, Color = Black DefAssociation = 0x2, Sequence = 0x0 Pin-ctls: 0x24: IN VREF_80 Unsolicited: tag=01, enabled=1 Node 0x0c [Pin Complex] wcaps 0x400081: Stereo Pincap 0x00001724: IN Detect Vref caps: HIZ 50 GRD 80 Pin Default 0x40f000f1: [N/A] Other at Ext N/A Conn = Unknown, Color = Unknown DefAssociation = 0xf, Sequence = 0x1 Pin-ctls: 0x00: VREF_HIZ Unsolicited: tag=00, enabled=0 Node 0x0d [Pin Complex] wcaps 0x400181: Stereo Pincap 0x00000014: OUT Detect Pin Default 0x90170010: [Fixed] Speaker at Int N/A Conn = Analog, Color = Unknown DefAssociation = 0x1, Sequence = 0x0 Pin-ctls: 0x40: OUT Unsolicited: tag=00, enabled=0 Connection: 3 0x10 0x11* 0x17 Node 0x0e [Pin Complex] wcaps 0x400081: Stereo Pincap 0x00001724: IN Detect Vref caps: HIZ 50 GRD 80 Pin Default 0x40f100f2: [N/A] Other at Ext N/A Conn = 1/8, Color = Unknown DefAssociation = 0xf, Sequence = 0x2 Pin-ctls: 0x00: VREF_HIZ Unsolicited: tag=00, enabled=0 Node 0x0f [Pin Complex] wcaps 0x400181: Stereo Pincap 0x00000014: OUT Detect Pin Default 0x02014040: [Jack] Line Out at Ext Front Conn = 1/8, Color = Green DefAssociation = 0x4, Sequence = 0x0 Pin-ctls: 0x40: OUT Unsolicited: tag=00, enabled=0 Connection: 3 0x10 0x11 0x17* Node 0x10 [Audio Output] wcaps 0xd0c05: Stereo Amp-Out R/L Amp-Out caps: N/A Amp-Out vals: [0x5d 0x5d] Converter: stream=5, channel=0 Power: setting=D0, actual=D0 Delay: 13 samples Node 0x11 [Audio Output] wcaps 0xd0c05: Stereo Amp-Out R/L Amp-Out caps: N/A Amp-Out vals: [0x63 0x63] Converter: stream=5, channel=0 Power: setting=D0, actual=D0 Delay: 13 samples Node 0x12 [Audio Input] wcaps 0x1d0541: Stereo Converter: stream=0, channel=0 SDI-Select: 0 Power: setting=D3, actual=D3 Delay: 13 samples Connection: 1 0x1c Processing caps: benign=0, ncoeff=0 Node 0x13 [Audio Input] wcaps 0x1d0541: Stereo Converter: stream=0, channel=0 SDI-Select: 0 Power: setting=D3, actual=D3 Delay: 13 samples Connection: 1 0x1d Processing caps: benign=0, ncoeff=0 Node 0x14 [Pin Complex] wcaps 0x400100: Mono Pincap 0x00000030: IN OUT Pin Default 0x40f000f0: [N/A] Other at Ext N/A Conn = Unknown, Color = Unknown DefAssociation = 0xf, Sequence = 0x0 Pin-ctls: 0x00: Connection: 1 0x16 Node 0x15 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x10 0x11 0x17* Node 0x16 [Audio Mixer] wcaps 0x200100: Mono Connection: 1 0x15 Node 0x17 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Amp-In caps: ofs=0x17, nsteps=0x1f, stepsize=0x05, mute=1 Amp-In vals: [0x97 0x97] [0x97 0x97] [0x97 0x97] [0x97 0x97] [0x97 0x97] Connection: 5 0x10 0x11 0x14 0x1a 0x1b Node 0x18 [Pin Complex] wcaps 0x40000b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Pincap 0x00000020: IN Pin Default 0x90a60350: [Fixed] Mic at Int N/A Conn = Digital, Color = Unknown DefAssociation = 0x5, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN Node 0x19 [Pin Complex] wcaps 0x40000b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Pincap 0x00000020: IN Pin Default 0x40f000f4: [N/A] Other at Ext N/A Conn = Unknown, Color = Unknown DefAssociation = 0xf, Sequence = 0x4 Pin-ctls: 0x00: Node 0x1a [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 3 0x0b* 0x0c 0x0e Node 0x1b [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 3 0x0b* 0x0c 0x0e Node 0x1c [Audio Selector] wcaps 0x30090d: Stereo Amp-Out R/L Amp-Out caps: ofs=0x00, nsteps=0x0f, stepsize=0x05, mute=1 Amp-Out vals: [0x88 0x88] Connection: 4 0x1a* 0x17 0x18 0x19 Node 0x1d [Audio Selector] wcaps 0x30090d: Stereo Amp-Out R/L Amp-Out caps: ofs=0x00, nsteps=0x0f, stepsize=0x05, mute=1 Amp-Out vals: [0x88 0x88] Connection: 4 0x1b* 0x17 0x18 0x19 Node 0x1e [Pin Complex] wcaps 0x400301: Stereo Digital Pincap 0x00000010: OUT Pin Default 0x024511a0: [Jack] SPDIF Out at Ext Front Conn = Optical, Color = Black DefAssociation = 0xa, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x40: OUT Connection: 1 0x24 Node 0x1f [Pin Complex] wcaps 0x400701: Stereo Digital Pincap 0x00010010: OUT EAPD EAPD 0x0: Pin Default 0x40f000f5: [N/A] Other at Ext N/A Conn = Unknown, Color = Unknown DefAssociation = 0xf, Sequence = 0x5 Pin-ctls: 0x00: Power: setting=D0, actual=D0 Connection: 2 0x24* 0x25 Node 0x20 [Pin Complex] wcaps 0x400301: Stereo Digital Pincap 0x00000010: OUT Pin Default 0x40f000f0: [N/A] Other at Ext N/A Conn = Unknown, Color = Unknown DefAssociation = 0xf, Sequence = 0x0 Pin-ctls: 0x00: Connection: 1 0x25 Node 0x21 [Audio Output] wcaps 0x40211: Stereo Digital Converter: stream=0, channel=0 Digital: Enabled Digital category: 0x0 PCM: rates [0x7e0]: 44100 48000 88200 96000 176400 192000 bits [0xe]: 16 20 24 formats [0x5]: PCM AC3 Delay: 4 samples Node 0x22 [Audio Output] wcaps 0x40211: Stereo Digital Converter: stream=0, channel=0 Digital: Enabled Digital category: 0x0 PCM: rates [0x7e0]: 44100 48000 88200 96000 176400 192000 bits [0xe]: 16 20 24 formats [0x5]: PCM AC3 Delay: 4 samples Node 0x23 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x24 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x21* 0x1c 0x1d Node 0x25 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x22* 0x1c 0x1d Node 0x26 [Beep Generator Widget] wcaps 0x70000c: Mono Amp-Out Amp-Out caps: ofs=0x03, nsteps=0x03, stepsize=0x17, mute=1 Amp-Out vals: [0x00] Node 0x27 [Volume Knob Widget] wcaps 0x600000: Mono Volume-Knob: delta=1, steps=127, direct=0, val=127 Connection: 2 0x10 0x11 Codec: ATI R6xx HDMI Address: 0 Function Id: 0x1 Vendor Id: 0x1002aa01 Subsystem Id: 0x00aa0100 Revision Id: 0x100100 No Modem Function Group found Default PCM: rates [0x40]: 48000 bits [0x6]: 16 20 formats [0x1]: PCM Default Amp-In caps: N/A Default Amp-Out caps: N/A GPIO: io=0, o=0, i=0, unsolicited=0, wake=0 Node 0x02 [Audio Output] wcaps 0x201: Stereo Digital Converter: stream=0, channel=0 Digital: Digital category: 0x0 Node 0x03 [Pin Complex] wcaps 0x400381: Stereo Digital Pincap 0x00000094: OUT Detect HDMI Pin Default 0x18560010: [Jack] Digital Out at Int HDMI Conn = Digital, Color = Unknown DefAssociation = 0x1, Sequence = 0x0 Pin-ctls: 0x40: OUT Unsolicited: tag=00, enabled=0 Connection: 1 0x02 --endcollapse-- !!ALSA Device nodes !!----------------- crw-rw----+ 1 root audio 116, 7 Sep 4 11:06 /dev/snd/controlC0 crw-rw----+ 1 root audio 116, 10 Sep 4 11:06 /dev/snd/controlC1 crw-rw----+ 1 root audio 116, 6 Sep 4 11:06 /dev/snd/hwC0D0 crw-rw----+ 1 root audio 116, 9 Sep 4 11:06 /dev/snd/hwC1D0 crw-rw----+ 1 root audio 116, 5 Sep 4 11:06 /dev/snd/pcmC0D0c crw-rw----+ 1 root audio 116, 4 Sep 4 12:12 /dev/snd/pcmC0D0p crw-rw----+ 1 root audio 116, 3 Sep 4 11:06 /dev/snd/pcmC0D1p crw-rw----+ 1 root audio 116, 8 Sep 4 11:06 /dev/snd/pcmC1D3p crw-rw----+ 1 root audio 116, 11 Sep 4 11:06 /dev/snd/seq crw-rw----+ 1 root audio 116, 2 Sep 4 11:06 /dev/snd/timer /dev/snd/by-path: total 0 drwxr-xr-x 2 root root 80 Sep 4 11:06 . drwxr-xr-x 3 root root 260 Sep 4 11:06 .. lrwxrwxrwx 1 root root 12 Sep 4 11:06 pci-0000:00:1b.0 -> ../controlC0 lrwxrwxrwx 1 root root 12 Sep 4 11:06 pci-0000:01:00.1 -> ../controlC1 !!Aplay/Arecord output !!------------ APLAY **** List of PLAYBACK Hardware Devices **** card 0: Intel [HDA Intel], device 0: STAC92xx Analog [STAC92xx Analog] Subdevices: 0/1 Subdevice #0: subdevice #0 card 0: Intel [HDA Intel], device 1: STAC92xx Digital [STAC92xx Digital] Subdevices: 1/1 Subdevice #0: subdevice #0 card 1: HDMI [HDA ATI HDMI], device 3: ATI HDMI [ATI HDMI] Subdevices: 1/1 Subdevice #0: subdevice #0 ARECORD **** List of CAPTURE Hardware Devices **** card 0: Intel [HDA Intel], device 0: STAC92xx Analog [STAC92xx Analog] Subdevices: 2/2 Subdevice #0: subdevice #0 Subdevice #1: subdevice #1 !!Amixer output !!------------- !!-------Mixer controls for card 0 [Intel] Card hw:0 'Intel'/'HDA Intel at 0xda100000 irq 22' Mixer name : 'IDT 92HD75B3X5' Components : 'HDA:111d7603,103c3624,00100202' Controls : 32 Simple ctrls : 19 Simple mixer control 'Master',0 Capabilities: pvolume pvolume-joined pswitch pswitch-joined Playback channels: Mono Limits: Playback 0 - 64 Mono: Playback 49 [77%] [-11.25dB] [on] Simple mixer control 'PCM',0 Capabilities: pvolume Playback channels: Front Left - Front Right Limits: Playback 0 - 255 Mono: Front Left: Playback 255 [100%] [0.00dB] Front Right: Playback 255 [100%] [0.00dB] Simple mixer control 'Front',0 Capabilities: pvolume pswitch Playback channels: Front Left - Front Right Limits: Playback 0 - 64 Mono: Front Left: Playback 45 [70%] [-14.25dB] [on] Front Right: Playback 45 [70%] [-14.25dB] [on] Simple mixer control 'IEC958',0 Capabilities: pswitch pswitch-joined Playback channels: Mono Mono: Playback [on] Simple mixer control 'IEC958 Default PCM',0 Capabilities: pswitch pswitch-joined Playback channels: Mono Mono: Playback [on] Simple mixer control 'IEC958 Playback Source',0 Capabilities: enum Items: 'Digital Playback' 'Analog Mux 1' 'Analog Mux 2' Item0: 'Digital Playback' Simple mixer control 'Capture',0 Capabilities: cvolume cswitch Capture channels: Front Left - Front Right Limits: Capture 0 - 15 Front Left: Capture 8 [53%] [12.00dB] [off] Front Right: Capture 8 [53%] [12.00dB] [off] Simple mixer control 'Capture',1 Capabilities: cvolume cswitch Capture channels: Front Left - Front Right Limits: Capture 0 - 15 Front Left: Capture 8 [53%] [12.00dB] [off] Front Right: Capture 8 [53%] [12.00dB] [off] Simple mixer control 'DAC0',0 Capabilities: cvolume cswitch Capture channels: Front Left - Front Right Limits: Capture 0 - 31 Front Left: Capture 23 [74%] [0.00dB] [off] Front Right: Capture 23 [74%] [0.00dB] [off] Simple mixer control 'DAC1',0 Capabilities: cvolume cswitch Capture channels: Front Left - Front Right Limits: Capture 0 - 31 Front Left: Capture 23 [74%] [0.00dB] [off] Front Right: Capture 23 [74%] [0.00dB] [off] Simple mixer control 'Digital',0 Capabilities: cvolume Capture channels: Front Left - Front Right Limits: Capture 0 - 120 Front Left: Capture 60 [50%] [0.00dB] Front Right: Capture 60 [50%] [0.00dB] Simple mixer control 'Digital Input Source',0 Capabilities: enum Items: 'Analog Inputs' 'Mixer' 'Digital Mic 1' Item0: 'Analog Inputs' Simple mixer control 'Digital Input Source',1 Capabilities: enum Items: 'Analog Inputs' 'Mixer' 'Digital Mic 1' Item0: 'Analog Inputs' Simple mixer control 'Import0 Mux',0 Capabilities: cvolume cswitch Capture channels: Front Left - Front Right Limits: Capture 0 - 31 Front Left: Capture 23 [74%] [0.00dB] [off] Front Right: Capture 23 [74%] [0.00dB] [off] Simple mixer control 'Import1 Mux',0 Capabilities: cvolume cswitch Capture channels: Front Left - Front Right Limits: Capture 0 - 31 Front Left: Capture 23 [74%] [0.00dB] [off] Front Right: Capture 23 [74%] [0.00dB] [off] Simple mixer control 'Mux',0 Capabilities: cvolume Capture channels: Front Left - Front Right Limits: Capture 0 - 3 Front Left: Capture 0 [0%] [0.00dB] Front Right: Capture 0 [0%] [0.00dB] Simple mixer control 'Mux',1 Capabilities: cvolume Capture channels: Front Left - Front Right Limits: Capture 0 - 3 Front Left: Capture 0 [0%] [0.00dB] Front Right: Capture 0 [0%] [0.00dB] Simple mixer control 'PC Beep',0 Capabilities: pvolume pvolume-joined pswitch pswitch-joined Playback channels: Mono Limits: Playback 0 - 3 Mono: Playback 1 [33%] [-12.00dB] [off] Simple mixer control 'Speaker',0 Capabilities: pvolume pswitch Playback channels: Front Left - Front Right Limits: Playback 0 - 64 Mono: Front Left: Playback 51 [80%] [-9.75dB] [on] Front Right: Playback 51 [80%] [-9.75dB] [on] !!-------Mixer controls for card 1 [HDMI] Card hw:1 'HDMI'/'HDA ATI HDMI at 0xda010000 irq 17' Mixer name : 'ATI R6xx HDMI' Components : 'HDA:1002aa01,00aa0100,00100100' Controls : 4 Simple ctrls : 1 Simple mixer control 'IEC958',0 Capabilities: pswitch pswitch-joined Playback channels: Mono Mono: Playback [off] !!Alsactl output !!------------- --startcollapse-- state.Intel { control.1 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 15' comment.dbmin 0 comment.dbmax 2250 iface MIXER name 'Capture Volume' value.0 8 value.1 8 } control.2 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'Capture Switch' value.0 false value.1 false } control.3 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 15' comment.dbmin 0 comment.dbmax 2250 iface MIXER name 'Capture Volume' index 1 value.0 8 value.1 8 } control.4 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'Capture Switch' index 1 value.0 false value.1 false } control.5 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'Import0 Mux Capture Switch' value.0 false value.1 false } control.6 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 31' comment.dbmin -3450 comment.dbmax 1200 iface MIXER name 'Import0 Mux Capture Volume' value.0 23 value.1 23 } control.7 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'Import1 Mux Capture Switch' value.0 false value.1 false } control.8 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 31' comment.dbmin -3450 comment.dbmax 1200 iface MIXER name 'Import1 Mux Capture Volume' value.0 23 value.1 23 } control.9 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'DAC0 Capture Switch' value.0 false value.1 false } control.10 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 31' comment.dbmin -3450 comment.dbmax 1200 iface MIXER name 'DAC0 Capture Volume' value.0 23 value.1 23 } control.11 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'DAC1 Capture Switch' value.0 false value.1 false } control.12 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 31' comment.dbmin -3450 comment.dbmax 1200 iface MIXER name 'DAC1 Capture Volume' value.0 23 value.1 23 } control.13 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 64' comment.dbmin -4800 comment.dbmax 0 iface MIXER name 'Front Playback Volume' value.0 45 value.1 45 } control.14 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'Front Playback Switch' value.0 true value.1 true } control.15 { comment.access 'read write' comment.type BOOLEAN comment.count 1 iface MIXER name 'PC Beep Playback Switch' value false } control.16 { comment.access 'read write' comment.type INTEGER comment.count 1 comment.range '0 - 3' comment.dbmin -1800 comment.dbmax 0 iface MIXER name 'PC Beep Playback Volume' value 1 } control.17 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 64' comment.dbmin -4800 comment.dbmax 0 iface MIXER name 'Speaker Playback Volume' value.0 51 value.1 51 } control.18 { comment.access 'read write' comment.type BOOLEAN comment.count 2 iface MIXER name 'Speaker Playback Switch' value.0 true value.1 true } control.19 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 3' comment.dbmin 0 comment.dbmax 3000 iface MIXER name 'Mux Capture Volume' value.0 0 value.1 0 } control.20 { comment.access 'read write' comment.type INTEGER comment.count 2 comment.range '0 - 3' comment.dbmin 0 comment.dbmax 3000 iface MIXER name 'Mux Capture Volume' index 1 value.0 0 value.1 0 } control.21 { comment.access 'read write' comment.type ENUMERATED comment.count 1 comment.item.0 'Analog Inputs' comment.item.1 Mixer comment.item.2 'Digital Mic 1' iface MIXER name 'Digital Input Source' value 'Analog Inputs' } control.22 { comment.access 'read write' comment.type ENUMERATED comment.count 1 comment.item.0 'Analog Inputs' comment.item.1 Mixer comment.item.2 'Digital Mic 1' iface MIXER name 'Digital Input Source' index 1 value 'Analog Inputs' } control.23 { comment.access 'read write' comment.type ENUMERATED comment.count 1 comment.item.0 'Digital Playback' comment.item.1 'Analog Mux 1' comment.item.2 'Analog Mux 2' iface MIXER name 'IEC958 Playback Source' value 'Digital Playback' } control.24 { comment.access read comment.type IEC958 comment.count 1 iface MIXER name 'IEC958 Playback Con Mask' value '0fff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' } control.25 { comment.access read comment.type IEC958 comment.count 1 iface MIXER name 'IEC958 Playback Pro Mask' value '0f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' } control.26 { comment.access 'read write' comment.type IEC958 comment.count 1 iface MIXER name 'IEC958 Playback Default' value '0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' } control.27 { comment.access 'read write' comment.type BOOLEAN comment.count 1 iface MIXER name 'IEC958 Playback Switch' value true } control.28 { comment.access 'read write' comment.type BOOLEAN comment.count 1 iface MIXER name 'IEC958 Default PCM Playback Switch' value true } control.29 { comment.access 'read write' comment.type INTEGER comment.count 1 comment.range '0 - 64' comment.dbmin -4800 comment.dbmax 0 iface MIXER name 'Master Playback Volume' value 49 } control.30 { comment.access 'read write' comment.type BOOLEAN comment.count 1 iface MIXER name 'Master Playback Switch' value true } control.31 { comment.access 'read write user' comment.type INTEGER comment.count 2 comment.range '0 - 255' comment.tlv '0000000100000008ffffec1400000014' comment.dbmin -5100 comment.dbmax 0 iface MIXER name 'PCM Playback Volume' value.0 255 value.1 255 } control.32 { comment.access 'read write user' comment.type INTEGER comment.count 2 comment.range '0 - 120' comment.tlv '0000000100000008fffff44800000032' comment.dbmin -3000 comment.dbmax 3000 iface MIXER name 'Digital Capture Volume' value.0 60 value.1 60 } } state.HDMI { control.1 { comment.access read comment.type IEC958 comment.count 1 iface MIXER name 'IEC958 Playback Con Mask' value '0fff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' } control.2 { comment.access read comment.type IEC958 comment.count 1 iface MIXER name 'IEC958 Playback Pro Mask' value '0f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' } control.3 { comment.access 'read write' comment.type IEC958 comment.count 1 iface MIXER name 'IEC958 Playback Default' value '0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' } control.4 { comment.access 'read write' comment.type BOOLEAN comment.count 1 iface MIXER name 'IEC958 Playback Switch' value false } } --endcollapse-- !!All Loaded Modules !!------------------ Module usbhid hid cryptd aes_x86_64 aes_generic nfsd exportfs nfs lockd fscache nfs_acl auth_rpcgss sunrpc ipv6 arc4 ecb uvcvideo videodev v4l1_compat snd_seq_dummy iwlagn v4l2_compat_ioctl32 snd_seq_oss fan iwlcore snd_seq_midi_event snd_seq snd_seq_device snd_hda_codec_atihdmi cpufreq_ondemand rfkill snd_hda_codec_idt snd_pcm_oss snd_mixer_oss mac80211 jmb38x_ms i2c_i801 joydev snd_hda_intel snd_hda_codec acpi_cpufreq sdhci_pci sdhci snd_hwdep snd_pcm snd_timer snd psmouse uhci_hcd ehci_hcd iTCO_wdt freq_table hp_accel lis3lv02d mmc_core cfg80211 soundcore snd_page_alloc serio_raw pcspkr memstick ohci1394 wmi intel_agp i2c_core iTCO_vendor_support usbcore r8169 mii thermal video output sg led_class ac processor evdev battery ieee1394 button coretemp rtc_cmos rtc_core rtc_lib ext4 mbcache jbd2 crc16 sr_mod sd_mod cdrom ahci libata scsi_mod !!Sysfs Files !!----------- /sys/class/sound/hwC0D0/init_pin_configs: 0x0a 0x40f100f0 0x0b 0x02a11020 0x0c 0x40f000f1 0x0d 0x90170110 0x0e 0x40f100f2 0x0f 0x02014040 0x14 0x40f000f0 0x18 0x90a60350 0x19 0x40f000f4 0x1e 0x024511a0 0x1f 0x40f000f5 0x20 0x40f000f0 /sys/class/sound/hwC0D0/driver_pin_configs: 0x0d 0x90170010 /sys/class/sound/hwC0D0/user_pin_configs: /sys/class/sound/hwC0D0/init_verbs: /sys/class/sound/hwC1D0/init_pin_configs: 0x03 0x18560010 /sys/class/sound/hwC1D0/driver_pin_configs: /sys/class/sound/hwC1D0/user_pin_configs: /sys/class/sound/hwC1D0/init_verbs: !!ALSA/HDA dmesg !!------------------ usb 2-4: new high speed USB device using ehci_hcd and address 2 HDA Intel 0000:00:1b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22 HDA Intel 0000:00:1b.0: setting latency timer to 64 jmb38x_ms 0000:06:00.3: PCI INT A -> GSI 16 (level, low) -> IRQ 16 -- usb 2-4: configuration #1 chosen from 1 choice input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1b.0/input/input9 input: HDA Intel Mic at Ext Front Jack as /devices/pci0000:00/0000:00:1b.0/input/input10 input: HDA Intel Line Out at Ext Front Jack as /devices/pci0000:00/0000:00:1b.0/input/input11 HDA Intel 0000:01:00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17 HDA Intel 0000:01:00.1: setting latency timer to 64 i801_smbus 0000:00:1f.3: PCI INT C -> GSI 18 (level, low) -> IRQ 18

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[alsa-devel] Kernel panic with alsa-driver 1.0.21 and RHEL 5
by Paulo Cavalcanti 06 Sep '09

06 Sep '09

Hi, I upgraded to alsa 1.0.21 on Fedora 10/11 with no problem at all. However, I always get a kernel panic when I install alsa-driver 1.0.21 on RHEL 5 (either i386 or x86_63) and reboot: I have no idea on how to debug this situation. The memory dump references: snd_hda_codec .... snd_hda_intel ... RHEL 5 runs just fine with alsa-driver 1.0.20, thought. Thanks. -- Paulo Roma Cavalcanti LCG - UFRJ

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[alsa-devel] Check out my photos on Facebook
by Justin P. Mattock 05 Sep '09

05 Sep '09

I set up a Facebook profile where I can post my pictures, videos and events and I want to add you as a friend so you can see it. First, you need to join Facebook! Once you join, you can also create your own profile. Thanks, Justin To sign up for Facebook, follow the link below: http://www.facebook.com/p.php?i=1358683573&k=Z31T6VT5R4TF6BD1Q142YPT2RT&r alsa-devel(a)alsa-project.org was invited to join Facebook by Justin P. Mattock. If you do not wish to receive this type of email from Facebook in the future, please click on the link below to unsubscribe. http://www.facebook.com/o.php?k=15ec76&u=100000227845811&mid=10cc736G5af31e… Facebook's offices are located at 1601 S. California Ave., Palo Alto, CA 94304.

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