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[alsa-devel] [PATCH v2 00/26] Add support for the Ingenic JZ4740 System-on-a-Chip
by Lars-Peter Clausen 23 Jun '10

23 Jun '10

Foreword: Ralf suggested that it might be a good idea in order to allow for reasonable testing and to avoid build failures due to two-way dependencies in different parts of the kernel, that he applies all the patches once they have been acked by their respective maintainers, feeds them into -next and eventually sends the whole series to Linus. One exception will be the ASoC patches which will, due to major changes in the ASoC subsystem, go through the ASoC tree. So if you are a maintainer for one of the subsystem touched by this series and would rather see the patch going through your tree (given the patch is ok) please tell. This patch series adds support for the Ingenic JZ4740 System-on-a-Chip. The JZ4740 has a mostly MIPS32 compatible core (no on cpu timers) and many on chip peripherals like RTC, NAND, MMC, OHCI, UDC, ADC, I2C, SPI, AC97, I2S, I2S Codec, UART and LCD controller. The JZ4740 is mostly used in eBooks, PMPs and hand-held consoles. This series contains patches for the Qi Ben NanoNote clamshell device as the inital supported device. Changes since v1: There have been some minor changes since v1, mostly code cleanup and some functional changes. One bigger change is that there is now a MFD driver for the ADC core which does IRQ demultiplexing for the ADC unit and synchronizes access to shared registers between the different users of the ADC core. The patch adding a defconfig for the Qi LB60 has been dropped. A detailed list of changes is present in each patch. - Lars Cc: Alessandro Zummo <a.zummo(a)towertech.it> Cc: Andrew Morton <akpm(a)linux-foundation.org> Cc: Anton Vorontsov <cbouatmailru(a)gmail.com> Cc: David Brownell <dbrownell(a)users.sourceforge.net> Cc: David Woodhouse <dwmw2(a)infradead.org> Cc: Greg Kroah-Hartman <gregkh(a)suse.de> Cc: Liam Girdwood <lrg(a)slimlogic.co.uk> Cc: Mark Brown <broonie(a)opensource.wolfsonmicro.com> Cc: Paul Gortmaker <p_gortmaker(a)yahoo.com> Cc: Samuel Ortiz <sameo(a)linux.intel.com> Cc: alsa-devel(a)alsa-project.org Cc: linux-fbdev(a)vger.kernel.org Cc: linux-mmc(a)vger.kernel.org Cc: linux-mtd(a)lists.infradead.org Cc: linux-usb(a)vger.kernel.org Cc: lm-sensors(a)lm-sensors.org Cc: rtc-linux(a)googlegroups.com Lars-Peter Clausen (26): MIPS: Add base support for Ingenic JZ4740 System-on-a-Chip MIPS: jz4740: Add IRQ handler code MIPS: JZ4740: Add clock API support. MIPS: JZ4740: Add timer support MIPS: JZ4740: Add clocksource/clockevent support. MIPS: JZ4740: Add power-management and system reset support MIPS: JZ4740: Add setup code MIPS: JZ4740: Add gpio support MIPS: JZ4740: Add DMA support. MIPS: JZ4740: Add PWM support MIPS: JZ4740: Add serial support MIPS: JZ4740: Add prom support MIPS: JZ4740: Add platform devices MIPS: JZ4740: Add Kbuild files RTC: Add JZ4740 RTC driver fbdev: Add JZ4740 framebuffer driver MTD: Nand: Add JZ4740 NAND driver MMC: Add JZ4740 mmc driver USB: Add JZ4740 ohci support alsa: ASoC: Add JZ4740 codec driver alsa: ASoC: Add JZ4740 ASoC support MFD: Add JZ4740 ADC driver hwmon: Add JZ4740 ADC driver power: Add JZ4740 battery driver. MIPS: JZ4740: Add qi_lb60 board support alsa: ASoC: JZ4740: Add qi_lb60 board driver arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 13 + arch/mips/include/asm/bootinfo.h | 6 + arch/mips/include/asm/cpu.h | 9 +- arch/mips/include/asm/mach-jz4740/base.h | 26 + arch/mips/include/asm/mach-jz4740/clock.h | 28 + arch/mips/include/asm/mach-jz4740/dma.h | 90 +++ arch/mips/include/asm/mach-jz4740/gpio.h | 398 +++++++++++ arch/mips/include/asm/mach-jz4740/irq.h | 57 ++ arch/mips/include/asm/mach-jz4740/platform.h | 36 + arch/mips/include/asm/mach-jz4740/timer.h | 22 + arch/mips/include/asm/mach-jz4740/war.h | 25 + arch/mips/jz4740/Kconfig | 12 + arch/mips/jz4740/Makefile | 20 + arch/mips/jz4740/Platform | 5 + arch/mips/jz4740/board-qi_lb60.c | 483 +++++++++++++ arch/mips/jz4740/clock-debugfs.c | 109 +++ arch/mips/jz4740/clock.c | 920 ++++++++++++++++++++++++ arch/mips/jz4740/clock.h | 76 ++ arch/mips/jz4740/dma.c | 289 ++++++++ arch/mips/jz4740/gpio.c | 601 ++++++++++++++++ arch/mips/jz4740/irq.c | 169 +++++ arch/mips/jz4740/irq.h | 21 + arch/mips/jz4740/platform.c | 284 ++++++++ arch/mips/jz4740/pm.c | 56 ++ arch/mips/jz4740/prom.c | 68 ++ arch/mips/jz4740/pwm.c | 169 +++++ arch/mips/jz4740/reset.c | 79 ++ arch/mips/jz4740/reset.h | 7 + arch/mips/jz4740/serial.c | 33 + arch/mips/jz4740/serial.h | 21 + arch/mips/jz4740/setup.c | 29 + arch/mips/jz4740/time.c | 144 ++++ arch/mips/jz4740/timer.c | 48 ++ arch/mips/jz4740/timer.h | 136 ++++ arch/mips/kernel/cpu-probe.c | 20 + arch/mips/mm/tlbex.c | 5 + drivers/hwmon/Kconfig | 11 + drivers/hwmon/Makefile | 1 + drivers/hwmon/jz4740-hwmon.c | 206 ++++++ drivers/mfd/Kconfig | 8 + drivers/mfd/Makefile | 1 + drivers/mfd/jz4740-adc.c | 392 ++++++++++ drivers/mmc/host/Kconfig | 8 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/jz4740_mmc.c | 993 ++++++++++++++++++++++++++ drivers/mtd/nand/Kconfig | 6 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4740_nand.c | 474 ++++++++++++ drivers/power/Kconfig | 11 + drivers/power/Makefile | 1 + drivers/power/jz4740-battery.c | 445 ++++++++++++ drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-jz4740.c | 341 +++++++++ drivers/usb/Kconfig | 1 + drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-jz4740.c | 276 +++++++ drivers/video/Kconfig | 9 + drivers/video/Makefile | 1 + drivers/video/jz4740_fb.c | 817 +++++++++++++++++++++ include/linux/jz4740-adc.h | 32 + include/linux/jz4740_fb.h | 58 ++ include/linux/mmc/jz4740_mmc.h | 15 + include/linux/mtd/jz4740_nand.h | 34 + include/linux/power/jz4740-battery.h | 24 + sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/jz4740-codec.c | 514 +++++++++++++ sound/soc/codecs/jz4740-codec.h | 20 + sound/soc/jz4740/Kconfig | 23 + sound/soc/jz4740/Makefile | 13 + sound/soc/jz4740/jz4740-i2s.c | 540 ++++++++++++++ sound/soc/jz4740/jz4740-i2s.h | 18 + sound/soc/jz4740/jz4740-pcm.c | 373 ++++++++++ sound/soc/jz4740/jz4740-pcm.h | 22 + sound/soc/jz4740/qi_lb60.c | 167 +++++ 79 files changed, 10396 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/base.h create mode 100644 arch/mips/include/asm/mach-jz4740/clock.h create mode 100644 arch/mips/include/asm/mach-jz4740/dma.h create mode 100644 arch/mips/include/asm/mach-jz4740/gpio.h create mode 100644 arch/mips/include/asm/mach-jz4740/irq.h create mode 100644 arch/mips/include/asm/mach-jz4740/platform.h create mode 100644 arch/mips/include/asm/mach-jz4740/timer.h create mode 100644 arch/mips/include/asm/mach-jz4740/war.h create mode 100644 arch/mips/jz4740/Kconfig create mode 100644 arch/mips/jz4740/Makefile create mode 100644 arch/mips/jz4740/Platform create mode 100644 arch/mips/jz4740/board-qi_lb60.c create mode 100644 arch/mips/jz4740/clock-debugfs.c create mode 100644 arch/mips/jz4740/clock.c create mode 100644 arch/mips/jz4740/clock.h create mode 100644 arch/mips/jz4740/dma.c create mode 100644 arch/mips/jz4740/gpio.c create mode 100644 arch/mips/jz4740/irq.c create mode 100644 arch/mips/jz4740/irq.h create mode 100644 arch/mips/jz4740/platform.c create mode 100644 arch/mips/jz4740/pm.c create mode 100644 arch/mips/jz4740/prom.c create mode 100644 arch/mips/jz4740/pwm.c create mode 100644 arch/mips/jz4740/reset.c create mode 100644 arch/mips/jz4740/reset.h create mode 100644 arch/mips/jz4740/serial.c create mode 100644 arch/mips/jz4740/serial.h create mode 100644 arch/mips/jz4740/setup.c create mode 100644 arch/mips/jz4740/time.c create mode 100644 arch/mips/jz4740/timer.c create mode 100644 arch/mips/jz4740/timer.h create mode 100644 drivers/hwmon/jz4740-hwmon.c create mode 100644 drivers/mfd/jz4740-adc.c create mode 100644 drivers/mmc/host/jz4740_mmc.c create mode 100644 drivers/mtd/nand/jz4740_nand.c create mode 100644 drivers/power/jz4740-battery.c create mode 100644 drivers/rtc/rtc-jz4740.c create mode 100644 drivers/usb/host/ohci-jz4740.c create mode 100644 drivers/video/jz4740_fb.c create mode 100644 include/linux/jz4740-adc.h create mode 100644 include/linux/jz4740_fb.h create mode 100644 include/linux/mmc/jz4740_mmc.h create mode 100644 include/linux/mtd/jz4740_nand.h create mode 100644 include/linux/power/jz4740-battery.h create mode 100644 sound/soc/codecs/jz4740-codec.c create mode 100644 sound/soc/codecs/jz4740-codec.h create mode 100644 sound/soc/jz4740/Kconfig create mode 100644 sound/soc/jz4740/Makefile create mode 100644 sound/soc/jz4740/jz4740-i2s.c create mode 100644 sound/soc/jz4740/jz4740-i2s.h create mode 100644 sound/soc/jz4740/jz4740-pcm.c create mode 100644 sound/soc/jz4740/jz4740-pcm.h create mode 100644 sound/soc/jz4740/qi_lb60.c

5 12

[alsa-devel] [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
by Stuart Longland 22 Jun '10

22 Jun '10

The TLV320AIC3204 is a low-power stereo audio CODEC capable of sample rates of up to 192kHz. This driver implements basic functionality, using I²C for the control channel. The audio interface supports many data bus formats, including I²S master/slave, DSP, left/right justified and TDM. What works: - Playback at various bitrates up to 96kHz - Recording at various bitrates up to 96kHz - Mixer interface - PLL generation of CODEC clocks from MCLK What could work better: - DAPM What isn't tested: - Audio interfaces other than I²S - PLL with clocks other than ~12MHz - Mono recording/playback - 192kHz recording/playback - Suspend & Resume What isn't implemented: - SPI interface support - PLL without fractional divider (would allow <10MHz clocks) - Clock sources other than MCLK - Adaptive filtering - AGC - Headset detection, JACK framework TODO list: - Clean up the register cache ... this is in the early planning phase Signed-off-by: Stuart Longland <redhatter(a)gentoo.org> --- include/sound/tlv320aic3204.h | 64 + sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/tlv320aic3204.c | 4197 ++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/tlv320aic3204.h | 1350 ++++++++++++ 5 files changed, 5618 insertions(+), 0 deletions(-) create mode 100644 include/sound/tlv320aic3204.h create mode 100644 sound/soc/codecs/tlv320aic3204.c create mode 100644 sound/soc/codecs/tlv320aic3204.h diff --git a/include/sound/tlv320aic3204.h b/include/sound/tlv320aic3204.h new file mode 100644 index 0000000..491cd22 --- /dev/null +++ b/include/sound/tlv320aic3204.h @@ -0,0 +1,64 @@ +/* + * Platform data for Texas Instruments TLV320AIC3204 codec + * + * Copyright (C) 2010 Jacques Electronics Pty Ltd + * Author: Stuart Longland <redhatter(a)gentoo.org> + * + * Based on tlv320aic3x.h: + * Author: Jarkko Nikula <jhnikula(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __TLV320AIC3204_H__ +#define __TLV320AIC3204_H__ + +/* + * Analogue Input Quick-Charge Power Up Delay + */ +enum { + /* Power up time: Default Value (whatever that is) */ + AIC3204_PDATA_AIN_PWRUP_DEFAULT = (0x00), + /* Power up time: 3.1ms */ + AIC3204_PDATA_AIN_PWRUP_3M1S = (0x31), + /* Power up time: 6.4ms */ + AIC3204_PDATA_AIN_PWRUP_6M4S = (0x32), + /* Power up time: 1.6ms */ + AIC3204_PDATA_AIN_PWRUP_1M6S = (0x33), +}; + +/* + * Analogue Reference Power Up Delay + */ +enum { + /* Reference Power-Up delay: Slow */ + AIC3204_PDATA_REF_PWRUP_SLOW = (0 << 0), + /* Reference Power-Up delay: 40ms */ + AIC3204_PDATA_REF_PWRUP_40MS = (1 << 0), + /* Reference Power-Up delay: 80ms */ + AIC3204_PDATA_REF_PWRUP_80MS = (2 << 0), + /* Reference Power-Up delay: 120ms */ + AIC3204_PDATA_REF_PWRUP_120MS = (3 << 0), +}; + +struct aic3204_pdata { + int gpio_reset; /* < 0 if not used */ + + /* Analogue-in Power up delay */ + u8 ain_pwrup_delay; + + /* Analogue Reference Power up delay */ + u8 ref_pwrup_delay; + + /* AVDD <->DVDD Link enable */ + u8 avdd_link_en; + + /* LDO Enable */ + u8 ldo_en; + + /* Oversampling rate (both ADC and DAC) */ + u8 osr; +}; + +#endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index c37c844..80b56a4 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -32,6 +32,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_STAC9766 if SND_SOC_AC97_BUS select SND_SOC_TLV320AIC23 if I2C select SND_SOC_TLV320AIC26 if SPI_MASTER + select SND_SOC_TLV320AIC3204 if I2C select SND_SOC_TLV320AIC3X if I2C select SND_SOC_TPA6130A2 if I2C select SND_SOC_TLV320DAC33 if I2C @@ -164,6 +165,10 @@ config SND_SOC_TLV320AIC26 tristate "TI TLV320AIC26 Codec support" if SND_SOC_OF_SIMPLE depends on SPI +config SND_SOC_TLV320AIC3204 + tristate + depends on I2C + config SND_SOC_TLV320AIC3X tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 4a9c205..c649f14 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -20,6 +20,7 @@ snd-soc-ssm2602-objs := ssm2602.o snd-soc-stac9766-objs := stac9766.o snd-soc-tlv320aic23-objs := tlv320aic23.o snd-soc-tlv320aic26-objs := tlv320aic26.o +snd-soc-tlv320aic3204-objs := tlv320aic3204.o snd-soc-tlv320aic3x-objs := tlv320aic3x.o snd-soc-tlv320dac33-objs := tlv320dac33.o snd-soc-twl4030-objs := twl4030.o @@ -86,6 +87,7 @@ obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o +obj-$(CONFIG_SND_SOC_TLV320AIC3204) += snd-soc-tlv320aic3204.o obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o diff --git a/sound/soc/codecs/tlv320aic3204.c b/sound/soc/codecs/tlv320aic3204.c new file mode 100644 index 0000000..6b185c5 --- /dev/null +++ b/sound/soc/codecs/tlv320aic3204.c @@ -0,0 +1,4197 @@ +/* + * ALSA SoC TLV320AIC3204 codec driver + * + * Author: Stuart Longland, <redhatter(a)gentoo.org> + * Copyright: (C) 2010 Jacques Electronics Pty. Ltd. + * + * Based upon the TLV320AIC3X driver: + * Author: Vladimir Barinov, <vbarinov(a)embeddedalley.com> + * Copyright: (C) 2007 MontaVista Software, Inc., <source(a)mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/tlv320aic3204.h> + +#include "tlv320aic3204.h" + +/* + * Default settings; these will be used if no platform data is provided. + */ +static const struct aic3204_pdata aic3204_default_pdata = { + .gpio_reset = -1, + .ain_pwrup_delay = AIC3204_PDATA_AIN_PWRUP_DEFAULT, + .ref_pwrup_delay = AIC3204_PDATA_REF_PWRUP_SLOW, + .avdd_link_en = 1, + .ldo_en = 0, + .osr = 128, +}; + +/* + * Default Register Values; this is used to initialise the register cache. + * There are 128 pages, of 128 registers each stored here. The data was + * captured from a TLV320AIC3204 immediately after reset, and therefore should + * be representative of what's displayed in the datasheet. + */ +static const u8 aic3204_default_reg_data[128*128] = { + /* --- Page 0 --- */ + 0x00, 0x00, 0x50, 0x00, 0x00, 0x11, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02, + 0x00, 0x08, 0x01, 0x01, 0x80, 0x01, 0x00, 0x04, + 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x03, 0x02, + 0x02, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x14, + 0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xee, 0x10, 0xd8, 0x7e, 0xe3, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 1 --- */ + 0x01, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 2 --- */ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 3 --- */ + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 122 --- */ + 0x7a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 123 --- */ + 0x7b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 124 --- */ + 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 125 --- */ + 0x7d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 126 --- */ + 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* --- Page 127 --- */ + 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +#define AIC3204_NUM_SUPPLIES 4 +static const char *aic3204_supply_names[AIC3204_NUM_SUPPLIES] = { + "IOVDD", /* I/O Voltage */ + "DVDD", /* Digital Core Voltage */ + "AVDD", /* Analog DAC Voltage */ + "LDOin", /* Supply for internal LDOs and output amplifiers */ +}; + +/* codec private data */ +struct aic3204_priv { + struct snd_soc_codec codec; + struct regulator_bulk_data supplies[AIC3204_NUM_SUPPLIES]; + unsigned int sysclk; + struct aic3204_pdata pdata; +}; + +/* + * Determine whether a register is readable. + */ +static int aic3204_reg_is_readable(unsigned int reg) +{ + u8 page = reg >> 7; + reg &= 0x7f; + + /* Anything beyond page 70 is undefined */ + if (page > 70) + return 0; + + /* Page 62..70 */ + if (page >= 62) { + /* Register 0 is page select */ + if (reg == 0) + return 1; + /* Registers 1..7 are reserved */ + if (reg <= 7) + return 0; + /* Registers 8..127 are valid */ + return 1; + } + + /* Pages 53..62 are undefined */ + if (page >= 53) + return 0; + + /* Pages 45..52 */ + if (page >= 45) { + /* Register 0 is page select */ + if (reg == 0) + return 1; + /* Registers 1..7 are reserved */ + if (reg <= 7) + return 0; + /* Registers 8..127 are valid */ + return 1; + } + + /* Page 44 --- XXX The datasheet may have some typos here! */ + if (page == 44) { + /* + * Register 0 is page select + * Register 1 enables adaptive filtering + */ + if (reg <= 1) + return 1; + /* Registers 2..7 are reserved */ + if (reg <= 7) + return 0; + /* Registers 8..127 are valid */ + return 1; + } + + /* Pages 35..43 are undefined */ + if (page >= 35) + return 0; + + /* Pages 26..34 */ + if (page >= 26) { + /* Register 0 is page select */ + if (reg == 0) + return 1; + /* Registers 1..7 are reserved */ + if (reg <= 7) + return 0; + /* Registers 8..127 are valid */ + return 1; + } + + /* Pages 17..25 are undefined */ + if (page >= 17) + return 0; + + /* Pages 9..16 */ + if (page >= 9) { + if (reg == 0) + return 1; + if (reg <= 7) + return 0; + return 1; + } + + /* Page 8 */ + if (page == 8) { + if (reg <= 1) + return 1; + if (reg <= 7) + return 0; + return 1; + } + + /* Page 2..7 are undefined */ + if (page >= 2) + return 0; + + /* Page 1 */ + if (page == 1) { + if (reg <= 4) + return 1; + if (reg <= 8) + return 0; + if (reg <= 20) + return 1; + if (reg == 21) + return 0; + if (reg <= 25) + return 1; + if (reg <= 50) + return 0; + if (reg <= 52) + return 1; + if (reg == 53) + return 0; + if (reg <= 55) + return 1; + if (reg == 56) + return 0; + if (reg <= 63) + return 1; + if (reg <= 70) + return 0; + if (reg == 71) + return 1; + if (reg <= 122) + return 0; + if (reg == 123) + return 1; + return 0; + } + + /* Page 0 */ + if (reg == 0) + return 1; + if (reg <= 3) + return 0; + if (reg <= 8) + return 1; + if (reg <= 10) + return 0; + if (reg <= 14) + return 1; + if (reg <= 17) + return 0; + if (reg <= 20) + return 1; + if (reg <= 24) + return 0; + if (reg <= 34) + return 1; + if (reg == 35) + return 0; + if (reg <= 38) + return 1; + if (reg <= 41) + return 0; + if (reg <= 49) + return 1; + if (reg <= 51) + return 0; + if (reg <= 56) + return 1; + if (reg <= 59) + return 0; + if (reg <= 61) + return 1; + if (reg == 62) + return 0; + if (reg <= 79) + return 1; + if (reg == 80) + return 0; + if (reg <= 109) + return 1; + return 0; +} + +/* + * read aic3204 register cache + */ +static inline unsigned int aic3204_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 *cache = codec->reg_cache; + if (reg >= AIC3204_CACHEREGNUM) + return -EINVAL; + + return cache[reg]; +} + +/* + * Pretty-print the value of a register + */ +static int aic3204_show_reg(struct snd_soc_codec *codec, char *buf, + int buf_sz, unsigned int reg) +{ + return snprintf(buf, buf_sz, "%02x", + aic3204_read_reg_cache(codec, reg)); +} + +/* + * write aic3204 register cache + */ +static inline void aic3204_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, u8 value) +{ + u8 *cache = codec->reg_cache; + + if (reg >= AIC3204_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the aic3204 register space + */ +static int aic3204_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + /* data is + * D15..D8 aic3204 register offset + * D7...D0 register data + */ + u8 data[2]; + + /* + * Register number; upper 8 bits indicate page + */ + if (reg && (aic3204_read_reg_cache(codec, AIC3204_PAGE_SELECT) + != (reg >> 7))) { + /* Select the required page */ + data[0] = 0; + data[1] = reg >> 7; + if (codec->hw_write(codec->control_data, data, 2) != 2) + return -EIO; + aic3204_write_reg_cache(codec, AIC3204_PAGE_SELECT, reg >> 7); + dev_dbg(codec->dev, "%s: Page %d selected\n", + __func__, reg >> 7); + } + + data[0] = reg & 0x7f; + data[1] = value & 0xff; + + if (codec->hw_write(codec->control_data, data, 2) != 2) + return -EIO; + + dev_dbg(codec->dev, "%s: pg %d reg %d[%04x] <= %02x\n", + __func__, reg >> 7, reg & 0x7f, reg, value); + aic3204_write_reg_cache(codec, reg, value); + return 0; +} + +/* + * read from the aic3204 register space + */ +static int aic3204_read(struct snd_soc_codec *codec, unsigned int reg, + u8 *value) +{ + *value = reg & 0xff; + + /* + * Register number; upper 8 bits indicate page + */ + if (reg && (aic3204_read_reg_cache(codec, AIC3204_PAGE_SELECT) + != (reg >> 7))) + /* Select the required page */ + aic3204_write(codec, AIC3204_PAGE_SELECT, (reg >> 7)); + + value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]); + dev_dbg(codec->dev, "%s: pg %d reg %d[%04x] => %02x\n", + __func__, reg >> 7, reg & 0x7f, reg, value[0]); + aic3204_write_reg_cache(codec, reg, *value); + return 0; +} + +/* + * Check BCLK direction. Returns >0 if the BCLK pin is an output, 0 if it's an + * input, or negative error. + */ +static inline int aic3204_check_bclk_is_output( + struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + int reg = snd_soc_read(source->codec, AIC3204_AISR1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR1_BCLK; + + return reg & AIC3204_AISR1_BCLK_OUT; +} + +/* + * Check WCLK direction. Returns >0 if the WCLK pin is an output, 0 if it's an + * input, or negative error. + */ + +static inline int aic3204_check_wclk_is_output( + struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + int reg = snd_soc_read(source->codec, AIC3204_AISR1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR1_WCLK; + + return reg & AIC3204_AISR1_WCLK_OUT; +} + +/* + * Check PLL source; called by the PLL input clock DAPM widgets. + * Returns 1 if the two given widgets are presently connected, 0 otherwise. + * Negative error number returned on error. + */ +static int aic3204_check_pll_clk_src(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + int reg = snd_soc_read(source->codec, AIC3204_CLK1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + + reg &= AIC3204_CLK1_PLLSRC; + + if (reg == AIC3204_CLK1_PLLSRC_MCLK) + reg = (!strcmp(source->name, "MCLK")); + else if (reg == AIC3204_CLK1_PLLSRC_BCLK) + reg = (!strcmp(source->name, "BCLK")); + else if (reg == AIC3204_CLK1_PLLSRC_GPIO) + reg = (!strcmp(source->name, "GPIO")); + else if (reg == AIC3204_CLK1_PLLSRC_DIN) + reg = (!strcmp(source->name, "DIN")); + else + reg = 0; + + if (reg) + dev_dbg(source->codec->dev, "%s: %s is connected to %s\n", + __func__, source->name, sink->name); + return reg; +} + +/* + * Check CODEC source; called by the CODEC_CLKIN input clock DAPM widgets. + * Returns 1 if the two given widgets are presently connected, 0 otherwise. + * Negative error number returned on error. + */ +static int aic3204_check_codec_clk_src(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + int reg = snd_soc_read(source->codec, AIC3204_CLK1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + + reg &= AIC3204_CLK1_CODECCLK; + + if (reg == AIC3204_CLK1_CODECCLK_MCLK) + reg = (!strcmp(source->name, "MCLK")); + else if (reg == AIC3204_CLK1_CODECCLK_BCLK) + reg = (!strcmp(source->name, "BCLK")); + else if (reg == AIC3204_CLK1_CODECCLK_GPIO) + reg = (!strcmp(source->name, "GPIO")); + else if (reg == AIC3204_CLK1_CODECCLK_PLL) + reg = (!strcmp(source->name, "PLL_CLK")); + else + reg = 0; + + if (reg) + dev_dbg(source->codec->dev, "%s: %s is connected to %s\n", + __func__, source->name, sink->name); + return reg; +} + +/* + * Check BCLK source; called by the BCLK input clock DAPM widgets. + * Returns 1 if the two given widgets are presently connected, 0 otherwise. + * Negative error number returned on error. + */ +static int aic3204_check_bclk_src(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + int reg = snd_soc_read(source->codec, AIC3204_AISR1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR1_BCLK; + + if (reg == AIC3204_AISR1_BCLK_IN) + /* BCLK is externally generated */ + return 0; + + reg = snd_soc_read(source->codec, AIC3204_AISR3); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR3_BDIV; + + if (reg == AIC3204_AISR3_BDIV_DAC) + reg = (!strcmp(source->name, "DAC_CLK")); + else if (reg == AIC3204_AISR3_BDIV_DAC_MOD) + reg = (!strcmp(source->name, "DAC_MOD_CLK")); + else if (reg == AIC3204_AISR3_BDIV_ADC) + reg = (!strcmp(source->name, "ADC_CLK")); + else if (reg == AIC3204_AISR3_BDIV_ADC_MOD) + reg = (!strcmp(source->name, "ADC_MOD_CLK")); + else + reg = 0; + + if (reg) + dev_dbg(source->codec->dev, "%s: %s is connected to %s\n", + __func__, source->name, sink->name); + return reg; +} + +/* + * Check WCLK source; called by the WCLK input clock DAPM widgets. + * Returns 1 if the two given widgets are presently connected, 0 otherwise. + * Negative error number returned on error. + */ +static int aic3204_check_wclk_src(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + int reg = snd_soc_read(source->codec, AIC3204_AISR1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR1_WCLK; + + if (reg == AIC3204_AISR1_WCLK_IN) + /* WCLK is externally generated */ + return 0; + + reg = snd_soc_read(source->codec, AIC3204_AISR6); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR6_WCLKOUT; + + if (reg == AIC3204_AISR6_WCLKOUT_DAC) + reg = (!strcmp(source->name, "DAC_FS")); + else if (reg == AIC3204_AISR6_WCLKOUT_ADC) + reg = (!strcmp(source->name, "ADC_FS")); + else + reg = 0; + + if (reg) + dev_dbg(source->codec->dev, "%s: %s is connected to %s\n", + __func__, source->name, sink->name); + + return reg; +} + +/* + * Event handler for audio interface BCLK; checks the state of the ADCs and + * DACs and switches the audio interface to the presently active clock. + */ +static int aic3204_aif_bclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) { + u8 adcs_up; + u8 dacs_up; + u8 bclk_src; + /* Determine the current source */ + int reg = snd_soc_read(w->codec, AIC3204_AISR1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR1_BCLK; + if (reg == AIC3204_AISR1_BCLK_IN) + /* BCLK is an input, not our concirn */ + return 0; + + reg = snd_soc_read(w->codec, AIC3204_AISR3); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + bclk_src = reg & AIC3204_AISR3_BDIV; + + /* + * These registers are not manipulated by us, so we must read them from + * the CODEC directly. + */ + reg = aic3204_read(w->codec, AIC3204_ADCF, &adcs_up); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + adcs_up &= (AIC3204_ADCF_LEFT_UP | AIC3204_ADCF_RIGHT_UP); + + reg = aic3204_read(w->codec, AIC3204_DACF1, &dacs_up); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + dacs_up &= (AIC3204_DACF1_LEFT_UP | AIC3204_DACF1_RIGHT_UP); + + dev_dbg(w->codec->dev, "%s: BCLK source=0x%02x, event=%d, " + "dacf1=0x%02x, adcf=0x%02x\n", __func__, bclk_src, + event, dacs_up, adcs_up); + + /* What are we set to now? */ + if (bclk_src == AIC3204_AISR3_BDIV_DAC) { + /* Currently listening to DAC... check that it's up */ + if (adcs_up && !dacs_up) + /* No, but the ADCs are up; switch to those */ + bclk_src = AIC3204_AISR3_BDIV_ADC; + } else if (bclk_src == AIC3204_AISR3_BDIV_DAC_MOD) { + /* Currently listening to DAC... check that it's up */ + if (adcs_up && !dacs_up) + /* No, but the ADCs are up; switch to those */ + bclk_src = AIC3204_AISR3_BDIV_ADC_MOD; + } else if (bclk_src == AIC3204_AISR3_BDIV_ADC) { + /* Currently listening to ADC... check that it's up */ + if (dacs_up && !adcs_up) + /* No, but the DACs are up; switch to those */ + bclk_src = AIC3204_AISR3_BDIV_DAC; + } else if (bclk_src == AIC3204_AISR3_BDIV_ADC_MOD) { + /* Currently listening to ADC... check that it's up */ + if (adcs_up && !dacs_up) + /* No, but the DACs are up; switch to those */ + bclk_src = AIC3204_AISR3_BDIV_DAC_MOD; + } + + dev_dbg(w->codec->dev, "%s: setting source 0x%02x\n", + __func__, bclk_src); + + snd_soc_update_bits(w->codec, AIC3204_AISR3, + AIC3204_AISR3_BDIV, bclk_src); + return 0; +} + +/* + * Event handler for audio interface WCLK; checks the state of the ADCs and + * DACs and switches the audio interface to the presently active clock. + */ +static int aic3204_aif_wclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) { + u8 wclk_src; + u8 adcs_up; + u8 dacs_up; + /* Determine the current source */ + int reg = snd_soc_read(w->codec, AIC3204_AISR1); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + reg &= AIC3204_AISR1_WCLK; + + if (reg == AIC3204_AISR1_WCLK_IN) + /* WCLK is an input, not our concirn */ + return 0; + + reg = snd_soc_read(w->codec, AIC3204_AISR6); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + wclk_src = reg & AIC3204_AISR6_WCLKOUT; + + /* + * These registers are not manipulated by us, so we must read them from + * the CODEC directly. + */ + reg = aic3204_read(w->codec, AIC3204_ADCF, &adcs_up); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + adcs_up &= (AIC3204_ADCF_LEFT_UP | AIC3204_ADCF_RIGHT_UP); + + reg = aic3204_read(w->codec, AIC3204_DACF1, &dacs_up); + if (reg < 0) { + printk(KERN_WARNING "%s: read returned %d\n", __func__, reg); + return reg; + } + dacs_up &= (AIC3204_DACF1_LEFT_UP | AIC3204_DACF1_RIGHT_UP); + + dev_dbg(w->codec->dev, "%s: WCLK source=0x%02x, event=%d, " + "dacf1=0x%02x, adcf=0x%02x\n", __func__, wclk_src, + event, dacs_up, adcs_up); + + /* What are we set to now? */ + if (wclk_src == AIC3204_AISR6_WCLKOUT_DAC) { + /* Currently listening to DAC... check that it's up */ + if (adcs_up && !dacs_up) + /* No, but the ADCs are up; switch to those */ + wclk_src = AIC3204_AISR6_WCLKOUT_ADC; + } else if (wclk_src == AIC3204_AISR6_WCLKOUT_ADC) { + /* Currently listening to ADC... check that it's up */ + if (dacs_up && !adcs_up) + /* No, but the DACs are up; switch to those */ + wclk_src = AIC3204_AISR6_WCLKOUT_DAC; + } + + dev_dbg(w->codec->dev, "%s: setting source 0x%02x\n", + __func__, wclk_src); + + snd_soc_update_bits(w->codec, AIC3204_AISR6, + AIC3204_AISR6_WCLKOUT, wclk_src); + return 0; +} + +/* + * For MICPGA inputs; inputs may either be disconnected, or connected via one + * of three resistances. + */ +static const char *aic3204_micpga_input_mux[] = { + "not-connected", "10k", "20k", "40k" +}; + +static struct soc_enum aic3204_enum_in1l_lmicpgap = + SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE, + 6, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in2l_lmicpgap = + SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE, + 4, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in3l_lmicpgap = + SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE, + 2, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in1r_lmicpgap = + SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE, + 0, 4, aic3204_micpga_input_mux); + +static struct soc_enum aic3204_enum_cm1l_lmicpgan = + SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE, + 6, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in2r_lmicpgan = + SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE, + 4, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in3r_lmicpgan = + SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE, + 2, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_cm2l_lmicpgan = + SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE, + 0, 4, aic3204_micpga_input_mux); + +static struct soc_enum aic3204_enum_in1r_rmicpgap = + SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE, + 6, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in2r_rmicpgap = + SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE, + 4, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in3r_rmicpgap = + SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE, + 2, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in2l_rmicpgap = + SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE, + 0, 4, aic3204_micpga_input_mux); + +static struct soc_enum aic3204_enum_cm1r_rmicpgan = + SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE, + 6, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in1l_rmicpgan = + SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE, + 4, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_in3l_rmicpgan = + SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE, + 2, 4, aic3204_micpga_input_mux); +static struct soc_enum aic3204_enum_cm2r_rmicpgan = + SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE, + 0, 4, aic3204_micpga_input_mux); + +/* + * MICBIAS Voltages; The exact voltage depends on the common mode voltage + * setting... + * + * CM=0.75V CM=0.9V + * Low 1.04V 1.25V + * Medium 1.425V 1.7V + * High 2.075V 2.5V + * V+ Connects to power supply directly in both cases. + */ +static const char *aic3204_micbias_voltages[] = { + "Low", "Med", "High", "V+" +}; +static struct soc_enum aic3204_enum_micbias_voltage = + SOC_ENUM_SINGLE(AIC3204_MICBIAS, + 4, 4, aic3204_micbias_voltages); + +/* + * MICBIAS Voltage Source + */ +static const char *aic3204_micbias_srcs[] = { + "AVDD", "LDOIN" +}; +static struct soc_enum aic3204_enum_micbias_src = + SOC_ENUM_SINGLE(AIC3204_MICBIAS, + 3, 2, aic3204_micbias_srcs); + +/* + * Left DAC Data Source + */ +static const char *aic3204_ldac_srcs[] = { + "disabled", "left channel", "right channel", "mix" +}; +static struct soc_enum aic3204_enum_ldac_src = + SOC_ENUM_SINGLE(AIC3204_DACS1, + 4, 4, aic3204_ldac_srcs); + +/* + * Right DAC Data Source + */ +static const char *aic3204_rdac_srcs[] = { + "disabled", "right channel", "left channel", "mix" +}; +static struct soc_enum aic3204_enum_rdac_src = + SOC_ENUM_SINGLE(AIC3204_DACS1, + 2, 4, aic3204_rdac_srcs); + +/* + * DAC digital volumes. From -63.5 to +24 dB in 0.5 dB steps. + * Does not mute control. + */ +static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); +/* + * ADC gain volumes. From -12dB to 20 dB in 0.5dB steps. + * Does not mute control. + */ +static DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0); +#if 0 +/* + * ADC Fine gain volumes. From -0.4 to 0 dB in 0.1dB steps + * Does not mute control. + */ +static DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0); +#endif +/* + * Output driver stage volumes; -6dB through to +29dB in 1dB steps + * Does not mute control. + */ +static DECLARE_TLV_DB_SCALE(output_stage_tlv, -600, 100, 0); +/* + * MICPGA volumes; 0dB through to +47.5dB in 0.5dB steps. + * Does not mute control + */ +static DECLARE_TLV_DB_SCALE(micpga_tlv, 0, 50, 0); + +static const struct snd_kcontrol_new aic3204_snd_controls[] = { + /* Output */ + + /* + * Note regarding SOC_DOUBLE_R_SX_TLV... + * + * This is a bit misleading; xshift refers to the bit one bit *past* + * the most significant bit. Or at least that's what it appears to be + * doing the math. Mask needs to select the last 6 bits; which is the + * signed bitfield specifiying the gain in dB. + */ + SOC_DOUBLE_R_SX_TLV("Headphone Output Volume", + AIC3204_HPLGAIN, AIC3204_HPRGAIN, + 6, -6, 29, output_stage_tlv), + SOC_DOUBLE_R("Headphone Output Playback Switch", + AIC3204_HPLGAIN, AIC3204_HPRGAIN, + AIC3204_HPLGAIN_MUTE_SHIFT, 0x01, 1), + SOC_DOUBLE_R_SX_TLV("Line Output Playback Volume", + AIC3204_LOLGAIN, AIC3204_LORGAIN, + 6, -6, 29, output_stage_tlv), + SOC_DOUBLE_R("Line Output Playback Switch", AIC3204_LOLGAIN, + AIC3204_LORGAIN, AIC3204_LOLGAIN_MUTE_SHIFT, 0x01, 1), + SOC_DOUBLE_R_SX_TLV("PCM Playback Volume", + AIC3204_LDACVOL, AIC3204_RDACVOL, + 8, -127, 48, dac_tlv), + SOC_DOUBLE("PCM Playback Switch", AIC3204_DACS2, + AIC3204_DACS2_LEFT_MUTE_SHIFT, + AIC3204_DACS2_RIGHT_MUTE_SHIFT, 0x01, 1), + SOC_DOUBLE_R_SX_TLV("Mixer Amplifier Volume", + AIC3204_MALGAIN, AIC3204_MARGAIN, + 6, -6, 29, output_stage_tlv), + + /* DAC Options */ + SOC_ENUM("Left Playback Source", aic3204_enum_ldac_src), + SOC_ENUM("Right Playback Source", aic3204_enum_rdac_src), + SOC_SINGLE("Differential Output Switch", AIC3204_DACS2, + AIC3204_DACS2_RMOD_INV_SHIFT, 1, 0), + + /* MICPGA Options */ + SOC_DOUBLE_R_TLV("MICPGA Capture Volume", + AIC3204_LMICPGAVOL, AIC3204_RMICPGAVOL, + 0, 95, 0, micpga_tlv), + SOC_DOUBLE_R("MICPGA Capture Switch", + AIC3204_LMICPGAVOL, AIC3204_RMICPGAVOL, 7, 0x1, 1), + + /* MICBIAS Options */ + SOC_SINGLE("MICBIAS Enable", AIC3204_MICBIAS, 6, 0x1, 0), + SOC_ENUM("MICBIAS Level", aic3204_enum_micbias_voltage), + SOC_ENUM("MICBIAS Source", aic3204_enum_micbias_src), + + /* ADC */ + SOC_DOUBLE_R_SX_TLV("PCM Capture Volume", + AIC3204_LADCVOL, AIC3204_RADCVOL, + 7, -24, 40, adc_tlv), + SOC_DOUBLE("PCM Capture Switch", AIC3204_ADCFINE, 7, 3, 0x01, 1), + + /* Driver/Amplifier Selection -- DAPM should handle this! */ + SOC_DOUBLE("HP Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_HPL_UP_SHIFT, + AIC3204_OUTDRV_HPR_UP_SHIFT, 0x1, 0), + SOC_DOUBLE("LO Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_LOL_UP_SHIFT, + AIC3204_OUTDRV_LOR_UP_SHIFT, 0x1, 0), + SOC_DOUBLE("MA Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_MAL_UP_SHIFT, + AIC3204_OUTDRV_MAR_UP_SHIFT, 0x1, 0), +}; + +/* Driver/Amplifier Selection */ +static const struct snd_kcontrol_new aic3204_hpl_switch = + SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_HPL_UP_SHIFT, 0x1, 0); +static const struct snd_kcontrol_new aic3204_hpr_switch = + SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_HPR_UP_SHIFT, 0x1, 0); +static const struct snd_kcontrol_new aic3204_lol_switch = + SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_LOL_UP_SHIFT, 0x1, 0); +static const struct snd_kcontrol_new aic3204_lor_switch = + SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_LOR_UP_SHIFT, 0x1, 0); +static const struct snd_kcontrol_new aic3204_mal_switch = + SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_MAL_UP_SHIFT, 0x1, 0); +static const struct snd_kcontrol_new aic3204_mar_switch = + SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_MAR_UP_SHIFT, 0x1, 0); + +/* Line Output Left Driver Inputs */ +static const struct snd_kcontrol_new aic3204_lol_in_controls[] = { + SOC_DAPM_SINGLE("LOR Switch", AIC3204_LOLROUTE, + AIC3204_LOLROUTE_LOR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MAL Switch", AIC3204_LOLROUTE, + AIC3204_LOLROUTE_MAL_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LDAC+ Switch", AIC3204_LOLROUTE, + AIC3204_LOLROUTE_LDACP_SHIFT, 1, 0), + SOC_DAPM_SINGLE("RDAC- Switch", AIC3204_LOLROUTE, + AIC3204_LOLROUTE_RDACN_SHIFT, 1, 0), +}; + +/* Line Output Right Driver Inputs */ +static const struct snd_kcontrol_new aic3204_lor_in_controls[] = { + SOC_DAPM_SINGLE("MAR Switch", AIC3204_LORROUTE, + AIC3204_LORROUTE_MAR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("RDAC+ Switch", AIC3204_LORROUTE, + AIC3204_LORROUTE_RDACP_SHIFT, 1, 0), +}; + +/* Headphone Output Left Driver Inputs */ +static const struct snd_kcontrol_new aic3204_hpl_in_controls[] = { + SOC_DAPM_SINGLE("MAR Switch", AIC3204_HPLROUTE, + AIC3204_HPLROUTE_MAR_SHIFT, 0x1, 0), + SOC_DAPM_SINGLE("MAL Switch", AIC3204_HPLROUTE, + AIC3204_HPLROUTE_MAL_SHIFT, 0x1, 0), + SOC_DAPM_SINGLE("IN1L Switch", AIC3204_HPLROUTE, + AIC3204_HPLROUTE_IN1L_SHIFT, 0x1, 0), + SOC_DAPM_SINGLE("LDAC+ Switch", AIC3204_HPLROUTE, + AIC3204_HPLROUTE_LDACP_SHIFT, 0x1, 0), +}; + +/* Headphone Output Right Driver Inputs */ +static const struct snd_kcontrol_new aic3204_hpr_in_controls[] = { + SOC_DAPM_SINGLE("HPL Switch", AIC3204_HPRROUTE, + AIC3204_HPRROUTE_HPL_SHIFT, 0x1, 0), + SOC_DAPM_SINGLE("MAR Switch", AIC3204_HPRROUTE, + AIC3204_HPRROUTE_MAR_SHIFT, 0x1, 0), + SOC_DAPM_SINGLE("IN1R Switch", AIC3204_HPRROUTE, + AIC3204_HPRROUTE_IN1R_SHIFT, 0x1, 0), + SOC_DAPM_SINGLE("RDAC+ Switch", AIC3204_HPRROUTE, + AIC3204_HPRROUTE_RDACP_SHIFT, 0x1, 0), + SOC_DAPM_SINGLE("LDAC- Switch", AIC3204_HPRROUTE, + AIC3204_HPRROUTE_LDACN_SHIFT, 0x1, 0), +}; + +static const struct snd_kcontrol_new aic3204_lmicpgap_in_controls[] = { + SOC_DAPM_ENUM("IN1L Switch", aic3204_enum_in1l_lmicpgap), + SOC_DAPM_ENUM("IN2L Switch", aic3204_enum_in2l_lmicpgap), + SOC_DAPM_ENUM("IN3L Switch", aic3204_enum_in3l_lmicpgap), + SOC_DAPM_ENUM("IN1R Switch", aic3204_enum_in1r_lmicpgap), +}; + +static const struct snd_kcontrol_new aic3204_lmicpgan_in_controls[] = { + SOC_DAPM_ENUM("CM1L Switch", aic3204_enum_cm1l_lmicpgan), + SOC_DAPM_ENUM("IN2R Switch", aic3204_enum_in2r_lmicpgan), + SOC_DAPM_ENUM("IN3R Switch", aic3204_enum_in3r_lmicpgan), + SOC_DAPM_ENUM("CM2L Switch", aic3204_enum_cm2l_lmicpgan), +}; + +static const struct snd_kcontrol_new aic3204_rmicpgap_in_controls[] = { + SOC_DAPM_ENUM("IN1R Switch", aic3204_enum_in1r_rmicpgap), + SOC_DAPM_ENUM("IN2R Switch", aic3204_enum_in2r_rmicpgap), + SOC_DAPM_ENUM("IN3R Switch", aic3204_enum_in3r_rmicpgap), + SOC_DAPM_ENUM("IN2L Switch", aic3204_enum_in2l_rmicpgap), +}; + +static const struct snd_kcontrol_new aic3204_rmicpgan_in_controls[] = { + SOC_DAPM_ENUM("CM1R Switch", aic3204_enum_cm1r_rmicpgan), + SOC_DAPM_ENUM("IN1L Switch", aic3204_enum_in1l_rmicpgan), + SOC_DAPM_ENUM("IN3L Switch", aic3204_enum_in3l_rmicpgan), + SOC_DAPM_ENUM("CM2R Switch", aic3204_enum_cm2r_rmicpgan), +}; + +static const struct snd_soc_dapm_widget aic3204_dapm_widgets[] = { + /* Driver/Amplifier Selection */ + SND_SOC_DAPM_SWITCH("HPL Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_HPL_UP_SHIFT, 0, + &aic3204_hpl_switch), + SND_SOC_DAPM_SWITCH("HPR Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_HPR_UP_SHIFT, 0, + &aic3204_hpr_switch), + SND_SOC_DAPM_SWITCH("LOL Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_LOL_UP_SHIFT, 0, + &aic3204_lol_switch), + SND_SOC_DAPM_SWITCH("LOR Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_LOR_UP_SHIFT, 0, + &aic3204_lor_switch), + SND_SOC_DAPM_SWITCH("MAL Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_MAL_UP_SHIFT, 0, + &aic3204_mal_switch), + SND_SOC_DAPM_SWITCH("MAR Playback Switch", AIC3204_OUTDRV, + AIC3204_OUTDRV_MAR_UP_SHIFT, 0, + &aic3204_mar_switch), + + /* Line Output Driver Inputs */ + SND_SOC_DAPM_MIXER("Left Line Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_lol_in_controls, + ARRAY_SIZE(aic3204_lol_in_controls)), + SND_SOC_DAPM_MIXER("Right Line Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_lor_in_controls, + ARRAY_SIZE(aic3204_lor_in_controls)), + + /* Headphone Output Driver Inputs */ + SND_SOC_DAPM_MIXER("Left Headphone Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_hpl_in_controls, + ARRAY_SIZE(aic3204_hpl_in_controls)), + SND_SOC_DAPM_MIXER("Right Headphone Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_hpr_in_controls, + ARRAY_SIZE(aic3204_hpr_in_controls)), + + /* DACs, ADCs and audio interfaces */ + SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC3204_DACS1, + AIC3204_DACS1_LDAC_UP_SHIFT, 0), + SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC3204_DACS1, + AIC3204_DACS1_RDAC_UP_SHIFT, 0), + SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC3204_ADCS, + AIC3204_ADCS_RADC_UP_SHIFT, 0), + SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC3204_ADCS, + AIC3204_ADCS_RADC_UP_SHIFT, 0), + SND_SOC_DAPM_AIF_IN("Left Data In", "Left Playback", + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("Right Data In", "Right Playback", + 1, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("Left Data Out", "Left Capture", + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("Right Data Out", "Right Capture", + 1, SND_SOC_NOPM, 0, 0), + + /* System clock sources */ + SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BCLK", AIC3204_CLK12, + AIC3204_CLK12_BCLK_STATE_SHIFT, 0, + aic3204_aif_bclk_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_SUPPLY("WCLK", SND_SOC_NOPM, 0, 0, + aic3204_aif_wclk_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_SUPPLY("GPIO", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DIN", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL_CLK", AIC3204_CLK2, + AIC3204_CLK2_PLL_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CODEC_CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC_CLK", AIC3204_CLK6, + AIC3204_CLK6_NDAC_STATE_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC_MOD_CLK", AIC3204_CLK7, + AIC3204_CLK7_MDAC_STATE_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC_CLK", AIC3204_CLK8, + AIC3204_CLK8_NADC_STATE_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", AIC3204_CLK9, + AIC3204_CLK9_MADC_STATE_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC_FS", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC_FS", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* MICPGA Input Sources */ + SND_SOC_DAPM_MIXER("Left MICPGA+ Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_lmicpgap_in_controls, + ARRAY_SIZE(aic3204_lmicpgap_in_controls)), + SND_SOC_DAPM_MIXER("Left MICPGA- Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_lmicpgan_in_controls, + ARRAY_SIZE(aic3204_lmicpgan_in_controls)), + SND_SOC_DAPM_MIXER("Right MICPGA+ Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_rmicpgap_in_controls, + ARRAY_SIZE(aic3204_rmicpgap_in_controls)), + SND_SOC_DAPM_MIXER("Right MICPGA- Output Mixer", SND_SOC_NOPM, 0, 0, + aic3204_rmicpgan_in_controls, + ARRAY_SIZE(aic3204_rmicpgan_in_controls)), + SND_SOC_DAPM_PGA("Left MICPGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Right MICPGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MICBIAS("Mic Bias", AIC3204_MICBIAS, 6, 0), + + /* Bypass PGAs */ + SND_SOC_DAPM_PGA("IN1L Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IN1R Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Input Pins */ + SND_SOC_DAPM_INPUT("IN1L"), + SND_SOC_DAPM_INPUT("IN1R"), + SND_SOC_DAPM_INPUT("IN2L"), + SND_SOC_DAPM_INPUT("IN2R"), + SND_SOC_DAPM_INPUT("IN3L"), + SND_SOC_DAPM_INPUT("IN3R"), + + /* Output Pins */ + SND_SOC_DAPM_OUTPUT("LOL"), + SND_SOC_DAPM_OUTPUT("LOR"), + SND_SOC_DAPM_OUTPUT("HPL"), + SND_SOC_DAPM_OUTPUT("HPR"), + + /* Common-mode pins */ + SND_SOC_DAPM_VMID("CM1L"), + SND_SOC_DAPM_VMID("CM1R"), + SND_SOC_DAPM_VMID("CM2L"), + SND_SOC_DAPM_VMID("CM2R"), +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* Clock Signals and routing */ + {"PLL_CLK", NULL, "MCLK", aic3204_check_pll_clk_src}, + {"PLL_CLK", NULL, "BCLK", aic3204_check_pll_clk_src}, + {"PLL_CLK", NULL, "GPIO", aic3204_check_pll_clk_src}, + {"PLL_CLK", NULL, "DIN", aic3204_check_pll_clk_src}, + {"CODEC_CLKIN", NULL, "MCLK", aic3204_check_codec_clk_src}, + {"CODEC_CLKIN", NULL, "BCLK", aic3204_check_codec_clk_src}, + {"CODEC_CLKIN", NULL, "GPIO", aic3204_check_codec_clk_src}, + {"CODEC_CLKIN", NULL, "PLL_CLK", aic3204_check_codec_clk_src}, + {"DAC_CLK", NULL, "CODEC_CLKIN"}, + {"DAC_MOD_CLK", NULL, "DAC_CLK"}, + {"DAC_FS", NULL, "DAC_MOD_CLK"}, + {"ADC_CLK", NULL, "CODEC_CLKIN"}, + {"ADC_MOD_CLK", NULL, "ADC_CLK"}, + {"ADC_FS", NULL, "ADC_MOD_CLK"}, + {"BCLK", NULL, "DAC_CLK", aic3204_check_bclk_src}, + {"BCLK", NULL, "DAC_MOD_CLK", aic3204_check_bclk_src}, + {"BCLK", NULL, "ADC_CLK", aic3204_check_bclk_src}, + {"BCLK", NULL, "ADC_MOD_CLK", aic3204_check_bclk_src}, + {"WCLK", NULL, "DAC_FS", aic3204_check_wclk_src}, + {"WCLK", NULL, "ADC_FS", aic3204_check_wclk_src}, + + /* Clock sinks */ + {"Left DAC", NULL, "DAC_MOD_CLK"}, + {"Right DAC", NULL, "DAC_MOD_CLK"}, + {"Left ADC", NULL, "ADC_MOD_CLK"}, + {"Right ADC", NULL, "ADC_MOD_CLK"}, + {"Left Data Out", NULL, "BCLK", aic3204_check_bclk_is_output}, + {"Right Data Out", NULL, "BCLK", aic3204_check_bclk_is_output}, + {"Left Data Out", NULL, "WCLK", aic3204_check_wclk_is_output}, + {"Right Data Out", NULL, "WCLK", aic3204_check_wclk_is_output}, + {"Left Data In", NULL, "BCLK", aic3204_check_bclk_is_output}, + {"Right Data In", NULL, "BCLK", aic3204_check_bclk_is_output}, + {"Left Data In", NULL, "WCLK", aic3204_check_wclk_is_output}, + {"Right Data In", NULL, "WCLK", aic3204_check_wclk_is_output}, + + /* Data Connections */ + {"Left Data Out", NULL, "Left ADC"}, + {"Right Data Out", NULL, "Right ADC"}, + {"Left DAC", NULL, "Left Data In"}, + {"Right DAC", NULL, "Right Data In"}, + + /* Line Output */ + {"Left Line Output Mixer", "LOR Switch", "Right Line Output Mixer"}, + {"Left Line Output Mixer", "MAL Switch", "Left MICPGA"}, + {"Left Line Output Mixer", "LDAC+ Switch", "Left DAC"}, + {"Left Line Output Mixer", "RDAC- Switch", "Right DAC"}, + {"Right Line Output Mixer", "MAR Switch", "Right MICPGA"}, + {"Right Line Output Mixer", "RDAC+ Switch", "Right DAC"}, + {"LOL", "LOL Playback Switch", "Left Line Output Mixer"}, + {"LOR", "LOR Playback Switch", "Right Line Output Mixer"}, + + /* Headphone Output */ + {"Left Headphone Output Mixer", "MAR Switch", "Right MICPGA"}, + {"Left Headphone Output Mixer", "MAL Switch", "Left MICPGA"}, + {"Left Headphone Output Mixer", "IN1L Switch", "IN1L Bypass PGA"}, + {"Left Headphone Output Mixer", "LDAC+ Switch", "Left DAC"}, + {"Right Headphone Output Mixer", "HPL Switch", + "Left Headphone Output Mixer"}, + {"Right Headphone Output Mixer", "MAR Switch", "Right MICPGA"}, + {"Right Headphone Output Mixer", "IN1R Switch", "IN1R Bypass PGA"}, + {"Right Headphone Output Mixer", "RDAC+ Switch", "Right DAC"}, + {"Right Headphone Output Mixer", "LDAC- Switch", "Left DAC"}, + {"HPL", "HPL Playback Switch", "Left Headphone Output Mixer"}, + {"HPR", "HPR Playback Switch", "Right Headphone Output Mixer"}, + + /* MICPGA Input */ + {"Left MICPGA+ Output Mixer", "IN1L Switch", "IN1L"}, + {"Left MICPGA+ Output Mixer", "IN2L Switch", "IN2L"}, + {"Left MICPGA+ Output Mixer", "IN3L Switch", "IN3L"}, + {"Left MICPGA+ Output Mixer", "IN1R Switch", "IN1R"}, + {"Left MICPGA- Output Mixer", "CM1L Switch", "CM1L"}, + {"Left MICPGA- Output Mixer", "IN2R Switch", "IN2R"}, + {"Left MICPGA- Output Mixer", "IN3R Switch", "IN3R"}, + {"Left MICPGA- Output Mixer", "CM2L Switch", "CM2L"}, + {"Right MICPGA+ Output Mixer", "IN1R Switch", "IN1R"}, + {"Right MICPGA+ Output Mixer", "IN2R Switch", "IN2R"}, + {"Right MICPGA+ Output Mixer", "IN3R Switch", "IN3R"}, + {"Right MICPGA+ Output Mixer", "IN2L Switch", "IN2L"}, + {"Right MICPGA- Output Mixer", "CM1R Switch", "CM1R"}, + {"Right MICPGA- Output Mixer", "IN1L Switch", "IN1L"}, + {"Right MICPGA- Output Mixer", "IN3L Switch", "IN3L"}, + {"Right MICPGA- Output Mixer", "CM2R Switch", "CM2R"}, + {"Left MICPGA", "MAL Playback Switch", "Left MICPGA+ Output Mixer"}, + {"Right MICPGA", "MAR Playback Switch", "Right MICPGA+ Output Mixer"}, + {"Left MICPGA", "MAL Playback Switch", "Left MICPGA- Output Mixer"}, + {"Right MICPGA", "MAR Playback Switch", "Right MICPGA- Output Mixer"}, + + /* ADC Input */ + {"Left ADC", NULL, "Left MICPGA"}, + {"Right ADC", NULL, "Right MICPGA"}, +}; + +static int aic3204_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, aic3204_dapm_widgets, + ARRAY_SIZE(aic3204_dapm_widgets)); + + /* set up audio path interconnects */ + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + return 0; +} + +static int aic3204_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct aic3204_priv *aic3204 = snd_soc_codec_get_drvdata(codec); + int dac_clk = 0, bit_clk = 0; + int codec_clk = 0, bypass_pll = 0, last_clk = 0, last_error = 0; + u8 data = 0, ndac = 0, mdac = 0, bdiv = 1; + u8 pll_p = 1, pll_r = 1, pll_j = 1; + u16 pll_d = 0; + + int this_clk = 0, this_error = 0; + unsigned int this_abs_error; + u8 j, this_ndac; + u16 d; + + /* Determine the DAC clock and bit clock needed */ + dac_clk = aic3204->pdata.osr * params_rate(params); + bit_clk = params_rate(params) * params_channels(params); + + /* + * Select data word length. + * Note that the number of bits per frame used + * to determine BDIV is double the number of bits per sample, as there + * are two samples per frame. + */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + pr_debug("%s: Sample format 16 bits\n", __func__); + bit_clk *= 16; + data = AIC3204_AISR1_WL_16BITS; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + pr_debug("%s: Sample format 20 bits\n", __func__); + bit_clk *= 32; + data = AIC3204_AISR1_WL_20BITS; + break; + case SNDRV_PCM_FORMAT_S24_LE: + pr_debug("%s: Sample format 24 bits\n", __func__); + bit_clk *= 40; + data = AIC3204_AISR1_WL_24BITS; + break; + case SNDRV_PCM_FORMAT_S32_LE: + pr_debug("%s: Sample format 32 bits\n", __func__); + bit_clk *= 48; + data = AIC3204_AISR1_WL_32BITS; + break; + } + snd_soc_update_bits(codec, AIC3204_AISR1, AIC3204_AISR1_WL, data); + + pr_debug("%s: DAC Clock = %d Hz, Bit clock = %d Hz\n", __func__, + dac_clk, bit_clk); + + /* Try to find a value for div which allows us to bypass the PLL and + * generate CODEC_CLK directly. */ + for (this_ndac = 128; this_ndac >= 1; this_ndac--) { + this_clk = aic3204->sysclk / this_ndac; + + if (this_clk == dac_clk) { + pr_debug("%s: Scored exact match. NDAC=%d; " + "DAC_CLK=%d\n", + __func__, this_ndac, this_clk); + bypass_pll = 1; + ndac = this_ndac; + break; + } + } + + if (bypass_pll) { + /* Select MCLK as CODEC_CLKIN */ + aic3204_write(codec, AIC3204_CLK1, AIC3204_CLK1_CODECCLK_MCLK); + codec_clk = aic3204->sysclk; + goto setup_codec; + } + + /* + * Determine PLL Parameters... the input/output frequency ratio + * of the PLL is given in the datasheet: + * + * out R * J * (D/10000) J D + * --- = ----------------- = R * - * ------- + * in P P 10000 + * + * Limitations: + * - R range: 1..4 + * - J range: 4..63 + * - D range: 0..9999 + * - P range: 1..8 + * - If D == 0; + * 512 kHz <= in / P <= 20 MHz + * else + * 10 MHz <= in / P <= 20 MHz + * + * We will try for 8* the target frequency; then use NDAC/NADC to divide + * that down. If we set P = 1, and R = 1; we simplify the solution. + */ + pll_p = 1; + pll_r = 1; + for (this_ndac = 1; this_ndac <= 128; this_ndac++) { + int ratio, init_ratio; + + codec_clk = dac_clk * this_ndac; + + /* Ensure maximum CODEC frequency is not exceeded */ + if (codec_clk > 137000000) + continue; + if ((this_ndac % 2) && (codec_clk > 110000000)) + continue; + + /* Initial Fixed-point ratio ... this will be slightly lower */ + init_ratio = codec_clk / (aic3204->sysclk / 10000); + + pr_debug("%s: NDAC = %d, PLL J.D * 10000 = %d\n", + __func__, this_ndac, init_ratio); + if (init_ratio < 40000) + continue; + if (init_ratio > 639999) + continue; + + for (ratio = init_ratio; (ratio < init_ratio + 10000) + && (ratio < 639999); ratio++) { + j = ratio / 10000; + d = ratio % 10000; + + this_clk = aic3204->sysclk / 10000; + this_clk *= (10000 * j) + d; + this_error = this_clk - codec_clk; + this_abs_error = abs(this_error); + + if (this_abs_error > 1000) + continue; + + pr_debug("%s: Fractional PLL search; " + "P=%d R=%d J=%d D=%04d => " + "(%d * %d) / 10000 => %d " + "(%d error) [NDAC=%d]\n", + __func__, pll_p, pll_r, + j, d, aic3204->sysclk, + ratio, this_clk, this_error, + this_ndac); + if (!last_clk || (this_abs_error < last_error)) { + last_clk = this_clk; + last_error = this_abs_error; + ndac = this_ndac; + pll_j = j; + pll_d = d; + /* Early finish for exact match */ + if (!this_abs_error) + break; + } + } + } + + /* If we still haven't found anything; bail out here! */ + if (!last_clk) + goto fail; + + pr_debug("%s: Best Output: %d (%d Hz Error)\n", + __func__, last_clk, last_error); + pr_debug("%s: setting up PLL: P=%d R=%d J.D=%d.%04d\n", + __func__, pll_p, pll_r, pll_j, pll_d); + + codec_clk = last_clk; + + aic3204_write(codec, AIC3204_CLK4, (pll_d >> AIC3204_CLK4_PLL_D_VSHIFT) + & AIC3204_CLK4_PLL_D); /* PLL D[14:8] */ + aic3204_write(codec, AIC3204_CLK5, pll_d & AIC3204_CLK5_PLL_D); + /* PLL D[7:0] */ + aic3204_write(codec, AIC3204_CLK3, pll_j & AIC3204_CLK3_PLL_J); + /* PLL J */ + aic3204_write(codec, AIC3204_CLK2, + (pll_r & AIC3204_CLK2_PLL_R) /* PLL R */ + | ((pll_p << AIC3204_CLK2_PLL_P_SHIFT) + & AIC3204_CLK2_PLL_P) + /* PLL P */ + | AIC3204_CLK2_PLL_ON); /* PLL on */ + + /* Select PLL as CODEC_CLKIN */ + aic3204_write(codec, AIC3204_CLK1, AIC3204_CLK1_CODECCLK_PLL); + +setup_codec: + pr_debug("%s: CODEC CLK = %d => DAC CLK = %d\n", + __func__, codec_clk, codec_clk / ndac); + /* Calculate BDIV and NDAC */ + mdac = codec_clk / (ndac * dac_clk); + if (!mdac) + mdac = 1; + + bdiv = dac_clk / bit_clk; + if (!bdiv) + bdiv = 1; + + /* Set AOSR and DOSR */ + aic3204_write(codec, AIC3204_DOSR1, + (aic3204->pdata.osr >> AIC3204_DOSR1_MSB_VSHIFT) + & AIC3204_DOSR1_MSB); /* DOSR[9:8] */ + aic3204_write(codec, AIC3204_DOSR2, aic3204->pdata.osr + & AIC3204_DOSR2_LSB); /* DOSR[7:0] */ + aic3204_write(codec, AIC3204_AOSR, aic3204->pdata.osr); /* AOSR */ + + pr_debug("%s: NDAC = %d\n", __func__, ndac); + /* Set NDAC to divider value */ + aic3204_write(codec, AIC3204_CLK6, AIC3204_CLK6_NDAC_STATE_ON | ndac); + /* Set NADC to match NDAC */ + aic3204_write(codec, AIC3204_CLK8, AIC3204_CLK8_NADC_STATE_ON | ndac); + /* Set MDAC and turn on */ + aic3204_write(codec, AIC3204_CLK7, AIC3204_CLK7_MDAC_STATE_ON | mdac); + /* Use MDAC for MADC */ + aic3204_write(codec, AIC3204_CLK9, AIC3204_CLK7_MDAC_STATE_ON | mdac); + + /* Set BCLK and WCLK */ + pr_debug("%s: Bit clock divider = %d\n", __func__, bdiv); + /* Turn on and set BCLK N divider */ + aic3204_write(codec, AIC3204_CLK12, bdiv + | AIC3204_CLK12_BCLK_STATE_ON); + + /* + * Set BCLK and WCLK sources... + * + * Despite DAPM; this is still needed, as DAPM doesn't yet set the + * source at the right time. + * + * TODO: See if we can change the order of initialisation so this + * selection is made after bringing up the ADCs/DACs. Alternative: + * see if we can find out ahead of time which one to use. + */ + snd_soc_update_bits(codec, AIC3204_AISR3, AIC3204_AISR3_BDIV, + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ? AIC3204_AISR3_BDIV_DAC + : AIC3204_AISR3_BDIV_ADC); + snd_soc_update_bits(codec, AIC3204_AISR6, AIC3204_AISR6_WCLKOUT, + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ? AIC3204_AISR6_WCLKOUT_DAC + : AIC3204_AISR6_WCLKOUT_ADC); + return 0; +fail: + printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); + return -EINVAL; +} + +static int aic3204_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u8 dacs2; + + dacs2 = aic3204_read_reg_cache(codec, AIC3204_DACS2); + + if (mute) { + dacs2 |= (1 << AIC3204_DACS2_LEFT_MUTE_SHIFT) + | (1 << AIC3204_DACS2_RIGHT_MUTE_SHIFT); + } else { + dacs2 &= ~((1 << AIC3204_DACS2_LEFT_MUTE_SHIFT) + | (1 << AIC3204_DACS2_RIGHT_MUTE_SHIFT)); + } + + aic3204_write(codec, AIC3204_DACS2, dacs2); /* Unmute DAC */ + return 0; +} + +static int aic3204_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct aic3204_priv *aic3204 = snd_soc_codec_get_drvdata(codec); + + aic3204->sysclk = freq; + return 0; +} + +static int aic3204_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 aisr1 = 0, aisr2 = 0, aisr3 = 0; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + aisr1 |= AIC3204_AISR1_BCLK_OUT + | AIC3204_AISR1_WCLK_OUT; + break; + case SND_SOC_DAIFMT_CBM_CFS: + aisr1 |= AIC3204_AISR1_BCLK_OUT + | AIC3204_AISR1_WCLK_IN; + break; + case SND_SOC_DAIFMT_CBS_CFM: + aisr1 |= AIC3204_AISR1_BCLK_IN + | AIC3204_AISR1_WCLK_OUT; + break; + case SND_SOC_DAIFMT_CBS_CFS: + aisr1 |= AIC3204_AISR1_BCLK_IN + | AIC3204_AISR1_WCLK_IN; + break; + default: + printk(KERN_ERR "%s: Clock mode not supported " + "(fmt=0x%08x)\n", __func__, fmt); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + aisr1 |= AIC3204_AISR1_INT_I2S; + break; + case SND_SOC_DAIFMT_DSP_A: + aisr2 = 1; + case SND_SOC_DAIFMT_DSP_B: + aisr1 |= AIC3204_AISR1_INT_DSP; + break; + case SND_SOC_DAIFMT_RIGHT_J: + aisr1 |= AIC3204_AISR1_INT_RJF; + break; + case SND_SOC_DAIFMT_LEFT_J: + aisr1 |= AIC3204_AISR1_INT_LJF; + break; + default: + printk(KERN_ERR "%s: SSI mode not supported " + "(fmt=0x%08x)\n", __func__, fmt); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + aisr3 |= AIC3204_AISR3_BCLKPOL_NOR; + break; + case SND_SOC_DAIFMT_IB_NF: + aisr3 |= AIC3204_AISR3_BCLKPOL_INV; + break; + default: + printk(KERN_ERR "%s: Clock inversion mode not " + "supported (fmt=0x%08x)\n", __func__, fmt); + return -EINVAL; + } + + /* set iface */ + aic3204_write(codec, AIC3204_AISR1, aisr1); + aic3204_write(codec, AIC3204_AISR2, aisr2); + aic3204_write(codec, AIC3204_AISR3, aisr3); + + return 0; +} + +#define AIC3204_RATES SNDRV_PCM_RATE_8000_96000 +#define AIC3204_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops aic3204_dai_ops = { + .hw_params = aic3204_hw_params, + .digital_mute = aic3204_mute, + .set_sysclk = aic3204_set_dai_sysclk, + .set_fmt = aic3204_set_dai_fmt, +}; + +struct snd_soc_dai aic3204_dai = { + .name = "tlv320aic3204", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = AIC3204_RATES, + .formats = AIC3204_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AIC3204_RATES, + .formats = AIC3204_FORMATS,}, + .ops = &aic3204_dai_ops, +}; +EXPORT_SYMBOL_GPL(aic3204_dai); + +static int aic3204_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + int i; + u8 data[2]; + u8 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < AIC3204_CACHEREGNUM; i++) { + data[0] = i; + data[1] = cache[i]; + codec->hw_write(codec->control_data, data, 2); + } + + return 0; +} + +/* + * initialise the AIC3204 driver + * register the mixer and dsp interfaces with the kernel + */ +static int aic3204_init(struct snd_soc_codec *codec) +{ + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + codec->name = "tlv320aic3204"; + codec->owner = THIS_MODULE; + codec->read = aic3204_read_reg_cache; + codec->write = aic3204_write; + codec->dai = &aic3204_dai; + codec->num_dai = 1; + codec->reg_cache_size = AIC3204_CACHEREGNUM; + codec->reg_cache = kmemdup(aic3204_default_reg_data, + AIC3204_CACHEREGNUM, GFP_KERNEL); + codec->readable_register = aic3204_reg_is_readable; + codec->display_register = aic3204_show_reg; + if (codec->reg_cache == NULL) + return -ENOMEM; + + /* Reset the CODEC */ + aic3204_write(codec, AIC3204_PAGE_SELECT, 0); + aic3204_write(codec, AIC3204_RESET, AIC3204_RESET_SOFT); + + return 0; +} + +static struct snd_soc_codec *aic3204_codec; + +static int aic3204_register(struct snd_soc_codec *codec) +{ + int ret; + + ret = aic3204_init(codec); + if (ret < 0) { + dev_err(codec->dev, "Failed to initialise device\n"); + return ret; + } + + aic3204_codec = codec; + + ret = snd_soc_register_codec(codec); + if (ret) { + dev_err(codec->dev, "Failed to register codec\n"); + return ret; + } + + ret = snd_soc_register_dai(&aic3204_dai); + if (ret) { + dev_err(codec->dev, "Failed to register dai\n"); + snd_soc_unregister_codec(codec); + return ret; + } + + return 0; +} + +static int aic3204_unregister(struct aic3204_priv *aic3204) +{ + snd_soc_unregister_dai(&aic3204_dai); + snd_soc_unregister_codec(&aic3204->codec); + + if (aic3204->pdata.gpio_reset >= 0) { + gpio_set_value(aic3204->pdata.gpio_reset, 0); + gpio_free(aic3204->pdata.gpio_reset); + } + regulator_bulk_disable(ARRAY_SIZE(aic3204->supplies), + aic3204->supplies); + regulator_bulk_free(ARRAY_SIZE(aic3204->supplies), aic3204->supplies); + + kfree(aic3204); + aic3204_codec = NULL; + + return 0; +} + +static int aic3204_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct snd_soc_codec *codec; + struct aic3204_priv *aic3204; + struct aic3204_pdata *pdata = i2c->dev.platform_data; + int ret, i; + + aic3204 = kzalloc(sizeof(struct aic3204_priv), GFP_KERNEL); + if (aic3204 == NULL) { + dev_err(&i2c->dev, "failed to create private data\n"); + return -ENOMEM; + } + + codec = &aic3204->codec; + codec->dev = &i2c->dev; + snd_soc_codec_set_drvdata(codec, aic3204); + codec->control_data = i2c; + codec->hw_write = (hw_write_t) i2c_master_send; + + i2c_set_clientdata(i2c, aic3204); + + dev_dbg(&i2c->dev, "%s: platform data at %p\n", + __func__, pdata); + if (pdata) + memcpy(&aic3204->pdata, pdata, sizeof(struct aic3204_pdata)); + else + memcpy(&aic3204->pdata, &aic3204_default_pdata, + sizeof(struct aic3204_pdata)); + + if (aic3204->pdata.gpio_reset >= 0) { + ret = gpio_request(aic3204->pdata.gpio_reset, + "tlv320aic3204 reset"); + if (ret != 0) + goto err_gpio; + gpio_direction_output(aic3204->pdata.gpio_reset, 0); + } + + for (i = 0; i < ARRAY_SIZE(aic3204->supplies); i++) + aic3204->supplies[i].supply = aic3204_supply_names[i]; + + ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3204->supplies), + aic3204->supplies); + if (ret != 0) { + dev_err(codec->dev, "Failed to request supplies: %d\n", ret); + goto err_get; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(aic3204->supplies), + aic3204->supplies); + if (ret != 0) { + dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); + goto err_enable; + } + + if (aic3204->pdata.gpio_reset >= 0) { + udelay(1); + gpio_set_value(aic3204->pdata.gpio_reset, 1); + } + + return aic3204_register(codec); + +err_enable: + regulator_bulk_free(ARRAY_SIZE(aic3204->supplies), aic3204->supplies); +err_get: + if (aic3204->pdata.gpio_reset >= 0) + gpio_free(aic3204->pdata.gpio_reset); +err_gpio: + kfree(aic3204); + return ret; +} + +static int aic3204_i2c_remove(struct i2c_client *client) +{ + struct aic3204_priv *aic3204 = i2c_get_clientdata(client); + + return aic3204_unregister(aic3204); +} + +static const struct i2c_device_id aic3204_i2c_id[] = { + { "tlv320aic3204", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, aic3204_i2c_id); + +/* machine i2c codec control layer */ +static struct i2c_driver aic3204_i2c_driver = { + .driver = { + .name = "tlv320aic3204-i2c", + .owner = THIS_MODULE, + }, + .probe = aic3204_i2c_probe, + .remove = aic3204_i2c_remove, + .id_table = aic3204_i2c_id, +}; + +static inline void aic3204_i2c_init(void) +{ + int ret; + + ret = i2c_add_driver(&aic3204_i2c_driver); + if (ret) + printk(KERN_ERR "%s: error regsitering i2c driver, %d\n", + __func__, ret); +} + +static inline void aic3204_i2c_exit(void) +{ + i2c_del_driver(&aic3204_i2c_driver); +} + +static int aic3204_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct aic3204_setup_data *setup; + struct snd_soc_codec *codec; + struct aic3204_priv *aic3204; + int ret = 0; + + codec = aic3204_codec; + if (!codec) { + dev_err(&pdev->dev, "Codec not registered\n"); + return -ENODEV; + } + + socdev->card->codec = codec; + setup = socdev->codec_data; + aic3204 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: private data at %p\n", + __func__, aic3204); + /* Initialise the CODEC with the given settings */ + /* Analogue Input Quick-Charge Power-Up delay */ + ret = aic3204_write(codec, AIC3204_AIQC, + aic3204->pdata.ain_pwrup_delay); + if (ret) + return ret; + + /* Analogue Reference Power-Up delay */ + aic3204_write(codec, AIC3204_REFPU, + aic3204->pdata.ref_pwrup_delay); + if (ret) + return ret; + + /* AVDD<->DVDD link */ + snd_soc_update_bits(codec, AIC3204_POWER, + AIC3204_POWER_AVDD_DVDD_UNLINK, + aic3204->pdata.avdd_link_en ? + 0 : AIC3204_POWER_AVDD_DVDD_UNLINK); + + /* LDO enable, analogue blocks enable */ + snd_soc_update_bits(codec, AIC3204_LDO, + AIC3204_LDO_ANALOG | AIC3204_LDO_AVDD_UP, + AIC3204_LDO_ANALOG_ENABLED | + (aic3204->pdata.ldo_en + ? AIC3204_LDO_AVDD_UP : 0)); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "aic3204: failed to create pcms\n"); + goto pcm_err; + } + + snd_soc_add_controls(codec, aic3204_snd_controls, + ARRAY_SIZE(aic3204_snd_controls)); + + aic3204_add_widgets(codec); + + return ret; + +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static int aic3204_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + + kfree(codec->reg_cache); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_aic3204 = { + .probe = aic3204_probe, + .remove = aic3204_remove, + .resume = aic3204_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_aic3204); + +static int __init aic3204_modinit(void) +{ + aic3204_i2c_init(); + + return 0; +} +module_init(aic3204_modinit); + +static void __exit aic3204_exit(void) +{ + aic3204_i2c_exit(); +} +module_exit(aic3204_exit); + +MODULE_DESCRIPTION("ASoC TLV320AIC3204 codec driver"); +MODULE_AUTHOR("Jacques Electronics Pty Ltd"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/tlv320aic3204.h b/sound/soc/codecs/tlv320aic3204.h new file mode 100644 index 0000000..8f9ee43 --- /dev/null +++ b/sound/soc/codecs/tlv320aic3204.h @@ -0,0 +1,1350 @@ +/* + * ALSA SoC TLV320AIC3204 codec driver + * + * Author: Stuart Longland, <redhatter(a)gentoo.org> + * Copyright: (C) 2010 Jacques Electronics, Pty, Ltd. + * + * Author: Vladimir Barinov, <vbarinov(a)embeddedalley.com> + * Copyright: (C) 2007 MontaVista Software, Inc., <source(a)mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _AIC3204_H +#define _AIC3204_H + +/* + * The AIC3204's registers are divided into separate pages, the first page of + * every register is a "page select", which sets the current page being + * accessed. For the purposes of simplicity; we shall consider all registers + * as being addressed by a 16-bit value, consisting of the page number as + * most-significant 9 bits, followed by the register number as given in the + * datasheet. + * + * The register access functions will look after page flipping from here. + */ + +/* + * AIC3204 register space; 128 registers each page, we pages 0..127. It's not + * clear from the datasheet exactly how many pages are in use... and it's a + * sparse register map! Ideally, I'd like to just cache the pages that are + * needed, but the ALSA framework doesn't allow this easily. + * + * It does look as if up to and including page 70 is needed. For now, we will + * cache up to page 128 however; as this ensures we get *everything*. + */ +#define AIC3204_CACHEREGNUM (128*128) + +/* Page select register */ +#define AIC3204_PAGE_SELECT 0 + +/* Register Page/Number => Address Mapping Macro */ +#define AIC3204_PGREG(page, reg) (((page) << 7) | ((reg) & 0x7f)) + +/* Software reset register */ +#define AIC3204_RESET AIC3204_PGREG(0, 1) +/* Perform software reset */ +#define AIC3204_RESET_SOFT 1 + +/* Clock Setting Register 1, Multiplexers */ +#define AIC3204_CLK1 AIC3204_PGREG(0, 4) +/* PLL Range Select: Low Range */ +#define AIC3204_CLK1_PLLRANGE_LOW (0 << 6) +/* PLL Range Select: High Range */ +#define AIC3204_CLK1_PLLRANGE_HIGH (1 << 6) +/* PLL Range Select Mask */ +#define AIC3204_CLK1_PLLRANGE (1 << 6) +/* PLL Input Clock Select: MCLK */ +#define AIC3204_CLK1_PLLSRC_MCLK (0 << 2) +/* PLL Input Clock Select: BCLK */ +#define AIC3204_CLK1_PLLSRC_BCLK (1 << 2) +/* PLL Input Clock Select: GPIO */ +#define AIC3204_CLK1_PLLSRC_GPIO (2 << 2) +/* PLL Input Clock Select: Data In */ +#define AIC3204_CLK1_PLLSRC_DIN (3 << 2) +/* PLL Input Clock Select Mask */ +#define AIC3204_CLK1_PLLSRC (3 << 2) +/* CODEC Clock Source Select: MCLK */ +#define AIC3204_CLK1_CODECCLK_MCLK (0) +/* CODEC Clock Source Select: BCLK */ +#define AIC3204_CLK1_CODECCLK_BCLK (1) +/* CODEC Clock Source Select: GPIO */ +#define AIC3204_CLK1_CODECCLK_GPIO (2) +/* CODEC Clock Source Select: PLL */ +#define AIC3204_CLK1_CODECCLK_PLL (3) +/* CODEC Clock Source Select Mask */ +#define AIC3204_CLK1_CODECCLK (3) + +/* Clock Setting Register 2, PLL P & R Values */ +#define AIC3204_CLK2 AIC3204_PGREG(0, 5) +/* PLL State: Powered Down */ +#define AIC3204_CLK2_PLL_OFF (0 << 7) +/* PLL State: Powered Up */ +#define AIC3204_CLK2_PLL_ON (1 << 7) +/* PLL State Mask */ +#define AIC3204_CLK2_PLL (1 << 7) +/* PLL State bitfield location */ +#define AIC3204_CLK2_PLL_SHIFT (7) +/* PLL P Divider value bitfield location */ +#define AIC3204_CLK2_PLL_P_SHIFT (4) +/* PLL P Divider value bitfield mask */ +#define AIC3204_CLK2_PLL_P (7 << 4) +/* PLL R Divider value bitfield location */ +#define AIC3204_CLK2_PLL_R_SHIFT (0) +/* PLL R Divider value bitfield mask */ +#define AIC3204_CLK2_PLL_R (0xf) + +/* Clock Setting Register 3, PLL J Values */ +#define AIC3204_CLK3 AIC3204_PGREG(0, 6) +/* PLL J Divider value bitfield location */ +#define AIC3204_CLK3_PLL_J_SHIFT (0) +/* PLL J Divider value bitfield mask */ +#define AIC3204_CLK3_PLL_J (0x3f) + +/* Clock Setting Register 4, PLL D MSB */ +#define AIC3204_CLK4 AIC3204_PGREG(0, 7) +/* PLL D most significant portion bitfield location */ +#define AIC3204_CLK4_PLL_D_SHIFT (0) +/* PLL D most significant portion bitfield mask */ +#define AIC3204_CLK4_PLL_D (0x3f) +/* PLL D most significant portion value shift */ +#define AIC3204_CLK4_PLL_D_VSHIFT (8) + +/* Clock Setting Register 5, PLL D LSB */ +#define AIC3204_CLK5 AIC3204_PGREG(0, 8) +/* PLL D least significant portion bitfield location */ +#define AIC3204_CLK5_PLL_D_SHIFT (0) +/* PLL D least significant portion bitfield mask */ +#define AIC3204_CLK5_PLL_D (0xff) +/* PLL D least significant portion value shift */ +#define AIC3204_CLK5_PLL_D_VSHIFT (0) + +/* Clock Setting Register 6, NDAC Values */ +#define AIC3204_CLK6 AIC3204_PGREG(0, 11) +/* NDAC State: Powered Down */ +#define AIC3204_CLK6_NDAC_STATE_OFF (0 << 7) +/* NDAC State: Powered Up */ +#define AIC3204_CLK6_NDAC_STATE_ON (1 << 7) +/* NDAC State Mask */ +#define AIC3204_CLK6_NDAC_STATE (1 << 7) +/* NDAC State bitfield location */ +#define AIC3204_CLK6_NDAC_STATE_SHIFT (7) +/* NDAC value bitfield location */ +#define AIC3204_CLK6_NDAC_SHIFT (0) +/* NDAC value bitfield mask */ +#define AIC3204_CLK6_NDAC (0x7f) + +/* Clock Setting Register 7, MDAC Values */ +#define AIC3204_CLK7 AIC3204_PGREG(0, 12) +/* MDAC State: Powered Down */ +#define AIC3204_CLK7_MDAC_STATE_OFF (0 << 7) +/* MDAC State: Powered Up */ +#define AIC3204_CLK7_MDAC_STATE_ON (1 << 7) +/* MDAC State Mask */ +#define AIC3204_CLK7_MDAC_STATE (1 << 7) +/* MDAC State bitfield location */ +#define AIC3204_CLK7_MDAC_STATE_SHIFT (7) +/* MDAC value bitfield location */ +#define AIC3204_CLK7_MDAC_SHIFT (0) +/* MDAC value bitfield mask */ +#define AIC3204_CLK7_MDAC (0x7f) + +/* DAC OSR Setting Register 1, MSB */ +#define AIC3204_DOSR1 AIC3204_PGREG(0, 13) +/* DOSR most significant portion bitfield location */ +#define AIC3204_DOSR1_MSB_SHIFT (0) +/* DOSR most significant portion bitfield mask */ +#define AIC3204_DOSR1_MSB (3) +/* DOSR most significant portion value shift */ +#define AIC3204_DOSR1_MSB_VSHIFT (8) + +/* DAC OSR Setting Register 2, LSB */ +#define AIC3204_DOSR2 AIC3204_PGREG(0, 14) +/* DOSR least significant portion bitfield location */ +#define AIC3204_DOSR2_LSB_SHIFT (0) +/* DOSR least significant portion bitfield mask */ +#define AIC3204_DOSR2_LSB (0xff) +/* DOSR least significant portion value shift */ +#define AIC3204_DOSR2_LSB_VSHIFT (0) + +/* Clock Setting Register 8, NADC Values */ +#define AIC3204_CLK8 AIC3204_PGREG(0, 18) +/* NADC State: Powered Down */ +#define AIC3204_CLK8_NADC_STATE_OFF (0 << 7) +/* NADC State: Powered Up */ +#define AIC3204_CLK8_NADC_STATE_ON (1 << 7) +/* NADC State Mask */ +#define AIC3204_CLK8_NADC_STATE (1 << 7) +/* NADC State bitfield location */ +#define AIC3204_CLK8_NADC_STATE_SHIFT (7) +/* NADC value bitfield location */ +#define AIC3204_CLK8_NADC_SHIFT (0) +/* NADC value bitfield mask */ +#define AIC3204_CLK8_NADC (0x7f) + +/* Clock Setting Register 9, MADC Values */ +#define AIC3204_CLK9 AIC3204_PGREG(0, 19) +/* MADC State: Powered Down */ +#define AIC3204_CLK9_MADC_STATE_OFF (0 << 7) +/* MADC State: Powered Up */ +#define AIC3204_CLK9_MADC_STATE_ON (1 << 7) +/* MADC State Mask */ +#define AIC3204_CLK9_MADC_STATE (1 << 7) +/* MADC State bitfield location */ +#define AIC3204_CLK9_MADC_STATE_SHIFT (7) +/* MADC value bitfield location */ +#define AIC3204_CLK9_MADC_SHIFT (0) +/* MADC value bitfield mask */ +#define AIC3204_CLK9_MADC (0x7f) + +/* ADC OSR Setting Register */ +#define AIC3204_AOSR AIC3204_PGREG(0, 20) + +/* + * Clock Register setting 10, Multiplexers + * + * XXX: Note that the datasheet goofs up here, calling this register 9, but we + * already had a register 9 just before AOSR. Therefore, we will call this + * register 10, and will increment all following by one to correct TI's + * mistake. + */ +#define AIC3204_CLK10 AIC3204_PGREG(0, 25) +/* CDIV Clock Source: MCLK */ +#define AIC3204_CLK10_CDIV_MCLK (0) +/* CDIV Clock Source: BCLK */ +#define AIC3204_CLK10_CDIV_BCLK (1) +/* CDIV Clock Source: Data IN */ +#define AIC3204_CLK10_CDIV_DIN (2) +/* CDIV Clock Source: PLL */ +#define AIC3204_CLK10_CDIV_PLL (3) +/* CDIV Clock Source: DAC */ +#define AIC3204_CLK10_CDIV_DAC (4) +/* CDIV Clock Source: DAC Modulation */ +#define AIC3204_CLK10_CDIV_DAC_MOD (5) +/* CDIV Clock Source: ADC */ +#define AIC3204_CLK10_CDIV_ADC (6) +/* CDIV Clock Source: ADC Modulation */ +#define AIC3204_CLK10_CDIV_ADC_MOD (7) +/* CDIV Clock Source Mask */ +#define AIC3204_CLK10_CDIV (7) + +/* Clock Register setting 11, CLKOUT M divider value */ +#define AIC3204_CLK11 AIC3204_PGREG(0, 26) +/* CLKOUT Divider State: Off */ +#define AIC3204_CLK11_CLKOUT_OFF (0 << 7) +/* CLKOUT Divider State: On */ +#define AIC3204_CLK11_CLKOUT_ON (1 << 7) +/* CLKOUT Divider State Mask */ +#define AIC3204_CLK11_CLKOUT (1 << 7) +/* CLKOUT Divider M value bitfield location */ +#define AIC3204_CLK11_CLKOUTM_SHIFT (0) +/* CLKOUT Divider M value bitfield mask */ +#define AIC3204_CLK11_CLKOUTM (0x7f) + +/* Audio Interface Setting Register 1 */ +#define AIC3204_AISR1 AIC3204_PGREG(0, 27) +/* Audio Interface Select: I2S */ +#define AIC3204_AISR1_INT_I2S (0 << 6) +/* Audio Interface Select: DSP */ +#define AIC3204_AISR1_INT_DSP (1 << 6) +/* Audio Interface Select: Right-Justified Format */ +#define AIC3204_AISR1_INT_RJF (2 << 6) +/* Audio Interface Select: Left-Justified Format */ +#define AIC3204_AISR1_INT_LJF (3 << 6) +/* Audio Interface Select Mask */ +#define AIC3204_AISR1_INT (3 << 6) +/* Audio Data Word Length: 16 bits */ +#define AIC3204_AISR1_WL_16BITS (0 << 4) +/* Audio Data Word Length: 20 bits */ +#define AIC3204_AISR1_WL_20BITS (1 << 4) +/* Audio Data Word Length: 24 bits */ +#define AIC3204_AISR1_WL_24BITS (2 << 4) +/* Audio Data Word Length: 32 bits */ +#define AIC3204_AISR1_WL_32BITS (3 << 4) +/* Audio Data Word Length Mask */ +#define AIC3204_AISR1_WL (3 << 4) +/* BCLK Direction Control: Input */ +#define AIC3204_AISR1_BCLK_IN (0 << 3) +/* BCLK Direction Control: Output */ +#define AIC3204_AISR1_BCLK_OUT (1 << 3) +/* BCLK Direction Control: Mask */ +#define AIC3204_AISR1_BCLK (1 << 3) +/* WCLK Direction Control: Input */ +#define AIC3204_AISR1_WCLK_IN (0 << 2) +/* WCLK Direction Control: Output */ +#define AIC3204_AISR1_WCLK_OUT (1 << 2) +/* WCLK Direction Control: Mask */ +#define AIC3204_AISR1_WCLK (1 << 2) +/* DOUT High Impedance Output Control: Never high impedance */ +#define AIC3204_AISR1_HIZ_NEVER (0 << 0) +/* DOUT High Impedance Output Control: High impedance when idle */ +#define AIC3204_AISR1_HIZ_IDLE (1 << 0) +/* DOUT High Impedance Output Control Mask */ +#define AIC3204_AISR1_HIZ (1 << 0) + +/* Audio Interface Register 2, Data offset setting */ +#define AIC3204_AISR2 AIC3204_PGREG(0, 28) + +/* Audio Interface Register 3 */ +#define AIC3204_AISR3 AIC3204_PGREG(0, 29) +/* Audio Data Loopback Control: Disabled */ +#define AIC3204_AISR3_ADLO_OFF (0 << 5) +/* Audio Data Loopback Control: Enabled */ +#define AIC3204_AISR3_ADLO_ON (1 << 5) +/* Audio Data Loopback Control Mask */ +#define AIC3204_AISR3_ADLO (1 << 5) +/* ADC->DAC Loopback Control: Disabled */ +#define AIC3204_AISR3_ADDALO_OFF (0 << 4) +/* ADC->DAC Loopback Control: Enabled */ +#define AIC3204_AISR3_ADDALO_ON (1 << 4) +/* ADC->DAC Loopback Control Mask */ +#define AIC3204_AISR3_ADDALO (1 << 4) +/* Audio Bit Clock Polarity: Normal */ +#define AIC3204_AISR3_BCLKPOL_NOR (0 << 3) +/* Audio Bit Clock Polarity: Inverted */ +#define AIC3204_AISR3_BCLKPOL_INV (1 << 3) +/* Audio Bit Clock Polarity Mask */ +#define AIC3204_AISR3_BCLKPOL (1 << 3) +/* Audio Data Interface Clock Buffers: Always powered */ +#define AIC3204_AISR3_ADICLK_ALWAYS (0 << 2) +/* Audio Data Interface Clock Buffers: Powered with CODEC only */ +#define AIC3204_AISR3_ADICLK_CODEC (1 << 2) +/* Audio Data Interface Clock Buffers' State */ +#define AIC3204_AISR3_ADICLK (1 << 2) +/* Audio Bit Clock Divider Source: DAC */ +#define AIC3204_AISR3_BDIV_DAC (0 << 0) +/* Audio Bit Clock Divider Source: DAC Modulation */ +#define AIC3204_AISR3_BDIV_DAC_MOD (1 << 0) +/* Audio Bit Clock Divider Source: ADC */ +#define AIC3204_AISR3_BDIV_ADC (2 << 0) +/* Audio Bit Clock Divider Source: ADC Modulation */ +#define AIC3204_AISR3_BDIV_ADC_MOD (3 << 0) +/* Audio Bit Clock Divider Source Mask */ +#define AIC3204_AISR3_BDIV (3 << 0) + +/* Clock Setting Register 12, BCLK N Divider */ +#define AIC3204_CLK12 AIC3204_PGREG(0, 30) +/* BCLK N State: Powered Down */ +#define AIC3204_PG0_CLK12_BCLK_STATE_OFF (0 << 7) +/* BCLK N State: Powered Up */ +#define AIC3204_CLK12_BCLK_STATE_ON (1 << 7) +/* BCLK N State Mask */ +#define AIC3204_CLK12_BCLK_STATE (1 << 7) +/* BCLK N State bitfield location */ +#define AIC3204_CLK12_BCLK_STATE_SHIFT (7) +/* BCLK N value bitfield location */ +#define AIC3204_CLK12_BCLK_SHIFT (0) +/* BCLK N value bitfield mask */ +#define AIC3204_CLK12_BCLK (0x7f) + +/* Audio Interface Setting Register 4, Secondary Audio Interface */ +#define AIC3204_AISR4 AIC3204_PGREG(0, 31) +/* Secondary Bit Clock: GPIO */ +#define AIC3204_AISR4_SECBCLK_GPIO (0 << 5) +/* Secondary Bit Clock: SCLK */ +#define AIC3204_AISR4_SECBCLK_SCLK (1 << 5) +/* Secondary Bit Clock: MISO */ +#define AIC3204_AISR4_SECBCLK_MISO (2 << 5) +/* Secondary Bit Clock: DOUT */ +#define AIC3204_AISR4_SECBCLK_DOUT (3 << 5) +/* Secondary Bit Clock Mask */ +#define AIC3204_AISR4_SECBCLK (3 << 5) +/* Secondary Word Clock: GPIO */ +#define AIC3204_AISR4_SECWCLK_GPIO (0 << 3) +/* Secondary Word Clock: SCLK */ +#define AIC3204_AISR4_SECWCLK_SCLK (1 << 3) +/* Secondary Word Clock: MISO */ +#define AIC3204_AISR4_SECWCLK_MISO (2 << 3) +/* Secondary Word Clock: DOUT */ +#define AIC3204_AISR4_SECWCLK_DOUT (3 << 3) +/* Secondary Word Clock Mask */ +#define AIC3204_AISR4_SECWCLK (3 << 3) +/* ADC Word Clock: GPIO */ +#define AIC3204_AISR4_ADCWCLK_GPIO (0 << 3) +/* ADC Word Clock: SCLK */ +#define AIC3204_AISR4_ADCWCLK_SCLK (1 << 3) +/* ADC Word Clock: MISO */ +#define AIC3204_AISR4_ADCWCLK_MISO (2 << 3) +/* ADC Word Clock Mask */ +#define AIC3204_AISR4_ADCWCLK (3 << 3) +/* Secondary Data Input: GPIO */ +#define AIC3204_AISR4_SECDIN_GPIO (0 << 0) +/* Secondary Data Input: SCLK */ +#define AIC3204_AISR4_SECDIN_SCLK (1 << 0) +/* Secondary Data Input Mask */ +#define AIC3204_AISR4_SECDIN (1 << 0) + +/* Audio Interface Setting Register 5 */ +#define AIC3204_AISR5 AIC3204_PGREG(0, 32) +/* Audio Interface Bit Clock: Primary (BCLK) */ +#define AIC3204_AISR5_BCLKIN_PRI (0 << 3) +/* Audio Interface Bit Clock: Secondary */ +#define AIC3204_AISR5_BCLKIN_SEC (1 << 3) +/* Audio Interface Bit Clock Mask */ +#define AIC3204_AISR5_WCLKIN (1 << 2) +/* Audio Interface Word Clock: Primary (BCLK) */ +#define AIC3204_AISR5_WCLKIN_PRI (0 << 2) +/* Audio Interface Word Clock: Secondary */ +#define AIC3204_AISR5_WCLKIN_SEC (1 << 2) +/* Audio Interface Word Clock Mask */ +#define AIC3204_AISR5_WCLKIN (1 << 2) +/* ADC Word Clock Control: ADC WCLK = DAC WCLK */ +#define ADC3204_PG0_AISR5_ADCWCLK_DAC (0 << 1) +/* ADC Word Clock Control: ADC WCLK = Secondary ADC WCLK */ +#define ADC3204_PG0_AISR5_ADCWCLK_SEC (1 << 1) +/* ADC Word Clock Control Mask */ +#define ADC3204_PG0_AISR5_ADCWCLK (1 << 1) +/* Audio Data In: Primary Data In */ +#define ADC3204_PG0_AISR5_DIN_PRI (0 << 0) +/* Audio Data In: Secondary Data In */ +#define ADC3204_PG0_AISR5_DIN_SEC (1 << 0) +/* Audio Data In Mask */ +#define ADC3204_PG0_AISR5_DIN (1 << 0) + +/* Audio Interface Setting Register 6 */ +#define AIC3204_AISR6 AIC3204_PGREG(0, 33) +/* BCLK Output Control: Generated Primary Bit Clock */ +#define AIC3204_AISR6_BCLKOUT_GEN (0 << 7) +/* BCLK Output Control: Secondary Bit Clock */ +#define AIC3204_AISR6_BCLKOUT_SEC (1 << 7) +/* BCLK Output Control Mask */ +#define AIC3204_AISR6_BCLKOUT (1 << 7) +/* Secondary BCLK Output Control: Primary Bit Clock Input */ +#define AIC3204_AISR6_SBCLKOUT_BCLK (0 << 6) +/* Secondary BCLK Output Control: Generated Primary Bit Clock */ +#define AIC3204_AISR6_SBCLKOUT_GEN (1 << 6) +/* Secondary BCLK Output Control Mask */ +#define AIC3204_AISR6_SBCLKOUT (1 << 6) +/* WCLK Output Control: Generated DAC_FS */ +#define AIC3204_AISR6_WCLKOUT_DAC (0 << 4) +/* WCLK Output Control: Generated ADC_FS */ +#define AIC3204_AISR6_WCLKOUT_ADC (1 << 4) +/* WCLK Output Control: Secondary WCLK Input */ +#define AIC3204_AISR6_WCLKOUT_SWCLK (2 << 4) +/* WCLK Output Control Mask */ +#define AIC3204_AISR6_WCLKOUT (3 << 4) +/* Secondary WCLK Output Control: WCLK Input */ +#define AIC3204_AISR6_SWCLKOUT_WCLK (0 << 2) +/* Secondary WCLK Output Control: Generated DAC_FS */ +#define AIC3204_AISR6_SWCLKOUT_DAC (1 << 2) +/* Secondary WCLK Output Control: Generated ADC_FS */ +#define AIC3204_AISR6_SWCLKOUT_ADC (2 << 2) +/* Secondary WCLK Output Control Mask */ +#define AIC3204_AISR6_SWCLKOUT (3 << 2) +/* Primary Data Output Control: Serial Interface */ +#define AIC3204_AISR6_DOUT_INT (0 << 1) +/* Primary Data Output Control: Secondary Data Input */ +#define AIC3204_AISR6_DOUT_SDIN (1 << 1) +/* Primary Data Output Control Mask */ +#define AIC3204_AISR6_DOUT (1 << 1) +/* Secondary Data Output Control: Primary Data In */ +#define AIC3204_AISR6_SDOUT_DIN (0 << 0) +/* Secondary Data Output Control: Serial Interface */ +#define AIC3204_AISR6_SDOUT_INT (1 << 0) +/* Secondary Data Output Control Mask */ +#define AIC3204_AISR6_SDOUT (1 << 0) + +/* Digital Interface Misc. Setting Register */ +#define AIC3204_DIMISC AIC3204_PGREG(0, 34) +/* I2C General Call Address Configuration: Ignore */ +#define AIC3204_DIMISC_I2CGC_IGNORE (0 << 5) +/* I2C General Call Address Configuration: Accept */ +#define AIC3204_DIMISC_I2CGC_ACCEPT (1 << 5) + +/* ADC Flag Register */ +#define AIC3204_ADCF AIC3204_PGREG(0, 36) +/* Left ADC PGA Status: Gain is set */ +#define AIC3204_ADCF_LEFT_PGASET (1 << 7) +/* Left ADC Power Status: Powered Up */ +#define AIC3204_ADCF_LEFT_UP (1 << 6) +/* Left ADC AGC Status: Gain is saturated */ +#define AIC3204_ADCF_LEFT_AGCSAT (1 << 5) +/* Right ADC PGA Status: Gain is set */ +#define AIC3204_ADCF_RIGHT_PGASET (1 << 3) +/* Right ADC Power Status: Powered Up */ +#define AIC3204_ADCF_RIGHT_UP (1 << 2) +/* Right ADC AGC Status: Gain is saturated */ +#define AIC3204_ADCF_RIGHT_AGCSAT (1 << 1) + +/* DAC Flag Register 1 */ +#define AIC3204_DACF1 AIC3204_PGREG(0, 37) +/* Left DAC powered up */ +#define AIC3204_DACF1_LEFT_UP (1 << 7) +/* Left Line Output Driver powered up */ +#define AIC3204_DACF1_LOL_UP (1 << 6) +/* Left Headphone Output Driver powered up */ +#define AIC3204_DACF1_HPL_UP (1 << 5) +/* Right DAC powered up */ +#define AIC3204_DACF1_RIGHT_UP (1 << 7) +/* Right Line Output Driver powered up */ +#define AIC3204_DACF1_LOR_UP (1 << 6) +/* Right Headphone Output Driver powered up */ +#define AIC3204_DACF1_HPR_UP (1 << 5) + +/* DAC Flag Register 2 */ +#define AIC3204_DACF2 AIC3204_PGREG(0, 38) +/* Left DAC PGA Status: Gain is set */ +#define AIC3204_DACF2_LEFT_PGASET (1 << 4) +/* Right DAC PGA Status: Gain is set */ +#define AIC3204_DACF2_RIGHT_PGASET (1 << 0) + +/* Sticky Flag Register 1 */ +#define AIC3204_STICK1 AIC3204_PGREG(0, 42) +/* Left DAC Overflow */ +#define AIC3204_STICK1_LDAC_OVER (1 << 7) +/* Right DAC Overflow */ +#define AIC3204_STICK1_RDAC_OVER (1 << 6) +/* Left ADC Overflow */ +#define AIC3204_STICK1_LADC_OVER (1 << 3) +/* Right ADC Overflow */ +#define AIC3204_STICK1_RADC_OVER (1 << 2) + +/* Interrupt Flag Register 1 */ +#define AIC3204_INTF1 AIC3204_PGREG(0, 43) +/* Left DAC Overflow */ +#define AIC3204_INTF1_LDAC_OVER (1 << 7) +/* Right DAC Overflow */ +#define AIC3204_INTF1_RDAC_OVER (1 << 6) +/* Left ADC Overflow */ +#define AIC3204_INTF1_LADC_OVER (1 << 3) +/* Right ADC Overflow */ +#define AIC3204_INTF1_RADC_OVER (1 << 2) + +/* Sticky Flag Register 2 */ +#define AIC3204_STICK2 AIC3204_PGREG(0, 44) +/* Left Headphone Driver Over Current */ +#define AIC3204_STICK2_HPL_OVER (1 << 7) +/* Right Headphone Driver Over Current */ +#define AIC3204_STICK2_HPR_OVER (1 << 6) +/* Headset button pressed */ +#define AIC3204_STICK2_HS_BUTTON (1 << 5) +/* Headset plug inserted/removed */ +#define AIC3204_STICK2_HS_PLUGGED (1 << 4) +/* Left Channel DRC: Over threshold */ +#define AIC3204_STICK2_LDRC_OVER (1 << 3) +/* Right Channel DRC: Over threshold */ +#define AIC3204_STICK2_RDRC_OVER (1 << 2) + +/* Sticky Flag Register 3 */ +#define AIC3204_STICK3 AIC3204_PGREG(0, 45) +/* Left AGC Noise Threshold Flag: Over threshold */ +#define AIC3204_STICK3_LAGC_OVER (1 << 6) +/* Right AGC Noise Threshold Flag: Over threshold */ +#define AIC3204_STICK3_RAGC_OVER (1 << 5) +/* Left ADC DC Measurement Available */ +#define AIC3204_STICK3_LADC_DC (1 << 2) +/* Right ADC DC Measurement Available */ +#define AIC3204_STICK3_RADC_DC (1 << 1) + +/* Interrupt Flag Register 2 */ +#define AIC3204_INTF2 AIC3204_PGREG(0, 46) +/* Left Headphone Driver Over Current */ +#define AIC3204_INTF2_HPL_OVER (1 << 7) +/* Right Headphone Driver Over Current */ +#define AIC3204_INTF2_HPR_OVER (1 << 6) +/* Headset button pressed */ +#define AIC3204_INTF2_HS_BUTTON (1 << 5) +/* Headset plug inserted/removed */ +#define AIC3204_INTF2_HS_PLUGGED (1 << 4) +/* Left Channel DRC: Over threshold */ +#define AIC3204_INTF2_LDRC_OVER (1 << 3) +/* Right Channel DRC: Over threshold */ +#define AIC3204_INTF2_RDRC_OVER (1 << 2) + +/* Interrupt Flag Register 3 */ +#define AIC3204_INTF3 AIC3204_PGREG(0, 47) +/* Left AGC Noise Threshold Flag: Over threshold */ +#define AIC3204_INTF3_LAGC_OVER (1 << 6) +/* Right AGC Noise Threshold Flag: Over threshold */ +#define AIC3204_INTF3_RAGC_OVER (1 << 5) +/* Left ADC DC Measurement Available */ +#define AIC3204_INTF3_LADC_DC (1 << 2) +/* Right ADC DC Measurement Available */ +#define AIC3204_INTF3_RADC_DC (1 << 1) + +/* INT1 Interrupt Control Register */ +#define AIC3204_INT1 AIC3204_PGREG(0, 48) +/* INT1 Generated on Headset insertion */ +#define AIC3204_INT1_HS_PLUG (1 << 7) +/* INT1 Generated on Headset Button press */ +#define AIC3204_INT1_HS_BUTTON (1 << 6) +/* INT1 Generated on DAC DRC Signal Threshold */ +#define AIC3204_INT1_DAC_DRC (1 << 5) +/* INT1 Generated on AGC Noise Interrupt */ +#define AIC3204_INT1_ADC_NOISE (1 << 4) +/* INT1 Generated on Over Current */ +#define AIC3204_INT1_HP_OVERCURRENT (1 << 3) +/* INT1 Generated on overflow event */ +#define AIC3204_INT1_OVERFLOW (1 << 2) +/* INT1 Generated on DC measurement */ +#define AIC3204_INT1_DC (1 << 1) +/* INT1 pulse control: Continuous pulse train */ +#define AIC3204_INT1_CONT_PULSE (1 << 0) + +/* INT2 Interrupt Control Register */ +#define AIC3204_INT2 AIC3204_PGREG(0, 49) +/* INT2 Generated on Headset insertion */ +#define AIC3204_INT2_HS_PLUG (1 << 7) +/* INT2 Generated on Headset Button press */ +#define AIC3204_INT2_HS_BUTTON (1 << 6) +/* INT2 Generated on DAC DRC Signal Threshold */ +#define AIC3204_INT2_DAC_DRC (1 << 5) +/* INT2 Generated on AGC Noise Interrupt */ +#define AIC3204_INT2_ADC_NOISE (1 << 4) +/* INT2 Generated on Over Current */ +#define AIC3204_INT2_HP_OVERCURRENT (1 << 3) +/* INT2 Generated on overflow event */ +#define AIC3204_INT2_OVERFLOW (1 << 2) +/* INT2 Generated on DC measurement */ +#define AIC3204_INT2_DC (1 << 1) +/* INT2 pulse control: Continuous pulse train */ +#define AIC3204_INT2_CONT_PULSE (1 << 0) + +/* GPIO/MFP5 Control Register */ +#define AIC3204_MFP5 AIC3204_PGREG(0, 52) +/* GPIO Control: Disabled */ +#define AIC3204_MFP5_FUNC_DISABLED (0 << 2) +/* GPIO Control: Secondary audio interface/digital microphone/clock input */ +#define AIC3204_MFP5_FUNC_SAI_DM_CI (1 << 2) +/* GPIO Control: General Purpose Input */ +#define AIC3204_MFP5_FUNC_INPUT (2 << 2) +/* GPIO Control: General Purpose Output */ +#define AIC3204_MFP5_FUNC_OUTPUT (3 << 2) +/* GPIO Control: CLKOUT Output */ +#define AIC3204_MFP5_FUNC_CLKOUT (4 << 2) +/* GPIO Control: INT1 Output */ +#define AIC3204_MFP5_FUNC_INT1 (4 << 2) +/* GPIO Control: INT2 Output */ +#define AIC3204_MFP5_FUNC_INT2 (4 << 2) +/* GPIO Control: ADC_WCLK */ +#define AIC3204_MFP5_FUNC_ADC_WCLK (4 << 2) +/* GPIO Control: Secondary Bit Clock */ +#define AIC3204_MFP5_FUNC_SEC_BCLK (4 << 2) +/* GPIO Control: Secondary Word Clock */ +#define AIC3204_MFP5_FUNC_SEC_WCLK (4 << 2) +/* GPIO Control: Digital Microphone Clock */ +#define AIC3204_MFP5_FUNC_DMIC_CLK (4 << 2) +/* GPIO Control Mask */ +#define AIC3204_MFP5_FUNC (15 << 2) +/* GPIO Input State */ +#define AIC3204_MFP5_IN (1 << 1) +/* GPIO Output State */ +#define AIC3204_MFP5_OUT (1 << 0) + +/* DOUT/MFP2 Function Control Register */ +#define AIC3204_MFP2 AIC3204_PGREG(0, 53) +/* DOUT Bus Keeper Enabled */ +#define AIC3204_MFP2_BK (1 << 4) +/* DOUT MUX Control: Disabled */ +#define AIC3204_MFP2_FUNC_DISABLED (0 << 1) +/* DOUT MUX Control: Primary DOUT */ +#define AIC3204_MFP2_FUNC_PRI_DOUT (1 << 1) +/* DOUT MUX Control: General Purpose Output */ +#define AIC3204_MFP2_FUNC_OUTPUT (2 << 1) +/* DOUT MUX Control: CLKOUT Clock Output */ +#define AIC3204_MFP2_FUNC_CLKOUT (3 << 1) +/* DOUT MUX Control: INT1 Output */ +#define AIC3204_MFP2_FUNC_INT1 (4 << 1) +/* DOUT MUX Control: INT2 Output */ +#define AIC3204_MFP2_FUNC_INT2 (5 << 1) +/* DOUT MUX Control: Secondary Bit Clock */ +#define AIC3204_MFP2_FUNC_SEC_BCLK (6 << 1) +/* DOUT MUX Control: Secondary Word Clock */ +#define AIC3204_MFP2_FUNC_SEC_WCLK (7 << 1) +/* DOUT MUX Control Mask */ +#define AIC3204_MFP2_FUNC (7 << 1) +/* DOUT General Purpose Output State */ +#define AIC3204_MFP2_OUT (1 << 0) + +/* DIN/MFP1 Function Control Register */ +#define AIC3204_MFP1 AIC3204_PGREG(0, 54) +/* DIN Function Control: Disabled */ +#define AIC3204_MFP1_FUNC_DISABLED (0 << 1) +/* DIN Function Control: Primary Data Input/Digital Microphone/Clock Input */ +#define AIC3204_MFP1_FUNC_DIN_DM_CI (1 << 1) +/* DIN Function Control: General Purpose Input */ +#define AIC3204_MFP1_FUNC_INPUT (2 << 1) +/* DIN Function Control Mask */ +#define AIC3204_MFP1_FUNC (3 << 1) +/* DIN Input State */ +#define AIC3204_MFP1_IN (1 << 0) + +/* MISO/MFP4 Function Control Register */ +#define AIC3204_MFP4 AIC3204_PGREG(0, 55) +/* MISO Function Control: Disabled */ +#define AIC3204_MFP4_FUNC_DISABLED (0 << 1) +/* MISO Function Control: SPI Data Output (disabled in I2C mode) */ +#define AIC3204_MFP4_FUNC_SPI_OUT (1 << 1) +/* MISO Function Control: General Purpose Output */ +#define AIC3204_MFP4_FUNC_OUTPUT (2 << 1) +/* MISO Function Control: CLKOUT Clock Output */ +#define AIC3204_MFP4_FUNC_CLKOUT (3 << 1) +/* MISO Function Control: INT1 Output */ +#define AIC3204_MFP4_FUNC_INT1 (4 << 1) +/* MISO Function Control: INT2 Output */ +#define AIC3204_MFP4_FUNC_INT2 (5 << 1) +/* MISO Function Control: ADC Word Clock Output */ +#define AIC3204_MFP4_FUNC_ADC_WCLK (6 << 1) +/* MISO Function Control: Digital Microphone Clock Output */ +#define AIC3204_MFP4_FUNC_DMIC_CLK (7 << 1) +/* MISO Function Control: Secondary Data Output */ +#define AIC3204_MFP4_FUNC_SEC_DOUT (8 << 1) +/* MISO Function Control: Secondary Bit Clock */ +#define AIC3204_MFP4_FUNC_SEC_BCLK (9 << 1) +/* MISO Function Control: Secondary Word Clock */ +#define AIC3204_MFP4_FUNC_SEC_WCLK (10 << 1) +/* MISO Function Control Mask */ +#define AIC3204_MFP4_FUNC (15 << 1) +/* MISO Output State */ +#define AIC3204_MFP4_OUT (1 << 0) + +/* SCLK/MFP3 Function Control Register */ +#define AIC3204_MFP3 AIC3204_PGREG(0, 56) +/* SCLK Function Control: Disabled */ +#define AIC3204_MFP3_FUNC_DISABLED (0 << 1) +/* SCLK Function Control: SPI Clock / Secondary Interface / Digital Mic Input */ +#define AIC3204_MFP3_FUNC_SPI_SI_DM (1 << 1) +/* SCLK Function Control: General Purpose Input */ +#define AIC3204_MFP3_FUNC_INPUT (2 << 1) +/* SCLK Function Control Mask */ +#define AIC3204_MFP3_FUNC (3 << 1) +/* SCLK Input State */ +#define AIC3204_MFP3_IN (1 << 0) + +/* DAC Signal Processing Block Control Register */ +#define AIC3204_DACSPB AIC3204_PGREG(0, 60) +/* DAC Signal Processing Block Mask */ +#define AIC3204_DACSPB_MASK 0x1f + +/* ADC Signal Processing Block Control Register */ +#define AIC3204_ADCSPB AIC3204_PGREG(0, 61) +/* ADC Signal Processing Block Mask */ +#define AIC3204_ADCSPB_MASK 0x1f + +/* DAC Channel Setup Register 1 */ +#define AIC3204_DACS1 AIC3204_PGREG(0, 63) +/* Left DAC Powered Up */ +#define AIC3204_DACS1_LDAC_UP_SHIFT (7) +/* Right DAC Powered Up */ +#define AIC3204_DACS1_RDAC_UP_SHIFT (6) +/* Left DAC Data Path Control: Disabled */ +#define AIC3204_DACS1_LDACD_DIS (0 << 4) +/* Left DAC Data Path Control: Left Data */ +#define AIC3204_DACS1_LDACD_LEFT (1 << 4) +/* Left DAC Data Path Control: Right Data */ +#define AIC3204_DACS1_LDACD_RIGHT (2 << 4) +/* Left DAC Data Path Control: Left + Right */ +#define AIC3204_DACS1_LDACD_MIX (3 << 4) +/* Left DAC Data Path Control Mask */ +#define AIC3204_DACS1_LDACD (3 << 4) +/* Right DAC Data Path Control: Disabled */ +#define AIC3204_DACS1_RDACD_DIS (0 << 2) +/* Right DAC Data Path Control: Right Data */ +#define AIC3204_DACS1_RDACD_RIGHT (1 << 2) +/* Right DAC Data Path Control: Left Data */ +#define AIC3204_DACS1_RDACD_LEFT (2 << 2) +/* Right DAC Data Path Control: Left + Right */ +#define AIC3204_DACS1_RDACD_MIX (3 << 2) +/* Right DAC Data Path Control Mask */ +#define AIC3204_DACS1_RDACD (3 << 2) +/* DAC Soft-Step: Disabled */ +#define AIC3204_DACS1_SOFT_DIS (0 << 0) +/* DAC Soft-Step: 1 step every clock */ +#define AIC3204_DACS1_SOFT_1SEC (1 << 0) +/* DAC Soft-Step: 1 step every 2 clocks */ +#define AIC3204_DACS1_SOFT_1SE2C (2 << 0) +/* DAC Soft-Step Mask */ +#define AIC3204_DACS1_SOFT (3 << 0) + +/* DAC Channel Setup Register 2 */ +#define AIC3204_DACS2 AIC3204_PGREG(0, 64) +/* Right Modulator Output Control: Output is inverted left output */ +#define AIC3204_DACS2_RMOD_INV_SHIFT (7) +/* DAC Auto Mute: Disabled */ +#define AIC3204_DACS2_AMUTE_DIS (0 << 4) +/* DAC Auto Mute: After 100 samples of DC */ +#define AIC3204_DACS2_AMUTE_100 (1 << 4) +/* DAC Auto Mute: After 200 samples of DC */ +#define AIC3204_DACS2_AMUTE_200 (2 << 4) +/* DAC Auto Mute: After 400 samples of DC */ +#define AIC3204_DACS2_AMUTE_400 (3 << 4) +/* DAC Auto Mute: After 800 samples of DC */ +#define AIC3204_DACS2_AMUTE_800 (4 << 4) +/* DAC Auto Mute: After 1600 samples of DC */ +#define AIC3204_DACS2_AMUTE_1600 (5 << 4) +/* DAC Auto Mute: After 3200 samples of DC */ +#define AIC3204_DACS2_AMUTE_3200 (6 << 4) +/* DAC Auto Mute: After 6400 samples of DC */ +#define AIC3204_DACS2_AMUTE_6400 (7 << 4) +/* DAC Auto Mute Mask */ +#define AIC3204_DACS2_AMUTE (7 << 4) +/* Left DAC Muted */ +#define AIC3204_DACS2_LEFT_MUTE_SHIFT (3) +/* Right DAC Muted */ +#define AIC3204_DACS2_RIGHT_MUTE_SHIFT (2) +/* DAC Master Volume Control: Independant */ +#define AIC3204_DACS2_VOL_IND (0 << 0) +/* DAC Master Volume Control: Left controls right */ +#define AIC3204_DACS2_VOL_LEFT (1 << 0) +/* DAC Master Volume Control: Right controls left */ +#define AIC3204_DACS2_VOL_RIGHT (2 << 0) +/* DAC Master Volume Control Mask */ +#define AIC3204_DACS2_VOL (3 << 0) + +/* Left DAC Digital Volume Control */ +#define AIC3204_LDACVOL AIC3204_PGREG(0, 65) + +/* Right DAC Digital Volume Control */ +#define AIC3204_RDACVOL AIC3204_PGREG(0, 66) + +/* Headset Detection Configuration Register */ +#define AIC3204_HSDET AIC3204_PGREG(0, 67) +/* Enable Headset Detection */ +#define AIC3204_HSDET_ENABLE (1 << 7) +/* Headset Type: No Headset */ +#define AIC3204_HSDET_NONE (0 << 5) +/* Headset Type: Stereo Headset */ +#define AIC3204_HSDET_STEREO (1 << 5) +/* Headset Type: Cellular Stereo Headset */ +#define AIC3204_HSDET_CELLSTEREO (3 << 5) +/* Headset Detection Debounce Time: 16ms */ +#define AIC3204_HSDET_PLUGDT_16 (0 << 2) +/* Headset Detection Debounce Time: 32ms */ +#define AIC3204_HSDET_PLUGDT_32 (1 << 2) +/* Headset Detection Debounce Time: 64ms */ +#define AIC3204_HSDET_PLUGDT_64 (2 << 2) +/* Headset Detection Debounce Time: 128ms */ +#define AIC3204_HSDET_PLUGDT_128 (3 << 2) +/* Headset Detection Debounce Time: 256ms */ +#define AIC3204_HSDET_PLUGDT_256 (4 << 2) +/* Headset Detection Debounce Time: 512ms */ +#define AIC3204_HSDET_PLUGDT_512 (5 << 2) +/* Headset Detection Debounce Time Mask */ +#define AIC3204_HSDET_PLUGDT (7 << 2) +/* Headset Button Debounce Time: 8ms */ +#define AIC3204_HSDET_BTNDT_8 (0 << 0) +/* Headset Button Debounce Time: 16ms */ +#define AIC3204_HSDET_BTNDT_16 (1 << 0) +/* Headset Button Debounce Time: 32ms */ +#define AIC3204_HSDET_BTNDT_32 (2 << 0) +/* Headset Button Debounce Time Mask */ +#define AIC3204_HSDET_BTNDT (3 << 0) + +/* DRC Control Register 1 */ +#define AIC3204_DRC1 AIC3204_PGREG(0, 68) +/* Left Channel DRC Enable */ +#define AIC3204_DRC1_LEFT_EN (1 << 6) +/* Right Channel DRC Enable */ +#define AIC3204_DRC1_RIGHT_EN (1 << 5) +/* DRC Threshold: -3dBFS */ +#define AIC3204_DRC1_THOLD_3DBFS (0 << 2) +/* DRC Threshold: -6dBFS */ +#define AIC3204_DRC1_THOLD_6DBFS (1 << 2) +/* DRC Threshold: -9dBFS */ +#define AIC3204_DRC1_THOLD_9DBFS (2 << 2) +/* DRC Threshold: -12dBFS */ +#define AIC3204_DRC1_THOLD_12DBFS (3 << 2) +/* DRC Threshold: -15dBFS */ +#define AIC3204_DRC1_THOLD_15DBFS (4 << 2) +/* DRC Threshold: -18dBFS */ +#define AIC3204_DRC1_THOLD_18DBFS (5 << 2) +/* DRC Threshold: -21dBFS */ +#define AIC3204_DRC1_THOLD_21DBFS (6 << 2) +/* DRC Threshold: -24dBFS */ +#define AIC3204_DRC1_THOLD_24DBFS (7 << 2) +/* DRC Threshold Mask */ +#define AIC3204_DRC1_THOLD (7 << 2) +/* DRC Hysteresis: 0dB */ +#define AIC3204_DRC1_HYST_0DB (0 << 0) +/* DRC Hysteresis: 1dB */ +#define AIC3204_DRC1_HYST_1DB (1 << 0) +/* DRC Hysteresis: 2dB */ +#define AIC3204_DRC1_HYST_2DB (2 << 0) +/* DRC Hysteresis: 3dB */ +#define AIC3204_DRC1_HYST_3DB (3 << 0) +/* DRC Hysteresis Mask */ +#define AIC3204_DRC1_HYST (3 << 0) + +/* DRC Control Register 2 */ +#define AIC3204_DRC2 AIC3204_PGREG(0, 69) +/* DRC Hold: Disabled */ +#define AIC3204_DRC2_HOLD_DISABLED (0 << 3) +/* DRC Hold: 32 Word Clocks */ +#define AIC3204_DRC2_HOLD_32WC (1 << 3) +/* DRC Hold: 64 Word Clocks */ +#define AIC3204_DRC2_HOLD_64WC (2 << 3) +/* DRC Hold: 128 Word Clocks */ +#define AIC3204_DRC2_HOLD_128WC (3 << 3) +/* DRC Hold: 256 Word Clocks */ +#define AIC3204_DRC2_HOLD_256WC (4 << 3) +/* DRC Hold: 512 Word Clocks */ +#define AIC3204_DRC2_HOLD_512WC (5 << 3) +/* DRC Hold: 1024 Word Clocks */ +#define AIC3204_DRC2_HOLD_1024WC (6 << 3) +/* DRC Hold: 2048 Word Clocks */ +#define AIC3204_DRC2_HOLD_2048WC (7 << 3) +/* DRC Hold: 4096 Word Clocks */ +#define AIC3204_DRC2_HOLD_4096WC (8 << 3) +/* DRC Hold: 8192 Word Clocks */ +#define AIC3204_DRC2_HOLD_8192WC (9 << 3) +/* DRC Hold: 16384 Word Clocks */ +#define AIC3204_DRC2_HOLD_16384WC (10 << 3) +/* DRC Hold: 32768 Word Clocks */ +#define AIC3204_DRC2_HOLD_32768WC (11 << 3) +/* DRC Hold: 65536 Word Clocks */ +#define AIC3204_DRC2_HOLD_65536WC (12 << 3) +/* DRC Hold: 98304 Word Clocks */ +#define AIC3204_DRC2_HOLD_98304WC (13 << 3) +/* DRC Hold: 131072 Word Clocks */ +#define AIC3204_DRC2_HOLD_131072WC (14 << 3) +/* DRC Hold: 163840 Word Clocks */ +#define AIC3204_DRC2_HOLD_163840WC (15 << 3) +/* DRC Hold Mask */ +#define AIC3204_DRC2_HOLD (15 << 3) + +/* DRC Control Register 3 */ +#define AIC3204_DRC3 AIC3204_PGREG(0, 70) +/* DRC Attack Rate Shift */ +#define AIC3204_DRC3_ATTACK_SHIFT 4 +/* DRC Attack Rate Mask */ +#define AIC3204_DRC3_ATTACK (15 << AIC3204_DRC3_ATTACK_SHIFT) +/* DRC Decay Rate Shift */ +#define AIC3204_DRC3_DECAY_SHIFT 0 +/* DRC Decay Rate Mask */ +#define AIC3204_DRC3_DECAY (15 << AIC3204_DRC3_DECAY_SHIFT) + +/* Beep Generator Register 1 */ +#define AIC3204_BEEP1 AIC3204_PGREG(0, 71) +/* Enable Beep Generator */ +#define AIC3204_BEEP1_EN (1 << 7) +/* Left Channel Beep Volume Shift */ +#define AIC3204_BEEP1_VOL_SHIFT 0 +/* Left Channel Beep Volume Mask */ +#define AIC3204_BEEP1_VOL (0x3f) + +/* Beep Generator Register 2 */ +#define AIC3204_BEEP2 AIC3204_PGREG(0, 72) +/* Beep Generator Master Volume: Independant Left/Right Channels */ +#define AIC3204_BEEP2_MVOL_IND (0 << 6) +/* Beep Generator Master Volume: Left Channel controls Right */ +#define AIC3204_BEEP2_MVOL_LEFT (1 << 6) +/* Beep Generator Master Volume: Right Channel controls Left */ +#define AIC3204_BEEP2_MVOL_RIGHT (2 << 6) +/* Beep Generator Master Volume Mask */ +#define AIC3204_BEEP2_MVOL (3 << 6) + +/* Beep Generator Register 3 */ +#define AIC3204_BEEP3 AIC3204_PGREG(0, 73) +/* Sample Length Value Shift */ +#define AIC3204_BEEP3_LENGTH_VSHIFT 16 +/* Sample Length Shift */ +#define AIC3204_BEEP3_LENGTH_SHIFT 0 +/* Sample Length Mask */ +#define AIC3204_BEEP3_LENGTH (0xff) + +/* Beep Generator Register 4 */ +#define AIC3204_BEEP4 AIC3204_PGREG(0, 74) +/* Sample Length Value Shift */ +#define AIC3204_BEEP4_LENGTH_VSHIFT 8 +/* Sample Length Shift */ +#define AIC3204_BEEP4_LENGTH_SHIFT 0 +/* Sample Length Mask */ +#define AIC3204_BEEP4_LENGTH (0xff) + +/* Beep Generator Register 5 */ +#define AIC3204_BEEP5 AIC3204_PGREG(0, 75) +/* Sample Length Value Shift */ +#define AIC3204_BEEP5_LENGTH_VSHIFT 0 +/* Sample Length Shift */ +#define AIC3204_BEEP5_LENGTH_SHIFT 0 +/* Sample Length Mask */ +#define AIC3204_BEEP5_LENGTH (0xff) + +/* Beep Generator Register 6 */ +#define AIC3204_BEEP6 AIC3204_PGREG(0, 76) +/* Relative Sine Frequency Value Shift */ +#define AIC3204_BEEP6_SINFREQ_VSHIFT 8 +/* Relative Sine Frequency Shift */ +#define AIC3204_BEEP6_SINFREQ_SHIFT 0 +/* Relative Sine Frequency Mask */ +#define AIC3204_BEEP6_SINFREQ (0xff) + +/* Beep Generator Register 7 */ +#define AIC3204_BEEP7 AIC3204_PGREG(0, 77) +/* Relative Sine Frequency Value Shift */ +#define AIC3204_BEEP7_SINFREQ_VSHIFT 0 +/* Relative Sine Frequency Shift */ +#define AIC3204_BEEP7_SINFREQ_SHIFT 0 +/* Relative Sine Frequency Mask */ +#define AIC3204_BEEP7_SINFREQ (0xff) + +/* Beep Generator Register 8 */ +#define AIC3204_BEEP8 AIC3204_PGREG(0, 78) +/* Relative Cosine Frequency Value Shift */ +#define AIC3204_BEEP8_COSFREQ_VSHIFT 8 +/* Relative Cosine Frequency Shift */ +#define AIC3204_BEEP8_COSFREQ_SHIFT 0 +/* Relative Cosine Frequency Mask */ +#define AIC3204_BEEP8_COSFREQ (0xff) + +/* Beep Generator Register 9 */ +#define AIC3204_BEEP9 AIC3204_PGREG(0, 79) +/* Relative Cosine Frequency Value Shift */ +#define AIC3204_BEEP9_COSFREQ_VSHIFT 0 +/* Relative Cosine Frequency Shift */ +#define AIC3204_BEEP9_COSFREQ_SHIFT 0 +/* Relative Cosine Frequency Mask */ +#define AIC3204_BEEP9_COSFREQ (0xff) + +/* ADC Channel Setup Register */ +#define AIC3204_ADCS AIC3204_PGREG(0, 81) +/* Left Channel ADC Powered Up */ +#define AIC3204_ADCS_LADC_UP_SHIFT (7) +/* Right Channel ADC Powered Up */ +#define AIC3204_ADCS_RADC_UP_SHIFT (6) +/* Digital Microphone Input: GPIO */ +#define AIC3204_ADC5_DMICIN_GPIO (0 << 4) +/* Digital Microphone Input: SCLK */ +#define AIC3204_ADC5_DMICIN_SCLK (1 << 4) +/* Digital Microphone Input: DIN */ +#define AIC3204_ADC5_DMICIN_DIN (2 << 4) +/* Digital Microphone Input Mask */ +#define AIC3204_ADC5_DMICIN (3 << 4) +/* Left ADC Source: Digital Microphone */ +#define AIC3204_ADC5_LADC_DMIC (1 << 3) +/* Right ADC Source: Digital Microphone */ +#define AIC3204_ADC5_RADC_DMIC (1 << 2) +/* ADC Volume Soft Step: 1 step / word clock */ +#define AIC3204_ADC5_VOLSS_1SPWC (0 << 0) +/* ADC Volume Soft Step: 1 step / 2 word clocks */ +#define AIC3204_ADC5_VOLSS_1SP2WC (1 << 0) +/* ADC Volume Soft Step: Disabled */ +#define AIC3204_ADC5_VOLSS_DISABLED (2 << 0) +/* ADC Volume Soft Step Mask */ +#define AIC3204_ADC5_VOLSS (3 << 0) + +/* ADC Fine Gain Adjust Register */ +#define AIC3204_ADCFINE AIC3204_PGREG(0, 82) +/* Left ADC Mute */ +#define AIC3204_ADCFINE_LEFT_MUTE (1 << 7) +/* Left ADC Gain: 0dB */ +#define AIC3204_ADCFINE_LEFT_0DB (0 << 4) +/* Left ADC Gain: -0.1dB */ +#define AIC3204_ADCFINE_LEFT_0DB1 (1 << 4) +/* Left ADC Gain: -0.2dB */ +#define AIC3204_ADCFINE_LEFT_0DB2 (2 << 4) +/* Left ADC Gain: -0.3dB */ +#define AIC3204_ADCFINE_LEFT_0DB3 (2 << 4) +/* Left ADC Gain: -0.4dB */ +#define AIC3204_ADCFINE_LEFT_0DB4 (3 << 4) +/* Left ADC Gain Mask */ +#define AIC3204_ADCFINE_LEFT (7 << 4) +/* Right ADC Mute */ +#define AIC3204_ADCFINE_RIGHT_MUTE (1 << 3) +/* Right ADC Gain: 0dB */ +#define AIC3204_ADCFINE_RIGHT_0DB (0 << 0) +/* Right ADC Gain: -0.1dB */ +#define AIC3204_ADCFINE_RIGHT_0DB1 (1 << 0) +/* Right ADC Gain: -0.2dB */ +#define AIC3204_ADCFINE_RIGHT_0DB2 (2 << 0) +/* Right ADC Gain: -0.3dB */ +#define AIC3204_ADCFINE_RIGHT_0DB3 (2 << 0) +/* Right ADC Gain: -0.4dB */ +#define AIC3204_ADCFINE_RIGHT_0DB4 (3 << 0) +/* Right ADC Gain Mask */ +#define AIC3204_ADCFINE_RIGHT (7 << 0) + +/* Left ADC Channel Volume Register */ +#define AIC3204_LADCVOL AIC3204_PGREG(0, 83) +/* Left ADC Channel Volume Mask */ +#define AIC3204_LADCVOL_MASK 0x7f + +/* Right ADC Channel Volume Register */ +#define AIC3204_RADCVOL AIC3204_PGREG(0, 84) +/* Right ADC Channel Volume Mask */ +#define AIC3204_RADCVOL_MASK 0x7f + +/* ADC Phase Adjust Register */ +#define AIC3204_ADCPHASE AIC3204_PGREG(0, 85) + +/* Left Channel AGC Control Register 1 */ +#define AIC3204_LAGC1 AIC3204_PGREG(0, 86) +/* Left Channel AGC Enabled */ +#define AIC3204_LAGC1_ENABLE (1 << 7) +/* Left Channel Target Level: -5.5dBFS */ +#define AIC3204_LAGC1_LEVEL_5DBFS5 (0 << 4) +/* Left Channel Target Level: -8.0dBFS */ +#define AIC3204_LAGC1_LEVEL_8DBFS (1 << 4) +/* Left Channel Target Level: -10dBFS */ +#define AIC3204_LAGC1_LEVEL_10DBFS (2 << 4) +/* Left Channel Target Level: -12dBFS */ +#define AIC3204_LAGC1_LEVEL_12DBFS (3 << 4) +/* Left Channel Target Level: -14dBFS */ +#define AIC3204_LAGC1_LEVEL_14DBFS (4 << 4) +/* Left Channel Target Level: -17dBFS */ +#define AIC3204_LAGC1_LEVEL_17DBFS (5 << 4) +/* Left Channel Target Level: -20dBFS */ +#define AIC3204_LAGC1_LEVEL_20DBFS (6 << 4) +/* Left Channel Target Level: -24dBFS */ +#define AIC3204_LAGC1_LEVEL_24DBFS (7 << 4) +/* Left Channel Target Level Mask */ +#define AIC3204_LAGC1_LEVEL (7 << 4) +/* Left Channel Gain Hysteresis: Disabled */ +#define AIC3204_LAGC1_GAINHYST_DISABLED (0 << 0) +/* Left Channel Gain Hysteresis: 0.5dB */ +#define AIC3204_LAGC1_GAINHYST_0DB5 (1 << 0) +/* Left Channel Gain Hysteresis: 1dB */ +#define AIC3204_LAGC1_GAINHYST_1DB (2 << 0) +/* Left Channel Gain Hysteresis: 1.5dB */ +#define AIC3204_LAGC1_GAINHYST_1DB5 (3 << 0) +/* Left Channel Gain Hysteresis Mask */ +#define AIC3204_LAGC1_GAINHYST (3 << 0) + +/* Left Channel AGC Control Register 2 */ +#define AIC3204_LAGC2 AIC3204_PGREG(0, 87) +/* Left Channel AGC Hysteresis: 1dB */ +#define AIC3204_LAGC2_HYST_1DB (0 << 6) +/* Left Channel AGC Hysteresis: 2dB */ +#define AIC3204_LAGC2_HYST_2DB (1 << 6) +/* Left Channel AGC Hysteresis: 4dB */ +#define AIC3204_LAGC2_HYST_4DB (2 << 6) +/* Left Channel AGC Hysteresis: Disabled */ +#define AIC3204_LAGC2_HYST_DISABLED (3 << 6) +/* Left Channel AGC Hysteresis Mask */ +#define AIC3204_LAGC2_HYST (3 << 6) +/* Left Channel AGC Noise Gate Threshold Mask */ +#define AIC3204_LAGC2_NGATE (0x1f) +/* Left Channel AGC Noise Gate Threshold Shift */ +#define AIC3204_LAGC2_NGATE_SHIFT 1 + +/* TODO: Remaining AGC registers, DC measurement registers */ + +/* Power Configuration Register */ +#define AIC3204_POWER AIC3204_PGREG(1, 1) +/* Disable AVDD -> DVDD Link */ +#define AIC3204_POWER_AVDD_DVDD_UNLINK (1 << 3) + +/* LDO Control Register */ +#define AIC3204_LDO AIC3204_PGREG(1, 2) +/* DVDD LDO: 1.72V */ +#define AIC3204_LDO_DVDD_1V72 (0 << 6) +/* DVDD LDO: 1.67V */ +#define AIC3204_LDO_DVDD_1V67 (1 << 6) +/* DVDD LDO: 1.77V */ +#define AIC3204_LDO_DVDD_1V77 (2 << 6) +/* DVDD LDO Mask */ +#define AIC3204_LDO_DVDD (3 << 6) +/* AVDD LDO: 1.72V */ +#define AIC3204_LDO_AVDD_1V72 (0 << 4) +/* AVDD LDO: 1.67V */ +#define AIC3204_LDO_AVDD_1V67 (1 << 4) +/* AVDD LDO: 1.77V */ +#define AIC3204_LDO_AVDD_1V77 (2 << 4) +/* AVDD LDO Mask */ +#define AIC3204_LDO_AVDD (3 << 4) +/* Analog Blocks Enabled */ +#define AIC3204_LDO_ANALOG_ENABLED (0 << 3) +/* Analog Blocks Disabled */ +#define AIC3204_LDO_ANALOG_DISABLED (1 << 3) +/* Analog Block Status */ +#define AIC3204_LDO_ANALOG (1 << 3) +/* DVDD Over Current Detect */ +#define AIC3204_LDO_DVDD_OVERCURRENT (1 << 2) +/* AVDD Over Current Detect */ +#define AIC3204_LDO_AVDD_OVERCURRENT (1 << 1) +/* AVDD Powered Up */ +#define AIC3204_LDO_AVDD_UP (1 << 0) + +/* TODO: Playback Configuration Registers */ + +/* Output Driver Power Control Register */ +#define AIC3204_OUTDRV AIC3204_PGREG(1, 9) +/* Left Headphone Driver Up */ +#define AIC3204_OUTDRV_HPL_UP_SHIFT (5) +/* Right Headphone Driver Up */ +#define AIC3204_OUTDRV_HPR_UP_SHIFT (4) +/* Left Line Output Driver Up */ +#define AIC3204_OUTDRV_LOL_UP_SHIFT (3) +/* Right Line Output Driver Up */ +#define AIC3204_OUTDRV_LOR_UP_SHIFT (2) +/* Left Mixer Amplifier Up */ +#define AIC3204_OUTDRV_MAL_UP_SHIFT (1) +/* Right Mixer Amplifier Up */ +#define AIC3204_OUTDRV_MAR_UP_SHIFT (0) + +/* Common Mode Control Register */ +#define AIC3204_CMCTL AIC3204_PGREG(1, 10) +/* Full Chip Common Mode = 0.9V */ +#define AIC3204_CMCTL_FCCM_0V9 (0 << 6) +/* Full Chip Common Mode = 0.75V */ +#define AIC3204_CMCTL_FCCM_0V75 (1 << 6) +/* Full Chip Common Mode Mask */ +#define AIC3204_CMCTL_FCCM (1 << 6) +/* Headphone Output Common Mode = Full Chip Common Mode */ +#define AIC3204_CMCTL_HPCM_FCCM (0 << 4) +/* Headphone Output Common Mode = 1.25V */ +#define AIC3204_CMCTL_HPCM_1V25 (1 << 4) +/* Headphone Output Common Mode = 1.5V */ +#define AIC3204_CMCTL_HPCM_1V5 (2 << 4) +/* Headphone Output Common Mode = 1.65V */ +#define AIC3204_CMCTL_HPCM_1V65 (3 << 4) +/* Headphone Output Common Mode Mask */ +#define AIC3204_CMCTL_HPCM (3 << 4) +/* Line Output Common Mode = Full Chip Common Mode */ +#define AIC3204_CMCTL_LOCM_FCCM (0 << 3) +/* Line Output Common Mode = 1.65V from LDOin */ +#define AIC3204_CMCTL_LOCM_1V65LDOIN (1 << 3) +/* Line Output Common Mode Mask */ +#define AIC3204_CMCTL_LOCM (1 << 3) +/* Headphone Output Common Mode Source = AVDD */ +#define AIC3204_CMCTL_HPCMSRC_AVDD (0 << 1) +/* Headphone Output Common Mode Source = LDOin */ +#define AIC3204_CMCTL_HPCMSRC_LDOIN (1 << 1) +/* Headphone Output Common Mode Source Mask */ +#define AIC3204_CMCTL_HPCMSRC (1 << 1) +/* LDO Input Range = 1.5~1.95V */ +#define AIC3204_CMCTL_LDORANGE_1V5_1V95 (0 << 0) +/* LDO Input Range = 1.8~3.6V */ +#define AIC3204_CMCTL_LDORANGE_1V8_3V6 (1 << 0) +/* LDO Input Range Mask (effective when HPCMSRC = LDOIN) */ +#define AIC3204_CMCTL_LDORANGE (1 << 0) + +/* Over Current Protection Configuration Register TODO */ +#define AIC3204_OCP AIC3204_PGREG(1, 11) + +/* Left Headphone Driver Routing Register */ +#define AIC3204_HPLROUTE AIC3204_PGREG(1, 12) +/* Left Headphone Driver connects to LDAC+ */ +#define AIC3204_HPLROUTE_LDACP_SHIFT (3) +/* Left Headphone Driver connects to IN1L */ +#define AIC3204_HPLROUTE_IN1L_SHIFT (2) +/* Left Headphone Driver connects to MAL */ +#define AIC3204_HPLROUTE_MAL_SHIFT (1) +/* Left Headphone Driver connects to MAR */ +#define AIC3204_HPLROUTE_MAR_SHIFT (0) + +/* Right Headphone Driver Routing Register */ +#define AIC3204_HPRROUTE AIC3204_PGREG(1, 13) +/* Right Headphone Driver connects to LDAC- */ +#define AIC3204_HPRROUTE_LDACN_SHIFT (4) +/* Right Headphone Driver connects to RDAC+ */ +#define AIC3204_HPRROUTE_RDACP_SHIFT (3) +/* Right Headphone Driver connects to IN1L */ +#define AIC3204_HPRROUTE_IN1R_SHIFT (2) +/* Right Headphone Driver connects to MAL */ +#define AIC3204_HPRROUTE_MAR_SHIFT (1) +/* Right Headphone Driver connects to HPL */ +#define AIC3204_HPRROUTE_HPL_SHIFT (0) + +/* Left Line Output Routing Register */ +#define AIC3204_LOLROUTE AIC3204_PGREG(1, 14) +/* Left Line Output Driver connects to RDAC- */ +#define AIC3204_LOLROUTE_RDACN_SHIFT (4) +/* Left Line Output Driver connects to LDAC+ */ +#define AIC3204_LOLROUTE_LDACP_SHIFT (3) +/* Left Line Output Driver connects to MAL */ +#define AIC3204_LOLROUTE_MAL_SHIFT (1) +/* Left Line Output Driver connects to LOR */ +#define AIC3204_LOLROUTE_LOR_SHIFT (0) + +/* Right Line Output Routing Register */ +#define AIC3204_LORROUTE AIC3204_PGREG(1, 15) +/* Right Line Output Driver connects to RDAC+ */ +#define AIC3204_LORROUTE_RDACP_SHIFT (3) +/* Right Line Output Driver connects to MAR */ +#define AIC3204_LORROUTE_MAR_SHIFT (1) + +/* Left Headphone Gain Setting Register */ +#define AIC3204_HPLGAIN AIC3204_PGREG(1, 16) +/* Left Headphone Mute */ +#define AIC3204_HPLGAIN_MUTE_SHIFT (6) +/* Left Headphone Gain Mask */ +#define AIC3204_HPLGAIN_MASK (0x3f) + +/* Right Headphone Gain Setting Register */ +#define AIC3204_HPRGAIN AIC3204_PGREG(1, 17) +/* Right Headphone Mute */ +#define AIC3204_HPRGAIN_MUTE_SHIFT (6) +/* Right Headphone Gain Mask */ +#define AIC3204_HPRGAIN_MASK (0x3f) + +/* Left Line Output Gain Setting Register */ +#define AIC3204_LOLGAIN AIC3204_PGREG(1, 18) +/* Left Line Output Mute */ +#define AIC3204_LOLGAIN_MUTE_SHIFT (6) +/* Left Line Output Gain Mask */ +#define AIC3204_LOLGAIN_MASK (0x3f) + +/* Right Line Output Gain Setting Register */ +#define AIC3204_LORGAIN AIC3204_PGREG(1, 19) +/* Right Line Output Mute */ +#define AIC3204_LORGAIN_MUTE_SHIFT (6) +/* Right Line Output Gain Mask */ +#define AIC3204_LORGAIN_MASK (0x3f) + +/* Left Mixer Amplifier Gain Setting Register */ +#define AIC3204_MALGAIN AIC3204_PGREG(1, 24) +/* Left Mixer Amplifier Gain Mask */ +#define AIC3204_MALGAIN_MASK (0x3f) + +/* Right Mixer Amplifier Gain Setting Register */ +#define AIC3204_MARGAIN AIC3204_PGREG(1, 25) +/* Right Mixer Amplifier Gain Mask */ +#define AIC3204_MARGAIN_MASK (0x3f) + +#define AIC3204_MICBIAS AIC3204_PGREG(1, 51) + +#define AIC3204_LMICPGAPROUTE AIC3204_PGREG(1, 52) +#define AIC3204_LMICPGANROUTE AIC3204_PGREG(1, 54) + +#define AIC3204_RMICPGAPROUTE AIC3204_PGREG(1, 55) +#define AIC3204_RMICPGANROUTE AIC3204_PGREG(1, 57) + +#define AIC3204_LMICPGAVOL AIC3204_PGREG(1, 59) +#define AIC3204_RMICPGAVOL AIC3204_PGREG(1, 60) + +/* ADC Power Tune Mode Register */ +#define AIC3204_ADCPTM AIC3204_PGREG(1, 61) +/* ADC Power Tune Mode: PTM_R4 */ +#define AIC3204_ADCPTM_R4 (0x00) +/* ADC Power Tune Mode: PTM_R3 */ +#define AIC3204_ADCPTM_R3 (0x64) +/* ADC Power Tune Mode: PTM_R2 */ +#define AIC3204_ADCPTM_R2 (0xb6) +/* ADC Power Tune Mode: PTM_R1 */ +#define AIC3204_ADCPTM_R1 (0xff) + +/* Analogue Input Quick Charging Configuration Register */ +#define AIC3204_AIQC AIC3204_PGREG(1, 71) +/* Power up time: Default Value (whatever that is) */ +#define AIC3204_AIQC_PWRUP_DEFAULT (0x00) +/* Power up time: 3.1ms */ +#define AIC3204_AIQC_PWRUP_3M1S (0x31) +/* Power up time: 6.4ms */ +#define AIC3204_AIQC_PWRUP_6M4S (0x32) +/* Power up time: 1.6ms */ +#define AIC3204_AIQC_PWRUP_1M6S (0x33) +/* Power up time mask */ +#define AIC3204_AIQC_PWRUP (0x3f) + +/* Reference Power-Up Configuration Register */ +#define AIC3204_REFPU AIC3204_PGREG(1, 123) +/* Reference Power-Up delay: Slow */ +#define AIC3204_REFPU_DELAY_SLOW (0 << 0) +/* Reference Power-Up delay: 40ms */ +#define AIC3204_REFPU_DELAY_40MS (1 << 0) +/* Reference Power-Up delay: 80ms */ +#define AIC3204_REFPU_DELAY_80MS (2 << 0) +/* Reference Power-Up delay: 120ms */ +#define AIC3204_REFPU_DELAY_120MS (3 << 0) +/* Force power-up */ +#define AIC3204_REFPU_FORCE (1 << 2) + +/* TODO: Define the remaining registers ... this will do for now */ + +extern struct snd_soc_dai aic3204_dai; +extern struct snd_soc_codec_device soc_codec_dev_aic3204; + +#endif /* _AIC3204_H */ -- 1.6.4.4

2 7

[alsa-devel] [PATCH v3] alsa: ASoC: JZ4740: Add qi_lb60 board driver
by 1276924111-11158-27-git-send-email-lars＠metafoo.de 22 Jun '10

22 Jun '10

From: Lars-Peter Clausen <lars(a)metafoo.de> This patch adds ASoC support for the qi_lb60 board. Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> Cc: Mark Brown <broonie(a)opensource.wolfsonmicro.com> Cc: Liam Girdwood <lrg(a)slimlogic.co.uk> Cc: alsa-devel(a)alsa-project.org -- Changes since v1 - Refer to AMP gpios always by their define - Do not try to set codecs format, since the set_fmt callback for the codec was dropped. Changes since v2 - The codec prefix was removed from jz4740 codec include file - This patch accidentally contained a few bits meant for ASoC JZ4740 platform support patch. Removed them. --- sound/soc/jz4740/Kconfig | 9 +++ sound/soc/jz4740/Makefile | 4 + sound/soc/jz4740/qi_lb60.c | 166 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 179 insertions(+), 0 deletions(-) create mode 100644 sound/soc/jz4740/qi_lb60.c diff --git a/sound/soc/jz4740/Kconfig b/sound/soc/jz4740/Kconfig index 27480f2..5351cba 100644 --- a/sound/soc/jz4740/Kconfig +++ b/sound/soc/jz4740/Kconfig @@ -12,3 +12,12 @@ config SND_JZ4740_SOC_I2S help Say Y if you want to use I2S protocol and I2S codec on Ingenic JZ4740 based boards. + +config SND_JZ4740_SOC_QI_LB60 + tristate "SoC Audio support for Qi LB60" + depends on SND_JZ4740_SOC && JZ4740_QI_LB60 + select SND_JZ4740_SOC_I2S + select SND_SOC_JZ4740_CODEC + help + Say Y if you want to add support for ASoC audio on the Qi LB60 board + a.k.a Qi Ben NanoNote. diff --git a/sound/soc/jz4740/Makefile b/sound/soc/jz4740/Makefile index 1be8d19..be873c1 100644 --- a/sound/soc/jz4740/Makefile +++ b/sound/soc/jz4740/Makefile @@ -7,3 +7,7 @@ snd-soc-jz4740-i2s-objs := jz4740-i2s.o obj-$(CONFIG_SND_JZ4740_SOC) += snd-soc-jz4740.o obj-$(CONFIG_SND_JZ4740_SOC_I2S) += snd-soc-jz4740-i2s.o +# Jz4740 Machine Support +snd-soc-qi-lb60-objs := qi_lb60.o + +obj-$(CONFIG_SND_JZ4740_SOC_QI_LB60) += snd-soc-qi-lb60.o diff --git a/sound/soc/jz4740/qi_lb60.c b/sound/soc/jz4740/qi_lb60.c new file mode 100644 index 0000000..f15f491 --- /dev/null +++ b/sound/soc/jz4740/qi_lb60.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2009, Lars-Peter Clausen <lars(a)metafoo.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/timer.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <linux/gpio.h> + +#include "../codecs/jz4740.h" +#include "jz4740-pcm.h" +#include "jz4740-i2s.h" + + +#define QI_LB60_SND_GPIO JZ_GPIO_PORTB(29) +#define QI_LB60_AMP_GPIO JZ_GPIO_PORTD(4) + +static int qi_lb60_spk_event(struct snd_soc_dapm_widget *widget, + struct snd_kcontrol *ctrl, int event) +{ + int on = 0; + if (event & SND_SOC_DAPM_POST_PMU) + on = 1; + else if (event & SND_SOC_DAPM_PRE_PMD) + on = 0; + + gpio_set_value(QI_LB60_SND_GPIO, on); + gpio_set_value(QI_LB60_AMP_GPIO, on); + + return 0; +} + +static const struct snd_soc_dapm_widget qi_lb60_widgets[] = { + SND_SOC_DAPM_SPK("Speaker", qi_lb60_spk_event), + SND_SOC_DAPM_MIC("Mic", NULL), +}; + +static const struct snd_soc_dapm_route qi_lb60_routes[] = { + {"Mic", NULL, "MIC"}, + {"Speaker", NULL, "LOUT"}, + {"Speaker", NULL, "ROUT"}, +}; + +#define QI_LB60_DAIFMT (SND_SOC_DAIFMT_I2S | \ + SND_SOC_DAIFMT_NB_NF | \ + SND_SOC_DAIFMT_CBM_CFM) + +static int qi_lb60_codec_init(struct snd_soc_codec *codec) +{ + int ret; + struct snd_soc_dai *cpu_dai = codec->socdev->card->dai_link->cpu_dai; + + snd_soc_dapm_nc_pin(codec, "LIN"); + snd_soc_dapm_nc_pin(codec, "RIN"); + + ret = snd_soc_dai_set_fmt(cpu_dai, QI_LB60_DAIFMT); + if (ret < 0) { + dev_err(codec->dev, "Failed to set cpu dai format: %d\n", ret); + return ret; + } + + snd_soc_dapm_new_controls(codec, qi_lb60_widgets, ARRAY_SIZE(qi_lb60_widgets)); + snd_soc_dapm_add_routes(codec, qi_lb60_routes, ARRAY_SIZE(qi_lb60_routes)); + snd_soc_dapm_sync(codec); + + return 0; +} + +static struct snd_soc_dai_link qi_lb60_dai = { + .name = "jz4740", + .stream_name = "jz4740", + .cpu_dai = &jz4740_i2s_dai, + .codec_dai = &jz4740_codec_dai, + .init = qi_lb60_codec_init, +}; + +static struct snd_soc_card qi_lb60 = { + .name = "QI LB60", + .dai_link = &qi_lb60_dai, + .num_links = 1, + .platform = &jz4740_soc_platform, +}; + +static struct snd_soc_device qi_lb60_snd_devdata = { + .card = &qi_lb60, + .codec_dev = &soc_codec_dev_jz4740_codec, +}; + +static struct platform_device *qi_lb60_snd_device; + +static int __init qi_lb60_init(void) +{ + int ret; + + qi_lb60_snd_device = platform_device_alloc("soc-audio", -1); + + if (!qi_lb60_snd_device) + return -ENOMEM; + + ret = gpio_request(QI_LB60_SND_GPIO, "SND"); + if (ret) { + pr_err("qi_lb60 snd: Failed to request SND GPIO(%d): %d\n", + QI_LB60_SND_GPIO, ret); + goto err_device_put; + } + + ret = gpio_request(QI_LB60_AMP_GPIO, "AMP"); + if (ret) { + pr_err("qi_lb60 snd: Failed to request AMP GPIO(%d): %d\n", + QI_LB60_AMP_GPIO, ret); + goto err_gpio_free_snd; + } + + gpio_direction_output(QI_LB60_SND_GPIO, 0); + gpio_direction_output(QI_LB60_AMP_GPIO, 0); + + platform_set_drvdata(qi_lb60_snd_device, &qi_lb60_snd_devdata); + qi_lb60_snd_devdata.dev = &qi_lb60_snd_device->dev; + + ret = platform_device_add(qi_lb60_snd_device); + if (ret) { + pr_err("qi_lb60 snd: Failed to add snd soc device: %d\n", ret); + goto err_unset_pdata; + } + + return 0; + +err_unset_pdata: + platform_set_drvdata(qi_lb60_snd_device, NULL); +/*err_gpio_free_amp:*/ + gpio_free(QI_LB60_AMP_GPIO); +err_gpio_free_snd: + gpio_free(QI_LB60_SND_GPIO); +err_device_put: + platform_device_put(qi_lb60_snd_device); + + return ret; +} +module_init(qi_lb60_init); + +static void __exit qi_lb60_exit(void) +{ + gpio_free(QI_LB60_AMP_GPIO); + gpio_free(QI_LB60_SND_GPIO); + platform_device_unregister(qi_lb60_snd_device); +} +module_exit(qi_lb60_exit); + +MODULE_AUTHOR("Lars-Peter Clausen <lars(a)metafoo.de>"); +MODULE_DESCRIPTION("ALSA SoC QI LB60 Audio support"); +MODULE_LICENSE("GPL v2"); -- 1.5.6.5

2 1

[alsa-devel] [PATCH] ALSA: hda - Add Macbook 5,2 quirk
by Luke Yelavich 22 Jun '10

22 Jun '10

From: Luke Yelavich <luke.yelavich(a)canonical.com> BugLink: https://bugs.launchpad.net/bugs/463178 Set Macbook 5,2 (106b:4a00) hardware to use ALC885_MB5 Cc: <stable(a)kernel.org> Signed-off-by: Luke Yelavich <luke.yelavich(a)canonical.com> --- sound/pci/hda/patch_realtek.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index f1ce7d7..b145306 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9486,6 +9486,7 @@ static struct snd_pci_quirk alc882_ssid_cfg_tbl[] = { SND_PCI_QUIRK(0x106b, 0x3e00, "iMac 24 Aluminum", ALC885_IMAC24), SND_PCI_QUIRK(0x106b, 0x4900, "iMac 9,1 Aluminum", ALC885_IMAC91), SND_PCI_QUIRK(0x106b, 0x3f00, "Macbook 5,1", ALC885_MB5), + SND_PCI_QUIRK(0x106b, 0x4a00, "Macbook 5,2", ALC885_MB5), /* FIXME: HP jack sense seems not working for MBP 5,1 or 5,2, * so apparently no perfect solution yet */ -- 1.7.0.4

2 1

[alsa-devel] reading 1 second of audio at a time
by folkert 22 Jun '10

22 Jun '10

Hi, Am trying to achieve something trivial: reading 1 second of audio at a time, but something goes wrong: Sound 1277148008.835094 Sound 1277148008.838224 Sound 1277148010.834839 Sound 1277148010.838001 Sound 1277148012.834523 Sound 1277148012.837580 Sound 1277148014.835240 Sound 1277148014.838333 As you can see; audio is returned for 2 seconds, then it sleeps 2 secondsn, then 2 seconds of audio, etc. What I do is: if (snd_pcm_hw_params_set_access(pcm_handle, hwparams, SND_PCM_ACCESS_RW_INTERLEAVED) < 0) { } if (snd_pcm_hw_params_set_format(pcm_handle, hwparams, SND_PCM_FORMAT_S16_LE) < 0) { } exact_rate = 44100; if (snd_pcm_hw_params_set_rate_near(pcm_handle, hwparams, &exact_rate, 0) < 0) { error_exit("Error setting rate.\n"); } if (*rate != exact_rate) { fprintf(stderr, "The rate %d Hz is not supported by your hardware.\n ==> Using %d Hz instead.\n", *rate, exact_rate); *rate = exact_rate; } if (snd_pcm_hw_params_set_channels(pcm_handle, hwparams, 2) < 0) { } int periods = 2; if (snd_pcm_hw_params_set_periods(pcm_handle, hwparams, periods, 0) < 0) { } if (snd_pcm_hw_params_set_buffer_size(pcm_handle, hwparams, exact_rate * 2 * n_channels) < 0) { } if (snd_pcm_hw_params(pcm_handle, hwparams) < 0) { } return pcm_handle; } void get_audio_1s(snd_pcm_t *pcm_handle, short *buffer, int rate, int channels) { int samples = channels * rate, index = 0; while(samples > 0) { int cur = samples, pcmreturn; while ((pcmreturn = snd_pcm_readi(pcm_handle, &buffer[index], cur)) < 0) { snd_pcm_prepare(pcm_handle); printf(" underrun\n"); } index += pcmreturn; samples -= pcmreturn; } } So I call this get_audio_1s() with the samplerate (44100) and the number of channels (2). Then it seems to return the first second at once, then the second second of audio too, then sleeps for 2 seconds(!) and then repeats. Folkert van Heusden -- Ever wonder what is out there? Any alien races? Then please support the seti@home project: setiathome.ssl.berkeley.edu ---------------------------------------------------------------------- Phone: +31-6-41278122, PGP-key: 1F28D8AE, www.vanheusden.com

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[alsa-devel] Question about snd_soc_add_controls
by Kuninori Morimoto 22 Jun '10

22 Jun '10

Dear very kind guys I would like to use snd_soc_add_controls for ak4642. But I'm not good at it now, so, for 1st step, I would like to add "Playback Volume". Playback Volume length of ak4642 chip is -115.0 dB to +12.0 dB step is 0.5 dB. and It can use mute. So, I created code like this ---------------------------------------------------------------------------- static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1); /* 0.5 dB step */ static const struct snd_kcontrol_new ak4642_snd_controls[] = { SOC_DOUBLE_R_TLV("Playback Volume", L_DVC, R_DVC, 0, 256, 0, out_tlv), }; ---------------------------------------------------------------------------- But I wonder #define DECLARE_TLV_DB_SCALE(name, min, step, mute) Does this "mute" mean that it can use mute ? But how to ? #define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) What is this "xinvert" ? Can you please teach me about above ? And where is these code used ? It seems very complex for me... Best regards -- Kuninori Morimoto

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Re: [alsa-devel] snd_mixer_selem_get_playback_volume return value outside allowed range
by Raymond Yau 22 Jun '10

22 Jun '10

2010/5/25 Clemens Ladisch <clemens(a)ladisch.de> > James Courtier-Dutton wrote: > > On 25 May 2010 09:38, Clemens Ladisch <clemens(a)ladisch.de> wrote: > > > All the others seem to be mistakes: > > > > > > > soc/codecs/stac9766.c:... > > > > soc/codecs/wm8350.c:... > > > > soc/codecs/wm8400.c:... > > > > soc/codecs/wm8990.c:... > > > > Could this maybe explain why pulseaudio was having such problems with > > alsa with regards to gain controls???? > > Only if it happens on embedded hardware that uses these particular > codecs. > > > Regards, > Clemens > http://git.alsa-project.org/?p=alsa-utils.git;a=commit;h=c9b86f49a8a1a8c337… your patch did not fix the buggy driver (e.g. alsa-pulse plugin) which return volume outside the alllowed range amixer -D pulse Simple mixer control 'Master',0 Capabilities: pvolume pswitch pswitch-joined Playback channels: Front Left - Front Right Limits: Playback 0 - 65536 Mono: Front Left: Playback 98304 [150%] [on] Front Right: Playback 98304 [150%] [on] Should snd_mixer_selem_get_playback_volume() perform range check ? tatic int get_volume_ops(snd_mixer_elem_t *elem, int dir, snd_mixer_selem_channel_id_t channel, long *value) { selem_none_t *s = snd_mixer_elem_get_private(elem); if (s->selem.caps & SM_CAP_GVOLUME) dir = SM_PLAY; if ((unsigned int) channel >= s->str[dir].channels) return -EINVAL; *value = s->str[dir].vol[channel]; + if (*value > s->str[dir].max) + return -EINVAL; + if (*value < s->str[dir].min) + return -EINVAL; return 0;

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[alsa-devel] [PATCH] ASoC: pandora: fix CLKX polarity
by Grazvydas Ignotas 21 Jun '10

21 Jun '10

After mass production started it was found that several boards exhibit noise problems during sound playback. After some investigation it was determined that CLKX polarity is set incorrectly, and even if most boards can tolerate the wrong setting, there are some that don't. Fix polarity setup in the board file. As the clock settings for input and output now match, merge in and out functions and structures to simplify code. Signed-off-by: Grazvydas Ignotas <notasas(a)gmail.com> --- sound/soc/omap/omap3pandora.c | 36 ++++++++---------------------------- 1 files changed, 8 insertions(+), 28 deletions(-) diff --git a/sound/soc/omap/omap3pandora.c b/sound/soc/omap/omap3pandora.c index 87ce842..9eecac1 100644 --- a/sound/soc/omap/omap3pandora.c +++ b/sound/soc/omap/omap3pandora.c @@ -43,12 +43,14 @@ static struct regulator *omap3pandora_dac_reg; -static int omap3pandora_cmn_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, unsigned int fmt) +static int omap3pandora_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; + int fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS; int ret; /* Set codec DAI configuration */ @@ -91,24 +93,6 @@ static int omap3pandora_cmn_hw_params(struct snd_pcm_substream *substream, return 0; } -static int omap3pandora_out_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - return omap3pandora_cmn_hw_params(substream, params, - SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_IB_NF | - SND_SOC_DAIFMT_CBS_CFS); -} - -static int omap3pandora_in_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - return omap3pandora_cmn_hw_params(substream, params, - SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBS_CFS); -} - static int omap3pandora_dac_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *k, int event) { @@ -231,12 +215,8 @@ static int omap3pandora_in_init(struct snd_soc_codec *codec) return snd_soc_dapm_sync(codec); } -static struct snd_soc_ops omap3pandora_out_ops = { - .hw_params = omap3pandora_out_hw_params, -}; - -static struct snd_soc_ops omap3pandora_in_ops = { - .hw_params = omap3pandora_in_hw_params, +static struct snd_soc_ops omap3pandora_ops = { + .hw_params = omap3pandora_hw_params, }; /* Digital audio interface glue - connects codec <--> CPU */ @@ -246,14 +226,14 @@ static struct snd_soc_dai_link omap3pandora_dai[] = { .stream_name = "HiFi Out", .cpu_dai = &omap_mcbsp_dai[0], .codec_dai = &twl4030_dai[TWL4030_DAI_HIFI], - .ops = &omap3pandora_out_ops, + .ops = &omap3pandora_ops, .init = omap3pandora_out_init, }, { .name = "TWL4030", .stream_name = "Line/Mic In", .cpu_dai = &omap_mcbsp_dai[1], .codec_dai = &twl4030_dai[TWL4030_DAI_HIFI], - .ops = &omap3pandora_in_ops, + .ops = &omap3pandora_ops, .init = omap3pandora_in_init, } }; -- 1.6.3.3

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[alsa-devel] [PATCH] SOUND: usb/endpoint, fix dangling pointer use
by Jiri Slaby 21 Jun '10

21 Jun '10

Stanse found that in snd_usb_parse_audio_endpoints, there is a dangling pointer dereference. When snd_usb_parse_audio_format fails, fp is freed, and continue invoked. On the next loop, there is "fp && fp->altsetting == 1 && fp->channels == 1" test, but fp is set from the last iteration (but is bogus) and thus ilegally dereferenced. Set fp to NULL before "continue". Signed-off-by: Jiri Slaby <jslaby(a)suse.cz> Cc: Daniel Mack <daniel(a)caiaq.de> Cc: Clemens Ladisch <clemens(a)ladisch.de> Cc: Takashi Iwai <tiwai(a)suse.de> --- sound/usb/endpoint.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/sound/usb/endpoint.c b/sound/usb/endpoint.c index 9593b91..6f6596c 100644 --- a/sound/usb/endpoint.c +++ b/sound/usb/endpoint.c @@ -427,6 +427,7 @@ int snd_usb_parse_audio_endpoints(struct snd_usb_audio *chip, int iface_no) if (snd_usb_parse_audio_format(chip, fp, format, fmt, stream, alts) < 0) { kfree(fp->rate_table); kfree(fp); + fp = NULL; continue; } -- 1.7.1

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[alsa-devel] redirecting audio to another desktop machine
by Viral Mehta 21 Jun '10

21 Jun '10

Hi list, I have an embedded device running linux kernel and a minimal filesystem. I want to access this device remotely which means I should be able to connect to the device just like we do Remote Desktop over ethernet. I am able to do this. I am able to send key-event and framebuffer data whenever my desktop machine connects to the device. But, I am not able to send audio data on remote side. I am really not sure which device file (/dev/snd/ ???) I should read and capture the data and should send across.... Or can I read the playback device ? I think NO. Do I need to create some kind of virtual sound device ? Any pointers/suggestions are appreciated. Thanks, Viral This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. ______________________________________________________________________

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