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[PATCH] ASoC: rt1019: add rt1019 amplifier driver
by jack.yu＠realtek.com 10 Mar '21

10 Mar '21

From: Jack Yu <jack.yu(a)realtek.com> This is initial amplifier driver for rt1019. Signed-off-by: Jack Yu <jack.yu(a)realtek.com> --- .../devicetree/bindings/sound/rt1019.txt | 16 + sound/soc/codecs/Kconfig | 7 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt1019.c | 940 ++++++++++++++++++ sound/soc/codecs/rt1019.h | 320 ++++++ 5 files changed, 1285 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rt1019.txt create mode 100644 sound/soc/codecs/rt1019.c create mode 100644 sound/soc/codecs/rt1019.h diff --git a/Documentation/devicetree/bindings/sound/rt1019.txt b/Documentation/devicetree/bindings/sound/rt1019.txt new file mode 100644 index 000000000000..fdefd4ff1d3d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt1019.txt @@ -0,0 +1,16 @@ +RT1019 Mono Class-D Audio Amplifier + +This device supports I2C only. + +Required properties: + +- compatible : "realtek,rt1019". + +- reg : The I2C address of the device. + +Example: + +rt1019: codec@28 { + compatible = "realtek,rt1019"; + reg = <0x28>; +}; diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 6ce74c99a305..4ab34bca71aa 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -161,6 +161,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_RT1011 imply SND_SOC_RT1015 imply SND_SOC_RT1015P + imply SND_SOC_RT1019 imply SND_SOC_RT1305 imply SND_SOC_RT1308 imply SND_SOC_RT5514 @@ -1079,6 +1080,7 @@ config SND_SOC_RL6231 default y if SND_SOC_RT1011=y default y if SND_SOC_RT1015=y default y if SND_SOC_RT1015P=y + default y if SND_SOC_RT1019=y default y if SND_SOC_RT1305=y default y if SND_SOC_RT1308=y default m if SND_SOC_RT5514=m @@ -1097,6 +1099,7 @@ config SND_SOC_RL6231 default m if SND_SOC_RT1011=m default m if SND_SOC_RT1015=m default m if SND_SOC_RT1015P=m + default m if SND_SOC_RT1019=m default m if SND_SOC_RT1305=m default m if SND_SOC_RT1308=m @@ -1133,6 +1136,10 @@ config SND_SOC_RT1015P tristate depends on GPIOLIB +config SND_SOC_RT1019 + tristate + depends on I2C + config SND_SOC_RT1305 tristate depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index dcc2f757bb82..edff5c5b92d3 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -170,6 +170,7 @@ snd-soc-rl6347a-objs := rl6347a.o snd-soc-rt1011-objs := rt1011.o snd-soc-rt1015-objs := rt1015.o snd-soc-rt1015p-objs := rt1015p.o +snd-soc-rt1019-objs := rt1019.o snd-soc-rt1305-objs := rt1305.o snd-soc-rt1308-objs := rt1308.o snd-soc-rt1308-sdw-objs := rt1308-sdw.o @@ -487,6 +488,7 @@ obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o obj-$(CONFIG_SND_SOC_RT1011) += snd-soc-rt1011.o obj-$(CONFIG_SND_SOC_RT1015) += snd-soc-rt1015.o obj-$(CONFIG_SND_SOC_RT1015P) += snd-soc-rt1015p.o +obj-$(CONFIG_SND_SOC_RT1019) += snd-soc-rt1019.o obj-$(CONFIG_SND_SOC_RT1305) += snd-soc-rt1305.o obj-$(CONFIG_SND_SOC_RT1308) += snd-soc-rt1308.o obj-$(CONFIG_SND_SOC_RT1308_SDW) += snd-soc-rt1308-sdw.o diff --git a/sound/soc/codecs/rt1019.c b/sound/soc/codecs/rt1019.c new file mode 100644 index 000000000000..fb275686a00f --- /dev/null +++ b/sound/soc/codecs/rt1019.c @@ -0,0 +1,940 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// rt1019.c -- RT1019 ALSA SoC audio amplifier driver +// Author: Jack Yu <jack.yu(a)realtek.com> +// +// Copyright(c) 2021 Realtek Semiconductor Corp. +// +// + +#include <linux/acpi.h> +#include <linux/fs.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/regmap.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/firmware.h> +#include <linux/gpio.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#include "rl6231.h" +#include "rt1019.h" + +static const struct reg_default rt1019_reg[] = { + { 0x0000, 0x00 }, + { 0x0002, 0x55 }, + { 0x0003, 0x55 }, + { 0x0005, 0x54 }, + { 0x0006, 0x05 }, + { 0x0007, 0x01 }, + { 0x0008, 0x70 }, + { 0x0009, 0x28 }, + { 0x000a, 0x7f }, + { 0x0011, 0x04 }, + { 0x0013, 0x00 }, + { 0x0015, 0x00 }, + { 0x0017, 0x00 }, + { 0x0019, 0x30 }, + { 0x001b, 0x01 }, + { 0x001d, 0x18 }, + { 0x001f, 0x29 }, + { 0x0021, 0x09 }, + { 0x0023, 0x02 }, + { 0x0025, 0x00 }, + { 0x0026, 0x00 }, + { 0x0028, 0x03 }, + { 0x0053, 0x00 }, + { 0x0055, 0x00 }, + { 0x0056, 0x00 }, + { 0x0057, 0x00 }, + { 0x0058, 0x00 }, + { 0x005a, 0x00 }, + { 0x005c, 0x00 }, + { 0x005d, 0x00 }, + { 0x005e, 0x10 }, + { 0x005f, 0xec }, + { 0x0061, 0x10 }, + { 0x0062, 0x19 }, + { 0x0064, 0x00 }, + { 0x0066, 0x08 }, + { 0x0068, 0x00 }, + { 0x006a, 0x00 }, + { 0x006c, 0x00 }, + { 0x006e, 0x00 }, + { 0x0100, 0x80 }, + { 0x0100, 0x51 }, + { 0x0102, 0x23 }, + { 0x0102, 0x0f }, + { 0x0104, 0x6c }, + { 0x0105, 0xec }, + { 0x0106, 0x00 }, + { 0x0107, 0x00 }, + { 0x0108, 0x00 }, + { 0x0200, 0x40 }, + { 0x0201, 0x00 }, + { 0x0202, 0x00 }, + { 0x0203, 0x00 }, + { 0x0301, 0x02 }, + { 0x0302, 0xaa }, + { 0x0303, 0x2a }, + { 0x0304, 0x6a }, + { 0x0306, 0xb0 }, + { 0x0308, 0x48 }, + { 0x030a, 0x0a }, + { 0x030b, 0x4b }, + { 0x030d, 0x7d }, + { 0x030e, 0xef }, + { 0x030f, 0x5a }, + { 0x0311, 0x00 }, + { 0x0312, 0x3e }, + { 0x0313, 0x86 }, + { 0x0315, 0xa8 }, + { 0x0318, 0x1b }, + { 0x031a, 0x3d }, + { 0x031c, 0x40 }, + { 0x031d, 0x40 }, + { 0x031e, 0x30 }, + { 0x031f, 0xbb }, + { 0x0320, 0xa5 }, + { 0x0321, 0xa5 }, + { 0x0323, 0x5a }, + { 0x0324, 0xaa }, + { 0x0325, 0x80 }, + { 0x0326, 0xaa }, + { 0x0327, 0x66 }, + { 0x0328, 0x94 }, + { 0x0329, 0x00 }, + { 0x0330, 0x00 }, + { 0x0331, 0x30 }, + { 0x0332, 0x05 }, + { 0x0400, 0x03 }, + { 0x0401, 0x02 }, + { 0x0402, 0x01 }, + { 0x0403, 0x23 }, + { 0x0404, 0x45 }, + { 0x0405, 0x67 }, + { 0x0500, 0x80 }, + { 0x0501, 0x00 }, + { 0x0502, 0x00 }, + { 0x0503, 0x00 }, + { 0x0504, 0xff }, + { 0x0505, 0x24 }, + { 0x0600, 0x75 }, + { 0x0601, 0x41 }, + { 0x0602, 0x60 }, + { 0x0603, 0x7f }, + { 0x0604, 0x65 }, + { 0x0605, 0x43 }, + { 0x0606, 0x00 }, + { 0x0607, 0x00 }, + { 0x0608, 0x00 }, + { 0x0609, 0x00 }, + { 0x060a, 0x00 }, + { 0x060b, 0x00 }, + { 0x060c, 0x00 }, + { 0x060d, 0x00 }, + { 0x060e, 0x00 }, + { 0x060f, 0x00 }, + { 0x0700, 0x15 }, + { 0x0701, 0xc8 }, + { 0x0704, 0x02 }, + { 0x0705, 0x00 }, + { 0x0706, 0x00 }, + { 0x0707, 0x80 }, + { 0x0708, 0x08 }, + { 0x0709, 0x00 }, + { 0x0800, 0x00 }, + { 0x0801, 0x00 }, + { 0x0802, 0x09 }, + { 0x0803, 0x00 }, + { 0x0900, 0x87 }, + { 0x0a01, 0x99 }, + { 0x0a02, 0x40 }, + { 0x0a03, 0x10 }, + { 0x0b00, 0x50 }, + { 0x0b01, 0xc3 }, + { 0x0c00, 0x84 }, + { 0x0c01, 0x00 }, + { 0x0c02, 0xbb }, + { 0x0c03, 0x80 }, + { 0x0c04, 0x10 }, + { 0x0c05, 0x30 }, + { 0x0c06, 0x00 }, + { 0x0d00, 0x80 }, + { 0x0d01, 0xbb }, + { 0x0d02, 0x80 }, + { 0x0d03, 0x00 }, + { 0x0d04, 0x00 }, + { 0x0d05, 0x00 }, + { 0x0e00, 0x80 }, + { 0x0e01, 0xbb }, + { 0x0e02, 0x80 }, + { 0x0e03, 0x00 }, + { 0x0e04, 0x10 }, + { 0x0e05, 0x30 }, + { 0x0f00, 0x80 }, + { 0x0f01, 0xbb }, + { 0x0f02, 0x80 }, + { 0x0f03, 0x00 }, + { 0x0f04, 0x10 }, + { 0x0f05, 0x30 }, + { 0x0f06, 0x88 }, + { 0x0f07, 0x88 }, + { 0x0f08, 0x00 }, + { 0x0f09, 0x00 }, +}; + +static bool rt1019_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RT1019_PWR_STRP_1: + case RT1019_PWR_STRP_2: + case RT1019_SIL_DET_GAT: + case RT1019_PHASE_SYNC: + case RT1019_STAT_MACH_2: + case RT1019_FS_DET_1: + case RT1019_FS_DET_2: + case RT1019_FS_DET_3: + case RT1019_FS_DET_4: + case RT1019_FS_DET_5: + case RT1019_FS_DET_6: + case RT1019_FS_DET_7: + case RT1019_ANA_READ: + case RT1019_VER_ID: + case RT1019_CUSTOM_ID: + case RT1019_VEND_ID_1: + case RT1019_VEND_ID_2: + case RT1019_DEV_ID_1: + case RT1019_DEV_ID_2: + case RT1019_CAL_TOP_3: + case RT1019_CAL_TOP_7: + case RT1019_CAL_TOP_17: + case RT1019_CAL_TOP_18: + case RT1019_CAL_TOP_19: + case RT1019_CAL_TOP_20: + case RT1019_CAL_TOP_21: + case RT1019_CAL_TOP_22: + case RT1019_MDRE_CTRL_2: + case RT1019_MDRE_CTRL_3: + case RT1019_MDRE_CTRL_4: + case RT1019_SIL_DET_2: + case RT1019_PWM_DC_DET_1: + case RT1019_PMC_8: + case RT1019_PMC_9: + case RT1019_SPKDRC_7: + case RT1019_HALF_FREQ_7: + case RT1019_CUR_CTRL_11: + case RT1019_CUR_CTRL_12: + case RT1019_CUR_CTRL_13: + return true; + + default: + return false; + } +} + +static bool rt1019_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RT1019_RESET: + case RT1019_PAD_DRV_1: + case RT1019_PAD_DRV_2: + case RT1019_PAD_PULL_1: + case RT1019_PAD_PULL_2: + case RT1019_PAD_PULL_3: + case RT1019_I2C_CTRL_1: + case RT1019_I2C_CTRL_2: + case RT1019_I2C_CTRL_3: + case RT1019_IDS_CTRL: + case RT1019_ASEL_CTRL: + case RT1019_PLL_RESET: + case RT1019_PWR_STRP_1: + case RT1019_PWR_STRP_2: + case RT1019_BEEP_TONE: + case RT1019_SIL_DET_GAT: + case RT1019_CLASSD_TIME: + case RT1019_CLASSD_OCP: + case RT1019_PHASE_SYNC: + case RT1019_STAT_MACH_1: + case RT1019_STAT_MACH_2: + case RT1019_EFF_CTRL: + case RT1019_FS_DET_1: + case RT1019_FS_DET_2: + case RT1019_FS_DET_3: + case RT1019_FS_DET_4: + case RT1019_FS_DET_5: + case RT1019_FS_DET_6: + case RT1019_FS_DET_7: + case RT1019_ANA_CTRL: + case RT1019_DUMMY_A: + case RT1019_DUMMY_B: + case RT1019_DUMMY_C: + case RT1019_DUMMY_D: + case RT1019_ANA_READ: + case RT1019_VER_ID: + case RT1019_CUSTOM_ID: + case RT1019_VEND_ID_1: + case RT1019_VEND_ID_2: + case RT1019_DEV_ID_1: + case RT1019_DEV_ID_2: + case RT1019_TEST_PAD: + case RT1019_SDB_CTRL: + case RT1019_TEST_CTRL_1: + case RT1019_TEST_CTRL_2: + case RT1019_TEST_CTRL_3: + case RT1019_SCAN_MODE: + case RT1019_CLK_TREE_1: + case RT1019_CLK_TREE_2: + case RT1019_CLK_TREE_3: + case RT1019_CLK_TREE_4: + case RT1019_CLK_TREE_5: + case RT1019_CLK_TREE_6: + case RT1019_CLK_TREE_7: + case RT1019_CLK_TREE_8: + case RT1019_CLK_TREE_9: + case RT1019_ASRC_1: + case RT1019_ASRC_2: + case RT1019_ASRC_3: + case RT1019_ASRC_4: + case RT1019_SYS_CLK: + case RT1019_BIAS_CUR_1: + case RT1019_BIAS_CUR_2: + case RT1019_BIAS_CUR_3: + case RT1019_BIAS_CUR_4: + case RT1019_CHOP_CLK_DAC: + case RT1019_CHOP_CLK_ADC: + case RT1019_LDO_CTRL_1: + case RT1019_LDO_CTRL_2: + case RT1019_PM_ANA_1: + case RT1019_PM_ANA_2: + case RT1019_PM_ANA_3: + case RT1019_PLL_1: + case RT1019_PLL_2: + case RT1019_PLL_3: + case RT1019_PLL_INT_1: + case RT1019_PLL_INT_3: + case RT1019_MIXER: + case RT1019_CLD_OUT_1: + case RT1019_CLD_OUT_2: + case RT1019_CLD_OUT_3: + case RT1019_CLD_OUT_4: + case RT1019_CLD_OUT_5: + case RT1019_CLD_OUT_6: + case RT1019_CLS_INT_REG_1: + case RT1019_CLS_INT_REG_2: + case RT1019_CLS_INT_REG_3: + case RT1019_CLS_INT_REG_4: + case RT1019_CLS_INT_REG_5: + case RT1019_CLS_INT_REG_6: + case RT1019_CLS_INT_REG_7: + case RT1019_CLS_INT_REG_8: + case RT1019_CLS_INT_REG_9: + case RT1019_CLS_INT_REG_10: + case RT1019_TDM_1: + case RT1019_TDM_2: + case RT1019_TDM_3: + case RT1019_TDM_4: + case RT1019_TDM_5: + case RT1019_TDM_6: + case RT1019_DVOL_1: + case RT1019_DVOL_2: + case RT1019_DVOL_3: + case RT1019_DVOL_4: + case RT1019_DMIX_MONO_1: + case RT1019_DMIX_MONO_2: + case RT1019_CAL_TOP_1: + case RT1019_CAL_TOP_2: + case RT1019_CAL_TOP_3: + case RT1019_CAL_TOP_4: + case RT1019_CAL_TOP_5: + case RT1019_CAL_TOP_6: + case RT1019_CAL_TOP_7: + case RT1019_CAL_TOP_8: + case RT1019_CAL_TOP_9: + case RT1019_CAL_TOP_10: + case RT1019_CAL_TOP_11: + case RT1019_CAL_TOP_12: + case RT1019_CAL_TOP_13: + case RT1019_CAL_TOP_14: + case RT1019_CAL_TOP_15: + case RT1019_CAL_TOP_16: + case RT1019_CAL_TOP_17: + case RT1019_CAL_TOP_18: + case RT1019_CAL_TOP_19: + case RT1019_CAL_TOP_20: + case RT1019_CAL_TOP_21: + case RT1019_CAL_TOP_22: + case RT1019_MDRE_CTRL_1: + case RT1019_MDRE_CTRL_2: + case RT1019_MDRE_CTRL_3: + case RT1019_MDRE_CTRL_4: + case RT1019_MDRE_CTRL_5: + case RT1019_MDRE_CTRL_6: + case RT1019_MDRE_CTRL_7: + case RT1019_MDRE_CTRL_8: + case RT1019_MDRE_CTRL_9: + case RT1019_MDRE_CTRL_10: + case RT1019_SCC_CTRL_1: + case RT1019_SCC_CTRL_2: + case RT1019_SCC_CTRL_3: + case RT1019_SCC_DUMMY: + case RT1019_SIL_DET_1: + case RT1019_SIL_DET_2: + case RT1019_PWM_DC_DET_1: + case RT1019_PWM_DC_DET_2: + case RT1019_PWM_DC_DET_3: + case RT1019_PWM_DC_DET_4: + case RT1019_BEEP_1: + case RT1019_BEEP_2: + case RT1019_PMC_1: + case RT1019_PMC_2: + case RT1019_PMC_3: + case RT1019_PMC_4: + case RT1019_PMC_5: + case RT1019_PMC_6: + case RT1019_PMC_7: + case RT1019_PMC_8: + case RT1019_PMC_9: + case RT1019_SPKDRC_1: + case RT1019_SPKDRC_2: + case RT1019_SPKDRC_3: + case RT1019_SPKDRC_4: + case RT1019_SPKDRC_5: + case RT1019_SPKDRC_6: + case RT1019_SPKDRC_7: + case RT1019_HALF_FREQ_1: + case RT1019_HALF_FREQ_2: + case RT1019_HALF_FREQ_3: + case RT1019_HALF_FREQ_4: + case RT1019_HALF_FREQ_5: + case RT1019_HALF_FREQ_6: + case RT1019_HALF_FREQ_7: + case RT1019_CUR_CTRL_1: + case RT1019_CUR_CTRL_2: + case RT1019_CUR_CTRL_3: + case RT1019_CUR_CTRL_4: + case RT1019_CUR_CTRL_5: + case RT1019_CUR_CTRL_6: + case RT1019_CUR_CTRL_7: + case RT1019_CUR_CTRL_8: + case RT1019_CUR_CTRL_9: + case RT1019_CUR_CTRL_10: + case RT1019_CUR_CTRL_11: + case RT1019_CUR_CTRL_12: + case RT1019_CUR_CTRL_13: + return true; + default: + return false; + } +} + +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0); + +static const char * const rt1019_din_source_select[] = { + "Left", + "Right", + "Left + Right average", +}; + +static SOC_ENUM_SINGLE_DECL(rt1019_mono_lr_sel, RT1019_IDS_CTRL, 0, + rt1019_din_source_select); + +static const struct snd_kcontrol_new rt1019_snd_controls[] = { + SOC_SINGLE_TLV("DAC Playback Volume", RT1019_DMIX_MONO_1, 0, + 127, 0, dac_vol_tlv), + SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel), +}; + +static int r1019_dac_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_component_write(component, RT1019_SDB_CTRL, 0xb); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa); + break; + default: + break; + } + + return 0; +} + +static const struct snd_soc_dapm_widget rt1019_dapm_widgets[] = { + SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, + r1019_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_OUTPUT("SPO"), +}; + +static const struct snd_soc_dapm_route rt1019_dapm_routes[] = { + { "DAC", NULL, "AIFRX" }, + { "SPO", NULL, "DAC" }, +}; + +static int rt1019_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); + int pre_div, bclk_ms, frame_size; + unsigned int val_len = 0, sys_div_da_filter = 0; + unsigned int sys_dac_osr = 0, sys_fifo_clk = 0; + unsigned int sys_clk_cal = 0, sys_asrc_in = 0; + + rt1019->lrck = params_rate(params); + pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck); + if (pre_div < 0) { + dev_err(component->dev, "Unsupported clock setting\n"); + return -EINVAL; + } + + frame_size = snd_soc_params_to_frame_size(params); + if (frame_size < 0) { + dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); + return -EINVAL; + } + + bclk_ms = frame_size > 32; + rt1019->bclk = rt1019->lrck * (32 << bclk_ms); + + dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", + rt1019->bclk, rt1019->lrck); + dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", + bclk_ms, pre_div, dai->id); + + switch (pre_div) { + case 0: + sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV1; + sys_dac_osr = RT1019_SYS_DA_OSR_DIV1; + sys_asrc_in = RT1019_ASRC_256FS_DIV1; + sys_fifo_clk = RT1019_SEL_FIFO_DIV1; + sys_clk_cal = RT1019_SEL_CLK_CAL_DIV1; + break; + case 1: + sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV2; + sys_dac_osr = RT1019_SYS_DA_OSR_DIV2; + sys_asrc_in = RT1019_ASRC_256FS_DIV2; + sys_fifo_clk = RT1019_SEL_FIFO_DIV2; + sys_clk_cal = RT1019_SEL_CLK_CAL_DIV2; + break; + case 3: + sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV4; + sys_dac_osr = RT1019_SYS_DA_OSR_DIV4; + sys_asrc_in = RT1019_ASRC_256FS_DIV4; + sys_fifo_clk = RT1019_SEL_FIFO_DIV4; + sys_clk_cal = RT1019_SEL_CLK_CAL_DIV4; + break; + default: + return -EINVAL; + } + + switch (params_width(params)) { + case 16: + break; + case 20: + val_len = RT1019_I2S_DL_20; + break; + case 24: + val_len = RT1019_I2S_DL_24; + break; + case 32: + val_len = RT1019_I2S_DL_32; + break; + case 8: + val_len = RT1019_I2S_DL_8; + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, RT1019_TDM_2, RT1019_I2S_DL_MASK, + val_len); + snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, + RT1019_SEL_FIFO_MASK, sys_fifo_clk); + snd_soc_component_update_bits(component, RT1019_CLK_TREE_2, + RT1019_SYS_DIV_DA_FIL_MASK | RT1019_SYS_DA_OSR_MASK | + RT1019_ASRC_256FS_MASK, sys_div_da_filter | sys_dac_osr | + sys_asrc_in); + snd_soc_component_update_bits(component, RT1019_CLK_TREE_3, + RT1019_SEL_CLK_CAL_MASK, sys_clk_cal); + + return 0; +} + +static int rt1019_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + unsigned int reg_val = 0, reg_val2 = 0; + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + reg_val2 |= RT1019_TDM_BCLK_INV; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + break; + + case SND_SOC_DAIFMT_LEFT_J: + reg_val |= RT1019_I2S_DF_LEFT; + break; + + case SND_SOC_DAIFMT_DSP_A: + reg_val |= RT1019_I2S_DF_PCM_A_R; + break; + + case SND_SOC_DAIFMT_DSP_B: + reg_val |= RT1019_I2S_DF_PCM_B_R; + break; + + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, RT1019_TDM_2, + RT1019_I2S_DF_MASK, reg_val); + snd_soc_component_update_bits(component, RT1019_TDM_1, + RT1019_TDM_BCLK_MASK, reg_val2); + + return 0; +} + +static int rt1019_set_dai_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_component *component = dai->component; + struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0; + + if (freq == rt1019->sysclk && clk_id == rt1019->sysclk_src) + return 0; + + switch (clk_id) { + case RT1019_SCLK_S_BCLK: + reg_val |= RT1019_CLK_SYS_PRE_SEL_BCLK; + break; + + case RT1019_SCLK_S_PLL: + reg_val |= RT1019_CLK_SYS_PRE_SEL_PLL; + break; + + default: + dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); + return -EINVAL; + } + + rt1019->sysclk = freq; + rt1019->sysclk_src = clk_id; + + dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); + + snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, + RT1019_CLK_SYS_PRE_SEL_MASK, reg_val); + + return 0; +} + +static int rt1019_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, + unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_component *component = dai->component; + struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); + struct rl6231_pll_code pll_code; + int ret; + + if (!freq_in || !freq_out) { + dev_dbg(component->dev, "PLL disabled\n"); + rt1019->pll_in = 0; + rt1019->pll_out = 0; + return 0; + } + + if (source == rt1019->pll_src && freq_in == rt1019->pll_in && + freq_out == rt1019->pll_out) + return 0; + + switch (source) { + case RT1019_PLL_S_BCLK: + snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, + RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_BCLK); + break; + + case RT1019_PLL_S_RC25M: + snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, + RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_RC); + break; + + default: + dev_err(component->dev, "Unknown PLL source %d\n", source); + return -EINVAL; + } + + ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); + if (ret < 0) { + dev_err(component->dev, "Unsupport input clock %d\n", freq_in); + return ret; + } + + dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", + pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), + pll_code.n_code, pll_code.k_code); + + snd_soc_component_update_bits(component, RT1019_PWR_STRP_2, + RT1019_AUTO_BITS_SEL_MASK | RT1019_AUTO_CLK_SEL_MASK, + RT1019_AUTO_BITS_SEL_MANU | RT1019_AUTO_CLK_SEL_MANU); + snd_soc_component_update_bits(component, RT1019_PLL_1, + RT1019_PLL_M_MASK | RT1019_PLL_M_BP_MASK | RT1019_PLL_Q_8_8_MASK, + (pll_code.m_bp ? 0 : pll_code.m_code) << RT1019_PLL_M_SFT | + pll_code.m_bp << RT1019_PLL_M_BP_SFT | + ((pll_code.n_code >> 8) & RT1019_PLL_Q_8_8_MASK)); + snd_soc_component_update_bits(component, RT1019_PLL_2, + RT1019_PLL_Q_7_0_MASK, pll_code.n_code & RT1019_PLL_Q_7_0_MASK); + snd_soc_component_update_bits(component, RT1019_PLL_3, + RT1019_PLL_K_MASK, pll_code.k_code); + + rt1019->pll_in = freq_in; + rt1019->pll_out = freq_out; + rt1019->pll_src = source; + + return 0; +} + +static int rt1019_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_component *component = dai->component; + unsigned int val = 0, rx_slotnum; + int ret = 0, first_bit; + + switch (slots) { + case 4: + val |= RT1019_I2S_TX_4CH; + break; + case 6: + val |= RT1019_I2S_TX_6CH; + break; + case 8: + val |= RT1019_I2S_TX_8CH; + break; + case 2: + break; + default: + return -EINVAL; + } + + switch (slot_width) { + case 20: + val |= RT1019_I2S_DL_20; + break; + case 24: + val |= RT1019_I2S_DL_24; + break; + case 32: + val |= RT1019_I2S_DL_32; + break; + case 8: + val |= RT1019_I2S_DL_8; + break; + case 16: + break; + default: + return -EINVAL; + } + + /* Rx slot configuration */ + rx_slotnum = hweight_long(rx_mask); + if (rx_slotnum != 1) { + ret = -EINVAL; + dev_err(component->dev, "too many rx slots or zero slot\n"); + goto _set_tdm_err_; + } + /* This is an assumption that the system sends stereo audio to the + * amplifier typically. And the stereo audio is placed in slot 0/2/4/6 + * as the starting slot. The users could select the channel from + * L/R/L+R by "Mono LR Select" control. + */ + first_bit = __ffs(rx_mask); + switch (first_bit) { + case 0: + case 2: + case 4: + case 6: + snd_soc_component_update_bits(component, + RT1019_TDM_3, + RT1019_TDM_I2S_TX_L_DAC1_1_MASK | + RT1019_TDM_I2S_TX_R_DAC1_1_MASK, + (first_bit << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) | + ((first_bit + 1) << RT1019_TDM_I2S_TX_R_DAC1_1_SFT)); + break; + case 1: + case 3: + case 5: + case 7: + snd_soc_component_update_bits(component, + RT1019_TDM_3, + RT1019_TDM_I2S_TX_L_DAC1_1_MASK | + RT1019_TDM_I2S_TX_R_DAC1_1_MASK, + ((first_bit - 1) << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) | + (first_bit << RT1019_TDM_I2S_TX_R_DAC1_1_SFT)); + break; + default: + ret = -EINVAL; + goto _set_tdm_err_; + } + + snd_soc_component_update_bits(component, RT1019_TDM_2, + RT1019_I2S_CH_TX_MASK | RT1019_I2S_DF_MASK, val); + +_set_tdm_err_: + return ret; +} + +static int rt1019_probe(struct snd_soc_component *component) +{ + struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); + + rt1019->component = component; + snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa); + + return 0; +} + +#define RT1019_STEREO_RATES SNDRV_PCM_RATE_8000_192000 +#define RT1019_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) + +static struct snd_soc_dai_ops rt1019_aif_dai_ops = { + .hw_params = rt1019_hw_params, + .set_fmt = rt1019_set_dai_fmt, + .set_sysclk = rt1019_set_dai_sysclk, + .set_pll = rt1019_set_dai_pll, + .set_tdm_slot = rt1019_set_tdm_slot, +}; + +static struct snd_soc_dai_driver rt1019_dai[] = { + { + .name = "rt1019-aif", + .id = 0, + .playback = { + .stream_name = "AIF Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1019_STEREO_RATES, + .formats = RT1019_FORMATS, + }, + .ops = &rt1019_aif_dai_ops, + } +}; + +static const struct snd_soc_component_driver soc_component_dev_rt1019 = { + .probe = rt1019_probe, + .controls = rt1019_snd_controls, + .num_controls = ARRAY_SIZE(rt1019_snd_controls), + .dapm_widgets = rt1019_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1019_dapm_widgets), + .dapm_routes = rt1019_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1019_dapm_routes), +}; + +static const struct regmap_config rt1019_regmap = { + .reg_bits = 16, + .val_bits = 8, + .use_single_read = true, + .use_single_write = true, + .max_register = RT1019_CUR_CTRL_13, + .volatile_reg = rt1019_volatile_register, + .readable_reg = rt1019_readable_register, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = rt1019_reg, + .num_reg_defaults = ARRAY_SIZE(rt1019_reg), +}; + +static const struct i2c_device_id rt1019_i2c_id[] = { + { "rt1019", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rt1019_i2c_id); + +static const struct of_device_id rt1019_of_match[] = { + { .compatible = "realtek,rt1019", }, + {}, +}; +MODULE_DEVICE_TABLE(of, rt1019_of_match); + +#ifdef CONFIG_ACPI +static const struct acpi_device_id rt1019_acpi_match[] = { + { "10EC1019", 0}, + { }, +}; +MODULE_DEVICE_TABLE(acpi, rt1019_acpi_match); +#endif + +static int rt1019_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct rt1019_priv *rt1019; + int ret; + unsigned int val, val2, dev_id; + + rt1019 = devm_kzalloc(&i2c->dev, sizeof(struct rt1019_priv), + GFP_KERNEL); + if (!rt1019) + return -ENOMEM; + + i2c_set_clientdata(i2c, rt1019); + + rt1019->regmap = devm_regmap_init_i2c(i2c, &rt1019_regmap); + if (IS_ERR(rt1019->regmap)) { + ret = PTR_ERR(rt1019->regmap); + dev_err(&i2c->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + regmap_read(rt1019->regmap, RT1019_DEV_ID_1, &val); + regmap_read(rt1019->regmap, RT1019_DEV_ID_2, &val2); + dev_id = val << 8 | val2; + if (dev_id != RT1019_DEVICE_ID_VAL && dev_id != RT1019_DEVICE_ID_VAL2) { + dev_err(&i2c->dev, + "Device with ID register 0x%x is not rt1019\n", dev_id); + return -ENODEV; + } + + return devm_snd_soc_register_component(&i2c->dev, + &soc_component_dev_rt1019, rt1019_dai, ARRAY_SIZE(rt1019_dai)); +} + +struct i2c_driver rt1019_i2c_driver = { + .driver = { + .name = "rt1019", + .of_match_table = of_match_ptr(rt1019_of_match), + .acpi_match_table = ACPI_PTR(rt1019_acpi_match), + }, + .probe = rt1019_i2c_probe, + .id_table = rt1019_i2c_id, +}; +module_i2c_driver(rt1019_i2c_driver); + +MODULE_DESCRIPTION("ASoC RT1019 driver"); +MODULE_AUTHOR("Jack Yu <jack.yu(a)realtek.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/rt1019.h b/sound/soc/codecs/rt1019.h new file mode 100644 index 000000000000..46973e71c963 --- /dev/null +++ b/sound/soc/codecs/rt1019.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * rt1019.h -- RT1019 ALSA SoC audio amplifier driver + * + * Copyright(c) 2021 Realtek Semiconductor Corp. + */ + +#ifndef __RT1019_H__ +#define __RT1019_H__ + +#define RT1019_DEVICE_ID_VAL 0x1019 +#define RT1019_DEVICE_ID_VAL2 0x6731 + +#define RT1019_RESET 0x0000 +#define RT1019_PAD_DRV_1 0x0002 +#define RT1019_PAD_DRV_2 0x0003 +#define RT1019_PAD_PULL_1 0x0005 +#define RT1019_PAD_PULL_2 0x0006 +#define RT1019_PAD_PULL_3 0x0007 +#define RT1019_I2C_CTRL_1 0x0008 +#define RT1019_I2C_CTRL_2 0x0009 +#define RT1019_I2C_CTRL_3 0x000a +#define RT1019_IDS_CTRL 0x0011 +#define RT1019_ASEL_CTRL 0x0013 +#define RT1019_PLL_RESET 0x0015 +#define RT1019_PWR_STRP_1 0x0017 +#define RT1019_PWR_STRP_2 0x0019 +#define RT1019_BEEP_TONE 0x001b +#define RT1019_SIL_DET_GAT 0x001d +#define RT1019_CLASSD_TIME 0x001f +#define RT1019_CLASSD_OCP 0x0021 +#define RT1019_PHASE_SYNC 0x0023 +#define RT1019_STAT_MACH_1 0x0025 +#define RT1019_STAT_MACH_2 0x0026 +#define RT1019_EFF_CTRL 0x0028 +#define RT1019_FS_DET_1 0x002a +#define RT1019_FS_DET_2 0x002b +#define RT1019_FS_DET_3 0x002c +#define RT1019_FS_DET_4 0x002d +#define RT1019_FS_DET_5 0x002e +#define RT1019_FS_DET_6 0x002f +#define RT1019_FS_DET_7 0x0030 +#define RT1019_ANA_CTRL 0x0053 +#define RT1019_DUMMY_A 0x0055 +#define RT1019_DUMMY_B 0x0056 +#define RT1019_DUMMY_C 0x0057 +#define RT1019_DUMMY_D 0x0058 +#define RT1019_ANA_READ 0x005a +#define RT1019_VER_ID 0x005c +#define RT1019_CUSTOM_ID 0x005d +#define RT1019_VEND_ID_1 0x005e +#define RT1019_VEND_ID_2 0x005f +#define RT1019_DEV_ID_1 0x0061 +#define RT1019_DEV_ID_2 0x0062 +#define RT1019_TEST_PAD 0x0064 +#define RT1019_SDB_CTRL 0x0066 +#define RT1019_TEST_CTRL_1 0x0068 +#define RT1019_TEST_CTRL_2 0x006a +#define RT1019_TEST_CTRL_3 0x006c +#define RT1019_SCAN_MODE 0x006e +#define RT1019_CLK_TREE_1 0x0100 +#define RT1019_CLK_TREE_2 0x0101 +#define RT1019_CLK_TREE_3 0x0102 +#define RT1019_CLK_TREE_4 0x0103 +#define RT1019_CLK_TREE_5 0x0104 +#define RT1019_CLK_TREE_6 0x0105 +#define RT1019_CLK_TREE_7 0x0106 +#define RT1019_CLK_TREE_8 0x0107 +#define RT1019_CLK_TREE_9 0x0108 +#define RT1019_ASRC_1 0x0200 +#define RT1019_ASRC_2 0x0201 +#define RT1019_ASRC_3 0x0202 +#define RT1019_ASRC_4 0x0203 +#define RT1019_SYS_CLK 0x0300 +#define RT1019_BIAS_CUR_1 0x0301 +#define RT1019_BIAS_CUR_2 0x0302 +#define RT1019_BIAS_CUR_3 0x0303 +#define RT1019_BIAS_CUR_4 0x0304 +#define RT1019_CHOP_CLK_DAC 0x0306 +#define RT1019_CHOP_CLK_ADC 0x0308 +#define RT1019_LDO_CTRL_1 0x030a +#define RT1019_LDO_CTRL_2 0x030b +#define RT1019_PM_ANA_1 0x030d +#define RT1019_PM_ANA_2 0x030e +#define RT1019_PM_ANA_3 0x030f +#define RT1019_PLL_1 0x0311 +#define RT1019_PLL_2 0x0312 +#define RT1019_PLL_3 0x0313 +#define RT1019_PLL_INT_1 0x0315 +#define RT1019_PLL_INT_3 0x0318 +#define RT1019_MIXER 0x031a +#define RT1019_CLD_OUT_1 0x031c +#define RT1019_CLD_OUT_2 0x031d +#define RT1019_CLD_OUT_3 0x031e +#define RT1019_CLD_OUT_4 0x031f +#define RT1019_CLD_OUT_5 0x0320 +#define RT1019_CLD_OUT_6 0x0321 +#define RT1019_CLS_INT_REG_1 0x0323 +#define RT1019_CLS_INT_REG_2 0x0324 +#define RT1019_CLS_INT_REG_3 0x0325 +#define RT1019_CLS_INT_REG_4 0x0326 +#define RT1019_CLS_INT_REG_5 0x0327 +#define RT1019_CLS_INT_REG_6 0x0328 +#define RT1019_CLS_INT_REG_7 0x0329 +#define RT1019_CLS_INT_REG_8 0x0330 +#define RT1019_CLS_INT_REG_9 0x0331 +#define RT1019_CLS_INT_REG_10 0x0332 +#define RT1019_TDM_1 0x0400 +#define RT1019_TDM_2 0x0401 +#define RT1019_TDM_3 0x0402 +#define RT1019_TDM_4 0x0403 +#define RT1019_TDM_5 0x0404 +#define RT1019_TDM_6 0x0405 +#define RT1019_DVOL_1 0x0500 +#define RT1019_DVOL_2 0x0501 +#define RT1019_DVOL_3 0x0502 +#define RT1019_DVOL_4 0x0503 +#define RT1019_DMIX_MONO_1 0x0504 +#define RT1019_DMIX_MONO_2 0x0505 +#define RT1019_CAL_TOP_1 0x0600 +#define RT1019_CAL_TOP_2 0x0601 +#define RT1019_CAL_TOP_3 0x0602 +#define RT1019_CAL_TOP_4 0x0603 +#define RT1019_CAL_TOP_5 0x0604 +#define RT1019_CAL_TOP_6 0x0605 +#define RT1019_CAL_TOP_7 0x0606 +#define RT1019_CAL_TOP_8 0x0607 +#define RT1019_CAL_TOP_9 0x0608 +#define RT1019_CAL_TOP_10 0x0609 +#define RT1019_CAL_TOP_11 0x060a +#define RT1019_CAL_TOP_12 0x060b +#define RT1019_CAL_TOP_13 0x060c +#define RT1019_CAL_TOP_14 0x060d +#define RT1019_CAL_TOP_15 0x060e +#define RT1019_CAL_TOP_16 0x060f +#define RT1019_CAL_TOP_17 0x0610 +#define RT1019_CAL_TOP_18 0x0611 +#define RT1019_CAL_TOP_19 0x0612 +#define RT1019_CAL_TOP_20 0x0613 +#define RT1019_CAL_TOP_21 0x0614 +#define RT1019_CAL_TOP_22 0x0615 +#define RT1019_MDRE_CTRL_1 0x0700 +#define RT1019_MDRE_CTRL_2 0x0701 +#define RT1019_MDRE_CTRL_3 0x0702 +#define RT1019_MDRE_CTRL_4 0x0703 +#define RT1019_MDRE_CTRL_5 0x0704 +#define RT1019_MDRE_CTRL_6 0x0705 +#define RT1019_MDRE_CTRL_7 0x0706 +#define RT1019_MDRE_CTRL_8 0x0707 +#define RT1019_MDRE_CTRL_9 0x0708 +#define RT1019_MDRE_CTRL_10 0x0709 +#define RT1019_SCC_CTRL_1 0x0800 +#define RT1019_SCC_CTRL_2 0x0801 +#define RT1019_SCC_CTRL_3 0x0802 +#define RT1019_SCC_DUMMY 0x0803 +#define RT1019_SIL_DET_1 0x0900 +#define RT1019_SIL_DET_2 0x0901 +#define RT1019_PWM_DC_DET_1 0x0a00 +#define RT1019_PWM_DC_DET_2 0x0a01 +#define RT1019_PWM_DC_DET_3 0x0a02 +#define RT1019_PWM_DC_DET_4 0x0a03 +#define RT1019_BEEP_1 0x0b00 +#define RT1019_BEEP_2 0x0b01 +#define RT1019_PMC_1 0x0c00 +#define RT1019_PMC_2 0x0c01 +#define RT1019_PMC_3 0x0c02 +#define RT1019_PMC_4 0x0c03 +#define RT1019_PMC_5 0x0c04 +#define RT1019_PMC_6 0x0c05 +#define RT1019_PMC_7 0x0c06 +#define RT1019_PMC_8 0x0c07 +#define RT1019_PMC_9 0x0c08 +#define RT1019_SPKDRC_1 0x0d00 +#define RT1019_SPKDRC_2 0x0d01 +#define RT1019_SPKDRC_3 0x0d02 +#define RT1019_SPKDRC_4 0x0d03 +#define RT1019_SPKDRC_5 0x0d04 +#define RT1019_SPKDRC_6 0x0d05 +#define RT1019_SPKDRC_7 0x0d06 +#define RT1019_HALF_FREQ_1 0x0e00 +#define RT1019_HALF_FREQ_2 0x0e01 +#define RT1019_HALF_FREQ_3 0x0e02 +#define RT1019_HALF_FREQ_4 0x0e03 +#define RT1019_HALF_FREQ_5 0x0e04 +#define RT1019_HALF_FREQ_6 0x0e05 +#define RT1019_HALF_FREQ_7 0x0e06 +#define RT1019_CUR_CTRL_1 0x0f00 +#define RT1019_CUR_CTRL_2 0x0f01 +#define RT1019_CUR_CTRL_3 0x0f02 +#define RT1019_CUR_CTRL_4 0x0f03 +#define RT1019_CUR_CTRL_5 0x0f04 +#define RT1019_CUR_CTRL_6 0x0f05 +#define RT1019_CUR_CTRL_7 0x0f06 +#define RT1019_CUR_CTRL_8 0x0f07 +#define RT1019_CUR_CTRL_9 0x0f08 +#define RT1019_CUR_CTRL_10 0x0f09 +#define RT1019_CUR_CTRL_11 0x0f0a +#define RT1019_CUR_CTRL_12 0x0f0b +#define RT1019_CUR_CTRL_13 0x0f0c + +/* 0x0019 Power On Strap Control-2 */ +#define RT1019_AUTO_BITS_SEL_MASK (0x1 << 5) +#define RT1019_AUTO_BITS_SEL_AUTO (0x1 << 5) +#define RT1019_AUTO_BITS_SEL_MANU (0x0 << 5) +#define RT1019_AUTO_CLK_SEL_MASK (0x1 << 4) +#define RT1019_AUTO_CLK_SEL_AUTO (0x1 << 4) +#define RT1019_AUTO_CLK_SEL_MANU (0x0 << 4) + +/* 0x0100 Clock Tree Control-1 */ +#define RT1019_CLK_SYS_PRE_SEL_MASK (0x1 << 7) +#define RT1019_CLK_SYS_PRE_SEL_SFT 7 +#define RT1019_CLK_SYS_PRE_SEL_BCLK (0x0 << 7) +#define RT1019_CLK_SYS_PRE_SEL_PLL (0x1 << 7) +#define RT1019_PLL_SRC_MASK (0x1 << 4) +#define RT1019_PLL_SRC_SFT 4 +#define RT1019_PLL_SRC_SEL_BCLK (0x0 << 4) +#define RT1019_PLL_SRC_SEL_RC (0x1 << 4) +#define RT1019_SEL_FIFO_MASK (0x3 << 2) +#define RT1019_SEL_FIFO_DIV1 (0x0 << 2) +#define RT1019_SEL_FIFO_DIV2 (0x1 << 2) +#define RT1019_SEL_FIFO_DIV4 (0x2 << 2) + +/* 0x0101 clock tree control-2 */ +#define RT1019_SYS_DIV_DA_FIL_MASK (0x7 << 5) +#define RT1019_SYS_DIV_DA_FIL_DIV1 (0x2 << 5) +#define RT1019_SYS_DIV_DA_FIL_DIV2 (0x3 << 5) +#define RT1019_SYS_DIV_DA_FIL_DIV4 (0x4 << 5) +#define RT1019_SYS_DA_OSR_MASK (0x3 << 2) +#define RT1019_SYS_DA_OSR_DIV1 (0x0 << 2) +#define RT1019_SYS_DA_OSR_DIV2 (0x1 << 2) +#define RT1019_SYS_DA_OSR_DIV4 (0x2 << 2) +#define RT1019_ASRC_256FS_MASK 0x3 +#define RT1019_ASRC_256FS_DIV1 0x0 +#define RT1019_ASRC_256FS_DIV2 0x1 +#define RT1019_ASRC_256FS_DIV4 0x2 + +/* 0x0102 clock tree control-3 */ +#define RT1019_SEL_CLK_CAL_MASK (0x3 << 6) +#define RT1019_SEL_CLK_CAL_DIV1 (0x0 << 6) +#define RT1019_SEL_CLK_CAL_DIV2 (0x1 << 6) +#define RT1019_SEL_CLK_CAL_DIV4 (0x2 << 6) + +/* 0x0311 PLL-1 */ +#define RT1019_PLL_M_MASK (0xf << 4) +#define RT1019_PLL_M_SFT 4 +#define RT1019_PLL_M_BP_MASK (0x1 << 1) +#define RT1019_PLL_M_BP_SFT 1 +#define RT1019_PLL_Q_8_8_MASK (0x1) + +/* 0x0312 PLL-2 */ +#define RT1019_PLL_Q_7_0_MASK 0xff + +/* 0x0313 PLL-3 */ +#define RT1019_PLL_K_MASK 0x1f + +/* 0x0400 TDM Control-1 */ +#define RT1019_TDM_BCLK_MASK (0x1 << 6) +#define RT1019_TDM_BCLK_NORM (0x0 << 6) +#define RT1019_TDM_BCLK_INV (0x1 << 6) + +/* 0x0401 TDM Control-2 */ +#define RT1019_I2S_CH_TX_MASK (0x3 << 6) +#define RT1019_I2S_CH_TX_SFT 6 +#define RT1019_I2S_TX_2CH (0x0 << 6) +#define RT1019_I2S_TX_4CH (0x1 << 6) +#define RT1019_I2S_TX_6CH (0x2 << 6) +#define RT1019_I2S_TX_8CH (0x3 << 6) +#define RT1019_I2S_DF_MASK (0x7 << 3) +#define RT1019_I2S_DF_SFT 3 +#define RT1019_I2S_DF_I2S (0x0 << 3) +#define RT1019_I2S_DF_LEFT (0x1 << 3) +#define RT1019_I2S_DF_PCM_A_R (0x2 << 3) +#define RT1019_I2S_DF_PCM_B_R (0x3 << 3) +#define RT1019_I2S_DF_PCM_A_F (0x6 << 3) +#define RT1019_I2S_DF_PCM_B_F (0x7 << 3) +#define RT1019_I2S_DL_MASK 0x7 +#define RT1019_I2S_DL_SFT 0 +#define RT1019_I2S_DL_16 0x0 +#define RT1019_I2S_DL_20 0x1 +#define RT1019_I2S_DL_24 0x2 +#define RT1019_I2S_DL_32 0x3 +#define RT1019_I2S_DL_8 0x4 + +/* TDM1 Control-3 (0x0402) */ +#define RT1019_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 4) +#define RT1019_TDM_I2S_TX_R_DAC1_1_MASK 0x7 +#define RT1019_TDM_I2S_TX_L_DAC1_1_SFT 4 +#define RT1019_TDM_I2S_TX_R_DAC1_1_SFT 0 + +/* System Clock Source */ +enum { + RT1019_SCLK_S_BCLK, + RT1019_SCLK_S_PLL, +}; + +/* PLL1 Source */ +enum { + RT1019_PLL_S_BCLK, + RT1019_PLL_S_RC25M, +}; + +enum { + RT1019_AIF1, + RT1019_AIFS +}; + +struct rt1019_priv { + struct snd_soc_component *component; + struct regmap *regmap; + int sysclk; + int sysclk_src; + int lrck; + int bclk; + int pll_src; + int pll_in; + int pll_out; + unsigned int bclk_ratio; +}; + +#endif /* __RT1019_H__ */ -- 2.29.0

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[PATCH 5.10 02/49] [PATCH v2] ASoC: SOF: Intel: broadwell: fix mutual exclusion with catpt driver
by gregkh＠linuxfoundation.org 10 Mar '21

10 Mar '21

From: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> From: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> In v5.10, the "haswell" driver was replaced by the "catpt" driver, but the mutual exclusion with the SOF driver was not updated. This leads to errors with card names and UCM profiles not being loaded by PulseAudio. This fix should only be applied on v5.10-stable, the mutual exclusion was removed in 5.11. Reported-by: David Ward <david.ward(a)ll.mit.edu> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=211985 Fixes: 6cbfa11d2694 ("ASoC: Intel: Select catpt and deprecate haswell") Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Cezary Rojewski <cezary.rojewski(a)intel.com> Acked-by: Mark Brown <broonie(a)kernel.org> Cc: <stable(a)vger.kernel.org> Cc: Sasha Levin <sashal(a)kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> --- sound/soc/sof/intel/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/sound/soc/sof/intel/Kconfig +++ b/sound/soc/sof/intel/Kconfig @@ -84,7 +84,7 @@ config SND_SOC_SOF_BAYTRAIL config SND_SOC_SOF_BROADWELL_SUPPORT bool "SOF support for Broadwell" - depends on SND_SOC_INTEL_HASWELL=n + depends on SND_SOC_INTEL_CATPT=n help This adds support for Sound Open Firmware for Intel(R) platforms using the Broadwell processors.

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[PATCH v2] ASoC: SOF: Intel: broadwell: fix mutual exclusion with catpt driver
by Pierre-Louis Bossart 10 Mar '21

10 Mar '21

In v5.10, the "haswell" driver was replaced by the "catpt" driver, but the mutual exclusion with the SOF driver was not updated. This leads to errors with card names and UCM profiles not being loaded by PulseAudio. This fix should only be applied on v5.10-stable, the mutual exclusion was removed in 5.11. Reported-by: David Ward <david.ward(a)ll.mit.edu> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=211985 Fixes: 6cbfa11d2694 ("ASoC: Intel: Select catpt and deprecate haswell") Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Cezary Rojewski <cezary.rojewski(a)intel.com> Acked-by: Mark Brown <broonie(a)kernel.org> Cc: <stable(a)vger.kernel.org> Cc: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> Cc: Sasha Levin <sashal(a)kernel.org> --- v2: added Mark and Cezary tags, fixed stable address, added maintainers sound/soc/sof/intel/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/sof/intel/Kconfig b/sound/soc/sof/intel/Kconfig index de7ff2d097ab..6708a2c5a838 100644 --- a/sound/soc/sof/intel/Kconfig +++ b/sound/soc/sof/intel/Kconfig @@ -84,7 +84,7 @@ config SND_SOC_SOF_BAYTRAIL config SND_SOC_SOF_BROADWELL_SUPPORT bool "SOF support for Broadwell" - depends on SND_SOC_INTEL_HASWELL=n + depends on SND_SOC_INTEL_CATPT=n help This adds support for Sound Open Firmware for Intel(R) platforms using the Broadwell processors. -- 2.25.1

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[PATCH 0/3] ALSA: hda: Fix potential bad accesses at suspend/resume
by Takashi Iwai 10 Mar '21

10 Mar '21

Hi, this is a small patch series to address the bugs that triggers the unexpected accesses during the system suspend/resume. It happens often with Nvidia driver and HDMI codec driver, and it may lead to the serious CORB/RIRB errors. Although the issues are seen mostly on DP/HDMI, a part of the problems is rather generic to all platforms. Takashi === Takashi Iwai (3): ALSA: hda: Flush pending unsolicited events before suspend ALSA: hda: Avoid spurious unsol event handling during S3/S4 ALSA: hda/hdmi: Cancel pending works before suspend sound/pci/hda/hda_bind.c | 4 ++++ sound/pci/hda/hda_intel.c | 2 ++ sound/pci/hda/patch_hdmi.c | 13 +++++++++++++ 3 files changed, 19 insertions(+) -- 2.26.2

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[PATCH alsa-ucm-conf 1/3] codecs/es8316: Fix capture settings
by Hans de Goede 10 Mar '21

10 Mar '21

Fix the following issues with the capture settings: 1. Disable ALC / Auto Level Control, it tries to always get an input signal even when the user is not talking into the mic leading to it cranking up the volume till there is noise at the same level as the user talking. 2. The 'ADC PGA Gain Volume' volume control is not the main 'ADC vol' control, it is the mic amplifier control and setting it to 10 sets it to 24dB not 0dB. Adjust the comment and set it to 7 which is 16dB which gives a good microphone signal strength without introducing too much noise (with 'ADC Capture Volume' set to 0dB). 3. There actually is a main 'ADC vol' control which goes from -96 to 0dB which is simply called the 'ADC Capture Volume' and when disabling ALC it defaults to -96 dB. Add a line setting it to 0dB. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- ucm2/codecs/es8316/EnableSeq.conf | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/ucm2/codecs/es8316/EnableSeq.conf b/ucm2/codecs/es8316/EnableSeq.conf index 97ccfc9..272ef1a 100644 --- a/ucm2/codecs/es8316/EnableSeq.conf +++ b/ucm2/codecs/es8316/EnableSeq.conf @@ -11,11 +11,15 @@ EnableSequence [ cset "name='Headphone Mixer Volume' 4" # Set DAC vol to 0 dB (192/192) cset "name='DAC Playback Volume' 192" - # Set ADC vold to 0 dB (10/10) - cset "name='ADC PGA Gain Volume' 10" + + # Disable Auto Level Control + cset "name='ALC Capture Switch' off" + # Set ADC vol to 0 dB (192/192) + cset "name='ADC Capture Volume' 192" + # Set Mic amplifier to +16 dB + cset "name='ADC PGA Gain Volume' 7" # Setup muxes / switches cset "name='Left Headphone Mixer Left DAC Switch' on" cset "name='Right Headphone Mixer Right DAC Switch' on" - cset "name='ALC Capture Switch' on" ] -- 2.30.1

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RE: [PATCH] Add audio driver for rk817 upstream
by Christopher Morgan 10 Mar '21

10 Mar '21

Thank you. Turns out my mail client crapped out on me (I'm trying to switch to using mutt for replies and accidentally deleted the thread) so I'm afraid my nice and neat reply didn't go quite as expected. I'll work on the things you mention below and resubmit this as an RFC. I'll include the devicetree bindings that I did so you can see how things are mapped. To answer your questions: Acknowledged on the maintainers, the signed-off tag, the pointer, and the commit message. I don't know for sure the best way to accomplish things, I read in the documentation that the simple-audio-card has an option of setting a GPIO which should automatically register with the jack for headphone or microphone sources, that's what I'm trying to do. The specific chip I'm working with has 2 headphone ports (R and L), a single speaker port (let's say LR combined to L), and a single microphone port (L). The codec itself supports 2 channels for the DAC which either power the headphones or the speaker (or both at the same time, if you don't mind either only sending L to the speaker with a proper RL split on the headphones or RL combined to the L headphone with a proper RL combined to the speaker). There are also 2 channels on the ADC, but again only one microphone port which seems odd. Register documentation here for the codec: https://rockchip.fr/RK817%20datasheet%20V1.01.pdf As for the specific implementation I'm working with its here: https://dn.odroid.com/ODROID_GO_ADVANCE/ODROID_GO_ADVANCE_rev1.1.pdf Here's my simple-audio-card DT node: rk817-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,name = "rockchip,rk817-codec"; simple-audio-card,mclk-fs = <256>; simple-audio-card,widgets = "Microphone", "Mic Jack", "Headphone", "Headphones", simple-audio-card,routing = "MIC", "Mic Jack", "Headphones", "HPOL", "Headphones", "HPOR", simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; simple-audio-card,cpu { sound-dai = <&i2s1_2ch>; }; simple-audio-card,codec { sound-dai = <&rk817_codec>; }; }; I copied the rockchip code from the BSP kernel and it had some of the variables, such as the pre_path, as a long. Since it looks like it's just checking the path enums to see if there was a change, I imagine int will do just fine on the pre_path. Speaking of which, that is pre as opposed to post. In this specific step it's looking to see if we're going from off to on or on to off and setting the register values accordingly. As for whether or not the steps are trying to bypass or reimplement something that should be done in DAPM, I'm not sure honestly; this is my first audio driver (or any driver for that matter). I tried to read the DAPM documentation and didn't understand much of it. What I can say is that the code in question is setting the register values via I2C depending upon which audio path is chosen. For example on the SPK_PATH it sets the register at address 0x38 (RK817_CODEC_DDAC_MUTE_MIXCTL) to 0x10, which tells it to switch the amplifier on and combine the channels into a single channel. The HP path likewise does the opposite, setting this same register to 0x00 which turns off the amplifier/splits it back into L+R channels. Curiously enough, this is actually a bug I found in Rockchip's BSP kernel where the channels don't get split apart again when jumping from external speaker back to headphones and your headphones start to output R to R and RL to L... In regards to the DT bindings, I will document all of them, however that poses a dilemma. Most of the bindings I'm unable to test, as aside from mic-in-differential I'm not really using any of them on the single hardware implementation I have available to me. Should I document them based on Rockchip's BSP kernel and note that they are untested, or should I simply delete them and their associated functionality (and focus on that which I can test)? I'll test removing the unregister_component code and see if that does anything unexpected. Thank you again for all of your help. On 3/9/21 5:41 PM, Chris Morgan wrote: > I'm wondering if you all can help me. I'm trying to get the rk817 > codec driver working from Rockchip's BSP kernel sources (GPL per > the license) and I'm struggling with a few parts. The first part is to Cc: audio maintainers (Takashi Iwai and Mark Brown). Then you need to make sure there is a Signed-off-by tag from the original contribution this code is based on, along with yours. It doesn't hurt to have a pointer to that code either in the commit message. > is I'm not sure if I have my audio paths set up correctly. For example > the sinks I have set up are for HPOL and HPOR, and the source is for > MIC. While this does work (audio output seems fine) I'm having issues > with the GPIO to detect headphone insertion. When I insert headphones > I expect the audio to output to the headphones, and when I remove > headphones I expect the audio to output to a speaker. Right now I > have to manually change the output between the different paths. You don't necessarily have to do everything at the kernel level, it's not uncommon to have the driver set a kcontrol for jack detection, and let userspace change settings on a jack detection event. PulseAudio relies on UCM JackControl to switch to Headphones and Headset devices. > Additionally, while the codec "technically" has dual channel inputs > for the microphone, I'm only using the L channel. Should I have a > stereo mixer? Note that I'm using the simple-audio-card to set my > paths, widgets, and the gpio pin. They all work, just not seamlessly > together. > > Basically, I'm wanting to know if and how I should set up my audio > paths for the speaker and headphones, they use mostly the same pins > and only really differ in setting the external amp settings. > Additionally, once I set up my paths how do I ensure that the GPIO > events will result in switching between the speaker/headphone path? > > Any help you can provide is appreciated. This is my first attempt at > something of this magnitude (for me it's a big step), even if it's > just trying to facilitate in getting a vendor's code ready for upstream. > --- /dev/null > +++ b/sound/soc/codecs/rk817_codec.c > @@ -0,0 +1,1148 @@ > +/* > + * Copyright (c) 2018 Rockchip Electronics Co. Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. remove and replace by an SPDX line. > +static int rk817_playback_path_put(struct snd_kcontrol *kcontrol, > + struct snd_ctl_elem_value *ucontrol) > +{ > + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); > + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); > + long int pre_path; it's uncommon to see this, use either int or u32/u64 if your require a specific size. > + > + if (rk817->playback_path == ucontrol->value.integer.value[0]) { > + return 0; > + } > + > + pre_path = rk817->playback_path; 'pre' as in 'previous' or 'preamp' or as opposed to 'post'? > + rk817->playback_path = ucontrol->value.integer.value[0]; > + > + if (rk817->playback_path != OFF) > + clk_prepare_enable(rk817->mclk); > + else > + clk_disable_unprepare(rk817->mclk); > + > + switch (rk817->playback_path) { > + case OFF: > + if (pre_path != OFF && pre_path != HP_PATH) { > + rk817_codec_power_down(component, RK817_CODEC_PLAYBACK); > + if (rk817->capture_path == 0) > + rk817_codec_power_down(component, RK817_CODEC_ALL); > + } > + break; > + case SPK_PATH: > + if (pre_path == OFF) > + rk817_codec_power_up(component, RK817_CODEC_PLAYBACK); > + if (!rk817->use_ext_amplifier) { > + /* power on dac ibias/l/r */ > + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, > + PWD_DACBIAS_ON | PWD_DACD_ON | > + PWD_DACL_DOWN | PWD_DACR_DOWN); > + /* CLASS D mode, combine LR channels */ > + snd_soc_component_write(component, > + RK817_CODEC_DDAC_MUTE_MIXCTL, > + 0x10); > + /* CLASS D enable */ > + snd_soc_component_write(component, > + RK817_CODEC_ACLASSD_CFG1, > + 0xa5); > + /* restart CLASS D, OCPP/N */ > + snd_soc_component_write(component, > + RK817_CODEC_ACLASSD_CFG2, > + 0xf7); > + } else { > + /* HP_CP_EN , CP 2.3V */ > + snd_soc_component_write(component, RK817_CODEC_AHP_CP, > + 0x11); > + /* power on HP two stage opamp ,HP amplitude 0db */ > + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, > + 0x80); > + /* power on dac ibias/l/r */ > + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, > + PWD_DACBIAS_ON | PWD_DACD_DOWN | > + PWD_DACL_ON | PWD_DACR_ON); > + snd_soc_component_update_bits(component, > + RK817_CODEC_DDAC_MUTE_MIXCTL, > + DACMT_ENABLE, DACMT_DISABLE); > + } > + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL, > + rk817->spk_volume); > + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR, > + rk817->spk_volume); > + break; > + case HP_PATH: > + if (pre_path == OFF) > + rk817_codec_power_up(component, RK817_CODEC_PLAYBACK); > + /* HP_CP_EN , CP 2.3V */ > + snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11); > + /* power on HP two stage opamp ,HP amplitude 0db */ > + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80); > + /* power on dac ibias/l/r */ > + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, > + PWD_DACBIAS_ON | PWD_DACD_DOWN | > + PWD_DACL_ON | PWD_DACR_ON); > + /* CLASS D mode disable, split LR channels */ > + snd_soc_component_write(component, > + RK817_CODEC_DDAC_MUTE_MIXCTL, > + 0x00); > + > + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL, > + rk817->hp_volume); > + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR, > + rk817->hp_volume); > + break; > + case SPK_HP: > + if (pre_path == OFF) > + rk817_codec_power_up(component, RK817_CODEC_PLAYBACK); > + > + /* HP_CP_EN , CP 2.3V */ > + snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11); > + /* power on HP two stage opamp ,HP amplitude 0db */ > + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80); > + > + /* power on dac ibias/l/r */ > + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, > + PWD_DACBIAS_ON | PWD_DACD_ON | > + PWD_DACL_ON | PWD_DACR_ON); > + > + if (!rk817->use_ext_amplifier) { > + /* CLASS D mode, combine LR channels */ > + snd_soc_component_write(component, > + RK817_CODEC_DDAC_MUTE_MIXCTL, > + 0x10); > + /* CLASS D enable */ > + snd_soc_component_write(component, > + RK817_CODEC_ACLASSD_CFG1, > + 0xa5); > + /* restart CLASS D, OCPP/N */ > + snd_soc_component_write(component, > + RK817_CODEC_ACLASSD_CFG2, > + 0xf7); > + } > + > + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL, > + rk817->hp_volume); > + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR, > + rk817->hp_volume); > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int rk817_capture_path_get(struct snd_kcontrol *kcontrol, > + struct snd_ctl_elem_value *ucontrol) > +{ > + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); > + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); > + > + dev_dbg(component->dev, "%s:capture_path %ld\n", __func__, rk817->capture_path); > + ucontrol->value.integer.value[0] = rk817->capture_path; > + return 0; > +} > + > +static int rk817_capture_path_put(struct snd_kcontrol *kcontrol, > + struct snd_ctl_elem_value *ucontrol) > +{ > + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); > + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); > + long int pre_path; > + > + if (rk817->capture_path == ucontrol->value.integer.value[0]) { > + dev_dbg(component->dev, "%s:capture_path is not changed!\n", > + __func__); > + return 0; > + } > + > + pre_path = rk817->capture_path; > + rk817->capture_path = ucontrol->value.integer.value[0]; > + > + if (rk817->capture_path != MIC_OFF) > + clk_prepare_enable(rk817->mclk); > + else > + clk_disable_unprepare(rk817->mclk); > + > + switch (rk817->capture_path) { > + case MIC_OFF: > + if (pre_path != MIC_OFF) > + rk817_codec_power_down(component, RK817_CODEC_CAPTURE); > + break; > + case MIC: > + if (pre_path == MIC_OFF) > + rk817_codec_power_up(component, RK817_CODEC_CAPTURE); these sequences look like trying to bypass DAPM or re-invent it with custom state machines. > + > + if (rk817->adc_for_loopback) { > + /* don't need to gain when adc use for loopback */ > + snd_soc_component_update_bits(component, > + RK817_CODEC_AMIC_CFG0, > + 0xf, > + 0x0); > + snd_soc_component_write(component, > + RK817_CODEC_DMIC_PGA_GAIN, > + 0x66); > + snd_soc_component_write(component, > + RK817_CODEC_DADC_VOLL, > + 0x00); > + snd_soc_component_write(component, > + RK817_CODEC_DADC_VOLR, > + 0x00); > + break; > + } > + if (!rk817->mic_in_differential) { > + snd_soc_component_write(component, > + RK817_CODEC_DADC_VOLR, > + 0xff); > + snd_soc_component_update_bits(component, > + RK817_CODEC_AADC_CFG0, > + ADC_R_PWD_MASK, > + ADC_R_PWD_EN); > + snd_soc_component_update_bits(component, > + RK817_CODEC_AMIC_CFG0, > + PWD_PGA_R_MASK, > + PWD_PGA_R_EN); > + } > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + [...] > +static int rk817_codec_parse_dt_property(struct device *dev, > + struct rk817_codec_priv *rk817) > +{ > + struct device_node *node = dev->parent->of_node; > + int ret; > + > + if (!node) { > + dev_err(dev, "%s() dev->parent->of_node is NULL\n", > + __func__); > + return -ENODEV; > + } > + > + node = of_get_child_by_name(dev->parent->of_node, "codec"); > + if (!node) { > + dev_err(dev, "%s() Can not get child: codec\n", > + __func__); > + return -ENODEV; > + } > + > + rk817->hp_ctl_gpio = devm_gpiod_get_optional(dev, "hp-ctl", > + GPIOD_OUT_LOW); > + > + rk817->spk_ctl_gpio = devm_gpiod_get_optional(dev, "spk-ctl", > + GPIOD_OUT_LOW); > + > + ret = of_property_read_u32(node, "spk-mute-delay-ms", > + &rk817->spk_mute_delay); > + if (ret < 0) { > + rk817->spk_mute_delay = 0; > + } > + > + ret = of_property_read_u32(node, "hp-mute-delay-ms", > + &rk817->hp_mute_delay); > + if (ret < 0) { > + rk817->hp_mute_delay = 0; > + } > + > + ret = of_property_read_u32(node, "spk-volume", &rk817->spk_volume); > + if (ret < 0) { > + rk817->spk_volume = OUT_VOLUME; > + } > + if (rk817->spk_volume < 3) > + rk817->spk_volume = 3; > + > + ret = of_property_read_u32(node, "hp-volume", > + &rk817->hp_volume); > + if (ret < 0) { > + rk817->hp_volume = OUT_VOLUME; > + } > + if (rk817->hp_volume < 3) > + rk817->hp_volume = 3; > + > + ret = of_property_read_u32(node, "capture-volume", > + &rk817->capture_volume); > + if (ret < 0) { > + rk817->capture_volume = CAPTURE_VOLUME; > + } > + > + rk817->mic_in_differential = > + of_property_read_bool(node, "mic-in-differential"); > + > + rk817->pdmdata_out_enable = > + of_property_read_bool(node, "pdmdata-out-enable"); > + > + rk817->use_ext_amplifier = > + of_property_read_bool(node, "use-ext-amplifier"); > + > + rk817->adc_for_loopback = > + of_property_read_bool(node, "adc-for-loopback"); you will need DT bindings for all these properties. > + > + return 0; > +} > + > +static const struct regmap_config rk817_codec_regmap_config = { > + .name = "rk817-codec", > + .reg_bits = 8, > + .val_bits = 8, > + .reg_stride = 1, > + .max_register = 0x4f, > + .cache_type = REGCACHE_NONE, > + .volatile_reg = rk817_volatile_register, > + .writeable_reg = rk817_codec_register, > + .readable_reg = rk817_codec_register, > + .reg_defaults = rk817_reg_defaults, > + .num_reg_defaults = ARRAY_SIZE(rk817_reg_defaults), > +}; > + > +static int rk817_platform_probe(struct platform_device *pdev) > +{ > + struct rk808 *rk817 = dev_get_drvdata(pdev->dev.parent); > + struct rk817_codec_priv *rk817_codec_data; > + int ret; > + > + if (!rk817) { > + dev_err(&pdev->dev, "%s : rk817 is NULL\n", __func__); > + return -EINVAL; > + } > + > + rk817_codec_data = devm_kzalloc(&pdev->dev, > + sizeof(struct rk817_codec_priv), > + GFP_KERNEL); > + if (!rk817_codec_data) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, rk817_codec_data); > + > + ret = rk817_codec_parse_dt_property(&pdev->dev, rk817_codec_data); > + if (ret < 0) { > + dev_err(&pdev->dev, "%s() parse device tree property error %d\n", > + __func__, ret); > + goto err_; > + } > + > + rk817_codec_data->regmap = devm_regmap_init_i2c(rk817->i2c, > + &rk817_codec_regmap_config); > + if (IS_ERR(rk817_codec_data->regmap)) { > + ret = PTR_ERR(rk817_codec_data->regmap); > + dev_err(&pdev->dev, "failed to allocate register map: %d\n", > + ret); > + goto err_; > + } > + > + rk817_codec_data->mclk = devm_clk_get(&pdev->dev, "mclk"); > + if (IS_ERR(rk817_codec_data->mclk)) { > + dev_err(&pdev->dev, "Unable to get mclk\n"); > + ret = -ENXIO; > + goto err_; > + } > + > + ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817, > + rk817_dai, ARRAY_SIZE(rk817_dai)); > + if (ret < 0) { > + dev_err(&pdev->dev, "%s() register codec error %d\n", > + __func__, ret); > + goto err_; > + } > + > + return 0; > +err_: > + > + return ret; > +} > + > +static int rk817_platform_remove(struct platform_device *pdev) > +{ > + snd_soc_unregister_component(&pdev->dev); humm, that looks like a bug. If you used devm_soc_register_component() in the probe, you don't need to release it here manually? > +++ b/sound/soc/codecs/rk817_codec.h > @@ -0,0 +1,197 @@ > +/* > + * Copyright (c) 2018 Rockchip Electronics Co. Ltd. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. remove and use SPDX

1 0

[PATCH] Add audio driver for rk817 upstream
by Chris Morgan 10 Mar '21

10 Mar '21

I'm wondering if you all can help me. I'm trying to get the rk817 codec driver working from Rockchip's BSP kernel sources (GPL per the license) and I'm struggling with a few parts. The first part is I'm not sure if I have my audio paths set up correctly. For example the sinks I have set up are for HPOL and HPOR, and the source is for MIC. While this does work (audio output seems fine) I'm having issues with the GPIO to detect headphone insertion. When I insert headphones I expect the audio to output to the headphones, and when I remove headphones I expect the audio to output to a speaker. Right now I have to manually change the output between the different paths. Additionally, while the codec "technically" has dual channel inputs for the microphone, I'm only using the L channel. Should I have a stereo mixer? Note that I'm using the simple-audio-card to set my paths, widgets, and the gpio pin. They all work, just not seamlessly together. Basically, I'm wanting to know if and how I should set up my audio paths for the speaker and headphones, they use mostly the same pins and only really differ in setting the external amp settings. Additionally, once I set up my paths how do I ensure that the GPIO events will result in switching between the speaker/headphone path? Any help you can provide is appreciated. This is my first attempt at something of this magnitude (for me it's a big step), even if it's just trying to facilitate in getting a vendor's code ready for upstream. Thank you. --- drivers/mfd/rk808.c | 6 + sound/soc/codecs/Kconfig | 6 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rk817_codec.c | 1148 ++++++++++++++++++++++++++++++++ sound/soc/codecs/rk817_codec.h | 197 ++++++ 5 files changed, 1359 insertions(+) create mode 100644 sound/soc/codecs/rk817_codec.c create mode 100644 sound/soc/codecs/rk817_codec.h diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c index ad923dd4e007..adb8a7da29db 100644 --- a/drivers/mfd/rk808.c +++ b/drivers/mfd/rk808.c @@ -163,6 +163,12 @@ static const struct mfd_cell rk817s[] = { .num_resources = ARRAY_SIZE(rk817_rtc_resources), .resources = &rk817_rtc_resources[0], }, +#ifdef CONFIG_SND_SOC_RK817 + { + .name = "rk817-codec", + .of_compatible = "rockchip,rk817-codec", + }, +#endif }; static const struct mfd_cell rk818s[] = { diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index e4cf14e66a51..d835145ad65e 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -155,6 +155,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_PCM512x_I2C imply SND_SOC_PCM512x_SPI imply SND_SOC_RK3328 + imply SND_SOC_RK817 imply SND_SOC_RT274 imply SND_SOC_RT286 imply SND_SOC_RT298 @@ -1059,6 +1060,11 @@ config SND_SOC_RK3328 tristate "Rockchip RK3328 audio CODEC" select REGMAP_MMIO +config SND_SOC_RK817 + tristate "Rockchip RK817 audio CODEC" + depends on MFD_RK808 + select REGMAP_I2C + config SND_SOC_RL6231 tristate default y if SND_SOC_RT5514=y diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 81357dc62ea0..4e5e9b28775c 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -165,6 +165,7 @@ snd-soc-pcm512x-objs := pcm512x.o snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o snd-soc-pcm512x-spi-objs := pcm512x-spi.o snd-soc-rk3328-objs := rk3328_codec.o +snd-soc-rk817-objs := rk817_codec.o snd-soc-rl6231-objs := rl6231.o snd-soc-rl6347a-objs := rl6347a.o snd-soc-rt1011-objs := rt1011.o @@ -479,6 +480,7 @@ obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o +obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o obj-$(CONFIG_SND_SOC_RT1011) += snd-soc-rt1011.o diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c new file mode 100644 index 000000000000..973e2f7562f8 --- /dev/null +++ b/sound/soc/codecs/rk817_codec.c @@ -0,0 +1,1148 @@ +/* + * Copyright (c) 2018 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/mfd/rk808.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <sound/core.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/tlv.h> +#include "rk817_codec.h" + +/* For route */ +#define RK817_CODEC_PLAYBACK 1 +#define RK817_CODEC_CAPTURE 2 +#define RK817_CODEC_ALL (RK817_CODEC_PLAYBACK |\ + RK817_CODEC_CAPTURE) + +/* + * DDAC L/R volume setting + * 0db~-95db,0.375db/step,for example: + * 0: 0dB + * 0x0a: -3.75dB + * 0x7d: -46dB + * 0xff: -95dB + */ +#define OUT_VOLUME (0x03) + +/* + * DADC L/R volume setting + * 0db~-95db,0.375db/step,for example: + * 0: 0dB + * 0x0a: -3.75dB + * 0x7d: -46dB + * 0xff: -95dB + */ +#define CAPTURE_VOLUME (0x03) + +#define CODEC_SET_SPK 1 +#define CODEC_SET_HP 2 + +struct rk817_codec_priv { + struct snd_soc_component *component; + struct regmap *regmap; + struct rk808 *rk817; + struct clk *mclk; + + unsigned int stereo_sysclk; + unsigned int rate; + + unsigned int spk_volume; + unsigned int hp_volume; + unsigned int capture_volume; + + bool mic_in_differential; + bool pdmdata_out_enable; + bool use_ext_amplifier; + bool adc_for_loopback; + + long int playback_path; + long int capture_path; + + struct gpio_desc *spk_ctl_gpio; + struct gpio_desc *hp_ctl_gpio; + int spk_mute_delay; + int hp_mute_delay; +}; + +static const struct reg_default rk817_reg_defaults[] = { + { RK817_CODEC_DTOP_VUCTL, 0x003 }, + { RK817_CODEC_DTOP_VUCTIME, 0x00 }, + { RK817_CODEC_DTOP_LPT_SRST, 0x00 }, + { RK817_CODEC_DTOP_DIGEN_CLKE, 0x00 }, + { RK817_CODEC_AREF_RTCFG0, 0x00 }, + { RK817_CODEC_AREF_RTCFG1, 0x06 }, + { RK817_CODEC_AADC_CFG0, 0xc8 }, + { RK817_CODEC_AADC_CFG1, 0x00 }, + { RK817_CODEC_DADC_VOLL, 0x00 }, + { RK817_CODEC_DADC_VOLR, 0x00 }, + { RK817_CODEC_DADC_SR_ACL0, 0x00 }, + { RK817_CODEC_DADC_ALC1, 0x00 }, + { RK817_CODEC_DADC_ALC2, 0x00 }, + { RK817_CODEC_DADC_NG, 0x00 }, + { RK817_CODEC_DADC_HPF, 0x00 }, + { RK817_CODEC_DADC_RVOLL, 0xff }, + { RK817_CODEC_DADC_RVOLR, 0xff }, + { RK817_CODEC_AMIC_CFG0, 0x70 }, + { RK817_CODEC_AMIC_CFG1, 0x00 }, + { RK817_CODEC_DMIC_PGA_GAIN, 0x66 }, + { RK817_CODEC_DMIC_LMT1, 0x00 }, + { RK817_CODEC_DMIC_LMT2, 0x00 }, + { RK817_CODEC_DMIC_NG1, 0x00 }, + { RK817_CODEC_DMIC_NG2, 0x00 }, + { RK817_CODEC_ADAC_CFG0, 0x00 }, + { RK817_CODEC_ADAC_CFG1, 0x07 }, + { RK817_CODEC_DDAC_POPD_DACST, 0x82 }, + { RK817_CODEC_DDAC_VOLL, 0x00 }, + { RK817_CODEC_DDAC_VOLR, 0x00 }, + { RK817_CODEC_DDAC_SR_LMT0, 0x00 }, + { RK817_CODEC_DDAC_LMT1, 0x00 }, + { RK817_CODEC_DDAC_LMT2, 0x00 }, + { RK817_CODEC_DDAC_MUTE_MIXCTL, 0xa0 }, + { RK817_CODEC_DDAC_RVOLL, 0xff }, + { RK817_CODEC_DDAC_RVOLR, 0xff }, + { RK817_CODEC_AHP_ANTI0, 0x00 }, + { RK817_CODEC_AHP_ANTI1, 0x00 }, + { RK817_CODEC_AHP_CFG0, 0xe0 }, + { RK817_CODEC_AHP_CFG1, 0x1f }, + { RK817_CODEC_AHP_CP, 0x09 }, + { RK817_CODEC_ACLASSD_CFG1, 0x69 }, + { RK817_CODEC_ACLASSD_CFG2, 0x44 }, + { RK817_CODEC_APLL_CFG0, 0x04 }, + { RK817_CODEC_APLL_CFG1, 0x00 }, + { RK817_CODEC_APLL_CFG2, 0x30 }, + { RK817_CODEC_APLL_CFG3, 0x19 }, + { RK817_CODEC_APLL_CFG4, 0x65 }, + { RK817_CODEC_APLL_CFG5, 0x01 }, + { RK817_CODEC_DI2S_CKM, 0x01 }, + { RK817_CODEC_DI2S_RSD, 0x00 }, + { RK817_CODEC_DI2S_RXCR1, 0x00 }, + { RK817_CODEC_DI2S_RXCR2, 0x17 }, + { RK817_CODEC_DI2S_RXCMD_TSD, 0x00 }, + { RK817_CODEC_DI2S_TXCR1, 0x00 }, + { RK817_CODEC_DI2S_TXCR2, 0x17 }, + { RK817_CODEC_DI2S_TXCR3_TXCMD, 0x00 }, +}; + +static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, -675); + +static const struct snd_kcontrol_new rk817_dac_controls[] = { + SOC_DOUBLE_R_RANGE_TLV("Playback Volume", RK817_CODEC_DDAC_VOLL, + RK817_CODEC_DDAC_VOLR, 0, 0x12, 0xff, 1, rk817_vol_tlv), + SOC_DOUBLE_R("Record Volume", RK817_CODEC_DADC_VOLL, RK817_CODEC_DADC_VOLR, + 0, 0xFF, 1) +}; + +static bool rk817_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RK817_CODEC_DTOP_LPT_SRST: + return true; + default: + return false; + } +} + +static bool rk817_codec_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RK817_CODEC_DTOP_VUCTL: + case RK817_CODEC_DTOP_VUCTIME: + case RK817_CODEC_DTOP_LPT_SRST: + case RK817_CODEC_DTOP_DIGEN_CLKE: + case RK817_CODEC_AREF_RTCFG0: + case RK817_CODEC_AREF_RTCFG1: + case RK817_CODEC_AADC_CFG0: + case RK817_CODEC_AADC_CFG1: + case RK817_CODEC_DADC_VOLL: + case RK817_CODEC_DADC_VOLR: + case RK817_CODEC_DADC_SR_ACL0: + case RK817_CODEC_DADC_ALC1: + case RK817_CODEC_DADC_ALC2: + case RK817_CODEC_DADC_NG: + case RK817_CODEC_DADC_HPF: + case RK817_CODEC_DADC_RVOLL: + case RK817_CODEC_DADC_RVOLR: + case RK817_CODEC_AMIC_CFG0: + case RK817_CODEC_AMIC_CFG1: + case RK817_CODEC_DMIC_PGA_GAIN: + case RK817_CODEC_DMIC_LMT1: + case RK817_CODEC_DMIC_LMT2: + case RK817_CODEC_DMIC_NG1: + case RK817_CODEC_DMIC_NG2: + case RK817_CODEC_ADAC_CFG0: + case RK817_CODEC_ADAC_CFG1: + case RK817_CODEC_DDAC_POPD_DACST: + case RK817_CODEC_DDAC_VOLL: + case RK817_CODEC_DDAC_VOLR: + case RK817_CODEC_DDAC_SR_LMT0: + case RK817_CODEC_DDAC_LMT1: + case RK817_CODEC_DDAC_LMT2: + case RK817_CODEC_DDAC_MUTE_MIXCTL: + case RK817_CODEC_DDAC_RVOLL: + case RK817_CODEC_DDAC_RVOLR: + case RK817_CODEC_AHP_ANTI0: + case RK817_CODEC_AHP_ANTI1: + case RK817_CODEC_AHP_CFG0: + case RK817_CODEC_AHP_CFG1: + case RK817_CODEC_AHP_CP: + case RK817_CODEC_ACLASSD_CFG1: + case RK817_CODEC_ACLASSD_CFG2: + case RK817_CODEC_APLL_CFG0: + case RK817_CODEC_APLL_CFG1: + case RK817_CODEC_APLL_CFG2: + case RK817_CODEC_APLL_CFG3: + case RK817_CODEC_APLL_CFG4: + case RK817_CODEC_APLL_CFG5: + case RK817_CODEC_DI2S_CKM: + case RK817_CODEC_DI2S_RSD: + case RK817_CODEC_DI2S_RXCR1: + case RK817_CODEC_DI2S_RXCR2: + case RK817_CODEC_DI2S_RXCMD_TSD: + case RK817_CODEC_DI2S_TXCR1: + case RK817_CODEC_DI2S_TXCR2: + case RK817_CODEC_DI2S_TXCR3_TXCMD: + return true; + default: + return false; + } +} + +static int rk817_codec_ctl_gpio(struct rk817_codec_priv *rk817, + int gpio, int level) +{ + if ((gpio & CODEC_SET_SPK) && + rk817->spk_ctl_gpio) { + gpiod_set_value(rk817->spk_ctl_gpio, level); + msleep(rk817->spk_mute_delay); + } + + if ((gpio & CODEC_SET_HP) && + rk817->hp_ctl_gpio) { + gpiod_set_value(rk817->hp_ctl_gpio, level); + msleep(rk817->hp_mute_delay); + } + + return 0; +} + +static int rk817_reset(struct snd_soc_component *component) +{ + snd_soc_component_write(component, RK817_CODEC_DTOP_LPT_SRST, 0x40); + snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02); + snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x0f); + snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04); + snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58); + snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d); + snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, 0x0c); + snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5); + snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x00); + snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00); + + return 0; +} + +static struct rk817_reg_val_typ playback_power_up_list[] = { + {RK817_CODEC_AREF_RTCFG1, 0x40}, + {RK817_CODEC_DDAC_POPD_DACST, 0x02}, + {RK817_CODEC_DDAC_SR_LMT0, 0x02}, + /* APLL */ + {RK817_CODEC_APLL_CFG0, 0x04}, + {RK817_CODEC_APLL_CFG1, 0x58}, + {RK817_CODEC_APLL_CFG2, 0x2d}, + {RK817_CODEC_APLL_CFG3, 0x0c}, + {RK817_CODEC_APLL_CFG4, 0xa5}, + {RK817_CODEC_APLL_CFG5, 0x00}, + + {RK817_CODEC_DI2S_RXCMD_TSD, 0x00}, + {RK817_CODEC_DI2S_RSD, 0x00}, + {RK817_CODEC_DI2S_RXCR1, 0x00}, + {RK817_CODEC_DI2S_RXCMD_TSD, 0x20}, + {RK817_CODEC_DTOP_VUCTIME, 0xf4}, + {RK817_CODEC_DDAC_MUTE_MIXCTL, 0x00}, + + {RK817_CODEC_DDAC_VOLL, 0x0a}, + {RK817_CODEC_DDAC_VOLR, 0x0a}, +}; + +#define RK817_CODEC_PLAYBACK_POWER_UP_LIST_LEN \ + ARRAY_SIZE(playback_power_up_list) + +static struct rk817_reg_val_typ playback_power_down_list[] = { + {RK817_CODEC_DDAC_MUTE_MIXCTL, 0x01}, + {RK817_CODEC_ADAC_CFG1, 0x0f}, + /* HP */ + {RK817_CODEC_AHP_CFG0, 0xe0}, + {RK817_CODEC_AHP_CP, 0x09}, + /* SPK */ + {RK817_CODEC_ACLASSD_CFG1, 0x69}, +}; + +#define RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN \ + ARRAY_SIZE(playback_power_down_list) + +static struct rk817_reg_val_typ capture_power_up_list[] = { + {RK817_CODEC_AREF_RTCFG1, 0x40}, + {RK817_CODEC_DDAC_SR_LMT0, 0x02}, + {RK817_CODEC_DADC_SR_ACL0, 0x02}, + + {RK817_CODEC_APLL_CFG0, 0x04}, + {RK817_CODEC_APLL_CFG1, 0x58}, + {RK817_CODEC_APLL_CFG2, 0x2d}, + {RK817_CODEC_APLL_CFG3, 0x0c}, + {RK817_CODEC_APLL_CFG4, 0xa5}, + {RK817_CODEC_APLL_CFG5, 0x00}, + + {RK817_CODEC_DI2S_RSD, 0x00}, + {RK817_CODEC_DI2S_RXCR1, 0x00}, + {RK817_CODEC_DI2S_RXCMD_TSD, 0x20}, + {RK817_CODEC_DTOP_VUCTIME, 0xf4}, + + {RK817_CODEC_DDAC_MUTE_MIXCTL, 0x00}, + {RK817_CODEC_AADC_CFG0, 0x08}, + {RK817_CODEC_AMIC_CFG0, 0x0f}, + {RK817_CODEC_DI2S_TXCR3_TXCMD, 0x88}, + {RK817_CODEC_DDAC_POPD_DACST, 0x02}, + /* 0x29: -18db to 27db */ + {RK817_CODEC_DMIC_PGA_GAIN, 0x99}, +}; + +#define RK817_CODEC_CAPTURE_POWER_UP_LIST_LEN \ + ARRAY_SIZE(capture_power_up_list) + +static struct rk817_reg_val_typ capture_power_down_list[] = { + {RK817_CODEC_AADC_CFG0, 0xc8}, + {RK817_CODEC_AMIC_CFG0, 0x70}, +}; + +#define RK817_CODEC_CAPTURE_POWER_DOWN_LIST_LEN \ + ARRAY_SIZE(capture_power_down_list) + +static int rk817_codec_power_up(struct snd_soc_component *component, int type) +{ + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + int i; + + if (type & RK817_CODEC_PLAYBACK) { + snd_soc_component_update_bits(component, + RK817_CODEC_DTOP_DIGEN_CLKE, + DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN); + for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_UP_LIST_LEN; i++) { + snd_soc_component_write(component, + playback_power_up_list[i].reg, + playback_power_up_list[i].value); + } + } + + if (type & RK817_CODEC_CAPTURE) { + snd_soc_component_update_bits(component, + RK817_CODEC_DTOP_DIGEN_CLKE, + ADC_DIG_CLK_MASK, + ADC_DIG_CLK_EN); + for (i = 0; i < RK817_CODEC_CAPTURE_POWER_UP_LIST_LEN; i++) { + snd_soc_component_write(component, + capture_power_up_list[i].reg, + capture_power_up_list[i].value); + } + + if (rk817->mic_in_differential) + snd_soc_component_update_bits(component, + RK817_CODEC_AMIC_CFG0, + MIC_DIFF_MASK, MIC_DIFF_EN); + else + snd_soc_component_update_bits(component, + RK817_CODEC_AMIC_CFG0, + MIC_DIFF_MASK, + MIC_DIFF_DIS); + + if (rk817->pdmdata_out_enable) + snd_soc_component_update_bits(component, + RK817_CODEC_DI2S_CKM, + PDM_EN_MASK, + PDM_EN_ENABLE); + + snd_soc_component_write(component, RK817_CODEC_DADC_VOLL, + rk817->capture_volume); + snd_soc_component_write(component, RK817_CODEC_DADC_VOLR, + rk817->capture_volume); + } + + return 0; +} + +static int rk817_codec_power_down(struct snd_soc_component *component, int type) +{ + int i; + + /* mute output for pop noise */ + if (type & RK817_CODEC_PLAYBACK) { + snd_soc_component_update_bits(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_ENABLE, DACMT_ENABLE); + } + + if (type & RK817_CODEC_CAPTURE) { + for (i = 0; i < RK817_CODEC_CAPTURE_POWER_DOWN_LIST_LEN; i++) { + snd_soc_component_write(component, + capture_power_down_list[i].reg, + capture_power_down_list[i].value); + } + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS); + } + + if (type & RK817_CODEC_PLAYBACK) { + for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN; i++) { + snd_soc_component_write(component, + playback_power_down_list[i].reg, + playback_power_down_list[i].value); + } + snd_soc_component_update_bits(component, + RK817_CODEC_DTOP_DIGEN_CLKE, + DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS); + } + + if (type == RK817_CODEC_ALL) { + for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN; i++) { + snd_soc_component_write(component, + playback_power_down_list[i].reg, + playback_power_down_list[i].value); + } + for (i = 0; i < RK817_CODEC_CAPTURE_POWER_DOWN_LIST_LEN; i++) { + snd_soc_component_write(component, + capture_power_down_list[i].reg, + capture_power_down_list[i].value); + } + snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00); + snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x01); + snd_soc_component_write(component, RK817_CODEC_AREF_RTCFG1, 0x06); + } + + return 0; +} + +/* For tiny alsa playback/capture path*/ +static const char * const rk817_playback_path_mode[] = { + "OFF", "SPK", "HP", "SPK_HP"}; + +static const char * const rk817_capture_path_mode[] = { + "MIC OFF", "MIC"}; + +static SOC_ENUM_SINGLE_DECL(rk817_playback_path_type, + 0, 0, rk817_playback_path_mode); + +static SOC_ENUM_SINGLE_DECL(rk817_capture_path_type, + 0, 0, rk817_capture_path_mode); + +static int rk817_playback_path_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rk817->playback_path; + + return 0; +} + +static int rk817_playback_path_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + long int pre_path; + + if (rk817->playback_path == ucontrol->value.integer.value[0]) { + return 0; + } + + pre_path = rk817->playback_path; + rk817->playback_path = ucontrol->value.integer.value[0]; + + if (rk817->playback_path != OFF) + clk_prepare_enable(rk817->mclk); + else + clk_disable_unprepare(rk817->mclk); + + switch (rk817->playback_path) { + case OFF: + if (pre_path != OFF && pre_path != HP_PATH) { + rk817_codec_power_down(component, RK817_CODEC_PLAYBACK); + if (rk817->capture_path == 0) + rk817_codec_power_down(component, RK817_CODEC_ALL); + } + break; + case SPK_PATH: + if (pre_path == OFF) + rk817_codec_power_up(component, RK817_CODEC_PLAYBACK); + if (!rk817->use_ext_amplifier) { + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_ON | + PWD_DACL_DOWN | PWD_DACR_DOWN); + /* CLASS D mode, combine LR channels */ + snd_soc_component_write(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + 0x10); + /* CLASS D enable */ + snd_soc_component_write(component, + RK817_CODEC_ACLASSD_CFG1, + 0xa5); + /* restart CLASS D, OCPP/N */ + snd_soc_component_write(component, + RK817_CODEC_ACLASSD_CFG2, + 0xf7); + } else { + /* HP_CP_EN , CP 2.3V */ + snd_soc_component_write(component, RK817_CODEC_AHP_CP, + 0x11); + /* power on HP two stage opamp ,HP amplitude 0db */ + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, + 0x80); + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_DOWN | + PWD_DACL_ON | PWD_DACR_ON); + snd_soc_component_update_bits(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_ENABLE, DACMT_DISABLE); + } + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL, + rk817->spk_volume); + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR, + rk817->spk_volume); + break; + case HP_PATH: + if (pre_path == OFF) + rk817_codec_power_up(component, RK817_CODEC_PLAYBACK); + /* HP_CP_EN , CP 2.3V */ + snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11); + /* power on HP two stage opamp ,HP amplitude 0db */ + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80); + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_DOWN | + PWD_DACL_ON | PWD_DACR_ON); + /* CLASS D mode disable, split LR channels */ + snd_soc_component_write(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + 0x00); + + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL, + rk817->hp_volume); + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR, + rk817->hp_volume); + break; + case SPK_HP: + if (pre_path == OFF) + rk817_codec_power_up(component, RK817_CODEC_PLAYBACK); + + /* HP_CP_EN , CP 2.3V */ + snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11); + /* power on HP two stage opamp ,HP amplitude 0db */ + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80); + + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_ON | + PWD_DACL_ON | PWD_DACR_ON); + + if (!rk817->use_ext_amplifier) { + /* CLASS D mode, combine LR channels */ + snd_soc_component_write(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + 0x10); + /* CLASS D enable */ + snd_soc_component_write(component, + RK817_CODEC_ACLASSD_CFG1, + 0xa5); + /* restart CLASS D, OCPP/N */ + snd_soc_component_write(component, + RK817_CODEC_ACLASSD_CFG2, + 0xf7); + } + + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL, + rk817->hp_volume); + snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR, + rk817->hp_volume); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk817_capture_path_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + dev_dbg(component->dev, "%s:capture_path %ld\n", __func__, rk817->capture_path); + ucontrol->value.integer.value[0] = rk817->capture_path; + return 0; +} + +static int rk817_capture_path_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + long int pre_path; + + if (rk817->capture_path == ucontrol->value.integer.value[0]) { + dev_dbg(component->dev, "%s:capture_path is not changed!\n", + __func__); + return 0; + } + + pre_path = rk817->capture_path; + rk817->capture_path = ucontrol->value.integer.value[0]; + + if (rk817->capture_path != MIC_OFF) + clk_prepare_enable(rk817->mclk); + else + clk_disable_unprepare(rk817->mclk); + + switch (rk817->capture_path) { + case MIC_OFF: + if (pre_path != MIC_OFF) + rk817_codec_power_down(component, RK817_CODEC_CAPTURE); + break; + case MIC: + if (pre_path == MIC_OFF) + rk817_codec_power_up(component, RK817_CODEC_CAPTURE); + + if (rk817->adc_for_loopback) { + /* don't need to gain when adc use for loopback */ + snd_soc_component_update_bits(component, + RK817_CODEC_AMIC_CFG0, + 0xf, + 0x0); + snd_soc_component_write(component, + RK817_CODEC_DMIC_PGA_GAIN, + 0x66); + snd_soc_component_write(component, + RK817_CODEC_DADC_VOLL, + 0x00); + snd_soc_component_write(component, + RK817_CODEC_DADC_VOLR, + 0x00); + break; + } + if (!rk817->mic_in_differential) { + snd_soc_component_write(component, + RK817_CODEC_DADC_VOLR, + 0xff); + snd_soc_component_update_bits(component, + RK817_CODEC_AADC_CFG0, + ADC_R_PWD_MASK, + ADC_R_PWD_EN); + snd_soc_component_update_bits(component, + RK817_CODEC_AMIC_CFG0, + PWD_PGA_R_MASK, + PWD_PGA_R_EN); + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static struct snd_kcontrol_new rk817_snd_path_controls[] = { + SOC_ENUM_EXT("Playback Path", rk817_playback_path_type, + rk817_playback_path_get, rk817_playback_path_put), + + SOC_ENUM_EXT("Capture Path", rk817_capture_path_type, + rk817_capture_path_get, rk817_capture_path_put), +}; + +static const struct snd_soc_dapm_widget rk817_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("MIC"), + SND_SOC_DAPM_OUTPUT("HPOL"), + SND_SOC_DAPM_OUTPUT("HPOR"), +}; + +static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_component *component = codec_dai->component; + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + rk817->stereo_sysclk = freq; + + return 0; +} + +static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_component *component = codec_dai->component; + unsigned int i2s_mst = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + i2s_mst |= RK817_I2S_MODE_SLV; + break; + case SND_SOC_DAIFMT_CBM_CFM: + i2s_mst |= RK817_I2S_MODE_MST; + break; + default: + dev_err(component->dev, "%s : set master mask failed!\n", __func__); + return -EINVAL; + } + + snd_soc_component_update_bits(component, RK817_CODEC_DI2S_CKM, + RK817_I2S_MODE_MASK, i2s_mst); + + return 0; +} + +static int rk817_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2, + VDW_RX_16BITS); + snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2, + VDW_TX_16BITS); + break; + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S32_LE: + snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2, + VDW_RX_24BITS); + snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2, + VDW_TX_24BITS); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk817_digital_mute(struct snd_soc_dai *dai, int mute, int stream) +{ + struct snd_soc_component *component = dai->component; + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + if (mute) + snd_soc_component_update_bits(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_ENABLE, DACMT_ENABLE); + else + snd_soc_component_update_bits(component, + RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_ENABLE, DACMT_DISABLE); + + if (mute) { + rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 0); + rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 0); + } else { + switch (rk817->playback_path) { + case SPK_PATH: + rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 1); + rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 0); + break; + case HP_PATH: + rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 0); + rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 1); + break; + case SPK_HP: + rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 1); + rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 1); + break; + default: + break; + } + } + + return 0; +} + +#define RK817_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ + SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_96000) + +#define RK817_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ + SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_96000) + +#define RK817_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops rk817_dai_ops = { + .hw_params = rk817_hw_params, + .set_fmt = rk817_set_dai_fmt, + .set_sysclk = rk817_set_dai_sysclk, + .mute_stream = rk817_digital_mute, + .no_capture_mute = 1, +}; + +static struct snd_soc_dai_driver rk817_dai[] = { + { + .name = "rk817-hifi", + .id = RK817_HIFI, + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, + .rates = RK817_PLAYBACK_RATES, + .formats = RK817_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RK817_CAPTURE_RATES, + .formats = RK817_FORMATS, + }, + .ops = &rk817_dai_ops, + }, +}; + +static int rk817_suspend(struct snd_soc_component *component) +{ + rk817_codec_power_down(component, RK817_CODEC_ALL); + return 0; +} + +static int rk817_resume(struct snd_soc_component *component) +{ + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + rk817_codec_power_up(component, RK817_CODEC_ALL); + + switch (rk817->playback_path) { + case OFF: + break; + case SPK_PATH: + if (!rk817->use_ext_amplifier) { + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_ON | + PWD_DACL_ON | PWD_DACR_ON); + /* CLASS D mode */ + snd_soc_component_write(component, RK817_CODEC_DDAC_MUTE_MIXCTL, 0x10); + /* CLASS D enable */ + snd_soc_component_write(component, RK817_CODEC_ACLASSD_CFG1, 0xa5); + /* restart CLASS D, OCPP/N */ + snd_soc_component_write(component, RK817_CODEC_ACLASSD_CFG2, 0xc4); + } else { + /* HP_CP_EN , CP 2.3V */ + snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11); + /* power on HP two stage opamp ,HP amplitude 0db */ + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80); + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_DOWN | + PWD_DACL_ON | PWD_DACR_ON); + snd_soc_component_update_bits(component, RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_ENABLE, DACMT_DISABLE); + } + break; + case HP_PATH: + /* HP_CP_EN , CP 2.3V */ + snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11); + /* power on HP two stage opamp ,HP amplitude 0db */ + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80); + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_DOWN | + PWD_DACL_ON | PWD_DACR_ON); + snd_soc_component_update_bits(component, RK817_CODEC_DDAC_MUTE_MIXCTL, + DACMT_ENABLE, DACMT_DISABLE); + break; + case SPK_HP: + /* HP_CP_EN , CP 2.3V */ + snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11); + /* power on HP two stage opamp ,HP amplitude 0db */ + snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80); + + /* power on dac ibias/l/r */ + snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_ON | PWD_DACD_ON | + PWD_DACL_ON | PWD_DACR_ON); + + if (!rk817->use_ext_amplifier) { + /* CLASS D mode */ + snd_soc_component_write(component, RK817_CODEC_DDAC_MUTE_MIXCTL, 0x10); + /* CLASS D enable */ + snd_soc_component_write(component, RK817_CODEC_ACLASSD_CFG1, 0xa5); + /* restart CLASS D, OCPP/N */ + snd_soc_component_write(component, RK817_CODEC_ACLASSD_CFG2, 0xc4); + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk817_probe(struct snd_soc_component *component) +{ + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + + if (!rk817) { + dev_err(component->dev, "%s : rk817 priv is NULL!\n", + __func__); + return -EINVAL; + } + snd_soc_component_init_regmap(component, rk817->regmap); + rk817->component = component; + rk817->playback_path = OFF; + rk817->capture_path = MIC_OFF; + + rk817_reset(component); + snd_soc_add_component_controls(component, rk817_snd_path_controls, + ARRAY_SIZE(rk817_snd_path_controls)); + + snd_soc_dapm_new_controls(dapm, rk817_dapm_widgets, + ARRAY_SIZE(rk817_dapm_widgets)); + return 0; +} + +/* power down chip */ +static void rk817_remove(struct snd_soc_component *component) +{ + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); + + if (!rk817) { + dev_err(component->dev, "%s : rk817 is NULL\n", __func__); + return; + } + + rk817_codec_power_down(component, RK817_CODEC_ALL); + snd_soc_component_exit_regmap(component); + mdelay(10); + +} + +static const struct snd_soc_component_driver soc_codec_dev_rk817 = { + .probe = rk817_probe, + .remove = rk817_remove, + .suspend = rk817_suspend, + .resume = rk817_resume, + .idle_bias_on = 1, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, + .controls = rk817_dac_controls, + .num_controls = ARRAY_SIZE(rk817_dac_controls), +}; + +static int rk817_codec_parse_dt_property(struct device *dev, + struct rk817_codec_priv *rk817) +{ + struct device_node *node = dev->parent->of_node; + int ret; + + if (!node) { + dev_err(dev, "%s() dev->parent->of_node is NULL\n", + __func__); + return -ENODEV; + } + + node = of_get_child_by_name(dev->parent->of_node, "codec"); + if (!node) { + dev_err(dev, "%s() Can not get child: codec\n", + __func__); + return -ENODEV; + } + + rk817->hp_ctl_gpio = devm_gpiod_get_optional(dev, "hp-ctl", + GPIOD_OUT_LOW); + + rk817->spk_ctl_gpio = devm_gpiod_get_optional(dev, "spk-ctl", + GPIOD_OUT_LOW); + + ret = of_property_read_u32(node, "spk-mute-delay-ms", + &rk817->spk_mute_delay); + if (ret < 0) { + rk817->spk_mute_delay = 0; + } + + ret = of_property_read_u32(node, "hp-mute-delay-ms", + &rk817->hp_mute_delay); + if (ret < 0) { + rk817->hp_mute_delay = 0; + } + + ret = of_property_read_u32(node, "spk-volume", &rk817->spk_volume); + if (ret < 0) { + rk817->spk_volume = OUT_VOLUME; + } + if (rk817->spk_volume < 3) + rk817->spk_volume = 3; + + ret = of_property_read_u32(node, "hp-volume", + &rk817->hp_volume); + if (ret < 0) { + rk817->hp_volume = OUT_VOLUME; + } + if (rk817->hp_volume < 3) + rk817->hp_volume = 3; + + ret = of_property_read_u32(node, "capture-volume", + &rk817->capture_volume); + if (ret < 0) { + rk817->capture_volume = CAPTURE_VOLUME; + } + + rk817->mic_in_differential = + of_property_read_bool(node, "mic-in-differential"); + + rk817->pdmdata_out_enable = + of_property_read_bool(node, "pdmdata-out-enable"); + + rk817->use_ext_amplifier = + of_property_read_bool(node, "use-ext-amplifier"); + + rk817->adc_for_loopback = + of_property_read_bool(node, "adc-for-loopback"); + + return 0; +} + +static const struct regmap_config rk817_codec_regmap_config = { + .name = "rk817-codec", + .reg_bits = 8, + .val_bits = 8, + .reg_stride = 1, + .max_register = 0x4f, + .cache_type = REGCACHE_NONE, + .volatile_reg = rk817_volatile_register, + .writeable_reg = rk817_codec_register, + .readable_reg = rk817_codec_register, + .reg_defaults = rk817_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(rk817_reg_defaults), +}; + +static int rk817_platform_probe(struct platform_device *pdev) +{ + struct rk808 *rk817 = dev_get_drvdata(pdev->dev.parent); + struct rk817_codec_priv *rk817_codec_data; + int ret; + + if (!rk817) { + dev_err(&pdev->dev, "%s : rk817 is NULL\n", __func__); + return -EINVAL; + } + + rk817_codec_data = devm_kzalloc(&pdev->dev, + sizeof(struct rk817_codec_priv), + GFP_KERNEL); + if (!rk817_codec_data) + return -ENOMEM; + + platform_set_drvdata(pdev, rk817_codec_data); + + ret = rk817_codec_parse_dt_property(&pdev->dev, rk817_codec_data); + if (ret < 0) { + dev_err(&pdev->dev, "%s() parse device tree property error %d\n", + __func__, ret); + goto err_; + } + + rk817_codec_data->regmap = devm_regmap_init_i2c(rk817->i2c, + &rk817_codec_regmap_config); + if (IS_ERR(rk817_codec_data->regmap)) { + ret = PTR_ERR(rk817_codec_data->regmap); + dev_err(&pdev->dev, "failed to allocate register map: %d\n", + ret); + goto err_; + } + + rk817_codec_data->mclk = devm_clk_get(&pdev->dev, "mclk"); + if (IS_ERR(rk817_codec_data->mclk)) { + dev_err(&pdev->dev, "Unable to get mclk\n"); + ret = -ENXIO; + goto err_; + } + + ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817, + rk817_dai, ARRAY_SIZE(rk817_dai)); + if (ret < 0) { + dev_err(&pdev->dev, "%s() register codec error %d\n", + __func__, ret); + goto err_; + } + + return 0; +err_: + + return ret; +} + +static int rk817_platform_remove(struct platform_device *pdev) +{ + snd_soc_unregister_component(&pdev->dev); + + return 0; +} + +static void rk817_platform_shutdown(struct platform_device *pdev) +{ + struct rk817_codec_priv *rk817 = dev_get_drvdata(&pdev->dev); + + if (rk817 && rk817->component) + rk817_codec_power_down(rk817->component, RK817_CODEC_ALL); +} + +static const struct of_device_id rk817_codec_dt_ids[] = { + { .compatible = "rockchip,rk817-codec" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rk817_codec_dt_ids); + +static struct platform_driver rk817_codec_driver = { + .driver = { + .name = "rk817-codec", + .of_match_table = rk817_codec_dt_ids, + }, + .probe = rk817_platform_probe, + .remove = rk817_platform_remove, + .shutdown = rk817_platform_shutdown, +}; + +module_platform_driver(rk817_codec_driver); + +MODULE_DESCRIPTION("ASoC RK817 codec driver"); +MODULE_AUTHOR("binyuan <kevan.lan(a)rock-chips.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/rk817_codec.h b/sound/soc/codecs/rk817_codec.h new file mode 100644 index 000000000000..3f13eade80b3 --- /dev/null +++ b/sound/soc/codecs/rk817_codec.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2018 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __RK817_CODEC_H__ +#define __RK817_CODEC_H__ + +/* codec register */ +#define RK817_CODEC_BASE 0x0000 + +#define RK817_CODEC_DTOP_VUCTL (RK817_CODEC_BASE + 0x12) +#define RK817_CODEC_DTOP_VUCTIME (RK817_CODEC_BASE + 0x13) +#define RK817_CODEC_DTOP_LPT_SRST (RK817_CODEC_BASE + 0x14) +#define RK817_CODEC_DTOP_DIGEN_CLKE (RK817_CODEC_BASE + 0x15) +#define RK817_CODEC_AREF_RTCFG0 (RK817_CODEC_BASE + 0x16) +#define RK817_CODEC_AREF_RTCFG1 (RK817_CODEC_BASE + 0x17) +#define RK817_CODEC_AADC_CFG0 (RK817_CODEC_BASE + 0x18) +#define RK817_CODEC_AADC_CFG1 (RK817_CODEC_BASE + 0x19) +#define RK817_CODEC_DADC_VOLL (RK817_CODEC_BASE + 0x1a) +#define RK817_CODEC_DADC_VOLR (RK817_CODEC_BASE + 0x1b) +#define RK817_CODEC_DADC_SR_ACL0 (RK817_CODEC_BASE + 0x1e) +#define RK817_CODEC_DADC_ALC1 (RK817_CODEC_BASE + 0x1f) +#define RK817_CODEC_DADC_ALC2 (RK817_CODEC_BASE + 0x20) +#define RK817_CODEC_DADC_NG (RK817_CODEC_BASE + 0x21) +#define RK817_CODEC_DADC_HPF (RK817_CODEC_BASE + 0x22) +#define RK817_CODEC_DADC_RVOLL (RK817_CODEC_BASE + 0x23) +#define RK817_CODEC_DADC_RVOLR (RK817_CODEC_BASE + 0x24) +#define RK817_CODEC_AMIC_CFG0 (RK817_CODEC_BASE + 0x27) +#define RK817_CODEC_AMIC_CFG1 (RK817_CODEC_BASE + 0x28) +#define RK817_CODEC_DMIC_PGA_GAIN (RK817_CODEC_BASE + 0x29) +#define RK817_CODEC_DMIC_LMT1 (RK817_CODEC_BASE + 0x2a) +#define RK817_CODEC_DMIC_LMT2 (RK817_CODEC_BASE + 0x2b) +#define RK817_CODEC_DMIC_NG1 (RK817_CODEC_BASE + 0x2c) +#define RK817_CODEC_DMIC_NG2 (RK817_CODEC_BASE + 0x2d) +#define RK817_CODEC_ADAC_CFG0 (RK817_CODEC_BASE + 0x2e) +#define RK817_CODEC_ADAC_CFG1 (RK817_CODEC_BASE + 0x2f) +#define RK817_CODEC_DDAC_POPD_DACST (RK817_CODEC_BASE + 0x30) +#define RK817_CODEC_DDAC_VOLL (RK817_CODEC_BASE + 0x31) +#define RK817_CODEC_DDAC_VOLR (RK817_CODEC_BASE + 0x32) +#define RK817_CODEC_DDAC_SR_LMT0 (RK817_CODEC_BASE + 0x35) +#define RK817_CODEC_DDAC_LMT1 (RK817_CODEC_BASE + 0x36) +#define RK817_CODEC_DDAC_LMT2 (RK817_CODEC_BASE + 0x37) +#define RK817_CODEC_DDAC_MUTE_MIXCTL (RK817_CODEC_BASE + 0x38) +#define RK817_CODEC_DDAC_RVOLL (RK817_CODEC_BASE + 0x39) +#define RK817_CODEC_DDAC_RVOLR (RK817_CODEC_BASE + 0x3a) +#define RK817_CODEC_AHP_ANTI0 (RK817_CODEC_BASE + 0x3b) +#define RK817_CODEC_AHP_ANTI1 (RK817_CODEC_BASE + 0x3c) +#define RK817_CODEC_AHP_CFG0 (RK817_CODEC_BASE + 0x3d) +#define RK817_CODEC_AHP_CFG1 (RK817_CODEC_BASE + 0x3e) +#define RK817_CODEC_AHP_CP (RK817_CODEC_BASE + 0x3f) +#define RK817_CODEC_ACLASSD_CFG1 (RK817_CODEC_BASE + 0x40) +#define RK817_CODEC_ACLASSD_CFG2 (RK817_CODEC_BASE + 0x41) +#define RK817_CODEC_APLL_CFG0 (RK817_CODEC_BASE + 0x42) +#define RK817_CODEC_APLL_CFG1 (RK817_CODEC_BASE + 0x43) +#define RK817_CODEC_APLL_CFG2 (RK817_CODEC_BASE + 0x44) +#define RK817_CODEC_APLL_CFG3 (RK817_CODEC_BASE + 0x45) +#define RK817_CODEC_APLL_CFG4 (RK817_CODEC_BASE + 0x46) +#define RK817_CODEC_APLL_CFG5 (RK817_CODEC_BASE + 0x47) +#define RK817_CODEC_DI2S_CKM (RK817_CODEC_BASE + 0x48) +#define RK817_CODEC_DI2S_RSD (RK817_CODEC_BASE + 0x49) +#define RK817_CODEC_DI2S_RXCR1 (RK817_CODEC_BASE + 0x4a) +#define RK817_CODEC_DI2S_RXCR2 (RK817_CODEC_BASE + 0x4b) +#define RK817_CODEC_DI2S_RXCMD_TSD (RK817_CODEC_BASE + 0x4c) +#define RK817_CODEC_DI2S_TXCR1 (RK817_CODEC_BASE + 0x4d) +#define RK817_CODEC_DI2S_TXCR2 (RK817_CODEC_BASE + 0x4e) +#define RK817_CODEC_DI2S_TXCR3_TXCMD (RK817_CODEC_BASE + 0x4f) + +/* RK817_CODEC_DTOP_DIGEN_CLKE */ +#define ADC_DIG_CLK_MASK (0xf << 4) +#define ADC_DIG_CLK_SFT 4 +#define ADC_DIG_CLK_DIS (0x0 << 4) +#define ADC_DIG_CLK_EN (0xf << 4) + +#define DAC_DIG_CLK_MASK (0xf << 0) +#define DAC_DIG_CLK_SFT 0 +#define DAC_DIG_CLK_DIS (0x0 << 0) +#define DAC_DIG_CLK_EN (0xf << 0) + +/* RK817_CODEC_APLL_CFG5 */ +#define PLL_PW_DOWN (0x01 << 0) +#define PLL_PW_UP (0x00 << 0) + +/* RK817_CODEC_DI2S_CKM */ +#define PDM_EN_MASK (0x1 << 3) +#define PDM_EN_SFT 3 +#define PDM_EN_DISABLE (0x0 << 3) +#define PDM_EN_ENABLE (0x1 << 3) + +#define SCK_EN_ENABLE (0x1 << 2) +#define SCK_EN_DISABLE (0x0 << 2) + +#define RK817_I2S_MODE_MASK (0x1 << 0) +#define RK817_I2S_MODE_SFT 0 +#define RK817_I2S_MODE_MST (0x1 << 0) +#define RK817_I2S_MODE_SLV (0x0 << 0) + +/* RK817_CODEC_DDAC_MUTE_MIXCTL */ +#define DACMT_ENABLE (0x1 << 0) +#define DACMT_DISABLE (0x0 << 0) + +/* RK817_CODEC_DI2S_RXCR2 */ +#define VDW_RX_24BITS (0x17) +#define VDW_RX_16BITS (0x0f) +/* RK817_CODEC_DI2S_TXCR2 */ +#define VDW_TX_24BITS (0x17) +#define VDW_TX_16BITS (0x0f) + +/* RK817_CODEC_AHP_CFG1 */ +#define HP_ANTIPOP_ENABLE (0x1 << 4) +#define HP_ANTIPOP_DISABLE (0x0 << 4) + +/* RK817_CODEC_ADAC_CFG1 */ +#define PWD_DACBIAS_MASK (0x1 << 3) +#define PWD_DACBIAS_SFT 3 +#define PWD_DACBIAS_DOWN (0x1 << 3) +#define PWD_DACBIAS_ON (0x0 << 3) + +#define PWD_DACD_MASK (0x1 << 2) +#define PWD_DACD_SFT 2 +#define PWD_DACD_DOWN (0x1 << 2) +#define PWD_DACD_ON (0x0 << 2) + +#define PWD_DACL_MASK (0x1 << 1) +#define PWD_DACL_SFT 1 +#define PWD_DACL_DOWN (0x1 << 1) +#define PWD_DACL_ON (0x0 << 1) + +#define PWD_DACR_MASK (0x1 << 0) +#define PWD_DACR_SFT 0 +#define PWD_DACR_DOWN (0x1 << 0) +#define PWD_DACR_ON (0x0 << 0) + +/* RK817_CODEC_AADC_CFG0 */ +#define ADC_L_PWD_MASK (0x1 << 7) +#define ADC_L_PWD_SFT 7 +#define ADC_L_PWD_DIS (0x0 << 7) +#define ADC_L_PWD_EN (0x1 << 7) + +#define ADC_R_PWD_MASK (0x1 << 6) +#define ADC_R_PWD_SFT 6 +#define ADC_R_PWD_DIS (0x0 << 6) +#define ADC_R_PWD_EN (0x1 << 6) + +/* RK817_CODEC_AMIC_CFG0 */ +#define MIC_DIFF_MASK (0x1 << 7) +#define MIC_DIFF_SFT 7 +#define MIC_DIFF_DIS (0x0 << 7) +#define MIC_DIFF_EN (0x1 << 7) + +#define PWD_PGA_L_MASK (0x1 << 5) +#define PWD_PGA_L_SFT 5 +#define PWD_PGA_L_DIS (0x0 << 5) +#define PWD_PGA_L_EN (0x1 << 5) + +#define PWD_PGA_R_MASK (0x1 << 4) +#define PWD_PGA_R_SFT 4 +#define PWD_PGA_R_DIS (0x0 << 4) +#define PWD_PGA_R_EN (0x1 << 4) + +enum { + RK817_HIFI, +}; + +enum { + OFF, + SPK_PATH, + HP_PATH, + SPK_HP, +}; + +enum { + MIC_OFF, + MIC, +}; + +struct rk817_reg_val_typ { + unsigned int reg; + unsigned int value; +}; + +struct rk817_init_bit_typ { + unsigned int reg; + unsigned int power_bit; + unsigned int init_bit; +}; + +#endif /* __RK817_CODEC_H__ */ -- 2.25.1

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[PATCH v2 0/3] ASoC: sdm845: array out of bound issues
by Srinivas Kandagatla 09 Mar '21

09 Mar '21

During testing John Stultz and Amit reported few array our bound issues after enabling bound sanitizer This patch series attempts to fix those! changes since v1: - make sure the wcd is not de-referenced without intialization Srinivas Kandagatla (3): ASoC: qcom: sdm845: Fix array out of bounds access ASoC: qcom: sdm845: Fix array out of range on rx slim channels ASoC: codecs: wcd934x: add a sanity check in set channel map sound/soc/codecs/wcd934x.c | 6 ++++++ sound/soc/qcom/sdm845.c | 6 +++--- 2 files changed, 9 insertions(+), 3 deletions(-) -- 2.21.0

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[PATCH v3 00/15] Report jack and button detection + Capture Support
by Lucas Tanure 09 Mar '21

09 Mar '21

Hi All, Here is a patch series for reporting to user space jack and button events and add the support for Capture. With some cleanups and fixes along the way. Regards, Lucas Tanure Lucas Tanure (12): ASoC: cs42l42: Fix Bitclock polarity inversion ASoC: cs42l42: Fix channel width support ASoC: cs42l42: Fix mixer volume control ASoC: cs42l42: Don't enable/disable regulator at Bias Level ASoC: cs42l42: Always wait at least 3ms after reset ASoC: cs42l42: Remove power if the driver is being removed ASoC: cs42l42: Disable regulators if probe fails ASoC: cs42l42: Provide finer control on playback path ASoC: cs42l42: Set clock source for both ways of stream ASoC: cs42l42: Add Capture Support ASoC: cs42l42: Report jack and button detection ASoC: cs42l42: Use bclk from hw_params if set_sysclk was not called Richard Fitzgerald (3): ASoC: cs42l42: Wait at least 150us after writing SCLK_PRESENT ASoC: cs42l42: Only start PLL if it is needed ASoC: cs42l42: Wait for PLL to lock before switching to it sound/soc/codecs/cs42l42.c | 435 +++++++++++++++++++++---------------- sound/soc/codecs/cs42l42.h | 41 +++- 2 files changed, 282 insertions(+), 194 deletions(-) -- 2.30.1

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[PATCH] ASoC: SOF: intel: fix wrong poll bits in dsp power down
by Pierre-Louis Bossart 09 Mar '21

09 Mar '21

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> The ADSPCS_SPA is Set Power Active bit. To check if DSP is powered down, we need to check ADSPCS_CPA, the Current Power Active bit. Fixes: 747503b1813a3 ("ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations") Reviewed-by: Rander Wang <rander.wang(a)intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> --- sound/soc/sof/intel/hda-dsp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/sof/intel/hda-dsp.c b/sound/soc/sof/intel/hda-dsp.c index 9900a058ba6e..6e24e1cb13f9 100644 --- a/sound/soc/sof/intel/hda-dsp.c +++ b/sound/soc/sof/intel/hda-dsp.c @@ -207,7 +207,7 @@ int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask) ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, adspcs, - !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)), + !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)), HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); if (ret < 0) -- 2.25.1

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