May 2024 - Alsa-devel - mailman.alsa-project.org

Burst in sound UFX+ AVLinux MXE and Ubuntu studio
by Mika Kilpi 21 May '24

21 May '24

Hello, Can you please take a look at my problem that I have written about on the RME forum? https://forum.rme-audio.de/viewtopic.php?id=39385 Kind Regards Mika Kilpi Sent with [Proton Mail](https://proton.me/) secure email.

1 0

[PATCH] ASoC: dt-bindings: stm32: Ensure compatible pattern matches whole string
by Rob Herring (Arm) 21 May '24

21 May '24

The compatible pattern "st,stm32-sai-sub-[ab]" is missing starting and ending anchors, so any prefix and/or suffix would still be valid. This also fixes a warning on the example: Documentation/devicetree/bindings/sound/st,stm32-sai.example.dtb: /example-0/sai@4400b000/audio-controller@4400b004: failed to match any schema with compatible: ['st,stm32-sai-sub-a'] Signed-off-by: Rob Herring (Arm) <robh(a)kernel.org> --- Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index 59df8a832310..f555ccd6b00a 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -68,7 +68,7 @@ patternProperties: properties: compatible: description: Compatible for SAI sub-block A or B. - pattern: "st,stm32-sai-sub-[ab]" + pattern: "^st,stm32-sai-sub-[ab]$" "#sound-dai-cells": const: 0 -- 2.43.0

3 2

[PATCH v4] ASoC: rt1320: Add RT1320 SDCA vendor-specific driver
by shumingf＠realtek.com 21 May '24

21 May '24

From: Shuming Fan <shumingf(a)realtek.com> This is the initial amplifier driver for rt1320. Signed-off-by: Shuming Fan <shumingf(a)realtek.com> -- v2: add Capture DAI for AEC feedback v3: add some comments for blind writes/patch_code/calling sdw_slave_read_prop add class id 1 v4: add comments for different class id --- sound/soc/codecs/Kconfig | 7 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt1320-sdw.c | 2260 +++++++++++++++++++++++++++++++++ sound/soc/codecs/rt1320-sdw.h | 94 ++ 4 files changed, 2363 insertions(+) create mode 100644 sound/soc/codecs/rt1320-sdw.c create mode 100644 sound/soc/codecs/rt1320-sdw.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 4afc43d3f71f..7502581d1631 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -222,6 +222,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_RT1308_SDW imply SND_SOC_RT1316_SDW imply SND_SOC_RT1318_SDW + imply SND_SOC_RT1320_SDW imply SND_SOC_RT9120 imply SND_SOC_RTQ9128 imply SND_SOC_SDW_MOCKUP @@ -1575,6 +1576,12 @@ config SND_SOC_RT1318_SDW depends on SOUNDWIRE select REGMAP_SOUNDWIRE +config SND_SOC_RT1320_SDW + tristate "Realtek RT1320 Codec - SDW" + depends on SOUNDWIRE + select REGMAP_SOUNDWIRE + select REGMAP_SOUNDWIRE_MBQ + config SND_SOC_RT5514 tristate depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index b4df22186e25..f9eb7c073a00 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -222,6 +222,7 @@ snd-soc-rt1308-y := rt1308.o snd-soc-rt1308-sdw-y := rt1308-sdw.o snd-soc-rt1316-sdw-y := rt1316-sdw.o snd-soc-rt1318-sdw-y := rt1318-sdw.o +snd-soc-rt1320-sdw-y := rt1320-sdw.o snd-soc-rt274-y := rt274.o snd-soc-rt286-y := rt286.o snd-soc-rt298-y := rt298.o @@ -614,6 +615,7 @@ obj-$(CONFIG_SND_SOC_RT1308) += snd-soc-rt1308.o obj-$(CONFIG_SND_SOC_RT1308_SDW) += snd-soc-rt1308-sdw.o obj-$(CONFIG_SND_SOC_RT1316_SDW) += snd-soc-rt1316-sdw.o obj-$(CONFIG_SND_SOC_RT1318_SDW) += snd-soc-rt1318-sdw.o +obj-$(CONFIG_SND_SOC_RT1320_SDW) += snd-soc-rt1320-sdw.o obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o diff --git a/sound/soc/codecs/rt1320-sdw.c b/sound/soc/codecs/rt1320-sdw.c new file mode 100644 index 000000000000..2916fa77b791 --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.c @@ -0,0 +1,2260 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver +// +// Copyright(c) 2024 Realtek Semiconductor Corp. +// +// +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/pm_runtime.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include <linux/dmi.h> +#include <linux/firmware.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/sdw.h> +#include "rt1320-sdw.h" + +/* + * The 'blind writes' is an SDCA term to deal with platform-specific initialization. + * It might include vendor-specific or SDCA control registers. + */ +static const struct reg_sequence rt1320_blind_write[] = { + { 0xc003, 0xe0 }, + { 0xc01b, 0xfc }, + { 0xc5c3, 0xf2 }, + { 0xc5c2, 0x00 }, + { 0xc5c6, 0x10 }, + { 0xc5c4, 0x12 }, + { 0xc5c8, 0x03 }, + { 0xc5d8, 0x0a }, + { 0xc5f7, 0x22 }, + { 0xc5f6, 0x22 }, + { 0xc5d0, 0x0f }, + { 0xc5d1, 0x89 }, + { 0xc057, 0x51 }, + { 0xc054, 0x35 }, + { 0xc053, 0x55 }, + { 0xc052, 0x55 }, + { 0xc051, 0x13 }, + { 0xc050, 0x15 }, + { 0xc060, 0x77 }, + { 0xc061, 0x55 }, + { 0xc063, 0x55 }, + { 0xc065, 0xa5 }, + { 0xc06b, 0x0a }, + { 0xca05, 0xd6 }, + { 0xca25, 0xd6 }, + { 0xcd00, 0x05 }, + { 0xc604, 0x40 }, + { 0xc609, 0x40 }, + { 0xc046, 0xff }, + { 0xc045, 0xff }, + { 0xc044, 0xff }, + { 0xc043, 0xff }, + { 0xc042, 0xff }, + { 0xc041, 0xff }, + { 0xc040, 0xff }, + { 0xcc10, 0x01 }, + { 0xc700, 0xf0 }, + { 0xc701, 0x13 }, + { 0xc901, 0x04 }, + { 0xc900, 0x73 }, + { 0xde03, 0x05 }, + { 0xdd0b, 0x0d }, + { 0xdd0a, 0xff }, + { 0xdd09, 0x0d }, + { 0xdd08, 0xff }, + { 0xc570, 0x08 }, + { 0xe803, 0xbe }, + { 0xc003, 0xc0 }, + { 0xc081, 0xfe }, + { 0xce31, 0x0d }, + { 0xce30, 0xae }, + { 0xce37, 0x0b }, + { 0xce36, 0xd2 }, + { 0xce39, 0x04 }, + { 0xce38, 0x80 }, + { 0xce3f, 0x00 }, + { 0xce3e, 0x00 }, + { 0xd470, 0x8b }, + { 0xd471, 0x18 }, + { 0xc019, 0x10 }, + { 0xd487, 0x3f }, + { 0xd486, 0xc3 }, +}; + +/* + * The 'patch code' is written to the patch code area. + * The patch code area is used for SDCA register expansion flexibility. + */ +static const struct reg_sequence rt1320_patch_code_write[] = { + { 0x10007000, 0x37 }, + { 0x10007001, 0x77 }, + { 0x10007002, 0x00 }, + { 0x10007003, 0x10 }, + { 0x10007004, 0xb7 }, + { 0x10007005, 0xe7 }, + { 0x10007006, 0x00 }, + { 0x10007007, 0x10 }, + { 0x10007008, 0x13 }, + { 0x10007009, 0x07 }, + { 0x1000700a, 0x07 }, + { 0x1000700b, 0x40 }, + { 0x1000700c, 0x23 }, + { 0x1000700d, 0xae }, + { 0x1000700e, 0xe7 }, + { 0x1000700f, 0xda }, + { 0x10007010, 0x37 }, + { 0x10007011, 0x77 }, + { 0x10007012, 0x00 }, + { 0x10007013, 0x10 }, + { 0x10007014, 0x13 }, + { 0x10007015, 0x07 }, + { 0x10007016, 0x47 }, + { 0x10007017, 0x61 }, + { 0x10007018, 0x23 }, + { 0x10007019, 0xa4 }, + { 0x1000701a, 0xe7 }, + { 0x1000701b, 0xde }, + { 0x1000701c, 0x37 }, + { 0x1000701d, 0x77 }, + { 0x1000701e, 0x00 }, + { 0x1000701f, 0x10 }, + { 0x10007020, 0x13 }, + { 0x10007021, 0x07 }, + { 0x10007022, 0x07 }, + { 0x10007023, 0x52 }, + { 0x10007024, 0x23 }, + { 0x10007025, 0xae }, + { 0x10007026, 0xe7 }, + { 0x10007027, 0xde }, + { 0x10007028, 0x37 }, + { 0x10007029, 0x77 }, + { 0x1000702a, 0x00 }, + { 0x1000702b, 0x10 }, + { 0x1000702c, 0x13 }, + { 0x1000702d, 0x07 }, + { 0x1000702e, 0x47 }, + { 0x1000702f, 0x54 }, + { 0x10007030, 0x23 }, + { 0x10007031, 0xaa }, + { 0x10007032, 0xe7 }, + { 0x10007033, 0xe4 }, + { 0x10007034, 0x37 }, + { 0x10007035, 0x87 }, + { 0x10007036, 0x00 }, + { 0x10007037, 0x10 }, + { 0x10007038, 0x13 }, + { 0x10007039, 0x07 }, + { 0x1000703a, 0x47 }, + { 0x1000703b, 0x81 }, + { 0x1000703c, 0x23 }, + { 0x1000703d, 0xa2 }, + { 0x1000703e, 0xe7 }, + { 0x1000703f, 0xe8 }, + { 0x10007040, 0x23 }, + { 0x10007041, 0xa4 }, + { 0x10007042, 0xe7 }, + { 0x10007043, 0xe8 }, + { 0x10007044, 0x37 }, + { 0x10007045, 0x77 }, + { 0x10007046, 0x00 }, + { 0x10007047, 0x10 }, + { 0x10007048, 0x13 }, + { 0x10007049, 0x07 }, + { 0x1000704a, 0x07 }, + { 0x1000704b, 0x59 }, + { 0x1000704c, 0x23 }, + { 0x1000704d, 0xa8 }, + { 0x1000704e, 0xe7 }, + { 0x1000704f, 0xea }, + { 0x10007050, 0x37 }, + { 0x10007051, 0x77 }, + { 0x10007052, 0x00 }, + { 0x10007053, 0x10 }, + { 0x10007054, 0x13 }, + { 0x10007055, 0x07 }, + { 0x10007056, 0x07 }, + { 0x10007057, 0x78 }, + { 0x10007058, 0x23 }, + { 0x10007059, 0xa6 }, + { 0x1000705a, 0xe7 }, + { 0x1000705b, 0xec }, + { 0x1000705c, 0x67 }, + { 0x1000705d, 0x80 }, + { 0x1000705e, 0x00 }, + { 0x1000705f, 0x00 }, + { 0x10007400, 0x37 }, + { 0x10007401, 0xd7 }, + { 0x10007402, 0x00 }, + { 0x10007403, 0x00 }, + { 0x10007404, 0x83 }, + { 0x10007405, 0x27 }, + { 0x10007406, 0x47 }, + { 0x10007407, 0x56 }, + { 0x10007408, 0xb7 }, + { 0x10007409, 0x06 }, + { 0x1000740a, 0x00 }, + { 0x1000740b, 0x02 }, + { 0x1000740c, 0xb3 }, + { 0x1000740d, 0xf7 }, + { 0x1000740e, 0xd7 }, + { 0x1000740f, 0x00 }, + { 0x10007410, 0x63 }, + { 0x10007411, 0x8a }, + { 0x10007412, 0x07 }, + { 0x10007413, 0x00 }, + { 0x10007414, 0x93 }, + { 0x10007415, 0x06 }, + { 0x10007416, 0x10 }, + { 0x10007417, 0x00 }, + { 0x10007418, 0x23 }, + { 0x10007419, 0x83 }, + { 0x1000741a, 0xd1 }, + { 0x1000741b, 0x44 }, + { 0x1000741c, 0x93 }, + { 0x1000741d, 0x07 }, + { 0x1000741e, 0xf0 }, + { 0x1000741f, 0xff }, + { 0x10007420, 0x23 }, + { 0x10007421, 0x22 }, + { 0x10007422, 0xf7 }, + { 0x10007423, 0x56 }, + { 0x10007424, 0x37 }, + { 0x10007425, 0xd7 }, + { 0x10007426, 0x00 }, + { 0x10007427, 0x00 }, + { 0x10007428, 0x83 }, + { 0x10007429, 0x27 }, + { 0x1000742a, 0x47 }, + { 0x1000742b, 0x58 }, + { 0x1000742c, 0x93 }, + { 0x1000742d, 0xf7 }, + { 0x1000742e, 0x17 }, + { 0x1000742f, 0x00 }, + { 0x10007430, 0x63 }, + { 0x10007431, 0x86 }, + { 0x10007432, 0x07 }, + { 0x10007433, 0x00 }, + { 0x10007434, 0x93 }, + { 0x10007435, 0x07 }, + { 0x10007436, 0x10 }, + { 0x10007437, 0x00 }, + { 0x10007438, 0x23 }, + { 0x10007439, 0x22 }, + { 0x1000743a, 0xf7 }, + { 0x1000743b, 0x58 }, + { 0x1000743c, 0xb7 }, + { 0x1000743d, 0xd7 }, + { 0x1000743e, 0x00 }, + { 0x1000743f, 0x00 }, + { 0x10007440, 0x03 }, + { 0x10007441, 0xa7 }, + { 0x10007442, 0x47 }, + { 0x10007443, 0x58 }, + { 0x10007444, 0xb7 }, + { 0x10007445, 0x07 }, + { 0x10007446, 0x00 }, + { 0x10007447, 0x04 }, + { 0x10007448, 0x33 }, + { 0x10007449, 0x77 }, + { 0x1000744a, 0xf7 }, + { 0x1000744b, 0x00 }, + { 0x1000744c, 0x93 }, + { 0x1000744d, 0x07 }, + { 0x1000744e, 0x00 }, + { 0x1000744f, 0x00 }, + { 0x10007450, 0x63 }, + { 0x10007451, 0x0e }, + { 0x10007452, 0x07 }, + { 0x10007453, 0x04 }, + { 0x10007454, 0x37 }, + { 0x10007455, 0x07 }, + { 0x10007456, 0x00 }, + { 0x10007457, 0x11 }, + { 0x10007458, 0x03 }, + { 0x10007459, 0x47 }, + { 0x1000745a, 0x87 }, + { 0x1000745b, 0x0e }, + { 0x1000745c, 0x93 }, + { 0x1000745d, 0x06 }, + { 0x1000745e, 0x40 }, + { 0x1000745f, 0x00 }, + { 0x10007460, 0x13 }, + { 0x10007461, 0x77 }, + { 0x10007462, 0xf7 }, + { 0x10007463, 0x0f }, + { 0x10007464, 0x63 }, + { 0x10007465, 0x02 }, + { 0x10007466, 0xd7 }, + { 0x10007467, 0x0a }, + { 0x10007468, 0x93 }, + { 0x10007469, 0x06 }, + { 0x1000746a, 0x70 }, + { 0x1000746b, 0x00 }, + { 0x1000746c, 0x63 }, + { 0x1000746d, 0x10 }, + { 0x1000746e, 0xd7 }, + { 0x1000746f, 0x04 }, + { 0x10007470, 0x93 }, + { 0x10007471, 0x07 }, + { 0x10007472, 0x60 }, + { 0x10007473, 0x06 }, + { 0x10007474, 0x37 }, + { 0x10007475, 0xd7 }, + { 0x10007476, 0x00 }, + { 0x10007477, 0x00 }, + { 0x10007478, 0x83 }, + { 0x10007479, 0x46 }, + { 0x1000747a, 0x77 }, + { 0x1000747b, 0xa6 }, + { 0x1000747c, 0x93 }, + { 0x1000747d, 0xe6 }, + { 0x1000747e, 0x06 }, + { 0x1000747f, 0xf8 }, + { 0x10007480, 0x93 }, + { 0x10007481, 0xf6 }, + { 0x10007482, 0xf6 }, + { 0x10007483, 0x0f }, + { 0x10007484, 0xa3 }, + { 0x10007485, 0x03 }, + { 0x10007486, 0xd7 }, + { 0x10007487, 0xa6 }, + { 0x10007488, 0x83 }, + { 0x10007489, 0x46 }, + { 0x1000748a, 0x77 }, + { 0x1000748b, 0xa8 }, + { 0x1000748c, 0x93 }, + { 0x1000748d, 0xe6 }, + { 0x1000748e, 0x06 }, + { 0x1000748f, 0xf8 }, + { 0x10007490, 0x93 }, + { 0x10007491, 0xf6 }, + { 0x10007492, 0xf6 }, + { 0x10007493, 0x0f }, + { 0x10007494, 0xa3 }, + { 0x10007495, 0x03 }, + { 0x10007496, 0xd7 }, + { 0x10007497, 0xa8 }, + { 0x10007498, 0xb7 }, + { 0x10007499, 0xc6 }, + { 0x1000749a, 0x00 }, + { 0x1000749b, 0x00 }, + { 0x1000749c, 0x23 }, + { 0x1000749d, 0x84 }, + { 0x1000749e, 0xf6 }, + { 0x1000749f, 0x06 }, + { 0x100074a0, 0xa3 }, + { 0x100074a1, 0x84 }, + { 0x100074a2, 0xf6 }, + { 0x100074a3, 0x06 }, + { 0x100074a4, 0xb7 }, + { 0x100074a5, 0x06 }, + { 0x100074a6, 0x00 }, + { 0x100074a7, 0x04 }, + { 0x100074a8, 0x23 }, + { 0x100074a9, 0x22 }, + { 0x100074aa, 0xd7 }, + { 0x100074ab, 0x58 }, + { 0x100074ac, 0x37 }, + { 0x100074ad, 0xd7 }, + { 0x100074ae, 0x00 }, + { 0x100074af, 0x00 }, + { 0x100074b0, 0x03 }, + { 0x100074b1, 0x27 }, + { 0x100074b2, 0x47 }, + { 0x100074b3, 0x58 }, + { 0x100074b4, 0xb7 }, + { 0x100074b5, 0x06 }, + { 0x100074b6, 0x00 }, + { 0x100074b7, 0x08 }, + { 0x100074b8, 0x33 }, + { 0x100074b9, 0x77 }, + { 0x100074ba, 0xd7 }, + { 0x100074bb, 0x00 }, + { 0x100074bc, 0x63 }, + { 0x100074bd, 0x04 }, + { 0x100074be, 0x07 }, + { 0x100074bf, 0x04 }, + { 0x100074c0, 0x37 }, + { 0x100074c1, 0x07 }, + { 0x100074c2, 0x00 }, + { 0x100074c3, 0x11 }, + { 0x100074c4, 0x03 }, + { 0x100074c5, 0x47 }, + { 0x100074c6, 0xc7 }, + { 0x100074c7, 0x0e }, + { 0x100074c8, 0x93 }, + { 0x100074c9, 0x06 }, + { 0x100074ca, 0x40 }, + { 0x100074cb, 0x00 }, + { 0x100074cc, 0x13 }, + { 0x100074cd, 0x77 }, + { 0x100074ce, 0xf7 }, + { 0x100074cf, 0x0f }, + { 0x100074d0, 0x63 }, + { 0x100074d1, 0x00 }, + { 0x100074d2, 0xd7 }, + { 0x100074d3, 0x04 }, + { 0x100074d4, 0x93 }, + { 0x100074d5, 0x06 }, + { 0x100074d6, 0x70 }, + { 0x100074d7, 0x00 }, + { 0x100074d8, 0x63 }, + { 0x100074d9, 0x00 }, + { 0x100074da, 0xd7 }, + { 0x100074db, 0x04 }, + { 0x100074dc, 0x63 }, + { 0x100074dd, 0x84 }, + { 0x100074de, 0x07 }, + { 0x100074df, 0x02 }, + { 0x100074e0, 0xb7 }, + { 0x100074e1, 0xd6 }, + { 0x100074e2, 0x00 }, + { 0x100074e3, 0x00 }, + { 0x100074e4, 0x03 }, + { 0x100074e5, 0xc7 }, + { 0x100074e6, 0x56 }, + { 0x100074e7, 0xa4 }, + { 0x100074e8, 0x13 }, + { 0x100074e9, 0x67 }, + { 0x100074ea, 0x07 }, + { 0x100074eb, 0xf8 }, + { 0x100074ec, 0x13 }, + { 0x100074ed, 0x77 }, + { 0x100074ee, 0xf7 }, + { 0x100074ef, 0x0f }, + { 0x100074f0, 0xa3 }, + { 0x100074f1, 0x82 }, + { 0x100074f2, 0xe6 }, + { 0x100074f3, 0xa4 }, + { 0x100074f4, 0x37 }, + { 0x100074f5, 0xc7 }, + { 0x100074f6, 0x00 }, + { 0x100074f7, 0x00 }, + { 0x100074f8, 0x23 }, + { 0x100074f9, 0x02 }, + { 0x100074fa, 0xf7 }, + { 0x100074fb, 0x06 }, + { 0x100074fc, 0xb7 }, + { 0x100074fd, 0x07 }, + { 0x100074fe, 0x00 }, + { 0x100074ff, 0x08 }, + { 0x10007500, 0x23 }, + { 0x10007501, 0xa2 }, + { 0x10007502, 0xf6 }, + { 0x10007503, 0x58 }, + { 0x10007504, 0x67 }, + { 0x10007505, 0x80 }, + { 0x10007506, 0x00 }, + { 0x10007507, 0x00 }, + { 0x10007508, 0x93 }, + { 0x10007509, 0x07 }, + { 0x1000750a, 0x80 }, + { 0x1000750b, 0x08 }, + { 0x1000750c, 0x6f }, + { 0x1000750d, 0xf0 }, + { 0x1000750e, 0x9f }, + { 0x1000750f, 0xf6 }, + { 0x10007510, 0x93 }, + { 0x10007511, 0x07 }, + { 0x10007512, 0x80 }, + { 0x10007513, 0x08 }, + { 0x10007514, 0x6f }, + { 0x10007515, 0xf0 }, + { 0x10007516, 0xdf }, + { 0x10007517, 0xfc }, + { 0x10007518, 0x93 }, + { 0x10007519, 0x07 }, + { 0x1000751a, 0x60 }, + { 0x1000751b, 0x06 }, + { 0x1000751c, 0x6f }, + { 0x1000751d, 0xf0 }, + { 0x1000751e, 0x5f }, + { 0x1000751f, 0xfc }, + { 0x10007520, 0x37 }, + { 0x10007521, 0xd7 }, + { 0x10007522, 0x00 }, + { 0x10007523, 0x00 }, + { 0x10007524, 0x83 }, + { 0x10007525, 0x27 }, + { 0x10007526, 0x07 }, + { 0x10007527, 0x53 }, + { 0x10007528, 0xb7 }, + { 0x10007529, 0x06 }, + { 0x1000752a, 0x02 }, + { 0x1000752b, 0x00 }, + { 0x1000752c, 0xb3 }, + { 0x1000752d, 0xf7 }, + { 0x1000752e, 0xd7 }, + { 0x1000752f, 0x00 }, + { 0x10007530, 0x63 }, + { 0x10007531, 0x88 }, + { 0x10007532, 0x07 }, + { 0x10007533, 0x00 }, + { 0x10007534, 0x13 }, + { 0x10007535, 0x06 }, + { 0x10007536, 0xa0 }, + { 0x10007537, 0x05 }, + { 0x10007538, 0x23 }, + { 0x10007539, 0xa8 }, + { 0x1000753a, 0xc1 }, + { 0x1000753b, 0x56 }, + { 0x1000753c, 0x23 }, + { 0x1000753d, 0x28 }, + { 0x1000753e, 0xd7 }, + { 0x1000753f, 0x52 }, + { 0x10007540, 0x67 }, + { 0x10007541, 0x80 }, + { 0x10007542, 0x00 }, + { 0x10007543, 0x00 }, + { 0x10007544, 0x37 }, + { 0x10007545, 0xd7 }, + { 0x10007546, 0x00 }, + { 0x10007547, 0x10 }, + { 0x10007548, 0x83 }, + { 0x10007549, 0x47 }, + { 0x1000754a, 0x07 }, + { 0x1000754b, 0xd9 }, + { 0x1000754c, 0x93 }, + { 0x1000754d, 0x06 }, + { 0x1000754e, 0x20 }, + { 0x1000754f, 0x00 }, + { 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0x10007795, 0xc7 }, + { 0x10007796, 0xa1 }, + { 0x10007797, 0x40 }, + { 0x10007798, 0x63 }, + { 0x10007799, 0x9c }, + { 0x1000779a, 0x07 }, + { 0x1000779b, 0x06 }, + { 0x1000779c, 0x13 }, + { 0x1000779d, 0x01 }, + { 0x1000779e, 0x01 }, + { 0x1000779f, 0xff }, + { 0x100077a0, 0x23 }, + { 0x100077a1, 0x22 }, + { 0x100077a2, 0x91 }, + { 0x100077a3, 0x00 }, + { 0x100077a4, 0x23 }, + { 0x100077a5, 0x26 }, + { 0x100077a6, 0x11 }, + { 0x100077a7, 0x00 }, + { 0x100077a8, 0x23 }, + { 0x100077a9, 0x24 }, + { 0x100077aa, 0x81 }, + { 0x100077ab, 0x00 }, + { 0x100077ac, 0xb7 }, + { 0x100077ad, 0xc4 }, + { 0x100077ae, 0x00 }, + { 0x100077af, 0x00 }, + { 0x100077b0, 0x83 }, + { 0x100077b1, 0xc7 }, + { 0x100077b2, 0x04 }, + { 0x100077b3, 0x56 }, + { 0x100077b4, 0x13 }, + { 0x100077b5, 0x07 }, + { 0x100077b6, 0x80 }, + { 0x100077b7, 0x01 }, + { 0x100077b8, 0x93 }, + { 0x100077b9, 0xf7 }, + { 0x100077ba, 0xf7 }, + { 0x100077bb, 0x0f }, + { 0x100077bc, 0x63 }, + { 0x100077bd, 0x70 }, + { 0x100077be, 0xf7 }, + { 0x100077bf, 0x04 }, + { 0x100077c0, 0x37 }, + { 0x100077c1, 0xd4 }, + { 0x100077c2, 0x00 }, + { 0x100077c3, 0x10 }, + { 0x100077c4, 0x83 }, + { 0x100077c5, 0x47 }, + { 0x100077c6, 0x54 }, + { 0x100077c7, 0xd9 }, + { 0x100077c8, 0x93 }, + { 0x100077c9, 0xf7 }, + { 0x100077ca, 0xf7 }, + { 0x100077cb, 0x0f }, + { 0x100077cc, 0x63 }, + { 0x100077cd, 0x88 }, + { 0x100077ce, 0x07 }, + { 0x100077cf, 0x02 }, + { 0x100077d0, 0x93 }, + { 0x100077d1, 0x07 }, + { 0x100077d2, 0x10 }, + { 0x100077d3, 0x00 }, + { 0x100077d4, 0x23 }, + { 0x100077d5, 0x82 }, + { 0x100077d6, 0xf4 }, + { 0x100077d7, 0x58 }, + { 0x100077d8, 0x03 }, + { 0x100077d9, 0x45 }, + { 0x100077da, 0x64 }, + { 0x100077db, 0xd9 }, + { 0x100077dc, 0xb7 }, + { 0x100077dd, 0x15 }, + { 0x100077de, 0x00 }, + { 0x100077df, 0x00 }, + { 0x100077e0, 0x93 }, + { 0x100077e1, 0x85 }, + { 0x100077e2, 0x85 }, + { 0x100077e3, 0x38 }, + { 0x100077e4, 0x13 }, + { 0x100077e5, 0x75 }, + { 0x100077e6, 0xf5 }, + { 0x100077e7, 0x0f }, + { 0x100077e8, 0xef }, + { 0x100077e9, 0xe0 }, + { 0x100077ea, 0x9f }, + { 0x100077eb, 0xd0 }, + { 0x100077ec, 0x93 }, + { 0x100077ed, 0x55 }, + { 0x100077ee, 0xf5 }, + { 0x100077ef, 0x41 }, + { 0x100077f0, 0xef }, + { 0x100077f1, 0xe0 }, + { 0x100077f2, 0x8f }, + { 0x100077f3, 0xa3 }, + { 0x100077f4, 0x23 }, + { 0x100077f5, 0x82 }, + { 0x100077f6, 0x04 }, + { 0x100077f7, 0x58 }, + { 0x100077f8, 0xa3 }, + { 0x100077f9, 0x0a }, + { 0x100077fa, 0x04 }, + { 0x100077fb, 0xd8 }, + { 0x100077fc, 0x83 }, + { 0x100077fd, 0x20 }, + { 0x100077fe, 0xc1 }, + { 0x100077ff, 0x00 }, + { 0x10007800, 0x03 }, + { 0x10007801, 0x24 }, + { 0x10007802, 0x81 }, + { 0x10007803, 0x00 }, + { 0x10007804, 0x83 }, + { 0x10007805, 0x24 }, + { 0x10007806, 0x41 }, + { 0x10007807, 0x00 }, + { 0x10007808, 0x13 }, + { 0x10007809, 0x01 }, + { 0x1000780a, 0x01 }, + { 0x1000780b, 0x01 }, + { 0x1000780c, 0x67 }, + { 0x1000780d, 0x80 }, + { 0x1000780e, 0x00 }, + { 0x1000780f, 0x00 }, + { 0x10007810, 0x67 }, + { 0x10007811, 0x80 }, + { 0x10007812, 0x00 }, + { 0x10007813, 0x00 }, + { 0x10007814, 0x13 }, + { 0x10007815, 0x01 }, + { 0x10007816, 0x01 }, + { 0x10007817, 0xff }, + { 0x10007818, 0x23 }, + { 0x10007819, 0x26 }, + { 0x1000781a, 0x11 }, + { 0x1000781b, 0x00 }, + { 0x1000781c, 0xef }, + { 0x1000781d, 0xd0 }, + { 0x1000781e, 0x8f }, + { 0x1000781f, 0x86 }, + { 0x10007820, 0x83 }, + { 0x10007821, 0xc7 }, + { 0x10007822, 0x11 }, + { 0x10007823, 0x42 }, + { 0x10007824, 0x63 }, + { 0x10007825, 0x86 }, + { 0x10007826, 0x07 }, + { 0x10007827, 0x00 }, + { 0x10007828, 0x03 }, + { 0x10007829, 0xc7 }, + { 0x1000782a, 0x01 }, + { 0x1000782b, 0x42 }, + { 0x1000782c, 0x63 }, + { 0x1000782d, 0x10 }, + { 0x1000782e, 0x07 }, + { 0x1000782f, 0x02 }, + { 0x10007830, 0x83 }, + { 0x10007831, 0xc6 }, + { 0x10007832, 0x21 }, + { 0x10007833, 0x41 }, + { 0x10007834, 0x13 }, + { 0x10007835, 0x07 }, + { 0x10007836, 0xf0 }, + { 0x10007837, 0x01 }, + { 0x10007838, 0x13 }, + { 0x10007839, 0x05 }, + { 0x1000783a, 0xf0 }, + { 0x1000783b, 0x01 }, + { 0x1000783c, 0x63 }, + { 0x1000783d, 0x98 }, + { 0x1000783e, 0xe6 }, + { 0x1000783f, 0x02 }, + { 0x10007840, 0x63 }, + { 0x10007841, 0x8a }, + { 0x10007842, 0x07 }, + { 0x10007843, 0x02 }, + { 0x10007844, 0x83 }, + { 0x10007845, 0xc7 }, + { 0x10007846, 0x01 }, + { 0x10007847, 0x42 }, + { 0x10007848, 0x63 }, + { 0x10007849, 0x86 }, + { 0x1000784a, 0x07 }, + { 0x1000784b, 0x02 }, + { 0x1000784c, 0x83 }, + { 0x1000784d, 0xc7 }, + { 0x1000784e, 0x31 }, + { 0x1000784f, 0x42 }, + { 0x10007850, 0x63 }, + { 0x10007851, 0x86 }, + { 0x10007852, 0x07 }, + { 0x10007853, 0x00 }, + { 0x10007854, 0x83 }, + { 0x10007855, 0xc7 }, + { 0x10007856, 0x21 }, + { 0x10007857, 0x42 }, + { 0x10007858, 0x63 }, + { 0x10007859, 0x9e }, + { 0x1000785a, 0x07 }, + { 0x1000785b, 0x00 }, + { 0x1000785c, 0x03 }, + { 0x1000785d, 0xc7 }, + { 0x1000785e, 0x21 }, + { 0x1000785f, 0x41 }, + { 0x10007860, 0x93 }, + { 0x10007861, 0x07 }, + { 0x10007862, 0xb0 }, + { 0x10007863, 0x01 }, + { 0x10007864, 0x63 }, + { 0x10007865, 0x08 }, + { 0x10007866, 0xf7 }, + { 0x10007867, 0x00 }, + { 0x10007868, 0x13 }, + { 0x10007869, 0x05 }, + { 0x1000786a, 0xb0 }, + { 0x1000786b, 0x01 }, + { 0x1000786c, 0xef }, + { 0x1000786d, 0xd0 }, + { 0x1000786e, 0x0f }, + { 0x1000786f, 0xcf }, + { 0x10007870, 0xef }, + { 0x10007871, 0xd0 }, + { 0x10007872, 0x8f }, + { 0x10007873, 0xa4 }, + { 0x10007874, 0x93 }, + { 0x10007875, 0x06 }, + { 0x10007876, 0x10 }, + { 0x10007877, 0x00 }, + { 0x10007878, 0xa3 }, + { 0x10007879, 0x89 }, + { 0x1000787a, 0xd1 }, + { 0x1000787b, 0x40 }, + { 0x1000787c, 0x37 }, + { 0x1000787d, 0xd7 }, + { 0x1000787e, 0x00 }, + { 0x1000787f, 0x10 }, + { 0x10007880, 0x83 }, + { 0x10007881, 0x47 }, + { 0x10007882, 0x07 }, + { 0x10007883, 0xd9 }, + { 0x10007884, 0x93 }, + { 0x10007885, 0xf7 }, + { 0x10007886, 0xf7 }, + { 0x10007887, 0x0f }, + { 0x10007888, 0x63 }, + { 0x10007889, 0x90 }, + { 0x1000788a, 0x07 }, + { 0x1000788b, 0x02 }, + { 0x1000788c, 0x37 }, + { 0x1000788d, 0xc6 }, + { 0x1000788e, 0x00 }, + { 0x1000788f, 0x00 }, + { 0x10007890, 0x83 }, + { 0x10007891, 0x47 }, + { 0x10007892, 0x26 }, + { 0x10007893, 0x04 }, + { 0x10007894, 0x93 }, + { 0x10007895, 0xe7 }, + { 0x10007896, 0x07 }, + { 0x10007897, 0xf8 }, + { 0x10007898, 0x93 }, + { 0x10007899, 0xf7 }, + { 0x1000789a, 0xf7 }, + { 0x1000789b, 0x0f }, + { 0x1000789c, 0x23 }, + { 0x1000789d, 0x01 }, + { 0x1000789e, 0xf6 }, + { 0x1000789f, 0x04 }, + { 0x100078a0, 0x23 }, + { 0x100078a1, 0x08 }, + { 0x100078a2, 0xd7 }, + { 0x100078a3, 0xd8 }, + { 0x100078a4, 0x23 }, + { 0x100078a5, 0x09 }, + { 0x100078a6, 0x07 }, + { 0x100078a7, 0xd8 }, + { 0x100078a8, 0x83 }, + { 0x100078a9, 0x20 }, + { 0x100078aa, 0xc1 }, + { 0x100078ab, 0x00 }, + { 0x100078ac, 0x13 }, + { 0x100078ad, 0x01 }, + { 0x100078ae, 0x01 }, + { 0x100078af, 0x01 }, + { 0x100078b0, 0x67 }, + { 0x100078b1, 0x80 }, + { 0x100078b2, 0x00 }, + { 0x100078b3, 0x00 }, + { 0x3fc2bfc7, 0x00 }, + { 0x3fc2bfc6, 0x00 }, + { 0x3fc2bfc5, 0x00 }, + { 0x3fc2bfc4, 0x01 }, + { 0x0000d486, 0x43 }, + { 0x1000db00, 0x02 }, + { 0x1000db01, 0x00 }, + { 0x1000db02, 0x11 }, + { 0x1000db03, 0x00 }, + { 0x1000db04, 0x00 }, + { 0x1000db05, 0x82 }, + { 0x1000db06, 0x04 }, + { 0x1000db07, 0xf1 }, + { 0x1000db08, 0x00 }, + { 0x1000db09, 0x00 }, + { 0x1000db0a, 0x40 }, + { 0x0000d540, 0x01 }, +}; + +static const struct reg_default rt1320_reg_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, +}; + +static const struct reg_default rt1320_mbq_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, +}; + +static bool rt1320_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc000 ... 0xc086: + case 0xc400 ... 0xc409: + case 0xc480 ... 0xc48f: + case 0xc4c0 ... 0xc4c4: + case 0xc4e0 ... 0xc4e7: + case 0xc500: + case 0xc560 ... 0xc56b: + case 0xc570: + case 0xc580 ... 0xc59a: + case 0xc5b0 ... 0xc60f: + case 0xc640 ... 0xc64f: + case 0xc670: + case 0xc680 ... 0xc683: + case 0xc700 ... 0xc76f: + case 0xc800 ... 0xc801: + case 0xc820: + case 0xc900 ... 0xc901: + case 0xc920 ... 0xc921: + case 0xca00 ... 0xca07: + case 0xca20 ... 0xca27: + case 0xca40 ... 0xca4b: + case 0xca60 ... 0xca68: + case 0xca80 ... 0xca88: + case 0xcb00 ... 0xcb0c: + case 0xcc00 ... 0xcc12: + case 0xcc80 ... 0xcc81: + case 0xcd00: + case 0xcd80 ... 0xcd82: + case 0xce00 ... 0xce4d: + case 0xcf00 ... 0xcf25: + case 0xd000 ... 0xd0ff: + case 0xd100 ... 0xd1ff: + case 0xd200 ... 0xd2ff: + case 0xd300 ... 0xd3ff: + case 0xd400 ... 0xd403: + case 0xd410 ... 0xd417: + case 0xd470 ... 0xd497: + case 0xd4dc ... 0xd50f: + case 0xd520 ... 0xd543: + case 0xd560 ... 0xd5ef: + case 0xd600 ... 0xd663: + case 0xda00 ... 0xda6e: + case 0xda80 ... 0xda9e: + case 0xdb00 ... 0xdb7f: + case 0xdc00: + case 0xdc20 ... 0xdc21: + case 0xdd00 ... 0xdd17: + case 0xde00 ... 0xde09: + case 0xdf00 ... 0xdf1b: + case 0xe000 ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x1000f008: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc402 ... 0xc406: + case 0xc48c ... 0xc48f: + case 0xc560: + case 0xc5b5 ... 0xc5b7: + case 0xc5fc ... 0xc5ff: + case 0xc820: + case 0xc900: + case 0xc920: + case 0xca42: + case 0xca62: + case 0xca82: + case 0xcd00: + case 0xce03: + case 0xce10: + case 0xce14 ... 0xce17: + case 0xce44 ... 0xce49: + case 0xce4c ... 0xce4d: + case 0xcf0c: + case 0xcf10 ... 0xcf25: + case 0xd486 ... 0xd487: + case 0xd4e5 ... 0xd4e6: + case 0xd4e8 ... 0xd4ff: + case 0xd530: + case 0xd540: + case 0xd543: + case 0xdb58 ... 0xdb5f: + case 0xdb60 ... 0xdb63: + case 0xdb68 ... 0xdb69: + case 0xdb6d: + case 0xdb70 ... 0xdb71: + case 0xdb76: + case 0xdb7a: + case 0xdb7c ... 0xdb7f: + case 0xdd0c ... 0xdd13: + case 0xde02: + case 0xdf14 ... 0xdf1b: + case 0xe83c ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x10000000 ... 0x10007fff: + case 0x1000c000 ... 0x1000dfff: + case 0x1000f008: + case 0x3fc2bfc4 ... 0x3fc2bfc7: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): + return true; + default: + return false; + } +} + +static const struct regmap_config rt1320_sdw_regmap = { + .reg_bits = 32, + .val_bits = 8, + .readable_reg = rt1320_readable_register, + .volatile_reg = rt1320_volatile_register, + .max_register = 0x41081488, + .reg_defaults = rt1320_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static const struct regmap_config rt1320_mbq_regmap = { + .name = "sdw-mbq", + .reg_bits = 32, + .val_bits = 16, + .readable_reg = rt1320_mbq_readable_register, + .max_register = 0x41000192, + .reg_defaults = rt1320_mbq_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static int rt1320_read_prop(struct sdw_slave *slave) +{ + struct sdw_slave_prop *prop = &slave->prop; + int nval; + int i, j; + u32 bit; + unsigned long addr; + struct sdw_dpn_prop *dpn; + + /* + * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping + */ + sdw_slave_read_prop(slave); + + prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; + prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; + + prop->paging_support = true; + prop->lane_control_support = true; + + /* first we need to allocate memory for set bits in port lists */ + prop->source_ports = BIT(4); + prop->sink_ports = BIT(1); + + nval = hweight32(prop->source_ports); + prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, + sizeof(*prop->src_dpn_prop), GFP_KERNEL); + if (!prop->src_dpn_prop) + return -ENOMEM; + + i = 0; + dpn = prop->src_dpn_prop; + addr = prop->source_ports; + for_each_set_bit(bit, &addr, 32) { + dpn[i].num = bit; + dpn[i].type = SDW_DPN_FULL; + dpn[i].simple_ch_prep_sm = true; + dpn[i].ch_prep_timeout = 10; + i++; + } + + /* do this again for sink now */ + nval = hweight32(prop->sink_ports); + prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, + sizeof(*prop->sink_dpn_prop), GFP_KERNEL); + if (!prop->sink_dpn_prop) + return -ENOMEM; + + j = 0; + dpn = prop->sink_dpn_prop; + addr = prop->sink_ports; + for_each_set_bit(bit, &addr, 32) { + dpn[j].num = bit; + dpn[j].type = SDW_DPN_FULL; + dpn[j].simple_ch_prep_sm = true; + dpn[j].ch_prep_timeout = 10; + j++; + } + + /* set the timeout values */ + prop->clk_stop_timeout = 64; + + return 0; +} + +static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned int amp_func_status, val, tmp; + + if (rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, false); + regcache_cache_only(rt1320->mbq_regmap, false); + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, true); + regcache_cache_bypass(rt1320->mbq_regmap, true); + } else { + /* + * PM runtime status is marked as 'active' only when a Slave reports as Attached + */ + /* update count of parent 'active' children */ + pm_runtime_set_active(&slave->dev); + } + + pm_runtime_get_noresume(&slave->dev); + + if (rt1320->version_id < 0) { + regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); + rt1320->version_id = val; + } + + regmap_read(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &amp_func_status); + dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); + + /* initialization write */ + if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt1320->first_hw_init)) { + regmap_multi_reg_write(rt1320->regmap, rt1320_blind_write, ARRAY_SIZE(rt1320_blind_write)); + regmap_multi_reg_write(rt1320->regmap, rt1320_patch_code_write, + ARRAY_SIZE(rt1320_patch_code_write)); + + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), + FUNCTION_NEEDS_INITIALIZATION); + } + if (!rt1320->first_hw_init) { + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); + val = (tmp << 8) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); + val = (tmp << 16) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); + val = (tmp << 24) | val; + dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); + /* + * We call the version b which has the new DSP ROM code against version a. + * Therefore, we read the DSP address to check the ID. + */ + if (val == RT1320_VER_B_ID) + rt1320->version_id = RT1320_VB; + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); + } + dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); + + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, false); + regcache_cache_bypass(rt1320->mbq_regmap, false); + regcache_mark_dirty(rt1320->regmap); + regcache_mark_dirty(rt1320->mbq_regmap); + } + + /* Mark Slave initialization complete */ + rt1320->first_hw_init = true; + rt1320->hw_init = true; + + pm_runtime_mark_last_busy(&slave->dev); + pm_runtime_put_autosuspend(&slave->dev); + + dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); + return 0; +} + +static int rt1320_update_status(struct sdw_slave *slave, + enum sdw_slave_status status) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); + + if (status == SDW_SLAVE_UNATTACHED) + rt1320->hw_init = false; + + /* + * Perform initialization only if slave status is present and + * hw_init flag is false + */ + if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) + return 0; + + /* perform I/O transfers required for Slave initialization */ + return rt1320_io_init(&slave->dev, slave); +} + +static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned char ps0 = 0x0, ps3 = 0x3; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps0); + break; + case SND_SOC_DAPM_PRE_PMD: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps3); + break; + default: + break; + } + + return 0; +} + +static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned int read_l, read_r, gain_l_val, gain_r_val; + unsigned int lvalue, rvalue; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); + regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); + + /* L Channel */ + gain_l_val = ucontrol->value.integer.value[0]; + if (gain_l_val > mc->max) + gain_l_val = mc->max; + gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); + gain_l_val &= 0xffff; + + /* R Channel */ + gain_r_val = ucontrol->value.integer.value[1]; + if (gain_r_val > mc->max) + gain_r_val = mc->max; + gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); + gain_r_val &= 0xffff; + + if (lvalue == gain_l_val && rvalue == gain_r_val) + return 0; + + /* Lch*/ + regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); + /* Rch */ + regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + if (read_r == gain_r_val && read_l == gain_l_val) + return 1; + + return -EIO; +} + +static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + + ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); + + if (read_l != read_r) + ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); + else + ctl_r = ctl_l; + + ucontrol->value.integer.value[0] = ctl_l; + ucontrol->value.integer.value[1] = ctl_r; + return 0; +} + +static const char * const rt1320_rx_data_ch_select[] = { + "L,R", + "R,L", + "L,L", + "R,R", + "L,L+R", + "R,L+R", + "L+R,L", + "L+R,R", + "L+R,L+R", +}; + +static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, + rt1320_rx_data_ch_select); + +static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); + +static const struct snd_kcontrol_new rt1320_snd_controls[] = { + SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), + 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), + SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), +}; + +static const struct snd_kcontrol_new rt1320_spk_l_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), + 0, 1, 1); +static const struct snd_kcontrol_new rt1320_spk_r_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), + 0, 1, 1); + +static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), + + /* Digital Interface */ + SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, + rt1320_pde23_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + /* Output */ + SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), + SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), + SND_SOC_DAPM_OUTPUT("SPOL"), + SND_SOC_DAPM_OUTPUT("SPOR"), + + /* Input */ + SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SIGGEN("AEC Gen"), +}; + +static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { + { "FU21", NULL, "DP1RX" }, + { "FU21", NULL, "PDE 23" }, + { "OT23 L", "Switch", "FU21" }, + { "OT23 R", "Switch", "FU21" }, + { "SPOL", NULL, "OT23 L" }, + { "SPOR", NULL, "OT23 R" }, + + { "AEC Data", NULL, "AEC Gen" }, + { "DP4TX", NULL, "AEC Data" }, +}; + +static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, + int direction) +{ + snd_soc_dai_dma_data_set(dai, direction, sdw_stream); + return 0; +} + +static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + snd_soc_dai_set_dma_data(dai, substream, NULL); +} + +static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_config stream_config; + struct sdw_port_config port_config; + struct sdw_stream_runtime *sdw_stream; + int retval; + unsigned int sampling_rate; + + dev_dbg(dai->dev, "%s %s", __func__, dai->name); + sdw_stream = snd_soc_dai_get_dma_data(dai, substream); + + if (!sdw_stream) + return -EINVAL; + + if (!rt1320->sdw_slave) + return -EINVAL; + + /* SoundWire specific configuration */ + snd_sdw_params_to_config(substream, params, &stream_config, &port_config); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (dai->id == RT1320_AIF1) + port_config.num = 1; + else + return -EINVAL; + } else { + if (dai->id == RT1320_AIF1) + port_config.num = 4; + else + return -EINVAL; + } + + retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, + &port_config, 1, sdw_stream); + if (retval) { + dev_err(dai->dev, "%s: Unable to configure port\n", __func__); + return retval; + } + + /* sampling rate configuration */ + switch (params_rate(params)) { + case 16000: + sampling_rate = RT1320_SDCA_RATE_16000HZ; + break; + case 32000: + sampling_rate = RT1320_SDCA_RATE_32000HZ; + break; + case 44100: + sampling_rate = RT1320_SDCA_RATE_44100HZ; + break; + case 48000: + sampling_rate = RT1320_SDCA_RATE_48000HZ; + break; + case 96000: + sampling_rate = RT1320_SDCA_RATE_96000HZ; + break; + case 192000: + sampling_rate = RT1320_SDCA_RATE_192000HZ; + break; + default: + dev_err(component->dev, "%s: Rate %d is not supported\n", + __func__, params_rate(params)); + return -EINVAL; + } + + /* set sampling frequency */ + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), + sampling_rate); + + return 0; +} + +static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_runtime *sdw_stream = + snd_soc_dai_get_dma_data(dai, substream); + + if (!rt1320->sdw_slave) + return -EINVAL; + + sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); + return 0; +} + +/* + * slave_ops: callbacks for get_clock_stop_mode, clock_stop and + * port_prep are not defined for now + */ +static const struct sdw_slave_ops rt1320_slave_ops = { + .read_prop = rt1320_read_prop, + .update_status = rt1320_update_status, +}; + +static int rt1320_sdw_component_probe(struct snd_soc_component *component) +{ + int ret; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + + rt1320->component = component; + + if (!rt1320->first_hw_init) + return 0; + + ret = pm_runtime_resume(component->dev); + dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); + if (ret < 0 && ret != -EACCES) + return ret; + + return 0; +} + +static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { + .probe = rt1320_sdw_component_probe, + .controls = rt1320_snd_controls, + .num_controls = ARRAY_SIZE(rt1320_snd_controls), + .dapm_widgets = rt1320_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), + .dapm_routes = rt1320_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), + .endianness = 1, +}; + +static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { + .hw_params = rt1320_sdw_hw_params, + .hw_free = rt1320_sdw_pcm_hw_free, + .set_stream = rt1320_set_sdw_stream, + .shutdown = rt1320_sdw_shutdown, +}; + +#define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) +#define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver rt1320_sdw_dai[] = { + { + .name = "rt1320-aif1", + .id = RT1320_AIF1, + .playback = { + .stream_name = "DP1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1320_STEREO_RATES, + .formats = RT1320_FORMATS, + }, + .capture = { + .stream_name = "DP4 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT1320_STEREO_RATES, + .formats = RT1320_FORMATS, + }, + .ops = &rt1320_aif_dai_ops, + }, +}; + +static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, + struct regmap *mbq_regmap, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320; + int ret; + + rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); + if (!rt1320) + return -ENOMEM; + + dev_set_drvdata(dev, rt1320); + rt1320->sdw_slave = slave; + rt1320->mbq_regmap = mbq_regmap; + rt1320->regmap = regmap; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + + /* + * Mark hw_init to false + * HW init will be performed when device reports present + */ + rt1320->hw_init = false; + rt1320->first_hw_init = false; + rt1320->version_id = -1; + + ret = devm_snd_soc_register_component(dev, + &soc_component_sdw_rt1320, + rt1320_sdw_dai, + ARRAY_SIZE(rt1320_sdw_dai)); + if (ret < 0) + return ret; + + /* set autosuspend parameters */ + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + + /* make sure the device does not suspend immediately */ + pm_runtime_mark_last_busy(dev); + + pm_runtime_enable(dev); + + /* important note: the device is NOT tagged as 'active' and will remain + * 'suspended' until the hardware is enumerated/initialized. This is required + * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently + * fail with -EACCESS because of race conditions between card creation and enumeration + */ + + dev_dbg(dev, "%s\n", __func__); + + return ret; +} + +static int rt1320_sdw_probe(struct sdw_slave *slave, + const struct sdw_device_id *id) +{ + struct regmap *regmap, *mbq_regmap; + + /* Regmap Initialization */ + mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); + if (IS_ERR(mbq_regmap)) + return PTR_ERR(mbq_regmap); + + regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); +} + +static int rt1320_sdw_remove(struct sdw_slave *slave) +{ + pm_runtime_disable(&slave->dev); + + return 0; +} + +/* + * Version A/B will use the class id 0 + * The newer version than A/B will use the class id 1, so add it in advance + */ +static const struct sdw_device_id rt1320_id[] = { + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), + {}, +}; +MODULE_DEVICE_TABLE(sdw, rt1320_id); + +static int __maybe_unused rt1320_dev_suspend(struct device *dev) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + + if (!rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + return 0; +} + +#define RT1320_PROBE_TIMEOUT 5000 + +static int __maybe_unused rt1320_dev_resume(struct device *dev) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned long time; + + if (!rt1320->first_hw_init) + return 0; + + if (!slave->unattach_request) + goto regmap_sync; + + time = wait_for_completion_timeout(&slave->initialization_complete, + msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); + if (!time) { + dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); + return -ETIMEDOUT; + } + +regmap_sync: + slave->unattach_request = 0; + regcache_cache_only(rt1320->regmap, false); + regcache_sync(rt1320->regmap); + regcache_cache_only(rt1320->mbq_regmap, false); + regcache_sync(rt1320->mbq_regmap); + return 0; +} + +static const struct dev_pm_ops rt1320_pm = { + SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) + SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) +}; + +static struct sdw_driver rt1320_sdw_driver = { + .driver = { + .name = "rt1320-sdca", + .pm = &rt1320_pm, + }, + .probe = rt1320_sdw_probe, + .remove = rt1320_sdw_remove, + .ops = &rt1320_slave_ops, + .id_table = rt1320_id, +}; +module_sdw_driver(rt1320_sdw_driver); + +MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); +MODULE_AUTHOR("Shuming Fan <shumingf(a)realtek.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/rt1320-sdw.h b/sound/soc/codecs/rt1320-sdw.h new file mode 100644 index 000000000000..b23228e74568 --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * rt1320-sdw.h -- RT1320 SDCA ALSA SoC audio driver header + * + * Copyright(c) 2024 Realtek Semiconductor Corp. + */ + +#ifndef __RT1320_SDW_H__ +#define __RT1320_SDW_H__ + +#include <linux/regmap.h> +#include <linux/soundwire/sdw.h> +#include <linux/soundwire/sdw_type.h> +#include <linux/soundwire/sdw_registers.h> +#include <sound/soc.h> + +/* imp-defined registers */ +#define RT1320_DEV_VERSION_ID_1 0xc404 + +#define RT1320_KR0_STATUS_CNT 0x1000f008 +#define RT1320_HIFI_VER_0 0x3fe2e000 +#define RT1320_HIFI_VER_1 0x3fe2e001 +#define RT1320_HIFI_VER_2 0x3fe2e002 +#define RT1320_HIFI_VER_3 0x3fe2e003 + +/* RT1320 SDCA Control - function number */ +#define FUNC_NUM_AMP 0x04 + +/* RT1320 SDCA entity */ +#define RT1320_SDCA_ENT0 0x00 +#define RT1320_SDCA_ENT_PDE11 0x2a +#define RT1320_SDCA_ENT_PDE23 0x33 +#define RT1320_SDCA_ENT_PDE27 0x27 +#define RT1320_SDCA_ENT_FU14 0x32 +#define RT1320_SDCA_ENT_FU21 0x03 +#define RT1320_SDCA_ENT_FU113 0x30 +#define RT1320_SDCA_ENT_CS14 0x13 +#define RT1320_SDCA_ENT_CS21 0x21 +#define RT1320_SDCA_ENT_CS113 0x12 +#define RT1320_SDCA_ENT_SAPU 0x29 +#define RT1320_SDCA_ENT_PPU21 0x04 + +/* RT1320 SDCA control */ +#define RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10 +#define RT1320_SDCA_CTL_REQ_POWER_STATE 0x01 +#define RT1320_SDCA_CTL_FU_MUTE 0x01 +#define RT1320_SDCA_CTL_FU_VOLUME 0x02 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_MODE 0x10 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11 +#define RT1320_SDCA_CTL_POSTURE_NUMBER 0x10 +#define RT1320_SDCA_CTL_FUNC_STATUS 0x10 + +/* RT1320 SDCA channel */ +#define CH_01 0x01 +#define CH_02 0x02 + +/* Function_Status */ +#define FUNCTION_NEEDS_INITIALIZATION BIT(5) + +/* Sample Frequency Index */ +#define RT1320_SDCA_RATE_16000HZ 0x04 +#define RT1320_SDCA_RATE_32000HZ 0x07 +#define RT1320_SDCA_RATE_44100HZ 0x08 +#define RT1320_SDCA_RATE_48000HZ 0x09 +#define RT1320_SDCA_RATE_96000HZ 0x0b +#define RT1320_SDCA_RATE_192000HZ 0x0d + +enum { + RT1320_AIF1, +}; + +/* + * The version id will be useful to distinguish the capability between the different IC versions. + * Currently, VA and VB have different DSP FW versions. + */ +enum rt1320_version_id { + RT1320_VA, + RT1320_VB, +}; + +#define RT1320_VER_B_ID 0x07392238 + +struct rt1320_sdw_priv { + struct snd_soc_component *component; + struct regmap *regmap; + struct regmap *mbq_regmap; + struct sdw_slave *sdw_slave; + struct sdw_bus_params params; + bool hw_init; + bool first_hw_init; + int version_id; +}; + +#endif /* __RT1320_SDW_H__ */ -- 2.34.1

2 1

[PATCH] ALSA: scarlett2: Prevent leaking urb
by Chen Ni 21 May '24

21 May '24

In scarlett2_init_notify() if kmalloc() fails the allocated urb should be released. Signed-off-by: Chen Ni <nichen(a)iscas.ac.cn> --- sound/usb/mixer_scarlett2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/usb/mixer_scarlett2.c b/sound/usb/mixer_scarlett2.c index 1150cf104985..4cad6b2a0292 100644 --- a/sound/usb/mixer_scarlett2.c +++ b/sound/usb/mixer_scarlett2.c @@ -8637,9 +8637,10 @@ static int scarlett2_init_notify(struct usb_mixer_interface *mixer) return -ENOMEM; transfer_buffer = kmalloc(private->wMaxPacketSize, GFP_KERNEL); - if (!transfer_buffer) + if (!transfer_buffer) { + usb_free_urb(mixer->urb); return -ENOMEM; - + } usb_fill_int_urb(mixer->urb, dev, pipe, transfer_buffer, private->wMaxPacketSize, scarlett2_notify, mixer, private->bInterval); -- 2.25.1

1 0

Add UCM files for avs driver
by GitHub pull_request - opened 21 May '24

21 May '24

alsa-project/alsa-ucm-conf pull request #418 was opened from amadeuszslawinski-intel: Present in this pull request are UCM files for some of the devices available on market that we were able to test. They are meant to be used with avs driver and relevant topology files. Request URL : https://github.com/alsa-project/alsa-ucm-conf/pull/418 Patch URL : https://github.com/alsa-project/alsa-ucm-conf/pull/418.patch Repository URL: https://github.com/alsa-project/alsa-ucm-conf

1 0

[PATCH 0/2] Support Tegra I2S client format conversion
by Sameer Pujar 21 May '24

21 May '24

The AHUB HW modules are interconnected with CIF which are capable of supporting Channel and Sample bit format conversion. Due to this, the I2S Client can have different Channel and Sample bit from the hw_params() and this config is passed from CIF port of I2S DT node which can help to perform this conversion. - First change to split simple_fixup_sample_fmt to support returning sample format value - Second patch to support Tegra I2S client channel and sample format programming based on CIF port from DT node. Mohan Kumar (2): ASoC: simple-card-utils: Split simple_fixup_sample_fmt func ASoC: tegra: I2S client convert formats handling include/sound/simple_card_utils.h | 2 + sound/soc/generic/simple-card-utils.c | 26 +++++++--- sound/soc/tegra/tegra210_i2s.c | 71 +++++++++++++++++++++++++-- sound/soc/tegra/tegra210_i2s.h | 2 + 4 files changed, 91 insertions(+), 10 deletions(-) -- 2.45.1

2 3

[PATCH 1/2] ASoC: dt-bindings: fsl,mqs: Add i.MX95 platform support
by Shengjiu Wang 21 May '24

21 May '24

In order to support the MQS module on i.MX95, a new property "fsl,mqs-ctrl" needs to be added, as there are two MQS instances on the i.MX95 platform, the definition of bit positions in the control register is different. This new property is to distinguish these two instances. Without this property, the difference of platforms except the i.MX95 was handled by the driver itself. But this new property can also be used for previous platforms. The MQS only has one control register, the register may be in General Purpose Register memory space, or MQS its own memory space, or controlled by System Manager. The bit position in the register may be different for each platform, there are four parts (bits for module enablement, bits for reset, bits for oversampling ratio, bits for divider ratio). This new property includes all these things. Signed-off-by: Shengjiu Wang <shengjiu.wang(a)nxp.com> --- .../devicetree/bindings/sound/fsl,mqs.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml index 8b33353a80ca..a2129b7cb147 100644 --- a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml @@ -23,6 +23,7 @@ properties: - fsl,imx8qm-mqs - fsl,imx8qxp-mqs - fsl,imx93-mqs + - fsl,imx95-mqs clocks: minItems: 1 @@ -45,6 +46,22 @@ properties: resets: maxItems: 1 + fsl,mqs-ctrl: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 6 + maxItems: 6 + description: | + Contains the control register information, defined as, + Cell #1: register type + 0 - the register in owned register map + 1 - the register in general purpose register map + 2 - the register in control of system manager + Cell #2: offset of the control register from the syscon + Cell #3: shift bits for module enable bit + Cell #4: shift bits for reset bit + Cell #5: shift bits for oversampling ratio bit + Cell #6: shift bits for divider ratio control bit + required: - compatible - clocks -- 2.34.1

3 2

[PATCH v2] ASoC: intel: Constify struct snd_soc_ops
by Christophe JAILLET 20 May '24

20 May '24

Constifying "struct snd_soc_ops" moves some data to a read-only section, so increase overall security. This structure is also part of scripts/const_structs.checkpatch. As an example, on a x86_64, with allmodconfig: Before: text data bss dec hex filename 6315 3696 0 10011 271b sound/soc/intel/boards/ehl_rt5660.o After: text data bss dec hex filename 6379 3648 0 10027 272b sound/soc/intel/boards/ehl_rt5660.o Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- Compile tested only. I hope that it can be applied with this single patch because all files are in sound/soc/intel/boards/ Changes in v2: - Remove changes in sound/soc/intel/boards/sof_maxim_common.[ch]. An even better solution has been applied in commit 2bb765f05391 ("ASoC: Intel: maxim-common: change max98373 data to static") - synch with -next-20240513 v1: https://lore.kernel.org/all/242aef53b5b9533ae4cca78148622f5fe752b7ee.171545… --- sound/soc/intel/boards/bdw-rt5650.c | 2 +- sound/soc/intel/boards/ehl_rt5660.c | 2 +- sound/soc/intel/boards/kbl_da7219_max98357a.c | 4 ++-- sound/soc/intel/boards/kbl_da7219_max98927.c | 6 +++--- sound/soc/intel/boards/kbl_rt5660.c | 2 +- sound/soc/intel/boards/kbl_rt5663_max98927.c | 8 ++++---- sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c | 6 +++--- sound/soc/intel/boards/sof_es8336.c | 2 +- sound/soc/intel/boards/sof_nau8825.c | 2 +- sound/soc/intel/boards/sof_realtek_common.c | 2 +- sound/soc/intel/boards/sof_rt5682.c | 2 +- sound/soc/intel/boards/sof_sdw_common.h | 2 +- sound/soc/intel/boards/sof_sdw_rt_amp.c | 2 +- sound/soc/intel/boards/sof_wm8804.c | 2 +- 14 files changed, 22 insertions(+), 22 deletions(-) diff --git a/sound/soc/intel/boards/bdw-rt5650.c b/sound/soc/intel/boards/bdw-rt5650.c index 3ae26f21458f..3c7cee03a02e 100644 --- a/sound/soc/intel/boards/bdw-rt5650.c +++ b/sound/soc/intel/boards/bdw-rt5650.c @@ -131,7 +131,7 @@ static int bdw_rt5650_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops bdw_rt5650_ops = { +static const struct snd_soc_ops bdw_rt5650_ops = { .hw_params = bdw_rt5650_hw_params, }; diff --git a/sound/soc/intel/boards/ehl_rt5660.c b/sound/soc/intel/boards/ehl_rt5660.c index 686e60321224..26289e8fdd87 100644 --- a/sound/soc/intel/boards/ehl_rt5660.c +++ b/sound/soc/intel/boards/ehl_rt5660.c @@ -132,7 +132,7 @@ static int rt5660_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops rt5660_ops = { +static const struct snd_soc_ops rt5660_ops = { .hw_params = rt5660_hw_params, }; diff --git a/sound/soc/intel/boards/kbl_da7219_max98357a.c b/sound/soc/intel/boards/kbl_da7219_max98357a.c index 9dbc15f9d1c9..154f6a74ed15 100644 --- a/sound/soc/intel/boards/kbl_da7219_max98357a.c +++ b/sound/soc/intel/boards/kbl_da7219_max98357a.c @@ -354,7 +354,7 @@ static int kabylake_dmic_startup(struct snd_pcm_substream *substream) SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); } -static struct snd_soc_ops kabylake_dmic_ops = { +static const struct snd_soc_ops kabylake_dmic_ops = { .startup = kabylake_dmic_startup, }; @@ -388,7 +388,7 @@ static int kabylake_refcap_startup(struct snd_pcm_substream *substream) &constraints_16000); } -static struct snd_soc_ops skylake_refcap_ops = { +static const struct snd_soc_ops skylake_refcap_ops = { .startup = kabylake_refcap_startup, }; diff --git a/sound/soc/intel/boards/kbl_da7219_max98927.c b/sound/soc/intel/boards/kbl_da7219_max98927.c index e662da5af83b..02ed77a07e23 100644 --- a/sound/soc/intel/boards/kbl_da7219_max98927.c +++ b/sound/soc/intel/boards/kbl_da7219_max98927.c @@ -288,7 +288,7 @@ static int kabylake_ssp0_trigger(struct snd_pcm_substream *substream, int cmd) return 0; } -static struct snd_soc_ops kabylake_ssp0_ops = { +static const struct snd_soc_ops kabylake_ssp0_ops = { .hw_params = kabylake_ssp0_hw_params, .trigger = kabylake_ssp0_trigger, }; @@ -535,7 +535,7 @@ static int kabylake_dmic_startup(struct snd_pcm_substream *substream) SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); } -static struct snd_soc_ops kabylake_dmic_ops = { +static const struct snd_soc_ops kabylake_dmic_ops = { .startup = kabylake_dmic_startup, }; @@ -569,7 +569,7 @@ static int kabylake_refcap_startup(struct snd_pcm_substream *substream) } -static struct snd_soc_ops skylake_refcap_ops = { +static const struct snd_soc_ops skylake_refcap_ops = { .startup = kabylake_refcap_startup, }; diff --git a/sound/soc/intel/boards/kbl_rt5660.c b/sound/soc/intel/boards/kbl_rt5660.c index 894d127c482a..66885cb36f24 100644 --- a/sound/soc/intel/boards/kbl_rt5660.c +++ b/sound/soc/intel/boards/kbl_rt5660.c @@ -277,7 +277,7 @@ static int kabylake_rt5660_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops kabylake_rt5660_ops = { +static const struct snd_soc_ops kabylake_rt5660_ops = { .hw_params = kabylake_rt5660_hw_params, }; diff --git a/sound/soc/intel/boards/kbl_rt5663_max98927.c b/sound/soc/intel/boards/kbl_rt5663_max98927.c index e16c42e81eca..9da89436a917 100644 --- a/sound/soc/intel/boards/kbl_rt5663_max98927.c +++ b/sound/soc/intel/boards/kbl_rt5663_max98927.c @@ -489,7 +489,7 @@ static int kabylake_rt5663_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops kabylake_rt5663_ops = { +static const struct snd_soc_ops kabylake_rt5663_ops = { .hw_params = kabylake_rt5663_hw_params, }; @@ -539,7 +539,7 @@ static int kabylake_ssp0_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops kabylake_ssp0_ops = { +static const struct snd_soc_ops kabylake_ssp0_ops = { .hw_params = kabylake_ssp0_hw_params, }; @@ -575,7 +575,7 @@ static int kabylake_dmic_startup(struct snd_pcm_substream *substream) SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); } -static struct snd_soc_ops kabylake_dmic_ops = { +static const struct snd_soc_ops kabylake_dmic_ops = { .startup = kabylake_dmic_startup, }; @@ -609,7 +609,7 @@ static int kabylake_refcap_startup(struct snd_pcm_substream *substream) &constraints_16000); } -static struct snd_soc_ops skylake_refcap_ops = { +static const struct snd_soc_ops skylake_refcap_ops = { .startup = kabylake_refcap_startup, }; diff --git a/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c b/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c index a9501cd106ff..a32ce8f972f3 100644 --- a/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c +++ b/sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c @@ -424,7 +424,7 @@ static int kabylake_rt5663_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops kabylake_rt5663_ops = { +static const struct snd_soc_ops kabylake_rt5663_ops = { .hw_params = kabylake_rt5663_hw_params, }; @@ -469,7 +469,7 @@ static int kabylake_ssp0_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops kabylake_ssp0_ops = { +static const struct snd_soc_ops kabylake_ssp0_ops = { .hw_params = kabylake_ssp0_hw_params, }; @@ -508,7 +508,7 @@ static int kabylake_dmic_startup(struct snd_pcm_substream *substream) SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); } -static struct snd_soc_ops kabylake_dmic_ops = { +static const struct snd_soc_ops kabylake_dmic_ops = { .startup = kabylake_dmic_startup, }; diff --git a/sound/soc/intel/boards/sof_es8336.c b/sound/soc/intel/boards/sof_es8336.c index c1fcc156a575..2a88efaa6d26 100644 --- a/sound/soc/intel/boards/sof_es8336.c +++ b/sound/soc/intel/boards/sof_es8336.c @@ -371,7 +371,7 @@ static int sof_es8336_hw_params(struct snd_pcm_substream *substream, } /* machine stream operations */ -static struct snd_soc_ops sof_es8336_ops = { +static const struct snd_soc_ops sof_es8336_ops = { .hw_params = sof_es8336_hw_params, .trigger = sof_8336_trigger, }; diff --git a/sound/soc/intel/boards/sof_nau8825.c b/sound/soc/intel/boards/sof_nau8825.c index c08b4eef0bcb..bfe17acbc161 100644 --- a/sound/soc/intel/boards/sof_nau8825.c +++ b/sound/soc/intel/boards/sof_nau8825.c @@ -115,7 +115,7 @@ static int sof_nau8825_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops sof_nau8825_ops = { +static const struct snd_soc_ops sof_nau8825_ops = { .hw_params = sof_nau8825_hw_params, }; diff --git a/sound/soc/intel/boards/sof_realtek_common.c b/sound/soc/intel/boards/sof_realtek_common.c index dda346e0f737..f52e25083905 100644 --- a/sound/soc/intel/boards/sof_realtek_common.c +++ b/sound/soc/intel/boards/sof_realtek_common.c @@ -452,7 +452,7 @@ static int rt1015_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops rt1015_ops = { +static const struct snd_soc_ops rt1015_ops = { .hw_params = rt1015_hw_params, }; diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c index 6fc6eb0c5172..23a40b913290 100644 --- a/sound/soc/intel/boards/sof_rt5682.c +++ b/sound/soc/intel/boards/sof_rt5682.c @@ -397,7 +397,7 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream, return ret; } -static struct snd_soc_ops sof_rt5682_ops = { +static const struct snd_soc_ops sof_rt5682_ops = { .hw_params = sof_rt5682_hw_params, }; diff --git a/sound/soc/intel/boards/sof_sdw_common.h b/sound/soc/intel/boards/sof_sdw_common.h index 3dfba6f6b95d..7dedac918065 100644 --- a/sound/soc/intel/boards/sof_sdw_common.h +++ b/sound/soc/intel/boards/sof_sdw_common.h @@ -169,7 +169,7 @@ int sof_sdw_rt_sdca_jack_init(struct snd_soc_card *card, int sof_sdw_rt_sdca_jack_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link); /* RT1308 I2S support */ -extern struct snd_soc_ops sof_sdw_rt1308_i2s_ops; +extern const struct snd_soc_ops sof_sdw_rt1308_i2s_ops; /* generic amp support */ int sof_sdw_rt_amp_init(struct snd_soc_card *card, diff --git a/sound/soc/intel/boards/sof_sdw_rt_amp.c b/sound/soc/intel/boards/sof_sdw_rt_amp.c index 797ea9ffa77a..d1c0f91ce589 100644 --- a/sound/soc/intel/boards/sof_sdw_rt_amp.c +++ b/sound/soc/intel/boards/sof_sdw_rt_amp.c @@ -233,7 +233,7 @@ static int rt1308_i2s_hw_params(struct snd_pcm_substream *substream, } /* machine stream operations */ -struct snd_soc_ops sof_sdw_rt1308_i2s_ops = { +const struct snd_soc_ops sof_sdw_rt1308_i2s_ops = { .hw_params = rt1308_i2s_hw_params, }; diff --git a/sound/soc/intel/boards/sof_wm8804.c b/sound/soc/intel/boards/sof_wm8804.c index 4cb0d463bf40..b2d02cc92a6a 100644 --- a/sound/soc/intel/boards/sof_wm8804.c +++ b/sound/soc/intel/boards/sof_wm8804.c @@ -148,7 +148,7 @@ static int sof_wm8804_hw_params(struct snd_pcm_substream *substream, } /* machine stream operations */ -static struct snd_soc_ops sof_wm8804_ops = { +static const struct snd_soc_ops sof_wm8804_ops = { .hw_params = sof_wm8804_hw_params, }; -- 2.45.0

2 1

[PATCH 1/6] ASoC: topology: Constify an argument of snd_soc_tplg_component_load()
by Christophe JAILLET 20 May '24

20 May '24

snd_soc_tplg_component_load() does not modify its "*ops" argument. It only read some values and stores it in "soc_tplg.ops". This argument and the ops field in "struct soc_tplg" can be made const. Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- include/sound/soc-topology.h | 2 +- sound/soc/soc-topology.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/sound/soc-topology.h b/include/sound/soc-topology.h index f055c6917f6c..1eedd203ac29 100644 --- a/include/sound/soc-topology.h +++ b/include/sound/soc-topology.h @@ -178,7 +178,7 @@ static inline const void *snd_soc_tplg_get_data(struct snd_soc_tplg_hdr *hdr) /* Dynamic Object loading and removal for component drivers */ int snd_soc_tplg_component_load(struct snd_soc_component *comp, - struct snd_soc_tplg_ops *ops, const struct firmware *fw); + const struct snd_soc_tplg_ops *ops, const struct firmware *fw); int snd_soc_tplg_component_remove(struct snd_soc_component *comp); /* Binds event handlers to dynamic widgets */ diff --git a/sound/soc/soc-topology.c b/sound/soc/soc-topology.c index 90ca37e008b3..b00ec01361c2 100644 --- a/sound/soc/soc-topology.c +++ b/sound/soc/soc-topology.c @@ -73,7 +73,7 @@ struct soc_tplg { int bytes_ext_ops_count; /* optional fw loading callbacks to component drivers */ - struct snd_soc_tplg_ops *ops; + const struct snd_soc_tplg_ops *ops; }; /* check we dont overflow the data for this control chunk */ @@ -2334,7 +2334,7 @@ static int soc_tplg_load(struct soc_tplg *tplg) /* load audio component topology from "firmware" file */ int snd_soc_tplg_component_load(struct snd_soc_component *comp, - struct snd_soc_tplg_ops *ops, const struct firmware *fw) + const struct snd_soc_tplg_ops *ops, const struct firmware *fw) { struct soc_tplg tplg; int ret; -- 2.45.0

4 12

[RESEND PATCH v5 1/3] ASoC: tas2781: Fix wrong loading calibrated data sequence
by Shenghao Ding 20 May '24

20 May '24

Remove declaration of unused API which load calibrated data in wrong sequence, changed the copyright year and correct file name in license header. Fixes: ef3bcde75d06 ("ASoc: tas2781: Add tas2781 driver") Signed-off-by: Shenghao Ding <shenghao-ding(a)ti.com> --- v5: - correct changelog has no much relationship with the patch v4: - Use the the culprit of the bug itself as the fixes tag v3: - No changes. v2: - In the Subject, fixed --> Fix - Add Fixes tag - Changed the copyright year to 2024 in the related files - In tas2781-dsp.h, __TASDEVICE_DSP_H__ --> __TAS2781_DSP_H__ v1: - Download calibrated data after loading the new DSP config params - Remove tasdevice_prmg_calibdata_load, because it is unnecessary to load calibrated data after loading DSP program. --- include/sound/tas2781-dsp.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/sound/tas2781-dsp.h b/include/sound/tas2781-dsp.h index ea9af2726a53..7fba7ea26a4b 100644 --- a/include/sound/tas2781-dsp.h +++ b/include/sound/tas2781-dsp.h @@ -2,7 +2,7 @@ // // ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier // -// Copyright (C) 2022 - 2023 Texas Instruments Incorporated +// Copyright (C) 2022 - 2024 Texas Instruments Incorporated // https://www.ti.com // // The TAS2781 driver implements a flexible and configurable @@ -13,8 +13,8 @@ // Author: Kevin Lu <kevin-lu(a)ti.com> // -#ifndef __TASDEVICE_DSP_H__ -#define __TASDEVICE_DSP_H__ +#ifndef __TAS2781_DSP_H__ +#define __TAS2781_DSP_H__ #define MAIN_ALL_DEVICES 0x0d #define MAIN_DEVICE_A 0x01 @@ -180,7 +180,6 @@ void tasdevice_calbin_remove(void *context); int tasdevice_select_tuningprm_cfg(void *context, int prm, int cfg_no, int rca_conf_no); int tasdevice_prmg_load(void *context, int prm_no); -int tasdevice_prmg_calibdata_load(void *context, int prm_no); void tasdevice_tuning_switch(void *context, int state); int tas2781_load_calibration(void *context, char *file_name, unsigned short i); -- 2.34.1

2 3

[PATCH v1] ASoC: tas2552: Add TX path for capturing AUDIO-OUT data
by Shenghao Ding 20 May '24

20 May '24

TAS2552 is a Smartamp with I/V sense data, add TX path to support capturing I/V data. Fixes: 38803ce7b53b ("ASoC: codecs: tas*: merge .digital_mute() into .mute_stream()") Signed-off-by: Shenghao Ding <shenghao-ding(a)ti.com> --- v1: - Changed the copyright year to 2024 in the related files. - Add tx device in tas2552_dai. - Add Stream Domain Widgets for I/V capture - Add INPUT widget - Add I/V capture route --- sound/soc/codecs/tas2552.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c index 40f5f27e74c0..9fd3642b98b3 100644 --- a/sound/soc/codecs/tas2552.c +++ b/sound/soc/codecs/tas2552.c @@ -2,7 +2,8 @@ /* * tas2552.c - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier * - * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com + * Copyright (C) 2014 - 2024 Texas Instruments Incorporated - + * https://www.ti.com * * Author: Dan Murphy <dmurphy(a)ti.com> */ @@ -119,12 +120,14 @@ static const struct snd_soc_dapm_widget tas2552_dapm_widgets[] = &tas2552_input_mux_control), SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("ASI OUT", "DAC Capture", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_OUT_DRV("ClassD", TAS2552_CFG_2, 7, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("PLL", TAS2552_CFG_2, 3, 0, NULL, 0), SND_SOC_DAPM_POST("Post Event", tas2552_post_event), - SND_SOC_DAPM_OUTPUT("OUT") + SND_SOC_DAPM_OUTPUT("OUT"), + SND_SOC_DAPM_INPUT("DMIC") }; static const struct snd_soc_dapm_route tas2552_audio_map[] = { @@ -134,6 +137,7 @@ static const struct snd_soc_dapm_route tas2552_audio_map[] = { {"ClassD", NULL, "Input selection"}, {"OUT", NULL, "ClassD"}, {"ClassD", NULL, "PLL"}, + {"ASI OUT", NULL, "DMIC"} }; #ifdef CONFIG_PM @@ -538,6 +542,13 @@ static struct snd_soc_dai_driver tas2552_dai[] = { .rates = SNDRV_PCM_RATE_8000_192000, .formats = TAS2552_FORMATS, }, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = TAS2552_FORMATS, + }, .ops = &tas2552_speaker_dai_ops, }, }; -- 2.34.1

3 3

[PATCH v5 0/1] Add tas2781 driver for SPI.
by Baojun Xu 20 May '24

20 May '24

This patch was used to add TAS2781 devices on SPI support in sound/pci/hda. It use ACPI node descript about parameters of TAS2781 on SPI, it like: Scope (_SB.PC00.SPI0) { Device (GSPK) { Name (_HID, "TXNW2781") // _HID: Hardware ID Method (_CRS, 0, NotSerialized) { Name (RBUF, ResourceTemplate () { SpiSerialBusV2 (...) SpiSerialBusV2 (...) } } } } And in platform/x86/serial-multi-instantiate.c, those spi devices will be added into system as a single SPI device, so TAS2781 SPI driver will probe twice for every single SPI device. And driver will also parser mono DSP firmware binary and RCA binary for itself. Signed-off-by: Baojun Xu <baojun.xu(a)ti.com> Baojun Xu (1): ALSA: hda/tas2781: Add tas2781 hda driver based on SPI drivers/acpi/scan.c | 1 + .../platform/x86/serial-multi-instantiate.c | 12 + sound/pci/hda/Kconfig | 14 + sound/pci/hda/Makefile | 2 + sound/pci/hda/patch_realtek.c | 13 + sound/pci/hda/tas2781-spi.h | 148 ++ sound/pci/hda/tas2781_hda_spi.c | 1234 +++++++++ sound/pci/hda/tas2781_spi_fwlib.c | 2247 +++++++++++++++++ 8 files changed, 3671 insertions(+) create mode 100644 sound/pci/hda/tas2781-spi.h create mode 100644 sound/pci/hda/tas2781_hda_spi.c create mode 100644 sound/pci/hda/tas2781_spi_fwlib.c -- 2.40.1

1 1

[PATCH v4 0/4] ASoC: qcom: x1e80100: Correct channel mapping
by Krzysztof Kozlowski 20 May '24

20 May '24

Hi, First patch is a build dependency. Changes in v4: - Rename audioreach_set_channel_mapping -> audioreach_set_default_channel_mapping - Link to v3: https://lore.kernel.org/r/20240509-asoc-x1e80100-4-channel-mapping-v3-0-6f8… Changes in v3: - Add missing Charles' Ack - Link to v2: https://lore.kernel.org/r/20240508-asoc-x1e80100-4-channel-mapping-v2-0-cce… Changes in v2: - Re-work most of the idea according to Srini comments: set channel mapping for backend DAIs, not frontend. - Patch #1: no changes - Patch #2 is entirely replaced - now channel mapping is implemented in q6apm-lpass-dais. - Patch #3: rework to new approach, but most of the code stays. - Patch #4: rework significantly, because only backend DAIs is now affected. - Link to v1: https://lore.kernel.org/r/20240507-asoc-x1e80100-4-channel-mapping-v1-0-b12… Description =========== X1E80100 CRD is the first board, which comes with four speakers, so we still keep fixing and adding missing pieces. The board has speaker arranged as left front+back and then right front+back. Using default channel mapping causes front right speaker to play left back stream. Adjust the channel maps for frontend DAIs to fix stereo and four-channel playback. Best regards, Krzysztof --- Krzysztof Kozlowski (4): ASoC: Constify channel mapping array arguments in set_channel_map() ASoC: qcom: q6apm-lpass-dais: Implement proper channel mapping ASoC: qcom: qdsp6: Set channel mapping instead of fixed defaults ASoC: qcom: x1e80100: Correct channel mapping include/sound/cs35l41.h | 4 ++-- include/sound/soc-dai.h | 8 ++++---- sound/soc/codecs/adau7118.c | 6 ++++-- sound/soc/codecs/cs35l41-lib.c | 4 ++-- sound/soc/codecs/cs35l41.c | 3 ++- sound/soc/codecs/max98504.c | 6 ++++-- sound/soc/codecs/wcd9335.c | 6 ++++-- sound/soc/codecs/wcd934x.c | 6 ++++-- sound/soc/qcom/qdsp6/audioreach.c | 30 +++++++----------------------- sound/soc/qcom/qdsp6/audioreach.h | 2 +- sound/soc/qcom/qdsp6/q6afe-dai.c | 16 ++++++++++------ sound/soc/qcom/qdsp6/q6apm-dai.c | 3 +++ sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 21 +++++++++++++-------- sound/soc/qcom/x1e80100.c | 18 ++++++++++++++++++ sound/soc/soc-dai.c | 4 ++-- 15 files changed, 80 insertions(+), 57 deletions(-) --- base-commit: 2b84edefcad14934796fad37b16512b6a2ca467e change-id: 20240507-asoc-x1e80100-4-channel-mapping-ea5f02b9e678 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org>

1 4

[PATCH v3] ASoC: rt1320: Add RT1320 SDCA vendor-specific driver
by shumingf＠realtek.com 20 May '24

20 May '24

From: Shuming Fan <shumingf(a)realtek.com> This is the initial amplifier driver for rt1320. Signed-off-by: Shuming Fan <shumingf(a)realtek.com> -- v2: add Capture DAI for AEC feedback v3: add some comments for blind writes/patch_code/calling sdw_slave_read_prop add class id 1 --- sound/soc/codecs/Kconfig | 7 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt1320-sdw.c | 2256 +++++++++++++++++++++++++++++++++ sound/soc/codecs/rt1320-sdw.h | 94 ++ 4 files changed, 2359 insertions(+) create mode 100644 sound/soc/codecs/rt1320-sdw.c create mode 100644 sound/soc/codecs/rt1320-sdw.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 4afc43d3f71f..7502581d1631 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -222,6 +222,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_RT1308_SDW imply SND_SOC_RT1316_SDW imply SND_SOC_RT1318_SDW + imply SND_SOC_RT1320_SDW imply SND_SOC_RT9120 imply SND_SOC_RTQ9128 imply SND_SOC_SDW_MOCKUP @@ -1575,6 +1576,12 @@ config SND_SOC_RT1318_SDW depends on SOUNDWIRE select REGMAP_SOUNDWIRE +config SND_SOC_RT1320_SDW + tristate "Realtek RT1320 Codec - SDW" + depends on SOUNDWIRE + select REGMAP_SOUNDWIRE + select REGMAP_SOUNDWIRE_MBQ + config SND_SOC_RT5514 tristate depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index b4df22186e25..f9eb7c073a00 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -222,6 +222,7 @@ snd-soc-rt1308-y := rt1308.o snd-soc-rt1308-sdw-y := rt1308-sdw.o snd-soc-rt1316-sdw-y := rt1316-sdw.o snd-soc-rt1318-sdw-y := rt1318-sdw.o +snd-soc-rt1320-sdw-y := rt1320-sdw.o snd-soc-rt274-y := rt274.o snd-soc-rt286-y := rt286.o snd-soc-rt298-y := rt298.o @@ -614,6 +615,7 @@ obj-$(CONFIG_SND_SOC_RT1308) += snd-soc-rt1308.o obj-$(CONFIG_SND_SOC_RT1308_SDW) += snd-soc-rt1308-sdw.o obj-$(CONFIG_SND_SOC_RT1316_SDW) += snd-soc-rt1316-sdw.o obj-$(CONFIG_SND_SOC_RT1318_SDW) += snd-soc-rt1318-sdw.o +obj-$(CONFIG_SND_SOC_RT1320_SDW) += snd-soc-rt1320-sdw.o obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o diff --git a/sound/soc/codecs/rt1320-sdw.c b/sound/soc/codecs/rt1320-sdw.c new file mode 100644 index 000000000000..00a9e7d9f7a8 --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.c @@ -0,0 +1,2256 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver +// +// Copyright(c) 2024 Realtek Semiconductor Corp. +// +// +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/pm_runtime.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include <linux/dmi.h> +#include <linux/firmware.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/sdw.h> +#include "rt1320-sdw.h" + +/* + * The 'blind writes' is an SDCA term to deal with platform-specific initialization. + * It might include vendor-specific or SDCA control registers. + */ +static const struct reg_sequence rt1320_blind_write[] = { + { 0xc003, 0xe0 }, + { 0xc01b, 0xfc }, + { 0xc5c3, 0xf2 }, + { 0xc5c2, 0x00 }, + { 0xc5c6, 0x10 }, + { 0xc5c4, 0x12 }, + { 0xc5c8, 0x03 }, + { 0xc5d8, 0x0a }, + { 0xc5f7, 0x22 }, + { 0xc5f6, 0x22 }, + { 0xc5d0, 0x0f }, + { 0xc5d1, 0x89 }, + { 0xc057, 0x51 }, + { 0xc054, 0x35 }, + { 0xc053, 0x55 }, + { 0xc052, 0x55 }, + { 0xc051, 0x13 }, + { 0xc050, 0x15 }, + { 0xc060, 0x77 }, + { 0xc061, 0x55 }, + { 0xc063, 0x55 }, + { 0xc065, 0xa5 }, + { 0xc06b, 0x0a }, + { 0xca05, 0xd6 }, + { 0xca25, 0xd6 }, + { 0xcd00, 0x05 }, + { 0xc604, 0x40 }, + { 0xc609, 0x40 }, + { 0xc046, 0xff }, + { 0xc045, 0xff }, + { 0xc044, 0xff }, + { 0xc043, 0xff }, + { 0xc042, 0xff }, + { 0xc041, 0xff }, + { 0xc040, 0xff }, + { 0xcc10, 0x01 }, + { 0xc700, 0xf0 }, + { 0xc701, 0x13 }, + { 0xc901, 0x04 }, + { 0xc900, 0x73 }, + { 0xde03, 0x05 }, + { 0xdd0b, 0x0d }, + { 0xdd0a, 0xff }, + { 0xdd09, 0x0d }, + { 0xdd08, 0xff }, + { 0xc570, 0x08 }, + { 0xe803, 0xbe }, + { 0xc003, 0xc0 }, + { 0xc081, 0xfe }, + { 0xce31, 0x0d }, + { 0xce30, 0xae }, + { 0xce37, 0x0b }, + { 0xce36, 0xd2 }, + { 0xce39, 0x04 }, + { 0xce38, 0x80 }, + { 0xce3f, 0x00 }, + { 0xce3e, 0x00 }, + { 0xd470, 0x8b }, + { 0xd471, 0x18 }, + { 0xc019, 0x10 }, + { 0xd487, 0x3f }, + { 0xd486, 0xc3 }, +}; + +/* + * The 'patch code' is written to the patch code area. + * The patch code area is used for SDCA register expansion flexibility. + */ +static const struct reg_sequence rt1320_patch_code_write[] = { + { 0x10007000, 0x37 }, + { 0x10007001, 0x77 }, + { 0x10007002, 0x00 }, + { 0x10007003, 0x10 }, + { 0x10007004, 0xb7 }, + { 0x10007005, 0xe7 }, + { 0x10007006, 0x00 }, + { 0x10007007, 0x10 }, + { 0x10007008, 0x13 }, + { 0x10007009, 0x07 }, + { 0x1000700a, 0x07 }, + { 0x1000700b, 0x40 }, + { 0x1000700c, 0x23 }, + { 0x1000700d, 0xae }, + { 0x1000700e, 0xe7 }, + { 0x1000700f, 0xda }, + { 0x10007010, 0x37 }, + { 0x10007011, 0x77 }, + { 0x10007012, 0x00 }, + { 0x10007013, 0x10 }, + { 0x10007014, 0x13 }, + { 0x10007015, 0x07 }, + { 0x10007016, 0x47 }, + { 0x10007017, 0x61 }, + { 0x10007018, 0x23 }, + { 0x10007019, 0xa4 }, + { 0x1000701a, 0xe7 }, + { 0x1000701b, 0xde }, + { 0x1000701c, 0x37 }, + { 0x1000701d, 0x77 }, + { 0x1000701e, 0x00 }, + { 0x1000701f, 0x10 }, + { 0x10007020, 0x13 }, + { 0x10007021, 0x07 }, + { 0x10007022, 0x07 }, + { 0x10007023, 0x52 }, + { 0x10007024, 0x23 }, + { 0x10007025, 0xae }, + { 0x10007026, 0xe7 }, + { 0x10007027, 0xde }, + { 0x10007028, 0x37 }, + { 0x10007029, 0x77 }, + { 0x1000702a, 0x00 }, + { 0x1000702b, 0x10 }, + { 0x1000702c, 0x13 }, + { 0x1000702d, 0x07 }, + { 0x1000702e, 0x47 }, + { 0x1000702f, 0x54 }, + { 0x10007030, 0x23 }, + { 0x10007031, 0xaa }, + { 0x10007032, 0xe7 }, + { 0x10007033, 0xe4 }, + { 0x10007034, 0x37 }, + { 0x10007035, 0x87 }, + { 0x10007036, 0x00 }, + { 0x10007037, 0x10 }, + { 0x10007038, 0x13 }, + { 0x10007039, 0x07 }, + { 0x1000703a, 0x47 }, + { 0x1000703b, 0x81 }, + { 0x1000703c, 0x23 }, + { 0x1000703d, 0xa2 }, + { 0x1000703e, 0xe7 }, + { 0x1000703f, 0xe8 }, + { 0x10007040, 0x23 }, + { 0x10007041, 0xa4 }, + { 0x10007042, 0xe7 }, + { 0x10007043, 0xe8 }, + { 0x10007044, 0x37 }, + { 0x10007045, 0x77 }, + { 0x10007046, 0x00 }, + { 0x10007047, 0x10 }, + { 0x10007048, 0x13 }, + { 0x10007049, 0x07 }, + { 0x1000704a, 0x07 }, + { 0x1000704b, 0x59 }, + { 0x1000704c, 0x23 }, + { 0x1000704d, 0xa8 }, + { 0x1000704e, 0xe7 }, + { 0x1000704f, 0xea }, + { 0x10007050, 0x37 }, + { 0x10007051, 0x77 }, + { 0x10007052, 0x00 }, + { 0x10007053, 0x10 }, + { 0x10007054, 0x13 }, + { 0x10007055, 0x07 }, + { 0x10007056, 0x07 }, + { 0x10007057, 0x78 }, + { 0x10007058, 0x23 }, + { 0x10007059, 0xa6 }, + { 0x1000705a, 0xe7 }, + { 0x1000705b, 0xec }, + { 0x1000705c, 0x67 }, + { 0x1000705d, 0x80 }, + { 0x1000705e, 0x00 }, + { 0x1000705f, 0x00 }, + { 0x10007400, 0x37 }, + { 0x10007401, 0xd7 }, + { 0x10007402, 0x00 }, + { 0x10007403, 0x00 }, + { 0x10007404, 0x83 }, + { 0x10007405, 0x27 }, + { 0x10007406, 0x47 }, + { 0x10007407, 0x56 }, + { 0x10007408, 0xb7 }, + { 0x10007409, 0x06 }, + { 0x1000740a, 0x00 }, + { 0x1000740b, 0x02 }, + { 0x1000740c, 0xb3 }, + { 0x1000740d, 0xf7 }, + { 0x1000740e, 0xd7 }, + { 0x1000740f, 0x00 }, + { 0x10007410, 0x63 }, + { 0x10007411, 0x8a }, + { 0x10007412, 0x07 }, + { 0x10007413, 0x00 }, + { 0x10007414, 0x93 }, + { 0x10007415, 0x06 }, + { 0x10007416, 0x10 }, + { 0x10007417, 0x00 }, + { 0x10007418, 0x23 }, + { 0x10007419, 0x83 }, + { 0x1000741a, 0xd1 }, + { 0x1000741b, 0x44 }, + { 0x1000741c, 0x93 }, + { 0x1000741d, 0x07 }, + { 0x1000741e, 0xf0 }, + { 0x1000741f, 0xff }, + { 0x10007420, 0x23 }, + { 0x10007421, 0x22 }, + { 0x10007422, 0xf7 }, + { 0x10007423, 0x56 }, + { 0x10007424, 0x37 }, + { 0x10007425, 0xd7 }, + { 0x10007426, 0x00 }, + { 0x10007427, 0x00 }, + { 0x10007428, 0x83 }, + { 0x10007429, 0x27 }, + { 0x1000742a, 0x47 }, + { 0x1000742b, 0x58 }, + { 0x1000742c, 0x93 }, + { 0x1000742d, 0xf7 }, + { 0x1000742e, 0x17 }, + { 0x1000742f, 0x00 }, + { 0x10007430, 0x63 }, + { 0x10007431, 0x86 }, + { 0x10007432, 0x07 }, + { 0x10007433, 0x00 }, + { 0x10007434, 0x93 }, + { 0x10007435, 0x07 }, + { 0x10007436, 0x10 }, + { 0x10007437, 0x00 }, + { 0x10007438, 0x23 }, + { 0x10007439, 0x22 }, + { 0x1000743a, 0xf7 }, + { 0x1000743b, 0x58 }, + { 0x1000743c, 0xb7 }, + { 0x1000743d, 0xd7 }, + { 0x1000743e, 0x00 }, + { 0x1000743f, 0x00 }, + { 0x10007440, 0x03 }, + { 0x10007441, 0xa7 }, + { 0x10007442, 0x47 }, + { 0x10007443, 0x58 }, + { 0x10007444, 0xb7 }, + { 0x10007445, 0x07 }, + { 0x10007446, 0x00 }, + { 0x10007447, 0x04 }, + { 0x10007448, 0x33 }, + { 0x10007449, 0x77 }, + { 0x1000744a, 0xf7 }, + { 0x1000744b, 0x00 }, + { 0x1000744c, 0x93 }, + { 0x1000744d, 0x07 }, + { 0x1000744e, 0x00 }, + { 0x1000744f, 0x00 }, + { 0x10007450, 0x63 }, + { 0x10007451, 0x0e }, + { 0x10007452, 0x07 }, + { 0x10007453, 0x04 }, + { 0x10007454, 0x37 }, + { 0x10007455, 0x07 }, + { 0x10007456, 0x00 }, + { 0x10007457, 0x11 }, + { 0x10007458, 0x03 }, + { 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0x10007890, 0x83 }, + { 0x10007891, 0x47 }, + { 0x10007892, 0x26 }, + { 0x10007893, 0x04 }, + { 0x10007894, 0x93 }, + { 0x10007895, 0xe7 }, + { 0x10007896, 0x07 }, + { 0x10007897, 0xf8 }, + { 0x10007898, 0x93 }, + { 0x10007899, 0xf7 }, + { 0x1000789a, 0xf7 }, + { 0x1000789b, 0x0f }, + { 0x1000789c, 0x23 }, + { 0x1000789d, 0x01 }, + { 0x1000789e, 0xf6 }, + { 0x1000789f, 0x04 }, + { 0x100078a0, 0x23 }, + { 0x100078a1, 0x08 }, + { 0x100078a2, 0xd7 }, + { 0x100078a3, 0xd8 }, + { 0x100078a4, 0x23 }, + { 0x100078a5, 0x09 }, + { 0x100078a6, 0x07 }, + { 0x100078a7, 0xd8 }, + { 0x100078a8, 0x83 }, + { 0x100078a9, 0x20 }, + { 0x100078aa, 0xc1 }, + { 0x100078ab, 0x00 }, + { 0x100078ac, 0x13 }, + { 0x100078ad, 0x01 }, + { 0x100078ae, 0x01 }, + { 0x100078af, 0x01 }, + { 0x100078b0, 0x67 }, + { 0x100078b1, 0x80 }, + { 0x100078b2, 0x00 }, + { 0x100078b3, 0x00 }, + { 0x3fc2bfc7, 0x00 }, + { 0x3fc2bfc6, 0x00 }, + { 0x3fc2bfc5, 0x00 }, + { 0x3fc2bfc4, 0x01 }, + { 0x0000d486, 0x43 }, + { 0x1000db00, 0x02 }, + { 0x1000db01, 0x00 }, + { 0x1000db02, 0x11 }, + { 0x1000db03, 0x00 }, + { 0x1000db04, 0x00 }, + { 0x1000db05, 0x82 }, + { 0x1000db06, 0x04 }, + { 0x1000db07, 0xf1 }, + { 0x1000db08, 0x00 }, + { 0x1000db09, 0x00 }, + { 0x1000db0a, 0x40 }, + { 0x0000d540, 0x01 }, +}; + +static const struct reg_default rt1320_reg_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, +}; + +static const struct reg_default rt1320_mbq_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, +}; + +static bool rt1320_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc000 ... 0xc086: + case 0xc400 ... 0xc409: + case 0xc480 ... 0xc48f: + case 0xc4c0 ... 0xc4c4: + case 0xc4e0 ... 0xc4e7: + case 0xc500: + case 0xc560 ... 0xc56b: + case 0xc570: + case 0xc580 ... 0xc59a: + case 0xc5b0 ... 0xc60f: + case 0xc640 ... 0xc64f: + case 0xc670: + case 0xc680 ... 0xc683: + case 0xc700 ... 0xc76f: + case 0xc800 ... 0xc801: + case 0xc820: + case 0xc900 ... 0xc901: + case 0xc920 ... 0xc921: + case 0xca00 ... 0xca07: + case 0xca20 ... 0xca27: + case 0xca40 ... 0xca4b: + case 0xca60 ... 0xca68: + case 0xca80 ... 0xca88: + case 0xcb00 ... 0xcb0c: + case 0xcc00 ... 0xcc12: + case 0xcc80 ... 0xcc81: + case 0xcd00: + case 0xcd80 ... 0xcd82: + case 0xce00 ... 0xce4d: + case 0xcf00 ... 0xcf25: + case 0xd000 ... 0xd0ff: + case 0xd100 ... 0xd1ff: + case 0xd200 ... 0xd2ff: + case 0xd300 ... 0xd3ff: + case 0xd400 ... 0xd403: + case 0xd410 ... 0xd417: + case 0xd470 ... 0xd497: + case 0xd4dc ... 0xd50f: + case 0xd520 ... 0xd543: + case 0xd560 ... 0xd5ef: + case 0xd600 ... 0xd663: + case 0xda00 ... 0xda6e: + case 0xda80 ... 0xda9e: + case 0xdb00 ... 0xdb7f: + case 0xdc00: + case 0xdc20 ... 0xdc21: + case 0xdd00 ... 0xdd17: + case 0xde00 ... 0xde09: + case 0xdf00 ... 0xdf1b: + case 0xe000 ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x1000f008: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc402 ... 0xc406: + case 0xc48c ... 0xc48f: + case 0xc560: + case 0xc5b5 ... 0xc5b7: + case 0xc5fc ... 0xc5ff: + case 0xc820: + case 0xc900: + case 0xc920: + case 0xca42: + case 0xca62: + case 0xca82: + case 0xcd00: + case 0xce03: + case 0xce10: + case 0xce14 ... 0xce17: + case 0xce44 ... 0xce49: + case 0xce4c ... 0xce4d: + case 0xcf0c: + case 0xcf10 ... 0xcf25: + case 0xd486 ... 0xd487: + case 0xd4e5 ... 0xd4e6: + case 0xd4e8 ... 0xd4ff: + case 0xd530: + case 0xd540: + case 0xd543: + case 0xdb58 ... 0xdb5f: + case 0xdb60 ... 0xdb63: + case 0xdb68 ... 0xdb69: + case 0xdb6d: + case 0xdb70 ... 0xdb71: + case 0xdb76: + case 0xdb7a: + case 0xdb7c ... 0xdb7f: + case 0xdd0c ... 0xdd13: + case 0xde02: + case 0xdf14 ... 0xdf1b: + case 0xe83c ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x10000000 ... 0x10007fff: + case 0x1000c000 ... 0x1000dfff: + case 0x1000f008: + case 0x3fc2bfc4 ... 0x3fc2bfc7: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): + return true; + default: + return false; + } +} + +static const struct regmap_config rt1320_sdw_regmap = { + .reg_bits = 32, + .val_bits = 8, + .readable_reg = rt1320_readable_register, + .volatile_reg = rt1320_volatile_register, + .max_register = 0x41081488, + .reg_defaults = rt1320_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static const struct regmap_config rt1320_mbq_regmap = { + .name = "sdw-mbq", + .reg_bits = 32, + .val_bits = 16, + .readable_reg = rt1320_mbq_readable_register, + .max_register = 0x41000192, + .reg_defaults = rt1320_mbq_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static int rt1320_read_prop(struct sdw_slave *slave) +{ + struct sdw_slave_prop *prop = &slave->prop; + int nval; + int i, j; + u32 bit; + unsigned long addr; + struct sdw_dpn_prop *dpn; + + /* + * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping + */ + sdw_slave_read_prop(slave); + + prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; + prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; + + prop->paging_support = true; + prop->lane_control_support = true; + + /* first we need to allocate memory for set bits in port lists */ + prop->source_ports = BIT(4); + prop->sink_ports = BIT(1); + + nval = hweight32(prop->source_ports); + prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, + sizeof(*prop->src_dpn_prop), GFP_KERNEL); + if (!prop->src_dpn_prop) + return -ENOMEM; + + i = 0; + dpn = prop->src_dpn_prop; + addr = prop->source_ports; + for_each_set_bit(bit, &addr, 32) { + dpn[i].num = bit; + dpn[i].type = SDW_DPN_FULL; + dpn[i].simple_ch_prep_sm = true; + dpn[i].ch_prep_timeout = 10; + i++; + } + + /* do this again for sink now */ + nval = hweight32(prop->sink_ports); + prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, + sizeof(*prop->sink_dpn_prop), GFP_KERNEL); + if (!prop->sink_dpn_prop) + return -ENOMEM; + + j = 0; + dpn = prop->sink_dpn_prop; + addr = prop->sink_ports; + for_each_set_bit(bit, &addr, 32) { + dpn[j].num = bit; + dpn[j].type = SDW_DPN_FULL; + dpn[j].simple_ch_prep_sm = true; + dpn[j].ch_prep_timeout = 10; + j++; + } + + /* set the timeout values */ + prop->clk_stop_timeout = 64; + + return 0; +} + +static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned int amp_func_status, val, tmp; + + if (rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, false); + regcache_cache_only(rt1320->mbq_regmap, false); + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, true); + regcache_cache_bypass(rt1320->mbq_regmap, true); + } else { + /* + * PM runtime status is marked as 'active' only when a Slave reports as Attached + */ + /* update count of parent 'active' children */ + pm_runtime_set_active(&slave->dev); + } + + pm_runtime_get_noresume(&slave->dev); + + if (rt1320->version_id < 0) { + regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); + rt1320->version_id = val; + } + + regmap_read(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &amp_func_status); + dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); + + /* initialization write */ + if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt1320->first_hw_init)) { + regmap_multi_reg_write(rt1320->regmap, rt1320_blind_write, ARRAY_SIZE(rt1320_blind_write)); + regmap_multi_reg_write(rt1320->regmap, rt1320_patch_code_write, + ARRAY_SIZE(rt1320_patch_code_write)); + + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), + FUNCTION_NEEDS_INITIALIZATION); + } + if (!rt1320->first_hw_init) { + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); + val = (tmp << 8) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); + val = (tmp << 16) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); + val = (tmp << 24) | val; + dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); + /* + * We call the version b which has the new DSP ROM code against version a. + * Therefore, we read the DSP address to check the ID. + */ + if (val == RT1320_VER_B_ID) + rt1320->version_id = RT1320_VB; + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); + } + dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); + + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, false); + regcache_cache_bypass(rt1320->mbq_regmap, false); + regcache_mark_dirty(rt1320->regmap); + regcache_mark_dirty(rt1320->mbq_regmap); + } + + /* Mark Slave initialization complete */ + rt1320->first_hw_init = true; + rt1320->hw_init = true; + + pm_runtime_mark_last_busy(&slave->dev); + pm_runtime_put_autosuspend(&slave->dev); + + dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); + return 0; +} + +static int rt1320_update_status(struct sdw_slave *slave, + enum sdw_slave_status status) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); + + if (status == SDW_SLAVE_UNATTACHED) + rt1320->hw_init = false; + + /* + * Perform initialization only if slave status is present and + * hw_init flag is false + */ + if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) + return 0; + + /* perform I/O transfers required for Slave initialization */ + return rt1320_io_init(&slave->dev, slave); +} + +static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned char ps0 = 0x0, ps3 = 0x3; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps0); + break; + case SND_SOC_DAPM_PRE_PMD: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps3); + break; + default: + break; + } + + return 0; +} + +static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned int read_l, read_r, gain_l_val, gain_r_val; + unsigned int lvalue, rvalue; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); + regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); + + /* L Channel */ + gain_l_val = ucontrol->value.integer.value[0]; + if (gain_l_val > mc->max) + gain_l_val = mc->max; + gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); + gain_l_val &= 0xffff; + + /* R Channel */ + gain_r_val = ucontrol->value.integer.value[1]; + if (gain_r_val > mc->max) + gain_r_val = mc->max; + gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); + gain_r_val &= 0xffff; + + if (lvalue == gain_l_val && rvalue == gain_r_val) + return 0; + + /* Lch*/ + regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); + /* Rch */ + regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + if (read_r == gain_r_val && read_l == gain_l_val) + return 1; + + return -EIO; +} + +static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + + ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); + + if (read_l != read_r) + ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); + else + ctl_r = ctl_l; + + ucontrol->value.integer.value[0] = ctl_l; + ucontrol->value.integer.value[1] = ctl_r; + return 0; +} + +static const char * const rt1320_rx_data_ch_select[] = { + "L,R", + "R,L", + "L,L", + "R,R", + "L,L+R", + "R,L+R", + "L+R,L", + "L+R,R", + "L+R,L+R", +}; + +static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, + rt1320_rx_data_ch_select); + +static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); + +static const struct snd_kcontrol_new rt1320_snd_controls[] = { + SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), + 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), + SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), +}; + +static const struct snd_kcontrol_new rt1320_spk_l_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), + 0, 1, 1); +static const struct snd_kcontrol_new rt1320_spk_r_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), + 0, 1, 1); + +static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), + + /* Digital Interface */ + SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, + rt1320_pde23_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + /* Output */ + SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), + SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), + SND_SOC_DAPM_OUTPUT("SPOL"), + SND_SOC_DAPM_OUTPUT("SPOR"), + + /* Input */ + SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SIGGEN("AEC Gen"), +}; + +static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { + { "FU21", NULL, "DP1RX" }, + { "FU21", NULL, "PDE 23" }, + { "OT23 L", "Switch", "FU21" }, + { "OT23 R", "Switch", "FU21" }, + { "SPOL", NULL, "OT23 L" }, + { "SPOR", NULL, "OT23 R" }, + + { "AEC Data", NULL, "AEC Gen" }, + { "DP4TX", NULL, "AEC Data" }, +}; + +static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, + int direction) +{ + snd_soc_dai_dma_data_set(dai, direction, sdw_stream); + return 0; +} + +static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + snd_soc_dai_set_dma_data(dai, substream, NULL); +} + +static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_config stream_config; + struct sdw_port_config port_config; + struct sdw_stream_runtime *sdw_stream; + int retval; + unsigned int sampling_rate; + + dev_dbg(dai->dev, "%s %s", __func__, dai->name); + sdw_stream = snd_soc_dai_get_dma_data(dai, substream); + + if (!sdw_stream) + return -EINVAL; + + if (!rt1320->sdw_slave) + return -EINVAL; + + /* SoundWire specific configuration */ + snd_sdw_params_to_config(substream, params, &stream_config, &port_config); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (dai->id == RT1320_AIF1) + port_config.num = 1; + else + return -EINVAL; + } else { + if (dai->id == RT1320_AIF1) + port_config.num = 4; + else + return -EINVAL; + } + + retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, + &port_config, 1, sdw_stream); + if (retval) { + dev_err(dai->dev, "%s: Unable to configure port\n", __func__); + return retval; + } + + /* sampling rate configuration */ + switch (params_rate(params)) { + case 16000: + sampling_rate = RT1320_SDCA_RATE_16000HZ; + break; + case 32000: + sampling_rate = RT1320_SDCA_RATE_32000HZ; + break; + case 44100: + sampling_rate = RT1320_SDCA_RATE_44100HZ; + break; + case 48000: + sampling_rate = RT1320_SDCA_RATE_48000HZ; + break; + case 96000: + sampling_rate = RT1320_SDCA_RATE_96000HZ; + break; + case 192000: + sampling_rate = RT1320_SDCA_RATE_192000HZ; + break; + default: + dev_err(component->dev, "%s: Rate %d is not supported\n", + __func__, params_rate(params)); + return -EINVAL; + } + + /* set sampling frequency */ + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), + sampling_rate); + + return 0; +} + +static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_runtime *sdw_stream = + snd_soc_dai_get_dma_data(dai, substream); + + if (!rt1320->sdw_slave) + return -EINVAL; + + sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); + return 0; +} + +/* + * slave_ops: callbacks for get_clock_stop_mode, clock_stop and + * port_prep are not defined for now + */ +static const struct sdw_slave_ops rt1320_slave_ops = { + .read_prop = rt1320_read_prop, + .update_status = rt1320_update_status, +}; + +static int rt1320_sdw_component_probe(struct snd_soc_component *component) +{ + int ret; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + + rt1320->component = component; + + if (!rt1320->first_hw_init) + return 0; + + ret = pm_runtime_resume(component->dev); + dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); + if (ret < 0 && ret != -EACCES) + return ret; + + return 0; +} + +static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { + .probe = rt1320_sdw_component_probe, + .controls = rt1320_snd_controls, + .num_controls = ARRAY_SIZE(rt1320_snd_controls), + .dapm_widgets = rt1320_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), + .dapm_routes = rt1320_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), + .endianness = 1, +}; + +static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { + .hw_params = rt1320_sdw_hw_params, + .hw_free = rt1320_sdw_pcm_hw_free, + .set_stream = rt1320_set_sdw_stream, + .shutdown = rt1320_sdw_shutdown, +}; + +#define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) +#define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver rt1320_sdw_dai[] = { + { + .name = "rt1320-aif1", + .id = RT1320_AIF1, + .playback = { + .stream_name = "DP1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1320_STEREO_RATES, + .formats = RT1320_FORMATS, + }, + .capture = { + .stream_name = "DP4 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT1320_STEREO_RATES, + .formats = RT1320_FORMATS, + }, + .ops = &rt1320_aif_dai_ops, + }, +}; + +static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, + struct regmap *mbq_regmap, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320; + int ret; + + rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); + if (!rt1320) + return -ENOMEM; + + dev_set_drvdata(dev, rt1320); + rt1320->sdw_slave = slave; + rt1320->mbq_regmap = mbq_regmap; + rt1320->regmap = regmap; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + + /* + * Mark hw_init to false + * HW init will be performed when device reports present + */ + rt1320->hw_init = false; + rt1320->first_hw_init = false; + rt1320->version_id = -1; + + ret = devm_snd_soc_register_component(dev, + &soc_component_sdw_rt1320, + rt1320_sdw_dai, + ARRAY_SIZE(rt1320_sdw_dai)); + if (ret < 0) + return ret; + + /* set autosuspend parameters */ + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + + /* make sure the device does not suspend immediately */ + pm_runtime_mark_last_busy(dev); + + pm_runtime_enable(dev); + + /* important note: the device is NOT tagged as 'active' and will remain + * 'suspended' until the hardware is enumerated/initialized. This is required + * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently + * fail with -EACCESS because of race conditions between card creation and enumeration + */ + + dev_dbg(dev, "%s\n", __func__); + + return ret; +} + +static int rt1320_sdw_probe(struct sdw_slave *slave, + const struct sdw_device_id *id) +{ + struct regmap *regmap, *mbq_regmap; + + /* Regmap Initialization */ + mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); + if (IS_ERR(mbq_regmap)) + return PTR_ERR(mbq_regmap); + + regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); +} + +static int rt1320_sdw_remove(struct sdw_slave *slave) +{ + pm_runtime_disable(&slave->dev); + + return 0; +} + +static const struct sdw_device_id rt1320_id[] = { + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), + {}, +}; +MODULE_DEVICE_TABLE(sdw, rt1320_id); + +static int __maybe_unused rt1320_dev_suspend(struct device *dev) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + + if (!rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + return 0; +} + +#define RT1320_PROBE_TIMEOUT 5000 + +static int __maybe_unused rt1320_dev_resume(struct device *dev) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned long time; + + if (!rt1320->first_hw_init) + return 0; + + if (!slave->unattach_request) + goto regmap_sync; + + time = wait_for_completion_timeout(&slave->initialization_complete, + msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); + if (!time) { + dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); + return -ETIMEDOUT; + } + +regmap_sync: + slave->unattach_request = 0; + regcache_cache_only(rt1320->regmap, false); + regcache_sync(rt1320->regmap); + regcache_cache_only(rt1320->mbq_regmap, false); + regcache_sync(rt1320->mbq_regmap); + return 0; +} + +static const struct dev_pm_ops rt1320_pm = { + SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) + SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) +}; + +static struct sdw_driver rt1320_sdw_driver = { + .driver = { + .name = "rt1320-sdca", + .pm = &rt1320_pm, + }, + .probe = rt1320_sdw_probe, + .remove = rt1320_sdw_remove, + .ops = &rt1320_slave_ops, + .id_table = rt1320_id, +}; +module_sdw_driver(rt1320_sdw_driver); + +MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); +MODULE_AUTHOR("Shuming Fan <shumingf(a)realtek.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/rt1320-sdw.h b/sound/soc/codecs/rt1320-sdw.h new file mode 100644 index 000000000000..b23228e74568 --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * rt1320-sdw.h -- RT1320 SDCA ALSA SoC audio driver header + * + * Copyright(c) 2024 Realtek Semiconductor Corp. + */ + +#ifndef __RT1320_SDW_H__ +#define __RT1320_SDW_H__ + +#include <linux/regmap.h> +#include <linux/soundwire/sdw.h> +#include <linux/soundwire/sdw_type.h> +#include <linux/soundwire/sdw_registers.h> +#include <sound/soc.h> + +/* imp-defined registers */ +#define RT1320_DEV_VERSION_ID_1 0xc404 + +#define RT1320_KR0_STATUS_CNT 0x1000f008 +#define RT1320_HIFI_VER_0 0x3fe2e000 +#define RT1320_HIFI_VER_1 0x3fe2e001 +#define RT1320_HIFI_VER_2 0x3fe2e002 +#define RT1320_HIFI_VER_3 0x3fe2e003 + +/* RT1320 SDCA Control - function number */ +#define FUNC_NUM_AMP 0x04 + +/* RT1320 SDCA entity */ +#define RT1320_SDCA_ENT0 0x00 +#define RT1320_SDCA_ENT_PDE11 0x2a +#define RT1320_SDCA_ENT_PDE23 0x33 +#define RT1320_SDCA_ENT_PDE27 0x27 +#define RT1320_SDCA_ENT_FU14 0x32 +#define RT1320_SDCA_ENT_FU21 0x03 +#define RT1320_SDCA_ENT_FU113 0x30 +#define RT1320_SDCA_ENT_CS14 0x13 +#define RT1320_SDCA_ENT_CS21 0x21 +#define RT1320_SDCA_ENT_CS113 0x12 +#define RT1320_SDCA_ENT_SAPU 0x29 +#define RT1320_SDCA_ENT_PPU21 0x04 + +/* RT1320 SDCA control */ +#define RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10 +#define RT1320_SDCA_CTL_REQ_POWER_STATE 0x01 +#define RT1320_SDCA_CTL_FU_MUTE 0x01 +#define RT1320_SDCA_CTL_FU_VOLUME 0x02 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_MODE 0x10 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11 +#define RT1320_SDCA_CTL_POSTURE_NUMBER 0x10 +#define RT1320_SDCA_CTL_FUNC_STATUS 0x10 + +/* RT1320 SDCA channel */ +#define CH_01 0x01 +#define CH_02 0x02 + +/* Function_Status */ +#define FUNCTION_NEEDS_INITIALIZATION BIT(5) + +/* Sample Frequency Index */ +#define RT1320_SDCA_RATE_16000HZ 0x04 +#define RT1320_SDCA_RATE_32000HZ 0x07 +#define RT1320_SDCA_RATE_44100HZ 0x08 +#define RT1320_SDCA_RATE_48000HZ 0x09 +#define RT1320_SDCA_RATE_96000HZ 0x0b +#define RT1320_SDCA_RATE_192000HZ 0x0d + +enum { + RT1320_AIF1, +}; + +/* + * The version id will be useful to distinguish the capability between the different IC versions. + * Currently, VA and VB have different DSP FW versions. + */ +enum rt1320_version_id { + RT1320_VA, + RT1320_VB, +}; + +#define RT1320_VER_B_ID 0x07392238 + +struct rt1320_sdw_priv { + struct snd_soc_component *component; + struct regmap *regmap; + struct regmap *mbq_regmap; + struct sdw_slave *sdw_slave; + struct sdw_bus_params params; + bool hw_init; + bool first_hw_init; + int version_id; +}; + +#endif /* __RT1320_SDW_H__ */ -- 2.34.1

3 3

[PATCH v3 0/4] ASoC: qcom: x1e80100: Correct channel mapping
by Krzysztof Kozlowski 20 May '24

20 May '24

Hi, First patch is a build dependency. Changes in v3: - Add missing Charles' Ack - Link to v2: https://lore.kernel.org/r/20240508-asoc-x1e80100-4-channel-mapping-v2-0-cce… Changes in v2: - Re-work most of the idea according to Srini comments: set channel mapping for backend DAIs, not frontend. - Patch #1: no changes - Patch #2 is entirely replaced - now channel mapping is implemented in q6apm-lpass-dais. - Patch #3: rework to new approach, but most of the code stays. - Patch #4: rework significantly, because only backend DAIs is now affected. - Link to v1: https://lore.kernel.org/r/20240507-asoc-x1e80100-4-channel-mapping-v1-0-b12… Description =========== X1E80100 CRD is the first board, which comes with four speakers, so we still keep fixing and adding missing pieces. The board has speaker arranged as left front+back and then right front+back. Using default channel mapping causes front right speaker to play left back stream. Adjust the channel maps for frontend DAIs to fix stereo and four-channel playback. Best regards, Krzysztof --- Krzysztof Kozlowski (4): ASoC: Constify channel mapping array arguments in set_channel_map() ASoC: qcom: q6apm-lpass-dais: Implement proper channel mapping ASoC: qcom: qdsp6: Set channel mapping instead of fixed defaults ASoC: qcom: x1e80100: Correct channel mapping include/sound/cs35l41.h | 4 ++-- include/sound/soc-dai.h | 8 ++++---- sound/soc/codecs/adau7118.c | 6 ++++-- sound/soc/codecs/cs35l41-lib.c | 4 ++-- sound/soc/codecs/cs35l41.c | 3 ++- sound/soc/codecs/max98504.c | 6 ++++-- sound/soc/codecs/wcd9335.c | 6 ++++-- sound/soc/codecs/wcd934x.c | 6 ++++-- sound/soc/qcom/qdsp6/audioreach.c | 30 +++++++----------------------- sound/soc/qcom/qdsp6/audioreach.h | 2 +- sound/soc/qcom/qdsp6/q6afe-dai.c | 16 ++++++++++------ sound/soc/qcom/qdsp6/q6apm-dai.c | 2 ++ sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 21 +++++++++++++-------- sound/soc/qcom/x1e80100.c | 18 ++++++++++++++++++ sound/soc/soc-dai.c | 4 ++-- 15 files changed, 79 insertions(+), 57 deletions(-) --- base-commit: 2b84edefcad14934796fad37b16512b6a2ca467e change-id: 20240507-asoc-x1e80100-4-channel-mapping-ea5f02b9e678 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org>

2 8

[PATCH 2/2] ASoC: fsl_mqs: Add i.MX95 platform support
by Shengjiu Wang 20 May '24

20 May '24

On i.MX95 there are two MQS instances, so "fsl,mqs-ctrl" need to be used to distinguish them. Only can list the settings of one instance in soc data. As "fsl,mqs-ctrl" is optional, if this property does not exist, the driver will use soc data to configure the MQS module. On i.MX95 one instance in wakeup-mix is supported by this commit, another instance in always-on-mix is not supported, which depends on System Manager function readiness, but it can also benefit from the new property. Signed-off-by: Shengjiu Wang <shengjiu.wang(a)nxp.com> --- sound/soc/fsl/fsl_mqs.c | 106 ++++++++++++++++++++++++++++++++-------- 1 file changed, 86 insertions(+), 20 deletions(-) diff --git a/sound/soc/fsl/fsl_mqs.c b/sound/soc/fsl/fsl_mqs.c index 60929c36a0e3..3d69ac5736c8 100644 --- a/sound/soc/fsl/fsl_mqs.c +++ b/sound/soc/fsl/fsl_mqs.c @@ -28,10 +28,16 @@ #define MQS_CLK_DIV_MASK (0xFF << 0) #define MQS_CLK_DIV_SHIFT (0) +enum reg_type { + TYPE_REG_OWN, /* module own register space */ + TYPE_REG_GPR, /* register in GPR space */ + TYPE_REG_SM, /* System Manager controls the register */ +}; + /** * struct fsl_mqs_soc_data - soc specific data * - * @use_gpr: control register is in General Purpose Register group + * @type: control register space type * @ctrl_off: control register offset * @en_mask: enable bit mask * @en_shift: enable bit shift @@ -43,7 +49,7 @@ * @div_shift: clock divider bit shift */ struct fsl_mqs_soc_data { - bool use_gpr; + enum reg_type type; int ctrl_off; int en_mask; int en_shift; @@ -60,7 +66,7 @@ struct fsl_mqs { struct regmap *regmap; struct clk *mclk; struct clk *ipg; - const struct fsl_mqs_soc_data *soc; + struct fsl_mqs_soc_data soc; unsigned int reg_mqs_ctrl; }; @@ -90,11 +96,11 @@ static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, res = mclk_rate % (32 * lrclk * 2 * 8); if (res == 0 && div > 0 && div <= 256) { - regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, - mqs_priv->soc->div_mask, - (div - 1) << mqs_priv->soc->div_shift); - regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, - mqs_priv->soc->osr_mask, 0); + regmap_update_bits(mqs_priv->regmap, mqs_priv->soc.ctrl_off, + mqs_priv->soc.div_mask, + (div - 1) << mqs_priv->soc.div_shift); + regmap_update_bits(mqs_priv->regmap, mqs_priv->soc.ctrl_off, + mqs_priv->soc.osr_mask, 0); } else { dev_err(component->dev, "can't get proper divider\n"); } @@ -135,9 +141,9 @@ static int fsl_mqs_startup(struct snd_pcm_substream *substream, struct snd_soc_component *component = dai->component; struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); - regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, - mqs_priv->soc->en_mask, - 1 << mqs_priv->soc->en_shift); + regmap_update_bits(mqs_priv->regmap, mqs_priv->soc.ctrl_off, + mqs_priv->soc.en_mask, + 1 << mqs_priv->soc.en_shift); return 0; } @@ -147,8 +153,8 @@ static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, struct snd_soc_component *component = dai->component; struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); - regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, - mqs_priv->soc->en_mask, 0); + regmap_update_bits(mqs_priv->regmap, mqs_priv->soc.ctrl_off, + mqs_priv->soc.en_mask, 0); } static const struct snd_soc_component_driver soc_codec_fsl_mqs = { @@ -182,9 +188,50 @@ static const struct regmap_config fsl_mqs_regmap_config = { .cache_type = REGCACHE_NONE, }; +static int fsl_mqs_set_soc_data_from_of(struct device_node *np, + struct fsl_mqs_soc_data *soc) +{ + char *propname = "fsl,mqs-ctrl"; + int elems, index; + int ret; + + elems = of_property_count_u32_elems(np, propname); + if (elems == 6) { + index = 0; + + ret = of_property_read_u32_index(np, propname, index++, &soc->type); + if (ret) + return -EINVAL; + + ret = of_property_read_u32_index(np, propname, index++, &soc->ctrl_off); + if (ret) + return -EINVAL; + ret = of_property_read_u32_index(np, propname, index++, &soc->en_shift); + if (ret) + return -EINVAL; + ret = of_property_read_u32_index(np, propname, index++, &soc->rst_shift); + if (ret) + return -EINVAL; + ret = of_property_read_u32_index(np, propname, index++, &soc->osr_shift); + if (ret) + return -EINVAL; + ret = of_property_read_u32_index(np, propname, index++, &soc->div_shift); + if (ret) + return -EINVAL; + + soc->en_mask = 1 << soc->en_shift; + soc->rst_mask = 1 << soc->rst_shift; + soc->osr_mask = 1 << soc->osr_shift; + soc->div_mask = 0xFF << soc->div_shift; + } + + return 0; +} + static int fsl_mqs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + const struct fsl_mqs_soc_data *soc_data; struct device_node *gpr_np = NULL; struct fsl_mqs *mqs_priv; void __iomem *regs; @@ -198,9 +245,14 @@ static int fsl_mqs_probe(struct platform_device *pdev) * But in i.MX8QM/i.MX8QXP the control register is moved * to its own domain. */ - mqs_priv->soc = of_device_get_match_data(&pdev->dev); + soc_data = of_device_get_match_data(&pdev->dev); + mqs_priv->soc = *soc_data; + + ret = fsl_mqs_set_soc_data_from_of(np, &mqs_priv->soc); + if (ret) + return ret; - if (mqs_priv->soc->use_gpr) { + if (mqs_priv->soc.type == TYPE_REG_GPR) { gpr_np = of_parse_phandle(np, "gpr", 0); if (!gpr_np) { dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); @@ -278,7 +330,7 @@ static int fsl_mqs_runtime_resume(struct device *dev) return ret; } - regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl); + regmap_write(mqs_priv->regmap, mqs_priv->soc.ctrl_off, mqs_priv->reg_mqs_ctrl); return 0; } @@ -286,7 +338,7 @@ static int fsl_mqs_runtime_suspend(struct device *dev) { struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); - regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl); + regmap_read(mqs_priv->regmap, mqs_priv->soc.ctrl_off, &mqs_priv->reg_mqs_ctrl); clk_disable_unprepare(mqs_priv->mclk); clk_disable_unprepare(mqs_priv->ipg); @@ -304,7 +356,7 @@ static const struct dev_pm_ops fsl_mqs_pm_ops = { }; static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = { - .use_gpr = false, + .type = TYPE_REG_OWN, .ctrl_off = REG_MQS_CTRL, .en_mask = MQS_EN_MASK, .en_shift = MQS_EN_SHIFT, @@ -317,7 +369,7 @@ static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = { }; static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = { - .use_gpr = true, + .type = TYPE_REG_GPR, .ctrl_off = IOMUXC_GPR2, .en_mask = IMX6SX_GPR2_MQS_EN_MASK, .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT, @@ -330,7 +382,7 @@ static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = { }; static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = { - .use_gpr = true, + .type = TYPE_REG_GPR, .ctrl_off = 0x20, .en_mask = BIT(1), .en_shift = 1, @@ -342,10 +394,24 @@ static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = { .div_shift = 8, }; +static const struct fsl_mqs_soc_data fsl_mqs_imx95_data = { + .type = TYPE_REG_GPR, + .ctrl_off = 0x0, + .en_mask = BIT(2), + .en_shift = 2, + .rst_mask = BIT(3), + .rst_shift = 3, + .osr_mask = BIT(4), + .osr_shift = 4, + .div_mask = GENMASK(16, 9), + .div_shift = 9, +}; + static const struct of_device_id fsl_mqs_dt_ids[] = { { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data }, { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data }, { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data }, + { .compatible = "fsl,imx95-mqs", .data = &fsl_mqs_imx95_data }, {} }; MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); -- 2.34.1

1 0

[PATCH] Remove redundant description in struct segdist_code
by Abhishek Tamboli 20 May '24

20 May '24

Remove redundant description, ensuring the documentation accurately reflects the structure's members. Signed-off-by: Abhishek Tamboli <abhishektamboli9(a)gmail.com> --- The documentation for struct segdist_code contained an excess description for the member 'segdist_codes', which is not a member of the struct but rather an array of segdist_code structs. drivers/slimbus/stream.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/slimbus/stream.c b/drivers/slimbus/stream.c index 1d6b38657917..9e7983507f19 100644 --- a/drivers/slimbus/stream.c +++ b/drivers/slimbus/stream.c @@ -18,7 +18,6 @@ * and the first slot of the next consecutive Segment. * @segdist_code: Segment Distribution Code SD[11:0] * @seg_offset_mask: Segment offset mask in SD[11:0] - * @segdist_codes: List of all possible Segmet Distribution codes. */ static const struct segdist_code { int ratem; -- 2.25.1

1 0

Re: [PATCH v2] ASoC: rt1320: Add RT1320 SDCA vendor-specific driver
by Mark Brown 20 May '24

20 May '24

On Fri, May 17, 2024 at 09:38:55AM -0500, Pierre-Louis Bossart wrote: > > +static const struct reg_sequence rt1320_blind_write[] = { > > + { 0xc003, 0xe0 }, > ... > > + { 0xd486, 0xc3 }, > > +}; > I would add a comment that the 'blind writes' is an SDCA term to deal > with platform-specific initialization, but in this case it seems that > all the addresses targeted are in the vendor-specific space TBH it seems perfectly intelligable without knowing anything about SCDA.

1 0

[PATCH] ASoC: rt1320: Add RT1320 SDCA vendor-specific driver
by shumingf＠realtek.com 20 May '24

20 May '24

From: Shuming Fan <shumingf(a)realtek.com> This is the initial amplifier driver for rt1320. Signed-off-by: Shuming Fan <shumingf(a)realtek.com> --- sound/soc/codecs/Kconfig | 7 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt1320-sdw.c | 2213 +++++++++++++++++++++++++++++++++ sound/soc/codecs/rt1320-sdw.h | 92 ++ 4 files changed, 2314 insertions(+) create mode 100644 sound/soc/codecs/rt1320-sdw.c create mode 100644 sound/soc/codecs/rt1320-sdw.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 4afc43d3f71f..7502581d1631 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -222,6 +222,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_RT1308_SDW imply SND_SOC_RT1316_SDW imply SND_SOC_RT1318_SDW + imply SND_SOC_RT1320_SDW imply SND_SOC_RT9120 imply SND_SOC_RTQ9128 imply SND_SOC_SDW_MOCKUP @@ -1575,6 +1576,12 @@ config SND_SOC_RT1318_SDW depends on SOUNDWIRE select REGMAP_SOUNDWIRE +config SND_SOC_RT1320_SDW + tristate "Realtek RT1320 Codec - SDW" + depends on SOUNDWIRE + select REGMAP_SOUNDWIRE + select REGMAP_SOUNDWIRE_MBQ + config SND_SOC_RT5514 tristate depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index b4df22186e25..f9eb7c073a00 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -222,6 +222,7 @@ snd-soc-rt1308-y := rt1308.o snd-soc-rt1308-sdw-y := rt1308-sdw.o snd-soc-rt1316-sdw-y := rt1316-sdw.o snd-soc-rt1318-sdw-y := rt1318-sdw.o +snd-soc-rt1320-sdw-y := rt1320-sdw.o snd-soc-rt274-y := rt274.o snd-soc-rt286-y := rt286.o snd-soc-rt298-y := rt298.o @@ -614,6 +615,7 @@ obj-$(CONFIG_SND_SOC_RT1308) += snd-soc-rt1308.o obj-$(CONFIG_SND_SOC_RT1308_SDW) += snd-soc-rt1308-sdw.o obj-$(CONFIG_SND_SOC_RT1316_SDW) += snd-soc-rt1316-sdw.o obj-$(CONFIG_SND_SOC_RT1318_SDW) += snd-soc-rt1318-sdw.o +obj-$(CONFIG_SND_SOC_RT1320_SDW) += snd-soc-rt1320-sdw.o obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o diff --git a/sound/soc/codecs/rt1320-sdw.c b/sound/soc/codecs/rt1320-sdw.c new file mode 100644 index 000000000000..167a13b2a022 --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.c @@ -0,0 +1,2213 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver +// +// Copyright(c) 2024 Realtek Semiconductor Corp. +// +// +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/pm_runtime.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include <linux/dmi.h> +#include <linux/firmware.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/sdw.h> +#include "rt1320-sdw.h" + +static const struct reg_sequence rt1320_blind_write[] = { + { 0xc003, 0xe0 }, + { 0xc01b, 0xfc }, + { 0xc5c3, 0xf2 }, + { 0xc5c2, 0x00 }, + { 0xc5c6, 0x10 }, + { 0xc5c4, 0x12 }, + { 0xc5c8, 0x03 }, + { 0xc5d8, 0x0a }, + { 0xc5f7, 0x22 }, + { 0xc5f6, 0x22 }, + { 0xc5d0, 0x0f }, + { 0xc5d1, 0x89 }, + { 0xc057, 0x51 }, + { 0xc054, 0x35 }, + { 0xc053, 0x55 }, + { 0xc052, 0x55 }, + { 0xc051, 0x13 }, + { 0xc050, 0x15 }, + { 0xc060, 0x77 }, + { 0xc061, 0x55 }, + { 0xc063, 0x55 }, + { 0xc065, 0xa5 }, + { 0xc06b, 0x0a }, + { 0xca05, 0xd6 }, + { 0xca25, 0xd6 }, + { 0xcd00, 0x05 }, + { 0xc604, 0x40 }, + { 0xc609, 0x40 }, + { 0xc046, 0xff }, + { 0xc045, 0xff }, + { 0xc044, 0xff }, + { 0xc043, 0xff }, + { 0xc042, 0xff }, + { 0xc041, 0xff }, + { 0xc040, 0xff }, + { 0xcc10, 0x01 }, + { 0xc700, 0xf0 }, + { 0xc701, 0x13 }, + { 0xc901, 0x04 }, + { 0xc900, 0x73 }, + { 0xde03, 0x05 }, + { 0xdd0b, 0x0d }, + { 0xdd0a, 0xff }, + { 0xdd09, 0x0d }, + { 0xdd08, 0xff }, + { 0xc570, 0x08 }, + { 0xe803, 0xbe }, + { 0xc003, 0xc0 }, + { 0xc081, 0xfe }, + { 0xce31, 0x0d }, + { 0xce30, 0xae }, + { 0xce37, 0x0b }, + { 0xce36, 0xd2 }, + { 0xce39, 0x04 }, + { 0xce38, 0x80 }, + { 0xce3f, 0x00 }, + { 0xce3e, 0x00 }, + { 0xd470, 0x8b }, + { 0xd471, 0x18 }, + { 0xc019, 0x10 }, + { 0xd487, 0x3f }, + { 0xd486, 0xc3 }, +}; + +static const struct reg_sequence rt1320_patch_code_write[] = { + { 0x10007000, 0x37 }, + { 0x10007001, 0x77 }, + { 0x10007002, 0x00 }, + { 0x10007003, 0x10 }, + { 0x10007004, 0xb7 }, + { 0x10007005, 0xe7 }, + { 0x10007006, 0x00 }, + { 0x10007007, 0x10 }, + { 0x10007008, 0x13 }, + { 0x10007009, 0x07 }, + { 0x1000700a, 0x07 }, + { 0x1000700b, 0x40 }, + { 0x1000700c, 0x23 }, + { 0x1000700d, 0xae }, + { 0x1000700e, 0xe7 }, + { 0x1000700f, 0xda }, + { 0x10007010, 0x37 }, + { 0x10007011, 0x77 }, + { 0x10007012, 0x00 }, + { 0x10007013, 0x10 }, + { 0x10007014, 0x13 }, + { 0x10007015, 0x07 }, + { 0x10007016, 0x47 }, + { 0x10007017, 0x61 }, + { 0x10007018, 0x23 }, + { 0x10007019, 0xa4 }, + { 0x1000701a, 0xe7 }, + { 0x1000701b, 0xde }, + { 0x1000701c, 0x37 }, + { 0x1000701d, 0x77 }, + { 0x1000701e, 0x00 }, + { 0x1000701f, 0x10 }, + { 0x10007020, 0x13 }, + { 0x10007021, 0x07 }, + { 0x10007022, 0x07 }, + { 0x10007023, 0x52 }, + { 0x10007024, 0x23 }, + { 0x10007025, 0xae }, + { 0x10007026, 0xe7 }, + { 0x10007027, 0xde }, + { 0x10007028, 0x37 }, + { 0x10007029, 0x77 }, + { 0x1000702a, 0x00 }, + { 0x1000702b, 0x10 }, + { 0x1000702c, 0x13 }, + { 0x1000702d, 0x07 }, + { 0x1000702e, 0x47 }, + { 0x1000702f, 0x54 }, + { 0x10007030, 0x23 }, + { 0x10007031, 0xaa }, + { 0x10007032, 0xe7 }, + { 0x10007033, 0xe4 }, + { 0x10007034, 0x37 }, + { 0x10007035, 0x87 }, + { 0x10007036, 0x00 }, + { 0x10007037, 0x10 }, + { 0x10007038, 0x13 }, + { 0x10007039, 0x07 }, + { 0x1000703a, 0x47 }, + { 0x1000703b, 0x81 }, + { 0x1000703c, 0x23 }, + { 0x1000703d, 0xa2 }, + { 0x1000703e, 0xe7 }, + { 0x1000703f, 0xe8 }, + { 0x10007040, 0x23 }, + { 0x10007041, 0xa4 }, + { 0x10007042, 0xe7 }, + { 0x10007043, 0xe8 }, + { 0x10007044, 0x37 }, + { 0x10007045, 0x77 }, + { 0x10007046, 0x00 }, + { 0x10007047, 0x10 }, + { 0x10007048, 0x13 }, + { 0x10007049, 0x07 }, + { 0x1000704a, 0x07 }, + { 0x1000704b, 0x59 }, + { 0x1000704c, 0x23 }, + { 0x1000704d, 0xa8 }, + { 0x1000704e, 0xe7 }, + { 0x1000704f, 0xea }, + { 0x10007050, 0x37 }, + { 0x10007051, 0x77 }, + { 0x10007052, 0x00 }, + { 0x10007053, 0x10 }, + { 0x10007054, 0x13 }, + { 0x10007055, 0x07 }, + { 0x10007056, 0x07 }, + { 0x10007057, 0x78 }, + { 0x10007058, 0x23 }, + { 0x10007059, 0xa6 }, + { 0x1000705a, 0xe7 }, + { 0x1000705b, 0xec }, + { 0x1000705c, 0x67 }, + { 0x1000705d, 0x80 }, + { 0x1000705e, 0x00 }, + { 0x1000705f, 0x00 }, + { 0x10007400, 0x37 }, + { 0x10007401, 0xd7 }, + { 0x10007402, 0x00 }, + { 0x10007403, 0x00 }, + { 0x10007404, 0x83 }, + { 0x10007405, 0x27 }, + { 0x10007406, 0x47 }, + { 0x10007407, 0x56 }, + { 0x10007408, 0xb7 }, + { 0x10007409, 0x06 }, + { 0x1000740a, 0x00 }, + { 0x1000740b, 0x02 }, + { 0x1000740c, 0xb3 }, + { 0x1000740d, 0xf7 }, + { 0x1000740e, 0xd7 }, + { 0x1000740f, 0x00 }, + { 0x10007410, 0x63 }, + { 0x10007411, 0x8a }, + { 0x10007412, 0x07 }, + { 0x10007413, 0x00 }, + { 0x10007414, 0x93 }, + { 0x10007415, 0x06 }, + { 0x10007416, 0x10 }, + { 0x10007417, 0x00 }, + { 0x10007418, 0x23 }, + { 0x10007419, 0x83 }, + { 0x1000741a, 0xd1 }, + { 0x1000741b, 0x44 }, + { 0x1000741c, 0x93 }, + { 0x1000741d, 0x07 }, + { 0x1000741e, 0xf0 }, + { 0x1000741f, 0xff }, + { 0x10007420, 0x23 }, + { 0x10007421, 0x22 }, + { 0x10007422, 0xf7 }, + { 0x10007423, 0x56 }, + { 0x10007424, 0x37 }, + { 0x10007425, 0xd7 }, + { 0x10007426, 0x00 }, + { 0x10007427, 0x00 }, + { 0x10007428, 0x83 }, + { 0x10007429, 0x27 }, + { 0x1000742a, 0x47 }, + { 0x1000742b, 0x58 }, + { 0x1000742c, 0x93 }, + { 0x1000742d, 0xf7 }, + { 0x1000742e, 0x17 }, + { 0x1000742f, 0x00 }, + { 0x10007430, 0x63 }, + { 0x10007431, 0x86 }, + { 0x10007432, 0x07 }, + { 0x10007433, 0x00 }, + { 0x10007434, 0x93 }, + { 0x10007435, 0x07 }, + { 0x10007436, 0x10 }, + { 0x10007437, 0x00 }, + { 0x10007438, 0x23 }, + { 0x10007439, 0x22 }, + { 0x1000743a, 0xf7 }, + { 0x1000743b, 0x58 }, + { 0x1000743c, 0xb7 }, + { 0x1000743d, 0xd7 }, + { 0x1000743e, 0x00 }, + { 0x1000743f, 0x00 }, + { 0x10007440, 0x03 }, + { 0x10007441, 0xa7 }, + { 0x10007442, 0x47 }, + { 0x10007443, 0x58 }, + { 0x10007444, 0xb7 }, + { 0x10007445, 0x07 }, + { 0x10007446, 0x00 }, + { 0x10007447, 0x04 }, + { 0x10007448, 0x33 }, + { 0x10007449, 0x77 }, + { 0x1000744a, 0xf7 }, + { 0x1000744b, 0x00 }, + { 0x1000744c, 0x93 }, + { 0x1000744d, 0x07 }, + { 0x1000744e, 0x00 }, + { 0x1000744f, 0x00 }, + { 0x10007450, 0x63 }, + { 0x10007451, 0x0e }, + { 0x10007452, 0x07 }, + { 0x10007453, 0x04 }, + { 0x10007454, 0x37 }, + { 0x10007455, 0x07 }, + { 0x10007456, 0x00 }, + { 0x10007457, 0x11 }, + { 0x10007458, 0x03 }, + { 0x10007459, 0x47 }, + { 0x1000745a, 0x87 }, + { 0x1000745b, 0x0e }, + { 0x1000745c, 0x93 }, + { 0x1000745d, 0x06 }, + { 0x1000745e, 0x40 }, + { 0x1000745f, 0x00 }, + { 0x10007460, 0x13 }, + { 0x10007461, 0x77 }, + { 0x10007462, 0xf7 }, + { 0x10007463, 0x0f }, + { 0x10007464, 0x63 }, + { 0x10007465, 0x02 }, + { 0x10007466, 0xd7 }, + { 0x10007467, 0x0a }, + { 0x10007468, 0x93 }, + { 0x10007469, 0x06 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}, + { 0x100078a1, 0x08 }, + { 0x100078a2, 0xd7 }, + { 0x100078a3, 0xd8 }, + { 0x100078a4, 0x23 }, + { 0x100078a5, 0x09 }, + { 0x100078a6, 0x07 }, + { 0x100078a7, 0xd8 }, + { 0x100078a8, 0x83 }, + { 0x100078a9, 0x20 }, + { 0x100078aa, 0xc1 }, + { 0x100078ab, 0x00 }, + { 0x100078ac, 0x13 }, + { 0x100078ad, 0x01 }, + { 0x100078ae, 0x01 }, + { 0x100078af, 0x01 }, + { 0x100078b0, 0x67 }, + { 0x100078b1, 0x80 }, + { 0x100078b2, 0x00 }, + { 0x100078b3, 0x00 }, + { 0x3fc2bfc7, 0x00 }, + { 0x3fc2bfc6, 0x00 }, + { 0x3fc2bfc5, 0x00 }, + { 0x3fc2bfc4, 0x01 }, + { 0x0000d486, 0x43 }, + { 0x1000db00, 0x02 }, + { 0x1000db01, 0x00 }, + { 0x1000db02, 0x11 }, + { 0x1000db03, 0x00 }, + { 0x1000db04, 0x00 }, + { 0x1000db05, 0x82 }, + { 0x1000db06, 0x04 }, + { 0x1000db07, 0xf1 }, + { 0x1000db08, 0x00 }, + { 0x1000db09, 0x00 }, + { 0x1000db0a, 0x40 }, + { 0x0000d540, 0x01 }, +}; + +static const struct reg_default rt1320_reg_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, +}; + +static const struct reg_default rt1320_mbq_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, +}; + +static bool rt1320_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc000 ... 0xc086: + case 0xc400 ... 0xc409: + case 0xc480 ... 0xc48f: + case 0xc4c0 ... 0xc4c4: + case 0xc4e0 ... 0xc4e7: + case 0xc500: + case 0xc560 ... 0xc56b: + case 0xc570: + case 0xc580 ... 0xc59a: + case 0xc5b0 ... 0xc60f: + case 0xc640 ... 0xc64f: + case 0xc670: + case 0xc680 ... 0xc683: + case 0xc700 ... 0xc76f: + case 0xc800 ... 0xc801: + case 0xc820: + case 0xc900 ... 0xc901: + case 0xc920 ... 0xc921: + case 0xca00 ... 0xca07: + case 0xca20 ... 0xca27: + case 0xca40 ... 0xca4b: + case 0xca60 ... 0xca68: + case 0xca80 ... 0xca88: + case 0xcb00 ... 0xcb0c: + case 0xcc00 ... 0xcc12: + case 0xcc80 ... 0xcc81: + case 0xcd00: + case 0xcd80 ... 0xcd82: + case 0xce00 ... 0xce4d: + case 0xcf00 ... 0xcf25: + case 0xd000 ... 0xd0ff: + case 0xd100 ... 0xd1ff: + case 0xd200 ... 0xd2ff: + case 0xd300 ... 0xd3ff: + case 0xd400 ... 0xd403: + case 0xd410 ... 0xd417: + case 0xd470 ... 0xd497: + case 0xd4dc ... 0xd50f: + case 0xd520 ... 0xd543: + case 0xd560 ... 0xd5ef: + case 0xd600 ... 0xd663: + case 0xda00 ... 0xda6e: + case 0xda80 ... 0xda9e: + case 0xdb00 ... 0xdb7f: + case 0xdc00: + case 0xdc20 ... 0xdc21: + case 0xdd00 ... 0xdd17: + case 0xde00 ... 0xde09: + case 0xdf00 ... 0xdf1b: + case 0xe000 ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x1000f008: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc402 ... 0xc406: + case 0xc48c ... 0xc48f: + case 0xc560: + case 0xc5b5 ... 0xc5b7: + case 0xc5fc ... 0xc5ff: + case 0xc820: + case 0xc900: + case 0xc920: + case 0xca42: + case 0xca62: + case 0xca82: + case 0xcd00: + case 0xce03: + case 0xce10: + case 0xce14 ... 0xce17: + case 0xce44 ... 0xce49: + case 0xce4c ... 0xce4d: + case 0xcf0c: + case 0xcf10 ... 0xcf25: + case 0xd486 ... 0xd487: + case 0xd4e5 ... 0xd4e6: + case 0xd4e8 ... 0xd4ff: + case 0xd530: + case 0xd540: + case 0xd543: + case 0xdb58 ... 0xdb5f: + case 0xdb60 ... 0xdb63: + case 0xdb68 ... 0xdb69: + case 0xdb6d: + case 0xdb70 ... 0xdb71: + case 0xdb76: + case 0xdb7a: + case 0xdb7c ... 0xdb7f: + case 0xdd0c ... 0xdd13: + case 0xde02: + case 0xdf14 ... 0xdf1b: + case 0xe83c ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x10000000 ... 0x10007fff: + case 0x1000c000 ... 0x1000dfff: + case 0x1000f008: + case 0x3fc2bfc4 ... 0x3fc2bfc7: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): + return true; + default: + return false; + } +} + +static const struct regmap_config rt1320_sdw_regmap = { + .reg_bits = 32, + .val_bits = 8, + .readable_reg = rt1320_readable_register, + .volatile_reg = rt1320_volatile_register, + .max_register = 0x41081488, + .reg_defaults = rt1320_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static const struct regmap_config rt1320_mbq_regmap = { + .name = "sdw-mbq", + .reg_bits = 32, + .val_bits = 16, + .readable_reg = rt1320_mbq_readable_register, + .max_register = 0x41000192, + .reg_defaults = rt1320_mbq_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static int rt1320_read_prop(struct sdw_slave *slave) +{ + struct sdw_slave_prop *prop = &slave->prop; + int nval; + int j; + u32 bit; + unsigned long addr; + struct sdw_dpn_prop *dpn; + + sdw_slave_read_prop(slave); + + prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; + prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; + + prop->paging_support = true; + prop->lane_control_support = true; + + /* first we need to allocate memory for set bits in port lists */ + prop->sink_ports = BIT(1); + /* + * By default, the DSP FW will run the speaker protection algorithm. + * Therefore, the feedback feature is not necessary at this moment, but can be added later if required. + */ + prop->source_ports = 0x0; + + /* do this again for sink now */ + nval = hweight32(prop->sink_ports); + prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, + sizeof(*prop->sink_dpn_prop), GFP_KERNEL); + if (!prop->sink_dpn_prop) + return -ENOMEM; + + j = 0; + dpn = prop->sink_dpn_prop; + addr = prop->sink_ports; + for_each_set_bit(bit, &addr, 32) { + dpn[j].num = bit; + dpn[j].type = SDW_DPN_FULL; + dpn[j].simple_ch_prep_sm = true; + dpn[j].ch_prep_timeout = 10; + j++; + } + + /* set the timeout values */ + prop->clk_stop_timeout = 64; + + return 0; +} + +static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned int amp_func_status, val, tmp; + + if (rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, false); + regcache_cache_only(rt1320->mbq_regmap, false); + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, true); + regcache_cache_bypass(rt1320->mbq_regmap, true); + } else { + /* + * PM runtime status is marked as 'active' only when a Slave reports as Attached + */ + /* update count of parent 'active' children */ + pm_runtime_set_active(&slave->dev); + } + + pm_runtime_get_noresume(&slave->dev); + + if (rt1320->version_id < 0) { + regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); + rt1320->version_id = val; + } + + regmap_read(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &amp_func_status); + dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); + + /* initialization write */ + if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt1320->first_hw_init)) { + regmap_multi_reg_write(rt1320->regmap, rt1320_blind_write, ARRAY_SIZE(rt1320_blind_write)); + regmap_multi_reg_write(rt1320->regmap, rt1320_patch_code_write, + ARRAY_SIZE(rt1320_patch_code_write)); + + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), + FUNCTION_NEEDS_INITIALIZATION); + } + if (!rt1320->first_hw_init) { + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); + val = (tmp << 8) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); + val = (tmp << 16) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); + val = (tmp << 24) | val; + dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); + /* + * We call the version b which has the new DSP ROM code against version a. + * Therefore, we read the DSP address to check the ID. + */ + if (val == RT1320_VER_B_ID) + rt1320->version_id = RT1320_VB; + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); + } + dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); + + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, false); + regcache_cache_bypass(rt1320->mbq_regmap, false); + regcache_mark_dirty(rt1320->regmap); + regcache_mark_dirty(rt1320->mbq_regmap); + } + + /* Mark Slave initialization complete */ + rt1320->first_hw_init = true; + rt1320->hw_init = true; + + pm_runtime_mark_last_busy(&slave->dev); + pm_runtime_put_autosuspend(&slave->dev); + + dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); + return 0; +} + +static int rt1320_update_status(struct sdw_slave *slave, + enum sdw_slave_status status) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); + + if (status == SDW_SLAVE_UNATTACHED) + rt1320->hw_init = false; + + /* + * Perform initialization only if slave status is present and + * hw_init flag is false + */ + if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) + return 0; + + /* perform I/O transfers required for Slave initialization */ + return rt1320_io_init(&slave->dev, slave); +} + +static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned char ps0 = 0x0, ps3 = 0x3; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps0); + break; + case SND_SOC_DAPM_PRE_PMD: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps3); + break; + default: + break; + } + + return 0; +} + +static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned int read_l, read_r, gain_l_val, gain_r_val; + unsigned int lvalue, rvalue; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); + regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); + + /* L Channel */ + gain_l_val = ucontrol->value.integer.value[0]; + if (gain_l_val > mc->max) + gain_l_val = mc->max; + gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); + gain_l_val &= 0xffff; + + /* R Channel */ + gain_r_val = ucontrol->value.integer.value[1]; + if (gain_r_val > mc->max) + gain_r_val = mc->max; + gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); + gain_r_val &= 0xffff; + + if (lvalue == gain_l_val && rvalue == gain_r_val) + return 0; + + /* Lch*/ + regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); + /* Rch */ + regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + if (read_r == gain_r_val && read_l == gain_l_val) + return 1; + + return -EIO; +} + +static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + + ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); + + if (read_l != read_r) + ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); + else + ctl_r = ctl_l; + + ucontrol->value.integer.value[0] = ctl_l; + ucontrol->value.integer.value[1] = ctl_r; + return 0; +} + +static const char * const rt1320_rx_data_ch_select[] = { + "L,R", + "R,L", + "L,L", + "R,R", + "L,L+R", + "R,L+R", + "L+R,L", + "L+R,R", + "L+R,L+R", +}; + +static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, + rt1320_rx_data_ch_select); + +static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); + +static const struct snd_kcontrol_new rt1320_snd_controls[] = { + SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), + 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), + SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), +}; + +static const struct snd_kcontrol_new rt1320_spk_l_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), + 0, 1, 1); +static const struct snd_kcontrol_new rt1320_spk_r_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), + 0, 1, 1); + +static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), + + /* Digital Interface */ + SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, + rt1320_pde23_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + /* Output */ + SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), + SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), + SND_SOC_DAPM_OUTPUT("SPOL"), + SND_SOC_DAPM_OUTPUT("SPOR"), +}; + +static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { + { "FU21", NULL, "DP1RX" }, + { "FU21", NULL, "PDE 23" }, + { "OT23 L", "Switch", "FU21" }, + { "OT23 R", "Switch", "FU21" }, + { "SPOL", NULL, "OT23 L" }, + { "SPOR", NULL, "OT23 R" }, +}; + +static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, + int direction) +{ + snd_soc_dai_dma_data_set(dai, direction, sdw_stream); + return 0; +} + +static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + snd_soc_dai_set_dma_data(dai, substream, NULL); +} + +static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_config stream_config; + struct sdw_port_config port_config; + struct sdw_stream_runtime *sdw_stream; + int retval; + unsigned int sampling_rate; + + dev_dbg(dai->dev, "%s %s", __func__, dai->name); + sdw_stream = snd_soc_dai_get_dma_data(dai, substream); + + if (!sdw_stream) + return -EINVAL; + + if (!rt1320->sdw_slave) + return -EINVAL; + + /* SoundWire specific configuration */ + snd_sdw_params_to_config(substream, params, &stream_config, &port_config); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (dai->id == RT1320_AIF1) + port_config.num = 1; + else + return -EINVAL; + } else { + return -EINVAL; + } + + retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, + &port_config, 1, sdw_stream); + if (retval) { + dev_err(dai->dev, "%s: Unable to configure port\n", __func__); + return retval; + } + + /* sampling rate configuration */ + switch (params_rate(params)) { + case 16000: + sampling_rate = RT1320_SDCA_RATE_16000HZ; + break; + case 32000: + sampling_rate = RT1320_SDCA_RATE_32000HZ; + break; + case 44100: + sampling_rate = RT1320_SDCA_RATE_44100HZ; + break; + case 48000: + sampling_rate = RT1320_SDCA_RATE_48000HZ; + break; + case 96000: + sampling_rate = RT1320_SDCA_RATE_96000HZ; + break; + case 192000: + sampling_rate = RT1320_SDCA_RATE_192000HZ; + break; + default: + dev_err(component->dev, "%s: Rate %d is not supported\n", + __func__, params_rate(params)); + return -EINVAL; + } + + /* set sampling frequency */ + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), + sampling_rate); + + return 0; +} + +static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_runtime *sdw_stream = + snd_soc_dai_get_dma_data(dai, substream); + + if (!rt1320->sdw_slave) + return -EINVAL; + + sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); + return 0; +} + +/* + * slave_ops: callbacks for get_clock_stop_mode, clock_stop and + * port_prep are not defined for now + */ +static const struct sdw_slave_ops rt1320_slave_ops = { + .read_prop = rt1320_read_prop, + .update_status = rt1320_update_status, +}; + +static int rt1320_sdw_component_probe(struct snd_soc_component *component) +{ + int ret; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + + rt1320->component = component; + + if (!rt1320->first_hw_init) + return 0; + + ret = pm_runtime_resume(component->dev); + dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); + if (ret < 0 && ret != -EACCES) + return ret; + + return 0; +} + +static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { + .probe = rt1320_sdw_component_probe, + .controls = rt1320_snd_controls, + .num_controls = ARRAY_SIZE(rt1320_snd_controls), + .dapm_widgets = rt1320_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), + .dapm_routes = rt1320_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), + .endianness = 1, +}; + +static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { + .hw_params = rt1320_sdw_hw_params, + .hw_free = rt1320_sdw_pcm_hw_free, + .set_stream = rt1320_set_sdw_stream, + .shutdown = rt1320_sdw_shutdown, +}; + +#define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) +#define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver rt1320_sdw_dai[] = { + { + .name = "rt1320-aif1", + .id = RT1320_AIF1, + .playback = { + .stream_name = "DP1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1320_STEREO_RATES, + .formats = RT1320_FORMATS, + }, + .ops = &rt1320_aif_dai_ops, + }, +}; + +static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, + struct regmap *mbq_regmap, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320; + int ret; + + rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); + if (!rt1320) + return -ENOMEM; + + dev_set_drvdata(dev, rt1320); + rt1320->sdw_slave = slave; + rt1320->mbq_regmap = mbq_regmap; + rt1320->regmap = regmap; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + + /* + * Mark hw_init to false + * HW init will be performed when device reports present + */ + rt1320->hw_init = false; + rt1320->first_hw_init = false; + rt1320->version_id = -1; + + ret = devm_snd_soc_register_component(dev, + &soc_component_sdw_rt1320, + rt1320_sdw_dai, + ARRAY_SIZE(rt1320_sdw_dai)); + if (ret < 0) + return ret; + + /* set autosuspend parameters */ + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + + /* make sure the device does not suspend immediately */ + pm_runtime_mark_last_busy(dev); + + pm_runtime_enable(dev); + + /* important note: the device is NOT tagged as 'active' and will remain + * 'suspended' until the hardware is enumerated/initialized. This is required + * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently + * fail with -EACCESS because of race conditions between card creation and enumeration + */ + + dev_dbg(dev, "%s\n", __func__); + + return ret; +} + +static int rt1320_sdw_probe(struct sdw_slave *slave, + const struct sdw_device_id *id) +{ + struct regmap *regmap, *mbq_regmap; + + /* Regmap Initialization */ + mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); + if (IS_ERR(mbq_regmap)) + return PTR_ERR(mbq_regmap); + + regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); +} + +static int rt1320_sdw_remove(struct sdw_slave *slave) +{ + pm_runtime_disable(&slave->dev); + + return 0; +} + +static const struct sdw_device_id rt1320_id[] = { + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), + {}, +}; +MODULE_DEVICE_TABLE(sdw, rt1320_id); + +static int __maybe_unused rt1320_dev_suspend(struct device *dev) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + + if (!rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + return 0; +} + +#define RT1320_PROBE_TIMEOUT 5000 + +static int __maybe_unused rt1320_dev_resume(struct device *dev) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned long time; + + if (!rt1320->first_hw_init) + return 0; + + if (!slave->unattach_request) + goto regmap_sync; + + time = wait_for_completion_timeout(&slave->initialization_complete, + msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); + if (!time) { + dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); + return -ETIMEDOUT; + } + +regmap_sync: + slave->unattach_request = 0; + regcache_cache_only(rt1320->regmap, false); + regcache_sync(rt1320->regmap); + regcache_cache_only(rt1320->mbq_regmap, false); + regcache_sync(rt1320->mbq_regmap); + return 0; +} + +static const struct dev_pm_ops rt1320_pm = { + SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) + SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) +}; + +static struct sdw_driver rt1320_sdw_driver = { + .driver = { + .name = "rt1320-sdca", + .pm = &rt1320_pm, + }, + .probe = rt1320_sdw_probe, + .remove = rt1320_sdw_remove, + .ops = &rt1320_slave_ops, + .id_table = rt1320_id, +}; +module_sdw_driver(rt1320_sdw_driver); + +MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); +MODULE_AUTHOR("Shuming Fan <shumingf(a)realtek.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/rt1320-sdw.h b/sound/soc/codecs/rt1320-sdw.h new file mode 100644 index 000000000000..f944ae83223f --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * rt1320-sdw.h -- RT1320 SDCA ALSA SoC audio driver header + * + * Copyright(c) 2024 Realtek Semiconductor Corp. + */ + +#ifndef __RT1320_SDW_H__ +#define __RT1320_SDW_H__ + +#include <linux/regmap.h> +#include <linux/soundwire/sdw.h> +#include <linux/soundwire/sdw_type.h> +#include <linux/soundwire/sdw_registers.h> +#include <sound/soc.h> + +/* imp-defined registers */ +#define RT1320_DEV_VERSION_ID_1 0xc404 + +#define RT1320_KR0_STATUS_CNT 0x1000f008 +#define RT1320_HIFI_VER_0 0x3fe2e000 +#define RT1320_HIFI_VER_1 0x3fe2e001 +#define RT1320_HIFI_VER_2 0x3fe2e002 +#define RT1320_HIFI_VER_3 0x3fe2e003 + +/* RT1320 SDCA Control - function number */ +#define FUNC_NUM_AMP 0x04 + +/* RT1320 SDCA entity */ +#define RT1320_SDCA_ENT0 0x00 +#define RT1320_SDCA_ENT_PDE11 0x2a +#define RT1320_SDCA_ENT_PDE23 0x33 +#define RT1320_SDCA_ENT_PDE27 0x27 +#define RT1320_SDCA_ENT_FU14 0x32 +#define RT1320_SDCA_ENT_FU21 0x03 +#define RT1320_SDCA_ENT_FU113 0x30 +#define RT1320_SDCA_ENT_CS14 0x13 +#define RT1320_SDCA_ENT_CS21 0x21 +#define RT1320_SDCA_ENT_CS113 0x12 +#define RT1320_SDCA_ENT_SAPU 0x29 +#define RT1320_SDCA_ENT_PPU21 0x04 + +/* RT1320 SDCA control */ +#define RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10 +#define RT1320_SDCA_CTL_REQ_POWER_STATE 0x01 +#define RT1320_SDCA_CTL_FU_MUTE 0x01 +#define RT1320_SDCA_CTL_FU_VOLUME 0x02 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_MODE 0x10 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11 +#define RT1320_SDCA_CTL_POSTURE_NUMBER 0x10 +#define RT1320_SDCA_CTL_FUNC_STATUS 0x10 + +/* RT1320 SDCA channel */ +#define CH_01 0x01 +#define CH_02 0x02 + +/* Function_Status */ +#define FUNCTION_NEEDS_INITIALIZATION BIT(5) +#define FUNCTION_HAS_BEEN_RESET BIT(6) +#define FUNCTION_BUSY BIT(7) + +/* Sample Frequency Index */ +#define RT1320_SDCA_RATE_16000HZ 0x04 +#define RT1320_SDCA_RATE_32000HZ 0x07 +#define RT1320_SDCA_RATE_44100HZ 0x08 +#define RT1320_SDCA_RATE_48000HZ 0x09 +#define RT1320_SDCA_RATE_96000HZ 0x0b +#define RT1320_SDCA_RATE_192000HZ 0x0d + +enum { + RT1320_AIF1, +}; + +enum rt1320_version_id { + RT1320_VA, + RT1320_VB, +}; + +#define RT1320_VER_B_ID 0x07392238 + +struct rt1320_sdw_priv { + struct snd_soc_component *component; + struct regmap *regmap; + struct regmap *mbq_regmap; + struct sdw_slave *sdw_slave; + struct sdw_bus_params params; + bool hw_init; + bool first_hw_init; + int version_id; +}; + +#endif /* __RT1320_SDW_H__ */ -- 2.34.1

3 4

[PATCH 1/3] ASoC: fsl: fsl_aud2htx: Switch to RUNTIME_PM_OPS()
by Fabio Estevam 20 May '24

20 May '24

From: Fabio Estevam <festevam(a)denx.de> Replace SET_RUNTIME_PM_OPS() with its modern alternative RUNTIME_PM_OPS(). The combined usage of pm_ptr() and RUNTIME_PM_OPS() allows the compiler to evaluate if the runtime suspend/resume() functions are used at build time or are simply dead code. This allows removing the __maybe_unused notation from the runtime suspend/resume() functions. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- sound/soc/fsl/fsl_aud2htx.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/sound/soc/fsl/fsl_aud2htx.c b/sound/soc/fsl/fsl_aud2htx.c index ee2f6ad1f800..a6cbaa6364c7 100644 --- a/sound/soc/fsl/fsl_aud2htx.c +++ b/sound/soc/fsl/fsl_aud2htx.c @@ -261,7 +261,7 @@ static void fsl_aud2htx_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); } -static int __maybe_unused fsl_aud2htx_runtime_suspend(struct device *dev) +static int fsl_aud2htx_runtime_suspend(struct device *dev) { struct fsl_aud2htx *aud2htx = dev_get_drvdata(dev); @@ -271,7 +271,7 @@ static int __maybe_unused fsl_aud2htx_runtime_suspend(struct device *dev) return 0; } -static int __maybe_unused fsl_aud2htx_runtime_resume(struct device *dev) +static int fsl_aud2htx_runtime_resume(struct device *dev) { struct fsl_aud2htx *aud2htx = dev_get_drvdata(dev); int ret; @@ -288,9 +288,8 @@ static int __maybe_unused fsl_aud2htx_runtime_resume(struct device *dev) } static const struct dev_pm_ops fsl_aud2htx_pm_ops = { - SET_RUNTIME_PM_OPS(fsl_aud2htx_runtime_suspend, - fsl_aud2htx_runtime_resume, - NULL) + RUNTIME_PM_OPS(fsl_aud2htx_runtime_suspend, fsl_aud2htx_runtime_resume, + NULL) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) }; @@ -300,7 +299,7 @@ static struct platform_driver fsl_aud2htx_driver = { .remove_new = fsl_aud2htx_remove, .driver = { .name = "fsl-aud2htx", - .pm = &fsl_aud2htx_pm_ops, + .pm = pm_ptr(&fsl_aud2htx_pm_ops), .of_match_table = fsl_aud2htx_dt_ids, }, }; -- 2.34.1

2 5

[PATCH v2] ASoC: rt1320: Add RT1320 SDCA vendor-specific driver
by shumingf＠realtek.com 20 May '24

20 May '24

From: Shuming Fan <shumingf(a)realtek.com> This is the initial amplifier driver for rt1320. Signed-off-by: Shuming Fan <shumingf(a)realtek.com> --- sound/soc/codecs/Kconfig | 7 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt1320-sdw.c | 2244 +++++++++++++++++++++++++++++++++ sound/soc/codecs/rt1320-sdw.h | 96 ++ 4 files changed, 2349 insertions(+) create mode 100644 sound/soc/codecs/rt1320-sdw.c create mode 100644 sound/soc/codecs/rt1320-sdw.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 4afc43d3f71f..7502581d1631 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -222,6 +222,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_RT1308_SDW imply SND_SOC_RT1316_SDW imply SND_SOC_RT1318_SDW + imply SND_SOC_RT1320_SDW imply SND_SOC_RT9120 imply SND_SOC_RTQ9128 imply SND_SOC_SDW_MOCKUP @@ -1575,6 +1576,12 @@ config SND_SOC_RT1318_SDW depends on SOUNDWIRE select REGMAP_SOUNDWIRE +config SND_SOC_RT1320_SDW + tristate "Realtek RT1320 Codec - SDW" + depends on SOUNDWIRE + select REGMAP_SOUNDWIRE + select REGMAP_SOUNDWIRE_MBQ + config SND_SOC_RT5514 tristate depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index b4df22186e25..f9eb7c073a00 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -222,6 +222,7 @@ snd-soc-rt1308-y := rt1308.o snd-soc-rt1308-sdw-y := rt1308-sdw.o snd-soc-rt1316-sdw-y := rt1316-sdw.o snd-soc-rt1318-sdw-y := rt1318-sdw.o +snd-soc-rt1320-sdw-y := rt1320-sdw.o snd-soc-rt274-y := rt274.o snd-soc-rt286-y := rt286.o snd-soc-rt298-y := rt298.o @@ -614,6 +615,7 @@ obj-$(CONFIG_SND_SOC_RT1308) += snd-soc-rt1308.o obj-$(CONFIG_SND_SOC_RT1308_SDW) += snd-soc-rt1308-sdw.o obj-$(CONFIG_SND_SOC_RT1316_SDW) += snd-soc-rt1316-sdw.o obj-$(CONFIG_SND_SOC_RT1318_SDW) += snd-soc-rt1318-sdw.o +obj-$(CONFIG_SND_SOC_RT1320_SDW) += snd-soc-rt1320-sdw.o obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o diff --git a/sound/soc/codecs/rt1320-sdw.c b/sound/soc/codecs/rt1320-sdw.c new file mode 100644 index 000000000000..81980ec53213 --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.c @@ -0,0 +1,2244 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver +// +// Copyright(c) 2024 Realtek Semiconductor Corp. +// +// +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/pm_runtime.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include <linux/dmi.h> +#include <linux/firmware.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/sdw.h> +#include "rt1320-sdw.h" + +static const struct reg_sequence rt1320_blind_write[] = { + { 0xc003, 0xe0 }, + { 0xc01b, 0xfc }, + { 0xc5c3, 0xf2 }, + { 0xc5c2, 0x00 }, + { 0xc5c6, 0x10 }, + { 0xc5c4, 0x12 }, + { 0xc5c8, 0x03 }, + { 0xc5d8, 0x0a }, + { 0xc5f7, 0x22 }, + { 0xc5f6, 0x22 }, + { 0xc5d0, 0x0f }, + { 0xc5d1, 0x89 }, + { 0xc057, 0x51 }, + { 0xc054, 0x35 }, + { 0xc053, 0x55 }, + { 0xc052, 0x55 }, + { 0xc051, 0x13 }, + { 0xc050, 0x15 }, + { 0xc060, 0x77 }, + { 0xc061, 0x55 }, + { 0xc063, 0x55 }, + { 0xc065, 0xa5 }, + { 0xc06b, 0x0a }, + { 0xca05, 0xd6 }, + { 0xca25, 0xd6 }, + { 0xcd00, 0x05 }, + { 0xc604, 0x40 }, + { 0xc609, 0x40 }, + { 0xc046, 0xff }, + { 0xc045, 0xff }, + { 0xc044, 0xff }, + { 0xc043, 0xff }, + { 0xc042, 0xff }, + { 0xc041, 0xff }, + { 0xc040, 0xff }, + { 0xcc10, 0x01 }, + { 0xc700, 0xf0 }, + { 0xc701, 0x13 }, + { 0xc901, 0x04 }, + { 0xc900, 0x73 }, + { 0xde03, 0x05 }, + { 0xdd0b, 0x0d }, + { 0xdd0a, 0xff }, + { 0xdd09, 0x0d }, + { 0xdd08, 0xff }, + { 0xc570, 0x08 }, + { 0xe803, 0xbe }, + { 0xc003, 0xc0 }, + { 0xc081, 0xfe }, + { 0xce31, 0x0d }, + { 0xce30, 0xae }, + { 0xce37, 0x0b }, + { 0xce36, 0xd2 }, + { 0xce39, 0x04 }, + { 0xce38, 0x80 }, + { 0xce3f, 0x00 }, + { 0xce3e, 0x00 }, + { 0xd470, 0x8b }, + { 0xd471, 0x18 }, + { 0xc019, 0x10 }, + { 0xd487, 0x3f }, + { 0xd486, 0xc3 }, +}; + +static const struct reg_sequence rt1320_patch_code_write[] = { + { 0x10007000, 0x37 }, + { 0x10007001, 0x77 }, + { 0x10007002, 0x00 }, + { 0x10007003, 0x10 }, + { 0x10007004, 0xb7 }, + { 0x10007005, 0xe7 }, + { 0x10007006, 0x00 }, + { 0x10007007, 0x10 }, + { 0x10007008, 0x13 }, + { 0x10007009, 0x07 }, + { 0x1000700a, 0x07 }, + { 0x1000700b, 0x40 }, + { 0x1000700c, 0x23 }, + { 0x1000700d, 0xae }, + { 0x1000700e, 0xe7 }, + { 0x1000700f, 0xda }, + { 0x10007010, 0x37 }, + { 0x10007011, 0x77 }, + { 0x10007012, 0x00 }, + { 0x10007013, 0x10 }, + { 0x10007014, 0x13 }, + { 0x10007015, 0x07 }, + { 0x10007016, 0x47 }, + { 0x10007017, 0x61 }, + { 0x10007018, 0x23 }, + { 0x10007019, 0xa4 }, + { 0x1000701a, 0xe7 }, + { 0x1000701b, 0xde }, + { 0x1000701c, 0x37 }, + { 0x1000701d, 0x77 }, + { 0x1000701e, 0x00 }, + { 0x1000701f, 0x10 }, + { 0x10007020, 0x13 }, + { 0x10007021, 0x07 }, + { 0x10007022, 0x07 }, + { 0x10007023, 0x52 }, + { 0x10007024, 0x23 }, + { 0x10007025, 0xae }, + { 0x10007026, 0xe7 }, + { 0x10007027, 0xde }, + { 0x10007028, 0x37 }, + { 0x10007029, 0x77 }, + { 0x1000702a, 0x00 }, + { 0x1000702b, 0x10 }, + { 0x1000702c, 0x13 }, + { 0x1000702d, 0x07 }, + { 0x1000702e, 0x47 }, + { 0x1000702f, 0x54 }, + { 0x10007030, 0x23 }, + { 0x10007031, 0xaa }, + { 0x10007032, 0xe7 }, + { 0x10007033, 0xe4 }, + { 0x10007034, 0x37 }, + { 0x10007035, 0x87 }, + { 0x10007036, 0x00 }, + { 0x10007037, 0x10 }, + { 0x10007038, 0x13 }, + { 0x10007039, 0x07 }, + { 0x1000703a, 0x47 }, + { 0x1000703b, 0x81 }, + { 0x1000703c, 0x23 }, + { 0x1000703d, 0xa2 }, + { 0x1000703e, 0xe7 }, + { 0x1000703f, 0xe8 }, + { 0x10007040, 0x23 }, + { 0x10007041, 0xa4 }, + { 0x10007042, 0xe7 }, + { 0x10007043, 0xe8 }, + { 0x10007044, 0x37 }, + { 0x10007045, 0x77 }, + { 0x10007046, 0x00 }, + { 0x10007047, 0x10 }, + { 0x10007048, 0x13 }, + { 0x10007049, 0x07 }, + { 0x1000704a, 0x07 }, + { 0x1000704b, 0x59 }, + { 0x1000704c, 0x23 }, + { 0x1000704d, 0xa8 }, + { 0x1000704e, 0xe7 }, + { 0x1000704f, 0xea }, + { 0x10007050, 0x37 }, + { 0x10007051, 0x77 }, + { 0x10007052, 0x00 }, + { 0x10007053, 0x10 }, + { 0x10007054, 0x13 }, + { 0x10007055, 0x07 }, + { 0x10007056, 0x07 }, + { 0x10007057, 0x78 }, + { 0x10007058, 0x23 }, + { 0x10007059, 0xa6 }, + { 0x1000705a, 0xe7 }, + { 0x1000705b, 0xec }, + { 0x1000705c, 0x67 }, + { 0x1000705d, 0x80 }, + { 0x1000705e, 0x00 }, + { 0x1000705f, 0x00 }, + { 0x10007400, 0x37 }, + { 0x10007401, 0xd7 }, + { 0x10007402, 0x00 }, + { 0x10007403, 0x00 }, + { 0x10007404, 0x83 }, + { 0x10007405, 0x27 }, + { 0x10007406, 0x47 }, + { 0x10007407, 0x56 }, + { 0x10007408, 0xb7 }, + { 0x10007409, 0x06 }, + { 0x1000740a, 0x00 }, + { 0x1000740b, 0x02 }, + { 0x1000740c, 0xb3 }, + { 0x1000740d, 0xf7 }, + { 0x1000740e, 0xd7 }, + { 0x1000740f, 0x00 }, + { 0x10007410, 0x63 }, + { 0x10007411, 0x8a }, + { 0x10007412, 0x07 }, + { 0x10007413, 0x00 }, + { 0x10007414, 0x93 }, + { 0x10007415, 0x06 }, + { 0x10007416, 0x10 }, + { 0x10007417, 0x00 }, + { 0x10007418, 0x23 }, + { 0x10007419, 0x83 }, + { 0x1000741a, 0xd1 }, + { 0x1000741b, 0x44 }, + { 0x1000741c, 0x93 }, + { 0x1000741d, 0x07 }, + { 0x1000741e, 0xf0 }, + { 0x1000741f, 0xff }, + { 0x10007420, 0x23 }, + { 0x10007421, 0x22 }, + { 0x10007422, 0xf7 }, + { 0x10007423, 0x56 }, + { 0x10007424, 0x37 }, + { 0x10007425, 0xd7 }, + { 0x10007426, 0x00 }, + { 0x10007427, 0x00 }, + { 0x10007428, 0x83 }, + { 0x10007429, 0x27 }, + { 0x1000742a, 0x47 }, + { 0x1000742b, 0x58 }, + { 0x1000742c, 0x93 }, + { 0x1000742d, 0xf7 }, + { 0x1000742e, 0x17 }, + { 0x1000742f, 0x00 }, + { 0x10007430, 0x63 }, + { 0x10007431, 0x86 }, + { 0x10007432, 0x07 }, + { 0x10007433, 0x00 }, + { 0x10007434, 0x93 }, + { 0x10007435, 0x07 }, + { 0x10007436, 0x10 }, + { 0x10007437, 0x00 }, + { 0x10007438, 0x23 }, + { 0x10007439, 0x22 }, + { 0x1000743a, 0xf7 }, + { 0x1000743b, 0x58 }, + { 0x1000743c, 0xb7 }, + { 0x1000743d, 0xd7 }, + { 0x1000743e, 0x00 }, + { 0x1000743f, 0x00 }, + { 0x10007440, 0x03 }, + { 0x10007441, 0xa7 }, + { 0x10007442, 0x47 }, + { 0x10007443, 0x58 }, + { 0x10007444, 0xb7 }, + { 0x10007445, 0x07 }, + { 0x10007446, 0x00 }, + { 0x10007447, 0x04 }, + { 0x10007448, 0x33 }, + { 0x10007449, 0x77 }, + { 0x1000744a, 0xf7 }, + { 0x1000744b, 0x00 }, + { 0x1000744c, 0x93 }, + { 0x1000744d, 0x07 }, + { 0x1000744e, 0x00 }, + { 0x1000744f, 0x00 }, + { 0x10007450, 0x63 }, + { 0x10007451, 0x0e }, + { 0x10007452, 0x07 }, + { 0x10007453, 0x04 }, + { 0x10007454, 0x37 }, + { 0x10007455, 0x07 }, + { 0x10007456, 0x00 }, + { 0x10007457, 0x11 }, + { 0x10007458, 0x03 }, + { 0x10007459, 0x47 }, + { 0x1000745a, 0x87 }, + { 0x1000745b, 0x0e }, + { 0x1000745c, 0x93 }, + { 0x1000745d, 0x06 }, + { 0x1000745e, 0x40 }, + { 0x1000745f, 0x00 }, + { 0x10007460, 0x13 }, + { 0x10007461, 0x77 }, + { 0x10007462, 0xf7 }, + { 0x10007463, 0x0f }, + { 0x10007464, 0x63 }, + { 0x10007465, 0x02 }, + { 0x10007466, 0xd7 }, + { 0x10007467, 0x0a }, + { 0x10007468, 0x93 }, + { 0x10007469, 0x06 }, + { 0x1000746a, 0x70 }, + { 0x1000746b, 0x00 }, + { 0x1000746c, 0x63 }, + { 0x1000746d, 0x10 }, + { 0x1000746e, 0xd7 }, + { 0x1000746f, 0x04 }, + { 0x10007470, 0x93 }, + { 0x10007471, 0x07 }, + { 0x10007472, 0x60 }, + { 0x10007473, 0x06 }, + { 0x10007474, 0x37 }, + { 0x10007475, 0xd7 }, + { 0x10007476, 0x00 }, + { 0x10007477, 0x00 }, + { 0x10007478, 0x83 }, + { 0x10007479, 0x46 }, + { 0x1000747a, 0x77 }, + { 0x1000747b, 0xa6 }, + { 0x1000747c, 0x93 }, + { 0x1000747d, 0xe6 }, + { 0x1000747e, 0x06 }, + { 0x1000747f, 0xf8 }, + { 0x10007480, 0x93 }, + { 0x10007481, 0xf6 }, + { 0x10007482, 0xf6 }, + { 0x10007483, 0x0f }, + { 0x10007484, 0xa3 }, + { 0x10007485, 0x03 }, + { 0x10007486, 0xd7 }, + { 0x10007487, 0xa6 }, + { 0x10007488, 0x83 }, + { 0x10007489, 0x46 }, + { 0x1000748a, 0x77 }, + { 0x1000748b, 0xa8 }, + { 0x1000748c, 0x93 }, + { 0x1000748d, 0xe6 }, + { 0x1000748e, 0x06 }, + { 0x1000748f, 0xf8 }, + { 0x10007490, 0x93 }, + { 0x10007491, 0xf6 }, + { 0x10007492, 0xf6 }, + { 0x10007493, 0x0f }, + { 0x10007494, 0xa3 }, + { 0x10007495, 0x03 }, + { 0x10007496, 0xd7 }, + { 0x10007497, 0xa8 }, + { 0x10007498, 0xb7 }, + { 0x10007499, 0xc6 }, + { 0x1000749a, 0x00 }, + { 0x1000749b, 0x00 }, + { 0x1000749c, 0x23 }, + { 0x1000749d, 0x84 }, + { 0x1000749e, 0xf6 }, + { 0x1000749f, 0x06 }, + { 0x100074a0, 0xa3 }, + { 0x100074a1, 0x84 }, + { 0x100074a2, 0xf6 }, + { 0x100074a3, 0x06 }, + { 0x100074a4, 0xb7 }, + { 0x100074a5, 0x06 }, + { 0x100074a6, 0x00 }, + { 0x100074a7, 0x04 }, + { 0x100074a8, 0x23 }, + { 0x100074a9, 0x22 }, + { 0x100074aa, 0xd7 }, + { 0x100074ab, 0x58 }, + { 0x100074ac, 0x37 }, + { 0x100074ad, 0xd7 }, + { 0x100074ae, 0x00 }, + { 0x100074af, 0x00 }, + { 0x100074b0, 0x03 }, + { 0x100074b1, 0x27 }, + { 0x100074b2, 0x47 }, + { 0x100074b3, 0x58 }, + { 0x100074b4, 0xb7 }, + { 0x100074b5, 0x06 }, + { 0x100074b6, 0x00 }, + { 0x100074b7, 0x08 }, + { 0x100074b8, 0x33 }, + { 0x100074b9, 0x77 }, + { 0x100074ba, 0xd7 }, + { 0x100074bb, 0x00 }, + { 0x100074bc, 0x63 }, + { 0x100074bd, 0x04 }, + { 0x100074be, 0x07 }, + { 0x100074bf, 0x04 }, + { 0x100074c0, 0x37 }, + { 0x100074c1, 0x07 }, + { 0x100074c2, 0x00 }, + { 0x100074c3, 0x11 }, + { 0x100074c4, 0x03 }, + { 0x100074c5, 0x47 }, + { 0x100074c6, 0xc7 }, + { 0x100074c7, 0x0e }, + { 0x100074c8, 0x93 }, + { 0x100074c9, 0x06 }, + { 0x100074ca, 0x40 }, + { 0x100074cb, 0x00 }, + { 0x100074cc, 0x13 }, + { 0x100074cd, 0x77 }, + { 0x100074ce, 0xf7 }, + { 0x100074cf, 0x0f }, + { 0x100074d0, 0x63 }, + { 0x100074d1, 0x00 }, + { 0x100074d2, 0xd7 }, + { 0x100074d3, 0x04 }, + { 0x100074d4, 0x93 }, + { 0x100074d5, 0x06 }, + { 0x100074d6, 0x70 }, + { 0x100074d7, 0x00 }, + { 0x100074d8, 0x63 }, + { 0x100074d9, 0x00 }, + { 0x100074da, 0xd7 }, + { 0x100074db, 0x04 }, + { 0x100074dc, 0x63 }, + { 0x100074dd, 0x84 }, + { 0x100074de, 0x07 }, + { 0x100074df, 0x02 }, + { 0x100074e0, 0xb7 }, + { 0x100074e1, 0xd6 }, + { 0x100074e2, 0x00 }, + { 0x100074e3, 0x00 }, + { 0x100074e4, 0x03 }, + { 0x100074e5, 0xc7 }, + { 0x100074e6, 0x56 }, + { 0x100074e7, 0xa4 }, + { 0x100074e8, 0x13 }, + { 0x100074e9, 0x67 }, + { 0x100074ea, 0x07 }, + { 0x100074eb, 0xf8 }, + { 0x100074ec, 0x13 }, + { 0x100074ed, 0x77 }, + { 0x100074ee, 0xf7 }, + { 0x100074ef, 0x0f }, + { 0x100074f0, 0xa3 }, + { 0x100074f1, 0x82 }, + { 0x100074f2, 0xe6 }, + { 0x100074f3, 0xa4 }, + { 0x100074f4, 0x37 }, + { 0x100074f5, 0xc7 }, + { 0x100074f6, 0x00 }, + { 0x100074f7, 0x00 }, + { 0x100074f8, 0x23 }, + { 0x100074f9, 0x02 }, + { 0x100074fa, 0xf7 }, + { 0x100074fb, 0x06 }, + { 0x100074fc, 0xb7 }, + { 0x100074fd, 0x07 }, + { 0x100074fe, 0x00 }, + { 0x100074ff, 0x08 }, + { 0x10007500, 0x23 }, + { 0x10007501, 0xa2 }, + { 0x10007502, 0xf6 }, + { 0x10007503, 0x58 }, + { 0x10007504, 0x67 }, + { 0x10007505, 0x80 }, + { 0x10007506, 0x00 }, + { 0x10007507, 0x00 }, + { 0x10007508, 0x93 }, + { 0x10007509, 0x07 }, + { 0x1000750a, 0x80 }, + { 0x1000750b, 0x08 }, + { 0x1000750c, 0x6f }, + { 0x1000750d, 0xf0 }, + { 0x1000750e, 0x9f }, + { 0x1000750f, 0xf6 }, + { 0x10007510, 0x93 }, + { 0x10007511, 0x07 }, + { 0x10007512, 0x80 }, + { 0x10007513, 0x08 }, + { 0x10007514, 0x6f }, + { 0x10007515, 0xf0 }, + { 0x10007516, 0xdf }, + { 0x10007517, 0xfc }, + { 0x10007518, 0x93 }, + { 0x10007519, 0x07 }, + { 0x1000751a, 0x60 }, + { 0x1000751b, 0x06 }, + { 0x1000751c, 0x6f }, + { 0x1000751d, 0xf0 }, + { 0x1000751e, 0x5f }, + { 0x1000751f, 0xfc }, + { 0x10007520, 0x37 }, + { 0x10007521, 0xd7 }, + { 0x10007522, 0x00 }, + { 0x10007523, 0x00 }, + { 0x10007524, 0x83 }, + { 0x10007525, 0x27 }, + { 0x10007526, 0x07 }, + { 0x10007527, 0x53 }, + { 0x10007528, 0xb7 }, + { 0x10007529, 0x06 }, + { 0x1000752a, 0x02 }, + { 0x1000752b, 0x00 }, + { 0x1000752c, 0xb3 }, + { 0x1000752d, 0xf7 }, + { 0x1000752e, 0xd7 }, + { 0x1000752f, 0x00 }, + { 0x10007530, 0x63 }, + { 0x10007531, 0x88 }, + { 0x10007532, 0x07 }, + { 0x10007533, 0x00 }, + { 0x10007534, 0x13 }, + { 0x10007535, 0x06 }, + { 0x10007536, 0xa0 }, + { 0x10007537, 0x05 }, + { 0x10007538, 0x23 }, + { 0x10007539, 0xa8 }, + { 0x1000753a, 0xc1 }, + { 0x1000753b, 0x56 }, + { 0x1000753c, 0x23 }, + { 0x1000753d, 0x28 }, + { 0x1000753e, 0xd7 }, + { 0x1000753f, 0x52 }, + { 0x10007540, 0x67 }, + { 0x10007541, 0x80 }, + { 0x10007542, 0x00 }, + { 0x10007543, 0x00 }, + { 0x10007544, 0x37 }, + { 0x10007545, 0xd7 }, + { 0x10007546, 0x00 }, + { 0x10007547, 0x10 }, + { 0x10007548, 0x83 }, + { 0x10007549, 0x47 }, + { 0x1000754a, 0x07 }, + { 0x1000754b, 0xd9 }, + { 0x1000754c, 0x93 }, + { 0x1000754d, 0x06 }, + { 0x1000754e, 0x20 }, + { 0x1000754f, 0x00 }, + { 0x10007550, 0x93 }, + { 0x10007551, 0xf7 }, + { 0x10007552, 0xf7 }, + { 0x10007553, 0x0f }, + { 0x10007554, 0x63 }, + { 0x10007555, 0x9c }, + { 0x10007556, 0xd7 }, + { 0x10007557, 0x02 }, + { 0x10007558, 0xb7 }, + { 0x10007559, 0xc6 }, + { 0x1000755a, 0x00 }, + { 0x1000755b, 0x00 }, + { 0x1000755c, 0x83 }, + { 0x1000755d, 0xc7 }, + { 0x1000755e, 0x26 }, + { 0x1000755f, 0x04 }, + { 0x10007560, 0x93 }, + { 0x10007561, 0xf7 }, + { 0x10007562, 0xf7 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0x1000777e, 0x00 }, + { 0x1000777f, 0x00 }, + { 0x10007780, 0x03 }, + { 0x10007781, 0xc7 }, + { 0x10007782, 0xa1 }, + { 0x10007783, 0x40 }, + { 0x10007784, 0x93 }, + { 0x10007785, 0x06 }, + { 0x10007786, 0x10 }, + { 0x10007787, 0x00 }, + { 0x10007788, 0x63 }, + { 0x10007789, 0x16 }, + { 0x1000778a, 0xd7 }, + { 0x1000778b, 0x00 }, + { 0x1000778c, 0xb7 }, + { 0x1000778d, 0xd6 }, + { 0x1000778e, 0x00 }, + { 0x1000778f, 0x10 }, + { 0x10007790, 0xa3 }, + { 0x10007791, 0x8a }, + { 0x10007792, 0xe6 }, + { 0x10007793, 0xd8 }, + { 0x10007794, 0x83 }, + { 0x10007795, 0xc7 }, + { 0x10007796, 0xa1 }, + { 0x10007797, 0x40 }, + { 0x10007798, 0x63 }, + { 0x10007799, 0x9c }, + { 0x1000779a, 0x07 }, + { 0x1000779b, 0x06 }, + { 0x1000779c, 0x13 }, + { 0x1000779d, 0x01 }, + { 0x1000779e, 0x01 }, + { 0x1000779f, 0xff }, + { 0x100077a0, 0x23 }, + { 0x100077a1, 0x22 }, + { 0x100077a2, 0x91 }, + { 0x100077a3, 0x00 }, + { 0x100077a4, 0x23 }, + { 0x100077a5, 0x26 }, + { 0x100077a6, 0x11 }, + { 0x100077a7, 0x00 }, + { 0x100077a8, 0x23 }, + { 0x100077a9, 0x24 }, + { 0x100077aa, 0x81 }, + { 0x100077ab, 0x00 }, + { 0x100077ac, 0xb7 }, + { 0x100077ad, 0xc4 }, + { 0x100077ae, 0x00 }, + { 0x100077af, 0x00 }, + { 0x100077b0, 0x83 }, + { 0x100077b1, 0xc7 }, + { 0x100077b2, 0x04 }, + { 0x100077b3, 0x56 }, + { 0x100077b4, 0x13 }, + { 0x100077b5, 0x07 }, + { 0x100077b6, 0x80 }, + { 0x100077b7, 0x01 }, + { 0x100077b8, 0x93 }, + { 0x100077b9, 0xf7 }, + { 0x100077ba, 0xf7 }, + { 0x100077bb, 0x0f }, + { 0x100077bc, 0x63 }, + { 0x100077bd, 0x70 }, + { 0x100077be, 0xf7 }, + { 0x100077bf, 0x04 }, + { 0x100077c0, 0x37 }, + { 0x100077c1, 0xd4 }, + { 0x100077c2, 0x00 }, + { 0x100077c3, 0x10 }, + { 0x100077c4, 0x83 }, + { 0x100077c5, 0x47 }, + { 0x100077c6, 0x54 }, + { 0x100077c7, 0xd9 }, + { 0x100077c8, 0x93 }, + { 0x100077c9, 0xf7 }, + { 0x100077ca, 0xf7 }, + { 0x100077cb, 0x0f }, + { 0x100077cc, 0x63 }, + { 0x100077cd, 0x88 }, + { 0x100077ce, 0x07 }, + { 0x100077cf, 0x02 }, + { 0x100077d0, 0x93 }, + { 0x100077d1, 0x07 }, + { 0x100077d2, 0x10 }, + { 0x100077d3, 0x00 }, + { 0x100077d4, 0x23 }, + { 0x100077d5, 0x82 }, + { 0x100077d6, 0xf4 }, + { 0x100077d7, 0x58 }, + { 0x100077d8, 0x03 }, + { 0x100077d9, 0x45 }, + { 0x100077da, 0x64 }, + { 0x100077db, 0xd9 }, + { 0x100077dc, 0xb7 }, + { 0x100077dd, 0x15 }, + { 0x100077de, 0x00 }, + { 0x100077df, 0x00 }, + { 0x100077e0, 0x93 }, + { 0x100077e1, 0x85 }, + { 0x100077e2, 0x85 }, + { 0x100077e3, 0x38 }, + { 0x100077e4, 0x13 }, + { 0x100077e5, 0x75 }, + { 0x100077e6, 0xf5 }, + { 0x100077e7, 0x0f }, + { 0x100077e8, 0xef }, + { 0x100077e9, 0xe0 }, + { 0x100077ea, 0x9f }, + { 0x100077eb, 0xd0 }, + { 0x100077ec, 0x93 }, + { 0x100077ed, 0x55 }, + { 0x100077ee, 0xf5 }, + { 0x100077ef, 0x41 }, + { 0x100077f0, 0xef }, + { 0x100077f1, 0xe0 }, + { 0x100077f2, 0x8f }, + { 0x100077f3, 0xa3 }, + { 0x100077f4, 0x23 }, + { 0x100077f5, 0x82 }, + { 0x100077f6, 0x04 }, + { 0x100077f7, 0x58 }, + { 0x100077f8, 0xa3 }, + { 0x100077f9, 0x0a }, + { 0x100077fa, 0x04 }, + { 0x100077fb, 0xd8 }, + { 0x100077fc, 0x83 }, + { 0x100077fd, 0x20 }, + { 0x100077fe, 0xc1 }, + { 0x100077ff, 0x00 }, + { 0x10007800, 0x03 }, + { 0x10007801, 0x24 }, + { 0x10007802, 0x81 }, + { 0x10007803, 0x00 }, + { 0x10007804, 0x83 }, + { 0x10007805, 0x24 }, + { 0x10007806, 0x41 }, + { 0x10007807, 0x00 }, + { 0x10007808, 0x13 }, + { 0x10007809, 0x01 }, + { 0x1000780a, 0x01 }, + { 0x1000780b, 0x01 }, + { 0x1000780c, 0x67 }, + { 0x1000780d, 0x80 }, + { 0x1000780e, 0x00 }, + { 0x1000780f, 0x00 }, + { 0x10007810, 0x67 }, + { 0x10007811, 0x80 }, + { 0x10007812, 0x00 }, + { 0x10007813, 0x00 }, + { 0x10007814, 0x13 }, + { 0x10007815, 0x01 }, + { 0x10007816, 0x01 }, + { 0x10007817, 0xff }, + { 0x10007818, 0x23 }, + { 0x10007819, 0x26 }, + { 0x1000781a, 0x11 }, + { 0x1000781b, 0x00 }, + { 0x1000781c, 0xef }, + { 0x1000781d, 0xd0 }, + { 0x1000781e, 0x8f }, + { 0x1000781f, 0x86 }, + { 0x10007820, 0x83 }, + { 0x10007821, 0xc7 }, + { 0x10007822, 0x11 }, + { 0x10007823, 0x42 }, + { 0x10007824, 0x63 }, + { 0x10007825, 0x86 }, + { 0x10007826, 0x07 }, + { 0x10007827, 0x00 }, + { 0x10007828, 0x03 }, + { 0x10007829, 0xc7 }, + { 0x1000782a, 0x01 }, + { 0x1000782b, 0x42 }, + { 0x1000782c, 0x63 }, + { 0x1000782d, 0x10 }, + { 0x1000782e, 0x07 }, + { 0x1000782f, 0x02 }, + { 0x10007830, 0x83 }, + { 0x10007831, 0xc6 }, + { 0x10007832, 0x21 }, + { 0x10007833, 0x41 }, + { 0x10007834, 0x13 }, + { 0x10007835, 0x07 }, + { 0x10007836, 0xf0 }, + { 0x10007837, 0x01 }, + { 0x10007838, 0x13 }, + { 0x10007839, 0x05 }, + { 0x1000783a, 0xf0 }, + { 0x1000783b, 0x01 }, + { 0x1000783c, 0x63 }, + { 0x1000783d, 0x98 }, + { 0x1000783e, 0xe6 }, + { 0x1000783f, 0x02 }, + { 0x10007840, 0x63 }, + { 0x10007841, 0x8a }, + { 0x10007842, 0x07 }, + { 0x10007843, 0x02 }, + { 0x10007844, 0x83 }, + { 0x10007845, 0xc7 }, + { 0x10007846, 0x01 }, + { 0x10007847, 0x42 }, + { 0x10007848, 0x63 }, + { 0x10007849, 0x86 }, + { 0x1000784a, 0x07 }, + { 0x1000784b, 0x02 }, + { 0x1000784c, 0x83 }, + { 0x1000784d, 0xc7 }, + { 0x1000784e, 0x31 }, + { 0x1000784f, 0x42 }, + { 0x10007850, 0x63 }, + { 0x10007851, 0x86 }, + { 0x10007852, 0x07 }, + { 0x10007853, 0x00 }, + { 0x10007854, 0x83 }, + { 0x10007855, 0xc7 }, + { 0x10007856, 0x21 }, + { 0x10007857, 0x42 }, + { 0x10007858, 0x63 }, + { 0x10007859, 0x9e }, + { 0x1000785a, 0x07 }, + { 0x1000785b, 0x00 }, + { 0x1000785c, 0x03 }, + { 0x1000785d, 0xc7 }, + { 0x1000785e, 0x21 }, + { 0x1000785f, 0x41 }, + { 0x10007860, 0x93 }, + { 0x10007861, 0x07 }, + { 0x10007862, 0xb0 }, + { 0x10007863, 0x01 }, + { 0x10007864, 0x63 }, + { 0x10007865, 0x08 }, + { 0x10007866, 0xf7 }, + { 0x10007867, 0x00 }, + { 0x10007868, 0x13 }, + { 0x10007869, 0x05 }, + { 0x1000786a, 0xb0 }, + { 0x1000786b, 0x01 }, + { 0x1000786c, 0xef }, + { 0x1000786d, 0xd0 }, + { 0x1000786e, 0x0f }, + { 0x1000786f, 0xcf }, + { 0x10007870, 0xef }, + { 0x10007871, 0xd0 }, + { 0x10007872, 0x8f }, + { 0x10007873, 0xa4 }, + { 0x10007874, 0x93 }, + { 0x10007875, 0x06 }, + { 0x10007876, 0x10 }, + { 0x10007877, 0x00 }, + { 0x10007878, 0xa3 }, + { 0x10007879, 0x89 }, + { 0x1000787a, 0xd1 }, + { 0x1000787b, 0x40 }, + { 0x1000787c, 0x37 }, + { 0x1000787d, 0xd7 }, + { 0x1000787e, 0x00 }, + { 0x1000787f, 0x10 }, + { 0x10007880, 0x83 }, + { 0x10007881, 0x47 }, + { 0x10007882, 0x07 }, + { 0x10007883, 0xd9 }, + { 0x10007884, 0x93 }, + { 0x10007885, 0xf7 }, + { 0x10007886, 0xf7 }, + { 0x10007887, 0x0f }, + { 0x10007888, 0x63 }, + { 0x10007889, 0x90 }, + { 0x1000788a, 0x07 }, + { 0x1000788b, 0x02 }, + { 0x1000788c, 0x37 }, + { 0x1000788d, 0xc6 }, + { 0x1000788e, 0x00 }, + { 0x1000788f, 0x00 }, + { 0x10007890, 0x83 }, + { 0x10007891, 0x47 }, + { 0x10007892, 0x26 }, + { 0x10007893, 0x04 }, + { 0x10007894, 0x93 }, + { 0x10007895, 0xe7 }, + { 0x10007896, 0x07 }, + { 0x10007897, 0xf8 }, + { 0x10007898, 0x93 }, + { 0x10007899, 0xf7 }, + { 0x1000789a, 0xf7 }, + { 0x1000789b, 0x0f }, + { 0x1000789c, 0x23 }, + { 0x1000789d, 0x01 }, + { 0x1000789e, 0xf6 }, + { 0x1000789f, 0x04 }, + { 0x100078a0, 0x23 }, + { 0x100078a1, 0x08 }, + { 0x100078a2, 0xd7 }, + { 0x100078a3, 0xd8 }, + { 0x100078a4, 0x23 }, + { 0x100078a5, 0x09 }, + { 0x100078a6, 0x07 }, + { 0x100078a7, 0xd8 }, + { 0x100078a8, 0x83 }, + { 0x100078a9, 0x20 }, + { 0x100078aa, 0xc1 }, + { 0x100078ab, 0x00 }, + { 0x100078ac, 0x13 }, + { 0x100078ad, 0x01 }, + { 0x100078ae, 0x01 }, + { 0x100078af, 0x01 }, + { 0x100078b0, 0x67 }, + { 0x100078b1, 0x80 }, + { 0x100078b2, 0x00 }, + { 0x100078b3, 0x00 }, + { 0x3fc2bfc7, 0x00 }, + { 0x3fc2bfc6, 0x00 }, + { 0x3fc2bfc5, 0x00 }, + { 0x3fc2bfc4, 0x01 }, + { 0x0000d486, 0x43 }, + { 0x1000db00, 0x02 }, + { 0x1000db01, 0x00 }, + { 0x1000db02, 0x11 }, + { 0x1000db03, 0x00 }, + { 0x1000db04, 0x00 }, + { 0x1000db05, 0x82 }, + { 0x1000db06, 0x04 }, + { 0x1000db07, 0xf1 }, + { 0x1000db08, 0x00 }, + { 0x1000db09, 0x00 }, + { 0x1000db0a, 0x40 }, + { 0x0000d540, 0x01 }, +}; + +static const struct reg_default rt1320_reg_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, +}; + +static const struct reg_default rt1320_mbq_defaults[] = { + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, + { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, +}; + +static bool rt1320_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc000 ... 0xc086: + case 0xc400 ... 0xc409: + case 0xc480 ... 0xc48f: + case 0xc4c0 ... 0xc4c4: + case 0xc4e0 ... 0xc4e7: + case 0xc500: + case 0xc560 ... 0xc56b: + case 0xc570: + case 0xc580 ... 0xc59a: + case 0xc5b0 ... 0xc60f: + case 0xc640 ... 0xc64f: + case 0xc670: + case 0xc680 ... 0xc683: + case 0xc700 ... 0xc76f: + case 0xc800 ... 0xc801: + case 0xc820: + case 0xc900 ... 0xc901: + case 0xc920 ... 0xc921: + case 0xca00 ... 0xca07: + case 0xca20 ... 0xca27: + case 0xca40 ... 0xca4b: + case 0xca60 ... 0xca68: + case 0xca80 ... 0xca88: + case 0xcb00 ... 0xcb0c: + case 0xcc00 ... 0xcc12: + case 0xcc80 ... 0xcc81: + case 0xcd00: + case 0xcd80 ... 0xcd82: + case 0xce00 ... 0xce4d: + case 0xcf00 ... 0xcf25: + case 0xd000 ... 0xd0ff: + case 0xd100 ... 0xd1ff: + case 0xd200 ... 0xd2ff: + case 0xd300 ... 0xd3ff: + case 0xd400 ... 0xd403: + case 0xd410 ... 0xd417: + case 0xd470 ... 0xd497: + case 0xd4dc ... 0xd50f: + case 0xd520 ... 0xd543: + case 0xd560 ... 0xd5ef: + case 0xd600 ... 0xd663: + case 0xda00 ... 0xda6e: + case 0xda80 ... 0xda9e: + case 0xdb00 ... 0xdb7f: + case 0xdc00: + case 0xdc20 ... 0xdc21: + case 0xdd00 ... 0xdd17: + case 0xde00 ... 0xde09: + case 0xdf00 ... 0xdf1b: + case 0xe000 ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x1000f008: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0xc402 ... 0xc406: + case 0xc48c ... 0xc48f: + case 0xc560: + case 0xc5b5 ... 0xc5b7: + case 0xc5fc ... 0xc5ff: + case 0xc820: + case 0xc900: + case 0xc920: + case 0xca42: + case 0xca62: + case 0xca82: + case 0xcd00: + case 0xce03: + case 0xce10: + case 0xce14 ... 0xce17: + case 0xce44 ... 0xce49: + case 0xce4c ... 0xce4d: + case 0xcf0c: + case 0xcf10 ... 0xcf25: + case 0xd486 ... 0xd487: + case 0xd4e5 ... 0xd4e6: + case 0xd4e8 ... 0xd4ff: + case 0xd530: + case 0xd540: + case 0xd543: + case 0xdb58 ... 0xdb5f: + case 0xdb60 ... 0xdb63: + case 0xdb68 ... 0xdb69: + case 0xdb6d: + case 0xdb70 ... 0xdb71: + case 0xdb76: + case 0xdb7a: + case 0xdb7c ... 0xdb7f: + case 0xdd0c ... 0xdd13: + case 0xde02: + case 0xdf14 ... 0xdf1b: + case 0xe83c ... 0xe847: + case 0xf717 ... 0xf719: + case 0xf720 ... 0xf723: + case 0x10000000 ... 0x10007fff: + case 0x1000c000 ... 0x1000dfff: + case 0x1000f008: + case 0x3fc2bfc4 ... 0x3fc2bfc7: + case 0x3fe2e000 ... 0x3fe2e003: + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): + return true; + default: + return false; + } +} + +static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): + return true; + default: + return false; + } +} + +static const struct regmap_config rt1320_sdw_regmap = { + .reg_bits = 32, + .val_bits = 8, + .readable_reg = rt1320_readable_register, + .volatile_reg = rt1320_volatile_register, + .max_register = 0x41081488, + .reg_defaults = rt1320_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static const struct regmap_config rt1320_mbq_regmap = { + .name = "sdw-mbq", + .reg_bits = 32, + .val_bits = 16, + .readable_reg = rt1320_mbq_readable_register, + .max_register = 0x41000192, + .reg_defaults = rt1320_mbq_defaults, + .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), + .cache_type = REGCACHE_MAPLE, + .use_single_read = true, + .use_single_write = true, +}; + +static int rt1320_read_prop(struct sdw_slave *slave) +{ + struct sdw_slave_prop *prop = &slave->prop; + int nval; + int i, j; + u32 bit; + unsigned long addr; + struct sdw_dpn_prop *dpn; + + sdw_slave_read_prop(slave); + + prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; + prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; + + prop->paging_support = true; + prop->lane_control_support = true; + + /* first we need to allocate memory for set bits in port lists */ + prop->source_ports = BIT(4); + prop->sink_ports = BIT(1); + + nval = hweight32(prop->source_ports); + prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, + sizeof(*prop->src_dpn_prop), GFP_KERNEL); + if (!prop->src_dpn_prop) + return -ENOMEM; + + i = 0; + dpn = prop->src_dpn_prop; + addr = prop->source_ports; + for_each_set_bit(bit, &addr, 32) { + dpn[i].num = bit; + dpn[i].type = SDW_DPN_FULL; + dpn[i].simple_ch_prep_sm = true; + dpn[i].ch_prep_timeout = 10; + i++; + } + + /* do this again for sink now */ + nval = hweight32(prop->sink_ports); + prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, + sizeof(*prop->sink_dpn_prop), GFP_KERNEL); + if (!prop->sink_dpn_prop) + return -ENOMEM; + + j = 0; + dpn = prop->sink_dpn_prop; + addr = prop->sink_ports; + for_each_set_bit(bit, &addr, 32) { + dpn[j].num = bit; + dpn[j].type = SDW_DPN_FULL; + dpn[j].simple_ch_prep_sm = true; + dpn[j].ch_prep_timeout = 10; + j++; + } + + /* set the timeout values */ + prop->clk_stop_timeout = 64; + + return 0; +} + +static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned int amp_func_status, val, tmp; + + if (rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, false); + regcache_cache_only(rt1320->mbq_regmap, false); + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, true); + regcache_cache_bypass(rt1320->mbq_regmap, true); + } else { + /* + * PM runtime status is marked as 'active' only when a Slave reports as Attached + */ + /* update count of parent 'active' children */ + pm_runtime_set_active(&slave->dev); + } + + pm_runtime_get_noresume(&slave->dev); + + if (rt1320->version_id < 0) { + regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); + rt1320->version_id = val; + } + + regmap_read(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &amp_func_status); + dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); + + /* initialization write */ + if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt1320->first_hw_init)) { + regmap_multi_reg_write(rt1320->regmap, rt1320_blind_write, ARRAY_SIZE(rt1320_blind_write)); + regmap_multi_reg_write(rt1320->regmap, rt1320_patch_code_write, + ARRAY_SIZE(rt1320_patch_code_write)); + + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), + FUNCTION_NEEDS_INITIALIZATION); + } + if (!rt1320->first_hw_init) { + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); + regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); + val = (tmp << 8) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); + val = (tmp << 16) | val; + regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); + val = (tmp << 24) | val; + dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); + /* + * We call the version b which has the new DSP ROM code against version a. + * Therefore, we read the DSP address to check the ID. + */ + if (val == RT1320_VER_B_ID) + rt1320->version_id = RT1320_VB; + regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); + } + dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); + + if (rt1320->first_hw_init) { + regcache_cache_bypass(rt1320->regmap, false); + regcache_cache_bypass(rt1320->mbq_regmap, false); + regcache_mark_dirty(rt1320->regmap); + regcache_mark_dirty(rt1320->mbq_regmap); + } + + /* Mark Slave initialization complete */ + rt1320->first_hw_init = true; + rt1320->hw_init = true; + + pm_runtime_mark_last_busy(&slave->dev); + pm_runtime_put_autosuspend(&slave->dev); + + dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); + return 0; +} + +static int rt1320_update_status(struct sdw_slave *slave, + enum sdw_slave_status status) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); + + if (status == SDW_SLAVE_UNATTACHED) + rt1320->hw_init = false; + + /* + * Perform initialization only if slave status is present and + * hw_init flag is false + */ + if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) + return 0; + + /* perform I/O transfers required for Slave initialization */ + return rt1320_io_init(&slave->dev, slave); +} + +static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned char ps0 = 0x0, ps3 = 0x3; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps0); + break; + case SND_SOC_DAPM_PRE_PMD: + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, + RT1320_SDCA_CTL_REQ_POWER_STATE, 0), + ps3); + break; + default: + break; + } + + return 0; +} + +static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + unsigned int read_l, read_r, gain_l_val, gain_r_val; + unsigned int lvalue, rvalue; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); + regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); + + /* L Channel */ + gain_l_val = ucontrol->value.integer.value[0]; + if (gain_l_val > mc->max) + gain_l_val = mc->max; + gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); + gain_l_val &= 0xffff; + + /* R Channel */ + gain_r_val = ucontrol->value.integer.value[1]; + if (gain_r_val > mc->max) + gain_r_val = mc->max; + gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); + gain_r_val &= 0xffff; + + if (lvalue == gain_l_val && rvalue == gain_r_val) + return 0; + + /* Lch*/ + regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); + /* Rch */ + regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + if (read_r == gain_r_val && read_l == gain_l_val) + return 1; + + return -EIO; +} + +static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; + const unsigned int interval_offset = 0xc0; + + regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); + regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); + + ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); + + if (read_l != read_r) + ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); + else + ctl_r = ctl_l; + + ucontrol->value.integer.value[0] = ctl_l; + ucontrol->value.integer.value[1] = ctl_r; + return 0; +} + +static const char * const rt1320_rx_data_ch_select[] = { + "L,R", + "R,L", + "L,L", + "R,R", + "L,L+R", + "R,L+R", + "L+R,L", + "L+R,R", + "L+R,L+R", +}; + +static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, + rt1320_rx_data_ch_select); + +static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); + +static const struct snd_kcontrol_new rt1320_snd_controls[] = { + SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), + 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), + SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), +}; + +static const struct snd_kcontrol_new rt1320_spk_l_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), + 0, 1, 1); +static const struct snd_kcontrol_new rt1320_spk_r_dac = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), + 0, 1, 1); + +static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), + + /* Digital Interface */ + SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, + rt1320_pde23_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + /* Output */ + SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), + SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), + SND_SOC_DAPM_OUTPUT("SPOL"), + SND_SOC_DAPM_OUTPUT("SPOR"), + + /* Input */ + SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SIGGEN("AEC Gen"), +}; + +static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { + { "FU21", NULL, "DP1RX" }, + { "FU21", NULL, "PDE 23" }, + { "OT23 L", "Switch", "FU21" }, + { "OT23 R", "Switch", "FU21" }, + { "SPOL", NULL, "OT23 L" }, + { "SPOR", NULL, "OT23 R" }, + + { "AEC Data", NULL, "AEC Gen" }, + { "DP4TX", NULL, "AEC Data" }, +}; + +static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, + int direction) +{ + snd_soc_dai_dma_data_set(dai, direction, sdw_stream); + return 0; +} + +static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + snd_soc_dai_set_dma_data(dai, substream, NULL); +} + +static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_config stream_config; + struct sdw_port_config port_config; + struct sdw_stream_runtime *sdw_stream; + int retval; + unsigned int sampling_rate; + + dev_dbg(dai->dev, "%s %s", __func__, dai->name); + sdw_stream = snd_soc_dai_get_dma_data(dai, substream); + + if (!sdw_stream) + return -EINVAL; + + if (!rt1320->sdw_slave) + return -EINVAL; + + /* SoundWire specific configuration */ + snd_sdw_params_to_config(substream, params, &stream_config, &port_config); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (dai->id == RT1320_AIF1) + port_config.num = 1; + else + return -EINVAL; + } else { + if (dai->id == RT1320_AIF1) + port_config.num = 4; + else + return -EINVAL; + } + + retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, + &port_config, 1, sdw_stream); + if (retval) { + dev_err(dai->dev, "%s: Unable to configure port\n", __func__); + return retval; + } + + /* sampling rate configuration */ + switch (params_rate(params)) { + case 16000: + sampling_rate = RT1320_SDCA_RATE_16000HZ; + break; + case 32000: + sampling_rate = RT1320_SDCA_RATE_32000HZ; + break; + case 44100: + sampling_rate = RT1320_SDCA_RATE_44100HZ; + break; + case 48000: + sampling_rate = RT1320_SDCA_RATE_48000HZ; + break; + case 96000: + sampling_rate = RT1320_SDCA_RATE_96000HZ; + break; + case 192000: + sampling_rate = RT1320_SDCA_RATE_192000HZ; + break; + default: + dev_err(component->dev, "%s: Rate %d is not supported\n", + __func__, params_rate(params)); + return -EINVAL; + } + + /* set sampling frequency */ + regmap_write(rt1320->regmap, + SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), + sampling_rate); + + return 0; +} + +static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1320_sdw_priv *rt1320 = + snd_soc_component_get_drvdata(component); + struct sdw_stream_runtime *sdw_stream = + snd_soc_dai_get_dma_data(dai, substream); + + if (!rt1320->sdw_slave) + return -EINVAL; + + sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); + return 0; +} + +/* + * slave_ops: callbacks for get_clock_stop_mode, clock_stop and + * port_prep are not defined for now + */ +static const struct sdw_slave_ops rt1320_slave_ops = { + .read_prop = rt1320_read_prop, + .update_status = rt1320_update_status, +}; + +static int rt1320_sdw_component_probe(struct snd_soc_component *component) +{ + int ret; + struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); + + rt1320->component = component; + + if (!rt1320->first_hw_init) + return 0; + + ret = pm_runtime_resume(component->dev); + dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); + if (ret < 0 && ret != -EACCES) + return ret; + + return 0; +} + +static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { + .probe = rt1320_sdw_component_probe, + .controls = rt1320_snd_controls, + .num_controls = ARRAY_SIZE(rt1320_snd_controls), + .dapm_widgets = rt1320_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), + .dapm_routes = rt1320_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), + .endianness = 1, +}; + +static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { + .hw_params = rt1320_sdw_hw_params, + .hw_free = rt1320_sdw_pcm_hw_free, + .set_stream = rt1320_set_sdw_stream, + .shutdown = rt1320_sdw_shutdown, +}; + +#define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) +#define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver rt1320_sdw_dai[] = { + { + .name = "rt1320-aif1", + .id = RT1320_AIF1, + .playback = { + .stream_name = "DP1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1320_STEREO_RATES, + .formats = RT1320_FORMATS, + }, + .capture = { + .stream_name = "DP4 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT1320_STEREO_RATES, + .formats = RT1320_FORMATS, + }, + .ops = &rt1320_aif_dai_ops, + }, +}; + +static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, + struct regmap *mbq_regmap, struct sdw_slave *slave) +{ + struct rt1320_sdw_priv *rt1320; + int ret; + + rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); + if (!rt1320) + return -ENOMEM; + + dev_set_drvdata(dev, rt1320); + rt1320->sdw_slave = slave; + rt1320->mbq_regmap = mbq_regmap; + rt1320->regmap = regmap; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + + /* + * Mark hw_init to false + * HW init will be performed when device reports present + */ + rt1320->hw_init = false; + rt1320->first_hw_init = false; + rt1320->version_id = -1; + + ret = devm_snd_soc_register_component(dev, + &soc_component_sdw_rt1320, + rt1320_sdw_dai, + ARRAY_SIZE(rt1320_sdw_dai)); + if (ret < 0) + return ret; + + /* set autosuspend parameters */ + pm_runtime_set_autosuspend_delay(dev, 3000); + pm_runtime_use_autosuspend(dev); + + /* make sure the device does not suspend immediately */ + pm_runtime_mark_last_busy(dev); + + pm_runtime_enable(dev); + + /* important note: the device is NOT tagged as 'active' and will remain + * 'suspended' until the hardware is enumerated/initialized. This is required + * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently + * fail with -EACCESS because of race conditions between card creation and enumeration + */ + + dev_dbg(dev, "%s\n", __func__); + + return ret; +} + +static int rt1320_sdw_probe(struct sdw_slave *slave, + const struct sdw_device_id *id) +{ + struct regmap *regmap, *mbq_regmap; + + /* Regmap Initialization */ + mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); + if (IS_ERR(mbq_regmap)) + return PTR_ERR(mbq_regmap); + + regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); +} + +static int rt1320_sdw_remove(struct sdw_slave *slave) +{ + pm_runtime_disable(&slave->dev); + + return 0; +} + +static const struct sdw_device_id rt1320_id[] = { + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), + {}, +}; +MODULE_DEVICE_TABLE(sdw, rt1320_id); + +static int __maybe_unused rt1320_dev_suspend(struct device *dev) +{ + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + + if (!rt1320->hw_init) + return 0; + + regcache_cache_only(rt1320->regmap, true); + regcache_cache_only(rt1320->mbq_regmap, true); + return 0; +} + +#define RT1320_PROBE_TIMEOUT 5000 + +static int __maybe_unused rt1320_dev_resume(struct device *dev) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); + unsigned long time; + + if (!rt1320->first_hw_init) + return 0; + + if (!slave->unattach_request) + goto regmap_sync; + + time = wait_for_completion_timeout(&slave->initialization_complete, + msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); + if (!time) { + dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); + return -ETIMEDOUT; + } + +regmap_sync: + slave->unattach_request = 0; + regcache_cache_only(rt1320->regmap, false); + regcache_sync(rt1320->regmap); + regcache_cache_only(rt1320->mbq_regmap, false); + regcache_sync(rt1320->mbq_regmap); + return 0; +} + +static const struct dev_pm_ops rt1320_pm = { + SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) + SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) +}; + +static struct sdw_driver rt1320_sdw_driver = { + .driver = { + .name = "rt1320-sdca", + .pm = &rt1320_pm, + }, + .probe = rt1320_sdw_probe, + .remove = rt1320_sdw_remove, + .ops = &rt1320_slave_ops, + .id_table = rt1320_id, +}; +module_sdw_driver(rt1320_sdw_driver); + +MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); +MODULE_AUTHOR("Shuming Fan <shumingf(a)realtek.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/rt1320-sdw.h b/sound/soc/codecs/rt1320-sdw.h new file mode 100644 index 000000000000..a237261423b4 --- /dev/null +++ b/sound/soc/codecs/rt1320-sdw.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * rt1320-sdw.h -- RT1320 SDCA ALSA SoC audio driver header + * + * Copyright(c) 2024 Realtek Semiconductor Corp. + */ + +#ifndef __RT1320_SDW_H__ +#define __RT1320_SDW_H__ + +#include <linux/regmap.h> +#include <linux/soundwire/sdw.h> +#include <linux/soundwire/sdw_type.h> +#include <linux/soundwire/sdw_registers.h> +#include <sound/soc.h> + +/* imp-defined registers */ +#define RT1320_DEV_VERSION_ID_1 0xc404 + +#define RT1320_KR0_STATUS_CNT 0x1000f008 +#define RT1320_HIFI_VER_0 0x3fe2e000 +#define RT1320_HIFI_VER_1 0x3fe2e001 +#define RT1320_HIFI_VER_2 0x3fe2e002 +#define RT1320_HIFI_VER_3 0x3fe2e003 + +/* RT1320 SDCA Control - function number */ +#define FUNC_NUM_AMP 0x04 + +/* RT1320 SDCA entity */ +#define RT1320_SDCA_ENT0 0x00 +#define RT1320_SDCA_ENT_PDE11 0x2a +#define RT1320_SDCA_ENT_PDE23 0x33 +#define RT1320_SDCA_ENT_PDE27 0x27 +#define RT1320_SDCA_ENT_FU14 0x32 +#define RT1320_SDCA_ENT_FU21 0x03 +#define RT1320_SDCA_ENT_FU113 0x30 +#define RT1320_SDCA_ENT_CS14 0x13 +#define RT1320_SDCA_ENT_CS21 0x21 +#define RT1320_SDCA_ENT_CS113 0x12 +#define RT1320_SDCA_ENT_SAPU 0x29 +#define RT1320_SDCA_ENT_PPU21 0x04 + +/* RT1320 SDCA control */ +#define RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10 +#define RT1320_SDCA_CTL_REQ_POWER_STATE 0x01 +#define RT1320_SDCA_CTL_FU_MUTE 0x01 +#define RT1320_SDCA_CTL_FU_VOLUME 0x02 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_MODE 0x10 +#define RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11 +#define RT1320_SDCA_CTL_POSTURE_NUMBER 0x10 +#define RT1320_SDCA_CTL_FUNC_STATUS 0x10 + +/* RT1320 SDCA channel */ +#define CH_01 0x01 +#define CH_02 0x02 + +/* Function_Status */ +#define FUNCTION_NEEDS_INITIALIZATION BIT(5) +#define FUNCTION_HAS_BEEN_RESET BIT(6) +#define FUNCTION_BUSY BIT(7) + +/* Sample Frequency Index */ +#define RT1320_SDCA_RATE_16000HZ 0x04 +#define RT1320_SDCA_RATE_32000HZ 0x07 +#define RT1320_SDCA_RATE_44100HZ 0x08 +#define RT1320_SDCA_RATE_48000HZ 0x09 +#define RT1320_SDCA_RATE_96000HZ 0x0b +#define RT1320_SDCA_RATE_192000HZ 0x0d + +enum { + RT1320_AIF1, +}; + +/* + * The version id will be useful to distinguish the capability between the different IC versions. + * Currently, VA and VB have different DSP FW versions. + */ +enum rt1320_version_id { + RT1320_VA, + RT1320_VB, +}; + +#define RT1320_VER_B_ID 0x07392238 + +struct rt1320_sdw_priv { + struct snd_soc_component *component; + struct regmap *regmap; + struct regmap *mbq_regmap; + struct sdw_slave *sdw_slave; + struct sdw_bus_params params; + bool hw_init; + bool first_hw_init; + int version_id; +}; + +#endif /* __RT1320_SDW_H__ */ -- 2.34.1

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RE: [PATCH v2] ASoC: rt1320: Add RT1320 SDCA vendor-specific driver
by Shuming [范書銘] 20 May '24

20 May '24

> > +static const struct reg_sequence rt1320_blind_write[] = { > > + { 0xc003, 0xe0 }, > ... > > + { 0xd486, 0xc3 }, > > +}; > > I would add a comment that the 'blind writes' is an SDCA term to deal with > platform-specific initialization, but in this case it seems that all the addresses > targeted are in the vendor-specific space Sure, will add a comment to describe what blind writes means. > > +static const struct reg_sequence rt1320_patch_code_write[] = { > > + { 0x10007000, 0x37 }, > ... > > + { 0x0000d540, 0x01 }, > > +}; > > I would add a comment on the targeted register space. It seems to be the > SDCA function 1, except for the last one? > > Also possibly move the tables to a different file to make the driver code easier > to get to (less scrolling required). The driver will add a comment for the patch_code_write. The setting of the last one notifies the patch code and blind writes are done. That is the handshake mechanism we shall set. > > +static int rt1320_read_prop(struct sdw_slave *slave) { > > + struct sdw_slave_prop *prop = &slave->prop; > > + int nval; > > + int i, j; > > + u32 bit; > > + unsigned long addr; > > + struct sdw_dpn_prop *dpn; > > + > > + sdw_slave_read_prop(slave); > > add a comment that this is needed to fetch the lane information from platform > firmware. OK, will do. > > +static const struct sdw_device_id rt1320_id[] = { > > + SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0),\ > > missing class ID 1? Will add class ID 1. > > + > > +/* Function_Status */ > > +#define FUNCTION_NEEDS_INITIALIZATION BIT(5) > > +#define FUNCTION_HAS_BEEN_RESET BIT(6) > > You seem to use only NEEDS_INITIALIZATION, what happens on a RESET? The RESET should influence the SDCA control. The blind writes doesn't set the SDCA control. Therefore, the driver doesn't check RESET flag. > > +#define FUNCTION_BUSY BIT(7) > not used, can it be asserted? Will remove it. > Looks mostly good otherwise, thanks for the patch.

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Re: [PATCH v2 2/3] ASoC: soc-pcm: Indicate warning if CPU / Codec availability mismatch
by Kuninori Morimoto 20 May '24

20 May '24

Hi Amadeusz > > + if ((dai_link->dpcm_playback || dai_link->playback_only) && > > + !has_playback_both) > > + dev_warn(rtd->card->dev, > > + "System reuqsts playback, but not available (%s)." > > Typo: reuqsts -> requests > > > + " Please update Codec driver\n", > > + dai_link->stream_name); > > + if ((dai_link->dpcm_capture || dai_link->capture_only) && > > + !has_capture_both) > > + dev_warn(rtd->card->dev, > > + "System reuqsts capture, but not available (%s)." > > Same here. Grr, thank you pointing it. Will fix in v3. Thank you for your help !! Best regards --- Renesas Electronics Ph.D. Kuninori Morimoto

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[PATCH] ALSA: usb-audio: Fix for sampling rates support for Mbox3
by Manuel Barrio Linares 16 May '24

16 May '24

Fixed wrong use of usb_sndctrlpipe to usb_rcvctrlpipe Signed-off-by: Manuel Barrio Linares <mbarriolinares(a)gmail.com> --- sound/usb/quirks.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c index 2f961f0e9378..58156fbca02c 100644 --- a/sound/usb/quirks.c +++ b/sound/usb/quirks.c @@ -1740,7 +1740,7 @@ static void mbox3_set_format_quirk(struct snd_usb_substream *subs, u32 current_rate; // Get current rate from card and check if changing it is needed - snd_usb_ctl_msg(subs->dev, usb_sndctrlpipe(subs->dev, 0), + snd_usb_ctl_msg(subs->dev, usb_rcvctrlpipe(subs->dev, 0), 0x01, 0x21 | USB_DIR_IN, 0x0100, 0x8101, &buff4, 4); current_rate = le32_to_cpu(buff4); dev_dbg(&subs->dev->dev, @@ -1765,7 +1765,7 @@ static void mbox3_set_format_quirk(struct snd_usb_substream *subs, // Check whether the change was successful buff4 = 0; - snd_usb_ctl_msg(subs->dev, usb_sndctrlpipe(subs->dev, 0), + snd_usb_ctl_msg(subs->dev, usb_rcvctrlpipe(subs->dev, 0), 0x01, 0x21 | USB_DIR_IN, 0x0100, 0x8101, &buff4, 4); if (new_rate != le32_to_cpu(buff4)) dev_warn(&subs->dev->dev, "MBOX3: Couldn't set the sample rate"); -- 2.45.1

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[PATCH] ASoC: codecs: ES8326: solve hp and button detect issue
by Zhang Yi 15 May '24

15 May '24

We got an error report about headphone type detection and button detection. We fixed the headphone type detection error by adjusting the condition of setting es8326->hp to 0.And we fixed the button detection error by adjusting micbias and vref. Signed-off-by: Zhang Yi <zhangyi(a)everest-semi.com> --- sound/soc/codecs/es8326.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/es8326.c b/sound/soc/codecs/es8326.c index 93385f181d2c..3031699a14c4 100755 --- a/sound/soc/codecs/es8326.c +++ b/sound/soc/codecs/es8326.c @@ -829,8 +829,8 @@ static void es8326_jack_detect_handler(struct work_struct *work) /* mute adc when mic path switch */ regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44); regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66); - es8326->hp = 0; } + es8326->hp = 0; regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01); regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x0a); regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x03); @@ -981,7 +981,7 @@ static int es8326_resume(struct snd_soc_component *component) regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0); usleep_range(10000, 15000); regmap_write(es8326->regmap, ES8326_HPJACK_TIMER, 0xd9); - regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0xcb); + regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0xd8); /* set headphone default type and detect pin */ regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x83); regmap_write(es8326->regmap, ES8326_CLK_RESAMPLE, 0x05); @@ -1018,7 +1018,7 @@ static int es8326_resume(struct snd_soc_component *component) regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F); /* select vdda as micbias source */ - regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23); + regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x03); /* set dac dsmclip = 1 */ regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08); regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15); -- 2.17.1

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