February 2021 - Alsa-devel - mailman.alsa-project.org

question about ALSA devices not showing up in buildroot build
by Bert Schiettecatte 03 Feb '21

03 Feb '21

Hi all I am working on getting my ALSA machine driver and codecs working. I ported over my code which was based on 4.11, and I'm using 5.9.12 at the moment. At first sight everything seems to be working, but the hw: , plughw: etc devices are missing and when I list the PCMs with acrecord -L, I don't see any, even though arecord -l does show the card. I am using buildroot for my rootfs. So I am wondering if this is an issue with incorrectly defining the structs in my driver code, or if this is an issue with missing package in my buildroot config, or if this is due to a missing configuration file for ALSA in the rootfs. Previously I was using an off the shelf linaro rootfs when I was still on kernel version 4.11, and there the PCMs were showing up correctly and I could see the multiple devices such as hw:, plughw:, dmix: etc. Thanks! Bert

3 5

sof-soundwire: use the ${find-device} lookup for the dmic device
by GitHub pull_request - opened 03 Feb '21

03 Feb '21

alsa-project/alsa-ucm-conf pull request #77 was opened from perexg: The PCM device number for the internal digital microphone is not fixed. Request URL : https://github.com/alsa-project/alsa-ucm-conf/pull/77 Patch URL : https://github.com/alsa-project/alsa-ucm-conf/pull/77.patch Repository URL: https://github.com/alsa-project/alsa-ucm-conf

1 0

[PATCH] soundwire: bus: Make sdw_nwrite() data pointer argument const
by Richard Fitzgerald 03 Feb '21

03 Feb '21

Idiomatically, write functions should take const pointers to the data buffer, as they don't change the data. They are also likely to be called from functions that receive a const data pointer. Internally the pointer is passed to function/structs shared with the read functions, requiring a cast, but this is an implementation detail that should be hidden by the public API. Signed-off-by: Richard Fitzgerald <rf(a)opensource.cirrus.com> --- drivers/soundwire/bus.c | 6 +++--- include/linux/soundwire/sdw.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c index d9deafdcf495..4c76358416c5 100644 --- a/drivers/soundwire/bus.c +++ b/drivers/soundwire/bus.c @@ -394,13 +394,13 @@ sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) } static int -sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) +sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val) { struct sdw_msg msg; int ret; ret = sdw_fill_msg(&msg, slave, addr, count, - slave->dev_num, SDW_MSG_FLAG_WRITE, val); + slave->dev_num, SDW_MSG_FLAG_WRITE, (u8 *)val); if (ret < 0) return ret; @@ -524,7 +524,7 @@ EXPORT_SYMBOL(sdw_nread); * @count: length * @val: Buffer for values to be read */ -int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) +int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val) { int ret; diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index f0b01b728640..18f5979d9a60 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -1006,6 +1006,6 @@ int sdw_bus_exit_clk_stop(struct sdw_bus *bus); int sdw_read(struct sdw_slave *slave, u32 addr); int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); -int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); +int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val); #endif /* __SOUNDWIRE_H */ -- 2.20.1

1 0

[PATCH 0/3] soundwire: clear bus clash/parity interrupt before the mask is enabled
by Bard Liao 03 Feb '21

03 Feb '21

The SoundWire specification allows a Slave device to report a bus clash or parity error with the in-band interrupt mechanism. Unfortunately, on some platforms, these errors are randomly reported and don't seem to be valid. This series suggests the addition of a Master level quirk to discard such interrupts. The quirk should in theory have been added at the Slave level, but since the problem was detected with different generations of Slave devices it's hard to point to a specific IP. The problem might also be board-dependent and hence dealing with a Master quirk is simpler. Bard Liao (2): soundwire: bus: clear bus clash interrupt before the mask is enabled soundwire: intel: add SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH quirk Pierre-Louis Bossart (1): soundwire: bus: clear parity interrupt before the mask is enabled drivers/soundwire/bus.c | 19 +++++++++++++++++++ drivers/soundwire/intel.c | 3 +++ include/linux/soundwire/sdw.h | 5 +++++ 3 files changed, 27 insertions(+) -- 2.17.1

3 16

Re: [PATCH 2/2] ASoC: mediatek: mt6359: add MT6359 accdet driver
by Argus Lin 03 Feb '21

03 Feb '21

Dear maintainers: Can you reply to me if any opinion? thanks B.R. Argus On Wed, 2021-01-06 at 20:19 +0800, Argus Lin wrote: > MT6359 audio codec support accessory detect features, adds MT6359 > accdet driver to support plug detection and key detection. > > Signed-off-by: Argus Lin <argus.lin(a)mediatek.com> > --- > sound/soc/codecs/Kconfig | 7 + > sound/soc/codecs/Makefile | 2 + > sound/soc/codecs/mt6359-accdet.c | 1951 ++++++++++++++++++++++++++++++++++++++ > sound/soc/codecs/mt6359-accdet.h | 136 +++ > sound/soc/codecs/mt6359.h | 1863 +++++++++++++++++++++++++++++++++--- > 5 files changed, 3853 insertions(+), 106 deletions(-) > create mode 100644 sound/soc/codecs/mt6359-accdet.c > create mode 100644 sound/soc/codecs/mt6359-accdet.h > > diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig > index ba4eb54..dbf3141 100644 > --- a/sound/soc/codecs/Kconfig > +++ b/sound/soc/codecs/Kconfig > @@ -1774,6 +1774,13 @@ config SND_SOC_MT6359 > help > Enable support for the platform which uses MT6359 as > external codec device. > +config SND_SOC_MT6359_ACCDET > + tristate "MediaTek MT6359 ACCDET driver" > + depends on MTK_PMIC_WRAP > + help > + ACCDET means Accessory Detection technology, MediaTek develop it > + for ASoC codec soc-jack detection mechanism. > + Select N if you don't have jack on board. > > config SND_SOC_MT6660 > tristate "Mediatek MT6660 Speaker Amplifier" > diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile > index d277f03..f77d057 100644 > --- a/sound/soc/codecs/Makefile > +++ b/sound/soc/codecs/Makefile > @@ -133,6 +133,7 @@ snd-soc-msm8916-digital-objs := msm8916-wcd-digital.o > snd-soc-mt6351-objs := mt6351.o > snd-soc-mt6358-objs := mt6358.o > snd-soc-mt6359-objs := mt6359.o > +snd-soc-mt6359-accdet-objs := mt6359-accdet.o > snd-soc-mt6660-objs := mt6660.o > snd-soc-nau8315-objs := nau8315.o > snd-soc-nau8540-objs := nau8540.o > @@ -448,6 +449,7 @@ obj-$(CONFIG_SND_SOC_MSM8916_WCD_DIGITAL) +=snd-soc-msm8916-digital.o > obj-$(CONFIG_SND_SOC_MT6351) += snd-soc-mt6351.o > obj-$(CONFIG_SND_SOC_MT6358) += snd-soc-mt6358.o > obj-$(CONFIG_SND_SOC_MT6359) += snd-soc-mt6359.o > +obj-$(CONFIG_SND_SOC_MT6359_ACCDET) += mt6359-accdet.o > obj-$(CONFIG_SND_SOC_MT6660) += snd-soc-mt6660.o > obj-$(CONFIG_SND_SOC_NAU8315) += snd-soc-nau8315.o > obj-$(CONFIG_SND_SOC_NAU8540) += snd-soc-nau8540.o > diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c > new file mode 100644 > index 0000000..ff90e4e > --- /dev/null > +++ b/sound/soc/codecs/mt6359-accdet.c > @@ -0,0 +1,1951 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 MediaTek Inc. > + * Author: Argus Lin <argus.lin(a)mediatek.com> > + */ > + > +#include <linux/of_gpio.h> > +#include <linux/of.h> > +#include <linux/of_irq.h> > +#include <linux/of_device.h> > +#include <linux/of_address.h> > +#include <linux/input.h> > +#include <linux/kthread.h> > +#include <linux/io.h> > +#include <linux/sched/clock.h> > +#include <linux/workqueue.h> > +#include <linux/timer.h> > +#include <linux/delay.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/init.h> > +#include <linux/irqdomain.h> > +#include <linux/irq.h> > +#include <linux/regmap.h> > +#include <sound/soc.h> > +#include <sound/jack.h> > +#include <linux/mfd/mt6397/core.h> > +#include "mt6359-accdet.h" > +#include "mt6359.h" > +/* grobal variable definitions */ > +#define REGISTER_VAL(x) ((x) - 1) > +#define HAS_CAP(_c, _x) \ > + ({typeof(_c)c = (_c); \ > + typeof(_x)x = (_x); \ > + (((c) & (x)) == (x)); }) > +#define ACCDET_PMIC_EINT_IRQ BIT(0) > +#define ACCDET_AP_GPIO_EINT BIT(1) > + > +#define ACCDET_PMIC_EINT0 BIT(2) > +#define ACCDET_PMIC_EINT1 BIT(3) > +#define ACCDET_PMIC_BI_EINT BIT(4) > + > +#define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5) > +#define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6) > +#define ACCDET_PMIC_RSV_EINT BIT(7) > + > +#define ACCDET_THREE_KEY BIT(8) > +#define ACCDET_FOUR_KEY BIT(9) > +#define ACCDET_TRI_KEY_CDD BIT(10) > +#define ACCDET_RSV_KEY BIT(11) > + > +#define ACCDET_ANALOG_FASTDISCHARGE BIT(12) > +#define ACCDET_DIGITAL_FASTDISCHARGE BIT(13) > +#define ACCDET_AD_FASTDISCHRAGE BIT(14) > + > +#define RET_LT_5K (-1) > +#define RET_GT_5K (0) > + > +/* Used to let accdet know if the pin has been fully plugged-in */ > +#define EINT_PLUG_OUT (0) > +#define EINT_PLUG_IN (1) > + > +struct mt63xx_accdet_data { > + struct snd_soc_jack jack; > + struct platform_device *pdev; > + struct device *dev; > + struct accdet_priv *data; > + atomic_t init_once; > + struct regmap *regmap; > + int accdet_irq; > + int accdet_eint0; > + int accdet_eint1; > + struct wakeup_source *wake_lock; > + struct wakeup_source *timer_lock; > + struct mutex res_lock; /* lock to protect flag */ > + bool eint_sync_flag; > + /* accdet FSM State & lock*/ > + unsigned int cur_eint_state; > + unsigned int eint0_state; > + unsigned int eint1_state; > + unsigned int accdet_status; > + unsigned int cable_type; > + unsigned int cur_key; > + unsigned int cali_voltage; > + int auxadc_offset; > + unsigned int eint_id; > + /* when caps include ACCDET_AP_GPIO_EINT */ > + struct pinctrl *pinctrl; > + struct pinctrl_state *pins_eint; > + unsigned int gpiopin; > + unsigned int gpio_hp_deb; > + unsigned int gpioirq; > + unsigned int accdet_eint_type; > + /* when MICBIAS_DISABLE_TIMER timeout, queue work: dis_micbias_work */ > + struct work_struct delay_init_work; > + struct workqueue_struct *delay_init_workqueue; > + struct work_struct dis_micbias_work; > + struct workqueue_struct *dis_micbias_workqueue; > + struct work_struct accdet_work; > + struct workqueue_struct *accdet_workqueue; > + /* when eint issued, queue work: eint_work */ > + struct work_struct eint_work; > + struct workqueue_struct *eint_workqueue; > +}; > + > +static struct mt63xx_accdet_data *accdet; > + > +static struct head_dts_data accdet_dts; > +struct pwm_deb_settings *cust_pwm_deb; > + > +struct accdet_priv { > + unsigned int caps; > +}; > + > +static struct accdet_priv mt6359_accdet[] = { > + { > + .caps = 0, > + }, > +}; > + > +const struct of_device_id mt6359_accdet_of_match[] = { > + { > + .compatible = "mediatek,mt6359-accdet", > + .data = &mt6359_accdet, > + }, { > + /* sentinel */ > + }, > +}; > + > +static struct platform_driver mt6359_accdet_driver; > +static const struct snd_soc_component_driver mt6359_accdet_soc_driver; > + > +#define ACCDET_INIT_WAIT_TIMER (10 * HZ) > +static struct timer_list accdet_init_timer; > +static void delay_init_timerhandler(struct timer_list *t); > +/* micbias_timer: disable micbias if no accdet irq after eint, > + * timeout: 6 seconds > + * timerHandler: dis_micbias_timerhandler() > + */ > +#define MICBIAS_DISABLE_TIMER (6 * HZ) > +static struct timer_list micbias_timer; > +static void dis_micbias_timerhandler(struct timer_list *t); > + > +static unsigned int button_press_debounce = 0x400; > +static unsigned int button_press_debounce_01 = 0x800; > + > +/* local function declaration */ > +static void accdet_init_once(void); > +static inline void accdet_init(void); > +static void accdet_init_debounce(void); > +static unsigned int adjust_eint_analog_setting(void); > +static unsigned int adjust_eint_setting(unsigned int eintsts); > +static void config_digital_init_by_mode(void); > +static void config_eint_init_by_mode(void); > +static unsigned int get_triggered_eint(void); > +static void recover_eint_analog_setting(void); > +static void recover_eint_digital_setting(void); > +static void recover_eint_setting(unsigned int eintsts); > +static void send_status_event(unsigned int cable_type, unsigned int status); > +static void accdet_set_debounce(int state, unsigned int debounce); > + > +/* global function declaration */ > + > +static u64 mt6359_accdet_get_current_time(void) > +{ > + return sched_clock(); > +} > + > +static bool mt6359_accdet_timeout_ns(u64 start_time_ns, u64 timeout_time_ns) > +{ > + u64 cur_time = 0; > + u64 elapse_time = 0; > + > + /* get current tick, ns */ > + cur_time = mt6359_accdet_get_current_time(); > + if (cur_time < start_time_ns) { > + start_time_ns = cur_time; > + /* 400us */ > + timeout_time_ns = 400 * 1000; > + } > + elapse_time = cur_time - start_time_ns; > + > + /* check if timeout */ > + if (timeout_time_ns <= elapse_time) > + return false; > + > + return true; > +} > + > +static unsigned int check_key(unsigned int v) > +{ > + if (HAS_CAP(accdet->data->caps, ACCDET_FOUR_KEY)) { > + if (v < accdet_dts.four_key.down && v >= accdet_dts.four_key.up) > + return DW_KEY; > + if (v < accdet_dts.four_key.up && v >= accdet_dts.four_key.voice) > + return UP_KEY; > + if (v < accdet_dts.four_key.voice && v >= accdet_dts.four_key.mid) > + return AS_KEY; > + if (v < accdet_dts.four_key.mid) > + return MD_KEY; > + } else { > + if (v < accdet_dts.three_key.down && v >= accdet_dts.three_key.up) > + return DW_KEY; > + if (v < accdet_dts.three_key.up && v >= accdet_dts.three_key.mid) > + return UP_KEY; > + if (v < accdet_dts.three_key.mid) > + return MD_KEY; > + } > + return NO_KEY; > +} > + > +static void send_key_event(unsigned int keycode, unsigned int flag) > +{ > + int report = 0; > + > + switch (keycode) { > + case DW_KEY: > + if (flag != 0) > + report = SND_JACK_BTN_1; > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_BTN_1); > + break; > + case UP_KEY: > + if (flag != 0) > + report = SND_JACK_BTN_2; > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_BTN_2); > + break; > + case MD_KEY: > + if (flag != 0) > + report = SND_JACK_BTN_0; > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_BTN_0); > + break; > + case AS_KEY: > + if (flag != 0) > + report = SND_JACK_BTN_3; > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_BTN_3); > + break; > + } > +} > + > +static void send_status_event(unsigned int cable_type, unsigned int status) > +{ > + int report = 0; > + > + switch (cable_type) { > + case HEADSET_NO_MIC: > + if (status) > + report = SND_JACK_HEADPHONE; > + else > + report = 0; > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_HEADPHONE); > + /* when plug 4-pole out, if both AB=3 AB=0 happen,3-pole plug > + * in will be incorrectly reported, then 3-pole plug-out is > + * reported,if no mantory 4-pole plug-out, icon would be > + * visible. > + */ > + if (status == 0) { > + report = 0; > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_MICROPHONE); > + } > + pr_info("accdet HEADPHONE(3-pole) %s\n", > + status ? "PlugIn" : "PlugOut"); > + break; > + case HEADSET_MIC: > + /* when plug 4-pole out, 3-pole plug out should also be > + * reported for slow plug-in case > + */ > + if (status == 0) { > + report = 0; > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_HEADPHONE); > + } > + if (status) > + report = SND_JACK_MICROPHONE; > + else > + report = 0; > + > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_MICROPHONE); > + pr_info("accdet MICROPHONE(4-pole) %s\n", > + status ? "PlugIn" : "PlugOut"); > + /* when press key for a long time then plug in > + * even recoginized as 4-pole > + * disable micbias timer still timeout after 6s > + * it check AB=00(because keep to press key) then disable > + * micbias, it will cause key no response > + */ > + del_timer_sync(&micbias_timer); > + break; > + case LINE_OUT_DEVICE: > + if (status) > + report = SND_JACK_LINEOUT; > + else > + report = 0; > + > + snd_soc_jack_report(&accdet->jack, report, SND_JACK_LINEOUT); > + pr_info("accdet LineOut %s\n", > + status ? "PlugIn" : "PlugOut"); > + break; > + default: > + pr_info("%s Invalid cableType\n", __func__); > + } > +} > + > +static void multi_key_detection(unsigned int cur_AB) > +{ > + if (cur_AB == ACCDET_STATE_AB_00) > + accdet->cur_key = check_key(accdet->cali_voltage); > + > + /* delay to wait eint been flaged in register. > + * or eint handler issued. accdet->cur_eint_state == PLUG_OUT > + */ > + usleep_range(10000, 12000); > + > + if (HAS_CAP(accdet->data->caps, ACCDET_AP_GPIO_EINT)) { > + if (accdet->cur_eint_state == EINT_PLUG_IN) > + send_key_event(accdet->cur_key, !cur_AB); > + else > + accdet->cur_key = NO_KEY; > + } else { > + bool irq_bit = false; > + unsigned int val = 0; > + > + regmap_read(accdet->regmap, ACCDET_IRQ_ADDR, &val); > + irq_bit = !(val & ACCDET_EINT_IRQ_B2_B3); > + /* send key when: > + * no eint is flaged in reg, and now eint PLUG_IN > + */ > + if (irq_bit && accdet->cur_eint_state == EINT_PLUG_IN) > + send_key_event(accdet->cur_key, !cur_AB); > + else > + accdet->cur_key = NO_KEY; > + } > + > + if (cur_AB) > + accdet->cur_key = NO_KEY; > +} > + > +static inline void clear_accdet_int(void) > +{ > + /* it is safe by using polling to adjust when to clear IRQ_CLR_BIT */ > + regmap_update_bits(accdet->regmap, ACCDET_IRQ_ADDR, > + BIT(ACCDET_IRQ_CLR_SFT), BIT(ACCDET_IRQ_CLR_SFT)); > +} > + > +static inline void clear_accdet_int_check(void) > +{ > + u64 cur_time = mt6359_accdet_get_current_time(); > + unsigned int val = 0; > + > + regmap_read(accdet->regmap, ACCDET_IRQ_ADDR, &val); > + while (val & ACCDET_IRQ_MASK_SFT && > + mt6359_accdet_timeout_ns(cur_time, ACCDET_TIME_OUT)) > + ; > + /* clear accdet int, modify for fix interrupt trigger twice error */ > + regmap_update_bits(accdet->regmap, ACCDET_IRQ_ADDR, > + BIT(ACCDET_IRQ_CLR_SFT), 0); > + regmap_update_bits(accdet->regmap, RG_INT_STATUS_ACCDET_ADDR, > + BIT(RG_INT_STATUS_ACCDET_SFT), > + BIT(RG_INT_STATUS_ACCDET_SFT)); > +} > + > +static inline void clear_accdet_eint(unsigned int eintid) > +{ > + if ((eintid & PMIC_EINT0) == PMIC_EINT0) { > + regmap_update_bits(accdet->regmap, ACCDET_IRQ_ADDR, > + BIT(ACCDET_EINT0_IRQ_CLR_SFT), > + BIT(ACCDET_EINT0_IRQ_CLR_SFT)); > + } > + if ((eintid & PMIC_EINT1) == PMIC_EINT1) { > + regmap_update_bits(accdet->regmap, ACCDET_IRQ_ADDR, > + BIT(ACCDET_EINT1_IRQ_CLR_SFT), > + BIT(ACCDET_EINT1_IRQ_CLR_SFT)); > + } > +} > + > +static inline void clear_accdet_eint_check(unsigned int eintid) > +{ > + u64 cur_time = mt6359_accdet_get_current_time(); > + unsigned int val = 0; > + > + regmap_read(accdet->regmap, ACCDET_IRQ_ADDR, &val); > + > + if ((eintid & PMIC_EINT0) == PMIC_EINT0) { > + while (val & ACCDET_EINT0_IRQ_MASK_SFT && > + mt6359_accdet_timeout_ns(cur_time, ACCDET_TIME_OUT)) > + ; > + regmap_update_bits(accdet->regmap, ACCDET_IRQ_ADDR, > + BIT(ACCDET_EINT0_IRQ_CLR_SFT), 0); > + regmap_update_bits(accdet->regmap, > + RG_INT_STATUS_ACCDET_ADDR, > + BIT(RG_INT_STATUS_ACCDET_EINT0_SFT), > + BIT(RG_INT_STATUS_ACCDET_EINT0_SFT)); > + } > + if ((eintid & PMIC_EINT1) == PMIC_EINT1) { > + while (val & ACCDET_EINT1_IRQ_MASK_SFT && > + mt6359_accdet_timeout_ns(cur_time, ACCDET_TIME_OUT)) > + ; > + regmap_update_bits(accdet->regmap, ACCDET_IRQ_ADDR, > + BIT(ACCDET_EINT1_IRQ_CLR_SFT), 0); > + regmap_update_bits(accdet->regmap, > + RG_INT_STATUS_ACCDET_ADDR, > + BIT(RG_INT_STATUS_ACCDET_EINT1_SFT), > + BIT(RG_INT_STATUS_ACCDET_EINT1_SFT)); > + } > +} > + > +static unsigned int adjust_eint_analog_setting(void) > +{ > + if (accdet_dts.eint_detect_mode == 0x3 || > + accdet_dts.eint_detect_mode == 0x4) { > + /* ESD switches off */ > + regmap_update_bits(accdet->regmap, > + RG_ACCDETSPARE_ADDR, 1 << 8, 0); > + } > + if (accdet_dts.eint_detect_mode == 0x4) { > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* enable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), > + BIT(RG_EINT0CONFIGACCDET_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + /* enable RG_EINT1CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), > + BIT(RG_EINT1CONFIGACCDET_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + /* enable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), > + BIT(RG_EINT0CONFIGACCDET_SFT)); > + /* enable RG_EINT1CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), > + BIT(RG_EINT1CONFIGACCDET_SFT)); > + } > + if (accdet_dts.eint_use_ext_res == 0x3 || > + accdet_dts.eint_use_ext_res == 0x4) { > + /*select 500k, use internal resistor */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0HIRENB_ADDR, > + BIT(RG_EINT0HIRENB_SFT), > + BIT(RG_EINT0HIRENB_SFT)); > + } > + } > + return 0; > +} > + > +static unsigned int adjust_eint_digital_setting(void) > +{ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* disable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + /* disable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + /* disable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), 0); > + /* disable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), 0); > + } > + > + if (accdet_dts.eint_detect_mode == 0x4) { > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* set DA stable signal */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT0_CEN_STABLE_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + /* set DA stable signal */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT1_CEN_STABLE_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + /* set DA stable signal */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT0_CEN_STABLE_SFT), 0); > + /* set DA stable signal */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT1_CEN_STABLE_SFT), 0); > + } > + } > + return 0; > +} > + > +static unsigned int adjust_eint_setting(unsigned int eintsts) > +{ > + if (eintsts == M_PLUG_IN) { > + /* adjust digital setting */ > + adjust_eint_digital_setting(); > + /* adjust analog setting */ > + adjust_eint_analog_setting(); > + } else if (eintsts == M_PLUG_OUT) { > + /* set debounce to 1ms */ > + accdet_set_debounce(eint_state000, > + accdet_dts.pwm_deb.eint_debounce0); > + } else { > + pr_debug("should not be here %s()\n", __func__); > + } > + > + return 0; > +} > + > +static void recover_eint_analog_setting(void) > +{ > + if (accdet_dts.eint_detect_mode == 0x3 || > + accdet_dts.eint_detect_mode == 0x4) { > + /* ESD switches on */ > + regmap_update_bits(accdet->regmap, RG_ACCDETSPARE_ADDR, > + 1 << 8, 1 << 8); > + } > + if (accdet_dts.eint_detect_mode == 0x4) { > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* disable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + /* disable RG_EINT1CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + /* disable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), 0); > + /* disable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), 0); > + } > + regmap_update_bits(accdet->regmap, RG_EINT0HIRENB_ADDR, > + BIT(RG_EINT0HIRENB_SFT), 0); > + } > +} > + > +static void recover_eint_digital_setting(void) > +{ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_M_SW_EN_ADDR, > + BIT(ACCDET_EINT0_M_SW_EN_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_M_SW_EN_ADDR, > + BIT(ACCDET_EINT1_M_SW_EN_SFT), 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_M_SW_EN_ADDR, > + BIT(ACCDET_EINT0_M_SW_EN_SFT), 0); > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_M_SW_EN_ADDR, > + BIT(ACCDET_EINT1_M_SW_EN_SFT), 0); > + } > + if (accdet_dts.eint_detect_mode == 0x4) { > + /* enable eint0cen */ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* enable eint0cen */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT0_CEN_STABLE_SFT), > + BIT(ACCDET_EINT0_CEN_STABLE_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + /* enable eint1cen */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT1_CEN_STABLE_SFT), > + BIT(ACCDET_EINT1_CEN_STABLE_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + /* enable eint0cen */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT0_CEN_STABLE_SFT), > + BIT(ACCDET_EINT0_CEN_STABLE_SFT)); > + /* enable eint1cen */ > + regmap_update_bits(accdet->regmap, > + ACCDET_DA_STABLE_ADDR, > + BIT(ACCDET_EINT1_CEN_STABLE_SFT), > + BIT(ACCDET_EINT1_CEN_STABLE_SFT)); > + } > + } > + > + if (accdet_dts.eint_detect_mode != 0x1) { > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* enable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + /* enable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + /* enable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); > + /* enable inverter */ > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); > + } > + } > +} > + > +static void recover_eint_setting(unsigned int eintsts) > +{ > + if (eintsts == M_PLUG_OUT) { > + recover_eint_analog_setting(); > + recover_eint_digital_setting(); > + } > +} > + > +static unsigned int get_triggered_eint(void) > +{ > + unsigned int eint_ID = NO_PMIC_EINT; > + unsigned int irq_status = 0; > + > + regmap_read(accdet->regmap, ACCDET_IRQ_ADDR, &irq_status); > + > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + if ((irq_status & ACCDET_EINT0_IRQ_MASK_SFT) == > + ACCDET_EINT0_IRQ_MASK_SFT) > + eint_ID = PMIC_EINT0; > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + if ((irq_status & ACCDET_EINT1_IRQ_MASK_SFT) == > + ACCDET_EINT1_IRQ_MASK_SFT) > + eint_ID = PMIC_EINT1; > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + if ((irq_status & ACCDET_EINT0_IRQ_MASK_SFT) == > + ACCDET_EINT0_IRQ_MASK_SFT) > + eint_ID |= PMIC_EINT0; > + if ((irq_status & ACCDET_EINT1_IRQ_MASK_SFT) == > + ACCDET_EINT1_IRQ_MASK_SFT) > + eint_ID |= PMIC_EINT1; > + } > + return eint_ID; > +} > + > +static inline void enable_accdet(unsigned int state_swctrl) > +{ > + /* enable ACCDET unit */ > + regmap_update_bits(accdet->regmap, ACCDET_SW_EN_ADDR, > + BIT(ACCDET_SW_EN_SFT), BIT(ACCDET_SW_EN_SFT)); > +} > + > +static inline void disable_accdet(void) > +{ > + clear_accdet_int(); > + usleep_range(200, 300); > + mutex_lock(&accdet->res_lock); > + clear_accdet_int_check(); > + mutex_unlock(&accdet->res_lock); > + > + /* recover accdet debounce0,3 */ > + accdet_set_debounce(accdet_state000, cust_pwm_deb->debounce0); > + accdet_set_debounce(accdet_state001, cust_pwm_deb->debounce1); > + accdet_set_debounce(accdet_state011, cust_pwm_deb->debounce3); > +} > + > +static inline void headset_plug_out(void) > +{ > + send_status_event(accdet->cable_type, 0); > + accdet->accdet_status = PLUG_OUT; > + accdet->cable_type = NO_DEVICE; > + > + if (accdet->cur_key != 0) { > + send_key_event(accdet->cur_key, 0); > + accdet->cur_key = 0; > + } > + pr_info("accdet %s, set cable_type = NO_DEVICE\n", __func__); > +} > + > +static void dis_micbias_timerhandler(struct timer_list *t) > +{ > + int ret = 0; > + > + ret = queue_work(accdet->dis_micbias_workqueue, > + &accdet->dis_micbias_work); > + if (!ret) > + pr_notice("Error: %s (%d)\n", __func__, ret); > +} > + > +static void dis_micbias_work_callback(struct work_struct *work) > +{ > + unsigned int cur_AB = 0, eint = 0; > + unsigned int val = 0; > + > + /* check EINT0 status, if plug out, > + * not need to disable accdet here > + */ > + regmap_read(accdet->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val); > + eint = ((val >> ACCDET_EINT0_MEM_IN_SFT) & ACCDET_EINT0_MEM_IN_MASK); > + if (eint == M_PLUG_OUT) { > + pr_notice("%s Plug-out, no need disable micbias\n", __func__); > + return; > + } > + > + regmap_read(accdet->regmap, ACCDET_MEM_IN_ADDR, &val); > + cur_AB = (val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK; > + > + /* if 3pole disable accdet > + * if <20k + 4pole, disable accdet will disable accdet > + * plug out interrupt. The behavior will same as 3pole > + */ > + if (accdet->cable_type == HEADSET_NO_MIC || > + cur_AB == ACCDET_STATE_AB_00 || > + cur_AB == ACCDET_STATE_AB_11) { > + regmap_update_bits(accdet->regmap, ACCDET_SW_EN_ADDR, > + BIT(ACCDET_SW_EN_SFT), 0); > + disable_accdet(); > + } > +} > + > +static void eint_work_callback(struct work_struct *work) > +{ > + if (accdet->cur_eint_state == EINT_PLUG_IN) { > + /* disable vusb LP */ > + regmap_write(accdet->regmap, RG_LDO_VUSB_HW0_OP_EN_ADDR, 0x8000); > + > + mutex_lock(&accdet->res_lock); > + accdet->eint_sync_flag = true; > + mutex_unlock(&accdet->res_lock); > + __pm_wakeup_event(accdet->timer_lock, > + jiffies_to_msecs(7 * HZ)); > + > + accdet_init(); > + > + enable_accdet(0); > + } else { > + mutex_lock(&accdet->res_lock); > + accdet->eint_sync_flag = false; > + mutex_unlock(&accdet->res_lock); > + del_timer_sync(&micbias_timer); > + > + regmap_update_bits(accdet->regmap, ACCDET_SW_EN_ADDR, > + BIT(ACCDET_SW_EN_SFT), 0); > + disable_accdet(); > + headset_plug_out(); > + } > + > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT_IRQ)) > + recover_eint_setting(accdet->eint_id); > + else if (HAS_CAP(accdet->data->caps, ACCDET_AP_GPIO_EINT)) > + enable_irq(accdet->gpioirq); > +} > + > +static void accdet_set_debounce(int state, unsigned int debounce) > +{ > + switch (state) { > + case accdet_state000: > + /* set ACCDET debounce value = debounce/32 ms */ > + regmap_write(accdet->regmap, ACCDET_DEBOUNCE0_ADDR, debounce); > + break; > + case accdet_state001: > + regmap_write(accdet->regmap, ACCDET_DEBOUNCE1_ADDR, debounce); > + break; > + case accdet_state010: > + regmap_write(accdet->regmap, ACCDET_DEBOUNCE2_ADDR, debounce); > + break; > + case accdet_state011: > + regmap_write(accdet->regmap, ACCDET_DEBOUNCE3_ADDR, debounce); > + break; > + case accdet_auxadc: > + /* set auxadc debounce:0x42(2ms) */ > + regmap_write(accdet->regmap, > + ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR, debounce); > + break; > + case eint_state000: > + regmap_update_bits(accdet->regmap, ACCDET_EINT_DEBOUNCE0_ADDR, > + 0xF << ACCDET_EINT_DEBOUNCE0_SFT, > + debounce << ACCDET_EINT_DEBOUNCE0_SFT); > + break; > + case eint_state001: > + regmap_update_bits(accdet->regmap, ACCDET_EINT_DEBOUNCE1_ADDR, > + 0xF << ACCDET_EINT_DEBOUNCE1_SFT, > + debounce << ACCDET_EINT_DEBOUNCE1_SFT); > + break; > + case eint_state010: > + regmap_update_bits(accdet->regmap, ACCDET_EINT_DEBOUNCE2_ADDR, > + 0xF << ACCDET_EINT_DEBOUNCE2_SFT, > + debounce << ACCDET_EINT_DEBOUNCE2_SFT); > + break; > + case eint_state011: > + regmap_update_bits(accdet->regmap, ACCDET_EINT_DEBOUNCE3_ADDR, > + 0xF << ACCDET_EINT_DEBOUNCE3_SFT, > + debounce << ACCDET_EINT_DEBOUNCE3_SFT); > + break; > + case eint_inverter_state000: > + regmap_write(accdet->regmap, ACCDET_EINT_INVERTER_DEBOUNCE_ADDR, > + debounce); > + break; > + default: > + pr_notice("Error: %s error state (%d)\n", __func__, state); > + break; > + } > +} > + > +static inline void check_cable_type(void) > +{ > + unsigned int cur_AB = 0; > + unsigned int val = 0; > + > + regmap_read(accdet->regmap, ACCDET_MEM_IN_ADDR, &val); > + > + cur_AB = (val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK; > + > + switch (accdet->accdet_status) { > + case PLUG_OUT: > + if (cur_AB == ACCDET_STATE_AB_00) { > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) { > + accdet->cable_type = HEADSET_NO_MIC; > + accdet->accdet_status = HOOK_SWITCH; > + } else { > + pr_notice("accdet hp has been plug-out\n"); > + } > + mutex_unlock(&accdet->res_lock); > + /* for IOT HP */ > + accdet_set_debounce(eint_state011, > + accdet_dts.pwm_deb.eint_debounce3); > + } else if (cur_AB == ACCDET_STATE_AB_01) { > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) { > + accdet->accdet_status = MIC_BIAS; > + accdet->cable_type = HEADSET_MIC; > + } else { > + pr_notice("accdet hp has been plug-out\n"); > + } > + mutex_unlock(&accdet->res_lock); > + /* adjust hook switch debounce time > + * for fast key press condition, avoid to miss key > + */ > + accdet_set_debounce(accdet_state000, > + button_press_debounce); > + > + /* adjust debounce1 to original 0x800(64ms), > + * to fix miss key issue when fast press double key. > + */ > + accdet_set_debounce(accdet_state001, > + button_press_debounce_01); > + accdet_set_debounce(eint_state011, 0x1); > + } else if (cur_AB == ACCDET_STATE_AB_11) { > + /* accdet PLUG_OUT state not change */ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT_IRQ)) { > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) { > + accdet->accdet_status = PLUG_OUT; > + accdet->cable_type = NO_DEVICE; > + } else { > + pr_notice("accdet hp been plug-out\n"); > + } > + mutex_unlock(&accdet->res_lock); > + } > + } else { > + pr_notice("accdet %s Invalid AB.\n", __func__); > + } > + break; > + case MIC_BIAS: > + if (cur_AB == ACCDET_STATE_AB_00) { > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) { > + accdet->accdet_status = HOOK_SWITCH; > + multi_key_detection(cur_AB); > + } else { > + pr_notice("accdet hp has been plug-out\n"); > + } > + mutex_unlock(&accdet->res_lock); > + } else if (cur_AB == ACCDET_STATE_AB_01) { > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) { > + accdet->accdet_status = MIC_BIAS; > + accdet->cable_type = HEADSET_MIC; > + /* accdet MIC_BIAS state not change */ > + } else { > + pr_notice("accdet hp has been plug-out\n"); > + } > + mutex_unlock(&accdet->res_lock); > + accdet_set_debounce(eint_state011, 0x1); > + } else if (cur_AB == ACCDET_STATE_AB_11) { > + /* accdet Don't send plug out in MIC_BIAS */ > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) > + accdet->accdet_status = PLUG_OUT; > + else > + pr_notice("accdet hp has been plug-out\n"); > + mutex_unlock(&accdet->res_lock); > + } else { > + pr_notice("accdet %s Invalid AB.\n", __func__); > + } > + break; > + case HOOK_SWITCH: > + if (cur_AB == ACCDET_STATE_AB_00) { > + } else if (cur_AB == ACCDET_STATE_AB_01) { > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) { > + multi_key_detection(cur_AB); > + accdet->accdet_status = MIC_BIAS; > + accdet->cable_type = HEADSET_MIC; > + } else { > + pr_notice("accdet hp has been plug-out\n"); > + } > + mutex_unlock(&accdet->res_lock); > + > + /* adjust debounce0 and debounce1 to fix miss key issue. > + */ > + accdet_set_debounce(accdet_state000, > + button_press_debounce); > + accdet_set_debounce(accdet_state001, > + button_press_debounce_01); > + /* for IOT HP */ > + accdet_set_debounce(eint_state011, 0x1); > + } else if (cur_AB == ACCDET_STATE_AB_11) { > + /* accdet Don't send plugout in HOOK_SWITCH */ > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) > + accdet->accdet_status = PLUG_OUT; > + else > + pr_notice("accdet hp has been plug-out\n"); > + mutex_unlock(&accdet->res_lock); > + } else { > + pr_notice("accdet %s Invalid AB.\n", __func__); > + } > + break; > + case STAND_BY: > + /* accdet %s STANDBY state.Err!Do nothing */ > + break; > + default: > + /* accdet %s Error state.Do nothing */ > + break; > + } > +} > + > +static void accdet_work_callback(struct work_struct *work) > +{ > + unsigned int pre_cable_type = accdet->cable_type; > + > + __pm_stay_awake(accdet->wake_lock); > + check_cable_type(); > + > + mutex_lock(&accdet->res_lock); > + if (accdet->eint_sync_flag) { > + if (pre_cable_type != accdet->cable_type) > + send_status_event(accdet->cable_type, 1); > + } > + mutex_unlock(&accdet->res_lock); > + if (accdet->cable_type != NO_DEVICE) { > + /* enable vusb LP */ > + regmap_write(accdet->regmap, RG_LDO_VUSB_HW0_OP_EN_ADDR, 0x8005); > + } > + > + __pm_relax(accdet->wake_lock); > +} > + > +static void accdet_queue_work(void) > +{ > + int ret; > + > + if (accdet->accdet_status == MIC_BIAS) > + accdet->cali_voltage = 10; > + > + ret = queue_work(accdet->accdet_workqueue, &accdet->accdet_work); > + if (!ret) > + pr_notice("Error: %s (%d)\n", __func__, ret); > +} > + > +static int pmic_eint_queue_work(int eint) > +{ > + int ret = 0; > + > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + if (eint == PMIC_EINT0) { > + if (accdet->cur_eint_state == EINT_PLUG_IN) { > + accdet_set_debounce(accdet_state011, > + cust_pwm_deb->debounce3); > + accdet->cur_eint_state = EINT_PLUG_OUT; > + } else { > + if (accdet->eint_id != M_PLUG_OUT) { > + accdet->cur_eint_state = EINT_PLUG_IN; > + mod_timer(&micbias_timer, > + jiffies + MICBIAS_DISABLE_TIMER); > + } > + } > + ret = queue_work(accdet->eint_workqueue, > + &accdet->eint_work); > + } else { > + pr_notice("%s invalid EINT ID!\n", __func__); > + } > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + if (eint == PMIC_EINT1) { > + if (accdet->cur_eint_state == EINT_PLUG_IN) { > + accdet_set_debounce(accdet_state011, > + cust_pwm_deb->debounce3); > + accdet->cur_eint_state = EINT_PLUG_OUT; > + } else { > + if (accdet->eint_id != M_PLUG_OUT) { > + accdet->cur_eint_state = EINT_PLUG_IN; > + mod_timer(&micbias_timer, > + jiffies + MICBIAS_DISABLE_TIMER); > + } > + } > + ret = queue_work(accdet->eint_workqueue, > + &accdet->eint_work); > + } else { > + pr_notice("%s invalid EINT ID!\n", __func__); > + } > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + if ((eint & PMIC_EINT0) == PMIC_EINT0) { > + if (accdet->eint0_state == EINT_PLUG_IN) { > + accdet_set_debounce(accdet_state011, > + cust_pwm_deb->debounce3); > + accdet->eint0_state = EINT_PLUG_OUT; > + } else { > + if (accdet->eint_id != M_PLUG_OUT) > + accdet->eint0_state = EINT_PLUG_IN; > + } > + } > + if ((eint & PMIC_EINT1) == PMIC_EINT1) { > + if (accdet->eint1_state == EINT_PLUG_IN) { > + accdet_set_debounce(accdet_state011, > + cust_pwm_deb->debounce3); > + accdet->eint1_state = EINT_PLUG_OUT; > + } else { > + if (accdet->eint_id != M_PLUG_OUT) > + accdet->eint1_state = EINT_PLUG_IN; > + } > + } > + > + /* bi_eint trigger issued current state, may */ > + if (accdet->cur_eint_state == EINT_PLUG_OUT) { > + accdet->cur_eint_state = > + accdet->eint0_state & accdet->eint1_state; > + if (accdet->cur_eint_state == EINT_PLUG_IN) { > + mod_timer(&micbias_timer, > + jiffies + MICBIAS_DISABLE_TIMER); > + ret = queue_work(accdet->eint_workqueue, > + &accdet->eint_work); > + } > + } else if (accdet->cur_eint_state == EINT_PLUG_IN) { > + if ((accdet->eint0_state | accdet->eint1_state) == EINT_PLUG_OUT) { > + clear_accdet_eint_check(PMIC_EINT0); > + clear_accdet_eint_check(PMIC_EINT1); > + } else if ((accdet->eint0_state & accdet->eint1_state) > + == EINT_PLUG_OUT) { > + accdet->cur_eint_state = EINT_PLUG_OUT; > + ret = queue_work(accdet->eint_workqueue, > + &accdet->eint_work); > + } > + } > + } > + return ret; > +} > + > +void accdet_irq_handle(void) > +{ > + unsigned int eint = 0; > + unsigned int irq_status = 0, acc_sts = 0, eint_sts = 0; > + unsigned int val = 0; > + > + eint = get_triggered_eint(); > + regmap_read(accdet->regmap, ACCDET_IRQ_ADDR, &irq_status); > + regmap_read(accdet->regmap, ACCDET_MEM_IN_ADDR, &acc_sts); > + regmap_read(accdet->regmap, ACCDET_EINT0_MEM_IN_ADDR, &eint_sts); > + > + if ((irq_status & ACCDET_IRQ_MASK_SFT) && eint == 0) { > + clear_accdet_int(); > + accdet_queue_work(); > + clear_accdet_int_check(); > + } else if (eint != NO_PMIC_EINT) { > + /* check EINT0 status */ > + regmap_read(accdet->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val); > + accdet->eint_id = ((val >> ACCDET_EINT0_MEM_IN_SFT) & > + ACCDET_EINT0_MEM_IN_MASK); > + /* adjust eint digital/analog setting */ > + adjust_eint_setting(accdet->eint_id); > + clear_accdet_eint(eint); > + clear_accdet_eint_check(eint); > + pmic_eint_queue_work(eint); > + } else { > + pr_notice("%s no interrupt detected!\n", __func__); > + } > +} > + > +static irqreturn_t mtk_accdet_irq_handler_thread(int irq, void *data) > +{ > + accdet_irq_handle(); > + > + return IRQ_HANDLED; > +} > + > +static irqreturn_t ex_eint_handler(int irq, void *data) > +{ > + int ret = 0; > + > + if (accdet->cur_eint_state == EINT_PLUG_IN) { > + /* To trigger EINT when the headset was plugged in > + * We set the polarity back as we initialed. > + */ > + if (accdet->accdet_eint_type == IRQ_TYPE_LEVEL_HIGH) > + irq_set_irq_type(accdet->gpioirq, IRQ_TYPE_LEVEL_HIGH); > + else > + irq_set_irq_type(accdet->gpioirq, IRQ_TYPE_LEVEL_LOW); > + gpio_set_debounce(accdet->gpiopin, accdet->gpio_hp_deb); > + > + accdet->cur_eint_state = EINT_PLUG_OUT; > + } else { > + /* To trigger EINT when the headset was plugged out > + * We set the opposite polarity to what we initialed. > + */ > + if (accdet->accdet_eint_type == IRQ_TYPE_LEVEL_HIGH) > + irq_set_irq_type(accdet->gpioirq, IRQ_TYPE_LEVEL_LOW); > + else > + irq_set_irq_type(accdet->gpioirq, IRQ_TYPE_LEVEL_HIGH); > + > + gpio_set_debounce(accdet->gpiopin, > + accdet_dts.plugout_deb * 1000); > + > + accdet->cur_eint_state = EINT_PLUG_IN; > + > + mod_timer(&micbias_timer, > + jiffies + MICBIAS_DISABLE_TIMER); > + } > + > + disable_irq_nosync(accdet->gpioirq); > + ret = queue_work(accdet->eint_workqueue, &accdet->eint_work); > + return IRQ_HANDLED; > +} > + > +static inline int ext_eint_setup(struct platform_device *platform_device) > +{ > + int ret = 0; > + unsigned int ints[4] = { 0 }; > + struct device_node *node = NULL; > + struct pinctrl_state *pins_default = NULL; > + > + accdet->pinctrl = devm_pinctrl_get(&platform_device->dev); > + if (IS_ERR(accdet->pinctrl)) { > + ret = PTR_ERR(accdet->pinctrl); > + return ret; > + } > + > + pins_default = pinctrl_lookup_state(accdet->pinctrl, "default"); > + if (IS_ERR(pins_default)) > + ret = PTR_ERR(pins_default); > + > + accdet->pins_eint = pinctrl_lookup_state(accdet->pinctrl, > + "state_eint_as_int"); > + if (IS_ERR(accdet->pins_eint)) { > + ret = PTR_ERR(accdet->pins_eint); > + return ret; > + } > + pinctrl_select_state(accdet->pinctrl, accdet->pins_eint); > + > + node = of_find_matching_node(node, mt6359_accdet_of_match); > + if (!node) > + return -1; > + > + accdet->gpiopin = of_get_named_gpio(node, "deb-gpios", 0); > + ret = of_property_read_u32(node, "debounce", > + &accdet->gpio_hp_deb); > + if (ret < 0) > + return ret; > + > + gpio_set_debounce(accdet->gpiopin, accdet->gpio_hp_deb); > + > + accdet->gpioirq = irq_of_parse_and_map(node, 0); > + ret = of_property_read_u32_array(node, "interrupts", ints, > + ARRAY_SIZE(ints)); > + if (ret) > + return ret; > + > + accdet->accdet_eint_type = ints[1]; > + ret = request_irq(accdet->gpioirq, ex_eint_handler, IRQF_TRIGGER_NONE, > + "accdet-eint", NULL); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static int mt6359_accdet_parse_dt(void) > +{ > + int ret = 0; > + struct device_node *node = NULL; > + int pwm_deb[15] = {0}; > + int three_key[4] = {0}; > + unsigned int tmp = 0; > + > + node = of_find_matching_node(node, mt6359_accdet_of_match); > + if (!node) { > + pr_notice("Error: %s can't find dts node\n", __func__); > + return -1; > + } > + > + ret = of_property_read_u32(node, "eint_use_ext_res", > + &accdet_dts.eint_use_ext_res); > + if (ret) { > + /* eint use internal resister */ > + accdet_dts.eint_use_ext_res = 0x0; > + } > + ret = of_property_read_u32(node, "eint_detect_mode", > + &accdet_dts.eint_detect_mode); > + if (ret) { > + /* eint detection mode equals to EINT HW Mode */ > + accdet_dts.eint_detect_mode = 0x4; > + } > + > + ret = of_property_read_u32(node, > + "accdet-mic-vol", &accdet_dts.mic_vol); > + if (ret) > + accdet_dts.mic_vol = 8; > + > + ret = of_property_read_u32(node, "accdet-plugout-debounce", > + &accdet_dts.plugout_deb); > + if (ret) > + accdet_dts.plugout_deb = 1; > + > + ret = of_property_read_u32(node, > + "accdet-mic-mode", &accdet_dts.mic_mode); > + if (ret) > + accdet_dts.mic_mode = 2; > + > + ret = of_property_read_u32_array(node, "headset-mode-setting", pwm_deb, > + ARRAY_SIZE(pwm_deb)); > + /* debounce8(auxadc debounce) is default, needn't get from dts */ > + if (!ret) > + memcpy(&accdet_dts.pwm_deb, pwm_deb, sizeof(pwm_deb)); > + > + cust_pwm_deb = &accdet_dts.pwm_deb; > + > + ret = of_property_read_u32(node, "headset-eint-level-pol", > + &accdet_dts.eint_pol); > + if (ret) > + accdet_dts.eint_pol = 8; > + > + ret = of_property_read_u32(node, "headset-use-ap-eint", &tmp); > + if (ret) > + tmp = 0; > + if (tmp == 0) > + accdet->data->caps |= ACCDET_PMIC_EINT_IRQ; > + else if (tmp == 1) > + accdet->data->caps |= ACCDET_AP_GPIO_EINT; > + > + ret = of_property_read_u32(node, "headset-eint-num", &tmp); > + if (ret) > + tmp = 0; > + if (tmp == 0) > + accdet->data->caps |= ACCDET_PMIC_EINT0; > + else if (tmp == 1) > + accdet->data->caps |= ACCDET_PMIC_EINT1; > + else if (tmp == 2) > + accdet->data->caps |= ACCDET_PMIC_BI_EINT; > + > + ret = of_property_read_u32(node, "headset-eint-trig-mode", &tmp); > + if (ret) > + tmp = 0; > + if (tmp == 0) > + accdet->data->caps |= ACCDET_PMIC_GPIO_TRIG_EINT; > + else if (tmp == 1) > + accdet->data->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT; > + > + ret = of_property_read_u32(node, "headset-key-mode", &tmp); > + if (ret) > + tmp = 0; > + if (tmp == 0) > + accdet->data->caps |= ACCDET_THREE_KEY; > + else if (tmp == 1) > + accdet->data->caps |= ACCDET_FOUR_KEY; > + else if (tmp == 2) > + accdet->data->caps |= ACCDET_TRI_KEY_CDD; > + > + if (HAS_CAP(accdet->data->caps, ACCDET_FOUR_KEY)) { > + int four_key[5]; > + > + ret = of_property_read_u32_array(node, > + "headset-four-key-threshold", > + four_key, ARRAY_SIZE(four_key)); > + if (!ret) { > + memcpy(&accdet_dts.four_key, four_key + 1, > + sizeof(struct four_key_threshold)); > + } else { > + pr_notice("accdet no 4-key-thrsh dts, use efuse\n"); > + } > + } else { > + if (HAS_CAP(accdet->data->caps, ACCDET_THREE_KEY)) { > + ret = of_property_read_u32_array(node, > + "headset-three-key-threshold", > + three_key, ARRAY_SIZE(three_key)); > + } else { > + ret = of_property_read_u32_array(node, > + "headset-three-key-threshold-CDD", > + three_key, > + ARRAY_SIZE(three_key)); > + } > + if (!ret) > + memcpy(&accdet_dts.three_key, three_key + 1, > + sizeof(struct three_key_threshold)); > + } > + > + ret = of_property_read_u32(node, "eint_use_ext_res", > + &accdet_dts.eint_use_ext_res); > + if (ret) { > + /* eint use internal resister */ > + accdet_dts.eint_use_ext_res = 0x0; > + } > + pr_info("accdet caps=%x\n", accdet->data->caps); > + > + return 0; > +} > + > +static void config_digital_init_by_mode(void) > +{ > + /* enable eint cmpmem pwm */ > + regmap_write(accdet->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR, > + (accdet_dts.pwm_deb.eint_pwm_width << 4 | > + accdet_dts.pwm_deb.eint_pwm_thresh)); > + /* DA signal stable */ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + regmap_write(accdet->regmap, ACCDET_DA_STABLE_ADDR, > + ACCDET_EINT0_STABLE_VAL); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + regmap_write(accdet->regmap, ACCDET_DA_STABLE_ADDR, > + ACCDET_EINT1_STABLE_VAL); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + regmap_write(accdet->regmap, ACCDET_DA_STABLE_ADDR, > + ACCDET_EINT0_STABLE_VAL); > + regmap_write(accdet->regmap, ACCDET_DA_STABLE_ADDR, > + ACCDET_EINT1_STABLE_VAL); > + } > + /* after receive n+1 number, interrupt issued. now is 2 times */ > + regmap_update_bits(accdet->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR, > + BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT), > + BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT)); > + /* setting HW mode, enable digital fast discharge > + * if use EINT0 & EINT1 detection, please modify > + * ACCDET_HWMODE_EN_ADDR[2:1] > + */ > + regmap_write(accdet->regmap, ACCDET_HWMODE_EN_ADDR, 0x100); > + > + regmap_update_bits(accdet->regmap, ACCDET_EINT_M_DETECT_EN_ADDR, > + BIT(ACCDET_EINT_M_DETECT_EN_SFT), 0); > + > + /* enable PWM */ > + regmap_write(accdet->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67); > + /* enable inverter detection */ > + if (accdet_dts.eint_detect_mode == 0x1) { > + /* disable inverter detection */ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), > + 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), > + 0); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), > + 0); > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), > + 0); > + } > + } else { > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT0_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); > + regmap_update_bits(accdet->regmap, > + ACCDET_EINT1_INVERTER_SW_EN_ADDR, > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT), > + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); > + } > + } > +} > + > +static void config_eint_init_by_mode(void) > +{ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + regmap_update_bits(accdet->regmap, RG_EINT0EN_ADDR, > + BIT(RG_EINT0EN_SFT), BIT(RG_EINT0EN_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + regmap_update_bits(accdet->regmap, RG_EINT1EN_ADDR, > + BIT(RG_EINT1EN_SFT), BIT(RG_EINT1EN_SFT)); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + regmap_update_bits(accdet->regmap, RG_EINT0EN_ADDR, > + BIT(RG_EINT0EN_SFT), BIT(RG_EINT0EN_SFT)); > + regmap_update_bits(accdet->regmap, RG_EINT1EN_ADDR, > + BIT(RG_EINT1EN_SFT), BIT(RG_EINT1EN_SFT)); > + } > + /* ESD switches on */ > + regmap_update_bits(accdet->regmap, RG_ACCDETSPARE_ADDR, > + 1 << 8, 1 << 8); > + /* before playback, set NCP pull low before nagative voltage */ > + regmap_update_bits(accdet->regmap, RG_NCP_PDDIS_EN_ADDR, > + BIT(RG_NCP_PDDIS_EN_SFT), BIT(RG_NCP_PDDIS_EN_SFT)); > + > + if (accdet_dts.eint_detect_mode == 0x1 || > + accdet_dts.eint_detect_mode == 0x2 || > + accdet_dts.eint_detect_mode == 0x3) { > + if (accdet_dts.eint_use_ext_res == 0x1) { > + /* select VTH to 2v and 500k, use external resitance */ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* disable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), > + 0); > + } else if (HAS_CAP(accdet->data->caps, > + ACCDET_PMIC_EINT1)) { > + /* disable RG_EINT1CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), > + 0); > + } else if (HAS_CAP(accdet->data->caps, > + ACCDET_PMIC_BI_EINT)) { > + /* disable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), > + 0); > + /* disable RG_EINT1CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), > + 0); > + } > + } else { > + /* select VTH to 2v and 500k, use internal resitance */ > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + /* enable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), > + BIT(RG_EINT0CONFIGACCDET_SFT)); > + } else if (HAS_CAP(accdet->data->caps, > + ACCDET_PMIC_EINT1)) { > + /* enable RG_EINT1CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), > + BIT(RG_EINT1CONFIGACCDET_SFT)); > + } else if (HAS_CAP(accdet->data->caps, > + ACCDET_PMIC_BI_EINT)) { > + /* enable RG_EINT0CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT0CONFIGACCDET_ADDR, > + BIT(RG_EINT0CONFIGACCDET_SFT), > + BIT(RG_EINT0CONFIGACCDET_SFT)); > + /* enable RG_EINT1CONFIGACCDET */ > + regmap_update_bits(accdet->regmap, > + RG_EINT1CONFIGACCDET_ADDR, > + BIT(RG_EINT1CONFIGACCDET_SFT), > + BIT(RG_EINT1CONFIGACCDET_SFT)); > + } > + } > + } > + > + if (accdet_dts.eint_detect_mode != 0x1) { > + /* current detect set 0.25uA */ > + regmap_update_bits(accdet->regmap, RG_ACCDETSPARE_ADDR, > + 0x3 << RG_ACCDETSPARE_SFT, > + 0x3 << RG_ACCDETSPARE_SFT); > + } > +} > + > +static void accdet_init_once(void) > +{ > + unsigned int reg = 0; > + > + /* reset the accdet unit */ > + regmap_update_bits(accdet->regmap, RG_ACCDET_RST_ADDR, > + BIT(RG_ACCDET_RST_SFT), BIT(RG_ACCDET_RST_SFT)); > + regmap_update_bits(accdet->regmap, RG_ACCDET_RST_ADDR, > + BIT(RG_ACCDET_RST_SFT), 0); > + > + /* clear high micbias1 voltage setting */ > + regmap_update_bits(accdet->regmap, RG_AUDPWDBMICBIAS1_ADDR, > + 0x3 << RG_AUDMICBIAS1HVEN_SFT, 0); > + /* clear micbias1 voltage */ > + regmap_update_bits(accdet->regmap, RG_AUDPWDBMICBIAS1_ADDR, > + 0x7 << RG_AUDMICBIAS1VREF_SFT, 0); > + > + /* init pwm frequency, duty & rise/falling delay */ > + regmap_write(accdet->regmap, ACCDET_PWM_WIDTH_ADDR, > + REGISTER_VAL(cust_pwm_deb->pwm_width)); > + regmap_write(accdet->regmap, ACCDET_PWM_THRESH_ADDR, > + REGISTER_VAL(cust_pwm_deb->pwm_thresh)); > + regmap_write(accdet->regmap, ACCDET_RISE_DELAY_ADDR, > + (cust_pwm_deb->fall_delay << 15 | cust_pwm_deb->rise_delay)); > + > + /* config micbias voltage, micbias1 vref is only controlled by accdet > + * if we need 2.8V, config [12:13] > + */ > + regmap_read(accdet->regmap, RG_AUDPWDBMICBIAS1_ADDR, &reg); > + if (accdet_dts.mic_vol <= 7) { > + /* micbias1 <= 2.7V */ > + regmap_write(accdet->regmap, RG_AUDPWDBMICBIAS1_ADDR, > + reg | (accdet_dts.mic_vol << RG_AUDMICBIAS1VREF_SFT) | > + RG_AUDMICBIAS1LOWPEN_MASK_SFT); > + } else if (accdet_dts.mic_vol == 8) { > + /* micbias1 = 2.8v */ > + regmap_write(accdet->regmap, RG_AUDPWDBMICBIAS1_ADDR, > + reg | (3 << RG_AUDMICBIAS1HVEN_SFT) | > + RG_AUDMICBIAS1LOWPEN_MASK_SFT); > + } else if (accdet_dts.mic_vol == 9) { > + /* micbias1 = 2.85v */ > + regmap_write(accdet->regmap, RG_AUDPWDBMICBIAS1_ADDR, > + reg | (1 << RG_AUDMICBIAS1HVEN_SFT) | > + RG_AUDMICBIAS1LOWPEN_MASK_SFT); > + } > + /* mic mode setting */ > + regmap_read(accdet->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, &reg); > + if (accdet_dts.mic_mode == HEADSET_MODE_1) { > + /* ACC mode*/ > + regmap_write(accdet->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, > + reg | RG_ACCDET_MODE_ANA11_MODE1); > + /* enable analog fast discharge */ > + regmap_update_bits(accdet->regmap, RG_ANALOGFDEN_ADDR, > + BIT(RG_ANALOGFDEN_SFT), > + BIT(RG_ANALOGFDEN_SFT)); > + regmap_update_bits(accdet->regmap, RG_ACCDETSPARE_ADDR, > + 0x3 << 11, 0x3 << 11); > + } else if (accdet_dts.mic_mode == HEADSET_MODE_2) { > + /* DCC mode Low cost mode without internal bias*/ > + regmap_write(accdet->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, > + reg | RG_ACCDET_MODE_ANA11_MODE2); > + /* enable analog fast discharge */ > + regmap_update_bits(accdet->regmap, RG_ANALOGFDEN_ADDR, > + 0x3 << RG_ANALOGFDEN_SFT, > + 0x3 << RG_ANALOGFDEN_SFT); > + } else if (accdet_dts.mic_mode == HEADSET_MODE_6) { > + /* DCC mode Low cost mode with internal bias, > + * bit8 = 1 to use internal bias > + */ > + regmap_write(accdet->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, > + reg | RG_ACCDET_MODE_ANA11_MODE6); > + regmap_update_bits(accdet->regmap, RG_AUDPWDBMICBIAS1_ADDR, > + BIT(RG_AUDMICBIAS1DCSW1PEN_SFT), > + BIT(RG_AUDMICBIAS1DCSW1PEN_SFT)); > + /* enable analog fast discharge */ > + regmap_update_bits(accdet->regmap, RG_ANALOGFDEN_ADDR, > + 0x3 << RG_ANALOGFDEN_SFT, > + 0x3 << RG_ANALOGFDEN_SFT); > + } > + > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT_IRQ)) { > + config_eint_init_by_mode(); > + config_digital_init_by_mode(); > + } else if (HAS_CAP(accdet->data->caps, ACCDET_AP_GPIO_EINT)) { > + /* set pull low pads and DCC mode */ > + regmap_write(accdet->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, > + 0x8F); > + /* disconnect configaccdet */ > + regmap_write(accdet->regmap, RG_EINT1CONFIGACCDET_ADDR, > + 0x0); > + /* disable eint comparator */ > + regmap_write(accdet->regmap, RG_EINT0CMPEN_ADDR, 0x0); > + /* enable PWM */ > + regmap_write(accdet->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x7); > + /* enable accdet sw mode */ > + regmap_write(accdet->regmap, ACCDET_HWMODE_EN_ADDR, 0x0); > + /* set DA signal to stable */ > + regmap_write(accdet->regmap, ACCDET_DA_STABLE_ADDR, 0x1); > + /* disable eint/inverter/sw_en */ > + regmap_write(accdet->regmap, ACCDET_SW_EN_ADDR, 0x0); > + } > +} > + > +static void accdet_init_debounce(void) > +{ > + /* set debounce to 1ms */ > + accdet_set_debounce(eint_state000, accdet_dts.pwm_deb.eint_debounce0); > + /* set debounce to 128ms */ > + accdet_set_debounce(eint_state011, accdet_dts.pwm_deb.eint_debounce3); > +} > + > +static inline void accdet_init(void) > +{ > + /* set and clear initial bit every eint interrutp */ > + regmap_update_bits(accdet->regmap, ACCDET_SEQ_INIT_ADDR, > + BIT(ACCDET_SEQ_INIT_SFT), BIT(ACCDET_SEQ_INIT_SFT)); > + mdelay(2); > + regmap_update_bits(accdet->regmap, ACCDET_SEQ_INIT_ADDR, > + BIT(ACCDET_SEQ_INIT_SFT), 0); > + mdelay(1); > + /* init the debounce time (debounce/32768)sec */ > + accdet_set_debounce(accdet_state000, cust_pwm_deb->debounce0); > + accdet_set_debounce(accdet_state001, cust_pwm_deb->debounce1); > + accdet_set_debounce(accdet_state011, cust_pwm_deb->debounce3); > + /* auxadc:2ms */ > + accdet_set_debounce(accdet_auxadc, cust_pwm_deb->debounce4); > + accdet_set_debounce(eint_state001, accdet_dts.pwm_deb.eint_debounce1); > + accdet_set_debounce(eint_inverter_state000, > + accdet_dts.pwm_deb.eint_inverter_debounce); > +} > + > +/* late init for DC trim, and this API Will be called by audio */ > +void mt6359_accdet_late_init(unsigned long data) > +{ > + if (atomic_cmpxchg(&accdet->init_once, 1, 0)) { > + del_timer_sync(&accdet_init_timer); > + accdet_init(); > + accdet_init_debounce(); > + accdet_init_once(); > + } else { > + pr_info("%s fail\n", __func__); > + } > +} > +EXPORT_SYMBOL(mt6359_accdet_late_init); > + > +static void delay_init_work_callback(struct work_struct *work) > +{ > + accdet_init(); > + accdet_init_debounce(); > + accdet_init_once(); > +} > + > +static void delay_init_timerhandler(struct timer_list *t) > +{ > + int ret = 0; > + > + ret = queue_work(accdet->delay_init_workqueue, > + &accdet->delay_init_work); > + if (!ret) > + pr_err("Error: %s (%d)\n", __func__, ret); > +} > + > +int mt6359_accdet_init(struct snd_soc_component *component, > + struct snd_soc_card *card) > +{ > + int ret = 0; > + struct mt63xx_accdet_data *priv = > + snd_soc_card_get_drvdata(component->card); > + > + /* Enable Headset and 4 Buttons Jack detection */ > + ret = snd_soc_card_jack_new(card, > + "Headset Jack", > + SND_JACK_HEADSET | > + SND_JACK_LINEOUT | > + SND_JACK_MECHANICAL, > + &priv->jack, > + NULL, 0); > + if (ret) { > + dev_err(card->dev, "Can't new Headset Jack %x\n", ret); > + return ret; > + } > + > + accdet->jack.jack->input_dev->id.bustype = BUS_HOST; > + snd_jack_set_key(accdet->jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); > + snd_jack_set_key(accdet->jack.jack, SND_JACK_BTN_1, KEY_VOLUMEDOWN); > + snd_jack_set_key(accdet->jack.jack, SND_JACK_BTN_2, KEY_VOLUMEUP); > + snd_jack_set_key(accdet->jack.jack, SND_JACK_BTN_3, KEY_VOICECOMMAND); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(mt6359_accdet_init); > + > +int mt6359_accdet_set_drvdata(struct snd_soc_card *card) > +{ > + snd_soc_card_set_drvdata(card, accdet); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(mt6359_accdet_set_drvdata); > + > +static int mt6359_accdet_probe(struct platform_device *pdev) > +{ > + int ret = 0; > + struct resource *res; > + struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent); > + const struct of_device_id *of_id = > + of_match_device(mt6359_accdet_of_match, &pdev->dev); > + if (!of_id) { > + dev_err(&pdev->dev, "Error: No device match found\n"); > + return -ENODEV; > + } > + > + accdet = devm_kzalloc(&pdev->dev, sizeof(*accdet), GFP_KERNEL); > + if (!accdet) > + return -ENOMEM; > + > + accdet->data = (struct accdet_priv *)of_id->data; > + accdet->pdev = pdev; > + > + /* parse dts attributes */ > + ret = mt6359_accdet_parse_dt(); > + if (ret) { > + dev_err(&pdev->dev, "Error: Get dts data failed (%d)\n", ret); > + return ret; > + } > + /* init lock */ > + accdet->wake_lock = wakeup_source_register(NULL, "accdet_wake_lock"); > + if (!accdet->wake_lock) { > + dev_err(&pdev->dev, "Error: get accdet_wake_lock fail\n"); > + return -ENOMEM; > + } > + accdet->timer_lock = wakeup_source_register(NULL, "accdet_timer_lock"); > + if (!accdet->timer_lock) { > + dev_err(&pdev->dev, "Error: get accdet_timer_lock fail\n"); > + return -ENOMEM; > + } > + mutex_init(&accdet->res_lock); > + > + platform_set_drvdata(pdev, accdet); > + ret = devm_snd_soc_register_component(&pdev->dev, > + &mt6359_accdet_soc_driver, > + NULL, 0); > + if (ret) { > + dev_err(&pdev->dev, "Error: register component fail\n"); > + return ret; > + } > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + accdet->regmap = mt6397_chip->regmap; > + accdet->dev = &pdev->dev; > + accdet->auxadc_offset = 0; > + > + /* register pmic interrupt */ > + accdet->accdet_irq = platform_get_irq(pdev, 0); > + if (accdet->accdet_irq < 0) { > + dev_err(&pdev->dev, > + "Error: Get accdet irq failed (%d)\n", > + accdet->accdet_irq); > + return accdet->accdet_irq; > + } > + ret = devm_request_threaded_irq(&pdev->dev, accdet->accdet_irq, > + NULL, mtk_accdet_irq_handler_thread, > + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, > + "ACCDET_IRQ", accdet); > + if (ret) { > + dev_err(&pdev->dev, > + "Error: Get thread irq request failed (%d) (%d)\n", > + accdet->accdet_irq, ret); > + return ret; > + } > + > + if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT0)) { > + accdet->accdet_eint0 = platform_get_irq(pdev, 1); > + if (accdet->accdet_eint0 < 0) { > + dev_err(&pdev->dev, > + "Error: Get eint0 irq failed (%d)\n", > + accdet->accdet_eint0); > + return accdet->accdet_eint0; > + } > + ret = devm_request_threaded_irq(&pdev->dev, > + accdet->accdet_eint0, > + NULL, mtk_accdet_irq_handler_thread, > + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, > + "ACCDET_EINT0", accdet); > + if (ret) { > + dev_err(&pdev->dev, > + "Error: Get eint0 irq request failed (%d)\n", > + ret); > + return ret; > + } > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_EINT1)) { > + accdet->accdet_eint1 = platform_get_irq(pdev, 2); > + if (accdet->accdet_eint1 < 0) { > + dev_err(&pdev->dev, > + "Error: Get eint1 irq failed (%d)\n", > + accdet->accdet_eint1); > + return accdet->accdet_eint1; > + } > + ret = devm_request_threaded_irq(&pdev->dev, > + accdet->accdet_eint1, > + NULL, > + mtk_accdet_irq_handler_thread, > + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, > + "ACCDET_EINT1", accdet); > + if (ret) { > + dev_err(&pdev->dev, > + "Error: Get eint1 irq request failed (%d)\n", > + ret); > + return ret; > + } > + } else if (HAS_CAP(accdet->data->caps, ACCDET_PMIC_BI_EINT)) { > + accdet->accdet_eint0 = platform_get_irq(pdev, 1); > + if (accdet->accdet_eint0 < 0) { > + dev_err(&pdev->dev, > + "Error: Get eint0 irq failed (%d)\n", > + accdet->accdet_eint0); > + return accdet->accdet_eint0; > + } > + ret = devm_request_threaded_irq(&pdev->dev, > + accdet->accdet_eint0, > + NULL, > + mtk_accdet_irq_handler_thread, > + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, > + "ACCDET_EINT0", accdet); > + if (ret) { > + dev_err(&pdev->dev, > + "Error: Get eint0 irq request failed (%d)\n", > + ret); > + return ret; > + } > + accdet->accdet_eint1 = platform_get_irq(pdev, 2); > + if (accdet->accdet_eint1 < 0) { > + dev_err(&pdev->dev, > + "Error: Get eint1 irq failed (%d)\n", > + accdet->accdet_eint1); > + return accdet->accdet_eint1; > + } > + ret = devm_request_threaded_irq(&pdev->dev, > + accdet->accdet_eint1, > + NULL, > + mtk_accdet_irq_handler_thread, > + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, > + "ACCDET_EINT1", accdet); > + if (ret) { > + dev_err(&pdev->dev, > + "Error: Get eint1 irq request failed (%d)\n", > + ret); > + return ret; > + } > + } > + > + /* setup timer */ > + timer_setup(&micbias_timer, dis_micbias_timerhandler, 0); > + micbias_timer.expires = jiffies + MICBIAS_DISABLE_TIMER; > + timer_setup(&accdet_init_timer, delay_init_timerhandler, 0); > + accdet_init_timer.expires = jiffies + ACCDET_INIT_WAIT_TIMER; > + > + /* Create workqueue */ > + accdet->delay_init_workqueue = > + create_singlethread_workqueue("delay_init"); > + INIT_WORK(&accdet->delay_init_work, delay_init_work_callback); > + if (!accdet->delay_init_workqueue) { > + dev_err(&pdev->dev, "Error: Create dinit workqueue failed\n"); > + ret = -1; > + goto err_delay_init_wq; > + } > + accdet->accdet_workqueue = create_singlethread_workqueue("accdet"); > + INIT_WORK(&accdet->accdet_work, accdet_work_callback); > + if (!accdet->accdet_workqueue) { > + dev_err(&pdev->dev, "Error: Create accdet workqueue failed\n"); > + ret = -1; > + goto err_accdet_wq; > + } > + > + accdet->dis_micbias_workqueue = > + create_singlethread_workqueue("dismicQueue"); > + INIT_WORK(&accdet->dis_micbias_work, dis_micbias_work_callback); > + if (!accdet->dis_micbias_workqueue) { > + dev_err(&pdev->dev, "Error: Create dismic workqueue failed\n"); > + ret = -1; > + goto err_dis_micbias_wq; > + } > + accdet->eint_workqueue = create_singlethread_workqueue("accdet_eint"); > + INIT_WORK(&accdet->eint_work, eint_work_callback); > + if (!accdet->eint_workqueue) { > + dev_err(&pdev->dev, "Error: Create eint workqueue failed\n"); > + ret = -1; > + goto err_eint_wq; > + } > + if (HAS_CAP(accdet->data->caps, ACCDET_AP_GPIO_EINT)) { > + accdet->accdet_eint_type = IRQ_TYPE_LEVEL_LOW; > + ret = ext_eint_setup(pdev); > + if (ret) > + destroy_workqueue(accdet->eint_workqueue); > + } > + > + atomic_set(&accdet->init_once, 1); > + mod_timer(&accdet_init_timer, (jiffies + ACCDET_INIT_WAIT_TIMER)); > + > + return 0; > + > +err_eint_wq: > + destroy_workqueue(accdet->dis_micbias_workqueue); > +err_dis_micbias_wq: > + destroy_workqueue(accdet->accdet_workqueue); > +err_accdet_wq: > + destroy_workqueue(accdet->delay_init_workqueue); > +err_delay_init_wq: > + pr_notice("%s error. now exit.!\n", __func__); > + return ret; > +} > + > +static int mt6359_accdet_remove(struct platform_device *pdev) > +{ > + destroy_workqueue(accdet->eint_workqueue); > + destroy_workqueue(accdet->dis_micbias_workqueue); > + destroy_workqueue(accdet->accdet_workqueue); > + destroy_workqueue(accdet->delay_init_workqueue); > + devm_kfree(&pdev->dev, accdet); > + return 0; > +} > + > +static struct platform_driver mt6359_accdet_driver = { > + .probe = mt6359_accdet_probe, > + .remove = mt6359_accdet_remove, > + .driver = { > + .name = "pmic-codec-accdet", > + .of_match_table = mt6359_accdet_of_match, > + }, > +}; > + > +static int __init mt6359_accdet_soc_init(void) > +{ > + int ret = 0; > + > + ret = platform_driver_register(&mt6359_accdet_driver); > + if (ret) > + return -ENODEV; > + return 0; > +} > + > +static void __exit mt6359_accdet_soc_exit(void) > +{ > + platform_driver_unregister(&mt6359_accdet_driver); > +} > +module_init(mt6359_accdet_soc_init); > +module_exit(mt6359_accdet_soc_exit); > + > +/* Module information */ > +MODULE_DESCRIPTION("MT6359 ALSA SoC accdet driver"); > +MODULE_AUTHOR("Argus Lin <argus.lin(a)mediatek.com>"); > +MODULE_LICENSE("GPL v2"); > diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h > new file mode 100644 > index 0000000..d081d69 > --- /dev/null > +++ b/sound/soc/codecs/mt6359-accdet.h > @@ -0,0 +1,136 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2021 MediaTek Inc. > + * Author: Argus Lin <argus.lin(a)mediatek.com> > + */ > + > +#ifndef _ACCDET_H_ > +#define _ACCDET_H_ > + > +#include <linux/ctype.h> > +#include <linux/string.h> > + > +#define ACCDET_DEVNAME "accdet" > +/* SW ENV define */ > +#define NO_KEY (0x0) > +#define UP_KEY (0x01) > +#define MD_KEY (0x02) > +#define DW_KEY (0x04) > +#define AS_KEY (0x08) > + > +#define HEADSET_MODE_1 (1) > +#define HEADSET_MODE_2 (2) > +#define HEADSET_MODE_6 (6) > + > +/* IOCTL */ > +#define ACCDET_IOC_MAGIC 'A' > +#define ACCDET_INIT _IO(ACCDET_IOC_MAGIC, 0) > +#define SET_CALL_STATE _IO(ACCDET_IOC_MAGIC, 1) > +#define GET_BUTTON_STATUS _IO(ACCDET_IOC_MAGIC, 2) > + > +/* 400us, Accdet irq clear timeout */ > +#define ACCDET_TIME_OUT 0x61A80 > + > +/* cable type recognized by accdet, and report to WiredAccessoryManager */ > +enum accdet_report_state { > + NO_DEVICE = 0, > + HEADSET_MIC = 1, > + HEADSET_NO_MIC = 2, > + HEADSET_FIVE_POLE = 3, > + LINE_OUT_DEVICE = 4, > +}; > + > +/* accdet status got from accdet FSM */ > +enum accdet_status { > + PLUG_OUT = 0, > + MIC_BIAS = 1, > + HOOK_SWITCH = 2, > + BI_MIC_BIAS = 3, > + LINE_OUT = 4, > + STAND_BY = 5 > +}; > + > +enum accdet_eint_ID { > + NO_PMIC_EINT = 0, > + PMIC_EINT0 = 1, > + PMIC_EINT1 = 2, > + PMIC_BIEINT = 3, > +}; > + > +/* EINT state when moisture enable */ > +enum eint_moisture_status { > + M_PLUG_IN = 0, > + M_WATER_IN = 1, > + M_HP_PLUG_IN = 2, > + M_PLUG_OUT = 3, > + M_NO_ACT = 4, > + M_UNKNOWN = 5, > +}; > + > +struct three_key_threshold { > + unsigned int mid; > + unsigned int up; > + unsigned int down; > +}; > + > +struct four_key_threshold { > + unsigned int mid; > + unsigned int voice; > + unsigned int up; > + unsigned int down; > +}; > + > +struct pwm_deb_settings { > + unsigned int pwm_width; > + unsigned int pwm_thresh; > + unsigned int fall_delay; > + unsigned int rise_delay; > + unsigned int debounce0; > + unsigned int debounce1; > + unsigned int debounce3; > + unsigned int debounce4; > + unsigned int eint_pwm_width; > + unsigned int eint_pwm_thresh; > + unsigned int eint_debounce0; > + unsigned int eint_debounce1; > + unsigned int eint_debounce2; > + unsigned int eint_debounce3; > + unsigned int eint_inverter_debounce; > + > +}; > + > +struct head_dts_data { > + unsigned int mic_vol; > + unsigned int mic_mode; > + unsigned int plugout_deb; > + unsigned int eint_pol; > + struct pwm_deb_settings pwm_deb; > + struct three_key_threshold three_key; > + struct four_key_threshold four_key; > + unsigned int moisture_detect_enable; > + unsigned int eint_detect_mode; > + unsigned int eint_use_ext_res; > + unsigned int moisture_detect_mode; > + unsigned int moisture_comp_vth; > + unsigned int moisture_comp_vref2; > + unsigned int moisture_use_ext_res; > +}; > + > +enum { > + accdet_state000 = 0, > + accdet_state001, > + accdet_state010, > + accdet_state011, > + accdet_auxadc, > + eint_state000, > + eint_state001, > + eint_state010, > + eint_state011, > + eint_inverter_state000, > +}; > + > +/* just be called by audio module for DC trim */ > +void mt6359_accdet_late_init(unsigned long data); > +int mt6359_accdet_init(struct snd_soc_component *component, struct snd_soc_card *card); > +int mt6359_accdet_set_drvdata(struct snd_soc_card *card); > +#endif > diff --git a/sound/soc/codecs/mt6359.h b/sound/soc/codecs/mt6359.h > index 35f806b..9f9a94a 100644 > --- a/sound/soc/codecs/mt6359.h > +++ b/sound/soc/codecs/mt6359.h > @@ -8,128 +8,1779 @@ > #define _MT6359_H_ > > /*************Register Bit Define*************/ > -#define PMIC_ACCDET_IRQ_SHIFT 0 > -#define PMIC_ACCDET_EINT0_IRQ_SHIFT 2 > -#define PMIC_ACCDET_EINT1_IRQ_SHIFT 3 > -#define PMIC_ACCDET_IRQ_CLR_SHIFT 8 > -#define PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT 10 > -#define PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT 11 > -#define PMIC_RG_INT_STATUS_ACCDET_SHIFT 5 > -#define PMIC_RG_INT_STATUS_ACCDET_EINT0_SHIFT 6 > -#define PMIC_RG_INT_STATUS_ACCDET_EINT1_SHIFT 7 > -#define PMIC_RG_EINT0CONFIGACCDET_SHIFT 11 > -#define PMIC_RG_EINT1CONFIGACCDET_SHIFT 0 > -#define PMIC_ACCDET_EINT0_INVERTER_SW_EN_SHIFT 6 > -#define PMIC_ACCDET_EINT1_INVERTER_SW_EN_SHIFT 8 > -#define PMIC_RG_MTEST_EN_SHIFT 8 > -#define PMIC_RG_MTEST_SEL_SHIFT 9 > -#define PMIC_ACCDET_EINT0_M_SW_EN_SHIFT 10 > -#define PMIC_ACCDET_EINT1_M_SW_EN_SHIFT 11 > -#define PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT 5 > -#define PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT 10 > -#define PMIC_ACCDET_DA_STABLE_SHIFT 0 > -#define PMIC_ACCDET_EINT0_EN_STABLE_SHIFT 1 > -#define PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT 2 > -#define PMIC_ACCDET_EINT1_EN_STABLE_SHIFT 6 > -#define PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT 7 > -#define PMIC_ACCDET_EINT_CTURBO_SEL_SHIFT 7 > -#define PMIC_ACCDET_EINT0_CTURBO_SW_SHIFT 7 > -#define PMIC_RG_EINTCOMPVTH_SHIFT 4 > -#define PMIC_RG_EINT0HIRENB_SHIFT 12 > -#define PMIC_RG_EINT0NOHYS_SHIFT 10 > -#define PMIC_ACCDET_SW_EN_SHIFT 0 > -#define PMIC_ACCDET_EINT0_MEM_IN_SHIFT 6 > -#define PMIC_ACCDET_MEM_IN_SHIFT 6 > -#define PMIC_ACCDET_EINT_DEBOUNCE0_SHIFT 0 > -#define PMIC_ACCDET_EINT_DEBOUNCE1_SHIFT 4 > -#define PMIC_ACCDET_EINT_DEBOUNCE2_SHIFT 8 > -#define PMIC_ACCDET_EINT_DEBOUNCE3_SHIFT 12 > -#define PMIC_RG_ACCDET2AUXSWEN_SHIFT 14 > -#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 9 > -#define PMIC_AUDACCDETAUXADCSWCTRL_SW_SHIFT 10 > -#define PMIC_RG_EINT0CTURBO_SHIFT 5 > -#define PMIC_RG_EINT1CTURBO_SHIFT 13 > -#define PMIC_ACCDET_EINT_M_PLUG_IN_NUM_SHIFT 12 > -#define PMIC_ACCDET_EINT_M_DETECT_EN_SHIFT 12 > -#define PMIC_ACCDET_EINT0_SW_EN_SHIFT 2 > -#define PMIC_ACCDET_EINT1_SW_EN_SHIFT 4 > -#define PMIC_ACCDET_EINT_CMPMOUT_SEL_SHIFT 12 > -#define PMIC_ACCDET_EINT_CMPMEN_SEL_SHIFT 6 > -#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_SHIFT 0 > -#define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_SHIFT 4 > -#define PMIC_RG_EINT0EN_SHIFT 2 > -#define PMIC_RG_EINT1EN_SHIFT 10 > -#define PMIC_RG_NCP_PDDIS_EN_SHIFT 0 > -#define PMIC_RG_ACCDETSPARE_SHIFT 0 > -#define PMIC_RG_ACCDET_RST_SHIFT 1 > -#define PMIC_RG_AUDMICBIAS1HVEN_SHIFT 12 > -#define PMIC_RG_AUDMICBIAS1VREF_SHIFT 4 > -#define PMIC_RG_ANALOGFDEN_SHIFT 12 > -#define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT 8 > -#define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT 2 > -#define PMIC_ACCDET_SEQ_INIT_SHIFT 1 > -#define PMIC_RG_EINTCOMPVTH_MASK 0xf > -#define PMIC_ACCDET_EINT0_MEM_IN_MASK 0x3 > -#define PMIC_ACCDET_EINT_DEBOUNCE0_MASK 0xf > -#define PMIC_ACCDET_EINT_DEBOUNCE1_MASK 0xf > -#define PMIC_ACCDET_EINT_DEBOUNCE2_MASK 0xf > -#define PMIC_ACCDET_EINT_DEBOUNCE3_MASK 0xf > -#define PMIC_ACCDET_EINT0_IRQ_SHIFT 2 > -#define PMIC_ACCDET_EINT1_IRQ_SHIFT 3 > - > -/* AUDENC_ANA_CON16: */ > -#define RG_AUD_MICBIAS1_LOWP_EN BIT(PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT) > - > +#define MT6359_TOP0_ID 0x0 > +#define MT6359_SMT_CON1 0x32 > +#define MT6359_DRV_CON2 0x3c > +#define MT6359_DRV_CON3 0x3e > +#define MT6359_DRV_CON4 0x40 > +#define MT6359_TOP_CKPDN_CON0 0x10c > +#define MT6359_TOP_CKPDN_CON0_SET 0x10e > +#define MT6359_TOP_CKPDN_CON0_CLR 0x110 > +#define MT6359_AUXADC_RQST0 0x1108 > +#define MT6359_AUXADC_CON10 0x11a0 > +#define MT6359_AUXADC_ACCDET 0x11ba > +#define MT6359_LDO_VUSB_OP_EN 0x1d0c > +#define MT6359_LDO_VUSB_OP_EN_SET 0x1d0e > +#define MT6359_LDO_VUSB_OP_EN_CLR 0x1d10 > +#define MT6359_AUD_TOP_CKPDN_CON0 0x230c > +#define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e > +#define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x2310 > +#define MT6359_AUD_TOP_RST_CON0 0x2320 > +#define MT6359_AUD_TOP_RST_CON0_SET 0x2322 > +#define MT6359_AUD_TOP_RST_CON0_CLR 0x2324 > +#define MT6359_AUD_TOP_INT_CON0 0x2328 > +#define MT6359_AUD_TOP_INT_CON0_SET 0x232a > +#define MT6359_AUD_TOP_INT_CON0_CLR 0x232c > +#define MT6359_AUD_TOP_INT_MASK_CON0 0x232e > +#define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x2330 > +#define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x2332 > +#define MT6359_AUD_TOP_INT_STATUS0 0x2334 > +#define MT6359_AFE_NCP_CFG2 0x24e2 > +#define MT6359_AUDENC_DSN_ID 0x2500 > +#define MT6359_AUDENC_DSN_REV0 0x2502 > +#define MT6359_AUDENC_DSN_DBI 0x2504 > +#define MT6359_AUDENC_DSN_FPI 0x2506 > +#define MT6359_AUDENC_ANA_CON0 0x2508 > +#define MT6359_AUDENC_ANA_CON1 0x250a > +#define MT6359_AUDENC_ANA_CON2 0x250c > +#define MT6359_AUDENC_ANA_CON3 0x250e > +#define MT6359_AUDENC_ANA_CON4 0x2510 > +#define MT6359_AUDENC_ANA_CON5 0x2512 > +#define MT6359_AUDENC_ANA_CON6 0x2514 > +#define MT6359_AUDENC_ANA_CON7 0x2516 > +#define MT6359_AUDENC_ANA_CON8 0x2518 > +#define MT6359_AUDENC_ANA_CON9 0x251a > +#define MT6359_AUDENC_ANA_CON10 0x251c > +#define MT6359_AUDENC_ANA_CON11 0x251e > +#define MT6359_AUDENC_ANA_CON12 0x2520 > +#define MT6359_AUDENC_ANA_CON13 0x2522 > +#define MT6359_AUDENC_ANA_CON14 0x2524 > +#define MT6359_AUDENC_ANA_CON15 0x2526 > +#define MT6359_AUDENC_ANA_CON16 0x2528 > +#define MT6359_AUDENC_ANA_CON17 0x252a > +#define MT6359_AUDENC_ANA_CON18 0x252c > +#define MT6359_AUDENC_ANA_CON19 0x252e > +#define MT6359_AUDENC_ANA_CON20 0x2530 > +#define MT6359_AUDENC_ANA_CON21 0x2532 > +#define MT6359_AUDENC_ANA_CON22 0x2534 > +#define MT6359_AUDENC_ANA_CON23 0x2536 > +#define MT6359_AUDDEC_DSN_ID 0x2580 > +#define MT6359_AUDDEC_DSN_REV0 0x2582 > +#define MT6359_AUDDEC_DSN_DBI 0x2584 > +#define MT6359_AUDDEC_DSN_FPI 0x2586 > +#define MT6359_AUDDEC_ANA_CON0 0x2588 > +#define MT6359_AUDDEC_ANA_CON1 0x258a > +#define MT6359_AUDDEC_ANA_CON2 0x258c > +#define MT6359_AUDDEC_ANA_CON3 0x258e > +#define MT6359_AUDDEC_ANA_CON4 0x2590 > +#define MT6359_AUDDEC_ANA_CON5 0x2592 > +#define MT6359_AUDDEC_ANA_CON6 0x2594 > +#define MT6359_AUDDEC_ANA_CON7 0x2596 > +#define MT6359_AUDDEC_ANA_CON8 0x2598 > +#define MT6359_AUDDEC_ANA_CON9 0x259a > +#define MT6359_AUDDEC_ANA_CON10 0x259c > +#define MT6359_AUDDEC_ANA_CON11 0x259e > +#define MT6359_AUDDEC_ANA_CON12 0x25a0 > +#define MT6359_AUDDEC_ANA_CON13 0x25a2 > +#define MT6359_AUDDEC_ANA_CON14 0x25a4 > +#define MT6359_ACCDET_DSN_DIG_ID 0x2680 > +#define MT6359_ACCDET_DSN_DIG_REV0 0x2682 > +#define MT6359_ACCDET_DSN_DBI 0x2684 > +#define MT6359_ACCDET_DSN_FPI 0x2686 > +#define MT6359_ACCDET_CON0 0x2688 > +#define MT6359_ACCDET_CON1 0x268a > +#define MT6359_ACCDET_CON2 0x268c > +#define MT6359_ACCDET_CON3 0x268e > +#define MT6359_ACCDET_CON4 0x2690 > +#define MT6359_ACCDET_CON5 0x2692 > +#define MT6359_ACCDET_CON6 0x2694 > +#define MT6359_ACCDET_CON7 0x2696 > +#define MT6359_ACCDET_CON8 0x2698 > +#define MT6359_ACCDET_CON9 0x269a > +#define MT6359_ACCDET_CON10 0x269c > +#define MT6359_ACCDET_CON11 0x269e > +#define MT6359_ACCDET_CON12 0x26a0 > +#define MT6359_ACCDET_CON13 0x26a2 > +#define MT6359_ACCDET_CON14 0x26a4 > +#define MT6359_ACCDET_CON15 0x26a6 > +#define MT6359_ACCDET_CON16 0x26a8 > +#define MT6359_ACCDET_CON17 0x26aa > +#define MT6359_ACCDET_CON18 0x26ac > +#define MT6359_ACCDET_CON19 0x26ae > +#define MT6359_ACCDET_CON20 0x26b0 > +#define MT6359_ACCDET_CON21 0x26b2 > +#define MT6359_ACCDET_CON22 0x26b4 > +#define MT6359_ACCDET_CON23 0x26b6 > +#define MT6359_ACCDET_CON24 0x26b8 > +#define MT6359_ACCDET_CON25 0x26ba > +#define MT6359_ACCDET_CON26 0x26bc > +#define MT6359_ACCDET_CON27 0x26be > +#define MT6359_ACCDET_CON28 0x26c0 > +#define MT6359_ACCDET_CON29 0x26c2 > +#define MT6359_ACCDET_CON30 0x26c4 > +#define MT6359_ACCDET_CON31 0x26c6 > +#define MT6359_ACCDET_CON32 0x26c8 > +#define MT6359_ACCDET_CON33 0x26ca > +#define MT6359_ACCDET_CON34 0x26cc > +#define MT6359_ACCDET_CON35 0x26ce > +#define MT6359_ACCDET_CON36 0x26d0 > +#define MT6359_ACCDET_CON37 0x26d2 > +#define MT6359_ACCDET_CON38 0x26d4 > +#define MT6359_ACCDET_CON39 0x26d6 > +#define MT6359_ACCDET_CON40 0x26d8 > + > +#define TOP0_ANA_ID_ADDR \ > + MT6359_TOP0_ID > +#define TOP0_ANA_ID_SFT 0 > +#define TOP0_ANA_ID_MASK 0xFF > +#define TOP0_ANA_ID_MASK_SFT (0xFF << 0) > +#define AUXADC_RQST_CH0_ADDR \ > + MT6359_AUXADC_RQST0 > +#define AUXADC_RQST_CH0_SFT 0 > +#define AUXADC_RQST_CH0_MASK 0x1 > +#define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0) > +#define AUXADC_ACCDET_ANASWCTRL_EN_ADDR \ > + MT6359_AUXADC_CON15 > +#define AUXADC_ACCDET_ANASWCTRL_EN_SFT 6 > +#define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1 > +#define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6) > + > +#define AUXADC_ACCDET_AUTO_SPL_ADDR \ > + MT6359_AUXADC_ACCDET > +#define AUXADC_ACCDET_AUTO_SPL_SFT 0 > +#define AUXADC_ACCDET_AUTO_SPL_MASK 0x1 > +#define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0) > +#define AUXADC_ACCDET_AUTO_RQST_CLR_ADDR \ > + MT6359_AUXADC_ACCDET > +#define AUXADC_ACCDET_AUTO_RQST_CLR_SFT 1 > +#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1 > +#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1) > +#define AUXADC_ACCDET_DIG1_RSV0_ADDR \ > + MT6359_AUXADC_ACCDET > +#define AUXADC_ACCDET_DIG1_RSV0_SFT 2 > +#define AUXADC_ACCDET_DIG1_RSV0_MASK 0x3F > +#define AUXADC_ACCDET_DIG1_RSV0_MASK_SFT (0x3F << 2) > +#define AUXADC_ACCDET_DIG0_RSV0_ADDR \ > + MT6359_AUXADC_ACCDET > +#define AUXADC_ACCDET_DIG0_RSV0_SFT 8 > +#define AUXADC_ACCDET_DIG0_RSV0_MASK 0xFF > +#define AUXADC_ACCDET_DIG0_RSV0_MASK_SFT (0xFF << 8) > + > +#define RG_ACCDET_CK_PDN_ADDR \ > + MT6359_AUD_TOP_CKPDN_CON0 > +#define RG_ACCDET_CK_PDN_SFT 0 > +#define RG_ACCDET_CK_PDN_MASK 0x1 > +#define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0) > + > +#define RG_ACCDET_RST_ADDR \ > + MT6359_AUD_TOP_RST_CON0 > +#define RG_ACCDET_RST_SFT 1 > +#define RG_ACCDET_RST_MASK 0x1 > +#define RG_ACCDET_RST_MASK_SFT (0x1 << 1) > +#define BANK_ACCDET_SWRST_ADDR \ > + MT6359_AUD_TOP_RST_BANK_CON0 > +#define BANK_ACCDET_SWRST_SFT 0 > +#define BANK_ACCDET_SWRST_MASK 0x1 > +#define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0) > + > +#define RG_INT_EN_ACCDET_ADDR \ > + MT6359_AUD_TOP_INT_CON0 > +#define RG_INT_EN_ACCDET_SFT 5 > +#define RG_INT_EN_ACCDET_MASK 0x1 > +#define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5) > +#define RG_INT_EN_ACCDET_EINT0_ADDR \ > + MT6359_AUD_TOP_INT_CON0 > +#define RG_INT_EN_ACCDET_EINT0_SFT 6 > +#define RG_INT_EN_ACCDET_EINT0_MASK 0x1 > +#define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6) > +#define RG_INT_EN_ACCDET_EINT1_ADDR \ > + MT6359_AUD_TOP_INT_CON0 > +#define RG_INT_EN_ACCDET_EINT1_SFT 7 > +#define RG_INT_EN_ACCDET_EINT1_MASK 0x1 > +#define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7) > + > +#define RG_INT_MASK_ACCDET_ADDR \ > + MT6359_AUD_TOP_INT_MASK_CON0 > +#define RG_INT_MASK_ACCDET_SFT 5 > +#define RG_INT_MASK_ACCDET_MASK 0x1 > +#define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5) > +#define RG_INT_MASK_ACCDET_EINT0_ADDR \ > + MT6359_AUD_TOP_INT_MASK_CON0 > +#define RG_INT_MASK_ACCDET_EINT0_SFT 6 > +#define RG_INT_MASK_ACCDET_EINT0_MASK 0x1 > +#define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6) > +#define RG_INT_MASK_ACCDET_EINT1_ADDR \ > + MT6359_AUD_TOP_INT_MASK_CON0 > +#define RG_INT_MASK_ACCDET_EINT1_SFT 7 > +#define RG_INT_MASK_ACCDET_EINT1_MASK 0x1 > +#define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7) > + > +#define RG_INT_STATUS_ACCDET_ADDR \ > + MT6359_AUD_TOP_INT_STATUS0 > +#define RG_INT_STATUS_ACCDET_SFT 5 > +#define RG_INT_STATUS_ACCDET_MASK 0x1 > +#define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5) > +#define RG_INT_STATUS_ACCDET_EINT0_ADDR \ > + MT6359_AUD_TOP_INT_STATUS0 > +#define RG_INT_STATUS_ACCDET_EINT0_SFT 6 > +#define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1 > +#define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6) > +#define RG_INT_STATUS_ACCDET_EINT1_ADDR \ > + MT6359_AUD_TOP_INT_STATUS0 > +#define RG_INT_STATUS_ACCDET_EINT1_SFT 7 > +#define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1 > +#define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7) > + > +#define RG_INT_RAW_STATUS_ACCDET_ADDR \ > + MT6359_AUD_TOP_INT_RAW_STATUS0 > +#define RG_INT_RAW_STATUS_ACCDET_SFT 5 > +#define RG_INT_RAW_STATUS_ACCDET_MASK 0x1 > +#define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5) > +#define RG_INT_RAW_STATUS_ACCDET_EINT0_ADDR \ > + MT6359_AUD_TOP_INT_RAW_STATUS0 > +#define RG_INT_RAW_STATUS_ACCDET_EINT0_SFT 6 > +#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1 > +#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6) > +#define RG_INT_RAW_STATUS_ACCDET_EINT1_ADDR \ > + MT6359_AUD_TOP_INT_RAW_STATUS0 > +#define RG_INT_RAW_STATUS_ACCDET_EINT1_SFT 7 > +#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1 > +#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7) > + > +#define RG_AUDACCDETMICBIAS0PULLLOW_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0 > +#define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1 > +#define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0) > +#define RG_AUDACCDETMICBIAS1PULLLOW_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1 > +#define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1 > +#define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1) > +#define RG_AUDACCDETMICBIAS2PULLLOW_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETMICBIAS2PULLLOW_SFT 2 > +#define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1 > +#define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2) > +#define RG_AUDACCDETVIN1PULLLOW_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETVIN1PULLLOW_SFT 3 > +#define RG_AUDACCDETVIN1PULLLOW_MASK 0x1 > +#define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3) > +#define RG_AUDACCDETVTHACAL_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETVTHACAL_SFT 4 > +#define RG_AUDACCDETVTHACAL_MASK 0x1 > +#define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4) > +#define RG_AUDACCDETVTHBCAL_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETVTHBCAL_SFT 5 > +#define RG_AUDACCDETVTHBCAL_MASK 0x1 > +#define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5) > +#define RG_AUDACCDETTVDET_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETTVDET_SFT 6 > +#define RG_AUDACCDETTVDET_MASK 0x1 > +#define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6) > +#define RG_ACCDETSEL_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_ACCDETSEL_SFT 7 > +#define RG_ACCDETSEL_MASK 0x1 > +#define RG_ACCDETSEL_MASK_SFT (0x1 << 7) > + > +#define RG_AUDPWDBMICBIAS1_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDPWDBMICBIAS1_SFT 0 > +#define RG_AUDPWDBMICBIAS1_MASK 0x1 > +#define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0) > +#define RG_AUDMICBIAS1BYPASSEN_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDMICBIAS1BYPASSEN_SFT 1 > +#define RG_AUDMICBIAS1BYPASSEN_MASK 0x1 > +#define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1) > +#define RG_AUDMICBIAS1LOWPEN_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDMICBIAS1LOWPEN_SFT 2 > +#define RG_AUDMICBIAS1LOWPEN_MASK 0x1 > +#define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2) > +#define RG_AUDMICBIAS1VREF_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDMICBIAS1VREF_SFT 4 > +#define RG_AUDMICBIAS1VREF_MASK 0x7 > +#define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4) > +#define RG_AUDMICBIAS1DCSW1PEN_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDMICBIAS1DCSW1PEN_SFT 8 > +#define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1 > +#define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8) > +#define RG_AUDMICBIAS1DCSW1NEN_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDMICBIAS1DCSW1NEN_SFT 9 > +#define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1 > +#define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9) > +#define RG_BANDGAPGEN_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_BANDGAPGEN_SFT 10 > +#define RG_BANDGAPGEN_MASK 0x1 > +#define RG_BANDGAPGEN_MASK_SFT (0x1 << 10) > +#define RG_AUDMICBIAS1HVEN_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDMICBIAS1HVEN_SFT 12 > +#define RG_AUDMICBIAS1HVEN_MASK 0x1 > +#define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12) > +#define RG_AUDMICBIAS1HVVREF_ADDR \ > + MT6359_AUDENC_ANA_CON16 > +#define RG_AUDMICBIAS1HVVREF_SFT 13 > +#define RG_AUDMICBIAS1HVVREF_MASK 0x1 > +#define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13) > + > +#define RG_EINT0NOHYS_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_EINT0NOHYS_SFT 10 > +#define RG_EINT0NOHYS_MASK 0x1 > +#define RG_EINT0NOHYS_MASK_SFT (0x1 << 10) > +#define RG_EINT0CONFIGACCDET_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_EINT0CONFIGACCDET_SFT 11 > +#define RG_EINT0CONFIGACCDET_MASK 0x1 > +#define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11) > +#define RG_EINT0HIRENB_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_EINT0HIRENB_SFT 12 > +#define RG_EINT0HIRENB_MASK 0x1 > +#define RG_EINT0HIRENB_MASK_SFT (0x1 << 12) > +#define RG_ACCDET2AUXRESBYPASS_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_ACCDET2AUXRESBYPASS_SFT 13 > +#define RG_ACCDET2AUXRESBYPASS_MASK 0x1 > +#define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13) > +#define RG_ACCDET2AUXSWEN_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_ACCDET2AUXSWEN_SFT 14 > +#define RG_ACCDET2AUXSWEN_MASK 0x1 > +#define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14) > +#define RG_AUDACCDETMICBIAS3PULLLOW_ADDR \ > + MT6359_AUDENC_ANA_CON18 > +#define RG_AUDACCDETMICBIAS3PULLLOW_SFT 15 > +#define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1 > +#define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15) > +#define RG_EINT1CONFIGACCDET_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_EINT1CONFIGACCDET_SFT 0 > +#define RG_EINT1CONFIGACCDET_MASK 0x1 > +#define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0) > +#define RG_EINT1HIRENB_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_EINT1HIRENB_SFT 1 > +#define RG_EINT1HIRENB_MASK 0x1 > +#define RG_EINT1HIRENB_MASK_SFT (0x1 << 1) > +#define RG_EINT1NOHYS_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_EINT1NOHYS_SFT 2 > +#define RG_EINT1NOHYS_MASK 0x1 > +#define RG_EINT1NOHYS_MASK_SFT (0x1 << 2) > +#define RG_EINTCOMPVTH_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_MTEST_EN_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_MTEST_EN_SFT 8 > +#define RG_MTEST_EN_MASK 0x1 > +#define RG_MTEST_EN_MASK_SFT (0x1 << 8) > +#define RG_MTEST_SEL_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_MTEST_SEL_SFT 9 > +#define RG_MTEST_SEL_MASK 0x1 > +#define RG_MTEST_SEL_MASK_SFT (0x1 << 9) > +#define RG_MTEST_CURRENT_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_MTEST_CURRENT_SFT 10 > +#define RG_MTEST_CURRENT_MASK 0x1 > +#define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10) > +#define RG_ANALOGFDEN_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_ANALOGFDEN_SFT 12 > +#define RG_ANALOGFDEN_MASK 0x1 > +#define RG_ANALOGFDEN_MASK_SFT (0x1 << 12) > +#define RG_FDVIN1PPULLLOW_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_FDVIN1PPULLLOW_SFT 13 > +#define RG_FDVIN1PPULLLOW_MASK 0x1 > +#define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13) > +#define RG_FDEINT0TYPE_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_FDEINT0TYPE_SFT 14 > +#define RG_FDEINT0TYPE_MASK 0x1 > +#define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14) > +#define RG_FDEINT1TYPE_ADDR \ > + MT6359_AUDENC_ANA_CON19 > +#define RG_FDEINT1TYPE_SFT 15 > +#define RG_FDEINT1TYPE_MASK 0x1 > +#define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15) > +#define RG_EINT0CMPEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT0CMPEN_SFT 0 > +#define RG_EINT0CMPEN_MASK 0x1 > +#define RG_EINT0CMPEN_MASK_SFT (0x1 << 0) > +#define RG_EINT0CMPMEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT0CMPMEN_SFT 1 > +#define RG_EINT0CMPMEN_MASK 0x1 > +#define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1) > +#define RG_EINT0EN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT0EN_SFT 2 > +#define RG_EINT0EN_MASK 0x1 > +#define RG_EINT0EN_MASK_SFT (0x1 << 2) > +#define RG_EINT0CEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT0CEN_SFT 3 > +#define RG_EINT0CEN_MASK 0x1 > +#define RG_EINT0CEN_MASK_SFT (0x1 << 3) > +#define RG_EINT0INVEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT0INVEN_SFT 4 > +#define RG_EINT0INVEN_MASK 0x1 > +#define RG_EINT0INVEN_MASK_SFT (0x1 << 4) > +#define RG_EINT0CTURBO_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT0CTURBO_SFT 5 > +#define RG_EINT0CTURBO_MASK 0x7 > +#define RG_EINT0CTURBO_MASK_SFT (0x7 << 5) > +#define RG_EINT1CMPEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT1CMPEN_SFT 8 > +#define RG_EINT1CMPEN_MASK 0x1 > +#define RG_EINT1CMPEN_MASK_SFT (0x1 << 8) > +#define RG_EINT1CMPMEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT1CMPMEN_SFT 9 > +#define RG_EINT1CMPMEN_MASK 0x1 > +#define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9) > +#define RG_EINT1EN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT1EN_SFT 10 > +#define RG_EINT1EN_MASK 0x1 > +#define RG_EINT1EN_MASK_SFT (0x1 << 10) > +#define RG_EINT1CEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT1CEN_SFT 11 > +#define RG_EINT1CEN_MASK 0x1 > +#define RG_EINT1CEN_MASK_SFT (0x1 << 11) > +#define RG_EINT1INVEN_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT1INVEN_SFT 12 > +#define RG_EINT1INVEN_MASK 0x1 > +#define RG_EINT1INVEN_MASK_SFT (0x1 << 12) > +#define RG_EINT1CTURBO_ADDR \ > + MT6359_AUDENC_ANA_CON20 > +#define RG_EINT1CTURBO_SFT 13 > +#define RG_EINT1CTURBO_MASK 0x7 > +#define RG_EINT1CTURBO_MASK_SFT (0x7 << 13) > +#define RG_ACCDETSPARE_ADDR \ > + MT6359_AUDENC_ANA_CON21 > + > +#define ACCDET_ANA_ID_ADDR \ > + MT6359_ACCDET_DSN_DIG_ID > +#define ACCDET_ANA_ID_SFT 0 > +#define ACCDET_ANA_ID_MASK 0xFF > +#define ACCDET_ANA_ID_MASK_SFT (0xFF << 0) > +#define ACCDET_DIG_ID_ADDR \ > + MT6359_ACCDET_DSN_DIG_ID > +#define ACCDET_DIG_ID_SFT 8 > +#define ACCDET_DIG_ID_MASK 0xFF > +#define ACCDET_DIG_ID_MASK_SFT (0xFF << 8) > +#define ACCDET_ANA_MINOR_REV_ADDR \ > + MT6359_ACCDET_DSN_DIG_REV0 > +#define ACCDET_ANA_MINOR_REV_SFT 0 > +#define ACCDET_ANA_MINOR_REV_MASK 0xF > +#define ACCDET_ANA_MINOR_REV_MASK_SFT (0xF << 0) > +#define ACCDET_ANA_MAJOR_REV_ADDR \ > + MT6359_ACCDET_DSN_DIG_REV0 > +#define ACCDET_ANA_MAJOR_REV_SFT 4 > +#define ACCDET_ANA_MAJOR_REV_MASK 0xF > +#define ACCDET_ANA_MAJOR_REV_MASK_SFT (0xF << 4) > +#define ACCDET_DIG_MINOR_REV_ADDR \ > + MT6359_ACCDET_DSN_DIG_REV0 > +#define ACCDET_DIG_MINOR_REV_SFT 8 > +#define ACCDET_DIG_MINOR_REV_MASK 0xF > +#define ACCDET_DIG_MINOR_REV_MASK_SFT (0xF << 8) > +#define ACCDET_DIG_MAJOR_REV_ADDR \ > + MT6359_ACCDET_DSN_DIG_REV0 > +#define ACCDET_DIG_MAJOR_REV_SFT 12 > +#define ACCDET_DIG_MAJOR_REV_MASK 0xF > +#define ACCDET_DIG_MAJOR_REV_MASK_SFT (0xF << 12) > +#define ACCDET_DSN_CBS_ADDR \ > + MT6359_ACCDET_DSN_DBI > +#define ACCDET_DSN_CBS_SFT 0 > +#define ACCDET_DSN_CBS_MASK 0x3 > +#define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0) > +#define ACCDET_DSN_BIX_ADDR \ > + MT6359_ACCDET_DSN_DBI > +#define ACCDET_DSN_BIX_SFT 2 > +#define ACCDET_DSN_BIX_MASK 0x3 > +#define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2) > +#define ACCDET_ESP_ADDR \ > + MT6359_ACCDET_DSN_DBI > +#define ACCDET_ESP_SFT 8 > +#define ACCDET_ESP_MASK 0xFF > +#define ACCDET_ESP_MASK_SFT (0xFF << 8) > +#define ACCDET_DSN_FPI_ADDR \ > + MT6359_ACCDET_DSN_FPI > +#define ACCDET_DSN_FPI_SFT 0 > +#define ACCDET_DSN_FPI_MASK 0xFF > +#define ACCDET_DSN_FPI_MASK_SFT (0xFF << 0) > +#define ACCDET_AUXADC_SEL_ADDR \ > + MT6359_ACCDET_CON0 > +#define ACCDET_AUXADC_SEL_SFT 0 > +#define ACCDET_AUXADC_SEL_MASK 0x1 > +#define ACCDET_AUXADC_SEL_MASK_SFT (0x1 << 0) > +#define ACCDET_AUXADC_SW_ADDR \ > + MT6359_ACCDET_CON0 > +#define ACCDET_AUXADC_SW_SFT 1 > +#define ACCDET_AUXADC_SW_MASK 0x1 > +#define ACCDET_AUXADC_SW_MASK_SFT (0x1 << 1) > +#define ACCDET_TEST_AUXADC_ADDR \ > + MT6359_ACCDET_CON0 > +#define ACCDET_TEST_AUXADC_SFT 2 > +#define ACCDET_TEST_AUXADC_MASK 0x1 > +#define ACCDET_TEST_AUXADC_MASK_SFT (0x1 << 2) > +#define ACCDET_AUXADC_ANASWCTRL_SEL_ADDR \ > + MT6359_ACCDET_CON0 > +#define ACCDET_AUXADC_ANASWCTRL_SEL_SFT 8 > +#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK 0x1 > +#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK_SFT (0x1 << 8) > +#define AUDACCDETAUXADCSWCTRL_SEL_ADDR \ > + MT6359_ACCDET_CON0 > +#define AUDACCDETAUXADCSWCTRL_SEL_SFT 9 > +#define AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1 > +#define AUDACCDETAUXADCSWCTRL_SEL_MASK_SFT (0x1 << 9) > +#define AUDACCDETAUXADCSWCTRL_SW_ADDR \ > + MT6359_ACCDET_CON0 > +#define AUDACCDETAUXADCSWCTRL_SW_SFT 10 > +#define AUDACCDETAUXADCSWCTRL_SW_MASK 0x1 > +#define AUDACCDETAUXADCSWCTRL_SW_MASK_SFT (0x1 << 10) > +#define ACCDET_TEST_ANA_ADDR \ > + MT6359_ACCDET_CON0 > +#define ACCDET_TEST_ANA_SFT 11 > +#define ACCDET_TEST_ANA_MASK 0x1 > +#define ACCDET_TEST_ANA_MASK_SFT (0x1 << 11) > +#define RG_AUDACCDETRSV_ADDR \ > + MT6359_ACCDET_CON0 > +#define RG_AUDACCDETRSV_SFT 13 > +#define RG_AUDACCDETRSV_MASK 0x3 > +#define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13) > +#define ACCDET_SW_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_SW_EN_SFT 0 > +#define ACCDET_SW_EN_MASK 0x1 > +#define ACCDET_SW_EN_MASK_SFT (0x1 << 0) > +#define ACCDET_SEQ_INIT_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_SEQ_INIT_SFT 1 > +#define ACCDET_SEQ_INIT_MASK 0x1 > +#define ACCDET_SEQ_INIT_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT0_SW_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT0_SW_EN_SFT 2 > +#define ACCDET_EINT0_SW_EN_MASK 0x1 > +#define ACCDET_EINT0_SW_EN_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT0_SEQ_INIT_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT0_SEQ_INIT_SFT 3 > +#define ACCDET_EINT0_SEQ_INIT_MASK 0x1 > +#define ACCDET_EINT0_SEQ_INIT_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT1_SW_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT1_SW_EN_SFT 4 > +#define ACCDET_EINT1_SW_EN_MASK 0x1 > +#define ACCDET_EINT1_SW_EN_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT1_SEQ_INIT_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT1_SEQ_INIT_SFT 5 > +#define ACCDET_EINT1_SEQ_INIT_MASK 0x1 > +#define ACCDET_EINT1_SEQ_INIT_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT0_INVERTER_SW_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT0_INVERTER_SW_EN_SFT 6 > +#define ACCDET_EINT0_INVERTER_SW_EN_MASK 0x1 > +#define ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT (0x1 << 6) > +#define ACCDET_EINT0_INVERTER_SEQ_INIT_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT0_INVERTER_SEQ_INIT_SFT 7 > +#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK 0x1 > +#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 7) > +#define ACCDET_EINT1_INVERTER_SW_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT1_INVERTER_SW_EN_SFT 8 > +#define ACCDET_EINT1_INVERTER_SW_EN_MASK 0x1 > +#define ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT (0x1 << 8) > +#define ACCDET_EINT1_INVERTER_SEQ_INIT_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT1_INVERTER_SEQ_INIT_SFT 9 > +#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK 0x1 > +#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 9) > +#define ACCDET_EINT0_M_SW_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT0_M_SW_EN_SFT 10 > +#define ACCDET_EINT0_M_SW_EN_MASK 0x1 > +#define ACCDET_EINT0_M_SW_EN_MASK_SFT (0x1 << 10) > +#define ACCDET_EINT1_M_SW_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT1_M_SW_EN_SFT 11 > +#define ACCDET_EINT1_M_SW_EN_MASK 0x1 > +#define ACCDET_EINT1_M_SW_EN_MASK_SFT (0x1 << 11) > +#define ACCDET_EINT_M_DETECT_EN_ADDR \ > + MT6359_ACCDET_CON1 > +#define ACCDET_EINT_M_DETECT_EN_SFT 12 > +#define ACCDET_EINT_M_DETECT_EN_MASK 0x1 > +#define ACCDET_EINT_M_DETECT_EN_MASK_SFT (0x1 << 12) > +#define ACCDET_CMP_PWM_EN_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_CMP_PWM_EN_SFT 0 > +#define ACCDET_CMP_PWM_EN_MASK 0x1 > +#define ACCDET_CMP_PWM_EN_MASK_SFT (0x1 << 0) > +#define ACCDET_VTH_PWM_EN_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_VTH_PWM_EN_SFT 1 > +#define ACCDET_VTH_PWM_EN_MASK 0x1 > +#define ACCDET_VTH_PWM_EN_MASK_SFT (0x1 << 1) > +#define ACCDET_MBIAS_PWM_EN_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_MBIAS_PWM_EN_SFT 2 > +#define ACCDET_MBIAS_PWM_EN_MASK 0x1 > +#define ACCDET_MBIAS_PWM_EN_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT_EN_PWM_EN_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_EINT_EN_PWM_EN_SFT 3 > +#define ACCDET_EINT_EN_PWM_EN_MASK 0x1 > +#define ACCDET_EINT_EN_PWM_EN_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT_CMPEN_PWM_EN_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_EINT_CMPEN_PWM_EN_SFT 4 > +#define ACCDET_EINT_CMPEN_PWM_EN_MASK 0x1 > +#define ACCDET_EINT_CMPEN_PWM_EN_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT_CMPMEN_PWM_EN_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_EINT_CMPMEN_PWM_EN_SFT 5 > +#define ACCDET_EINT_CMPMEN_PWM_EN_MASK 0x1 > +#define ACCDET_EINT_CMPMEN_PWM_EN_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT_CTURBO_PWM_EN_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_EINT_CTURBO_PWM_EN_SFT 6 > +#define ACCDET_EINT_CTURBO_PWM_EN_MASK 0x1 > +#define ACCDET_EINT_CTURBO_PWM_EN_MASK_SFT (0x1 << 6) > +#define ACCDET_CMP_PWM_IDLE_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_CMP_PWM_IDLE_SFT 8 > +#define ACCDET_CMP_PWM_IDLE_MASK 0x1 > +#define ACCDET_CMP_PWM_IDLE_MASK_SFT (0x1 << 8) > +#define ACCDET_VTH_PWM_IDLE_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_VTH_PWM_IDLE_SFT 9 > +#define ACCDET_VTH_PWM_IDLE_MASK 0x1 > +#define ACCDET_VTH_PWM_IDLE_MASK_SFT (0x1 << 9) > +#define ACCDET_MBIAS_PWM_IDLE_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_MBIAS_PWM_IDLE_SFT 10 > +#define ACCDET_MBIAS_PWM_IDLE_MASK 0x1 > +#define ACCDET_MBIAS_PWM_IDLE_MASK_SFT (0x1 << 10) > +#define ACCDET_EINT0_CMPEN_PWM_IDLE_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_EINT0_CMPEN_PWM_IDLE_SFT 11 > +#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK 0x1 > +#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 11) > +#define ACCDET_EINT1_CMPEN_PWM_IDLE_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_EINT1_CMPEN_PWM_IDLE_SFT 12 > +#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK 0x1 > +#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 12) > +#define ACCDET_PWM_EN_SW_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_PWM_EN_SW_SFT 13 > +#define ACCDET_PWM_EN_SW_MASK 0x1 > +#define ACCDET_PWM_EN_SW_MASK_SFT (0x1 << 13) > +#define ACCDET_PWM_EN_SEL_ADDR \ > + MT6359_ACCDET_CON2 > +#define ACCDET_PWM_EN_SEL_SFT 14 > +#define ACCDET_PWM_EN_SEL_MASK 0x3 > +#define ACCDET_PWM_EN_SEL_MASK_SFT (0x3 << 14) > +#define ACCDET_PWM_WIDTH_ADDR \ > + MT6359_ACCDET_CON3 > +#define ACCDET_PWM_WIDTH_SFT 0 > +#define ACCDET_PWM_WIDTH_MASK 0xFFFF > +#define ACCDET_PWM_WIDTH_MASK_SFT (0xFFFF << 0) > +#define ACCDET_PWM_THRESH_ADDR \ > + MT6359_ACCDET_CON4 > +#define ACCDET_PWM_THRESH_SFT 0 > +#define ACCDET_PWM_THRESH_MASK 0xFFFF > +#define ACCDET_PWM_THRESH_MASK_SFT (0xFFFF << 0) > +#define ACCDET_RISE_DELAY_ADDR \ > + MT6359_ACCDET_CON5 > +#define ACCDET_RISE_DELAY_SFT 0 > +#define ACCDET_RISE_DELAY_MASK 0x7FFF > +#define ACCDET_RISE_DELAY_MASK_SFT (0x7FFF << 0) > +#define ACCDET_FALL_DELAY_ADDR \ > + MT6359_ACCDET_CON5 > +#define ACCDET_FALL_DELAY_SFT 15 > +#define ACCDET_FALL_DELAY_MASK 0x1 > +#define ACCDET_FALL_DELAY_MASK_SFT (0x1 << 15) > +#define ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR \ > + MT6359_ACCDET_CON6 > +#define ACCDET_EINT_CMPMEN_PWM_THRESH_SFT 0 > +#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK 0x7 > +#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK_SFT (0x7 << 0) > +#define ACCDET_EINT_CMPMEN_PWM_WIDTH_ADDR \ > + MT6359_ACCDET_CON6 > +#define ACCDET_EINT_CMPMEN_PWM_WIDTH_SFT 4 > +#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK 0x7 > +#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK_SFT (0x7 << 4) > +#define ACCDET_EINT_EN_PWM_THRESH_ADDR \ > + MT6359_ACCDET_CON7 > +#define ACCDET_EINT_EN_PWM_THRESH_SFT 0 > +#define ACCDET_EINT_EN_PWM_THRESH_MASK 0x7 > +#define ACCDET_EINT_EN_PWM_THRESH_MASK_SFT (0x7 << 0) > +#define ACCDET_EINT_EN_PWM_WIDTH_ADDR \ > + MT6359_ACCDET_CON7 > +#define ACCDET_EINT_EN_PWM_WIDTH_SFT 4 > +#define ACCDET_EINT_EN_PWM_WIDTH_MASK 0x3 > +#define ACCDET_EINT_EN_PWM_WIDTH_MASK_SFT (0x3 << 4) > +#define ACCDET_EINT_CMPEN_PWM_THRESH_ADDR \ > + MT6359_ACCDET_CON7 > +#define ACCDET_EINT_CMPEN_PWM_THRESH_SFT 8 > +#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK 0x7 > +#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK_SFT (0x7 << 8) > +#define ACCDET_EINT_CMPEN_PWM_WIDTH_ADDR \ > + MT6359_ACCDET_CON7 > +#define ACCDET_EINT_CMPEN_PWM_WIDTH_SFT 12 > +#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK 0x3 > +#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK_SFT (0x3 << 12) > +#define ACCDET_DEBOUNCE0_ADDR \ > + MT6359_ACCDET_CON8 > +#define ACCDET_DEBOUNCE0_SFT 0 > +#define ACCDET_DEBOUNCE0_MASK 0xFFFF > +#define ACCDET_DEBOUNCE0_MASK_SFT (0xFFFF << 0) > +#define ACCDET_DEBOUNCE1_ADDR \ > + MT6359_ACCDET_CON9 > +#define ACCDET_DEBOUNCE1_SFT 0 > +#define ACCDET_DEBOUNCE1_MASK 0xFFFF > +#define ACCDET_DEBOUNCE1_MASK_SFT (0xFFFF << 0) > +#define ACCDET_DEBOUNCE2_ADDR \ > + MT6359_ACCDET_CON10 > +#define ACCDET_DEBOUNCE2_SFT 0 > +#define ACCDET_DEBOUNCE2_MASK 0xFFFF > +#define ACCDET_DEBOUNCE2_MASK_SFT (0xFFFF << 0) > +#define ACCDET_DEBOUNCE3_ADDR \ > + MT6359_ACCDET_CON11 > +#define ACCDET_DEBOUNCE3_SFT 0 > +#define ACCDET_DEBOUNCE3_MASK 0xFFFF > +#define ACCDET_DEBOUNCE3_MASK_SFT (0xFFFF << 0) > +#define ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR \ > + MT6359_ACCDET_CON12 > +#define ACCDET_CONNECT_AUXADC_TIME_DIG_SFT 0 > +#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK 0xFFFF > +#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK_SFT (0xFFFF << 0) > +#define ACCDET_CONNECT_AUXADC_TIME_ANA_ADDR \ > + MT6359_ACCDET_CON13 > +#define ACCDET_CONNECT_AUXADC_TIME_ANA_SFT 0 > +#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK 0xFFFF > +#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK_SFT (0xFFFF << 0) > +#define ACCDET_EINT_DEBOUNCE0_ADDR \ > + MT6359_ACCDET_CON14 > +#define ACCDET_EINT_DEBOUNCE0_SFT 0 > +#define ACCDET_EINT_DEBOUNCE0_MASK 0xF > +#define ACCDET_EINT_DEBOUNCE0_MASK_SFT (0xF << 0) > +#define ACCDET_EINT_DEBOUNCE1_ADDR \ > + MT6359_ACCDET_CON14 > +#define ACCDET_EINT_DEBOUNCE1_SFT 4 > +#define ACCDET_EINT_DEBOUNCE1_MASK 0xF > +#define ACCDET_EINT_DEBOUNCE1_MASK_SFT (0xF << 4) > +#define ACCDET_EINT_DEBOUNCE2_ADDR \ > + MT6359_ACCDET_CON14 > +#define ACCDET_EINT_DEBOUNCE2_SFT 8 > +#define ACCDET_EINT_DEBOUNCE2_MASK 0xF > +#define ACCDET_EINT_DEBOUNCE2_MASK_SFT (0xF << 8) > +#define ACCDET_EINT_DEBOUNCE3_ADDR \ > + MT6359_ACCDET_CON14 > +#define ACCDET_EINT_DEBOUNCE3_SFT 12 > +#define ACCDET_EINT_DEBOUNCE3_MASK 0xF > +#define ACCDET_EINT_DEBOUNCE3_MASK_SFT (0xF << 12) > +#define ACCDET_EINT_INVERTER_DEBOUNCE_ADDR \ > + MT6359_ACCDET_CON15 > +#define ACCDET_EINT_INVERTER_DEBOUNCE_SFT 0 > +#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK 0xF > +#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK_SFT (0xF << 0) > +#define ACCDET_IVAL_CUR_IN_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_IVAL_CUR_IN_SFT 0 > +#define ACCDET_IVAL_CUR_IN_MASK 0x3 > +#define ACCDET_IVAL_CUR_IN_MASK_SFT (0x3 << 0) > +#define ACCDET_IVAL_SAM_IN_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_IVAL_SAM_IN_SFT 2 > +#define ACCDET_IVAL_SAM_IN_MASK 0x3 > +#define ACCDET_IVAL_SAM_IN_MASK_SFT (0x3 << 2) > +#define ACCDET_IVAL_MEM_IN_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_IVAL_MEM_IN_SFT 4 > +#define ACCDET_IVAL_MEM_IN_MASK 0x3 > +#define ACCDET_IVAL_MEM_IN_MASK_SFT (0x3 << 4) > +#define ACCDET_EINT_IVAL_CUR_IN_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_EINT_IVAL_CUR_IN_SFT 6 > +#define ACCDET_EINT_IVAL_CUR_IN_MASK 0x3 > +#define ACCDET_EINT_IVAL_CUR_IN_MASK_SFT (0x3 << 6) > +#define ACCDET_EINT_IVAL_SAM_IN_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_EINT_IVAL_SAM_IN_SFT 8 > +#define ACCDET_EINT_IVAL_SAM_IN_MASK 0x3 > +#define ACCDET_EINT_IVAL_SAM_IN_MASK_SFT (0x3 << 8) > +#define ACCDET_EINT_IVAL_MEM_IN_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_EINT_IVAL_MEM_IN_SFT 10 > +#define ACCDET_EINT_IVAL_MEM_IN_MASK 0x3 > +#define ACCDET_EINT_IVAL_MEM_IN_MASK_SFT (0x3 << 10) > +#define ACCDET_IVAL_SEL_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_IVAL_SEL_SFT 12 > +#define ACCDET_IVAL_SEL_MASK 0x1 > +#define ACCDET_IVAL_SEL_MASK_SFT (0x1 << 12) > +#define ACCDET_EINT_IVAL_SEL_ADDR \ > + MT6359_ACCDET_CON16 > +#define ACCDET_EINT_IVAL_SEL_SFT 13 > +#define ACCDET_EINT_IVAL_SEL_MASK 0x1 > +#define ACCDET_EINT_IVAL_SEL_MASK_SFT (0x1 << 13) > +#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_ADDR \ > + MT6359_ACCDET_CON17 > +#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_SFT 0 > +#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK 0x1 > +#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK_SFT (0x1 << 0) > +#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_ADDR \ > + MT6359_ACCDET_CON17 > +#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_SFT 1 > +#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK 0x1 > +#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_ADDR \ > + MT6359_ACCDET_CON17 > +#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_SFT 2 > +#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK 0x1 > +#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT_INVERTER_IVAL_SEL_ADDR \ > + MT6359_ACCDET_CON17 > +#define ACCDET_EINT_INVERTER_IVAL_SEL_SFT 3 > +#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK 0x1 > +#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT (0x1 << 3) > +#define ACCDET_IRQ_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_IRQ_SFT 0 > +#define ACCDET_IRQ_MASK 0x1 > +#define ACCDET_IRQ_MASK_SFT (0x1 << 0) > +#define ACCDET_EINT0_IRQ_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_EINT0_IRQ_SFT 2 > +#define ACCDET_EINT0_IRQ_MASK 0x1 > +#define ACCDET_EINT0_IRQ_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT1_IRQ_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_EINT1_IRQ_SFT 3 > +#define ACCDET_EINT1_IRQ_MASK 0x1 > +#define ACCDET_EINT1_IRQ_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT_IN_INVERSE_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_EINT_IN_INVERSE_SFT 4 > +#define ACCDET_EINT_IN_INVERSE_MASK 0x1 > +#define ACCDET_EINT_IN_INVERSE_MASK_SFT (0x1 << 4) > +#define ACCDET_IRQ_CLR_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_IRQ_CLR_SFT 8 > +#define ACCDET_IRQ_CLR_MASK 0x1 > +#define ACCDET_IRQ_CLR_MASK_SFT (0x1 << 8) > +#define ACCDET_EINT0_IRQ_CLR_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_EINT0_IRQ_CLR_SFT 10 > +#define ACCDET_EINT0_IRQ_CLR_MASK 0x1 > +#define ACCDET_EINT0_IRQ_CLR_MASK_SFT (0x1 << 10) > +#define ACCDET_EINT1_IRQ_CLR_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_EINT1_IRQ_CLR_SFT 11 > +#define ACCDET_EINT1_IRQ_CLR_MASK 0x1 > +#define ACCDET_EINT1_IRQ_CLR_MASK_SFT (0x1 << 11) > +#define ACCDET_EINT_M_PLUG_IN_NUM_ADDR \ > + MT6359_ACCDET_CON18 > +#define ACCDET_EINT_M_PLUG_IN_NUM_SFT 12 > +#define ACCDET_EINT_M_PLUG_IN_NUM_MASK 0x7 > +#define ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT (0x7 << 12) > +#define ACCDET_DA_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_DA_STABLE_SFT 0 > +#define ACCDET_DA_STABLE_MASK 0x1 > +#define ACCDET_DA_STABLE_MASK_SFT (0x1 << 0) > +#define ACCDET_EINT0_EN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT0_EN_STABLE_SFT 1 > +#define ACCDET_EINT0_EN_STABLE_MASK 0x1 > +#define ACCDET_EINT0_EN_STABLE_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT0_CMPEN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT0_CMPEN_STABLE_SFT 2 > +#define ACCDET_EINT0_CMPEN_STABLE_MASK 0x1 > +#define ACCDET_EINT0_CMPEN_STABLE_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT0_CMPMEN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT0_CMPMEN_STABLE_SFT 3 > +#define ACCDET_EINT0_CMPMEN_STABLE_MASK 0x1 > +#define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT0_CTURBO_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT0_CTURBO_STABLE_SFT 4 > +#define ACCDET_EINT0_CTURBO_STABLE_MASK 0x1 > +#define ACCDET_EINT0_CTURBO_STABLE_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT0_CEN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT0_CEN_STABLE_SFT 5 > +#define ACCDET_EINT0_CEN_STABLE_MASK 0x1 > +#define ACCDET_EINT0_CEN_STABLE_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT1_EN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT1_EN_STABLE_SFT 6 > +#define ACCDET_EINT1_EN_STABLE_MASK 0x1 > +#define ACCDET_EINT1_EN_STABLE_MASK_SFT (0x1 << 6) > +#define ACCDET_EINT1_CMPEN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT1_CMPEN_STABLE_SFT 7 > +#define ACCDET_EINT1_CMPEN_STABLE_MASK 0x1 > +#define ACCDET_EINT1_CMPEN_STABLE_MASK_SFT (0x1 << 7) > +#define ACCDET_EINT1_CMPMEN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT1_CMPMEN_STABLE_SFT 8 > +#define ACCDET_EINT1_CMPMEN_STABLE_MASK 0x1 > +#define ACCDET_EINT1_CMPMEN_STABLE_MASK_SFT (0x1 << 8) > +#define ACCDET_EINT1_CTURBO_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT1_CTURBO_STABLE_SFT 9 > +#define ACCDET_EINT1_CTURBO_STABLE_MASK 0x1 > +#define ACCDET_EINT1_CTURBO_STABLE_MASK_SFT (0x1 << 9) > +#define ACCDET_EINT1_CEN_STABLE_ADDR \ > + MT6359_ACCDET_CON19 > +#define ACCDET_EINT1_CEN_STABLE_SFT 10 > +#define ACCDET_EINT1_CEN_STABLE_MASK 0x1 > +#define ACCDET_EINT1_CEN_STABLE_MASK_SFT (0x1 << 10) > +#define ACCDET_HWMODE_EN_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_HWMODE_EN_SFT 0 > +#define ACCDET_HWMODE_EN_MASK 0x1 > +#define ACCDET_HWMODE_EN_MASK_SFT (0x1 << 0) > +#define ACCDET_HWMODE_SEL_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_HWMODE_SEL_SFT 1 > +#define ACCDET_HWMODE_SEL_MASK 0x3 > +#define ACCDET_HWMODE_SEL_MASK_SFT (0x3 << 1) > +#define ACCDET_PLUG_OUT_DETECT_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_PLUG_OUT_DETECT_SFT 3 > +#define ACCDET_PLUG_OUT_DETECT_MASK 0x1 > +#define ACCDET_PLUG_OUT_DETECT_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT0_REVERSE_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_EINT0_REVERSE_SFT 4 > +#define ACCDET_EINT0_REVERSE_MASK 0x1 > +#define ACCDET_EINT0_REVERSE_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT1_REVERSE_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_EINT1_REVERSE_SFT 5 > +#define ACCDET_EINT1_REVERSE_MASK 0x1 > +#define ACCDET_EINT1_REVERSE_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT_HWMODE_EN_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_EINT_HWMODE_EN_SFT 8 > +#define ACCDET_EINT_HWMODE_EN_MASK 0x1 > +#define ACCDET_EINT_HWMODE_EN_MASK_SFT (0x1 << 8) > +#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_SFT 9 > +#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK 0x1 > +#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK_SFT (0x1 << 9) > +#define ACCDET_EINT_M_PLUG_IN_EN_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_EINT_M_PLUG_IN_EN_SFT 10 > +#define ACCDET_EINT_M_PLUG_IN_EN_MASK 0x1 > +#define ACCDET_EINT_M_PLUG_IN_EN_MASK_SFT (0x1 << 10) > +#define ACCDET_EINT_M_HWMODE_EN_ADDR \ > + MT6359_ACCDET_CON20 > +#define ACCDET_EINT_M_HWMODE_EN_SFT 11 > +#define ACCDET_EINT_M_HWMODE_EN_MASK 0x1 > +#define ACCDET_EINT_M_HWMODE_EN_MASK_SFT (0x1 << 11) > +#define ACCDET_TEST_CMPEN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_TEST_CMPEN_SFT 0 > +#define ACCDET_TEST_CMPEN_MASK 0x1 > +#define ACCDET_TEST_CMPEN_MASK_SFT (0x1 << 0) > +#define ACCDET_TEST_VTHEN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_TEST_VTHEN_SFT 1 > +#define ACCDET_TEST_VTHEN_MASK 0x1 > +#define ACCDET_TEST_VTHEN_MASK_SFT (0x1 << 1) > +#define ACCDET_TEST_MBIASEN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_TEST_MBIASEN_SFT 2 > +#define ACCDET_TEST_MBIASEN_MASK 0x1 > +#define ACCDET_TEST_MBIASEN_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT_TEST_EN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_EN_SFT 3 > +#define ACCDET_EINT_TEST_EN_MASK 0x1 > +#define ACCDET_EINT_TEST_EN_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT_TEST_INVEN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_INVEN_SFT 4 > +#define ACCDET_EINT_TEST_INVEN_MASK 0x1 > +#define ACCDET_EINT_TEST_INVEN_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT_TEST_CMPEN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_CMPEN_SFT 5 > +#define ACCDET_EINT_TEST_CMPEN_MASK 0x1 > +#define ACCDET_EINT_TEST_CMPEN_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT_TEST_CMPMEN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_CMPMEN_SFT 6 > +#define ACCDET_EINT_TEST_CMPMEN_MASK 0x1 > +#define ACCDET_EINT_TEST_CMPMEN_MASK_SFT (0x1 << 6) > +#define ACCDET_EINT_TEST_CTURBO_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_CTURBO_SFT 7 > +#define ACCDET_EINT_TEST_CTURBO_MASK 0x1 > +#define ACCDET_EINT_TEST_CTURBO_MASK_SFT (0x1 << 7) > +#define ACCDET_EINT_TEST_CEN_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_CEN_SFT 8 > +#define ACCDET_EINT_TEST_CEN_MASK 0x1 > +#define ACCDET_EINT_TEST_CEN_MASK_SFT (0x1 << 8) > +#define ACCDET_TEST_B_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_TEST_B_SFT 9 > +#define ACCDET_TEST_B_MASK 0x1 > +#define ACCDET_TEST_B_MASK_SFT (0x1 << 9) > +#define ACCDET_TEST_A_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_TEST_A_SFT 10 > +#define ACCDET_TEST_A_MASK 0x1 > +#define ACCDET_TEST_A_MASK_SFT (0x1 << 10) > +#define ACCDET_EINT_TEST_CMPOUT_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_CMPOUT_SFT 11 > +#define ACCDET_EINT_TEST_CMPOUT_MASK 0x1 > +#define ACCDET_EINT_TEST_CMPOUT_MASK_SFT (0x1 << 11) > +#define ACCDET_EINT_TEST_CMPMOUT_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_CMPMOUT_SFT 12 > +#define ACCDET_EINT_TEST_CMPMOUT_MASK 0x1 > +#define ACCDET_EINT_TEST_CMPMOUT_MASK_SFT (0x1 << 12) > +#define ACCDET_EINT_TEST_INVOUT_ADDR \ > + MT6359_ACCDET_CON21 > +#define ACCDET_EINT_TEST_INVOUT_SFT 13 > +#define ACCDET_EINT_TEST_INVOUT_MASK 0x1 > +#define ACCDET_EINT_TEST_INVOUT_MASK_SFT (0x1 << 13) > +#define ACCDET_CMPEN_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_CMPEN_SEL_SFT 0 > +#define ACCDET_CMPEN_SEL_MASK 0x1 > +#define ACCDET_CMPEN_SEL_MASK_SFT (0x1 << 0) > +#define ACCDET_VTHEN_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_VTHEN_SEL_SFT 1 > +#define ACCDET_VTHEN_SEL_MASK 0x1 > +#define ACCDET_VTHEN_SEL_MASK_SFT (0x1 << 1) > +#define ACCDET_MBIASEN_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_MBIASEN_SEL_SFT 2 > +#define ACCDET_MBIASEN_SEL_MASK 0x1 > +#define ACCDET_MBIASEN_SEL_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT_EN_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_EN_SEL_SFT 3 > +#define ACCDET_EINT_EN_SEL_MASK 0x1 > +#define ACCDET_EINT_EN_SEL_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT_INVEN_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_INVEN_SEL_SFT 4 > +#define ACCDET_EINT_INVEN_SEL_MASK 0x1 > +#define ACCDET_EINT_INVEN_SEL_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT_CMPEN_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_CMPEN_SEL_SFT 5 > +#define ACCDET_EINT_CMPEN_SEL_MASK 0x1 > +#define ACCDET_EINT_CMPEN_SEL_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT_CMPMEN_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_CMPMEN_SEL_SFT 6 > +#define ACCDET_EINT_CMPMEN_SEL_MASK 0x1 > +#define ACCDET_EINT_CMPMEN_SEL_MASK_SFT (0x1 << 6) > +#define ACCDET_EINT_CTURBO_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_CTURBO_SEL_SFT 7 > +#define ACCDET_EINT_CTURBO_SEL_MASK 0x1 > +#define ACCDET_EINT_CTURBO_SEL_MASK_SFT (0x1 << 7) > +#define ACCDET_B_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_B_SEL_SFT 9 > +#define ACCDET_B_SEL_MASK 0x1 > +#define ACCDET_B_SEL_MASK_SFT (0x1 << 9) > +#define ACCDET_A_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_A_SEL_SFT 10 > +#define ACCDET_A_SEL_MASK 0x1 > +#define ACCDET_A_SEL_MASK_SFT (0x1 << 10) > +#define ACCDET_EINT_CMPOUT_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_CMPOUT_SEL_SFT 11 > +#define ACCDET_EINT_CMPOUT_SEL_MASK 0x1 > +#define ACCDET_EINT_CMPOUT_SEL_MASK_SFT (0x1 << 11) > +#define ACCDET_EINT_CMPMOUT_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_CMPMOUT_SEL_SFT 12 > +#define ACCDET_EINT_CMPMOUT_SEL_MASK 0x1 > +#define ACCDET_EINT_CMPMOUT_SEL_MASK_SFT (0x1 << 12) > +#define ACCDET_EINT_INVOUT_SEL_ADDR \ > + MT6359_ACCDET_CON22 > +#define ACCDET_EINT_INVOUT_SEL_SFT 13 > +#define ACCDET_EINT_INVOUT_SEL_MASK 0x1 > +#define ACCDET_EINT_INVOUT_SEL_MASK_SFT (0x1 << 13) > +#define ACCDET_CMPEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_CMPEN_SW_SFT 0 > +#define ACCDET_CMPEN_SW_MASK 0x1 > +#define ACCDET_CMPEN_SW_MASK_SFT (0x1 << 0) > +#define ACCDET_VTHEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_VTHEN_SW_SFT 1 > +#define ACCDET_VTHEN_SW_MASK 0x1 > +#define ACCDET_VTHEN_SW_MASK_SFT (0x1 << 1) > +#define ACCDET_MBIASEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_MBIASEN_SW_SFT 2 > +#define ACCDET_MBIASEN_SW_MASK 0x1 > +#define ACCDET_MBIASEN_SW_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT0_EN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT0_EN_SW_SFT 3 > +#define ACCDET_EINT0_EN_SW_MASK 0x1 > +#define ACCDET_EINT0_EN_SW_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT0_INVEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT0_INVEN_SW_SFT 4 > +#define ACCDET_EINT0_INVEN_SW_MASK 0x1 > +#define ACCDET_EINT0_INVEN_SW_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT0_CMPEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT0_CMPEN_SW_SFT 5 > +#define ACCDET_EINT0_CMPEN_SW_MASK 0x1 > +#define ACCDET_EINT0_CMPEN_SW_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT0_CMPMEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT0_CMPMEN_SW_SFT 6 > +#define ACCDET_EINT0_CMPMEN_SW_MASK 0x1 > +#define ACCDET_EINT0_CMPMEN_SW_MASK_SFT (0x1 << 6) > +#define ACCDET_EINT0_CTURBO_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT0_CTURBO_SW_SFT 7 > +#define ACCDET_EINT0_CTURBO_SW_MASK 0x1 > +#define ACCDET_EINT0_CTURBO_SW_MASK_SFT (0x1 << 7) > +#define ACCDET_EINT1_EN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT1_EN_SW_SFT 8 > +#define ACCDET_EINT1_EN_SW_MASK 0x1 > +#define ACCDET_EINT1_EN_SW_MASK_SFT (0x1 << 8) > +#define ACCDET_EINT1_INVEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT1_INVEN_SW_SFT 9 > +#define ACCDET_EINT1_INVEN_SW_MASK 0x1 > +#define ACCDET_EINT1_INVEN_SW_MASK_SFT (0x1 << 9) > +#define ACCDET_EINT1_CMPEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT1_CMPEN_SW_SFT 10 > +#define ACCDET_EINT1_CMPEN_SW_MASK 0x1 > +#define ACCDET_EINT1_CMPEN_SW_MASK_SFT (0x1 << 10) > +#define ACCDET_EINT1_CMPMEN_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT1_CMPMEN_SW_SFT 11 > +#define ACCDET_EINT1_CMPMEN_SW_MASK 0x1 > +#define ACCDET_EINT1_CMPMEN_SW_MASK_SFT (0x1 << 11) > +#define ACCDET_EINT1_CTURBO_SW_ADDR \ > + MT6359_ACCDET_CON23 > +#define ACCDET_EINT1_CTURBO_SW_SFT 12 > +#define ACCDET_EINT1_CTURBO_SW_MASK 0x1 > +#define ACCDET_EINT1_CTURBO_SW_MASK_SFT (0x1 << 12) > +#define ACCDET_B_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_B_SW_SFT 0 > +#define ACCDET_B_SW_MASK 0x1 > +#define ACCDET_B_SW_MASK_SFT (0x1 << 0) > +#define ACCDET_A_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_A_SW_SFT 1 > +#define ACCDET_A_SW_MASK 0x1 > +#define ACCDET_A_SW_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT0_CMPOUT_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_EINT0_CMPOUT_SW_SFT 2 > +#define ACCDET_EINT0_CMPOUT_SW_MASK 0x1 > +#define ACCDET_EINT0_CMPOUT_SW_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT0_CMPMOUT_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_EINT0_CMPMOUT_SW_SFT 3 > +#define ACCDET_EINT0_CMPMOUT_SW_MASK 0x1 > +#define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT0_INVOUT_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_EINT0_INVOUT_SW_SFT 4 > +#define ACCDET_EINT0_INVOUT_SW_MASK 0x1 > +#define ACCDET_EINT0_INVOUT_SW_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT1_CMPOUT_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_EINT1_CMPOUT_SW_SFT 5 > +#define ACCDET_EINT1_CMPOUT_SW_MASK 0x1 > +#define ACCDET_EINT1_CMPOUT_SW_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT1_CMPMOUT_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_EINT1_CMPMOUT_SW_SFT 6 > +#define ACCDET_EINT1_CMPMOUT_SW_MASK 0x1 > +#define ACCDET_EINT1_CMPMOUT_SW_MASK_SFT (0x1 << 6) > +#define ACCDET_EINT1_INVOUT_SW_ADDR \ > + MT6359_ACCDET_CON24 > +#define ACCDET_EINT1_INVOUT_SW_SFT 7 > +#define ACCDET_EINT1_INVOUT_SW_MASK 0x1 > +#define ACCDET_EINT1_INVOUT_SW_MASK_SFT (0x1 << 7) > +#define AD_AUDACCDETCMPOB_ADDR \ > + MT6359_ACCDET_CON25 > +#define AD_AUDACCDETCMPOB_SFT 0 > +#define AD_AUDACCDETCMPOB_MASK 0x1 > +#define AD_AUDACCDETCMPOB_MASK_SFT (0x1 << 0) > +#define AD_AUDACCDETCMPOA_ADDR \ > + MT6359_ACCDET_CON25 > +#define AD_AUDACCDETCMPOA_SFT 1 > +#define AD_AUDACCDETCMPOA_MASK 0x1 > +#define AD_AUDACCDETCMPOA_MASK_SFT (0x1 << 1) > +#define ACCDET_CUR_IN_ADDR \ > + MT6359_ACCDET_CON25 > +#define ACCDET_CUR_IN_SFT 2 > +#define ACCDET_CUR_IN_MASK 0x3 > +#define ACCDET_CUR_IN_MASK_SFT (0x3 << 2) > +#define ACCDET_SAM_IN_ADDR \ > + MT6359_ACCDET_CON25 > +#define ACCDET_SAM_IN_SFT 4 > +#define ACCDET_SAM_IN_MASK 0x3 > +#define ACCDET_SAM_IN_MASK_SFT (0x3 << 4) > +#define ACCDET_MEM_IN_ADDR \ > + MT6359_ACCDET_CON25 > +#define ACCDET_MEM_IN_SFT 6 > +#define ACCDET_MEM_IN_MASK 0x3 > +#define ACCDET_MEM_IN_MASK_SFT (0x3 << 6) > +#define ACCDET_STATE_ADDR \ > + MT6359_ACCDET_CON25 > +#define ACCDET_STATE_SFT 8 > +#define ACCDET_STATE_MASK 0x7 > +#define ACCDET_STATE_MASK_SFT (0x7 << 8) > +#define DA_AUDACCDETMBIASCLK_ADDR \ > + MT6359_ACCDET_CON25 > +#define DA_AUDACCDETMBIASCLK_SFT 12 > +#define DA_AUDACCDETMBIASCLK_MASK 0x1 > +#define DA_AUDACCDETMBIASCLK_MASK_SFT (0x1 << 12) > +#define DA_AUDACCDETVTHCLK_ADDR \ > + MT6359_ACCDET_CON25 > +#define DA_AUDACCDETVTHCLK_SFT 13 > +#define DA_AUDACCDETVTHCLK_MASK 0x1 > +#define DA_AUDACCDETVTHCLK_MASK_SFT (0x1 << 13) > +#define DA_AUDACCDETCMPCLK_ADDR \ > + MT6359_ACCDET_CON25 > +#define DA_AUDACCDETCMPCLK_SFT 14 > +#define DA_AUDACCDETCMPCLK_MASK 0x1 > +#define DA_AUDACCDETCMPCLK_MASK_SFT (0x1 << 14) > +#define DA_AUDACCDETAUXADCSWCTRL_ADDR \ > + MT6359_ACCDET_CON25 > +#define DA_AUDACCDETAUXADCSWCTRL_SFT 15 > +#define DA_AUDACCDETAUXADCSWCTRL_MASK 0x1 > +#define DA_AUDACCDETAUXADCSWCTRL_MASK_SFT (0x1 << 15) > +#define AD_EINT0CMPMOUT_ADDR \ > + MT6359_ACCDET_CON26 > +#define AD_EINT0CMPMOUT_SFT 0 > +#define AD_EINT0CMPMOUT_MASK 0x1 > +#define AD_EINT0CMPMOUT_MASK_SFT (0x1 << 0) > +#define AD_EINT0CMPOUT_ADDR \ > + MT6359_ACCDET_CON26 > +#define AD_EINT0CMPOUT_SFT 1 > +#define AD_EINT0CMPOUT_MASK 0x1 > +#define AD_EINT0CMPOUT_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT0_CUR_IN_ADDR \ > + MT6359_ACCDET_CON26 > +#define ACCDET_EINT0_CUR_IN_SFT 2 > +#define ACCDET_EINT0_CUR_IN_MASK 0x3 > +#define ACCDET_EINT0_CUR_IN_MASK_SFT (0x3 << 2) > +#define ACCDET_EINT0_SAM_IN_ADDR \ > + MT6359_ACCDET_CON26 > +#define ACCDET_EINT0_SAM_IN_SFT 4 > +#define ACCDET_EINT0_SAM_IN_MASK 0x3 > +#define ACCDET_EINT0_SAM_IN_MASK_SFT (0x3 << 4) > +#define ACCDET_EINT0_MEM_IN_ADDR \ > + MT6359_ACCDET_CON26 > +#define ACCDET_EINT0_MEM_IN_SFT 6 > +#define ACCDET_EINT0_MEM_IN_MASK 0x3 > +#define ACCDET_EINT0_MEM_IN_MASK_SFT (0x3 << 6) > +#define ACCDET_EINT0_STATE_ADDR \ > + MT6359_ACCDET_CON26 > +#define ACCDET_EINT0_STATE_SFT 8 > +#define ACCDET_EINT0_STATE_MASK 0x7 > +#define ACCDET_EINT0_STATE_MASK_SFT (0x7 << 8) > +#define DA_EINT0CMPEN_ADDR \ > + MT6359_ACCDET_CON26 > +#define DA_EINT0CMPEN_SFT 13 > +#define DA_EINT0CMPEN_MASK 0x1 > +#define DA_EINT0CMPEN_MASK_SFT (0x1 << 13) > +#define DA_EINT0CMPMEN_ADDR \ > + MT6359_ACCDET_CON26 > +#define DA_EINT0CMPMEN_SFT 14 > +#define DA_EINT0CMPMEN_MASK 0x1 > +#define DA_EINT0CMPMEN_MASK_SFT (0x1 << 14) > +#define DA_EINT0CTURBO_ADDR \ > + MT6359_ACCDET_CON26 > +#define DA_EINT0CTURBO_SFT 15 > +#define DA_EINT0CTURBO_MASK 0x1 > +#define DA_EINT0CTURBO_MASK_SFT (0x1 << 15) > +#define AD_EINT1CMPMOUT_ADDR \ > + MT6359_ACCDET_CON27 > +#define AD_EINT1CMPMOUT_SFT 0 > +#define AD_EINT1CMPMOUT_MASK 0x1 > +#define AD_EINT1CMPMOUT_MASK_SFT (0x1 << 0) > +#define AD_EINT1CMPOUT_ADDR \ > + MT6359_ACCDET_CON27 > +#define AD_EINT1CMPOUT_SFT 1 > +#define AD_EINT1CMPOUT_MASK 0x1 > +#define AD_EINT1CMPOUT_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT1_CUR_IN_ADDR \ > + MT6359_ACCDET_CON27 > +#define ACCDET_EINT1_CUR_IN_SFT 2 > +#define ACCDET_EINT1_CUR_IN_MASK 0x3 > +#define ACCDET_EINT1_CUR_IN_MASK_SFT (0x3 << 2) > +#define ACCDET_EINT1_SAM_IN_ADDR \ > + MT6359_ACCDET_CON27 > +#define ACCDET_EINT1_SAM_IN_SFT 4 > +#define ACCDET_EINT1_SAM_IN_MASK 0x3 > +#define ACCDET_EINT1_SAM_IN_MASK_SFT (0x3 << 4) > +#define ACCDET_EINT1_MEM_IN_ADDR \ > + MT6359_ACCDET_CON27 > +#define ACCDET_EINT1_MEM_IN_SFT 6 > +#define ACCDET_EINT1_MEM_IN_MASK 0x3 > +#define ACCDET_EINT1_MEM_IN_MASK_SFT (0x3 << 6) > +#define ACCDET_EINT1_STATE_ADDR \ > + MT6359_ACCDET_CON27 > +#define ACCDET_EINT1_STATE_SFT 8 > +#define ACCDET_EINT1_STATE_MASK 0x7 > +#define ACCDET_EINT1_STATE_MASK_SFT (0x7 << 8) > +#define DA_EINT1CMPEN_ADDR \ > + MT6359_ACCDET_CON27 > +#define DA_EINT1CMPEN_SFT 13 > +#define DA_EINT1CMPEN_MASK 0x1 > +#define DA_EINT1CMPEN_MASK_SFT (0x1 << 13) > +#define DA_EINT1CMPMEN_ADDR \ > + MT6359_ACCDET_CON27 > +#define DA_EINT1CMPMEN_SFT 14 > +#define DA_EINT1CMPMEN_MASK 0x1 > +#define DA_EINT1CMPMEN_MASK_SFT (0x1 << 14) > +#define DA_EINT1CTURBO_ADDR \ > + MT6359_ACCDET_CON27 > +#define DA_EINT1CTURBO_SFT 15 > +#define DA_EINT1CTURBO_MASK 0x1 > +#define DA_EINT1CTURBO_MASK_SFT (0x1 << 15) > +#define AD_EINT0INVOUT_ADDR \ > + MT6359_ACCDET_CON28 > +#define AD_EINT0INVOUT_SFT 0 > +#define AD_EINT0INVOUT_MASK 0x1 > +#define AD_EINT0INVOUT_MASK_SFT (0x1 << 0) > +#define ACCDET_EINT0_INVERTER_CUR_IN_ADDR \ > + MT6359_ACCDET_CON28 > +#define ACCDET_EINT0_INVERTER_CUR_IN_SFT 1 > +#define ACCDET_EINT0_INVERTER_CUR_IN_MASK 0x1 > +#define ACCDET_EINT0_INVERTER_CUR_IN_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT0_INVERTER_SAM_IN_ADDR \ > + MT6359_ACCDET_CON28 > +#define ACCDET_EINT0_INVERTER_SAM_IN_SFT 2 > +#define ACCDET_EINT0_INVERTER_SAM_IN_MASK 0x1 > +#define ACCDET_EINT0_INVERTER_SAM_IN_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT0_INVERTER_MEM_IN_ADDR \ > + MT6359_ACCDET_CON28 > +#define ACCDET_EINT0_INVERTER_MEM_IN_SFT 3 > +#define ACCDET_EINT0_INVERTER_MEM_IN_MASK 0x1 > +#define ACCDET_EINT0_INVERTER_MEM_IN_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT0_INVERTER_STATE_ADDR \ > + MT6359_ACCDET_CON28 > +#define ACCDET_EINT0_INVERTER_STATE_SFT 8 > +#define ACCDET_EINT0_INVERTER_STATE_MASK 0x7 > +#define ACCDET_EINT0_INVERTER_STATE_MASK_SFT (0x7 << 8) > +#define DA_EINT0EN_ADDR \ > + MT6359_ACCDET_CON28 > +#define DA_EINT0EN_SFT 12 > +#define DA_EINT0EN_MASK 0x1 > +#define DA_EINT0EN_MASK_SFT (0x1 << 12) > +#define DA_EINT0INVEN_ADDR \ > + MT6359_ACCDET_CON28 > +#define DA_EINT0INVEN_SFT 13 > +#define DA_EINT0INVEN_MASK 0x1 > +#define DA_EINT0INVEN_MASK_SFT (0x1 << 13) > +#define DA_EINT0CEN_ADDR \ > + MT6359_ACCDET_CON28 > +#define DA_EINT0CEN_SFT 14 > +#define DA_EINT0CEN_MASK 0x1 > +#define DA_EINT0CEN_MASK_SFT (0x1 << 14) > +#define AD_EINT1INVOUT_ADDR \ > + MT6359_ACCDET_CON29 > +#define AD_EINT1INVOUT_SFT 0 > +#define AD_EINT1INVOUT_MASK 0x1 > +#define AD_EINT1INVOUT_MASK_SFT (0x1 << 0) > +#define ACCDET_EINT1_INVERTER_CUR_IN_ADDR \ > + MT6359_ACCDET_CON29 > +#define ACCDET_EINT1_INVERTER_CUR_IN_SFT 1 > +#define ACCDET_EINT1_INVERTER_CUR_IN_MASK 0x1 > +#define ACCDET_EINT1_INVERTER_CUR_IN_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT1_INVERTER_SAM_IN_ADDR \ > + MT6359_ACCDET_CON29 > +#define ACCDET_EINT1_INVERTER_SAM_IN_SFT 2 > +#define ACCDET_EINT1_INVERTER_SAM_IN_MASK 0x1 > +#define ACCDET_EINT1_INVERTER_SAM_IN_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT1_INVERTER_MEM_IN_ADDR \ > + MT6359_ACCDET_CON29 > +#define ACCDET_EINT1_INVERTER_MEM_IN_SFT 3 > +#define ACCDET_EINT1_INVERTER_MEM_IN_MASK 0x1 > +#define ACCDET_EINT1_INVERTER_MEM_IN_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT1_INVERTER_STATE_ADDR \ > + MT6359_ACCDET_CON29 > +#define ACCDET_EINT1_INVERTER_STATE_SFT 8 > +#define ACCDET_EINT1_INVERTER_STATE_MASK 0x7 > +#define ACCDET_EINT1_INVERTER_STATE_MASK_SFT (0x7 << 8) > +#define DA_EINT1EN_ADDR \ > + MT6359_ACCDET_CON29 > +#define DA_EINT1EN_SFT 12 > +#define DA_EINT1EN_MASK 0x1 > +#define DA_EINT1EN_MASK_SFT (0x1 << 12) > +#define DA_EINT1INVEN_ADDR \ > + MT6359_ACCDET_CON29 > +#define DA_EINT1INVEN_SFT 13 > +#define DA_EINT1INVEN_MASK 0x1 > +#define DA_EINT1INVEN_MASK_SFT (0x1 << 13) > +#define DA_EINT1CEN_ADDR \ > + MT6359_ACCDET_CON29 > +#define DA_EINT1CEN_SFT 14 > +#define DA_EINT1CEN_MASK 0x1 > +#define DA_EINT1CEN_MASK_SFT (0x1 << 14) > +#define ACCDET_EN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EN_SFT 0 > +#define ACCDET_EN_MASK 0x1 > +#define ACCDET_EN_MASK_SFT (0x1 << 0) > +#define ACCDET_EINT0_EN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT0_EN_SFT 1 > +#define ACCDET_EINT0_EN_MASK 0x1 > +#define ACCDET_EINT0_EN_MASK_SFT (0x1 << 1) > +#define ACCDET_EINT1_EN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT1_EN_SFT 2 > +#define ACCDET_EINT1_EN_MASK 0x1 > +#define ACCDET_EINT1_EN_MASK_SFT (0x1 << 2) > +#define ACCDET_EINT0_M_EN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT0_M_EN_SFT 3 > +#define ACCDET_EINT0_M_EN_MASK 0x1 > +#define ACCDET_EINT0_M_EN_MASK_SFT (0x1 << 3) > +#define ACCDET_EINT0_DETECT_MOISTURE_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT0_DETECT_MOISTURE_SFT 4 > +#define ACCDET_EINT0_DETECT_MOISTURE_MASK 0x1 > +#define ACCDET_EINT0_DETECT_MOISTURE_MASK_SFT (0x1 << 4) > +#define ACCDET_EINT0_PLUG_IN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT0_PLUG_IN_SFT 5 > +#define ACCDET_EINT0_PLUG_IN_MASK 0x1 > +#define ACCDET_EINT0_PLUG_IN_MASK_SFT (0x1 << 5) > +#define ACCDET_EINT0_M_PLUG_IN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT0_M_PLUG_IN_SFT 6 > +#define ACCDET_EINT0_M_PLUG_IN_MASK 0x1 > +#define ACCDET_EINT0_M_PLUG_IN_MASK_SFT (0x1 << 6) > +#define ACCDET_EINT1_M_EN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT1_M_EN_SFT 7 > +#define ACCDET_EINT1_M_EN_MASK 0x1 > +#define ACCDET_EINT1_M_EN_MASK_SFT (0x1 << 7) > +#define ACCDET_EINT1_DETECT_MOISTURE_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT1_DETECT_MOISTURE_SFT 8 > +#define ACCDET_EINT1_DETECT_MOISTURE_MASK 0x1 > +#define ACCDET_EINT1_DETECT_MOISTURE_MASK_SFT (0x1 << 8) > +#define ACCDET_EINT1_PLUG_IN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT1_PLUG_IN_SFT 9 > +#define ACCDET_EINT1_PLUG_IN_MASK 0x1 > +#define ACCDET_EINT1_PLUG_IN_MASK_SFT (0x1 << 9) > +#define ACCDET_EINT1_M_PLUG_IN_ADDR \ > + MT6359_ACCDET_CON30 > +#define ACCDET_EINT1_M_PLUG_IN_SFT 10 > +#define ACCDET_EINT1_M_PLUG_IN_MASK 0x1 > +#define ACCDET_EINT1_M_PLUG_IN_MASK_SFT (0x1 << 10) > +#define ACCDET_CUR_DEB_ADDR \ > + MT6359_ACCDET_CON31 > +#define ACCDET_CUR_DEB_SFT 0 > +#define ACCDET_CUR_DEB_MASK 0xFFFF > +#define ACCDET_CUR_DEB_MASK_SFT (0xFFFF << 0) > +#define ACCDET_EINT0_CUR_DEB_ADDR \ > + MT6359_ACCDET_CON32 > +#define ACCDET_EINT0_CUR_DEB_SFT 0 > +#define ACCDET_EINT0_CUR_DEB_MASK 0x7FFF > +#define ACCDET_EINT0_CUR_DEB_MASK_SFT (0x7FFF << 0) > +#define ACCDET_EINT1_CUR_DEB_ADDR \ > + MT6359_ACCDET_CON33 > +#define ACCDET_EINT1_CUR_DEB_SFT 0 > +#define ACCDET_EINT1_CUR_DEB_MASK 0x7FFF > +#define ACCDET_EINT1_CUR_DEB_MASK_SFT (0x7FFF << 0) > +#define ACCDET_EINT0_INVERTER_CUR_DEB_ADDR \ > + MT6359_ACCDET_CON34 > +#define ACCDET_EINT0_INVERTER_CUR_DEB_SFT 0 > +#define ACCDET_EINT0_INVERTER_CUR_DEB_MASK 0x7FFF > +#define ACCDET_EINT0_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0) > +#define ACCDET_EINT1_INVERTER_CUR_DEB_ADDR \ > + MT6359_ACCDET_CON35 > +#define ACCDET_EINT1_INVERTER_CUR_DEB_SFT 0 > +#define ACCDET_EINT1_INVERTER_CUR_DEB_MASK 0x7FFF > +#define ACCDET_EINT1_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0) > +#define AD_AUDACCDETCMPOB_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_AUDACCDETCMPOB_MON_SFT 0 > +#define AD_AUDACCDETCMPOB_MON_MASK 0x1 > +#define AD_AUDACCDETCMPOB_MON_MASK_SFT (0x1 << 0) > +#define AD_AUDACCDETCMPOA_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_AUDACCDETCMPOA_MON_SFT 1 > +#define AD_AUDACCDETCMPOA_MON_MASK 0x1 > +#define AD_AUDACCDETCMPOA_MON_MASK_SFT (0x1 << 1) > +#define AD_EINT0CMPMOUT_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_EINT0CMPMOUT_MON_SFT 2 > +#define AD_EINT0CMPMOUT_MON_MASK 0x1 > +#define AD_EINT0CMPMOUT_MON_MASK_SFT (0x1 << 2) > +#define AD_EINT0CMPOUT_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_EINT0CMPOUT_MON_SFT 3 > +#define AD_EINT0CMPOUT_MON_MASK 0x1 > +#define AD_EINT0CMPOUT_MON_MASK_SFT (0x1 << 3) > +#define AD_EINT0INVOUT_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_EINT0INVOUT_MON_SFT 4 > +#define AD_EINT0INVOUT_MON_MASK 0x1 > +#define AD_EINT0INVOUT_MON_MASK_SFT (0x1 << 4) > +#define AD_EINT1CMPMOUT_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_EINT1CMPMOUT_MON_SFT 5 > +#define AD_EINT1CMPMOUT_MON_MASK 0x1 > +#define AD_EINT1CMPMOUT_MON_MASK_SFT (0x1 << 5) > +#define AD_EINT1CMPOUT_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_EINT1CMPOUT_MON_SFT 6 > +#define AD_EINT1CMPOUT_MON_MASK 0x1 > +#define AD_EINT1CMPOUT_MON_MASK_SFT (0x1 << 6) > +#define AD_EINT1INVOUT_MON_ADDR \ > + MT6359_ACCDET_CON36 > +#define AD_EINT1INVOUT_MON_SFT 7 > +#define AD_EINT1INVOUT_MON_MASK 0x1 > +#define AD_EINT1INVOUT_MON_MASK_SFT (0x1 << 7) > +#define DA_AUDACCDETCMPCLK_MON_ADDR \ > + MT6359_ACCDET_CON37 > +#define DA_AUDACCDETCMPCLK_MON_SFT 0 > +#define DA_AUDACCDETCMPCLK_MON_MASK 0x1 > +#define DA_AUDACCDETCMPCLK_MON_MASK_SFT (0x1 << 0) > +#define DA_AUDACCDETVTHCLK_MON_ADDR \ > + MT6359_ACCDET_CON37 > +#define DA_AUDACCDETVTHCLK_MON_SFT 1 > +#define DA_AUDACCDETVTHCLK_MON_MASK 0x1 > +#define DA_AUDACCDETVTHCLK_MON_MASK_SFT (0x1 << 1) > +#define DA_AUDACCDETMBIASCLK_MON_ADDR \ > + MT6359_ACCDET_CON37 > +#define DA_AUDACCDETMBIASCLK_MON_SFT 2 > +#define DA_AUDACCDETMBIASCLK_MON_MASK 0x1 > +#define DA_AUDACCDETMBIASCLK_MON_MASK_SFT (0x1 << 2) > +#define DA_AUDACCDETAUXADCSWCTRL_MON_ADDR \ > + MT6359_ACCDET_CON37 > +#define DA_AUDACCDETAUXADCSWCTRL_MON_SFT 3 > +#define DA_AUDACCDETAUXADCSWCTRL_MON_MASK 0x1 > +#define DA_AUDACCDETAUXADCSWCTRL_MON_MASK_SFT (0x1 << 3) > +#define DA_EINT0CTURBO_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT0CTURBO_MON_SFT 0 > +#define DA_EINT0CTURBO_MON_MASK 0x1 > +#define DA_EINT0CTURBO_MON_MASK_SFT (0x1 << 0) > +#define DA_EINT0CMPMEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT0CMPMEN_MON_SFT 1 > +#define DA_EINT0CMPMEN_MON_MASK 0x1 > +#define DA_EINT0CMPMEN_MON_MASK_SFT (0x1 << 1) > +#define DA_EINT0CMPEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT0CMPEN_MON_SFT 2 > +#define DA_EINT0CMPEN_MON_MASK 0x1 > +#define DA_EINT0CMPEN_MON_MASK_SFT (0x1 << 2) > +#define DA_EINT0INVEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT0INVEN_MON_SFT 3 > +#define DA_EINT0INVEN_MON_MASK 0x1 > +#define DA_EINT0INVEN_MON_MASK_SFT (0x1 << 3) > +#define DA_EINT0CEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT0CEN_MON_SFT 4 > +#define DA_EINT0CEN_MON_MASK 0x1 > +#define DA_EINT0CEN_MON_MASK_SFT (0x1 << 4) > +#define DA_EINT0EN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT0EN_MON_SFT 5 > +#define DA_EINT0EN_MON_MASK 0x1 > +#define DA_EINT0EN_MON_MASK_SFT (0x1 << 5) > +#define DA_EINT1CTURBO_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT1CTURBO_MON_SFT 8 > +#define DA_EINT1CTURBO_MON_MASK 0x1 > +#define DA_EINT1CTURBO_MON_MASK_SFT (0x1 << 8) > +#define DA_EINT1CMPMEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT1CMPMEN_MON_SFT 9 > +#define DA_EINT1CMPMEN_MON_MASK 0x1 > +#define DA_EINT1CMPMEN_MON_MASK_SFT (0x1 << 9) > +#define DA_EINT1CMPEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT1CMPEN_MON_SFT 10 > +#define DA_EINT1CMPEN_MON_MASK 0x1 > +#define DA_EINT1CMPEN_MON_MASK_SFT (0x1 << 10) > +#define DA_EINT1INVEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT1INVEN_MON_SFT 11 > +#define DA_EINT1INVEN_MON_MASK 0x1 > +#define DA_EINT1INVEN_MON_MASK_SFT (0x1 << 11) > +#define DA_EINT1CEN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT1CEN_MON_SFT 12 > +#define DA_EINT1CEN_MON_MASK 0x1 > +#define DA_EINT1CEN_MON_MASK_SFT (0x1 << 12) > +#define DA_EINT1EN_MON_ADDR \ > + MT6359_ACCDET_CON38 > +#define DA_EINT1EN_MON_SFT 13 > +#define DA_EINT1EN_MON_MASK 0x1 > +#define DA_EINT1EN_MON_MASK_SFT (0x1 << 13) > +#define ACCDET_EINT0_M_PLUG_IN_COUNT_ADDR \ > + MT6359_ACCDET_CON39 > +#define ACCDET_EINT0_M_PLUG_IN_COUNT_SFT 0 > +#define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK 0x7 > +#define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 0) > +#define ACCDET_EINT1_M_PLUG_IN_COUNT_ADDR \ > + MT6359_ACCDET_CON39 > +#define ACCDET_EINT1_M_PLUG_IN_COUNT_SFT 4 > +#define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK 0x7 > +#define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 4) > +#define ACCDET_MON_FLAG_EN_ADDR \ > + MT6359_ACCDET_CON40 > +#define ACCDET_MON_FLAG_EN_SFT 0 > +#define ACCDET_MON_FLAG_EN_MASK 0x1 > +#define ACCDET_MON_FLAG_EN_MASK_SFT (0x1 << 0) > +#define ACCDET_MON_FLAG_SEL_ADDR \ > + MT6359_ACCDET_CON40 > +#define ACCDET_MON_FLAG_SEL_SFT 4 > +#define ACCDET_MON_FLAG_SEL_MASK 0xF > +#define ACCDET_MON_FLAG_SEL_MASK_SFT (0xF << 4) > + > +#define RG_AUDPWDBMICBIAS0_ADDR \ > + MT6359_AUDENC_ANA_CON15 > +#define RG_AUDPWDBMICBIAS0_SFT 0 > +#define RG_AUDPWDBMICBIAS0_MASK 0x1 > +#define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0) > +#define RG_AUDPREAMPLON_ADDR \ > + MT6359_AUDENC_ANA_CON0 > +#define RG_AUDPREAMPLON_SFT 0 > +#define RG_AUDPREAMPLON_MASK 0x1 > +#define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0) > +#define RG_CLKSQ_EN_ADDR \ > + MT6359_AUDENC_ANA_CON23 > +#define RG_CLKSQ_EN_SFT 0 > +#define RG_CLKSQ_EN_MASK 0x1 > +#define RG_CLKSQ_EN_MASK_SFT (0x1 << 0) > +#define RG_RTC32K_CK_PDN_ADDR \ > + MT6359_TOP_CKPDN_CON0 > +#define RG_RTC32K_CK_PDN_SFT 15 > +#define RG_RTC32K_CK_PDN_MASK 0x1 > +#define RG_RTC32K_CK_PDN_MASK_SFT (0x1 << 15) > +#define RG_HPLOUTPUTSTBENH_VAUDP32_ADDR \ > + MT6359_AUDDEC_ANA_CON2 > +#define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 0 > +#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x7 > +#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0) > +#define AUXADC_RQST_CH5_ADDR \ > + MT6359_AUXADC_RQST0 > +#define AUXADC_RQST_CH5_SFT 5 > +#define AUXADC_RQST_CH5_MASK 0x1 > +#define AUXADC_RQST_CH5_MASK_SFT (0x1 << 5) > +#define RG_LDO_VUSB_HW0_OP_EN_ADDR \ > + MT6359_LDO_VUSB_OP_EN > +#define RG_LDO_VUSB_HW0_OP_EN_SFT 0 > +#define RG_LDO_VUSB_HW0_OP_EN_MASK 0x1 > +#define RG_LDO_VUSB_HW0_OP_EN_MASK_SFT (0x1 << 0) > +#define RG_HPROUTPUTSTBENH_VAUDP32_ADDR \ > + MT6359_AUDDEC_ANA_CON2 > +#define RG_HPROUTPUTSTBENH_VAUDP32_SFT 4 > +#define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x7 > +#define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4) > +#define RG_NCP_PDDIS_EN_ADDR \ > + MT6359_AFE_NCP_CFG2 > +#define RG_NCP_PDDIS_EN_SFT 0 > +#define RG_NCP_PDDIS_EN_MASK 0x1 > +#define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0) > +#define RG_SCK32K_CK_PDN_ADDR \ > + MT6359_TOP_CKPDN_CON0 > +#define RG_SCK32K_CK_PDN_SFT 0 > +#define RG_SCK32K_CK_PDN_MASK 0x1 > +#define RG_SCK32K_CK_PDN_MASK_SFT (0x1 << 0) > /* AUDENC_ANA_CON18: */ > -#define RG_ACCDET_MODE_ANA11_MODE1 (0x000f) > -#define RG_ACCDET_MODE_ANA11_MODE2 (0x008f) > -#define RG_ACCDET_MODE_ANA11_MODE6 (0x008f) > +#define RG_ACCDET_MODE_ANA11_MODE1 (0x000F) > +#define RG_ACCDET_MODE_ANA11_MODE2 (0x008F) > +#define RG_ACCDET_MODE_ANA11_MODE6 (0x008F) > > /* AUXADC_ADC5: Auxadc CH5 read data */ > #define AUXADC_DATA_RDY_CH5 BIT(15) > #define AUXADC_DATA_PROCEED_CH5 BIT(15) > -#define AUXADC_DATA_MASK (0x0fff) > +#define AUXADC_DATA_MASK (0x0FFF) > > /* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */ > #define AUXADC_RQST_CH5_SET BIT(5) > /* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */ > #define AUXADC_RQST_CH5_CLR BIT(5) > > -#define ACCDET_CALI_MASK0 (0xff) > -#define ACCDET_CALI_MASK1 (0xff << 8) > -#define ACCDET_CALI_MASK2 (0xff) > -#define ACCDET_CALI_MASK3 (0xff << 8) > -#define ACCDET_CALI_MASK4 (0xff) > - > -#define ACCDET_EINT1_IRQ_CLR_B11 BIT(PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT) > -#define ACCDET_EINT0_IRQ_CLR_B10 BIT(PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT) > -#define ACCDET_EINT_IRQ_CLR_B10_11 (0x03 << \ > - PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT) > -#define ACCDET_IRQ_CLR_B8 BIT(PMIC_ACCDET_IRQ_CLR_SHIFT) > +#define ACCDET_CALI_MASK0 (0xFF) > +#define ACCDET_CALI_MASK1 (0xFF << 8) > +#define ACCDET_CALI_MASK2 (0xFF) > +#define ACCDET_CALI_MASK3 (0xFF << 8) > +#define ACCDET_CALI_MASK4 (0xFF) > > -#define ACCDET_EINT1_IRQ_B3 BIT(PMIC_ACCDET_EINT1_IRQ_SHIFT) > -#define ACCDET_EINT0_IRQ_B2 BIT(PMIC_ACCDET_EINT0_IRQ_SHIFT) > -#define ACCDET_EINT_IRQ_B2_B3 (0x03 << PMIC_ACCDET_EINT0_IRQ_SHIFT) > -#define ACCDET_IRQ_B0 BIT(PMIC_ACCDET_IRQ_SHIFT) > +#define ACCDET_EINT_IRQ_B2_B3 (0x03 << ACCDET_EINT0_IRQ_SFT) > > /* ACCDET_CON25: RO, accdet FSM state,etc.*/ > -#define ACCDET_STATE_MEM_IN_OFFSET (PMIC_ACCDET_MEM_IN_SHIFT) > -#define ACCDET_STATE_AB_MASK (0x03) > -#define ACCDET_STATE_AB_00 (0x00) > -#define ACCDET_STATE_AB_01 (0x01) > -#define ACCDET_STATE_AB_10 (0x02) > -#define ACCDET_STATE_AB_11 (0x03) > +#define ACCDET_STATE_MEM_IN_OFFSET (ACCDET_MEM_IN_SFT) > +#define ACCDET_STATE_AB_MASK (0x03) > +#define ACCDET_STATE_AB_00 (0x00) > +#define ACCDET_STATE_AB_01 (0x01) > +#define ACCDET_STATE_AB_10 (0x02) > +#define ACCDET_STATE_AB_11 (0x03) > > /* ACCDET_CON19 */ > -#define ACCDET_EINT0_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \ > - (1 << PMIC_ACCDET_EINT0_EN_STABLE_SHIFT) | \ > - (1 << PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT) | \ > - (1 << PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT)) > - > -#define ACCDET_EINT1_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \ > - (1 << PMIC_ACCDET_EINT1_EN_STABLE_SHIFT) | \ > - (1 << PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT) | \ > - (1 << PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT)) > +#define ACCDET_EINT0_STABLE_VAL ((ACCDET_DA_STABLE_SFT) | \ > + (ACCDET_EINT0_EN_STABLE_SFT) | \ > + (ACCDET_EINT0_CMPEN_STABLE_SFT) | \ > + (ACCDET_EINT0_CEN_STABLE_SFT)) > + > +#define ACCDET_EINT1_STABLE_VAL ((ACCDET_DA_STABLE_SFT) | \ > + (ACCDET_EINT1_EN_STABLE_SFT) | \ > + (ACCDET_EINT1_CMPEN_STABLE_SFT) | \ > + (ACCDET_EINT1_CEN_STABLE_SFT)) > > /* The following are used for mt6359.c */ > /* MT6359_DCXO_CW12 */ > -- > 1.8.1.1.dirty >

1 0

Re: [PATCH 1/2] dt-bindings: mediatek: mt6359: add ASoC mt6359 accdet document
by Argus Lin 03 Feb '21

03 Feb '21

Dear maintainers: Can you reply to me if any opinion? thanks B.R. Argus On Wed, 2021-01-06 at 20:19 +0800, Argus Lin wrote: > This patch adds MediaTek MT6359 accdet document. > > Signed-off-by: Argus Lin <argus.lin(a)mediatek.com> > --- > .../devicetree/bindings/sound/mt6359-accdet.yaml | 142 +++++++++++++++++++++ > 1 file changed, 142 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/mt6359-accdet.yaml > > diff --git a/Documentation/devicetree/bindings/sound/mt6359-accdet.yaml b/Documentation/devicetree/bindings/sound/mt6359-accdet.yaml > new file mode 100644 > index 0000000..fde0d29 > --- /dev/null > +++ b/Documentation/devicetree/bindings/sound/mt6359-accdet.yaml > @@ -0,0 +1,142 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/sound/mt6359-accdet.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek Technologies Inc. MT6359 ASoC accdet driver bindings > + > +maintainers: > + - Chipeng Chang <chipeng.chang(a)mediatek.com> > + > +description: | > + This binding describes the Mediatek Technologies MT6359 ASoC > + accdet driver. > + > +properties: > + compatible: > + enum: > + - mediatek,mt6359-accdet > + - mediatek,pmic-accdet > + > + accdet-name: > + maxItems: 1 > + description: named as "mt6359-accdet" for snd_soc_card_jack. > + > + accdet-mic-vol: > + maxItems: 1 > + description: | > + accdet micbias1 voltage. > + > + enum: > + - 0x00 # 1.7v - micbias1 volage is 1.7v. > + - 0x01 # 1.8v - micbias1 volage is 1.8v. > + - 0x02 # 1.9v - micbias1 volage is 1.9v. > + - 0x03 # 2.0v - micbias1 volage is 2.0v. > + - 0x04 # 2.1v - micbias1 volage is 2.1v. > + - 0x05 # 2.5v - micbias1 volage is 2.5v. > + - 0x06 # 2.6v - micbias1 volage is 2.6v. > + - 0x07 # 2.7v - micbias1 volage is 2.7v. > + - 0x08 # 2.8v - micbias1 volage is 2.8v. > + - 0x09 # 2.85v - micbias1 volage is 2.85v. > + > + accdet-plugout-debounce: > + maxItems: 1 > + description: For using ap gpio eint only, it is sw debounce time. > + > + accdet-mic-mode: > + maxItems: 1 > + description: | > + value as 1, 2, 6 to indicate ACC/DCC mode. default is DCC mode 2. > + > + enum: > + - 0x01 # ACC - ACC mode. > + - 0x02 # DCC - low cost without in bias. > + - 0x06 # DCC - low cost with in bias. > + > + eint_use_ext_res: > + maxItems: 1 > + description: select HP_EINT pull up resistance, default 0 use internal resistance. > + > + headset-mode-setting: > + maxItems: 15 > + description: | > + headset-mode-setting : Indicates customized pwm, debounce setting > + accdet pwm_width, pwm_thresh, fall_delay, rise_delay > + debounce0, debounce1, debounce3, debounce4 > + eint pwm_width, eint pwm_thresh > + eint deb(debounce0, debounce1, debounce2, debounce3), inv_debounce. > + > + headset-use-ap-eint: > + maxItems: 1 > + description: indicates to use ap gpio. > + > + headset-eint-num: > + maxItems: 1 > + description: | > + incicates pmic eint usage. > + > + enum: > + - 0x0 # PMIC_EINT0 - use pmic eint0 to trigger plug interrupt. > + - 0x1 # PMIC_EINT1 - use pmic eint1 to trigger plug interrupt. > + - 0x2 # PMIC_BI_EINT - use pmic eint0/1 to trigger plug interrupt. > + > + headset-eint-trig-mode: > + maxItems: 1 > + description: | > + incicates pmic eint trigger mode. > + > + enum: > + - 0x0 # PMIC_GPIO - use pmic gpio to detect plug status by setting polarity to high or low. > + - 0x1 # PMIC_INVERTER - use pmic inverter to detect plug status. > + > + headset-key-mode: > + maxItems: 1 > + description: | > + incicates key mode type. > + > + enum: > + - 0x0 # THREE_KEY - support 3-key key mode. > + - 0x1 # FOUR_KEY - support 4-key key mode. > + - 0x1 # TRI_KEY_CDD - support 3-key google CDD key mode. > + > + headset-three-key-threshold: > + maxItems: 4 > + description: | > + 3 key device detection threshold: 0--MD_MAX--UP_MAX--DW_MAX. > + > + headset-three-key-threshold-CDD: > + maxItems: 4 > + description: | > + 3 key CDD device detection threshold: 0--MD_MAX--UP_MAX--DW_MAX. > + > + headset-four-key-threshold: > + maxItems: 4 > + description: | > + 4 key device detection threshold: 0--MD_MAX--VOICE_MAX--UP_MAX--DW_MAX. > + > +additionalProperties: false > + > +examples: > + - | > + accdet: accdet { > + compatible = "mediatek,mt6359-accdet"; > + accdet-name = "mt6359-accdet"; > + accdet-mic-vol = <8>; > + accdet-plugout-debounce = <1>; > + accdet-mic-mode = <2>; > + eint_use_ext_res = <0>; > + headset-mode-setting = <0x500 0x500 1 0x1f0 > + 0x800 0x800 0x20 0x44 > + 0x4 0x1 > + 0x5 0x3 0x3 0x5 0xe>; > + headset-use-ap-eint = <0>; > + headset-eint-num = <0>; > + headset-eint-trig-mode = <1>; > + headset-key-mode = <0>; > + headset-three-key-threshold = <0 80 220 400>; > + headset-three-key-threshold-CDD = <0 121 192 600>; > + headset-four-key-threshold = <0 58 121 192 400>; > + status = "okay"; > + }; > +... > -- > 1.8.1.1.dirty >

1 0

Oops with "ALSA: jack: implement software jack injection via debugfs"
by Chris Wilson 03 Feb '21

03 Feb '21

commit 2d670ea2bd53 ("ALSA: jack: implement software jack injection via debugfs") is causing issues for our CI as we see a use-after-free on module unload (on all machines): https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9715/fi-skl-6700k2/pstore0-… <4> [241.294412] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b6c13: 0000 [#1] PREEMPT SMP PTI <4> [241.294424] CPU: 7 PID: 5820 Comm: i915_module_loa Not tainted 5.11.0-rc6-CI-CI_DRM_9715+ #1 <4> [241.294432] Hardware name: System manufacturer System Product Name/Z170 PRO GAMING, BIOS 0802 09/02/2015 <4> [241.294438] RIP: 0010:__lock_acquire+0x61a/0x25a0 <4> [241.294444] Code: 00 00 83 f8 2f 0f 87 a0 00 00 00 3b 05 97 61 07 02 c7 44 24 18 01 00 00 00 0f 86 d4 00 00 00 89 05 83 61 07 02 e9 c9 00 00 00 <48> 81 3f 80 14 d9 82 41 bc 00 00 00 00 45 0f 45 e0 83 fe 01 0f 87 <4> [241.294451] RSP: 0018:ffffc90000e77b78 EFLAGS: 00010002 <4> [241.294454] RAX: 0000000000000000 RBX: ffff888137d50040 RCX: 0000000000000000 <4> [241.294458] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 6b6b6b6b6b6b6c13 <4> [241.294461] RBP: 0000000000000001 R08: 0000000000000001 R09: 0000000000000000 <4> [241.294464] R10: 0000000000000001 R11: 00000000d2337ff6 R12: 0000000000000001 <4> [241.294467] R13: 0000000000000000 R14: 0000000000000000 R15: 6b6b6b6b6b6b6c13 <4> [241.294470] FS: 00007f0e00616e40(0000) GS:ffff88824db80000(0000) knlGS:0000000000000000 <4> [241.294474] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [241.294477] CR2: 00007f375bda2cb0 CR3: 000000010ddd6001 CR4: 00000000003706e0 <4> [241.294480] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 <4> [241.294483] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 <4> [241.294486] Call Trace: <4> [241.294489] lock_acquire+0xd0/0x3b0 <4> [241.294493] ? lockref_get+0x9/0x20 <4> [241.294498] _raw_spin_lock+0x2a/0x40 <4> [241.294501] ? lockref_get+0x9/0x20 <4> [241.294505] lockref_get+0x9/0x20 <4> [241.294508] simple_recursive_removal+0x31/0x2a0 <4> [241.294511] ? debugfs_remove+0x50/0x50 <4> [241.294515] ? _raw_spin_unlock+0x24/0x40 <4> [241.294519] debugfs_remove+0x3b/0x50 <4> [241.294522] snd_card_free+0x76/0xa0 <4> [241.294527] pci_device_remove+0x36/0xb0 <4> [241.294531] device_release_driver_internal+0xf2/0x1d0 <4> [241.294820] unbind_store+0xeb/0x120 <4> [241.294824] kernfs_fop_write_iter+0x11d/0x1c0 <4> [241.294828] new_sync_write+0x11d/0x1b0 <4> [241.294832] vfs_write+0x260/0x390 <4> [241.294835] ksys_write+0x5a/0xd0 <4> [241.294838] do_syscall_64+0x33/0x80 <4> [241.294842] entry_SYSCALL_64_after_hwframe+0x44/0xa9 <4> [241.294845] RIP: 0033:0x7f0dffd80281 <4> [241.294848] Code: c3 0f 1f 84 00 00 00 00 00 48 8b 05 59 8d 20 00 c3 0f 1f 84 00 00 00 00 00 8b 05 8a d1 20 00 85 c0 75 16 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 57 f3 c3 0f 1f 44 00 00 41 54 55 49 89 d4 53 <4> [241.294855] RSP: 002b:00007fff5a3a9c88 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 <4> [241.294860] RAX: ffffffffffffffda RBX: 0000555708dc2cf0 RCX: 00007f0dffd80281 <4> [241.294863] RDX: 000000000000000c RSI: 0000555708dc2ddb RDI: 0000000000000006 <4> [241.294866] RBP: 00007fff5a3a9d20 R08: 0000555708dc2ddb R09: 000000000000000c <4> [241.294869] R10: 00000000fffffff4 R11: 0000000000000246 R12: 00007fff5a3a9c90 <4> [241.294872] R13: 00007f0e00007b18 R14: 0000000000000006 R15: 0000555708dc2ddb <4> [241.294877] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio i915 mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core e1000e mei_me snd_pcm mei ptp pps_core prime_numbers [last unloaded: vgem] <4> [241.294901] ---[ end trace 98e116c0344cf275 ]--- <4> [242.399691] RIP: 0010:__lock_acquire+0x61a/0x25a0 <4> [242.399698] Code: 00 00 83 f8 2f 0f 87 a0 00 00 00 3b 05 97 61 07 02 c7 44 24 18 01 00 00 00 0f 86 d4 00 00 00 89 05 83 61 07 02 e9 c9 00 00 00 <48> 81 3f 80 14 d9 82 41 bc 00 00 00 00 45 0f 45 e0 83 fe 01 0f 87 <4> [242.399705] RSP: 0018:ffffc90000e77b78 EFLAGS: 00010002 <4> [242.399709] RAX: 0000000000000000 RBX: ffff888137d50040 RCX: 0000000000000000 <4> [242.399713] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 6b6b6b6b6b6b6c13 <4> [242.399716] RBP: 0000000000000001 R08: 0000000000000001 R09: 0000000000000000 <4> [242.399719] R10: 0000000000000001 R11: 00000000d2337ff6 R12: 0000000000000001 <4> [242.399722] R13: 0000000000000000 R14: 0000000000000000 R15: 6b6b6b6b6b6b6c13 <4> [242.399725] FS: 00007f0e00616e40(0000) GS:ffff88824db80000(0000) knlGS:0000000000000000 <4> [242.399729] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [242.399732] CR2: 00007f375bda2cb0 CR3: 000000010ddd6001 CR4: 00000000003706e0 <4> [242.399735] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 <4> [242.399739] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 <6> [242.399742] note: i915_module_loa[5820] exited with preempt_count 1 <3> [242.399745] BUG: sleeping function called from invalid context at include/linux/percpu-rwsem.h:49 <3> [242.399749] in_atomic(): 0, irqs_disabled(): 1, non_block: 0, pid: 5820, name: i915_module_loa <4> [242.399753] INFO: lockdep is turned off. <4> [242.399755] irq event stamp: 125679 <4> [242.399757] hardirqs last enabled at (125679): [<ffffffff81a9e36f>] _raw_spin_unlock_irq+0x1f/0x40 <4> [242.399763] hardirqs last disabled at (125678): [<ffffffff81a9e151>] _raw_spin_lock_irq+0x41/0x50 <4> [242.399768] softirqs last enabled at (125054): [<ffffffff81e00342>] __do_softirq+0x342/0x48e <4> [242.399773] softirqs last disabled at (124021): [<ffffffff81c00f52>] asm_call_irq_on_stack+0x12/0x20 <4> [242.399779] CPU: 7 PID: 5820 Comm: i915_module_loa Tainted: G D 5.11.0-rc6-CI-CI_DRM_9715+ #1 <4> [242.399784] Hardware name: System manufacturer System Product Name/Z170 PRO GAMING, BIOS 0802 09/02/2015 <4> [242.399787] Call Trace: <4> [242.399790] dump_stack+0x77/0x97 <4> [242.399794] ___might_sleep.cold.120+0xf2/0x106 <4> [242.399799] exit_signals+0x2b/0x350 <4> [242.399803] do_exit+0xc8/0xcb0 <4> [242.399807] ? ksys_write+0x5a/0xd0 <4> [242.399811] rewind_stack_do_exit+0x17/0x17 <4> [242.399814] RIP: 0033:0x7f0dffd80281 <4> [242.399817] Code: c3 0f 1f 84 00 00 00 00 00 48 8b 05 59 8d 20 00 c3 0f 1f 84 00 00 00 00 00 8b 05 8a d1 20 00 85 c0 75 16 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 57 f3 c3 0f 1f 44 00 00 41 54 55 49 89 d4 53 <4> [242.399824] RSP: 002b:00007fff5a3a9c88 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 <4> [242.399828] RAX: ffffffffffffffda RBX: 0000555708dc2cf0 RCX: 00007f0dffd80281 <4> [242.399831] RDX: 000000000000000c RSI: 0000555708dc2ddb RDI: 0000000000000006 <4> [242.399834] RBP: 00007fff5a3a9d20 R08: 0000555708dc2ddb R09: 000000000000000c <4> [242.399838] R10: 00000000fffffff4 R11: 0000000000000246 R12: 00007fff5a3a9c90 <4> [242.399841] R13: 00007f0e00007b18 R14: 0000000000000006 R15: 0000555708dc2ddb Created at 2021-02-02 17:16:13

3 4

[PATCH] ALSA: core: Fix the debugfs removal at snd_card_free()
by Takashi Iwai 02 Feb '21

02 Feb '21

The commit 2d670ea2bd53 ("ALSA: jack: implement software jack injection via debugfs") introduced a debugfs root for each sound card object. The debugfs entry gets removed at the card removal, too, but it turned out that debugfs_remove() is called at a wrong place; it's after the card object gets freed, hence it leads to use-after-free. Fix it by moving the debugfs_remove() at the right place, the destructor of the card device. Fixes: 2d670ea2bd53 ("ALSA: jack: implement software jack injection via debugfs") Reported-and-tested-by: Chris Wilson <chris(a)chris-wilson.co.uk> Link: https://lore.kernel.org/r/161228343605.1150.8862281636043446562@build.alpor… Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/core/init.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/sound/core/init.c b/sound/core/init.c index d4e78b176793..84b573e9c1f9 100644 --- a/sound/core/init.c +++ b/sound/core/init.c @@ -487,6 +487,10 @@ static int snd_card_do_free(struct snd_card *card) dev_warn(card->dev, "unable to free card info\n"); /* Not fatal error */ } +#ifdef CONFIG_SND_DEBUG + debugfs_remove(card->debugfs_root); + card->debugfs_root = NULL; +#endif if (card->release_completion) complete(card->release_completion); kfree(card); @@ -537,11 +541,6 @@ int snd_card_free(struct snd_card *card) /* wait, until all devices are ready for the free operation */ wait_for_completion(&released); -#ifdef CONFIG_SND_DEBUG - debugfs_remove(card->debugfs_root); - card->debugfs_root = NULL; -#endif - return 0; } EXPORT_SYMBOL(snd_card_free); -- 2.26.2

1 0

Nux Mighty Plug USB - no clock source
by Peter Allen 02 Feb '21

02 Feb '21

I have a NUX Mighty Plug guitar effects which has a USB Audio interface. Unfortunately it doesn't work in Linux, and I'd love to fix it. It gets registered with Alsa, except it ends up without any valid sample rates (by the look of it due to a buggy clock source descriptor). This is on Ubuntu-Studio 20.04 LTS _Focal Fossa with kernel 5.4.0-62-lowlatency on a HP Omen 15 with i5-7300HQ I don't know what I'm doing (but did a little module development rather a long time ago in the 2.2 days :-)) Help is greatly appreciated. When plugged in I get: [12476.413792] usb 1-1: New USB device found, idVendor=1fc9, idProduct=8260, bcdDevice= 1.00 [12476.413797] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [12476.413800] usb 1-1: Product: MIGHTY PLUG USB [12476.413804] usb 1-1: Manufacturer: NUX [12476.413807] usb 1-1: SerialNumber: 2007151403 [12476.444988] usb 1-1: __uac_clock_find_source(): selector reported illegal value, id 40, ret 0 [12476.444992] usb 1-1: parse_audio_format_rates_v2v3(): unable to find clock source (clock -22) [12476.445413] usb 1-1: __uac_clock_find_source(): selector reported illegal value, id 40, ret 0 [12476.445479] usb 1-1: __uac_clock_find_source(): selector reported illegal value, id 40, ret 0 [12476.447095] usb 1-1: __uac_clock_find_source(): selector reported illegal value, id 40, ret 0 [12476.447098] usb 1-1: parse_audio_format_rates_v2v3(): unable to find clock source (clock -22) [12476.447459] usb 1-1: __uac_clock_find_source(): selector reported illegal value, id 40, ret 0 [12476.447684] usb 1-1: __uac_clock_find_source(): selector reported illegal value, id 40, ret 0 [12476.450397] usbcore: registered new interface driver snd-usb-audio ===== /proc/asound/cards give ====== 0 [PCH ]: HDA-Intel - HDA Intel PCH HDA Intel PCH at 0xb4428000 irq 134 1 [NVidia ]: HDA-Intel - HDA NVidia HDA NVidia at 0xb4000000 irq 17 2 [USB ]: USB-Audio - MIGHTY PLUG USB NUX MIGHTY PLUG USB at usb-0000:00:14.0-1, high speed ==== /proc/asound/stream======== NUX MIGHTY PLUG USB at usb-0000:00:14.0-1, high speed : USB Audio Playback: Status: Stop Interface 1 Altset 1 Format: S32_LE Channels: 2 Endpoint: 1 OUT (ASYNC) Rates: Data packet interval: 1000 us Bits: 24 Capture: Status: Stop Interface 2 Altset 1 Format: S32_LE Channels: 2 Endpoint: 2 IN (ASYNC) Rates: Data packet interval: 1000 us Bits: 24 ======== arecord =========== arecord -D "hw:2" -c 2 -f s24 -r 44100 -d 2 -v test.wav Recording WAVE 'xxxc' : Signed 24 bit Little Endian, Rate 44100 Hz, Stereo arecord: set_params:1314: Broken configuration for this PCM: no configuration available ========lsusb -v ========== iSerial 2 200901010001 bNumConfigurations 1 Bus 001 Device 005: ID 1fc9:8260 NXP Semiconductors MIGHTY PLUG USB Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x1fc9 NXP Semiconductors idProduct 0x8260 bcdDevice 1.00 iManufacturer 1 NUX iProduct 2 MIGHTY PLUG USB iSerial 3 2007151403 bNumConfigurations 1 Configuration Descriptor: bLength 9 bDescriptorType 2 wTotalLength 0x013e bNumInterfaces 4 bConfigurationValue 1 iConfiguration 0 bmAttributes 0xc0 Self Powered MaxPower 2mA Interface Association: bLength 8 bDescriptorType 11 bFirstInterface 0 bInterfaceCount 3 bFunctionClass 1 Audio bFunctionSubClass 0 bFunctionProtocol 32 iFunction 0 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 0 bAlternateSetting 0 bNumEndpoints 0 bInterfaceClass 1 Audio bInterfaceSubClass 1 Control Device bInterfaceProtocol 32 iInterface 0 AudioControl Interface Descriptor: bLength 9 bDescriptorType 36 bDescriptorSubtype 1 (HEADER) bcdADC 2.00 bCategory 8 wTotalLength 0x0065 bmControls 0x00 AudioControl Interface Descriptor: bLength 8 bDescriptorType 36 bDescriptorSubtype 10 (CLOCK_SOURCE) bClockID 41 bmAttributes 3 Internal programmable clock bmControls 0x07 Clock Frequency Control (read/write) Clock Validity Control (read-only) bAssocTerminal 0 iClockSource 0 AudioControl Interface Descriptor: bLength 8 bDescriptorType 36 bDescriptorSubtype 11 (CLOCK_SELECTOR) bClockID 40 bNrInPins 1 baCSourceID(0) 41 bmControls 0x03 Clock Selector Control (read/write) iClockSelector 0 AudioControl Interface Descriptor: bLength 17 bDescriptorType 36 bDescriptorSubtype 2 (INPUT_TERMINAL) bTerminalID 2 wTerminalType 0x0101 USB Streaming bAssocTerminal 0 bCSourceID 40 bNrChannels 2 bmChannelConfig 0x00000000 iChannelNames 0 bmControls 0x0000 iTerminal 0 AudioControl Interface Descriptor: bLength 18 bDescriptorType 36 bDescriptorSubtype 6 (FEATURE_UNIT) bUnitID 10 bSourceID 2 bmaControls(0) 0x0000000f Mute Control (read/write) Volume Control (read/write) bmaControls(1) 0x0000000f Mute Control (read/write) Volume Control (read/write) bmaControls(2) 0x0000000f Mute Control (read/write) Volume Control (read/write) iFeature 0 AudioControl Interface Descriptor: bLength 12 bDescriptorType 36 bDescriptorSubtype 3 (OUTPUT_TERMINAL) bTerminalID 20 wTerminalType 0x0301 Speaker bAssocTerminal 0 bSourceID 10 bCSourceID 40 bmControls 0x0000 iTerminal 0 AudioControl Interface Descriptor: bLength 17 bDescriptorType 36 bDescriptorSubtype 2 (INPUT_TERMINAL) bTerminalID 1 wTerminalType 0x0201 Microphone bAssocTerminal 0 bCSourceID 40 bNrChannels 2 bmChannelConfig 0x00000000 iChannelNames 0 bmControls 0x0000 iTerminal 0 AudioControl Interface Descriptor: bLength 12 bDescriptorType 36 bDescriptorSubtype 3 (OUTPUT_TERMINAL) bTerminalID 22 wTerminalType 0x0101 USB Streaming bAssocTerminal 0 bSourceID 2 bCSourceID 40 bmControls 0x0000 iTerminal 0 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 1 bAlternateSetting 0 bNumEndpoints 0 bInterfaceClass 1 Audio bInterfaceSubClass 2 Streaming bInterfaceProtocol 32 iInterface 0 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 1 bAlternateSetting 1 bNumEndpoints 2 bInterfaceClass 1 Audio bInterfaceSubClass 2 Streaming bInterfaceProtocol 32 iInterface 0 AudioStreaming Interface Descriptor: bLength 16 bDescriptorType 36 bDescriptorSubtype 1 (AS_GENERAL) bTerminalLink 2 bmControls 0x00 bFormatType 1 bmFormats 0x00000001 PCM bNrChannels 2 bmChannelConfig 0x00000000 iChannelNames 0 AudioStreaming Interface Descriptor: bLength 6 bDescriptorType 36 bDescriptorSubtype 2 (FORMAT_TYPE) bFormatType 1 (FORMAT_TYPE_I) bSubslotSize 4 bBitResolution 24 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x01 EP 1 OUT bmAttributes 5 Transfer Type Isochronous Synch Type Asynchronous Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 4 AudioStreaming Endpoint Descriptor: bLength 8 bDescriptorType 37 bDescriptorSubtype 1 (EP_GENERAL) bmAttributes 0x00 bmControls 0x00 bLockDelayUnits 0 Undefined wLockDelay 0x0000 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x81 EP 1 IN bmAttributes 17 Transfer Type Isochronous Synch Type None Usage Type Feedback wMaxPacketSize 0x0004 1x 4 bytes bInterval 4 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 2 bAlternateSetting 0 bNumEndpoints 0 bInterfaceClass 1 Audio bInterfaceSubClass 2 Streaming bInterfaceProtocol 32 iInterface 0 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 2 bAlternateSetting 1 bNumEndpoints 1 bInterfaceClass 1 Audio bInterfaceSubClass 2 Streaming bInterfaceProtocol 32 iInterface 0 AudioStreaming Interface Descriptor: bLength 16 bDescriptorType 36 bDescriptorSubtype 1 (AS_GENERAL) bTerminalLink 22 bmControls 0x00 bFormatType 1 bmFormats 0x00000001 PCM bNrChannels 2 bmChannelConfig 0x00000000 iChannelNames 0 AudioStreaming Interface Descriptor: bLength 6 bDescriptorType 36 bDescriptorSubtype 2 (FORMAT_TYPE) bFormatType 1 (FORMAT_TYPE_I) bSubslotSize 4 bBitResolution 24 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x82 EP 2 IN bmAttributes 5 Transfer Type Isochronous Synch Type Asynchronous Usage Type Data wMaxPacketSize 0x0400 1x 1024 bytes bInterval 4 AudioStreaming Endpoint Descriptor: bLength 8 bDescriptorType 37 bDescriptorSubtype 1 (EP_GENERAL) bmAttributes 0x00 bmControls 0x00 bLockDelayUnits 0 Undefined wLockDelay 0x0000 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 3 bAlternateSetting 0 bNumEndpoints 2 bInterfaceClass 1 Audio bInterfaceSubClass 3 MIDI Streaming bInterfaceProtocol 0 iInterface 4 MIGHTY PLUG USB MIDI MIDIStreaming Interface Descriptor: bLength 7 bDescriptorType 36 bDescriptorSubtype 1 (HEADER) bcdADC 1.00 wTotalLength 0x0041 MIDIStreaming Interface Descriptor: bLength 6 bDescriptorType 36 bDescriptorSubtype 2 (MIDI_IN_JACK) bJackType 1 Embedded bJackID 1 iJack 0 MIDIStreaming Interface Descriptor: bLength 6 bDescriptorType 36 bDescriptorSubtype 2 (MIDI_IN_JACK) bJackType 2 External bJackID 2 iJack 0 MIDIStreaming Interface Descriptor: bLength 9 bDescriptorType 36 bDescriptorSubtype 3 (MIDI_OUT_JACK) bJackType 1 Embedded bJackID 3 bNrInputPins 1 baSourceID( 0) 2 BaSourcePin( 0) 1 iJack 0 MIDIStreaming Interface Descriptor: bLength 9 bDescriptorType 36 bDescriptorSubtype 3 (MIDI_OUT_JACK) bJackType 2 External bJackID 4 bNrInputPins 1 baSourceID( 0) 1 BaSourcePin( 0) 1 iJack 0 Endpoint Descriptor: bLength 9 bDescriptorType 5 bEndpointAddress 0x04 EP 4 OUT bmAttributes 2 Transfer Type Bulk Synch Type None Usage Type Data wMaxPacketSize 0x0100 1x 256 bytes bInterval 0 bRefresh 0 bSynchAddress 0 MIDIStreaming Endpoint Descriptor: bLength 5 bDescriptorType 37 bDescriptorSubtype 1 (GENERAL) bNumEmbMIDIJack 1 baAssocJackID( 0) 1 Endpoint Descriptor: bLength 9 bDescriptorType 5 bEndpointAddress 0x83 EP 3 IN bmAttributes 2 Transfer Type Bulk Synch Type None Usage Type Data wMaxPacketSize 0x0100 1x 256 bytes bInterval 0 bRefresh 0 bSynchAddress 0 MIDIStreaming Endpoint Descriptor: bLength 5 bDescriptorType 37 bDescriptorSubtype 1 (GENERAL) bNumEmbMIDIJack 1 baAssocJackID( 0) 3 Device Qualifier (for other device speed): bLength 10 bDescriptorType 6 bcdUSB 2.00 bDeviceClass 0 bDeviceSubClass 0 bDeviceProtocol 0 bMaxPacketSize0 64 bNumConfigurations 1 can't get debug descriptor: Resource temporarily unavailable Device Status: 0x0001 Self Powered Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 9 Hub bDeviceSubClass 0 bDeviceProtocol 1 Single TT bMaxPacketSize0 64 idVendor 0x1d6b Linux Foundation idProduct 0x0002 2.0 root hub bcdDevice 5.04 iManufacturer 3 Linux 5.4.0-58-lowlatency xhci-hcd iProduct 2 xHCI Host Controller iSerial 1 0000:00:14.0 bNumConfigurations 1 Configuration Descriptor: bLength 9 bDescriptorType 2 wTotalLength 0x0019 bNumInterfaces 1 bConfigurationValue 1 iConfiguration 0 bmAttributes 0xe0 Self Powered Remote Wakeup MaxPower 0mA Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 0 bAlternateSetting 0 bNumEndpoints 1 bInterfaceClass 9 Hub bInterfaceSubClass 0 bInterfaceProtocol 0 Full speed (or root) hub iInterface 0 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x81 EP 1 IN bmAttributes 3 Transfer Type Interrupt Synch Type None Usage Type Data wMaxPacketSize 0x0004 1x 4 bytes bInterval 12 Hub Descriptor: bLength 13 bDescriptorType 41 nNbrPorts 16 wHubCharacteristic 0x000a No power switching (usb 1.0) Per-port overcurrent protection TT think time 8 FS bits bPwrOn2PwrGood 10 * 2 milli seconds bHubContrCurrent 0 milli Ampere DeviceRemovable 0x90 0x01 0x00 PortPwrCtrlMask 0xff 0xff 0xff Hub Port Status: Port 1: 0000.0503 highspeed power enable connect Port 2: 0000.0100 power Port 3: 0000.0100 power Port 4: 0000.0503 highspeed power enable connect Port 5: 0000.0100 power Port 6: 0000.0100 power Port 7: 0000.0103 power enable connect Port 8: 0000.0100 power Port 9: 0000.0100 power Port 10: 0000.0100 power Port 11: 0000.0100 power Port 12: 0000.0100 power Port 13: 0000.0100 power Port 14: 0000.0100 power Port 15: 0000.0100 power Port 16: 0000.0100 power can't get device qualifier: Resource temporarily unavailable can't get debug descriptor: Resource temporarily unavailable Device Status: 0x0001 Self Powered

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[PATCH v2 0/2] ALSA: usb-audio: Add Pioneer DJM-450 support
by Olivia Mackintosh 02 Feb '21

02 Feb '21

Re-roll of this patchset to fix the following: 1. Missing 'Signed-of-by:' line 2. Spaces around operators 3. Test that I'm threading submissions correctly Apologies for the clumsiness on my part. Olivia Olivia Mackintosh (2): ALSA: usb-audio: Add DJM450 to Pioneer format quirk ALSA: usb-audio: Add DJM-450 to the quirks table sound/usb/quirks-table.h | 57 ++++++++++++++++++++++++++++++++++++++++ sound/usb/quirks.c | 20 ++++++++++++++ 2 files changed, 77 insertions(+) -- 2.30.0

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