October 2021 - Alsa-devel - mailman.alsa-project.org

[PATCH v4 0/3] Update SoundWire RX and TX cgcr register control
by Srinivasa Rao Mandadapu 27 Oct '21

27 Oct '21

This patch series is to add v1.6.0 compatable name for qcom soundwire driver and to update soundwire RX and TX cgcr register control. Changes Since V3: -- Add v1.6.0 compatable name and soundwire data structure. -- Change macro define name properly. -- Update bindings for new property. -- Change commit message description. -- Change signedoff by sequence. Changes since v2: -- Update error check after ioremap. Changes since v1: -- Add const name to mask value. Srinivasa Rao Mandadapu (3): ASoC: qcom: soundwire: Disable soundwire rxtx cgcr hardware control dt-bindings: soundwire: qcom: Add bindings for RX and TX cgcr register control soundwire: qcom: Add compatible name for v1.6.0 .../devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ drivers/soundwire/qcom.c | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+) -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

3 7

[PATCH] ASoC: amd: acp: fix Kconfig dependencies
by Arnd Bergmann 27 Oct '21

27 Oct '21

From: Arnd Bergmann <arnd(a)arndb.de> The CONFIG_SND_SOC_AMD_MACH_COMMON has some dependencies that are not checked by the symbols that select it: WARNING: unmet direct dependencies detected for SND_SOC_AMD_MACH_COMMON Depends on [n]: SOUND [=y] && !UML && SND [=m] && SND_SOC [=m] && X86 && PCI [=y] && I2C [=n] Selected by [m]: - SND_SOC_AMD_LEGACY_MACH [=m] && SOUND [=y] && !UML && SND [=m] && SND_SOC [=m] - SND_SOC_AMD_SOF_MACH [=m] && SOUND [=y] && !UML && SND [=m] && SND_SOC [=m] WARNING: unmet direct dependencies detected for SND_SOC_AMD_MACH_COMMON Depends on [n]: SOUND [=m] && !UML && SND [=m] && SND_SOC [=m] && X86 && PCI [=n] && I2C [=m] Selected by [m]: - SND_SOC_AMD_LEGACY_MACH [=m] && SOUND [=m] && !UML && SND [=m] && SND_SOC [=m] Make this more consistent by adding the same checks everywhere. Fixes: 9d8a7be88b33 ("ASoC: amd: acp: Add legacy sound card support for Chrome audio") Fixes: 9f84940f5004 ("ASoC: amd: acp: Add SOF audio support on Chrome board") Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- sound/soc/amd/acp/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/soc/amd/acp/Kconfig b/sound/soc/amd/acp/Kconfig index 98ec18791d35..737135357ee2 100644 --- a/sound/soc/amd/acp/Kconfig +++ b/sound/soc/amd/acp/Kconfig @@ -28,24 +28,26 @@ config SND_AMD_ASOC_RENOIR config SND_SOC_AMD_MACH_COMMON tristate + depends on X86 && PCI && I2C select CLK_FIXED_FCH select SND_SOC_RT5682_I2C select SND_SOC_DMIC select SND_SOC_RT1019 select SND_SOC_MAX98357A select SND_SOC_RT5682S - depends on X86 && PCI && I2C help This option enables common Machine driver module for ACP. config SND_SOC_AMD_LEGACY_MACH tristate "AMD Legacy Machine Driver Support" + depends on X86 && PCI && I2C select SND_SOC_AMD_MACH_COMMON help This option enables legacy sound card support for ACP audio. config SND_SOC_AMD_SOF_MACH tristate "AMD SOF Machine Driver Support" + depends on X86 && PCI && I2C select SND_SOC_AMD_MACH_COMMON help This option enables SOF sound card support for ACP audio. -- 2.29.2

2 1

[PATCH v2 1/1] ASoC: meson: t9015: Add missing AVDD-supply property
by Alexander Stein 27 Oct '21

27 Oct '21

Fixes the schema check warning "audio-controller@32000: 'AVDD-supply' do not match any of the regexes: 'pinctrl-[0-9]+'" Fixes: 5c36abcd2621 ("ASoC: meson: add t9015 internal codec binding documentation") Reviewed-by: Jerome Brunet <jbrunet(a)baylibre.com> Signed-off-by: Alexander Stein <alexander.stein(a)mailbox.org> --- Thanks all for their review. Here is v2 with the following changes: v2: * Separated from other meson DT patches (2/4 - 4/4) * Adjusted recipients * Added missing property in example * Adjusted commit message subject * Added Reviewed-by: Jerome Brunet tag Documentation/devicetree/bindings/sound/amlogic,t9015.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/amlogic,t9015.yaml b/Documentation/devicetree/bindings/sound/amlogic,t9015.yaml index c7613ea728d4..db7b04da0b39 100644 --- a/Documentation/devicetree/bindings/sound/amlogic,t9015.yaml +++ b/Documentation/devicetree/bindings/sound/amlogic,t9015.yaml @@ -34,6 +34,10 @@ properties: resets: maxItems: 1 + AVDD-supply: + description: + Analogue power supply. + required: - "#sound-dai-cells" - compatible @@ -41,6 +45,7 @@ required: - clocks - clock-names - resets + - AVDD-supply additionalProperties: false @@ -56,4 +61,5 @@ examples: clocks = <&clkc CLKID_AUDIO_CODEC>; clock-names = "pclk"; resets = <&reset RESET_AUDIO_CODEC>; + AVDD-supply = <&vddao_1v8>; }; -- 2.33.1

2 1

[PATCH] ASoC: Intel: soc-acpi: add entry for ESSX8336 on JSL
by Bard Liao 27 Oct '21

27 Oct '21

From: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> We have configurations for this codec on APL, GLK and TGL, somehow the information that some designs rely on JasperLake was not shared. BugLink: https://github.com/thesofproject/linux/issues/3210 Fixes: 790049fb6623 ('ASoC: Intel: soc-acpi: apl/glk/tgl: add entry for devices based on ES8336 codec') Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen(a)intel.com> Signed-off-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> --- sound/soc/intel/common/soc-acpi-intel-jsl-match.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sound/soc/intel/common/soc-acpi-intel-jsl-match.c b/sound/soc/intel/common/soc-acpi-intel-jsl-match.c index 20fd9dcc74af..e7d22e397299 100644 --- a/sound/soc/intel/common/soc-acpi-intel-jsl-match.c +++ b/sound/soc/intel/common/soc-acpi-intel-jsl-match.c @@ -105,6 +105,12 @@ struct snd_soc_acpi_mach snd_soc_acpi_intel_jsl_machines[] = { .quirk_data = &mx98360a_spk, .sof_tplg_filename = "sof-jsl-rt5682-mx98360a.tplg", }, + { + .id = "ESSX8336", + .drv_name = "sof-essx8336", + .sof_fw_filename = "sof-jsl.ri", + .sof_tplg_filename = "sof-jsl-es8336.tplg", + }, {}, }; EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_jsl_machines); -- 2.17.1

2 1

[RESEND,v6 1/2] ASoC: dt-bindings: max98520: add initial bindings
by George Song 27 Oct '21

27 Oct '21

add initial bindings for max98520 audio amplifier Signed-off-by: George Song <george.song(a)maximintegrated.com> Reviewed-by: Rob Herring <robh(a)kernel.org> --- .../bindings/sound/maxim,max98520.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/maxim,max98520.yaml diff --git a/Documentation/devicetree/bindings/sound/maxim,max98520.yaml b/Documentation/devicetree/bindings/sound/maxim,max98520.yaml new file mode 100644 index 000000000000..b6509cb2c8e0 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/maxim,max98520.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/maxim,max98520.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX98520 Speaker Amplifier Driver + +maintainers: + - George Song <george.song(a)maximintegrated.com> + +properties: + compatible: + const: maxim,max98520 + + reg: + maxItems: 1 + description: I2C address of the device. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + max98520: amplifier@38 { + compatible = "maxim,max98520"; + reg = <0x38>; + }; + }; + -- 2.25.1

2 2

[PATCH -next] ASoC: amd: acp: Fix return value check in acp_machine_select()
by Yang Yingliang 27 Oct '21

27 Oct '21

In case of error, platform_device_register_data() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Reported-by: Hulk Robot <hulkci(a)huawei.com> Fixes: e646b51f5dd5 ("ASoC: amd: acp: Add callback for machine driver on ACP") Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- sound/soc/amd/acp/acp-platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/amd/acp/acp-platform.c b/sound/soc/amd/acp/acp-platform.c index 75003d0a41e3..65a809e2c29f 100644 --- a/sound/soc/amd/acp/acp-platform.c +++ b/sound/soc/amd/acp/acp-platform.c @@ -81,7 +81,7 @@ int acp_machine_select(struct acp_dev_data *adata) adata->mach_dev = platform_device_register_data(adata->dev, mach->drv_name, PLATFORM_DEVID_NONE, mach, size); - if (!adata->mach_dev) + if (IS_ERR(adata->mach_dev)) dev_warn(adata->dev, "Unable to register Machine device\n"); return 0; -- 2.25.1

2 1

[PATCH 0/8] ASoC: minor cleanup of warnings
by Pierre-Louis Bossart 27 Oct '21

27 Oct '21

Sparse, make W=1 and cppcheck all report minor warnings. The only functional change is in patch7 where the error code is now returned to the caller. Pierre-Louis Bossart (8): ASoC: topology: handle endianness warning ASoC: rt5682s: use 'static' qualifier ASoC: nau8821: fix kernel-doc ASoC: nau8821: clarify out-of-bounds check ASoC: mediatek: remove unnecessary initialization ASoC: mediatek: mt8195: rename shadowed array ASoC: mediatek: mt8195: fix return value ASoC: rockchip: i2s_tdm: improve return value handling sound/soc/codecs/nau8821.c | 6 ++++-- sound/soc/codecs/rt5682s.c | 6 +++--- sound/soc/mediatek/common/mtk-afe-fe-dai.c | 2 +- sound/soc/mediatek/mt8195/mt8195-afe-pcm.c | 4 ++-- sound/soc/mediatek/mt8195/mt8195-dai-etdm.c | 2 +- sound/soc/rockchip/rockchip_i2s_tdm.c | 2 +- sound/soc/soc-topology.c | 2 +- 7 files changed, 13 insertions(+), 11 deletions(-) -- 2.25.1

2 9

[PATCH] ASoC: rt5682-i2c: Use devm_clk_get_optional for optional clock
by AngeloGioacchino Del Regno 27 Oct '21

27 Oct '21

The mclk clock is optional, but it's currently using devm_clk_get: simplify the handling by using devm_clk_get_optional instead. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno(a)collabora.com> --- sound/soc/codecs/rt5682-i2c.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/sound/soc/codecs/rt5682-i2c.c b/sound/soc/codecs/rt5682-i2c.c index a30e42932cf7..983347b65127 100644 --- a/sound/soc/codecs/rt5682-i2c.c +++ b/sound/soc/codecs/rt5682-i2c.c @@ -280,14 +280,9 @@ static int rt5682_i2c_probe(struct i2c_client *i2c, #ifdef CONFIG_COMMON_CLK /* Check if MCLK provided */ - rt5682->mclk = devm_clk_get(&i2c->dev, "mclk"); - if (IS_ERR(rt5682->mclk)) { - if (PTR_ERR(rt5682->mclk) != -ENOENT) { - ret = PTR_ERR(rt5682->mclk); - return ret; - } - rt5682->mclk = NULL; - } + rt5682->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); + if (IS_ERR(rt5682->mclk)) + return PTR_ERR(rt5682->mclk); /* Register CCF DAI clock control */ ret = rt5682_register_dai_clks(rt5682); -- 2.33.0

2 1

[PATCH 0/3] Make genaral and simple for new sof machine driver
by David Lin 27 Oct '21

27 Oct '21

The series of features will make general and simple for new sof machine driver. David Lin (3): ASoC: nau8825: add set_jack coponment support ASoC: nau8825: add disable jack detection support ASoC: nau8825: add clock management for power saving sound/soc/codecs/nau8825.c | 49 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-)

4 9

[PATCH 0/2] Make genaral and simple for new sof machine driver
by David Lin 27 Oct '21

27 Oct '21

The series of features will make general and simple for new sof machine driver. David Lin (2): ASoC: nau8825: add set_jack coponment support ASoC: nau8825: add clock management for power saving sound/soc/codecs/nau8825.c | 48 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-)

3 7

dt-bindings: treewide: Update @st.com email address to @foss.st.com
by patrice.chotard＠foss.st.com 27 Oct '21

27 Oct '21

From: Patrice Chotard <patrice.chotard(a)foss.st.com> Not all @st.com email address are concerned, only people who have a specific @foss.st.com email will see their entry updated. For some people, who left the company, remove their email. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- Documentation/devicetree/bindings/arm/sti.yaml | 2 +- Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml | 4 ++-- .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 4 ++-- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 +- Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 2 +- Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml | 2 +- Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml | 2 +- Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 2 +- .../devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml | 2 +- .../devicetree/bindings/display/panel/orisetech,otm8009a.yaml | 2 +- .../devicetree/bindings/display/panel/raydium,rm68200.yaml | 2 +- Documentation/devicetree/bindings/display/st,stm32-dsi.yaml | 4 ++-- Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 4 ++-- Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 2 +- Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 2 +- Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml | 2 +- .../devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml | 3 +-- Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 2 +- .../devicetree/bindings/iio/adc/sigma-delta-modulator.yaml | 2 +- Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 2 +- .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++-- Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 2 +- .../bindings/interrupt-controller/st,stm32-exti.yaml | 4 ++-- Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml | 4 ++-- Documentation/devicetree/bindings/media/st,stm32-cec.yaml | 3 +-- Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 2 +- .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 2 +- Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 2 +- Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 3 +-- Documentation/devicetree/bindings/mfd/st,stmfx.yaml | 2 +- Documentation/devicetree/bindings/mfd/st,stpmic1.yaml | 2 +- Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml | 2 +- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 +- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++-- Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml | 2 +- Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 2 +- .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 2 +- .../devicetree/bindings/regulator/st,stm32-booster.yaml | 2 +- .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 2 +- .../devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml | 2 +- .../devicetree/bindings/remoteproc/st,stm32-rproc.yaml | 4 ++-- Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 2 +- Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml | 2 +- Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 2 +- Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml | 2 +- Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 2 +- Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 2 +- Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml | 2 +- Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++-- Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++-- .../devicetree/bindings/thermal/st,stm32-thermal.yaml | 2 +- Documentation/devicetree/bindings/timer/st,stm32-timer.yaml | 3 ++- Documentation/devicetree/bindings/usb/st,stusb160x.yaml | 2 +- Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml | 4 ++-- 54 files changed, 67 insertions(+), 69 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml index b1f28d16d3fb..a41cd8764885 100644 --- a/Documentation/devicetree/bindings/arm/sti.yaml +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST STi Platforms Device Tree Bindings maintainers: - - Patrice Chotard <patrice.chotard(a)st.com> + - Patrice Chotard <patrice.chotard(a)foss.st.com> properties: $nodename: diff --git a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml index 8e711bd202fd..ecb28e90fd11 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml @@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 ML-AHB interconnect bindings maintainers: - - Fabien Dessenne <fabien.dessenne(a)st.com> - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> description: | These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 149afb5df5af..6f846d69c5e1 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 Platforms System Controller bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> - - Christophe Roullier <christophe.roullier(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> + - Christophe Roullier <christophe.roullier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 9a77ab74be99..e33fbb62b430 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Platforms Device Tree Bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> properties: $nodename: diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index 8b1ecb2ecdd5..a0ae4867ed27 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Reset Clock Controller Binding maintainers: - - Gabriel Fernandez <gabriel.fernandez(a)st.com> + - Gabriel Fernandez <gabriel.fernandez(a)foss.st.com> description: | The RCC IP is both a reset and a clock controller. diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml index cee624c14f07..b72e4858f9aa 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRC bindings maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml index a4574552502a..ed23bf94a8e0 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRYP bindings maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index 6dd658f0912c..10ba94792d95 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 HASH bindings maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml index 3c3e51af154b..11fd68a70dca 100644 --- a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare MIPI DSI host controller maintainers: - - Philippe CORNU <philippe.cornu(a)st.com> + - Philippe CORNU <philippe.cornu(a)foss.st.com> description: | This document defines device tree properties for the Synopsys DesignWare MIPI diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml index 4b6dda6dbc0f..17cbd0ad32bf 100644 --- a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml +++ b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode) maintainers: - - Philippe CORNU <philippe.cornu(a)st.com> + - Philippe CORNU <philippe.cornu(a)foss.st.com> description: | The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml index 39477793d289..e8ce2315631a 100644 --- a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel maintainers: - - Philippe CORNU <philippe.cornu(a)st.com> + - Philippe CORNU <philippe.cornu(a)foss.st.com> description: | The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml index ed310bbe3afe..ce1ef93cce93 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DSI host controller maintainers: - - Philippe Cornu <philippe.cornu(a)st.com> - - Yannick Fertre <yannick.fertre(a)st.com> + - Philippe Cornu <philippe.cornu(a)foss.st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> description: The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index 4ae3d75492d3..01e2da23790b 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 lcd-tft display controller maintainers: - - Philippe Cornu <philippe.cornu(a)st.com> - - Yannick Fertre <yannick.fertre(a)st.com> + - Philippe Cornu <philippe.cornu(a)foss.st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 4bf676fd25dc..55faab6a468e 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -50,7 +50,7 @@ description: | maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> allOf: - $ref: "dma-controller.yaml#" diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index c8d2b51d8410..f751796531c9 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> allOf: - $ref: "dma-router.yaml#" diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml index c30be840be1c..87b4afd2cf62 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml @@ -50,7 +50,7 @@ description: | if no HW ack signal is used by the MDMA client maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> allOf: - $ref: "dma-controller.yaml#" diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml index 47cf9c8d97e9..b18c616035a8 100644 --- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Hardware Spinlock bindings maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> - - Fabien Dessenne <fabien.dessenne(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> properties: "#hwlock-cells": diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index d747f4990ad8..c07289a643d8 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: I2C controller embedded in STMicroelectronics STM32 I2C platform maintainers: - - Pierre-Yves MORDRET <pierre-yves.mordret(a)st.com> + - Pierre-Yves MORDRET <pierre-yves.mordret(a)foss.st.com> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml index a390343d0c2a..2287697f1f61 100644 --- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml +++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Device-Tree bindings for sigma delta modulator maintainers: - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index a58334c3bb76..a055c78cc047 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -19,7 +19,7 @@ description: | Each STM32 ADC block can have up to 3 ADC instances. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 733351dee252..7c260f209687 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DFSDM ADC device driver maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> - - Olivier Moysan <olivier.moysan(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: | STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 393f7005941a..6adeda4087fc 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -15,7 +15,7 @@ description: | current. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml index 6d3e68eb2e8b..d19c881b4abc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32 External Interrupt Controller Device Tree Bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> - - Ludovic Barre <ludovic.barre(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> + - Ludovic Barre <ludovic.barre(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml index b15da9ba90b2..8eb4bf52ea27 100644 --- a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml @@ -13,8 +13,8 @@ description: channels (N) can be read from a dedicated register. maintainers: - - Fabien Dessenne <fabien.dessenne(a)st.com> - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml index d75019c093a4..77144cc6f7db 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CEC bindings maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> - - Yannick Fertre <yannick.fertre(a)st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 41e1d0cd80e5..9c1262a276b5 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) binding maintainers: - - Hugues Fruchet <hugues.fruchet(a)st.com> + - Hugues Fruchet <hugues.fruchet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index cba74205846a..6b516d3895af 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -19,7 +19,7 @@ description: | Select. The FMC2 performs only one access at a time to an external device. maintainers: - - Christophe Kerello <christophe.kerello(a)st.com> + - Christophe Kerello <christophe.kerello(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 8bcea8dd7d90..ec7f0190f46e 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -17,7 +17,7 @@ description: | - simple counter from IN1 input signal. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index dace35362a7a..10b330d42901 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -17,8 +17,7 @@ description: | programmable prescaler. maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stmfx.yaml b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml index 19e9afb385ac..b2a4e4aa7ff6 100644 --- a/Documentation/devicetree/bindings/mfd/st,stmfx.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml @@ -12,7 +12,7 @@ description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C through VDD) and resistive touchscreen controller. maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml index 305123e74a58..426658ad81d4 100644 --- a/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml @@ -9,7 +9,7 @@ title: STMicroelectonics STPMIC1 Power Management IC bindings description: STMicroelectronics STPMIC1 Power Management IC maintainers: - - pascal Paillet <p.paillet(a)st.com> + - pascal Paillet <p.paillet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml index 29c5ef24ac6a..eab8ea3da1fa 100644 --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings maintainers: - - Christophe Kerello <christophe.kerello(a)st.com> + - Christophe Kerello <christophe.kerello(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 42689b7d03a2..a5c55127cc44 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare MAC Device Tree Bindings maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> - Giuseppe Cavallaro <peppe.cavallaro(a)st.com> - Jose Abreu <joabreu(a)synopsys.com> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index d3f05d5934d5..577f4e284425 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -8,8 +8,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 / MCU DWMAC glue layer controller maintainers: - - Alexandre Torgue <alexandre.torgue(a)st.com> - - Christophe Roullier <christophe.roullier(a)st.com> + - Alexandre Torgue <alexandre.torgue(a)foss.st.com> + - Christophe Roullier <christophe.roullier(a)foss.st.com> description: This file documents platform glue layer for stmmac. diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml index 0b80ce22a2f8..a48c8fa56bce 100644 --- a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml +++ b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml @@ -13,7 +13,7 @@ description: | internal vref (VREFIN_CAL), unique device ID... maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> allOf: - $ref: "nvmem.yaml#" diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 3329f1d33a4f..7bae8dff3ef6 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -24,7 +24,7 @@ description: |_ UTMI switch_______| OTG controller maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index dfee6d38a701..ac88e01ec430 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32 GPIO and Pin Mux/Config controller maintainers: - - Alexandre TORGUE <alexandre.torgue(a)st.com> + - Alexandre TORGUE <alexandre.torgue(a)foss.st.com> description: | STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml index 9f1c70381b82..df0191b1ceba 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 booster for ADC analog input switches bindings maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> description: | Some STM32 devices embed a 3.3V booster supplied by Vdda, that can be used diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml index 3cd4a254e4cb..836d4156d54c 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -12,7 +12,7 @@ description: | components through the dedicated VREF+ pin. maintainers: - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> allOf: - $ref: "regulator.yaml#" diff --git a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml index e6322bc3e447..bd07b9c81570 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32MP1 PWR voltage regulators maintainers: - - Pascal Paillet <p.paillet(a)st.com> + - Pascal Paillet <p.paillet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 1e6225677e00..b587c97c282b 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -11,8 +11,8 @@ description: boots firmwares on the ST32MP family chipset. maintainers: - - Fabien Dessenne <fabien.dessenne(a)st.com> - - Arnaud Pouliquen <arnaud.pouliquen(a)st.com> + - Fabien Dessenne <fabien.dessenne(a)foss.st.com> + - Arnaud Pouliquen <arnaud.pouliquen(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml index 82bb2e97e889..9a6e4eaf4d3c 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml @@ -11,7 +11,7 @@ description: | IP and is fully separated from other crypto functions. maintainers: - - Lionel Debieve <lionel.debieve(a)st.com> + - Lionel Debieve <lionel.debieve(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml index 5456604b1c14..2359f541b770 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Real Time Clock Bindings maintainers: - - Gabriel Fernandez <gabriel.fernandez(a)st.com> + - Gabriel Fernandez <gabriel.fernandez(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index f50f4ca893a0..333dc42722d2 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# maintainers: - - Erwan Le Ray <erwan.leray(a)st.com> + - Erwan Le Ray <erwan.leray(a)foss.st.com> title: STMicroelectronics STM32 USART bindings diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml index 0d87e2c86a42..963a871e74da 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: CS42L51 audio codec DT bindings maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index 6feb5a09c184..d3966ae04ad0 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 SPI/I2S Controller maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode. diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index f97132400bb6..1538d11ce9a8 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Serial Audio Interface (SAI) maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: The SAI interface (Serial Audio Interface) offers a wide set of audio diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml index b7f7dc452231..837e830c47ac 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 S/PDIF receiver (SPDIFRX) maintainers: - - Olivier Moysan <olivier.moysan(a)st.com> + - Olivier Moysan <olivier.moysan(a)foss.st.com> description: | The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 983c4e54c0be..6ec6f556182f 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings maintainers: - - Christophe Kerello <christophe.kerello(a)st.com> - - Patrice Chotard <patrice.chotard(a)st.com> + - Christophe Kerello <christophe.kerello(a)foss.st.com> + - Patrice Chotard <patrice.chotard(a)foss.st.com> allOf: - $ref: "spi-controller.yaml#" diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 2d9af4c506bb..3d64bed266ac 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -13,8 +13,8 @@ description: | from 4 to 32-bit data size. maintainers: - - Erwan Leray <erwan.leray(a)st.com> - - Fabrice Gasnier <fabrice.gasnier(a)st.com> + - Erwan Leray <erwan.leray(a)foss.st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> allOf: - $ref: "spi-controller.yaml#" diff --git a/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml index c0f59c56003d..bee41cff5142 100644 --- a/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 digital thermal sensor (DTS) binding maintainers: - - David Hernandez Sanchez <david.hernandezsanchez(a)st.com> + - Pascal Paillet <p.paillet(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml index 176aa3c9baf8..937aa8a56366 100644 --- a/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings maintainers: - - Benjamin Gaignard <benjamin.gaignard(a)st.com> + - Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> + - Patrice Chotard <patrice.chotard(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml index 9a51efa9d101..ead1571e0e43 100644 --- a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml +++ b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml @@ -7,7 +7,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STUSB160x Type-C controller bindings maintainers: - - Amelie Delaunay <amelie.delaunay(a)st.com> + - Amelie Delaunay <amelie.delaunay(a)foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml index 481bf91f988a..39736449ba64 100644 --- a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml +++ b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Independent WatchDoG (IWDG) bindings maintainers: - - Yannick Fertre <yannick.fertre(a)st.com> - - Christophe Roullier <christophe.roullier(a)st.com> + - Yannick Fertre <yannick.fertre(a)foss.st.com> + - Christophe Roullier <christophe.roullier(a)foss.st.com> allOf: - $ref: "watchdog.yaml#" -- 2.17.1

5 7

[PATCH 0/3] ALSA: firewire-motu: fix message parser and refine UAPI
by Takashi Sakamoto 27 Oct '21

27 Oct '21

Hi, This patchset is to fix message parser and refine UAPI added in below patchset. https://lore.kernel.org/alsa-devel/20211015080826.34847-1-o-takashi@sakamoc… Current implementation of message parser for register DSP models has a bug to cause invalid memory access in the other type of models. I attempted to fix it in my previous patch[1] but got a comment for simpler solution. The first patch in the patchset is revised version of the previous one. After working for libhinawa(g-i binding)[2], Rust bindings[3], and service program[4] as application of the new features in UAPI, I found that the number of input meters is greater than current structure in UAPI for some models. The second patch is to refine the structure and message parser. I note that the other part of UAPI is pretty good, and the service program now supports control notification in register DSP mdoels as well as command DSP models. After discussion about usage of float type in UAPI, it shall be allowed in some cases. The third patch is to interpret the UAPI for float type in userspace and u32 type in kernel space. [1] https://lore.kernel.org/alsa-devel/20211020042555.40866-1-o-takashi@sakamoc… [2] https://github.com/alsa-project/libhinawa/tree/topic/motu-mixer-ioctl [3] https://github.com/alsa-project/hinawa-rs/tree/topic/v0.5.0 [4] https://github.com/alsa-project/snd-firewire-ctl-services/tree/topic/motu-m… Takashi Sakamoto (3): ALSA: firewire-motu: fix null pointer dereference when polling hwdep character device ALSA: firewire-motu: refine parser for meter information in register DSP models ALSA: firewire-motu: export mete information to userspace as float value include/uapi/sound/firewire.h | 13 +++++++++---- .../motu/motu-command-dsp-message-parser.c | 7 +++++-- sound/firewire/motu/motu-hwdep.c | 16 +++++++++++----- .../motu/motu-register-dsp-message-parser.c | 14 +++++++++----- 4 files changed, 34 insertions(+), 16 deletions(-) -- 2.30.2

1 3

[PATCH] sound: ua101: fix division by zero at probe
by Johan Hovold 27 Oct '21

27 Oct '21

Add the missing endpoint max-packet sanity check to probe() to avoid division by zero in alloc_stream_buffers() in case a malicious device has broken descriptors (or when doing descriptor fuzz testing). Note that USB core will reject URBs submitted for endpoints with zero wMaxPacketSize but that drivers doing packet-size calculations still need to handle this (cf. commit 2548288b4fb0 ("USB: Fix: Don't skip endpoint descriptors with maxpacket=0")). Fixes: 63978ab3e3e9 ("sound: add Edirol UA-101 support") Cc: stable(a)vger.kernel.org # 2.6.34 Signed-off-by: Johan Hovold <johan(a)kernel.org> --- sound/usb/misc/ua101.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/usb/misc/ua101.c b/sound/usb/misc/ua101.c index 5834d1dc317e..4f6b20ed29dd 100644 --- a/sound/usb/misc/ua101.c +++ b/sound/usb/misc/ua101.c @@ -1000,7 +1000,7 @@ static int detect_usb_format(struct ua101 *ua) fmt_playback->bSubframeSize * ua->playback.channels; epd = &ua->intf[INTF_CAPTURE]->altsetting[1].endpoint[0].desc; - if (!usb_endpoint_is_isoc_in(epd)) { + if (!usb_endpoint_is_isoc_in(epd) || usb_endpoint_maxp(epd) == 0) { dev_err(&ua->dev->dev, "invalid capture endpoint\n"); return -ENXIO; } @@ -1008,7 +1008,7 @@ static int detect_usb_format(struct ua101 *ua) ua->capture.max_packet_bytes = usb_endpoint_maxp(epd); epd = &ua->intf[INTF_PLAYBACK]->altsetting[1].endpoint[0].desc; - if (!usb_endpoint_is_isoc_out(epd)) { + if (!usb_endpoint_is_isoc_out(epd) || usb_endpoint_maxp(epd) == 0) { dev_err(&ua->dev->dev, "invalid playback endpoint\n"); return -ENXIO; } -- 2.32.0

2 1

[PATCH 1/2] ALSA SoC MAX98520 dt-bindings : Added device tree binding for max98520 Signed-off-by: George Song <george.song@maximintegrated.com>
by George Song 26 Oct '21

26 Oct '21

From: "george.song" <george.song(a)analog.com> --- .../bindings/sound/maxim,max98520.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/maxim,max98520.yaml diff --git a/Documentation/devicetree/bindings/sound/maxim,max98520.yaml b/Documentation/devicetree/bindings/sound/maxim,max98520.yaml new file mode 100644 index 000000000000..02481428e2ed --- /dev/null +++ b/Documentation/devicetree/bindings/sound/maxim,max98520.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/maxim,max98520.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX98520 Speaker Amplifier Driver + +maintainers: + - Goerge Song <George.song(a)maximintegrated.com> + +properties: + compatible: + const: maxim,max98520 + + reg: + maxItems: 1 + description: I2C address of the device. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + max98520: amplifier@38 { + compatible = "maxim,max98520"; + reg = <0x38>; + }; + }; -- 2.25.1

2 1

[PATCH 0/3] ASoC: amd: acp: Dependency cleanup
by Geert Uytterhoeven 26 Oct '21

26 Oct '21

Hi all, This patch series cleans up the dependencies of the various configuration symbols related to AMD Audio-Coprocessor support. Feel free to squash into a single patch if you prefer that. Thanks! Geert Uytterhoeven (3): ASoC: amd: acp: Wrap AMD Audio ACP components in SND_SOC_AMD_ACP_COMMON ASoC: amd: acp: SND_SOC_AMD_{LEGACY_MACH,SOF_MACH} should depend on X86 && PCI && I2C ASoC: amd: acp: SND_SOC_AMD_ACP_COMMON should depend on X86 && PCI sound/soc/amd/acp/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.25.1 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert(a)linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds

2 4

[PATCH 0/2] ASoC: cs42l42: Fixes to power-down
by Richard Fitzgerald 26 Oct '21

26 Oct '21

Driver probe and remove were inconsistent in what they did to power-down and neither did all steps. In addition to that, neither function prevented the interrupt handler from running during and after power-down. Richard Fitzgerald (2): ASoC: cs42l42: Reset and power-down on remove() and failed probe() ASoC: cs42l42: free_irq() before powering-down on probe() fail sound/soc/codecs/cs42l42.c | 43 +++++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) -- 2.11.0

2 3

[PATCH v11 00/17] ASoC: qcom: Add AudioReach support
by Srinivas Kandagatla 26 Oct '21

26 Oct '21

Hi Mark, This version is a respin of v10 fixing a build error in 12/17 patch. QCOM SoC relevant non-audio patches in this series has been merged into the Qualcomm drivers-for-5.16 tree, as this series depends those patches an immutable tag is available at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/20210927135559.738-6-srinivas.kandagatla(a)linaro.org This patchset adds ASoC driver support to configure signal processing framework ("AudioReach") which is integral part of Qualcomm next generation audio SDK and will be deployed on upcoming Qualcomm chipsets. It makes use of ASoC Topology to load graphs on to the DSP which is then managed by APM (Audio Processing Manager) service to prepare/start/stop. Here is simplified high-level block diagram of AudioReach: ___________________________________________________________ | CPU (Application Processor) | | +---------+ +---------+ +----------+ | | | q6apm | | q6apm | | q6apm | | | | dais | <------> | | <-----> |lpass-dais| | | +---------+ +---------+ +----------+ | | ^ ^ | | | | +---------+ | | +---------+ v +---------->|topology | | | | q6prm | +---------+ | | | | | |<-------->| GPR | +---------+ | | +---------+ +---------+ | | ^ ^ | | | | | | +----------+ | | | | q6prm | | | | |lpass-clks| | | | +----------+ | | |____________________________|______________________________| | | RPMSG (IPC over GLINK) ____________________________|______________________________ | | | | +-----------------------+ | | | | | | v v q6 (Audio DSP) | |+-----+ +----------------------------------+ | || PRM | | APM (Audio Processing Manager) | | |+-----+ | . Graph Management | | | | . Command Handing | | | | . Event Management | | | | ... | | | +----------------------------------+ | | ^ | |____________________________|______________________________| | | LPASS AIF ____________________________|______________________________ | | Audio I/O | | v | | +--------------------------------------------------+ | | | Audio devices | | | | CODEC | HDMI-TX | PCM | SLIMBUS | I2S |MI2S |...| | | | | | | +--------------------------------------------------+ | |___________________________________________________________| AudioReach has constructs of sub-graph, container and modules. Each sub-graph can have N containers and each Container can have N Modules and connections between them can be linear or non-linear. An audio function can be realized with one or many connected sub-graphs. There are also control/event paths between modules that can be wired up while building graph to achieve various control mechanism between modules. These concepts of Sub-Graph, Containers and Modules are represented in ASoC topology. Here is simple I2S graph with a Write Shared Memory and a Volume control module within a single Subgraph (1) with one Container (1) and 5 modules. ____________________________________________________________ | Sub-Graph [1] | | _______________________________________________________ | | | Container [1] | | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]-> [I2S-EP]| | | |_______________________________________________________| | |____________________________________________________________| For now this graph is split into two subgraphs to achieve dpcm like below: ________________________________________________ _________________ | Sub-Graph [1] | | Sub-Graph [2] | | ____________________________________________ | | _____________ | | | Container [1] | | | |Container [2]| | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]| | | | [I2S-EP] | | | |____________________________________________| | | |_____________| | |________________________________________________| |_________________| _________________ | Sub-Graph [3] | | _____________ | | |Container [3]| | | | [DMA-EP] | | | |_____________| | |_________________| This patchset adds very minimal support for AudioReach which includes supporting sub-graphs containing CODEC DMA ports and simple PCM Decoder/Encoder and Logger Modules. Additional capabilities will be built over time to expose features offered by AudioReach. This patchset is Tested on SM8250 SoC based Qualcomm Robotics Platform RB5 and SM9250 MTP with WSA881X Smart Speaker Amplifiers, DMICs connected via VA Macro and WCD938x Codec connected via TX and RX Macro and HDMI audio via I2S. First 10 Patches are mostly reorganization existing Old QDSP Audio Framework code and bindings so that we could reuse them on AudioReach. ASoC topology graphs for DragonBoard RB5 and SM8250 MTP are available at https://git.linaro.org/people/srinivas.kandagatla/audioreach-topology.git/ and Qualcomm AudioReach DSP headers are available at: https://source.codeaurora.org/quic/la/platform/vendor/opensource/arspf-head… Note: There is one false positive warning in this patchset: audioreach.c:80:45: warning: array of flexible structures Thanks, srini Changes since v10: - fix build error during arm64 defconfig build reported by Mark in 12/17 patch for audioreach_tplg_init symbol Srinivas Kandagatla (17): ASoC: dt-bindings: move LPASS dai related bindings out of q6afe ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h ASoC: qdsp6: q6afe-dai: move lpass audio ports to common file ASoC: qdsp6: q6afe-clocks: move audio-clocks to common file ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible ASoC: dt-bindings: add q6apm digital audio stream bindings ASoC: qdsp6: audioreach: add basic pkt alloc support ASoC: qdsp6: audioreach: add q6apm support ASoC: qdsp6: audioreach: add module configuration command helpers ASoC: qdsp6: audioreach: add Kconfig and Makefile ASoC: qdsp6: audioreach: add topology support ASoC: qdsp6: audioreach: add q6apm-dai support ASoC: qdsp6: audioreach: add q6apm lpass dai support ASoC: qdsp6: audioreach: add q6prm support ASoC: qdsp6: audioreach: add support for q6prm-clocks .../devicetree/bindings/sound/qcom,q6afe.txt | 181 --- .../bindings/sound/qcom,q6apm-dai.yaml | 53 + .../sound/qcom,q6dsp-lpass-clocks.yaml | 77 ++ .../sound/qcom,q6dsp-lpass-ports.yaml | 205 +++ include/dt-bindings/sound/qcom,q6afe.h | 203 +-- .../sound/qcom,q6dsp-lpass-ports.h | 208 +++ include/uapi/sound/snd_ar_tokens.h | 208 +++ sound/soc/qcom/Kconfig | 22 + sound/soc/qcom/qdsp6/Makefile | 11 +- sound/soc/qcom/qdsp6/audioreach.c | 1130 +++++++++++++++++ sound/soc/qcom/qdsp6/audioreach.h | 726 +++++++++++ sound/soc/qcom/qdsp6/q6afe-clocks.c | 187 +-- sound/soc/qcom/qdsp6/q6afe-dai.c | 687 +--------- sound/soc/qcom/qdsp6/q6apm-dai.c | 416 ++++++ sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 260 ++++ sound/soc/qcom/qdsp6/q6apm.c | 822 ++++++++++++ sound/soc/qcom/qdsp6/q6apm.h | 152 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c | 186 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h | 30 + sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 627 +++++++++ sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h | 22 + sound/soc/qcom/qdsp6/q6prm-clocks.c | 85 ++ sound/soc/qcom/qdsp6/q6prm.c | 202 +++ sound/soc/qcom/qdsp6/q6prm.h | 78 ++ sound/soc/qcom/qdsp6/topology.c | 1113 ++++++++++++++++ 25 files changed, 6664 insertions(+), 1227 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h create mode 100644 include/uapi/sound/snd_ar_tokens.h create mode 100644 sound/soc/qcom/qdsp6/audioreach.c create mode 100644 sound/soc/qcom/qdsp6/audioreach.h create mode 100644 sound/soc/qcom/qdsp6/q6apm-dai.c create mode 100644 sound/soc/qcom/qdsp6/q6apm-lpass-dais.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.h create mode 100644 sound/soc/qcom/qdsp6/topology.c -- 2.21.0

2 18

[PATCH v4 0/5] Update Lpass digital codec macro drivers
by Srinivasa Rao Mandadapu 26 Oct '21

26 Oct '21

This patch set is to add support for lpass sc7280 based targets. Upadate compatible name and change of bulk clock voting to optional clock voting in digital codecs va, rx, tx macro drivers. Changes Since V3: -- Removed fixes tag. -- Change signedoff by sequence. Changes Since V2: -- Add Tx macro deafults for lpass sc7280 Changes Since V1: -- Removed individual clock voting and used bulk clock optional. -- Removed volatile changes and fixed default values. -- Typo errors. Srinivasa Rao Mandadapu (5): ASoC: qcom: Add compatible names in va,wsa,rx,tx codec drivers for sc7280 ASoC: qcom: dt-bindings: Add compatible names for lpass sc7280 digital codecs ASoC: codecs: tx-macro: Enable tx top soundwire mic clock ASoC: codecs: tx-macro: Update tx default values ASoC: codecs: Change bulk clock voting to optional voting in digital codecs .../bindings/sound/qcom,lpass-rx-macro.yaml | 4 +++- .../bindings/sound/qcom,lpass-tx-macro.yaml | 4 +++- .../bindings/sound/qcom,lpass-va-macro.yaml | 4 +++- .../bindings/sound/qcom,lpass-wsa-macro.yaml | 4 +++- sound/soc/codecs/lpass-rx-macro.c | 3 ++- sound/soc/codecs/lpass-tx-macro.c | 25 +++++++++++++++++++--- sound/soc/codecs/lpass-va-macro.c | 3 ++- sound/soc/codecs/lpass-wsa-macro.c | 1 + 8 files changed, 39 insertions(+), 9 deletions(-) -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

3 7

[RESEND PATCH v10 00/17] ASoC: qcom: Add AudioReach support
by Srinivas Kandagatla 26 Oct '21

26 Oct '21

Hi Mark, Am resending this series as I ended up sending incorrect patches for v10. Sorry for the resend noise. This version is a respin of v9 fixing a build error in 12/17 patch. QCOM SoC relevant non-audio patches in this series has been merged into the Qualcomm drivers-for-5.16 tree, as this series depends those patches an immutable tag is available at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/20210927135559.738-6-srinivas.kandagatla(a)linaro.org This patchset adds ASoC driver support to configure signal processing framework ("AudioReach") which is integral part of Qualcomm next generation audio SDK and will be deployed on upcoming Qualcomm chipsets. It makes use of ASoC Topology to load graphs on to the DSP which is then managed by APM (Audio Processing Manager) service to prepare/start/stop. Here is simplified high-level block diagram of AudioReach: ___________________________________________________________ | CPU (Application Processor) | | +---------+ +---------+ +----------+ | | | q6apm | | q6apm | | q6apm | | | | dais | <------> | | <-----> |lpass-dais| | | +---------+ +---------+ +----------+ | | ^ ^ | | | | +---------+ | | +---------+ v +---------->|topology | | | | q6prm | +---------+ | | | | | |<-------->| GPR | +---------+ | | +---------+ +---------+ | | ^ ^ | | | | | | +----------+ | | | | q6prm | | | | |lpass-clks| | | | +----------+ | | |____________________________|______________________________| | | RPMSG (IPC over GLINK) ____________________________|______________________________ | | | | +-----------------------+ | | | | | | v v q6 (Audio DSP) | |+-----+ +----------------------------------+ | || PRM | | APM (Audio Processing Manager) | | |+-----+ | . Graph Management | | | | . Command Handing | | | | . Event Management | | | | ... | | | +----------------------------------+ | | ^ | |____________________________|______________________________| | | LPASS AIF ____________________________|______________________________ | | Audio I/O | | v | | +--------------------------------------------------+ | | | Audio devices | | | | CODEC | HDMI-TX | PCM | SLIMBUS | I2S |MI2S |...| | | | | | | +--------------------------------------------------+ | |___________________________________________________________| AudioReach has constructs of sub-graph, container and modules. Each sub-graph can have N containers and each Container can have N Modules and connections between them can be linear or non-linear. An audio function can be realized with one or many connected sub-graphs. There are also control/event paths between modules that can be wired up while building graph to achieve various control mechanism between modules. These concepts of Sub-Graph, Containers and Modules are represented in ASoC topology. Here is simple I2S graph with a Write Shared Memory and a Volume control module within a single Subgraph (1) with one Container (1) and 5 modules. ____________________________________________________________ | Sub-Graph [1] | | _______________________________________________________ | | | Container [1] | | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]-> [I2S-EP]| | | |_______________________________________________________| | |____________________________________________________________| For now this graph is split into two subgraphs to achieve dpcm like below: ________________________________________________ _________________ | Sub-Graph [1] | | Sub-Graph [2] | | ____________________________________________ | | _____________ | | | Container [1] | | | |Container [2]| | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]| | | | [I2S-EP] | | | |____________________________________________| | | |_____________| | |________________________________________________| |_________________| _________________ | Sub-Graph [3] | | _____________ | | |Container [3]| | | | [DMA-EP] | | | |_____________| | |_________________| This patchset adds very minimal support for AudioReach which includes supporting sub-graphs containing CODEC DMA ports and simple PCM Decoder/Encoder and Logger Modules. Additional capabilities will be built over time to expose features offered by AudioReach. This patchset is Tested on SM8250 SoC based Qualcomm Robotics Platform RB5 and SM9250 MTP with WSA881X Smart Speaker Amplifiers, DMICs connected via VA Macro and WCD938x Codec connected via TX and RX Macro and HDMI audio via I2S. First 10 Patches are mostly reorganization existing Old QDSP Audio Framework code and bindings so that we could reuse them on AudioReach. ASoC topology graphs for DragonBoard RB5 and SM8250 MTP are available at https://git.linaro.org/people/srinivas.kandagatla/audioreach-topology.git/ and Qualcomm AudioReach DSP headers are available at: https://source.codeaurora.org/quic/la/platform/vendor/opensource/arspf-head… Note: There is one false positive warning in this patchset: audioreach.c:80:45: warning: array of flexible structures Thanks, srini Changes since v9: - fix build error during arm64 defconfig build reported by Mark in 12/17 patch Srinivas Kandagatla (17): ASoC: dt-bindings: move LPASS dai related bindings out of q6afe ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h ASoC: qdsp6: q6afe-dai: move lpass audio ports to common file ASoC: qdsp6: q6afe-clocks: move audio-clocks to common file ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible ASoC: dt-bindings: add q6apm digital audio stream bindings ASoC: qdsp6: audioreach: add basic pkt alloc support ASoC: qdsp6: audioreach: add q6apm support ASoC: qdsp6: audioreach: add module configuration command helpers ASoC: qdsp6: audioreach: add Kconfig and Makefile ASoC: qdsp6: audioreach: add topology support ASoC: qdsp6: audioreach: add q6apm-dai support ASoC: qdsp6: audioreach: add q6apm lpass dai support ASoC: qdsp6: audioreach: add q6prm support ASoC: qdsp6: audioreach: add support for q6prm-clocks .../devicetree/bindings/sound/qcom,q6afe.txt | 181 --- .../bindings/sound/qcom,q6apm-dai.yaml | 53 + .../sound/qcom,q6dsp-lpass-clocks.yaml | 77 ++ .../sound/qcom,q6dsp-lpass-ports.yaml | 205 +++ include/dt-bindings/sound/qcom,q6afe.h | 203 +-- .../sound/qcom,q6dsp-lpass-ports.h | 208 +++ include/uapi/sound/snd_ar_tokens.h | 208 +++ sound/soc/qcom/Kconfig | 22 + sound/soc/qcom/qdsp6/Makefile | 11 +- sound/soc/qcom/qdsp6/audioreach.c | 1130 +++++++++++++++++ sound/soc/qcom/qdsp6/audioreach.h | 726 +++++++++++ sound/soc/qcom/qdsp6/q6afe-clocks.c | 187 +-- sound/soc/qcom/qdsp6/q6afe-dai.c | 687 +--------- sound/soc/qcom/qdsp6/q6apm-dai.c | 416 ++++++ sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 260 ++++ sound/soc/qcom/qdsp6/q6apm.c | 822 ++++++++++++ sound/soc/qcom/qdsp6/q6apm.h | 152 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c | 186 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h | 30 + sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 627 +++++++++ sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h | 22 + sound/soc/qcom/qdsp6/q6prm-clocks.c | 85 ++ sound/soc/qcom/qdsp6/q6prm.c | 202 +++ sound/soc/qcom/qdsp6/q6prm.h | 78 ++ sound/soc/qcom/qdsp6/topology.c | 1113 ++++++++++++++++ 25 files changed, 6664 insertions(+), 1227 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h create mode 100644 include/uapi/sound/snd_ar_tokens.h create mode 100644 sound/soc/qcom/qdsp6/audioreach.c create mode 100644 sound/soc/qcom/qdsp6/audioreach.h create mode 100644 sound/soc/qcom/qdsp6/q6apm-dai.c create mode 100644 sound/soc/qcom/qdsp6/q6apm-lpass-dais.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.h create mode 100644 sound/soc/qcom/qdsp6/topology.c -- 2.21.0

2 22

[PATCH v10 00/17] ASoC: qcom: Add AudioReach support
by Srinivas Kandagatla 26 Oct '21

26 Oct '21

Hi Mark, This version is a respin of v9 fixing a build error in 12/17 patch. QCOM SoC relevant non-audio patches in this series has been merged into the Qualcomm drivers-for-5.16 tree, as this series depends those patches an immutable tag is available at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/20210927135559.738-6-srinivas.kandagatla(a)linaro.org This patchset adds ASoC driver support to configure signal processing framework ("AudioReach") which is integral part of Qualcomm next generation audio SDK and will be deployed on upcoming Qualcomm chipsets. It makes use of ASoC Topology to load graphs on to the DSP which is then managed by APM (Audio Processing Manager) service to prepare/start/stop. Here is simplified high-level block diagram of AudioReach: ___________________________________________________________ | CPU (Application Processor) | | +---------+ +---------+ +----------+ | | | q6apm | | q6apm | | q6apm | | | | dais | <------> | | <-----> |lpass-dais| | | +---------+ +---------+ +----------+ | | ^ ^ | | | | +---------+ | | +---------+ v +---------->|topology | | | | q6prm | +---------+ | | | | | |<-------->| GPR | +---------+ | | +---------+ +---------+ | | ^ ^ | | | | | | +----------+ | | | | q6prm | | | | |lpass-clks| | | | +----------+ | | |____________________________|______________________________| | | RPMSG (IPC over GLINK) ____________________________|______________________________ | | | | +-----------------------+ | | | | | | v v q6 (Audio DSP) | |+-----+ +----------------------------------+ | || PRM | | APM (Audio Processing Manager) | | |+-----+ | . Graph Management | | | | . Command Handing | | | | . Event Management | | | | ... | | | +----------------------------------+ | | ^ | |____________________________|______________________________| | | LPASS AIF ____________________________|______________________________ | | Audio I/O | | v | | +--------------------------------------------------+ | | | Audio devices | | | | CODEC | HDMI-TX | PCM | SLIMBUS | I2S |MI2S |...| | | | | | | +--------------------------------------------------+ | |___________________________________________________________| AudioReach has constructs of sub-graph, container and modules. Each sub-graph can have N containers and each Container can have N Modules and connections between them can be linear or non-linear. An audio function can be realized with one or many connected sub-graphs. There are also control/event paths between modules that can be wired up while building graph to achieve various control mechanism between modules. These concepts of Sub-Graph, Containers and Modules are represented in ASoC topology. Here is simple I2S graph with a Write Shared Memory and a Volume control module within a single Subgraph (1) with one Container (1) and 5 modules. ____________________________________________________________ | Sub-Graph [1] | | _______________________________________________________ | | | Container [1] | | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]-> [I2S-EP]| | | |_______________________________________________________| | |____________________________________________________________| For now this graph is split into two subgraphs to achieve dpcm like below: ________________________________________________ _________________ | Sub-Graph [1] | | Sub-Graph [2] | | ____________________________________________ | | _____________ | | | Container [1] | | | |Container [2]| | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]| | | | [I2S-EP] | | | |____________________________________________| | | |_____________| | |________________________________________________| |_________________| _________________ | Sub-Graph [3] | | _____________ | | |Container [3]| | | | [DMA-EP] | | | |_____________| | |_________________| This patchset adds very minimal support for AudioReach which includes supporting sub-graphs containing CODEC DMA ports and simple PCM Decoder/Encoder and Logger Modules. Additional capabilities will be built over time to expose features offered by AudioReach. This patchset is Tested on SM8250 SoC based Qualcomm Robotics Platform RB5 and SM9250 MTP with WSA881X Smart Speaker Amplifiers, DMICs connected via VA Macro and WCD938x Codec connected via TX and RX Macro and HDMI audio via I2S. First 10 Patches are mostly reorganization existing Old QDSP Audio Framework code and bindings so that we could reuse them on AudioReach. ASoC topology graphs for DragonBoard RB5 and SM8250 MTP are available at https://git.linaro.org/people/srinivas.kandagatla/audioreach-topology.git/ and Qualcomm AudioReach DSP headers are available at: https://source.codeaurora.org/quic/la/platform/vendor/opensource/arspf-head… Note: There is one false positive warning in this patchset: audioreach.c:80:45: warning: array of flexible structures Thanks, srini Changes since v9: - fix build error during arm64 defconfig build reported by Mark in 12/17 patch Srinivas Kandagatla (17): ASoC: dt-bindings: move LPASS dai related bindings out of q6afe ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h ASoC: qdsp6: q6afe-dai: move lpass audio ports to common file ASoC: qdsp6: q6afe-clocks: move audio-clocks to common file ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible ASoC: dt-bindings: add q6apm digital audio stream bindings ASoC: qdsp6: audioreach: add basic pkt alloc support ASoC: qdsp6: audioreach: add q6apm support ASoC: qdsp6: audioreach: add module configuration command helpers ASoC: qdsp6: audioreach: add Kconfig and Makefile ASoC: qdsp6: audioreach: add topology support ASoC: qdsp6: audioreach: add q6apm-dai support ASoC: qdsp6: audioreach: add q6apm lpass dai support ASoC: qdsp6: audioreach: add q6prm support ASoC: qdsp6: audioreach: add support for q6prm-clocks .../devicetree/bindings/sound/qcom,q6afe.txt | 181 --- .../bindings/sound/qcom,q6apm-dai.yaml | 53 + .../sound/qcom,q6dsp-lpass-clocks.yaml | 77 ++ .../sound/qcom,q6dsp-lpass-ports.yaml | 205 +++ include/dt-bindings/sound/qcom,q6afe.h | 203 +-- .../sound/qcom,q6dsp-lpass-ports.h | 208 +++ include/uapi/sound/snd_ar_tokens.h | 208 +++ sound/soc/qcom/Kconfig | 22 + sound/soc/qcom/qdsp6/Makefile | 11 +- sound/soc/qcom/qdsp6/audioreach.c | 1130 +++++++++++++++++ sound/soc/qcom/qdsp6/audioreach.h | 726 +++++++++++ sound/soc/qcom/qdsp6/q6afe-clocks.c | 187 +-- sound/soc/qcom/qdsp6/q6afe-dai.c | 687 +--------- sound/soc/qcom/qdsp6/q6apm-dai.c | 416 ++++++ sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 260 ++++ sound/soc/qcom/qdsp6/q6apm.c | 822 ++++++++++++ sound/soc/qcom/qdsp6/q6apm.h | 152 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c | 186 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h | 30 + sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 627 +++++++++ sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h | 22 + sound/soc/qcom/qdsp6/q6prm-clocks.c | 85 ++ sound/soc/qcom/qdsp6/q6prm.c | 202 +++ sound/soc/qcom/qdsp6/q6prm.h | 78 ++ sound/soc/qcom/qdsp6/topology.c | 1113 ++++++++++++++++ 25 files changed, 6664 insertions(+), 1227 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h create mode 100644 include/uapi/sound/snd_ar_tokens.h create mode 100644 sound/soc/qcom/qdsp6/audioreach.c create mode 100644 sound/soc/qcom/qdsp6/audioreach.h create mode 100644 sound/soc/qcom/qdsp6/q6apm-dai.c create mode 100644 sound/soc/qcom/qdsp6/q6apm-lpass-dais.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.h create mode 100644 sound/soc/qcom/qdsp6/topology.c -- 2.21.0

2 19

[PATCH v9 00/17] ASoC: qcom: Add AudioReach support
by Srinivas Kandagatla 26 Oct '21

26 Oct '21

Hi Mark, This version addresses all the comments raised as part of v8 review. QCOM SoC relevant non-audio patches in this series has been merged into the Qualcomm drivers-for-5.16 tree, as this series depends those patches an immutable tag is available at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/20210927135559.738-6-srinivas.kandagatla(a)linaro.org This patchset adds ASoC driver support to configure signal processing framework ("AudioReach") which is integral part of Qualcomm next generation audio SDK and will be deployed on upcoming Qualcomm chipsets. It makes use of ASoC Topology to load graphs on to the DSP which is then managed by APM (Audio Processing Manager) service to prepare/start/stop. Here is simplified high-level block diagram of AudioReach: ___________________________________________________________ | CPU (Application Processor) | | +---------+ +---------+ +----------+ | | | q6apm | | q6apm | | q6apm | | | | dais | <------> | | <-----> |lpass-dais| | | +---------+ +---------+ +----------+ | | ^ ^ | | | | +---------+ | | +---------+ v +---------->|topology | | | | q6prm | +---------+ | | | | | |<-------->| GPR | +---------+ | | +---------+ +---------+ | | ^ ^ | | | | | | +----------+ | | | | q6prm | | | | |lpass-clks| | | | +----------+ | | |____________________________|______________________________| | | RPMSG (IPC over GLINK) ____________________________|______________________________ | | | | +-----------------------+ | | | | | | v v q6 (Audio DSP) | |+-----+ +----------------------------------+ | || PRM | | APM (Audio Processing Manager) | | |+-----+ | . Graph Management | | | | . Command Handing | | | | . Event Management | | | | ... | | | +----------------------------------+ | | ^ | |____________________________|______________________________| | | LPASS AIF ____________________________|______________________________ | | Audio I/O | | v | | +--------------------------------------------------+ | | | Audio devices | | | | CODEC | HDMI-TX | PCM | SLIMBUS | I2S |MI2S |...| | | | | | | +--------------------------------------------------+ | |___________________________________________________________| AudioReach has constructs of sub-graph, container and modules. Each sub-graph can have N containers and each Container can have N Modules and connections between them can be linear or non-linear. An audio function can be realized with one or many connected sub-graphs. There are also control/event paths between modules that can be wired up while building graph to achieve various control mechanism between modules. These concepts of Sub-Graph, Containers and Modules are represented in ASoC topology. Here is simple I2S graph with a Write Shared Memory and a Volume control module within a single Subgraph (1) with one Container (1) and 5 modules. ____________________________________________________________ | Sub-Graph [1] | | _______________________________________________________ | | | Container [1] | | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]-> [I2S-EP]| | | |_______________________________________________________| | |____________________________________________________________| For now this graph is split into two subgraphs to achieve dpcm like below: ________________________________________________ _________________ | Sub-Graph [1] | | Sub-Graph [2] | | ____________________________________________ | | _____________ | | | Container [1] | | | |Container [2]| | | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]| | | | [I2S-EP] | | | |____________________________________________| | | |_____________| | |________________________________________________| |_________________| _________________ | Sub-Graph [3] | | _____________ | | |Container [3]| | | | [DMA-EP] | | | |_____________| | |_________________| This patchset adds very minimal support for AudioReach which includes supporting sub-graphs containing CODEC DMA ports and simple PCM Decoder/Encoder and Logger Modules. Additional capabilities will be built over time to expose features offered by AudioReach. This patchset is Tested on SM8250 SoC based Qualcomm Robotics Platform RB5 and SM9250 MTP with WSA881X Smart Speaker Amplifiers, DMICs connected via VA Macro and WCD938x Codec connected via TX and RX Macro and HDMI audio via I2S. First 10 Patches are mostly reorganization existing Old QDSP Audio Framework code and bindings so that we could reuse them on AudioReach. ASoC topology graphs for DragonBoard RB5 and SM8250 MTP are available at https://git.linaro.org/people/srinivas.kandagatla/audioreach-topology.git/ and Qualcomm AudioReach DSP headers are available at: https://source.codeaurora.org/quic/la/platform/vendor/opensource/arspf-head… Note: There is one false positive warning in this patchset: audioreach.c:80:45: warning: array of flexible structures Thanks, srini Changes since v8: - made use of struct_size where possible. - fixed an incorrect indent. - adding __packed for consistency on structures that are passed to dsp. - rebased to sound-next branch. Srinivas Kandagatla (17): ASoC: dt-bindings: move LPASS dai related bindings out of q6afe ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h ASoC: qdsp6: q6afe-dai: move lpass audio ports to common file ASoC: qdsp6: q6afe-clocks: move audio-clocks to common file ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible ASoC: dt-bindings: add q6apm digital audio stream bindings ASoC: qdsp6: audioreach: add basic pkt alloc support ASoC: qdsp6: audioreach: add q6apm support ASoC: qdsp6: audioreach: add module configuration command helpers ASoC: qdsp6: audioreach: add Kconfig and Makefile ASoC: qdsp6: audioreach: add topology support ASoC: qdsp6: audioreach: add q6apm-dai support ASoC: qdsp6: audioreach: add q6apm lpass dai support ASoC: qdsp6: audioreach: add q6prm support ASoC: qdsp6: audioreach: add support for q6prm-clocks .../devicetree/bindings/sound/qcom,q6afe.txt | 181 --- .../bindings/sound/qcom,q6apm-dai.yaml | 53 + .../sound/qcom,q6dsp-lpass-clocks.yaml | 77 ++ .../sound/qcom,q6dsp-lpass-ports.yaml | 205 +++ include/dt-bindings/sound/qcom,q6afe.h | 203 +-- .../sound/qcom,q6dsp-lpass-ports.h | 208 +++ include/uapi/sound/snd_ar_tokens.h | 208 +++ sound/soc/qcom/Kconfig | 22 + sound/soc/qcom/qdsp6/Makefile | 11 +- sound/soc/qcom/qdsp6/audioreach.c | 1130 +++++++++++++++++ sound/soc/qcom/qdsp6/audioreach.h | 726 +++++++++++ sound/soc/qcom/qdsp6/q6afe-clocks.c | 187 +-- sound/soc/qcom/qdsp6/q6afe-dai.c | 687 +--------- sound/soc/qcom/qdsp6/q6apm-dai.c | 416 ++++++ sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 260 ++++ sound/soc/qcom/qdsp6/q6apm.c | 822 ++++++++++++ sound/soc/qcom/qdsp6/q6apm.h | 152 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c | 186 +++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h | 30 + sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 627 +++++++++ sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h | 22 + sound/soc/qcom/qdsp6/q6prm-clocks.c | 85 ++ sound/soc/qcom/qdsp6/q6prm.c | 202 +++ sound/soc/qcom/qdsp6/q6prm.h | 78 ++ sound/soc/qcom/qdsp6/topology.c | 1113 ++++++++++++++++ 25 files changed, 6664 insertions(+), 1227 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h create mode 100644 include/uapi/sound/snd_ar_tokens.h create mode 100644 sound/soc/qcom/qdsp6/audioreach.c create mode 100644 sound/soc/qcom/qdsp6/audioreach.h create mode 100644 sound/soc/qcom/qdsp6/q6apm-dai.c create mode 100644 sound/soc/qcom/qdsp6/q6apm-lpass-dais.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.h create mode 100644 sound/soc/qcom/qdsp6/topology.c -- 2.21.0

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Re: 回复: [PATCH] sound/usb: fix null pointer dereference on pointer cs_desc
by Takashi Iwai 26 Oct '21

26 Oct '21

On Sun, 24 Oct 2021 13:20:48 +0200, YE Chengfeng wrote: > > Hi, > > I found another potential null-ptr-dereference problem in this file, and not > sure whether it is true. I send this patch to you just for reference, thinks > a lot if you could spare some time to look at it. The Fixes tag doesn't look correct (the code before the refactoring also didn't have NULL checks), so applied without it now. thanks, Takashi > > Thanks so much, > Chengfeng > ------------------------------------------------------------------------------ > 发件人: YE Chengfeng <cyeaa(a)connect.ust.hk> > 发送时间: 2021年10月24日 19:17 > 收件人: perex(a)perex.cz <perex(a)perex.cz>; tiwai(a)suse.com <tiwai(a)suse.com>; > chihhao.chen(a)mediatek.com <chihhao.chen(a)mediatek.com>; damien(a)zamaudio.com > <damien(a)zamaudio.com> > 抄送: alsa-devel(a)alsa-project.org <alsa-devel(a)alsa-project.org>; > linux-kernel(a)vger.kernel.org <linux-kernel(a)vger.kernel.org>; YE Chengfeng > <cyeaa(a)connect.ust.hk> > 主题: [PATCH] sound/usb: fix null pointer dereference on pointer cs_desc > > The pointer cs_desc return from snd_usb_find_clock_source could > be null, so there is a potential null pointer dereference issue. > Fix this by adding a null check before dereference. > > Fixes: 9ec73005 ("ALSA: usb-audio: Refactoring UAC2/3 clock setup code") > Signed-off-by: Chengfeng Ye <cyeaa(a)connect.ust.hk> > --- > sound/usb/clock.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/sound/usb/clock.c b/sound/usb/clock.c > index 81d5ce07d548..98345a695dcc 100644 > --- a/sound/usb/clock.c > +++ b/sound/usb/clock.c > @@ -496,6 +496,10 @@ int snd_usb_set_sample_rate_v2v3(struct snd_usb_audio > *chip, > union uac23_clock_source_desc *cs_desc; > > cs_desc = snd_usb_find_clock_source(chip, clock, fmt->protocol); > + > + if (!cs_desc) > + return 0; > + > if (fmt->protocol == UAC_VERSION_3) > bmControls = le32_to_cpu(cs_desc->v3.bmControls); > else > -- > 2.17.1 > >

2 1

[PATCH v3] ASoC: qcom: soundwire: Enable soundwire bus clock for version 1.6
by Srinivasa Rao Mandadapu 26 Oct '21

26 Oct '21

Add support for soundwire 1.6 version to gate RX/TX bus clock. Signed-off-by: Venkata Prasad Potturu <potturu(a)codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org> --- Changes since v2: -- Update error check after ioremap. Changes since v1: -- Add const name to mask value. drivers/soundwire/qcom.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 0ef79d6..bd6fabd 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -109,6 +109,7 @@ #define SWR_MAX_CMD_ID 14 #define MAX_FIFO_RD_RETRY 3 #define SWR_OVERFLOW_RETRY_COUNT 30 +#define SWRM_HCTL_REG_MASK ~BIT(1) struct qcom_swrm_port_config { u8 si; @@ -127,6 +128,7 @@ struct qcom_swrm_ctrl { struct device *dev; struct regmap *regmap; void __iomem *mmio; + char __iomem *swrm_hctl_reg; struct completion broadcast; struct completion enumeration; struct work_struct slave_work; @@ -610,6 +612,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); + if (ctrl->swrm_hctl_reg) { + val = ioread32(ctrl->swrm_hctl_reg); + val &= SWRM_HCTL_REG_MASK; + iowrite32(val, ctrl->swrm_hctl_reg); + } + ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); /* Enable Auto enumeration */ @@ -1200,7 +1208,7 @@ static int qcom_swrm_probe(struct platform_device *pdev) struct qcom_swrm_ctrl *ctrl; const struct qcom_swrm_data *data; int ret; - u32 val; + int val, swrm_hctl_reg = 0; ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); if (!ctrl) @@ -1251,6 +1259,11 @@ static int qcom_swrm_probe(struct platform_device *pdev) ctrl->bus.port_ops = &qcom_swrm_port_ops; ctrl->bus.compute_params = &qcom_swrm_compute_params; + if (!of_property_read_u32(dev->of_node, "qcom,swrm-hctl-reg", &swrm_hctl_reg)) { + ctrl->swrm_hctl_reg = devm_ioremap(&pdev->dev, swrm_hctl_reg, 0x4); + if (!ctrl->swrm_hctl_reg) + return -ENODEV; + } ret = qcom_swrm_get_port_config(ctrl); if (ret) goto err_clk; -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

2 2

[PATCH v2] ASoC: qcom: soundwire: Enable soundwire bus clock for version 1.6
by Srinivasa Rao Mandadapu 26 Oct '21

26 Oct '21

Add support for soundwire 1.6 version to gate RX/TX bus clock. Signed-off-by: Venkata Prasad Potturu <potturu(a)codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org> --- Changes since v1: -- Add const name to mask value. drivers/soundwire/qcom.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 0ef79d6..491407f 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -109,6 +109,7 @@ #define SWR_MAX_CMD_ID 14 #define MAX_FIFO_RD_RETRY 3 #define SWR_OVERFLOW_RETRY_COUNT 30 +#define SWRM_HCTL_REG_MASK 0xFFFFFFFD struct qcom_swrm_port_config { u8 si; @@ -127,6 +128,7 @@ struct qcom_swrm_ctrl { struct device *dev; struct regmap *regmap; void __iomem *mmio; + char __iomem *swrm_hctl_reg; struct completion broadcast; struct completion enumeration; struct work_struct slave_work; @@ -610,6 +612,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); + if (ctrl->swrm_hctl_reg) { + val = ioread32(ctrl->swrm_hctl_reg); + val &= SWRM_HCTL_REG_MASK; + iowrite32(val, ctrl->swrm_hctl_reg); + } + ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); /* Enable Auto enumeration */ @@ -1200,7 +1208,7 @@ static int qcom_swrm_probe(struct platform_device *pdev) struct qcom_swrm_ctrl *ctrl; const struct qcom_swrm_data *data; int ret; - u32 val; + int val, swrm_hctl_reg = 0; ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); if (!ctrl) @@ -1251,6 +1259,9 @@ static int qcom_swrm_probe(struct platform_device *pdev) ctrl->bus.port_ops = &qcom_swrm_port_ops; ctrl->bus.compute_params = &qcom_swrm_compute_params; + if (!of_property_read_u32(dev->of_node, "qcom,swrm-hctl-reg", &swrm_hctl_reg)) + ctrl->swrm_hctl_reg = devm_ioremap(&pdev->dev, swrm_hctl_reg, 0x4); + ret = qcom_swrm_get_port_config(ctrl); if (ret) goto err_clk; -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

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[PATCH 2/2] ASoC: codec: tlv320adc3xxx: New codec driver
by Ricard Wanderlof 26 Oct '21

26 Oct '21

New codec driver for Texas Instruments TLV320ADC3001 and TLV320ADC3101 audio ADCs. Signed-off-by: Ricard Wanderlof <ricardw(a)axis.com> --- sound/soc/codecs/Kconfig | 7 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/tlv320adc3xxx.c | 1239 ++++++++++++++++++++++++++++++ sound/soc/codecs/tlv320adc3xxx.h | 381 +++++++++ 4 files changed, 1629 insertions(+) create mode 100644 sound/soc/codecs/tlv320adc3xxx.c create mode 100644 sound/soc/codecs/tlv320adc3xxx.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index deda5ee02ebb..6385142826db 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -217,6 +217,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_TDA7419 imply SND_SOC_TFA9879 imply SND_SOC_TFA989X + imply SND_SOC_TLV320ADC3XXX imply SND_SOC_TLV320ADCX140 imply SND_SOC_TLV320AIC23_I2C imply SND_SOC_TLV320AIC23_SPI @@ -1463,6 +1464,12 @@ config SND_SOC_TFA989X Note that the driver currently bypasses the built-in "CoolFlux DSP" and does not support (hardware) volume control. +config SND_SOC_TLV320ADC3XXX + tristate "Texas Instruments TLV320ADC3001/3101 audio ADC" + help + Enable support for Texas Instruments TLV320ADC3001 and TLV320ADC3101 + ADCs. + config SND_SOC_TLV320AIC23 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 4cf939d0d3fb..227d597fd662 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -235,6 +235,7 @@ snd-soc-tda7419-objs := tda7419.o snd-soc-tas2770-objs := tas2770.o snd-soc-tfa9879-objs := tfa9879.o snd-soc-tfa989x-objs := tfa989x.o +snd-soc-tlv320adc3xxx-objs := tlv320adc3xxx.o snd-soc-tlv320aic23-objs := tlv320aic23.o snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o @@ -566,6 +567,7 @@ obj-$(CONFIG_SND_SOC_TDA7419) += snd-soc-tda7419.o obj-$(CONFIG_SND_SOC_TAS2770) += snd-soc-tas2770.o obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o obj-$(CONFIG_SND_SOC_TFA989X) += snd-soc-tfa989x.o +obj-$(CONFIG_SND_SOC_TLV320ADC3XXX) += snd-soc-tlv320adc3xxx.o obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o diff --git a/sound/soc/codecs/tlv320adc3xxx.c b/sound/soc/codecs/tlv320adc3xxx.c new file mode 100644 index 000000000000..894c07efaaf7 --- /dev/null +++ b/sound/soc/codecs/tlv320adc3xxx.c @@ -0,0 +1,1239 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov + * + * History: + * + * Author: "Shahina Shaik" < shahina.s(a)mistralsolutions.com > + * Copyright: (C) 2010 Mistral Solutions Pvt Ltd. + * + * Author: Dongge wu <dgwu(a)ambarella.com> + * 2015/10/28 - [Dongge wu] Created file + * Copyright (C) 2014-2018, Ambarella, Inc. + * + * Author: Ricard Wanderlof <ricardw(a)axis.com> + * 2020/11/05: Fixing driver for Linux 4.14: more clocking modes, etc. + * 2021/09/03: Porting driver to Linux 5.4. + * Add simple card and DT settable PLL mode, GPIO pin control. + * Copyright (C) 2021 Axis Communications AB + * + */ + +/***************************** INCLUDES ************************************/ + +#include <dt-bindings/sound/tlv320adc3xxx.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/cdev.h> +#include <linux/of_gpio.h> +#include <linux/slab.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/tlv.h> +#include <sound/initval.h> + +#include "tlv320adc3xxx.h" + +/* + * **************************************************************************** + * Macros + * **************************************************************************** + * + */ + +#define PLL_MODE_TEXT(mode) (mode == ADC3XXX_PLL_ENABLE ? "PLL enable" : \ + (mode == ADC3XXX_PLL_BYPASS ? "PLL bypass" : \ + "PLL auto")) + +enum adc3xxx_type { + ADC3001 = 0, + ADC3101 +}; + +/* codec private data */ +struct adc3xxx_priv { + struct device *dev; + enum adc3xxx_type type; + struct clk *mclk; + struct regmap *regmap; + unsigned int pll_mode; + unsigned int rst_pin; + unsigned int rst_active; + unsigned int sysclk; + unsigned int gpio1_cfg; /* GPIO1_CTRL value + 1 (0 => not set) */ + unsigned int gpio2_cfg; /* GPIO2_CTRL value + 1 (0 => not set) */ + int master; + u8 page_no; + int use_pll; +}; + +static int adc3xxx_set_bias_level(struct snd_soc_component *, + enum snd_soc_bias_level); + +static const struct reg_default adc3xxx_defaults[] = { + /* Page 0 */ + { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 }, + { 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 }, + { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 }, + { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 }, + { 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 }, + { 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 }, + { 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 }, + { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 }, + { 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 }, + { 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 }, + { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 }, + { 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, + { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 }, + { 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 }, + { 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 }, + { 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 }, + { 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 }, + { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, + { 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, + { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, + { 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 }, + { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, + { 88, 0x7F }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, + { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, + { 96, 0x7F }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, + { 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 }, + { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, + { 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 }, + { 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 }, + { 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 }, + { 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 }, + { 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 }, + + /* Page 1 */ + { 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 }, + { 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 }, + { 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 }, + { 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 }, + { 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 }, + { 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 }, + { 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 }, + { 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 }, + { 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 }, + { 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 }, + { 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 }, + { 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 }, + { 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 }, + { 180, 0xFF }, { 181, 0x00 }, { 182, 0x3F }, { 183, 0xFF }, + { 184, 0x00 }, { 185, 0x3F }, { 186, 0x00 }, { 187, 0x80 }, + { 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 }, +}; + +static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case PAGE_SELECT: /* required by regmap implementation */ + case RESET: + return true; + default: + return false; + } +} + +static const struct regmap_range_cfg adc3xxx_ranges[] = { + { + .range_min = 0, + .range_max = 2 * ADC3xxx_PAGE_SIZE, + .selector_reg = PAGE_SELECT, + .selector_mask = 0xff, + .selector_shift = 0, + .window_start = 0, + .window_len = ADC3xxx_PAGE_SIZE, + } +}; + +static const struct regmap_config adc3xxx_regmap = { + .reg_bits = 8, + .val_bits = 8, + + .reg_defaults = adc3xxx_defaults, + .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults), + + .volatile_reg = adc3xxx_volatile_reg, + + .cache_type = REGCACHE_RBTREE, + + .ranges = adc3xxx_ranges, + .num_ranges = ARRAY_SIZE(adc3xxx_ranges), + .max_register = 2 * ADC3xxx_PAGE_SIZE, +}; + +/* + * adc3xxx initialization data + * This structure initialization contains the initialization required for + * ADC3xxx. + * These registers values (reg_val) are written into the respective ADC3xxx + * register offset (reg_offset) to initialize ADC3xxx. + * These values are used in adc3xxx_init() function only. + */ +struct adc3xxx_configs { + u8 reg_offset; + u8 reg_val; +}; + +/* The global Register Initialization sequence Array. During the Audio Driver + * Initialization, this array will be utilized to perform the default + * initialization of the audio Driver. + */ +static const struct adc3xxx_configs adc3xxx_reg_init[] = { + /* The default (out-of-reset) values in the x_PGA_SEL_x registers + * disable the inputs by default, but also set the input attenuation + * to -6 dB by default, so we leave the inputs disabled but set + * the attenuation to a more natural 0 dB. + */ + { LEFT_PGA_SEL_1, 0xaa }, + { LEFT_PGA_SEL_2, 0x2a }, + { RIGHT_PGA_SEL_1, 0xaa }, + { RIGHT_PGA_SEL_2, 0x2a }, + /* mute Left PGA + default gain 0 dB (same as reset value) */ + { LEFT_APGA_CTRL, 0x80 }, + /* mute Right PGA + default gain 0 dB (same as reset value) */ + { RIGHT_APGA_CTRL, 0x80 }, + /* Disable AGC (same as reset value) */ + { LEFT_CHN_AGC_1, 0x00 }, + { RIGHT_CHN_AGC_1, 0x00 }, + /* Maximum AGC gain 40 dB */ + /* (Oddly enough, the data sheet says the register field default + * value for the maximum gain is 0b111111 = 127 (verified empirically) + * which is specified as 'Reserved. Do not use.' in the accompanying + * table). + */ + { LEFT_CHN_AGC_3, 0x50 }, + { RIGHT_CHN_AGC_3, 0x50 }, + /* Leave MICBIAS1 and MICBIAS2 powered down (same as reset value) */ + { MICBIAS_CTRL, 0x00 }, + /* Fine Gain 0dB, Left/Right ADC Unmute */ + { ADC_FGA, 0x00 }, +}; + +/* Additional initialization for TLV320ADC3101 + */ +static const struct adc3xxx_configs adc3101_reg_init[] = { + /* Use Primary BCLK and WCLK (same as reset value) */ + { INTERFACE_CTRL_4, 0x00 }, + /* DMCLK output = ADC_MOD_CLK */ + { GPIO2_CTRL, 0x28 }, + /* DMDIN is in input (used for Dig_Mic_In) mode */ + { GPIO1_CTRL, 0x04 }, +}; + +/* + * PLL and Clock settings. + * If p member is 0, PLL is not used. + * The order of the entries in this table have the PLL entries before + * the non-PLL entries, so that the PLL modes are preferred unless + * the PLL mode setting says otherwise. + */ +static const struct adc3xxx_rate_divs adc3xxx_divs[] = { + /* mclk, rate, p, r, j, d, nadc, madc, aosr */ + /* 8k rate */ + {12000000, 8000, 1, 1, 7, 1680, 42, 2, 128}, + {12288000, 8000, 1, 1, 7, 0000, 42, 2, 128}, + /* 11.025k rate */ + {12000000, 11025, 1, 1, 6, 8208, 29, 2, 128}, + /* 16k rate */ + {12000000, 16000, 1, 1, 7, 1680, 21, 2, 128}, + {12288000, 16000, 1, 1, 7, 0000, 21, 2, 128}, + /* 22.05k rate */ + {12000000, 22050, 1, 1, 7, 560, 15, 2, 128}, + /* 32k rate */ + {12000000, 32000, 1, 1, 8, 1920, 12, 2, 128}, + {12288000, 32000, 1, 1, 8, 0000, 12, 2, 128}, + /* 44.1k rate */ + {12000000, 44100, 1, 1, 7, 5264, 8, 2, 128}, + /* 48k rate */ + {12000000, 48000, 1, 1, 7, 1680, 7, 2, 128}, + {12288000, 48000, 1, 1, 7, 0000, 7, 2, 128}, + {24576000, 48000, 1, 1, 3, 5000, 7, 2, 128}, /* With PLL */ + {24576000, 48000, 0, 0, 0, 0000, 2, 2, 128}, /* Without PLL */ + /* 88.2k rate */ + {12000000, 88200, 1, 1, 7, 5264, 4, 4, 64}, + /* 96k rate */ + {12000000, 96000, 1, 1, 8, 1920, 4, 4, 64}, +}; + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_get_divs + * Purpose : This function is to get required divisor from the "adc3xxx_divs" + * table. + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode) +{ + int i; + + dev_info(dev, "mclk = %d, rate = %d, clock mode %u\n", + mclk, rate, pll_mode); + for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) { + const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i]; + + /* Skip this entry if it doesn't fulfill the intended clock + * mode requirement. We consider anything besides the two + * modes below to be the same as ADC3XXX_PLL_AUTO. + */ + if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) || + (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p)) + continue; + + if (mode->rate == rate && mode->mclk == mclk) + return i; + } + + dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n", + mclk, rate); + return -EINVAL; +} + +static const char * const micbias_voltage[] = { "off", "2V", "2.5V", "AVDD" }; +static const char * const linein_attenuation[] = { "0db", "-6dB" }; +static const char * const adc_softstepping[] = { "1 step", "2 step", "off" }; +static const char * const multiplier[] = { "1", "2", "4", "8", "16", "32", "64", "128" }; +static const char * const dither_dc_offset[] = { + "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV", + "reserved", "-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV" +}; + +static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0); +static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0); +static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0); +/* agc_target_tlv: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */ +/* It would be nice to declare these in the order above, but empirically + * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter + * being negative, despite there being examples to the contrary in other + * drivers. So declare these in the order from lowest to highest, and + * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead. + */ +static const DECLARE_TLV_DB_RANGE(agc_target_tlv, + 0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0), + 1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0), + 4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0), + 7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0)); +/* Since the 'disabled' value (mute) is at the highest value in the dB + * range (i.e. just before -32 dB) rather than the lowest, we need to resort + * to using a TLV_DB_RANGE in order to get the mute value in the right place. + */ +static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv, + 0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0), + 31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ +/* agc_hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */ +static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv, + 0, 1, TLV_DB_SCALE_ITEM(100, 100, 0), + 2, 2, TLV_DB_SCALE_ITEM(400, 0, 0), + 3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ +static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0); + +#define MICBIAS1_ENUM 0 +#define MICBIAS2_ENUM 1 +#define ADCSOFTSTEP_ENUM 2 +#define ATT_LEFT_IN_1L_ENUM 3 +#define ATT_LEFT_IN_2L_ENUM 4 +#define ATT_LEFT_IN_3L_ENUM 5 +#define ATT_LEFT_IN_1R_ENUM 6 +#define ATT_LEFT_DIF_2L_3L_ENUM 7 +#define ATT_LEFT_DIF_1L_1R_ENUM 8 +#define ATT_LEFT_DIF_2R_3R_ENUM 9 +#define ATT_RIGHT_IN_1R_ENUM 10 +#define ATT_RIGHT_IN_2R_ENUM 11 +#define ATT_RIGHT_IN_3R_ENUM 12 +#define ATT_RIGHT_IN_1L_ENUM 13 +#define ATT_RIGHT_DIF_2R_3R_ENUM 14 +#define ATT_RIGHT_DIF_1L_1R_ENUM 15 +#define ATT_RIGHT_DIF_2L_3L_ENUM 16 +#define AGCATKMULTL_ENUM 17 +#define AGCATKMULTR_ENUM 18 +#define AGCDECMULTL_ENUM 19 +#define AGCDECMULTR_ENUM 20 +#define DITHER_DC_OFFSET_ENUM 21 + +/* Creates an array of the Single Ended Widgets*/ +static const struct soc_enum adc3xxx_enum[] = { + SOC_ENUM_SINGLE(MICBIAS_CTRL, 5, 4, micbias_voltage), + SOC_ENUM_SINGLE(MICBIAS_CTRL, 3, 4, micbias_voltage), + SOC_ENUM_SINGLE(ADC_DIGITAL, 0, 3, adc_softstepping), + SOC_ENUM_SINGLE(LEFT_PGA_SEL_1, 0, 2, linein_attenuation), + SOC_ENUM_SINGLE(LEFT_PGA_SEL_1, 2, 2, linein_attenuation), + SOC_ENUM_SINGLE(LEFT_PGA_SEL_1, 4, 2, linein_attenuation), + SOC_ENUM_SINGLE(LEFT_PGA_SEL_2, 0, 2, linein_attenuation), + SOC_ENUM_SINGLE(LEFT_PGA_SEL_1, 6, 2, linein_attenuation), + SOC_ENUM_SINGLE(LEFT_PGA_SEL_2, 4, 2, linein_attenuation), + SOC_ENUM_SINGLE(LEFT_PGA_SEL_2, 2, 2, linein_attenuation), + SOC_ENUM_SINGLE(RIGHT_PGA_SEL_1, 0, 2, linein_attenuation), + SOC_ENUM_SINGLE(RIGHT_PGA_SEL_1, 2, 2, linein_attenuation), + SOC_ENUM_SINGLE(RIGHT_PGA_SEL_1, 4, 2, linein_attenuation), + SOC_ENUM_SINGLE(RIGHT_PGA_SEL_2, 0, 2, linein_attenuation), + SOC_ENUM_SINGLE(RIGHT_PGA_SEL_1, 6, 2, linein_attenuation), + SOC_ENUM_SINGLE(RIGHT_PGA_SEL_2, 4, 2, linein_attenuation), + SOC_ENUM_SINGLE(RIGHT_PGA_SEL_2, 2, 2, linein_attenuation), + SOC_ENUM_SINGLE(LEFT_CHN_AGC_4, 0, 8, multiplier), + SOC_ENUM_SINGLE(RIGHT_CHN_AGC_4, 0, 8, multiplier), + SOC_ENUM_SINGLE(LEFT_CHN_AGC_5, 0, 8, multiplier), + SOC_ENUM_SINGLE(RIGHT_CHN_AGC_5, 0, 8, multiplier), + SOC_ENUM_DOUBLE(DITHER_CTRL, 4, 0, 16, dither_dc_offset), +}; + +/* Various Controls For adc3xxx */ +static const struct snd_kcontrol_new adc3xxx_snd_controls[] = { + SOC_DOUBLE_R_TLV("PGA Gain Volume", LEFT_APGA_CTRL, RIGHT_APGA_CTRL, + 0, 80, 0, pga_tlv), + SOC_DOUBLE_R("AGC Enable", LEFT_CHN_AGC_1, + RIGHT_CHN_AGC_1, 7, 1, 0), + SOC_DOUBLE_R_TLV("AGC Target Level Volume", LEFT_CHN_AGC_1, + RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv), + SOC_DOUBLE_R_TLV("AGC Noise Threshold Volume", LEFT_CHN_AGC_2, + RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv), + SOC_DOUBLE_R_TLV("AGC Hysteresis Volume", LEFT_CHN_AGC_2, + RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv), + SOC_DOUBLE_R("AGC Clip Stepping Enable", LEFT_CHN_AGC_2, + RIGHT_CHN_AGC_2, 0, 1, 0), + SOC_DOUBLE_R_TLV("AGC Maximum Gain Volume", LEFT_CHN_AGC_3, + RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv), + SOC_DOUBLE_R("AGC Attack Time", LEFT_CHN_AGC_4, + RIGHT_CHN_AGC_4, 3, 0x1F, 0), + /* Would like to have the multipliers as LR pairs, but there is + * no SOC_ENUM_foo which accepts two values in separate registers. + */ + SOC_ENUM("AGC Left Attack Time Multiplier", + adc3xxx_enum[AGCATKMULTL_ENUM]), + SOC_ENUM("AGC Right Attack Time Multiplier", + adc3xxx_enum[AGCATKMULTR_ENUM]), + SOC_DOUBLE_R("AGC Decay Time", LEFT_CHN_AGC_5, + RIGHT_CHN_AGC_5, 3, 0x1F, 0), + SOC_ENUM("AGC Left Decay Time Multiplier", + adc3xxx_enum[AGCDECMULTL_ENUM]), + SOC_ENUM("AGC Right Decay Time Multiplier", + adc3xxx_enum[AGCDECMULTR_ENUM]), + SOC_DOUBLE_R("AGC Noise Debounce", LEFT_CHN_AGC_6, + RIGHT_CHN_AGC_6, 0, 0x1F, 0), + SOC_DOUBLE_R("AGC Signal Debounce", LEFT_CHN_AGC_7, + RIGHT_CHN_AGC_7, 0, 0x0F, 0), + /* Read only register */ + SOC_DOUBLE_R_S_TLV("AGC Applied Gain Volume", LEFT_AGC_GAIN, + RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv), + /* Mic Bias voltage */ + SOC_ENUM("Mic Bias 1 Voltage", adc3xxx_enum[MICBIAS1_ENUM]), + SOC_ENUM("Mic Bias 2 Voltage", adc3xxx_enum[MICBIAS2_ENUM]), + /* ADC soft stepping */ + SOC_ENUM("ADC soft stepping", adc3xxx_enum[ADCSOFTSTEP_ENUM]), + /* Left/Right Input attenuation */ + SOC_ENUM("Left IN_1L input attenuation", + adc3xxx_enum[ATT_LEFT_IN_1L_ENUM]), + SOC_ENUM("Left IN_2L input attenuation", + adc3xxx_enum[ATT_LEFT_IN_1L_ENUM]), + SOC_ENUM("Left IN_3L input attenuation", + adc3xxx_enum[ATT_LEFT_IN_1L_ENUM]), + SOC_ENUM("Left IN_1R input attenuation", + adc3xxx_enum[ATT_LEFT_IN_1R_ENUM]), + SOC_ENUM("Left DIF_2L_3L input attenuation", + adc3xxx_enum[ATT_LEFT_DIF_2L_3L_ENUM]), + SOC_ENUM("Left DIF_1L_1R input attenuation", + adc3xxx_enum[ATT_LEFT_DIF_1L_1R_ENUM]), + SOC_ENUM("Left DIF_2R_3R input attenuation", + adc3xxx_enum[ATT_LEFT_DIF_2R_3R_ENUM]), + SOC_ENUM("Right IN_1R input attenuation", + adc3xxx_enum[ATT_RIGHT_IN_1R_ENUM]), + SOC_ENUM("Right IN_2R input attenuation", + adc3xxx_enum[ATT_RIGHT_IN_2R_ENUM]), + SOC_ENUM("Right IN_3R input attenuation", + adc3xxx_enum[ATT_RIGHT_IN_3R_ENUM]), + SOC_ENUM("Right IN_1L input attenuation", + adc3xxx_enum[ATT_RIGHT_IN_1L_ENUM]), + SOC_ENUM("Right DIF_2R_3R input attenuation", + adc3xxx_enum[ATT_RIGHT_DIF_2R_3R_ENUM]), + SOC_ENUM("Right DIF_1L_1R input attenuation", + adc3xxx_enum[ATT_RIGHT_DIF_1L_1R_ENUM]), + SOC_ENUM("Right DIF_2L_3L input attenuation", + adc3xxx_enum[ATT_RIGHT_DIF_2L_3L_ENUM]), + SOC_DOUBLE_R_S_TLV("ADC Volume Control Volume", LADC_VOL, RADC_VOL, + 0, -24, 40, 6, 0, adc_tlv), + /* Empirically, the following doesn't work the way it's supposed + * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and + * -0.4 dB drops about 0.12 dB on a specific chip. + */ + SOC_DOUBLE_TLV("ADC Fine Volume Control Volume", ADC_FGA, 4, 0, 4, 1, + adc_fine_tlv), + SOC_SINGLE("Left ADC unselected CM bias", LEFT_PGA_SEL_2, 6, 1, 0), + SOC_SINGLE("Right ADC unselected CM bias", RIGHT_PGA_SEL_2, 6, 1, 0), + SOC_ENUM("Dither Control DC Offset", adc3xxx_enum[DITHER_DC_OFFSET_ENUM]), +}; + +/* Left input selection, Single Ended inputs and Differential inputs */ +static const struct snd_kcontrol_new left_input_mixer_controls[] = { + SOC_DAPM_SINGLE("IN_1L switch", LEFT_PGA_SEL_1, 1, 0x1, 1), + SOC_DAPM_SINGLE("IN_2L switch", LEFT_PGA_SEL_1, 3, 0x1, 1), + SOC_DAPM_SINGLE("IN_3L switch", LEFT_PGA_SEL_1, 5, 0x1, 1), + SOC_DAPM_SINGLE("DIF_2L_3L switch", LEFT_PGA_SEL_1, 7, 0x1, 1), + SOC_DAPM_SINGLE("DIF_1L_1R switch", LEFT_PGA_SEL_2, 5, 0x1, 1), + SOC_DAPM_SINGLE("DIF_2R_3R switch", LEFT_PGA_SEL_2, 3, 0x1, 1), + SOC_DAPM_SINGLE("IN_1R switch", LEFT_PGA_SEL_2, 1, 0x1, 1), +}; + +/* Right input selection, Single Ended inputs and Differential inputs */ +static const struct snd_kcontrol_new right_input_mixer_controls[] = { + SOC_DAPM_SINGLE("IN_1R switch", RIGHT_PGA_SEL_1, 1, 0x1, 1), + SOC_DAPM_SINGLE("IN_2R switch", RIGHT_PGA_SEL_1, 3, 0x1, 1), + SOC_DAPM_SINGLE("IN_3R switch", RIGHT_PGA_SEL_1, 5, 0x1, 1), + SOC_DAPM_SINGLE("DIF_2R_3R switch", RIGHT_PGA_SEL_1, 7, 0x1, 1), + SOC_DAPM_SINGLE("DIF_1L_1R switch", RIGHT_PGA_SEL_2, 5, 0x1, 1), + SOC_DAPM_SINGLE("DIF_2L_3L switch", RIGHT_PGA_SEL_2, 3, 0x1, 1), + SOC_DAPM_SINGLE("IN_1L switch", RIGHT_PGA_SEL_2, 1, 0x1, 1), +}; + +/* Left Digital Mic input for left ADC */ +static const struct snd_kcontrol_new left_input_dmic_controls[] = { + SOC_DAPM_SINGLE("Left ADC switch", ADC_DIGITAL, 3, 0x1, 0), +}; + +/* Right Digital Mic input for Right ADC */ +static const struct snd_kcontrol_new right_input_dmic_controls[] = { + SOC_DAPM_SINGLE("Right ADC switch", ADC_DIGITAL, 2, 0x1, 0), +}; + +/* adc3xxx Widget structure */ +static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = { + + /* Left Input Selection */ + SND_SOC_DAPM_MIXER("Left Input Selection", SND_SOC_NOPM, 0, 0, + &left_input_mixer_controls[0], + ARRAY_SIZE(left_input_mixer_controls)), + /* Right Input Selection */ + SND_SOC_DAPM_MIXER("Right Input Selection", SND_SOC_NOPM, 0, 0, + &right_input_mixer_controls[0], + ARRAY_SIZE(right_input_mixer_controls)), + /* PGA selection */ + SND_SOC_DAPM_PGA("Left PGA", LEFT_APGA_CTRL, 7, 1, NULL, 0), + SND_SOC_DAPM_PGA("Right PGA", RIGHT_APGA_CTRL, 7, 1, NULL, 0), + + /* Digital Microphone Input Control for Left/Right ADC */ + SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0, + &left_input_dmic_controls[0], + ARRAY_SIZE(left_input_dmic_controls)), + SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0, + &right_input_dmic_controls[0], + ARRAY_SIZE(right_input_dmic_controls)), + + /* Left/Right ADC */ + SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC_DIGITAL, 7, 0), + SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC_DIGITAL, 6, 0), + + /* Inputs */ + SND_SOC_DAPM_INPUT("IN_1L"), + SND_SOC_DAPM_INPUT("IN_1R"), + SND_SOC_DAPM_INPUT("IN_2L"), + SND_SOC_DAPM_INPUT("IN_2R"), + SND_SOC_DAPM_INPUT("IN_3L"), + SND_SOC_DAPM_INPUT("IN_3R"), + SND_SOC_DAPM_INPUT("DIFL_1L_1R"), + SND_SOC_DAPM_INPUT("DIFL_2L_3L"), + SND_SOC_DAPM_INPUT("DIFL_2R_3R"), + SND_SOC_DAPM_INPUT("DIFR_1L_1R"), + SND_SOC_DAPM_INPUT("DIFR_2L_3L"), + SND_SOC_DAPM_INPUT("DIFR_2R_3R"), + SND_SOC_DAPM_INPUT("DMic_L"), + SND_SOC_DAPM_INPUT("DMic_R"), +}; + +/* DAPM Routing related array declaration */ +static const struct snd_soc_dapm_route intercon[] = { +/* Left input selection from switches */ + {"Left Input Selection", "IN_1L switch", "IN_1L"}, + {"Left Input Selection", "IN_2L switch", "IN_2L"}, + {"Left Input Selection", "IN_3L switch", "IN_3L"}, + {"Left Input Selection", "DIF_2L_3L switch", "DIFL_2L_3L"}, + {"Left Input Selection", "DIF_1L_1R switch", "DIFL_1L_1R"}, + {"Left Input Selection", "DIF_2R_3R switch", "DIFL_2R_3R"}, + {"Left Input Selection", "IN_1R switch", "IN_1R"}, + +/* Left input selection to left PGA */ + {"Left PGA", NULL, "Left Input Selection"}, + +/* Left PGA to left ADC */ + {"Left ADC", NULL, "Left PGA"}, + +/* Right input selection from switches */ + {"Right Input Selection", "IN_1R switch", "IN_1R"}, + {"Right Input Selection", "IN_2R switch", "IN_2R"}, + {"Right Input Selection", "IN_3R switch", "IN_3R"}, + {"Right Input Selection", "DIF_2R_3R switch", "DIFR_2R_3R"}, + {"Right Input Selection", "DIF_1L_1R switch", "DIFR_1L_1R"}, + {"Right Input Selection", "DIF_2L_3L switch", "DIFR_2L_3L"}, + {"Right Input Selection", "IN_1L switch", "IN_1L"}, + +/* Right input selection to right PGA */ + {"Right PGA", NULL, "Right Input Selection"}, + +/* Right PGA to right ADC */ + {"Right ADC", NULL, "Right PGA"}, + +/* Left DMic Input selection from switch */ + {"Left DMic Input", "Left ADC switch", "DMic_L"}, + +/* Left DMic to left ADC */ + {"Left ADC", NULL, "Left DMic Input"}, + +/* Right DMic Input selection from switch */ + {"Right DMic Input", "Right ADC switch", "DMic_R"}, + +/* Right DMic to right ADC */ + {"Right ADC", NULL, "Right DMic Input"}, +}; + +/* GPIO control. These are only used when the corresponding GPIO pin is + * configured accordingly. + */ +static const struct snd_kcontrol_new adc3xxx_gpio1_out_control[] = { + SOC_SINGLE("GPIO1 Output", GPIO1_CTRL, GPIO_CTRL_OUTPUT_CTRL_SHIFT, 1, 0) +}; + +static const struct snd_kcontrol_new adc3xxx_gpio2_out_control[] = { + SOC_SINGLE("GPIO2 Output", GPIO2_CTRL, GPIO_CTRL_OUTPUT_CTRL_SHIFT, 1, 0) +}; + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_parse_gpio_mode + * Purpose : Parse a gpio mode property as found in devicetree, and write + * the resulting gpio mode to cfg, if available. + *---------------------------------------------------------------------------- + */ +static int adc3xxx_parse_gpio_mode(struct adc3xxx_priv *adc3xxx, + const char *propname, unsigned int *cfg) +{ + struct device *dev = adc3xxx->dev; + struct device_node *np = dev->of_node; + unsigned int val; + + if (!of_property_read_u32(np, propname, &val)) { + if (val & ~15 || val == 7 || val >= 11) { + dev_err(dev, "Invalid property value for '%s'\n", propname); + return -EINVAL; + } + if (val == ADC3XXX_GPIO_GPI) + dev_warn(dev, "GPIO Input read not yet implemented\n"); + *cfg = val + 1; /* 0 => not set up, all others shifted +1 */ + } + return 0; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_parse_pll_mode + * Purpose : Parse the clock-mode property as received from devicetree + * or via set_sysclk callback in the clk_id parameter. + *---------------------------------------------------------------------------- + */ +static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode) +{ + if (val == ADC3XXX_PLL_ENABLE || val == ADC3XXX_PLL_BYPASS || + val == ADC3XXX_PLL_AUTO) { + *pll_mode = val; + return 0; + } else if (val == ADC3XXX_PLL_DONT_SET) + return 0; + + return -EINVAL; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_setup_pll + * Purpose : This function is to set up the adc3xxx PLL. + * + *---------------------------------------------------------------------------- + */ +static void adc3xxx_setup_pll(struct snd_soc_component *component, + int div_entry) +{ + int i = div_entry; + + /* P & R values */ + snd_soc_component_write(component, PLL_PROG_PR, + (adc3xxx_divs[i].pll_p << PLLP_SHIFT) | + (adc3xxx_divs[i].pll_r << PLLR_SHIFT)); + /* J value */ + snd_soc_component_write(component, PLL_PROG_J, + adc3xxx_divs[i].pll_j & PLLJ_MASK); + /* D value */ + snd_soc_component_write(component, PLL_PROG_D_LSB, + adc3xxx_divs[i].pll_d & PLLD_LSB_MASK); + snd_soc_component_write(component, PLL_PROG_D_MSB, + (adc3xxx_divs[i].pll_d >> 8) & PLLD_MSB_MASK); +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_hw_params + * Purpose : This function sets the sample rate and audio data word length. + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct adc3xxx_priv *adc3xxx = snd_soc_component_get_drvdata(component); + int i, width = 16; + u8 iface_len, bdiv; + + i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk, + params_rate(params), adc3xxx->pll_mode); + + if (i < 0) + return i; + + /* select data word length */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + iface_len = IFACE_16BITS; + width = 16; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface_len = IFACE_20BITS; + width = 20; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface_len = IFACE_24BITS; + width = 24; + break; + case SNDRV_PCM_FORMAT_S32_LE: + iface_len = IFACE_32BITS; + width = 32; + break; + default: + dev_err(component->dev, "Unsupported serial data format\n"); + return -EINVAL; + } + snd_soc_component_update_bits(component, INTERFACE_CTRL_1, WLENGTH_MASK, iface_len); + + if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */ + adc3xxx_setup_pll(component, i); + snd_soc_component_write(component, CLKGEN_MUX, USE_PLL); + adc3xxx->use_pll = 1; + } else { + snd_soc_component_write(component, CLKGEN_MUX, NO_PLL); + adc3xxx->use_pll = 0; + } + + /* Write divisor values; masks => bit 7 = 0 => divisor powered down */ + /* NADC */ + snd_soc_component_write(component, ADC_NADC, + adc3xxx_divs[i].nadc & NADC_MASK); + /* MADC */ + snd_soc_component_write(component, ADC_MADC, + adc3xxx_divs[i].madc & MADC_MASK); + /* AOSR */ + snd_soc_component_write(component, ADC_AOSR, + adc3xxx_divs[i].aosr & AOSR_MASK); + /* BDIV N Value */ + /* BCLK is set up to be derived from ADC_CLK */ + bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width); + /* BCLK enabled (when needed) in adc3xxx_set_bias_level() */ + snd_soc_component_write(component, BCLK_N_DIV, bdiv & BDIV_MASK); + + return 0; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_set_dai_sysclk + * Purpose : This function is to set the DAI system clock + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_component *component = codec_dai->component; + struct adc3xxx_priv *adc3xxx = snd_soc_component_get_drvdata(component); + int ret; + + ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode); + if (ret < 0) + return ret; + + adc3xxx->sysclk = freq; + dev_info(component->dev, "Set sysclk to %u Hz, %s\n", + freq, PLL_MODE_TEXT(adc3xxx->pll_mode)); + return 0; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_set_dai_fmt + * Purpose : This function is to set the DAI format + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_component *component = codec_dai->component; + struct adc3xxx_priv *adc3xxx = snd_soc_component_get_drvdata(component); + u8 clkdir = 0, format = 0; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + adc3xxx->master = 1; + clkdir = BCLK_MASTER | WCLK_MASTER; + break; + case SND_SOC_DAIFMT_CBS_CFS: + adc3xxx->master = 0; + break; + default: + dev_err(component->dev, "Invalid DAI master/slave interface\n"); + return -EINVAL; + } + + /* + * match both interface format and signal polarities since they + * are fixed + */ + switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) { + case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF: + format = FORMAT_I2S; + break; + case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF: + format = FORMAT_DSP; + break; + case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF: + format = FORMAT_DSP; + break; + case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF: + format = FORMAT_RJF; + break; + case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF: + format = FORMAT_LJF; + break; + default: + dev_err(component->dev, "Invalid DAI format\n"); + return -EINVAL; + } + + /* set clock direction and format */ + return snd_soc_component_update_bits(component, INTERFACE_CTRL_1, + clkdir | format, + CLKDIR_MASK | FORMAT_MASK); +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_set_bias_level + * Purpose : This function is to get triggered when dapm events occurs. + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) +{ + struct adc3xxx_priv *adc3xxx = snd_soc_component_get_drvdata(component); + + if (snd_soc_component_get_bias_level(component) == level) + return 0; + + /* all power is driven by DAPM system */ + switch (level) { + case SND_SOC_BIAS_ON: + /* Enable pll when needed */ + if (adc3xxx->use_pll) + snd_soc_component_update_bits(component, PLL_PROG_PR, + ENABLE_PLL, ENABLE_PLL); + + /* Switch on NADC Divider */ + snd_soc_component_update_bits(component, ADC_NADC, + ENABLE_NADC, ENABLE_NADC); + + /* Switch on MADC Divider */ + snd_soc_component_update_bits(component, ADC_MADC, + ENABLE_MADC, ENABLE_MADC); + + if (adc3xxx->master) + /* Switch on BCLK_N Divider */ + snd_soc_component_update_bits(component, BCLK_N_DIV, + ENABLE_BCLK, ENABLE_BCLK); + else + /* Switch off BCLK_N Divider */ + snd_soc_component_update_bits(component, BCLK_N_DIV, + ENABLE_BCLK, 0); + + if (adc3xxx->use_pll) + /* 10msec delay needed after PLL power-up to allow + * PLL and dividers to stabilize (datasheet p13). + */ + usleep_range(10000, 20000); + + break; + + /* partial On */ + case SND_SOC_BIAS_PREPARE: + break; + + /* Off, with power */ + case SND_SOC_BIAS_STANDBY: + /* Disable pll if used */ + if (adc3xxx->use_pll) + snd_soc_component_update_bits(component, PLL_PROG_PR, + ENABLE_PLL, 0); + + /* Switch off NADC Divider */ + snd_soc_component_update_bits(component, ADC_NADC, + ENABLE_NADC, 0); + + /* Switch off MADC Divider */ + snd_soc_component_update_bits(component, ADC_MADC, + ENABLE_MADC, 0); + + /* Switch off BCLK_N Divider */ + if (adc3xxx->master) + snd_soc_component_update_bits(component, BCLK_N_DIV, + ENABLE_BCLK, 0); + break; + + /* Off without power */ + case SND_SOC_BIAS_OFF: + + /* power off Left/Right ADC channels */ + snd_soc_component_update_bits(component, ADC_DIGITAL, + LADC_PWR_ON | RADC_PWR_ON, 0); + /* Turn off PLLs if used */ + if (adc3xxx->use_pll) + snd_soc_component_update_bits(component, PLL_PROG_PR, + ENABLE_PLL, 0); + + /* Switch off NADC Divider */ + snd_soc_component_update_bits(component, ADC_NADC, + ENABLE_NADC, 0); + + /* Switch off MADC Divider */ + snd_soc_component_update_bits(component, ADC_MADC, + ENABLE_MADC, 0); + + /* Switch off BCLK_N Divider */ + if (adc3xxx->master) + snd_soc_component_update_bits(component, BCLK_N_DIV, + ENABLE_BCLK, 0); + break; + } + + return 0; +} + +static struct snd_soc_dai_ops adc3xxx_dai_ops = { + .hw_params = adc3xxx_hw_params, + .set_sysclk = adc3xxx_set_dai_sysclk, + .set_fmt = adc3xxx_set_dai_fmt, +}; + +struct snd_soc_dai_driver adc3xxx_dai = { + .name = "tlv320adc3xxx-hifi", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = ADC3xxx_RATES, + .formats = ADC3xxx_FORMATS, + }, + .ops = &adc3xxx_dai_ops, +}; +EXPORT_SYMBOL_GPL(adc3xxx_dai); + +#define REGISTER_INIT(CODEC, MAP) \ + do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(MAP); i++) \ + snd_soc_component_write(CODEC, MAP[i].reg_offset, \ + MAP[i].reg_val); \ + } while (0) + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_init + * Purpose : This function is to initialize the adc3xxx driver + * register the mixer and dsp interfaces with the kernel. + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_init(struct snd_soc_component *component) +{ + struct adc3xxx_priv *adc3xxx = snd_soc_component_get_drvdata(component); + + /* Issue software reset to adc3xxx */ + snd_soc_component_write(component, RESET, SOFT_RESET); + + adc3xxx_set_bias_level(component, SND_SOC_BIAS_STANDBY); + + REGISTER_INIT(component, adc3xxx_reg_init); + if (adc3xxx->type == ADC3101) + REGISTER_INIT(component, adc3101_reg_init); + + if (adc3xxx->gpio1_cfg) { + unsigned int cfg = adc3xxx->gpio1_cfg - 1; + + snd_soc_component_update_bits(component, + GPIO1_CTRL, GPIO_CTRL_CFG_MASK, + cfg << GPIO_CTRL_CFG_SHIFT); + if (cfg == ADC3XXX_GPIO_GPO) { + snd_soc_add_component_controls(component, + adc3xxx_gpio1_out_control, + ARRAY_SIZE(adc3xxx_gpio1_out_control)); + } + } + + if (adc3xxx->gpio2_cfg) { + unsigned int cfg = adc3xxx->gpio2_cfg - 1; + + snd_soc_component_update_bits(component, + GPIO2_CTRL, GPIO_CTRL_CFG_MASK, + cfg << GPIO_CTRL_CFG_SHIFT); + if (cfg == ADC3XXX_GPIO_GPO) { + snd_soc_add_component_controls(component, + adc3xxx_gpio2_out_control, + ARRAY_SIZE(adc3xxx_gpio2_out_control)); + } + } + + //adc3xxx_set_bias_level(component, SND_SOC_BIAS_STANDBY); + + return 0; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_probe + * Purpose : This is first driver function called by the SoC core driver. + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_probe(struct snd_soc_component *component) +{ + struct adc3xxx_priv *adc3xxx = snd_soc_component_get_drvdata(component); + int ret = 0; + + ret = devm_gpio_request(component->dev, adc3xxx->rst_pin, "adc3xxx reset"); + if (ret < 0) { + dev_err(component->dev, "Failed to request rst_pin: %d\n", ret); + return ret; + } + + /* Reset adc3xxx codec */ + gpio_direction_output(adc3xxx->rst_pin, adc3xxx->rst_active); + usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */ + gpio_direction_output(adc3xxx->rst_pin, !adc3xxx->rst_active); + + ret = adc3xxx_init(component); + + if (ret < 0) { + dev_err(component->dev, "Failed to initialize ADC3xxx\n"); + devm_gpio_free(component->dev, adc3xxx->rst_pin); + } + + return ret; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_remove + * Purpose : to remove adc3xxx soc device + * + *---------------------------------------------------------------------------- + */ +static void adc3xxx_remove(struct snd_soc_component *component) +{ + adc3xxx_set_bias_level(component, SND_SOC_BIAS_OFF); +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_suspend + * Purpose : This function is to suspend the adc3xxx driver. + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_suspend(struct snd_soc_component *component) +{ + adc3xxx_set_bias_level(component, SND_SOC_BIAS_OFF); + + return 0; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_resume + * Purpose : This function is to resume the ADC3xxx driver + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_resume(struct snd_soc_component *component) +{ + snd_soc_component_cache_sync(component); + adc3xxx_set_bias_level(component, SND_SOC_BIAS_STANDBY); + + return 0; +} + +static const struct snd_soc_component_driver soc_component_dev_adc3xxx = { + .probe = adc3xxx_probe, + .remove = adc3xxx_remove, + .suspend = adc3xxx_suspend, + .resume = adc3xxx_resume, + .set_bias_level = adc3xxx_set_bias_level, + + .controls = adc3xxx_snd_controls, + .num_controls = ARRAY_SIZE(adc3xxx_snd_controls), + .dapm_widgets = adc3xxx_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets), + .dapm_routes = intercon, + .num_dapm_routes = ARRAY_SIZE(intercon), +}; + + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_i2c_probe + * Purpose : This function attaches the i2c client and initializes + * adc3xxx CODEC. + * + *---------------------------------------------------------------------------- + */ +static int adc3xxx_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct device *dev = &i2c->dev; + struct device_node *np = dev->of_node; + struct adc3xxx_priv *adc3xxx = NULL; + enum of_gpio_flags flags; + int rst_pin; + uint32_t val; + int ret; + + adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx_priv), GFP_KERNEL); + if (!adc3xxx) + return -ENOMEM; + adc3xxx->dev = dev; + + adc3xxx->mclk = devm_clk_get(dev, NULL); + if (IS_ERR(adc3xxx->mclk)) { + if (PTR_ERR(adc3xxx->mclk) != -ENOENT) + return PTR_ERR(adc3xxx->mclk); + /* Make a note that there is no mclk specified. */ + adc3xxx->mclk = NULL; + } else if (adc3xxx->mclk) { + ret = clk_prepare_enable(adc3xxx->mclk); + if (ret < 0) + return ret; + dev_info(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk)); + } + + if (!of_property_read_u32(np, "ti,pll-mode", &val)) { + ret = adc3xxx_parse_pll_mode(val, &adc3xxx->pll_mode); + if (ret < 0) + return ret; + dev_info(dev, "PLL mode set in devicetree: %s\n", + PLL_MODE_TEXT(adc3xxx->pll_mode)); + } + + adc3xxx_parse_gpio_mode(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio1_cfg); + adc3xxx_parse_gpio_mode(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio2_cfg); + + adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap); + if (IS_ERR(adc3xxx->regmap)) { + ret = PTR_ERR(adc3xxx->regmap); + return ret; + } + + rst_pin = of_get_gpio_flags(np, 0, &flags); + if (rst_pin < 0 || !gpio_is_valid(rst_pin)) + return -ENXIO; + + adc3xxx->rst_pin = rst_pin; + adc3xxx->rst_active = !(flags & OF_GPIO_ACTIVE_LOW); + adc3xxx->type = id->driver_data; + + i2c_set_clientdata(i2c, adc3xxx); + ret = snd_soc_register_component(dev, + &soc_component_dev_adc3xxx, &adc3xxx_dai, 1); + if (ret < 0) + dev_err(dev, "Failed to register codec\n"); + + return ret; +} + +/* + *---------------------------------------------------------------------------- + * Function : adc3xxx_i2c_remove + * Purpose : This function removes the i2c client and unregisters + * adc3xxx CODEC. + * + *---------------------------------------------------------------------------- + */ +static int __exit adc3xxx_i2c_remove(struct i2c_client *client) +{ + struct adc3xxx_priv *adc3xxx = i2c_get_clientdata(client); + + if (adc3xxx->mclk) + clk_disable_unprepare(adc3xxx->mclk); + snd_soc_unregister_component(&client->dev); + return 0; +} + +static const struct of_device_id tlv320adc3xxx_of_match[] = { + { .compatible = "ti,tlv320adc3001",}, + { .compatible = "ti,tlv320adc3101",}, + {}, +}; +MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match); + + +static const struct i2c_device_id adc3xxx_i2c_id[] = { + {"tlv320adc3001", ADC3001}, + {"tlv320adc3101", ADC3101}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id); + +/* machine i2c codec control layer */ +static struct i2c_driver adc3xxx_i2c_driver = { + .driver = { + .name = "tlv320adc3xxx-codec", + .of_match_table = tlv320adc3xxx_of_match, + }, + .probe = adc3xxx_i2c_probe, + .remove = adc3xxx_i2c_remove, + .id_table = adc3xxx_i2c_id, +}; +#endif + +static int __init tlv320adc3xxx_init(void) +{ + return i2c_add_driver(&adc3xxx_i2c_driver); +} + +static void __exit tlv320adc3xxx_exit(void) +{ + i2c_del_driver(&adc3xxx_i2c_driver); +} + +module_init(tlv320adc3xxx_init); +module_exit(tlv320adc3xxx_exit); + +MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver"); +MODULE_AUTHOR(" shahina.s(a)mistralsolutions.com "); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/tlv320adc3xxx.h b/sound/soc/codecs/tlv320adc3xxx.h new file mode 100644 index 000000000000..21276ad71876 --- /dev/null +++ b/sound/soc/codecs/tlv320adc3xxx.h @@ -0,0 +1,381 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov + * + * History: + * + * Author: "Shahina Shaik" < shahina.s(a)mistralsolutions.com > + * Copyright: (C) 2010 Mistral Solutions Pvt Ltd. + * + * Author: Dongge wu <dgwu(a)ambarella.com> + * 2015/10/28 - [Dongge wu] Created file + * Copyright (C) 2014-2018, Ambarella, Inc. + * + * Author: Ricard Wanderlof <ricardw(a)axis.com> + * 2020/11/05: Fixing driver for Linux 4.14: more clocking modes, etc. + * 2021/09/03: Porting to Linux 5.4, with enhancements (see tlv320adc3xxx.c). + * Copyright (C) 2021 Axis Communications AB + * + */ + +#ifndef _ADC3xxx_H +#define _ADC3xxx_H + +/* 8 bit mask value */ +#define ADC3xxx_8BITS_MASK 0xFF + +/* Enable slave / master mode for codec */ +#define ADC3xxx_MCBSP_SLAVE //codec master +//#undef ADC3xxx_MCBSP_SLAVE + +#define ADC3xxx_PAGE_SIZE 128 +#define ADC3xxx_REG(page, reg) ((page * ADC3xxx_PAGE_SIZE) + reg) + + +/****************************************************************************/ +/* Page 0 Registers */ +/****************************************************************************/ + +/* Page select register */ +#define PAGE_SELECT ADC3xxx_REG(0, 0) +/* Software reset register */ +#define RESET ADC3xxx_REG(0, 1) + +/* 2-3 Reserved */ + +/* PLL programming register B */ +#define CLKGEN_MUX ADC3xxx_REG(0, 4) +/* PLL P and R-Val */ +#define PLL_PROG_PR ADC3xxx_REG(0, 5) +/* PLL J-Val */ +#define PLL_PROG_J ADC3xxx_REG(0, 6) +/* PLL D-Val MSB */ +#define PLL_PROG_D_MSB ADC3xxx_REG(0, 7) +/* PLL D-Val LSB */ +#define PLL_PROG_D_LSB ADC3xxx_REG(0, 8) + +/* 9-17 Reserved */ + +/* ADC NADC */ +#define ADC_NADC ADC3xxx_REG(0, 18) +/* ADC MADC */ +#define ADC_MADC ADC3xxx_REG(0, 19) +/* ADC AOSR */ +#define ADC_AOSR ADC3xxx_REG(0, 20) +/* ADC IADC */ +#define ADC_IADC ADC3xxx_REG(0, 21) + +/* 23-24 Reserved */ + +/* CLKOUT MUX */ +#define CLKOUT_MUX ADC3xxx_REG(0, 25) +/* CLOCKOUT M divider value */ +#define CLKOUT_M_DIV ADC3xxx_REG(0, 26) +/*Audio Interface Setting Register 1*/ +#define INTERFACE_CTRL_1 ADC3xxx_REG(0, 27) +/* Data Slot Offset (Ch_Offset_1) */ +#define CH_OFFSET_1 ADC3xxx_REG(0, 28) +/* ADC interface control 2 */ +#define INTERFACE_CTRL_2 ADC3xxx_REG(0, 29) +/* BCLK N Divider */ +#define BCLK_N_DIV ADC3xxx_REG(0, 30) +/* Secondary audio interface control 1 */ +#define INTERFACE_CTRL_3 ADC3xxx_REG(0, 31) +/* Secondary audio interface control 2 */ +#define INTERFACE_CTRL_4 ADC3xxx_REG(0, 32) +/* Secondary audio interface control 3 */ +#define INTERFACE_CTRL_5 ADC3xxx_REG(0, 33) +/* I2S sync */ +#define I2S_SYNC ADC3xxx_REG(0, 34) + +/* 35 Reserved */ + +/* ADC flag register */ +#define ADC_FLAG ADC3xxx_REG(0, 36) +/* Data slot offset 2 (Ch_Offset_2) */ +#define CH_OFFSET_2 ADC3xxx_REG(0, 37) +/* I2S TDM control register */ +#define I2S_TDM_CTRL ADC3xxx_REG(0, 38) + +/* 39-41 Reserved */ + +/* Interrupt flags (overflow) */ +#define INTR_FLAG_1 ADC3xxx_REG(0, 42) +/* Interrupt flags (overflow) */ +#define INTR_FLAG_2 ADC3xxx_REG(0, 43) + +/* 44 Reserved */ + +/* Interrupt flags ADC */ +#define INTR_FLAG_ADC1 ADC3xxx_REG(0, 45) + +/* 46 Reserved */ + +/* Interrupt flags ADC */ +#define INTR_FLAG_ADC2 ADC3xxx_REG(0, 47) +/* INT1 interrupt control */ +#define INT1_CTRL ADC3xxx_REG(0, 48) +/* INT2 interrupt control */ +#define INT2_CTRL ADC3xxx_REG(0, 49) + +/* 50 Reserved */ + +/* DMCLK/GPIO2 control */ +#define GPIO2_CTRL ADC3xxx_REG(0, 51) +/* DMDIN/GPIO1 control */ +#define GPIO1_CTRL ADC3xxx_REG(0, 52) +/* DOUT Control */ +#define DOUT_CTRL ADC3xxx_REG(0, 53) + +/* 54-56 Reserved */ + +/* ADC sync control 1 */ +#define SYNC_CTRL_1 ADC3xxx_REG(0, 57) +/* ADC sync control 2 */ +#define SYNC_CTRL_2 ADC3xxx_REG(0, 58) +/* ADC CIC filter gain control */ +#define CIC_GAIN_CTRL ADC3xxx_REG(0, 59) + +/* 60 Reserved */ + +/* ADC processing block selection */ +#define PRB_SELECT ADC3xxx_REG(0, 61) +/* Programmable instruction mode control bits */ +#define INST_MODE_CTRL ADC3xxx_REG(0, 62) + +/* 63-79 Reserved */ + +/* Digital microphone polarity control */ +#define MIC_POLARITY_CTRL ADC3xxx_REG(0, 80) +/* ADC Digital */ +#define ADC_DIGITAL ADC3xxx_REG(0, 81) +/* ADC Fine Gain Adjust */ +#define ADC_FGA ADC3xxx_REG(0, 82) +/* Left ADC Channel Volume Control */ +#define LADC_VOL ADC3xxx_REG(0, 83) +/* Right ADC Channel Volume Control */ +#define RADC_VOL ADC3xxx_REG(0, 84) +/* ADC phase compensation */ +#define ADC_PHASE_COMP ADC3xxx_REG(0, 85) +/* Left Channel AGC Control Register 1 */ +#define LEFT_CHN_AGC_1 ADC3xxx_REG(0, 86) +/* Left Channel AGC Control Register 2 */ +#define LEFT_CHN_AGC_2 ADC3xxx_REG(0, 87) +/* Left Channel AGC Control Register 3 */ +#define LEFT_CHN_AGC_3 ADC3xxx_REG(0, 88) +/* Left Channel AGC Control Register 4 */ +#define LEFT_CHN_AGC_4 ADC3xxx_REG(0, 89) +/* Left Channel AGC Control Register 5 */ +#define LEFT_CHN_AGC_5 ADC3xxx_REG(0, 90) +/* Left Channel AGC Control Register 6 */ +#define LEFT_CHN_AGC_6 ADC3xxx_REG(0, 91) +/* Left Channel AGC Control Register 7 */ +#define LEFT_CHN_AGC_7 ADC3xxx_REG(0, 92) +/* Left AGC gain */ +#define LEFT_AGC_GAIN ADC3xxx_REG(0, 93) +/* Right Channel AGC Control Register 1 */ +#define RIGHT_CHN_AGC_1 ADC3xxx_REG(0, 94) +/* Right Channel AGC Control Register 2 */ +#define RIGHT_CHN_AGC_2 ADC3xxx_REG(0, 95) +/* Right Channel AGC Control Register 3 */ +#define RIGHT_CHN_AGC_3 ADC3xxx_REG(0, 96) +/* Right Channel AGC Control Register 4 */ +#define RIGHT_CHN_AGC_4 ADC3xxx_REG(0, 97) +/* Right Channel AGC Control Register 5 */ +#define RIGHT_CHN_AGC_5 ADC3xxx_REG(0, 98) +/* Right Channel AGC Control Register 6 */ +#define RIGHT_CHN_AGC_6 ADC3xxx_REG(0, 99) +/* Right Channel AGC Control Register 7 */ +#define RIGHT_CHN_AGC_7 ADC3xxx_REG(0, 100) +/* Right AGC gain */ +#define RIGHT_AGC_GAIN ADC3xxx_REG(0, 101) + +/* 102-127 Reserved */ + +/****************************************************************************/ +/* Page 1 Registers */ +/****************************************************************************/ +/* 1-25 Reserved */ + +/* Dither control */ +#define DITHER_CTRL ADC3xxx_REG(1, 26) + +/* 27-50 Reserved */ + +/* MICBIAS Configuration Register */ +#define MICBIAS_CTRL ADC3xxx_REG(1, 51) +/* Left ADC input selection for Left PGA */ +#define LEFT_PGA_SEL_1 ADC3xxx_REG(1, 52) + +/* 53 Reserved */ + +/* Right ADC input selection for Left PGA */ +#define LEFT_PGA_SEL_2 ADC3xxx_REG(1, 54) +/* Right ADC input selection for right PGA */ +#define RIGHT_PGA_SEL_1 ADC3xxx_REG(1, 55) + +/* 56 Reserved */ + +/* Right ADC input selection for right PGA */ +#define RIGHT_PGA_SEL_2 ADC3xxx_REG(1, 57) + +/* 58 Reserved */ + +/* Left analog PGA settings */ +#define LEFT_APGA_CTRL ADC3xxx_REG(1, 59) +/* Right analog PGA settings */ +#define RIGHT_APGA_CTRL ADC3xxx_REG(1, 60) +/* ADC Low current Modes */ +#define LOW_CURRENT_MODES ADC3xxx_REG(1, 61) +/* ADC analog PGA flags */ +#define ANALOG_PGA_FLAGS ADC3xxx_REG(1, 62) + +/* 63-127 Reserved */ + +/****************************************************************************/ +/* Macros and definitions */ +/****************************************************************************/ + +#define ADC3xxx_RATES SNDRV_PCM_RATE_8000_96000 +#define ADC3xxx_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) + +/* bits defined for easy usage */ +#define D7 (0x01 << 7) +#define D6 (0x01 << 6) +#define D5 (0x01 << 5) +#define D4 (0x01 << 4) +#define D3 (0x01 << 3) +#define D2 (0x01 << 2) +#define D1 (0x01 << 1) +#define D0 (0x01 << 0) + +/****************************************************************************/ +/* ADC3xxx Register bits */ +/****************************************************************************/ +/* PLL Enable bits */ +#define ENABLE_PLL D7 +#define ENABLE_NADC D7 +#define ENABLE_MADC D7 +#define ENABLE_BCLK D7 + +/* Power bits */ +#define LADC_PWR_ON D7 +#define RADC_PWR_ON D6 + +#define SOFT_RESET D0 +#define BCLK_MASTER D3 +#define WCLK_MASTER D2 + +/* Interface register masks */ +#define FORMAT_MASK (D7|D6) +#define FORMAT_SHIFT 6 +#define WLENGTH_MASK (D5|D4) +#define WLENGTH_SHIFT 4 +#define CLKDIR_MASK (D3|D2) +#define CLKDIR_SHIFT 2 + +/* Interface register bit patterns */ +#define FORMAT_I2S (0 << FORMAT_SHIFT) +#define FORMAT_DSP (1 << FORMAT_SHIFT) +#define FORMAT_RJF (2 << FORMAT_SHIFT) +#define FORMAT_LJF (3 << FORMAT_SHIFT) + +#define IFACE_16BITS (0 << WLENGTH_SHIFT) +#define IFACE_20BITS (1 << WLENGTH_SHIFT) +#define IFACE_24BITS (2 << WLENGTH_SHIFT) +#define IFACE_32BITS (3 << WLENGTH_SHIFT) + +/* PLL P/R bit offsets */ +#define PLLP_SHIFT 4 +#define PLLR_SHIFT 0 +#define PLL_PR_MASK 0x7F +#define PLLJ_MASK 0x3F +#define PLLD_MSB_MASK 0x3F +#define PLLD_LSB_MASK 0xFF +#define NADC_MASK 0x7F +#define MADC_MASK 0x7F +#define AOSR_MASK 0xFF +#define IADC_MASK 0xFF +#define BDIV_MASK 0x7F + +/* PLL_CLKIN bits */ +#define PLL_CLKIN_SHIFT 2 +#define PLL_CLKIN_MCLK 0x0 +#define PLL_CLKIN_BCLK 0x1 +#define PLL_CLKIN_ZERO 0x3 + +/* CODEC_CLKIN bits */ +#define CODEC_CLKIN_SHIFT 0 +#define CODEC_CLKIN_MCLK 0x0 +#define CODEC_CLKIN_BCLK 0x1 +#define CODEC_CLKIN_PLL_CLK 0x3 + +#define USE_PLL ((PLL_CLKIN_MCLK << PLL_CLKIN_SHIFT) | \ + (CODEC_CLKIN_PLL_CLK << CODEC_CLKIN_SHIFT)) +#define NO_PLL ((PLL_CLKIN_ZERO << PLL_CLKIN_SHIFT) | \ + (CODEC_CLKIN_MCLK << CODEC_CLKIN_SHIFT)) + +/* Analog PGA control bits */ +#define LPGA_MUTE D7 +#define RPGA_MUTE D7 + +#define LPGA_GAIN_MASK 0x7F +#define RPGA_GAIN_MASK 0x7F + +/* ADC current modes */ +#define ADC_LOW_CURR_MODE D0 + +/* Left ADC Input selection bits */ +#define LCH_SEL1_SHIFT 0 +#define LCH_SEL2_SHIFT 2 +#define LCH_SEL3_SHIFT 4 +#define LCH_SEL4_SHIFT 6 + +#define LCH_SEL1X_SHIFT 0 +#define LCH_SEL2X_SHIFT 2 +#define LCH_SEL3X_SHIFT 4 +#define LCH_COMMON_MODE D6 +#define BYPASS_LPGA D7 + +/* Right ADC Input selection bits */ +#define RCH_SEL1_SHIFT 0 +#define RCH_SEL2_SHIFT 2 +#define RCH_SEL3_SHIFT 4 +#define RCH_SEL4_SHIFT 6 + +#define RCH_SEL1X_SHIFT 0 +#define RCH_SEL2X_SHIFT 2 +#define RCH_SEL3X_SHIFT 4 +#define RCH_COMMON_MODE D6 +#define BYPASS_RPGA D7 + +/* MICBIAS control bits */ +#define MICBIAS1_SHIFT 5 +#define MICBIAS2_SHIFT 3 + +#define ADC_MAX_VOLUME 64 +#define ADC_POS_VOL 24 + +/* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */ +#define GPIO_CTRL_CFG_MASK (D2 | D3 | D4 | D5) +#define GPIO_CTRL_CFG_SHIFT 2 +#define GPIO_CTRL_OUTPUT_CTRL D0 +#define GPIO_CTRL_OUTPUT_CTRL_SHIFT 0 +#define GPIO_CTRL_INPUT_VALUE D1 +#define GPIO_CTRL_INPUT_VALUE_SHIFT 1 + +/****************** RATES TABLE FOR ADC3xxx ************************/ +struct adc3xxx_rate_divs { + u32 mclk; + u32 rate; + u8 pll_p; + u8 pll_r; + u8 pll_j; + u16 pll_d; + u8 nadc; + u8 madc; + u8 aosr; +}; + +#endif /* _ADC3xxx_H */ -- 2.20.1 -- Ricard Wolf Wanderlof ricardw(at)axis.com Axis Communications AB, Lund, Sweden www.axis.com Phone +46 46 272 2016 Fax +46 46 13 61 30

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