March 2020 - Alsa-devel - mailman.alsa-project.org

[PATCH 0/3] Add topologies for generic HDA DSP machine driver
by Mateusz Gorski 25 Mar '20

25 Mar '20

The set of patches adds 3 topology conf files for HDA DSP generic machine driver. These topologies cover all three possible configurations: - no DMIC - 2 channel DMIC array - 4 channel DMIC array Mateusz Gorski (3): topology: Add topology conf for generic HDA DSP machine driver for devices without DMIC array topology: Add topology conf for generic HDA DSP machine driver for devices with 2 channel DMIC array topology: Add topology conf for generic HDA DSP machine driver for devices with 4 channel DMIC array topology/hdadsp/hda_dsp_DMIC_2ch.conf | 7453 +++++++++++++++++++++++++ topology/hdadsp/hda_dsp_DMIC_4ch.conf | 7453 +++++++++++++++++++++++++ topology/hdadsp/hda_dsp_noDMIC.conf | 6763 ++++++++++++++++++++++ 3 files changed, 21669 insertions(+) create mode 100644 topology/hdadsp/hda_dsp_DMIC_2ch.conf create mode 100644 topology/hdadsp/hda_dsp_DMIC_4ch.conf create mode 100644 topology/hdadsp/hda_dsp_noDMIC.conf -- 2.17.1

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[PATCH 0/3] Add topologies for generic HDA DSP machine driver
by Mateusz Gorski 25 Mar '20

25 Mar '20

From: Mateusz Gorski <mateusz.gorski(a)intel.com> The set of patches adds 3 topology conf files for HDA DSP generic machine driver. These topologies cover all three possible configurations: - no DMIC - 2 channel DMIC array - 4 channel DMIC array Mateusz Gorski (3): topology: Add topology conf for generic HDA DSP machine driver for devices without DMIC array topology: Add topology conf for generic HDA DSP machine driver for devices with 2 channel DMIC array topology: Add topology conf for generic HDA DSP machine driver for devices with 4 channel DMIC array topology/hdadsp/hda_dsp_DMIC_2ch.conf | 7453 +++++++++++++++++++++++++ topology/hdadsp/hda_dsp_DMIC_4ch.conf | 7453 +++++++++++++++++++++++++ topology/hdadsp/hda_dsp_noDMIC.conf | 6763 ++++++++++++++++++++++ 3 files changed, 21669 insertions(+) create mode 100644 topology/hdadsp/hda_dsp_DMIC_2ch.conf create mode 100644 topology/hdadsp/hda_dsp_DMIC_4ch.conf create mode 100644 topology/hdadsp/hda_dsp_noDMIC.conf -- 2.17.1

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[PATCH v2] topology: Add topology file for generic HDA DSP machine driver
by Mateusz Gorski 25 Mar '20

25 Mar '20

Provide conf file with reference topology for generic HDA DSP machine driver. Signed-off-by: Mateusz Gorski <mateusz.gorski(a)linux.intel.com> --- Changes in v2: - dmic01_hifi widget ceased to exist, routes link directly to DMIC01 Rx - simplified frontend dai link names for HDMI playback routes and DMIC capture route topology/hdadsp/hda_dsp.conf | 7237 ++++++++++++++++++++++++++++++++++ 1 file changed, 7237 insertions(+) create mode 100644 topology/hdadsp/hda_dsp.conf diff --git a/topology/hdadsp/hda_dsp.conf b/topology/hdadsp/hda_dsp.conf new file mode 100644 index 0000000..559cf4e --- /dev/null +++ b/topology/hdadsp/hda_dsp.conf @@ -0,0 +1,7237 @@ + +SectionVendorTokens."skl_tokens" { + SKL_TKN_UUID "1" + SKL_TKN_U8_NUM_BLOCKS "2" + SKL_TKN_U8_BLOCK_TYPE "3" + SKL_TKN_U8_IN_PIN_TYPE "4" + SKL_TKN_U8_OUT_PIN_TYPE "5" + SKL_TKN_U8_DYN_IN_PIN "6" + SKL_TKN_U8_DYN_OUT_PIN "7" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "9" + SKL_TKN_U8_TIME_SLOT "10" + SKL_TKN_U8_CORE_ID "11" + SKL_TKN_U8_MODULE_TYPE "12" + SKL_TKN_U8_CONN_TYPE "13" + SKL_TKN_U8_DEV_TYPE "14" + SKL_TKN_U8_HW_CONN_TYPE "15" + SKL_TKN_U16_MOD_INST_ID "16" + SKL_TKN_U16_BLOCK_SIZE "17" + SKL_TKN_U32_MAX_MCPS "18" + SKL_TKN_U32_MEM_PAGES "19" + SKL_TKN_U32_OBS "20" + SKL_TKN_U32_IBS "21" + SKL_TKN_U32_VBUS_ID "22" + SKL_TKN_U32_PARAMS_FIXUP "23" + SKL_TKN_U32_CONVERTER "24" + SKL_TKN_U32_PIPE_ID "25" + SKL_TKN_U32_PIPE_CONN_TYPE "26" + SKL_TKN_U32_PIPE_PRIORITY "27" + SKL_TKN_U32_PIPE_MEM_PGS "28" + SKL_TKN_U32_DIR_PIN_COUNT "29" + SKL_TKN_U32_FMT_CH "30" + SKL_TKN_U32_FMT_FREQ "31" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "33" + SKL_TKN_U32_FMT_CH_CONFIG "34" + SKL_TKN_U32_FMT_INTERLEAVE "35" + SKL_TKN_U32_FMT_SAMPLE_TYPE "36" + SKL_TKN_U32_FMT_CH_MAP "37" + SKL_TKN_U32_PIN_MOD_ID "38" + SKL_TKN_U32_PIN_INST_ID "39" + SKL_TKN_U32_MOD_SET_PARAMS "40" + SKL_TKN_U32_MOD_PARAM_ID "41" + SKL_TKN_U32_CAPS_SET_PARAMS "42" + SKL_TKN_U32_CAPS_PARAMS_ID "43" + SKL_TKN_U32_CAPS_SIZE "44" + SKL_TKN_U32_PROC_DOMAIN "45" + SKL_TKN_U32_LIB_COUNT "46" + SKL_TKN_STR_LIB_NAME "47" + SKL_TKN_U32_PMODE "48" + SKL_TKN_U32_D0I3_CAPS "49" + SKL_TKN_U32_DMA_BUF_SIZE "50" + SKL_TKN_U32_PIPE_DIRECTION "51" + SKL_TKN_U32_PIPE_CONFIG_ID "52" + SKL_TKN_U32_NUM_CONFIGS "53" + SKL_TKN_U32_PATH_MEM_PGS "54" + SKL_TKN_U32_CFG_FREQ "55" + SKL_TKN_U8_CFG_CHAN "56" + SKL_TKN_U8_CFG_BPS "57" + SKL_TKN_CFG_MOD_RES_ID "58" + SKL_TKN_CFG_MOD_FMT_ID "59" + SKL_TKN_U8_NUM_MOD "60" + SKL_TKN_MM_U8_MOD_IDX "61" + SKL_TKN_MM_U8_NUM_RES "62" + SKL_TKN_MM_U8_NUM_INTF "63" + SKL_TKN_MM_U32_RES_ID "64" + SKL_TKN_MM_U32_CPS "65" + SKL_TKN_MM_U32_DMA_SIZE "66" + SKL_TKN_MM_U32_CPC "67" + SKL_TKN_MM_U32_RES_PIN_ID "68" + SKL_TKN_MM_U32_INTF_PIN_ID "69" + SKL_TKN_MM_U32_PIN_BUF "70" + SKL_TKN_MM_U32_FMT_ID "71" + SKL_TKN_MM_U32_NUM_IN_FMT "72" + SKL_TKN_MM_U32_NUM_OUT_FMT "73" + SKL_TKN_U32_ASTATE_IDX "74" + SKL_TKN_U32_ASTATE_COUNT "75" + SKL_TKN_U32_ASTATE_KCPS "76" + SKL_TKN_U32_ASTATE_CLK_SRC "77" + SKL_TKN_U32_DMACTRL_CFG_IDX "82" + SKL_TKN_U32_DMACTRL_CFG_SIZE "83" + SKL_TKN_U32_DMA_IDX "84" + SKL_TKN_U32_DMA_TYPE "85" + SKL_TKN_U32_DMA_SIZE "86" + SKL_TKN_U32_DMA_MAX_SIZE "87" + SKL_TKN_U32_DMA_MIN_SIZE "88" + SKL_TKN_U32_SCH_TYPE "89" + SKL_TKN_U32_SCH_SIZE "90" + SKL_TKN_U32_SCH_SYS_TICK_MUL "91" + SKL_TKN_U32_SCH_SYS_TICK_DIV "92" + SKL_TKN_U32_SCH_SYS_TICK_LL_SRC "93" + SKL_TKN_U32_SCH_SYS_TICK_CFG_LEN "94" + SKL_TKN_U32_SCH_SYS_TICK_CFG "95" + SKL_TKN_U32_FMT_CFG_IDX "96" +} + +SectionVendorTuples."mod_type_data_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "5284" + } +} + +SectionData."mod_type_data_size_desc" { + tuples "mod_type_data_size_desc" +} + +SectionVendorTuples."mod_type_data" { + tokens "skl_tokens" + + tuples."byte.u8_num_mod" { + SKL_TKN_U8_NUM_MOD "5" + } + + tuples."uuid.mod_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_mod_type_0" { + SKL_TKN_MM_U8_MOD_IDX "0" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "3" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_0_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2666000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2666" + } + + tuples."word.u32_mod_type_0_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_0_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_0_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_0_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_0_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_1" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_mod_type_1" { + SKL_TKN_MM_U8_MOD_IDX "1" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_1_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1521000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "1521" + } + + tuples."word.u32_mod_type_1_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_1_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_1_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_1_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_1_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_2" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_mod_type_2" { + SKL_TKN_MM_U8_MOD_IDX "2" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "4" + SKL_TKN_MM_U8_NUM_RES "13" + SKL_TKN_MM_U8_NUM_INTF "13" + } + + tuples."word.u32_mod_type_2_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2581000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "384" + SKL_TKN_MM_U32_CPC "2581" + } + + tuples."word.u32_mod_type_2_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_1" { + SKL_TKN_MM_U32_RES_ID "1" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_2" { + SKL_TKN_MM_U32_RES_ID "2" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_2_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_2_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_3" { + SKL_TKN_MM_U32_RES_ID "3" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "4473000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "4473" + } + + tuples."word.u32_mod_type_2_res_3_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_3_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_4" { + SKL_TKN_MM_U32_RES_ID "4" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "384" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_4_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_4_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_5" { + SKL_TKN_MM_U32_RES_ID "5" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_5_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_5_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_6" { + SKL_TKN_MM_U32_RES_ID "6" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_OBS "768" + SKL_TKN_MM_U32_DMA_SIZE "1536" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_6_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_6_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_7" { + SKL_TKN_MM_U32_RES_ID "7" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "1536" + SKL_TKN_U32_OBS "1536" + SKL_TKN_MM_U32_DMA_SIZE "3072" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_7_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "1536" + } + + tuples."word.u32_mod_type_2_res_7_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "1536" + } + + tuples."word.u32_mod_type_2_res_8" { + SKL_TKN_MM_U32_RES_ID "8" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "579000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "579" + } + + tuples."word.u32_mod_type_2_res_8_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_8_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_9" { + SKL_TKN_MM_U32_RES_ID "9" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_9_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_9_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_10" { + SKL_TKN_MM_U32_RES_ID "10" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "384768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_10_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_10_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_11" { + SKL_TKN_MM_U32_RES_ID "11" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "384768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_11_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_11_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_12" { + SKL_TKN_MM_U32_RES_ID "12" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "384768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_12_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_12_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_1" { + SKL_TKN_MM_U32_FMT_ID "1" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_2" { + SKL_TKN_MM_U32_FMT_ID "2" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_2_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_2_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_3" { + SKL_TKN_MM_U32_FMT_ID "3" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_3_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_3_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_4" { + SKL_TKN_MM_U32_FMT_ID "4" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_4_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_4_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_5" { + SKL_TKN_MM_U32_FMT_ID "5" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_5_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_5_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_6" { + SKL_TKN_MM_U32_FMT_ID "6" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_6_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "6" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "8" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4283707920" + } + + tuples."word.u32_mod_type_2_intf_6_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "6" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "8" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4283707920" + } + + tuples."word.u32_mod_type_2_intf_7" { + SKL_TKN_MM_U32_FMT_ID "7" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_7_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "8" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "14" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "1985229328" + } + + tuples."word.u32_mod_type_2_intf_7_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "8" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "14" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "1985229328" + } + + tuples."word.u32_mod_type_2_intf_8" { + SKL_TKN_MM_U32_FMT_ID "8" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_8_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_8_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_9" { + SKL_TKN_MM_U32_FMT_ID "9" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_9_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_9_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_10" { + SKL_TKN_MM_U32_FMT_ID "10" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_10_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_10_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_11" { + SKL_TKN_MM_U32_FMT_ID "11" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_11_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_11_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_12" { + SKL_TKN_MM_U32_FMT_ID "12" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_12_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_12_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_3" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."byte.u8_mod_type_3" { + SKL_TKN_MM_U8_MOD_IDX "3" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_3_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "100000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2106" + } + + tuples."word.u32_mod_type_3_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_3_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_3_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_3_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_3_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_4" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."byte.u8_mod_type_4" { + SKL_TKN_MM_U8_MOD_IDX "4" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_4_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "4" + SKL_TKN_MM_U32_CPS "100000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "10157" + } + + tuples."word.u32_mod_type_4_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_4_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_4_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_4_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_4_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } +} + +SectionData."mod_type_data" { + tuples "mod_type_data" +} + +SectionVendorTuples."media0_in cpr 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in cpr 0 num_desc" { + tuples "media0_in cpr 0 num_desc" +} + +SectionVendorTuples."media0_in cpr 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media0_in cpr 0_size_desc" { + tuples "media0_in cpr 0_size_desc" +} + +SectionVendorTuples."media0_in cpr 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "7" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media0_in cpr 0" { + tuples "media0_in cpr 0" +} + +SectionWidget."media0_in cpr 0" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media0_in cpr 0 num_desc" + "media0_in cpr 0_size_desc" + "media0_in cpr 0" + ] +} + +SectionVendorTuples."media0_in updwmix 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in updwmix 0 num_desc" { + tuples "media0_in updwmix 0 num_desc" +} + +SectionVendorTuples."media0_in updwmix 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "388" + } +} + +SectionData."media0_in updwmix 0_size_desc" { + tuples "media0_in updwmix 0_size_desc" +} + +SectionVendorTuples."media0_in updwmix 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "2" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "8" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } +} + +SectionData."media0_in updwmix 0" { + tuples "media0_in updwmix 0" +} + +SectionWidget."media0_in updwmix 0" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_in updwmix 0 num_desc" + "media0_in updwmix 0_size_desc" + "media0_in updwmix 0" + ] +} + +SectionVendorTuples."media0_in srcintc 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in srcintc 0 num_desc" { + tuples "media0_in srcintc 0 num_desc" +} + +SectionVendorTuples."media0_in srcintc 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "388" + } +} + +SectionData."media0_in srcintc 0_size_desc" { + tuples "media0_in srcintc 0_size_desc" +} + +SectionVendorTuples."media0_in srcintc 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "3" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "1" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "7" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } +} + +SectionData."media0_in srcintc 0" { + tuples "media0_in srcintc 0" +} + +SectionWidget."media0_in srcintc 0" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_in srcintc 0 num_desc" + "media0_in srcintc 0_size_desc" + "media0_in srcintc 0" + ] +} + +SectionVendorTuples."media0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in mi num_desc" { + tuples "media0_in mi num_desc" +} + +SectionVendorTuples."media0_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media0_in mi_size_desc" { + tuples "media0_in mi_size_desc" +} + +SectionVendorTuples."media0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "8" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media0_in mi" { + tuples "media0_in mi" +} + +SectionWidget."media0_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media0_in mi num_desc" + "media0_in mi_size_desc" + "media0_in mi" + ] +} + +SectionVendorTuples."codec0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_out mo num_desc" { + tuples "codec0_out mo num_desc" +} + +SectionVendorTuples."codec0_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec0_out mo_size_desc" { + tuples "codec0_out mo_size_desc" +} + +SectionVendorTuples."codec0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec0_out mo" { + tuples "codec0_out mo" +} + +SectionWidget."codec0_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media0_in mi Switch" + ] + + data [ + "codec0_out mo num_desc" + "codec0_out mo_size_desc" + "codec0_out mo" + ] +} + +SectionVendorTuples."codec0_out cpr 1 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_out cpr 1 num_desc" { + tuples "codec0_out cpr 1 num_desc" +} + +SectionVendorTuples."codec0_out cpr 1_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec0_out cpr 1_size_desc" { + tuples "codec0_out cpr 1_size_desc" +} + +SectionVendorTuples."codec0_out cpr 1" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec0_out cpr 1" { + tuples "codec0_out cpr 1" +} + +SectionWidget."codec0_out cpr 1" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec0_out cpr 1 num_desc" + "codec0_out cpr 1_size_desc" + "codec0_out cpr 1" + ] +} + +SectionWidget."codec0_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."media1_in cpr 2 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_in cpr 2 num_desc" { + tuples "media1_in cpr 2 num_desc" +} + +SectionVendorTuples."media1_in cpr 2_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media1_in cpr 2_size_desc" { + tuples "media1_in cpr 2_size_desc" +} + +SectionVendorTuples."media1_in cpr 2" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media1_in cpr 2" { + tuples "media1_in cpr 2" +} + +SectionWidget."media1_in cpr 2" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media1_in cpr 2 num_desc" + "media1_in cpr 2_size_desc" + "media1_in cpr 2" + ] +} + +SectionVendorTuples."media1_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_in mi num_desc" { + tuples "media1_in mi num_desc" +} + +SectionVendorTuples."media1_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media1_in mi_size_desc" { + tuples "media1_in mi_size_desc" +} + +SectionVendorTuples."media1_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media1_in mi" { + tuples "media1_in mi" +} + +SectionWidget."media1_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media1_in mi num_desc" + "media1_in mi_size_desc" + "media1_in mi" + ] +} + +SectionVendorTuples."codec1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_out mo num_desc" { + tuples "codec1_out mo num_desc" +} + +SectionVendorTuples."codec1_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec1_out mo_size_desc" { + tuples "codec1_out mo_size_desc" +} + +SectionVendorTuples."codec1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec1_out mo" { + tuples "codec1_out mo" +} + +SectionWidget."codec1_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media1_in mi Switch" + ] + + data [ + "codec1_out mo num_desc" + "codec1_out mo_size_desc" + "codec1_out mo" + ] +} + +SectionVendorTuples."codec1_out cpr 3 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_out cpr 3 num_desc" { + tuples "codec1_out cpr 3 num_desc" +} + +SectionVendorTuples."codec1_out cpr 3_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec1_out cpr 3_size_desc" { + tuples "codec1_out cpr 3_size_desc" +} + +SectionVendorTuples."codec1_out cpr 3" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec1_out cpr 3" { + tuples "codec1_out cpr 3" +} + +SectionWidget."codec1_out cpr 3" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec1_out cpr 3 num_desc" + "codec1_out cpr 3_size_desc" + "codec1_out cpr 3" + ] +} + +SectionWidget."codec1_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."media2_in cpr 4 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_in cpr 4 num_desc" { + tuples "media2_in cpr 4 num_desc" +} + +SectionVendorTuples."media2_in cpr 4_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media2_in cpr 4_size_desc" { + tuples "media2_in cpr 4_size_desc" +} + +SectionVendorTuples."media2_in cpr 4" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media2_in cpr 4" { + tuples "media2_in cpr 4" +} + +SectionWidget."media2_in cpr 4" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media2_in cpr 4 num_desc" + "media2_in cpr 4_size_desc" + "media2_in cpr 4" + ] +} + +SectionVendorTuples."media2_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_in mi num_desc" { + tuples "media2_in mi num_desc" +} + +SectionVendorTuples."media2_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media2_in mi_size_desc" { + tuples "media2_in mi_size_desc" +} + +SectionVendorTuples."media2_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media2_in mi" { + tuples "media2_in mi" +} + +SectionWidget."media2_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media2_in mi num_desc" + "media2_in mi_size_desc" + "media2_in mi" + ] +} + +SectionVendorTuples."codec2_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_out mo num_desc" { + tuples "codec2_out mo num_desc" +} + +SectionVendorTuples."codec2_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec2_out mo_size_desc" { + tuples "codec2_out mo_size_desc" +} + +SectionVendorTuples."codec2_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec2_out mo" { + tuples "codec2_out mo" +} + +SectionWidget."codec2_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media2_in mi Switch" + ] + + data [ + "codec2_out mo num_desc" + "codec2_out mo_size_desc" + "codec2_out mo" + ] +} + +SectionVendorTuples."codec2_out cpr 5 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_out cpr 5 num_desc" { + tuples "codec2_out cpr 5 num_desc" +} + +SectionVendorTuples."codec2_out cpr 5_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec2_out cpr 5_size_desc" { + tuples "codec2_out cpr 5_size_desc" +} + +SectionVendorTuples."codec2_out cpr 5" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec2_out cpr 5" { + tuples "codec2_out cpr 5" +} + +SectionWidget."codec2_out cpr 5" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec2_out cpr 5 num_desc" + "codec2_out cpr 5_size_desc" + "codec2_out cpr 5" + ] +} + +SectionWidget."codec2_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."codec0_in cpr 6 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_in cpr 6 num_desc" { + tuples "codec0_in cpr 6 num_desc" +} + +SectionVendorTuples."codec0_in cpr 6_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec0_in cpr 6_size_desc" { + tuples "codec0_in cpr 6_size_desc" +} + +SectionVendorTuples."codec0_in cpr 6" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "9" + SKL_TKN_CFG_MOD_FMT_ID "9" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec0_in cpr 6" { + tuples "codec0_in cpr 6" +} + +SectionWidget."codec0_in cpr 6" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec0_in cpr 6 num_desc" + "codec0_in cpr 6_size_desc" + "codec0_in cpr 6" + ] +} + +SectionVendorTuples."codec0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_in mi num_desc" { + tuples "codec0_in mi num_desc" +} + +SectionVendorTuples."codec0_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec0_in mi_size_desc" { + tuples "codec0_in mi_size_desc" +} + +SectionVendorTuples."codec0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec0_in mi" { + tuples "codec0_in mi" +} + +SectionWidget."codec0_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec0_in mi num_desc" + "codec0_in mi_size_desc" + "codec0_in mi" + ] +} + +SectionWidget."codec0_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_out mo num_desc" { + tuples "media0_out mo num_desc" +} + +SectionVendorTuples."media0_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media0_out mo_size_desc" { + tuples "media0_out mo_size_desc" +} + +SectionVendorTuples."media0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "7" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media0_out mo" { + tuples "media0_out mo" +} + +SectionWidget."media0_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec0_in mi Switch" + ] + + data [ + "media0_out mo num_desc" + "media0_out mo_size_desc" + "media0_out mo" + ] +} + +SectionVendorTuples."media0_out cpr 7 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_out cpr 7 num_desc" { + tuples "media0_out cpr 7 num_desc" +} + +SectionVendorTuples."media0_out cpr 7_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media0_out cpr 7_size_desc" { + tuples "media0_out cpr 7_size_desc" +} + +SectionVendorTuples."media0_out cpr 7" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "7" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "8" + SKL_TKN_CFG_MOD_FMT_ID "8" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media0_out cpr 7" { + tuples "media0_out cpr 7" +} + +SectionWidget."media0_out cpr 7" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_out cpr 7 num_desc" + "media0_out cpr 7_size_desc" + "media0_out cpr 7" + ] +} + +SectionVendorTuples."codec1_in cpr 8 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_in cpr 8 num_desc" { + tuples "codec1_in cpr 8 num_desc" +} + +SectionVendorTuples."codec1_in cpr 8_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec1_in cpr 8_size_desc" { + tuples "codec1_in cpr 8_size_desc" +} + +SectionVendorTuples."codec1_in cpr 8" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "8" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "2" + SKL_TKN_CFG_MOD_FMT_ID "2" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec1_in cpr 8" { + tuples "codec1_in cpr 8" +} + +SectionWidget."codec1_in cpr 8" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec1_in cpr 8 num_desc" + "codec1_in cpr 8_size_desc" + "codec1_in cpr 8" + ] +} + +SectionVendorTuples."codec1_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_in mi num_desc" { + tuples "codec1_in mi num_desc" +} + +SectionVendorTuples."codec1_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec1_in mi_size_desc" { + tuples "codec1_in mi_size_desc" +} + +SectionVendorTuples."codec1_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "8" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec1_in mi" { + tuples "codec1_in mi" +} + +SectionWidget."codec1_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec1_in mi num_desc" + "codec1_in mi_size_desc" + "codec1_in mi" + ] +} + +SectionWidget."codec1_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_out mo num_desc" { + tuples "media1_out mo num_desc" +} + +SectionVendorTuples."media1_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media1_out mo_size_desc" { + tuples "media1_out mo_size_desc" +} + +SectionVendorTuples."media1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "9" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media1_out mo" { + tuples "media1_out mo" +} + +SectionWidget."media1_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec1_in mi Switch" + ] + + data [ + "media1_out mo num_desc" + "media1_out mo_size_desc" + "media1_out mo" + ] +} + +SectionVendorTuples."media1_out cpr 9 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_out cpr 9 num_desc" { + tuples "media1_out cpr 9 num_desc" +} + +SectionVendorTuples."media1_out cpr 9_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media1_out cpr 9_size_desc" { + tuples "media1_out cpr 9_size_desc" +} + +SectionVendorTuples."media1_out cpr 9" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "9" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "3" + SKL_TKN_CFG_MOD_FMT_ID "3" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media1_out cpr 9" { + tuples "media1_out cpr 9" +} + +SectionWidget."media1_out cpr 9" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media1_out cpr 9 num_desc" + "media1_out cpr 9_size_desc" + "media1_out cpr 9" + ] +} + +SectionVendorTuples."codec2_in cpr 10 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_in cpr 10 num_desc" { + tuples "codec2_in cpr 10 num_desc" +} + +SectionVendorTuples."codec2_in cpr 10_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec2_in cpr 10_size_desc" { + tuples "codec2_in cpr 10_size_desc" +} + +SectionVendorTuples."codec2_in cpr 10" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "10" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "2" + SKL_TKN_CFG_MOD_FMT_ID "2" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec2_in cpr 10" { + tuples "codec2_in cpr 10" +} + +SectionWidget."codec2_in cpr 10" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec2_in cpr 10 num_desc" + "codec2_in cpr 10_size_desc" + "codec2_in cpr 10" + ] +} + +SectionVendorTuples."codec2_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_in mi num_desc" { + tuples "codec2_in mi num_desc" +} + +SectionVendorTuples."codec2_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec2_in mi_size_desc" { + tuples "codec2_in mi_size_desc" +} + +SectionVendorTuples."codec2_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "10" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec2_in mi" { + tuples "codec2_in mi" +} + +SectionWidget."codec2_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec2_in mi num_desc" + "codec2_in mi_size_desc" + "codec2_in mi" + ] +} + +SectionWidget."codec2_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media2_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_out mo num_desc" { + tuples "media2_out mo num_desc" +} + +SectionVendorTuples."media2_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media2_out mo_size_desc" { + tuples "media2_out mo_size_desc" +} + +SectionVendorTuples."media2_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "11" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "11" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media2_out mo" { + tuples "media2_out mo" +} + +SectionWidget."media2_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec2_in mi Switch" + ] + + data [ + "media2_out mo num_desc" + "media2_out mo_size_desc" + "media2_out mo" + ] +} + +SectionVendorTuples."media2_out cpr 11 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_out cpr 11 num_desc" { + tuples "media2_out cpr 11 num_desc" +} + +SectionVendorTuples."media2_out cpr 11_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media2_out cpr 11_size_desc" { + tuples "media2_out cpr 11_size_desc" +} + +SectionVendorTuples."media2_out cpr 11" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "11" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "11" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "3" + SKL_TKN_CFG_MOD_FMT_ID "3" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media2_out cpr 11" { + tuples "media2_out cpr 11" +} + +SectionWidget."media2_out cpr 11" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media2_out cpr 11 num_desc" + "media2_out cpr 11_size_desc" + "media2_out cpr 11" + ] +} + +SectionVendorTuples."hdmi1_out cpr 12 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi1_out cpr 12 num_desc" { + tuples "hdmi1_out cpr 12 num_desc" +} + +SectionVendorTuples."hdmi1_out cpr 12_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."hdmi1_out cpr 12_size_desc" { + tuples "hdmi1_out cpr 12_size_desc" +} + +SectionVendorTuples."hdmi1_out cpr 12" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "12" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "12" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "13" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi1_out cpr 12" { + tuples "hdmi1_out cpr 12" +} + +SectionWidget."hdmi1_out cpr 12" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi1_out cpr 12 num_desc" + "hdmi1_out cpr 12_size_desc" + "hdmi1_out cpr 12" + ] +} + +SectionVendorTuples."hdmi1_out cpr 13 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi1_out cpr 13 num_desc" { + tuples "hdmi1_out cpr 13 num_desc" +} + +SectionVendorTuples."hdmi1_out cpr 13_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."hdmi1_out cpr 13_size_desc" { + tuples "hdmi1_out cpr 13_size_desc" +} + +SectionVendorTuples."hdmi1_out cpr 13" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "13" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "12" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "12" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi1_out cpr 13" { + tuples "hdmi1_out cpr 13" +} + +SectionWidget."hdmi1_out cpr 13" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi1_out cpr 13 num_desc" + "hdmi1_out cpr 13_size_desc" + "hdmi1_out cpr 13" + ] +} + +SectionWidget."iDisp1_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."hdmi2_out cpr 14 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi2_out cpr 14 num_desc" { + tuples "hdmi2_out cpr 14 num_desc" +} + +SectionVendorTuples."hdmi2_out cpr 14_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."hdmi2_out cpr 14_size_desc" { + tuples "hdmi2_out cpr 14_size_desc" +} + +SectionVendorTuples."hdmi2_out cpr 14" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "14" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "13" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "15" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi2_out cpr 14" { + tuples "hdmi2_out cpr 14" +} + +SectionWidget."hdmi2_out cpr 14" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi2_out cpr 14 num_desc" + "hdmi2_out cpr 14_size_desc" + "hdmi2_out cpr 14" + ] +} + +SectionVendorTuples."hdmi2_out cpr 15 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi2_out cpr 15 num_desc" { + tuples "hdmi2_out cpr 15 num_desc" +} + +SectionVendorTuples."hdmi2_out cpr 15_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."hdmi2_out cpr 15_size_desc" { + tuples "hdmi2_out cpr 15_size_desc" +} + +SectionVendorTuples."hdmi2_out cpr 15" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "15" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "13" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "14" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi2_out cpr 15" { + tuples "hdmi2_out cpr 15" +} + +SectionWidget."hdmi2_out cpr 15" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi2_out cpr 15 num_desc" + "hdmi2_out cpr 15_size_desc" + "hdmi2_out cpr 15" + ] +} + +SectionWidget."iDisp2_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."hdmi3_out cpr 16 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi3_out cpr 16 num_desc" { + tuples "hdmi3_out cpr 16 num_desc" +} + +SectionVendorTuples."hdmi3_out cpr 16_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."hdmi3_out cpr 16_size_desc" { + tuples "hdmi3_out cpr 16_size_desc" +} + +SectionVendorTuples."hdmi3_out cpr 16" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "16" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "14" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "17" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi3_out cpr 16" { + tuples "hdmi3_out cpr 16" +} + +SectionWidget."hdmi3_out cpr 16" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi3_out cpr 16 num_desc" + "hdmi3_out cpr 16_size_desc" + "hdmi3_out cpr 16" + ] +} + +SectionVendorTuples."hdmi3_out cpr 17 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi3_out cpr 17 num_desc" { + tuples "hdmi3_out cpr 17 num_desc" +} + +SectionVendorTuples."hdmi3_out cpr 17_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."hdmi3_out cpr 17_size_desc" { + tuples "hdmi3_out cpr 17_size_desc" +} + +SectionVendorTuples."hdmi3_out cpr 17" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "17" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "14" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "16" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi3_out cpr 17" { + tuples "hdmi3_out cpr 17" +} + +SectionWidget."hdmi3_out cpr 17" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi3_out cpr 17 num_desc" + "hdmi3_out cpr 17_size_desc" + "hdmi3_out cpr 17" + ] +} + +SectionWidget."iDisp3_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."mch_cap_in cpr 18 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_in cpr 18 num_desc" { + tuples "mch_cap_in cpr 18 num_desc" +} + +SectionVendorTuples."mch_cap_in cpr 18_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."mch_cap_in cpr 18_size_desc" { + tuples "mch_cap_in cpr 18_size_desc" +} + +SectionVendorTuples."mch_cap_in cpr 18" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "1" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "18" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "0" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "15" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "11" + SKL_TKN_CFG_MOD_FMT_ID "11" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."mch_cap_in cpr 18" { + tuples "mch_cap_in cpr 18" +} + +SectionWidget."mch_cap_in cpr 18" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "mch_cap_in cpr 18 num_desc" + "mch_cap_in cpr 18_size_desc" + "mch_cap_in cpr 18" + ] +} + +SectionVendorTuples."mch_cap_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_in mi num_desc" { + tuples "mch_cap_in mi num_desc" +} + +SectionVendorTuples."mch_cap_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."mch_cap_in mi_size_desc" { + tuples "mch_cap_in mi_size_desc" +} + +SectionVendorTuples."mch_cap_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "15" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "18" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."mch_cap_in mi" { + tuples "mch_cap_in mi" +} + +SectionWidget."mch_cap_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "mch_cap_in mi num_desc" + "mch_cap_in mi_size_desc" + "mch_cap_in mi" + ] +} + +SectionWidget."DMIC01 Rx" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."mch_cap_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_out mo num_desc" { + tuples "mch_cap_out mo num_desc" +} + +SectionVendorTuples."mch_cap_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."mch_cap_out mo_size_desc" { + tuples "mch_cap_out mo_size_desc" +} + +SectionVendorTuples."mch_cap_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "16" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "19" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."mch_cap_out mo" { + tuples "mch_cap_out mo" +} + +SectionWidget."mch_cap_out mo" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + mixer [ + "mch_cap_in mi Switch" + ] + + data [ + "mch_cap_out mo num_desc" + "mch_cap_out mo_size_desc" + "mch_cap_out mo" + ] +} + +SectionVendorTuples."mch_cap_out cpr 19 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_out cpr 19 num_desc" { + tuples "mch_cap_out cpr 19 num_desc" +} + +SectionVendorTuples."mch_cap_out cpr 19_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."mch_cap_out cpr 19_size_desc" { + tuples "mch_cap_out cpr 19_size_desc" +} + +SectionVendorTuples."mch_cap_out cpr 19" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "19" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "16" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "12" + SKL_TKN_CFG_MOD_FMT_ID "12" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."mch_cap_out cpr 19" { + tuples "mch_cap_out cpr 19" +} + +SectionWidget."mch_cap_out cpr 19" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "mch_cap_out cpr 19 num_desc" + "mch_cap_out cpr 19_size_desc" + "mch_cap_out cpr 19" + ] +} + +SectionControlMixer."media0_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."media1_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."media2_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec0_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec1_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec2_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."mch_cap_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionGraph."Pipeline 1 Graph" { + index "0" + + lines [ + "media0_in cpr 0, , hda-dsp-analog-playback" + "media0_in updwmix 0, , media0_in cpr 0" + "media0_in srcintc 0, , media0_in updwmix 0" + "media0_in mi, , media0_in srcintc 0" + "codec0_out cpr 1, , codec0_out mo" + "codec0_out, , codec0_out cpr 1" + "media1_in cpr 2, , hda-dsp-digital-playback" + "media1_in mi, , media1_in cpr 2" + "codec1_out cpr 3, , codec1_out mo" + "codec1_out, , codec1_out cpr 3" + "media2_in cpr 4, , hda-dsp-alt-analog-playback" + "media2_in mi, , media2_in cpr 4" + "codec2_out cpr 5, , codec2_out mo" + "codec2_out, , codec2_out cpr 5" + "codec0_in cpr 6, , codec0_in" + "codec0_in mi, , codec0_in cpr 6" + "media0_out cpr 7, , media0_out mo" + "hda-dsp-audio-analog-capture, , media0_out cpr 7" + "codec1_in cpr 8, , codec1_in" + "codec1_in mi, , codec1_in cpr 8" + "media1_out cpr 9, , media1_out mo" + "hda-dsp-audio-digital-capture, , media1_out cpr 9" + "codec2_in cpr 10, , codec2_in" + "codec2_in mi, , codec2_in cpr 10" + "media2_out cpr 11, , media2_out mo" + "hda-dsp-audio-alt-analog-capture, , media2_out cpr 11" + "hdmi1_out cpr 12, , HDMI1 Playback" + "hdmi1_out cpr 13, , hdmi1_out cpr 12" + "iDisp1_out, , hdmi1_out cpr 13" + "hdmi2_out cpr 14, , HDMI2 Playback" + "hdmi2_out cpr 15, , hdmi2_out cpr 14" + "iDisp2_out, , hdmi2_out cpr 15" + "hdmi3_out cpr 16, , HDMI3 Playback" + "hdmi3_out cpr 17, , hdmi3_out cpr 16" + "iDisp3_out, , hdmi3_out cpr 17" + "mch_cap_in cpr 18, , DMIC01 Rx" + "mch_cap_in mi, , mch_cap_in cpr 18" + "mch_cap_out cpr 19, , mch_cap_out mo" + "DMIC-Capture, , mch_cap_out cpr 19" + "codec0_out mo, media0_in mi Switch, media0_in mi" + "codec1_out mo, media1_in mi Switch, media1_in mi" + "codec2_out mo, media2_in mi Switch, media2_in mi" + "media0_out mo, codec0_in mi Switch, codec0_in mi" + "media1_out mo, codec1_in mi Switch, codec1_in mi" + "media2_out mo, codec2_in mi Switch, codec2_in mi" + "mch_cap_out mo, mch_cap_in mi Switch, mch_cap_in mi" + ] +} + +SectionPCMCapabilities."hda-dsp-analog-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-analog-capture" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."Analog HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-analog-dai" { + id "0" + } + + pcm."playback" { + capabilities "hda-dsp-analog-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-analog-capture" + } +} + +SectionPCMCapabilities."hda-dsp-digital-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-digital-capture" { + formats "S24_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "24" +} + +SectionPCM."Digital HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-digital-dai" { + id "1" + } + + pcm."playback" { + capabilities "hda-dsp-digital-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-digital-capture" + } +} + +SectionPCMCapabilities."hda-dsp-alt-analog-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-alt-analog-capture" { + formats "S24_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "24" +} + +SectionPCM."Alt Analog HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-alt-analog-dai" { + id "2" + } + + pcm."playback" { + capabilities "hda-dsp-alt-analog-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-alt-analog-capture" + } +} + +SectionPCMCapabilities."HDMI1 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."HDMI1" { + index "0" + id "255" + + dai."hdmi1" { + id "3" + } + + pcm."playback" { + capabilities "HDMI1 Playback" + } +} + +SectionPCMCapabilities."HDMI2 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."HDMI2" { + index "0" + id "255" + + dai."hdmi2" { + id "4" + } + + pcm."playback" { + capabilities "HDMI2 Playback" + } +} + +SectionPCMCapabilities."HDMI3 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."HDMI3" { + index "0" + id "255" + + dai."hdmi3" { + id "5" + } + + pcm."playback" { + capabilities "HDMI3 Playback" + } +} + +SectionPCMCapabilities."DMIC-Capture" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."DMIC1" { + index "0" + id "0" + + dai."hda-dsp-dmic-dai" { + id "6" + } + + pcm."capture" { + capabilities "DMIC-Capture" + } +} + +SectionVendorTuples."manifest_data num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."manifest_data num_desc" { + tuples "manifest_data num_desc" +} + +SectionManifest."manifest_data" { + + data [ + "manifest_data num_desc" + "mod_type_data_size_desc" + "mod_type_data" + ] +} -- 2.17.1

3 6

[PATCH] ucm2: hdadsp: add basic ucm config
by Mateusz Gorski 25 Mar '20

25 Mar '20

Basic UCM configuration for HDA DSP generic enabling codec playback and capture on both HDA codec and DMIC ports. Signed-off-by: Mateusz Gorski <mateusz.gorski(a)linux.intel.com> --- ucm2/hdadsp/hdadsp.conf | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 ucm2/hdadsp/hdadsp.conf diff --git a/ucm2/hdadsp/hdadsp.conf b/ucm2/hdadsp/hdadsp.conf new file mode 100644 index 0000000..4e98545 --- /dev/null +++ b/ucm2/hdadsp/hdadsp.conf @@ -0,0 +1,16 @@ +# UCM for Intel CAVS platforms +# For Audio in HDA and DMIC mode + +ValueDefaults { + PlaybackChannels "2" + PlaybackPriority "1" + CaptureChannels "2" + CapturePriority "2" +} + +SectionDefaults [ + cdev "hw:hdadsp" + cset "name='codec0_out mo media0_in mi Switch' 1" + cset "name='media0_out mo codec0_in mi Switch' 1" + cset "name='mch_cap_out mo mch_cap_in mi Switch' 1" +] -- 2.17.1

4 9

[PATCH 0/2] ASoC: SOF: initialise work immediately
by Guennadi Liakhovetski 25 Mar '20

25 Mar '20

Fix uninitialised work errors by moving initialisation to directly after allocation. Guennadi Liakhovetski (2): ASoC: SOF: (cosmetic) use for_each_pcm_streams() in sof_dai_load() ASoC: SOF: fix uninitialised "work" with VirtIO sound/soc/sof/pcm.c | 4 +--- sound/soc/sof/sof-audio.h | 3 +++ sound/soc/sof/topology.c | 17 ++++++++++++----- 3 files changed, 16 insertions(+), 8 deletions(-) -- 1.9.3

3 10

[PATCH 0/4] ALSA: usb-audio: Option for delayed registration
by Takashi Iwai 25 Mar '20

25 Mar '20

Hi, USB-audio driver probes per USB insterface, and this used to be the cause of the missing device enumeration on user-space because the driver registers the device per interface probe. The recently added quirk allows the delayed registration to sync with the last known stream, but we must have far more such devices. This patch set adds a new option to let user specify the delayed registration device setup and also inform such devices at probe time. Takashi === Takashi Iwai (4): ALSA: usb-audio: Rewrite registration quirk handling ALSA: usb-audio: Add delayed_register option ALSA: usb-audio: Inform devices that need delayed registration ALSA: usb-audio: Update the documentation for the new delayed_register option Documentation/sound/alsa-configuration.rst | 13 ++++++++++ sound/usb/card.c | 28 ++++++++++++++++++++- sound/usb/quirks.c | 40 ++++++++++++++++++++++-------- sound/usb/quirks.h | 3 +-- sound/usb/stream.c | 3 +++ sound/usb/usbaudio.h | 1 + 6 files changed, 75 insertions(+), 13 deletions(-) -- 2.16.4

1 4

Re: [patch 10/22] EDAC: Convert to new X86 CPU match macros
by Luck, Tony 24 Mar '20

24 Mar '20

On Fri, Mar 20, 2020 at 02:13:55PM +0100, Thomas Gleixner wrote: > The new macro set has a consistent namespace and uses C99 initializers > instead of the grufty C89 ones. ^^^^^^ grufty? Did you mean crufty? Though I suppose grufty may work as well here: gruft. Noun. (uncountable) (dialect) the particles of soil that are spattered up onto grass by the rain. > > Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de> Tested the Broadwell EDAC driver. The other changes look good too. Acked-by: Tony Luck <tony.luck(a)intel.com>

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[PATCH 23/22] x86/smpboot: Remove the last ICPU() macro
by Borislav Petkov 24 Mar '20

24 Mar '20

--- From: Borislav Petkov <bp(a)suse.de> Now all is using the shiny new macros. Signed-off-by: Borislav Petkov <bp(a)suse.de> Cc: Thomas Gleixner <tglx(a)linutronix.de> --- arch/x86/kernel/smpboot.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index fe3ab9632f3b..3b9bf8c7e29d 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1849,24 +1849,25 @@ static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) #include <asm/cpu_device_id.h> #include <asm/intel-family.h> -#define ICPU(model) \ - {X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF, 0} +#define X86_MATCH(model) \ + X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ + INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL) static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { - ICPU(INTEL_FAM6_XEON_PHI_KNL), - ICPU(INTEL_FAM6_XEON_PHI_KNM), + X86_MATCH(XEON_PHI_KNL), + X86_MATCH(XEON_PHI_KNM), {} }; static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { - ICPU(INTEL_FAM6_SKYLAKE_X), + X86_MATCH(SKYLAKE_X), {} }; static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { - ICPU(INTEL_FAM6_ATOM_GOLDMONT), - ICPU(INTEL_FAM6_ATOM_GOLDMONT_D), - ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS), + X86_MATCH(ATOM_GOLDMONT), + X86_MATCH(ATOM_GOLDMONT_D), + X86_MATCH(ATOM_GOLDMONT_PLUS), {} }; -- 2.21.0 -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette

1 0

[PATCH 1/3] ALSA USB MIDI: Fix port starvation
by Andreas Steinmetz 24 Mar '20

24 Mar '20

In case of a multiport USB MIDI interface the lower numbered ports starve higher numbered ports when more than one port is busy transmitting data. The starvation as of the current code is complete and can be for an arbitrarily long time. Control from userspace is not possible without at least halving the theoretically possible device throughput. This is especially bad as there are now 16x16 interface products available. An unpredicable and arbitrarily long latency is not acceptable. The loss of half of the throughput is not acceptable, either. Fair scheduling of all busy ports is required. The patch below balances the actual USB output between all busy ports. It is done in such a way that the single port use performance before applying the patch is identical to the one after applying the patch. To get there, the snd_usbmidi_transmit_byte helper had to be converted to return output notification to allow for the 'repeat' shortcut. The patch tries to avoid O(2) load increase by scaling the balancing loop to the ports that are actually busy as far as this is possible. For the patch to properly work the wMaxPacketSize of the device must be large enough to allow for at least one MIDI event per port in a URB. If this constraint is not met, which is quite improbable, starvation will occur again. Though this could be fixed the likelyhood of such a device is so low that the additional overhead introduced for all other devices is not worth it. Current multi port MIDI interfaces do typically have 2^n output ports and 2^x as wMaxPacketSize where x>n. For a four port USB MIDI interface with a wMaxPacketSize of 64 the maximum latency for any port is changed by the patch from indefinite to 107.52ms. The patch affects the output of all class compliant USB MIDI interfaces. Users will typically experience either no change or increased response, depending on their use case. Signed-off-by: Andreas Steinmetz <ast(a)domdv.de> --- a/sound/usb/midi.c 2020-03-12 22:45:06.611877152 +0100 +++ b/sound/usb/midi.c 2020-03-13 02:33:21.392847930 +0100 @@ -554,7 +554,7 @@ static void snd_usbmidi_output_midiman_p /* * Converts MIDI commands to USB MIDI packets. */ -static void snd_usbmidi_transmit_byte(struct usbmidi_out_port *port, +static int snd_usbmidi_transmit_byte(struct usbmidi_out_port *port, uint8_t b, struct urb *urb) { uint8_t p0 = port->cable; @@ -563,6 +563,7 @@ static void snd_usbmidi_transmit_byte(st if (b >= 0xf8) { output_packet(urb, p0 | 0x0f, b, 0, 0); + return 1; } else if (b >= 0xf0) { switch (b) { case 0xf0: @@ -585,20 +586,20 @@ static void snd_usbmidi_transmit_byte(st case 0xf6: output_packet(urb, p0 | 0x05, 0xf6, 0, 0); port->state = STATE_UNKNOWN; - break; + return 1; case 0xf7: switch (port->state) { case STATE_SYSEX_0: output_packet(urb, p0 | 0x05, 0xf7, 0, 0); - break; + return 1; case STATE_SYSEX_1: output_packet(urb, p0 | 0x06, port->data[0], 0xf7, 0); - break; + return 1; case STATE_SYSEX_2: output_packet(urb, p0 | 0x07, port->data[0], port->data[1], 0xf7); - break; + return 1; } port->state = STATE_UNKNOWN; break; @@ -619,7 +620,7 @@ static void snd_usbmidi_transmit_byte(st port->state = STATE_UNKNOWN; } output_packet(urb, p0, port->data[0], b, 0); - break; + return 1; case STATE_2PARAM_1: port->data[1] = b; port->state = STATE_2PARAM_2; @@ -633,7 +634,7 @@ static void snd_usbmidi_transmit_byte(st port->state = STATE_UNKNOWN; } output_packet(urb, p0, port->data[0], port->data[1], b); - break; + return 1; case STATE_SYSEX_0: port->data[0] = b; port->state = STATE_SYSEX_1; @@ -646,29 +647,49 @@ static void snd_usbmidi_transmit_byte(st output_packet(urb, p0 | 0x04, port->data[0], port->data[1], b); port->state = STATE_SYSEX_0; - break; + return 1; } } + return 0; } static void snd_usbmidi_standard_output(struct snd_usb_midi_out_endpoint *ep, struct urb *urb) { int p; + int start = 0; + int total = 0x10; + int max = ep->max_transfer - 4; + + if (max < 0) + return; + + while (1) { + int first = -1; + int final = -1; - /* FIXME: lower-numbered ports can starve higher-numbered ports */ - for (p = 0; p < 0x10; ++p) { - struct usbmidi_out_port *port = &ep->ports[p]; - if (!port->active) - continue; - while (urb->transfer_buffer_length + 3 < ep->max_transfer) { + for (p = start; p < total; ++p) { + struct usbmidi_out_port *port = &ep->ports[p]; uint8_t b; + if (!port->active) + continue; +repeat: if (snd_rawmidi_transmit(port->substream, &b, 1) != 1) { port->active = 0; - break; + continue; } - snd_usbmidi_transmit_byte(port, b, urb); + if (!snd_usbmidi_transmit_byte(port, b, urb)) + goto repeat; + if (urb->transfer_buffer_length > max) + return; + if (first == -1) + first = p; + final = p; } + if (final == -1) + return; + start = first; + total = final + 1; } }

2 7

Applied "dt-bindings: sound: convert rockchip i2s bindings to yaml" to the asoc tree
by Mark Brown 24 Mar '20

24 Mar '20

The patch dt-bindings: sound: convert rockchip i2s bindings to yaml has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 472abb80fac66b07b6940a40c6392d3dea5dd2a3 Mon Sep 17 00:00:00 2001 From: Johan Jonker <jbx6244(a)gmail.com> Date: Tue, 24 Mar 2020 10:41:47 +0100 Subject: [PATCH] dt-bindings: sound: convert rockchip i2s bindings to yaml Current dts files with 'i2s' nodes are manually verified. In order to automate this process rockchip-i2s.txt has to be converted to yaml. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> Reviewed-by: Rob Herring <robh(a)kernel.org> Link: https://lore.kernel.org/r/20200324094149.6904-1-jbx6244@gmail.com Signed-off-by: Mark Brown <broonie(a)kernel.org> --- .../bindings/sound/rockchip-i2s.txt | 49 -------- .../bindings/sound/rockchip-i2s.yaml | 106 ++++++++++++++++++ 2 files changed, 106 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/rockchip-i2s.txt create mode 100644 Documentation/devicetree/bindings/sound/rockchip-i2s.yaml diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt deleted file mode 100644 index 54aefab71f2c..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Rockchip I2S controller - -The I2S bus (Inter-IC sound bus) is a serial link for digital -audio data transfer between devices in the system. - -Required properties: - -- compatible: should be one of the following: - - "rockchip,rk3066-i2s": for rk3066 - - "rockchip,px30-i2s", "rockchip,rk3066-i2s": for px30 - - "rockchip,rk3036-i2s", "rockchip,rk3066-i2s": for rk3036 - - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188 - - "rockchip,rk3228-i2s", "rockchip,rk3066-i2s": for rk3228 - - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288 - - "rockchip,rk3328-i2s", "rockchip,rk3066-i2s": for rk3328 - - "rockchip,rk3366-i2s", "rockchip,rk3066-i2s": for rk3366 - - "rockchip,rk3368-i2s", "rockchip,rk3066-i2s": for rk3368 - - "rockchip,rk3399-i2s", "rockchip,rk3066-i2s": for rk3399 -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: should contain the I2S interrupt. -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should include "tx" and "rx". -- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. -- clock-names: should contain the following: - - "i2s_hclk": clock for I2S BUS - - "i2s_clk" : clock for I2S controller -- rockchip,playback-channels: max playback channels, if not set, 8 channels default. -- rockchip,capture-channels: max capture channels, if not set, 2 channels default. - -Required properties for controller which support multi channels -playback/capture: - -- rockchip,grf: the phandle of the syscon node for GRF register. - -Example for rk3288 I2S controller: - -i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0xff890000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&pdma1 0>, <&pdma1 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml b/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml new file mode 100644 index 000000000000..eff06b4b51db --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip I2S controller + +description: + The I2S bus (Inter-IC sound bus) is a serial link for digital + audio data transfer between devices in the system. + +maintainers: + - Heiko Stuebner <heiko(a)sntech.de> + +properties: + compatible: + oneOf: + - const: rockchip,rk3066-i2s + - items: + - enum: + - rockchip,px30-i2s + - rockchip,rk3036-i2s + - rockchip,rk3188-i2s + - rockchip,rk3228-i2s + - rockchip,rk3288-i2s + - rockchip,rk3328-i2s + - rockchip,rk3366-i2s + - rockchip,rk3368-i2s + - rockchip,rk3399-i2s + - const: rockchip,rk3066-i2s + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: clock for I2S controller + - description: clock for I2S BUS + + clock-names: + items: + - const: i2s_clk + - const: i2s_hclk + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + rockchip,capture-channels: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + default: 2 + description: + Max capture channels, if not set, 2 channels default. + + rockchip,playback-channels: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + default: 8 + description: + Max playback channels, if not set, 8 channels default. + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF register. + Required property for controllers which support multi channel + playback/capture. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2s@ff890000 { + compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; + reg = <0xff890000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma1 0>, <&pdma1 1>; + dma-names = "tx", "rx"; + rockchip,capture-channels = <2>; + rockchip,playback-channels = <8>; + }; -- 2.20.1

1 0