March 2020 - Alsa-devel - mailman.alsa-project.org

Re: linux-next: Tree for Mar 5 (sound/soc/codecs/wcd934x.o)
by Randy Dunlap 06 Mar '20

06 Mar '20

On 3/4/20 10:55 PM, Stephen Rothwell wrote: > Hi all, > > Changes since 20200304: > on x86_64: CONFIG_MFD_WCD934X=m CONFIG_SND_SOC_WCD934X=y ld: sound/soc/codecs/wcd934x.o: in function `wcd934x_trigger': wcd934x.c:(.text+0x754): undefined reference to `slim_stream_prepare' ld: wcd934x.c:(.text+0x768): undefined reference to `slim_stream_enable' ld: wcd934x.c:(.text+0x797): undefined reference to `slim_stream_unprepare' ld: wcd934x.c:(.text+0x7ab): undefined reference to `slim_stream_disable' ld: sound/soc/codecs/wcd934x.o: in function `wcd934x_codec_probe': wcd934x.c:(.text+0x4c6c): undefined reference to `of_slim_get_device' ld: wcd934x.c:(.text+0x4cd4): undefined reference to `slim_get_logical_addr' ld: wcd934x.c:(.text+0x4cfe): undefined reference to `__regmap_init_slimbus' ld: sound/soc/codecs/wcd934x.o: in function `wcd934x_hw_params': wcd934x.c:(.text+0x6027): undefined reference to `slim_stream_allocate' Full randconfig file is attached. -- ~Randy Reported-by: Randy Dunlap <rdunlap(a)infradead.org>

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[PATCH] topology: Add topology file for generic HDA DSP machine driver
by Mateusz Gorski 06 Mar '20

06 Mar '20

Provide conf file with reference topology for generic HDA DSP machine driver. Signed-off-by: Mateusz Gorski <mateusz.gorski(a)linux.intel.com> --- topology/hdadsp/hda_dsp.conf | 7237 ++++++++++++++++++++++++++++++++++ 1 file changed, 7237 insertions(+) create mode 100644 topology/hdadsp/hda_dsp.conf diff --git a/topology/hdadsp/hda_dsp.conf b/topology/hdadsp/hda_dsp.conf new file mode 100644 index 0000000..b29cd2d --- /dev/null +++ b/topology/hdadsp/hda_dsp.conf @@ -0,0 +1,7237 @@ + +SectionVendorTokens."skl_tokens" { + SKL_TKN_UUID "1" + SKL_TKN_U8_NUM_BLOCKS "2" + SKL_TKN_U8_BLOCK_TYPE "3" + SKL_TKN_U8_IN_PIN_TYPE "4" + SKL_TKN_U8_OUT_PIN_TYPE "5" + SKL_TKN_U8_DYN_IN_PIN "6" + SKL_TKN_U8_DYN_OUT_PIN "7" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "9" + SKL_TKN_U8_TIME_SLOT "10" + SKL_TKN_U8_CORE_ID "11" + SKL_TKN_U8_MODULE_TYPE "12" + SKL_TKN_U8_CONN_TYPE "13" + SKL_TKN_U8_DEV_TYPE "14" + SKL_TKN_U8_HW_CONN_TYPE "15" + SKL_TKN_U16_MOD_INST_ID "16" + SKL_TKN_U16_BLOCK_SIZE "17" + SKL_TKN_U32_MAX_MCPS "18" + SKL_TKN_U32_MEM_PAGES "19" + SKL_TKN_U32_OBS "20" + SKL_TKN_U32_IBS "21" + SKL_TKN_U32_VBUS_ID "22" + SKL_TKN_U32_PARAMS_FIXUP "23" + SKL_TKN_U32_CONVERTER "24" + SKL_TKN_U32_PIPE_ID "25" + SKL_TKN_U32_PIPE_CONN_TYPE "26" + SKL_TKN_U32_PIPE_PRIORITY "27" + SKL_TKN_U32_PIPE_MEM_PGS "28" + SKL_TKN_U32_DIR_PIN_COUNT "29" + SKL_TKN_U32_FMT_CH "30" + SKL_TKN_U32_FMT_FREQ "31" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "33" + SKL_TKN_U32_FMT_CH_CONFIG "34" + SKL_TKN_U32_FMT_INTERLEAVE "35" + SKL_TKN_U32_FMT_SAMPLE_TYPE "36" + SKL_TKN_U32_FMT_CH_MAP "37" + SKL_TKN_U32_PIN_MOD_ID "38" + SKL_TKN_U32_PIN_INST_ID "39" + SKL_TKN_U32_MOD_SET_PARAMS "40" + SKL_TKN_U32_MOD_PARAM_ID "41" + SKL_TKN_U32_CAPS_SET_PARAMS "42" + SKL_TKN_U32_CAPS_PARAMS_ID "43" + SKL_TKN_U32_CAPS_SIZE "44" + SKL_TKN_U32_PROC_DOMAIN "45" + SKL_TKN_U32_LIB_COUNT "46" + SKL_TKN_STR_LIB_NAME "47" + SKL_TKN_U32_PMODE "48" + SKL_TKN_U32_D0I3_CAPS "49" + SKL_TKN_U32_DMA_BUF_SIZE "50" + SKL_TKN_U32_PIPE_DIRECTION "51" + SKL_TKN_U32_PIPE_CONFIG_ID "52" + SKL_TKN_U32_NUM_CONFIGS "53" + SKL_TKN_U32_PATH_MEM_PGS "54" + SKL_TKN_U32_CFG_FREQ "55" + SKL_TKN_U8_CFG_CHAN "56" + SKL_TKN_U8_CFG_BPS "57" + SKL_TKN_CFG_MOD_RES_ID "58" + SKL_TKN_CFG_MOD_FMT_ID "59" + SKL_TKN_U8_NUM_MOD "60" + SKL_TKN_MM_U8_MOD_IDX "61" + SKL_TKN_MM_U8_NUM_RES "62" + SKL_TKN_MM_U8_NUM_INTF "63" + SKL_TKN_MM_U32_RES_ID "64" + SKL_TKN_MM_U32_CPS "65" + SKL_TKN_MM_U32_DMA_SIZE "66" + SKL_TKN_MM_U32_CPC "67" + SKL_TKN_MM_U32_RES_PIN_ID "68" + SKL_TKN_MM_U32_INTF_PIN_ID "69" + SKL_TKN_MM_U32_PIN_BUF "70" + SKL_TKN_MM_U32_FMT_ID "71" + SKL_TKN_MM_U32_NUM_IN_FMT "72" + SKL_TKN_MM_U32_NUM_OUT_FMT "73" + SKL_TKN_U32_ASTATE_IDX "74" + SKL_TKN_U32_ASTATE_COUNT "75" + SKL_TKN_U32_ASTATE_KCPS "76" + SKL_TKN_U32_ASTATE_CLK_SRC "77" + SKL_TKN_U32_DMACTRL_CFG_IDX "82" + SKL_TKN_U32_DMACTRL_CFG_SIZE "83" + SKL_TKN_U32_DMA_IDX "84" + SKL_TKN_U32_DMA_TYPE "85" + SKL_TKN_U32_DMA_SIZE "86" + SKL_TKN_U32_DMA_MAX_SIZE "87" + SKL_TKN_U32_DMA_MIN_SIZE "88" + SKL_TKN_U32_SCH_TYPE "89" + SKL_TKN_U32_SCH_SIZE "90" + SKL_TKN_U32_SCH_SYS_TICK_MUL "91" + SKL_TKN_U32_SCH_SYS_TICK_DIV "92" + SKL_TKN_U32_SCH_SYS_TICK_LL_SRC "93" + SKL_TKN_U32_SCH_SYS_TICK_CFG_LEN "94" + SKL_TKN_U32_SCH_SYS_TICK_CFG "95" + SKL_TKN_U32_FMT_CFG_IDX "96" +} + +SectionVendorTuples."mod_type_data_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "5284" + } +} + +SectionData."mod_type_data_size_desc" { + tuples "mod_type_data_size_desc" +} + +SectionVendorTuples."mod_type_data" { + tokens "skl_tokens" + + tuples."byte.u8_num_mod" { + SKL_TKN_U8_NUM_MOD "5" + } + + tuples."uuid.mod_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_mod_type_0" { + SKL_TKN_MM_U8_MOD_IDX "0" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "3" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_0_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2666000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2666" + } + + tuples."word.u32_mod_type_0_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_0_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_0_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_0_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_0_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_1" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_mod_type_1" { + SKL_TKN_MM_U8_MOD_IDX "1" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_1_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1521000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "1521" + } + + tuples."word.u32_mod_type_1_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_1_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_1_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_1_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_1_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_2" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_mod_type_2" { + SKL_TKN_MM_U8_MOD_IDX "2" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "4" + SKL_TKN_MM_U8_NUM_RES "13" + SKL_TKN_MM_U8_NUM_INTF "13" + } + + tuples."word.u32_mod_type_2_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "2581000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "384" + SKL_TKN_MM_U32_CPC "2581" + } + + tuples."word.u32_mod_type_2_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_1" { + SKL_TKN_MM_U32_RES_ID "1" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_2" { + SKL_TKN_MM_U32_RES_ID "2" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_2_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_2_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_3" { + SKL_TKN_MM_U32_RES_ID "3" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "4473000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "4473" + } + + tuples."word.u32_mod_type_2_res_3_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_3_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_4" { + SKL_TKN_MM_U32_RES_ID "4" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "384" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_4_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_4_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_5" { + SKL_TKN_MM_U32_RES_ID "5" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_5_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_5_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_6" { + SKL_TKN_MM_U32_RES_ID "6" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_OBS "768" + SKL_TKN_MM_U32_DMA_SIZE "1536" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_6_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_6_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "768" + } + + tuples."word.u32_mod_type_2_res_7" { + SKL_TKN_MM_U32_RES_ID "7" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "1000" + SKL_TKN_U32_IBS "1536" + SKL_TKN_U32_OBS "1536" + SKL_TKN_MM_U32_DMA_SIZE "3072" + SKL_TKN_MM_U32_CPC "1" + } + + tuples."word.u32_mod_type_2_res_7_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "1536" + } + + tuples."word.u32_mod_type_2_res_7_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "1536" + } + + tuples."word.u32_mod_type_2_res_8" { + SKL_TKN_MM_U32_RES_ID "8" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "579000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "579" + } + + tuples."word.u32_mod_type_2_res_8_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_8_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_9" { + SKL_TKN_MM_U32_RES_ID "9" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_9_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_9_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_10" { + SKL_TKN_MM_U32_RES_ID "10" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "384768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_10_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_10_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_11" { + SKL_TKN_MM_U32_RES_ID "11" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "192" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "384768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_11_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_res_11_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_12" { + SKL_TKN_MM_U32_RES_ID "12" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "3812000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "192" + SKL_TKN_MM_U32_DMA_SIZE "384768" + SKL_TKN_MM_U32_CPC "3812" + } + + tuples."word.u32_mod_type_2_res_12_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_2_res_12_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "192" + } + + tuples."word.u32_mod_type_2_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_1" { + SKL_TKN_MM_U32_FMT_ID "1" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_1_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_1_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_2" { + SKL_TKN_MM_U32_FMT_ID "2" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_2_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_2_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_3" { + SKL_TKN_MM_U32_FMT_ID "3" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_3_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_3_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_4" { + SKL_TKN_MM_U32_FMT_ID "4" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_4_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_4_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_5" { + SKL_TKN_MM_U32_FMT_ID "5" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_5_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_5_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "5" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294914576" + } + + tuples."word.u32_mod_type_2_intf_6" { + SKL_TKN_MM_U32_FMT_ID "6" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_6_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "6" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "8" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4283707920" + } + + tuples."word.u32_mod_type_2_intf_6_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "6" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "8" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4283707920" + } + + tuples."word.u32_mod_type_2_intf_7" { + SKL_TKN_MM_U32_FMT_ID "7" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_7_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "8" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "14" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "1985229328" + } + + tuples."word.u32_mod_type_2_intf_7_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "8" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "14" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "1985229328" + } + + tuples."word.u32_mod_type_2_intf_8" { + SKL_TKN_MM_U32_FMT_ID "8" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_8_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_8_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_9" { + SKL_TKN_MM_U32_FMT_ID "9" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_9_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_9_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_10" { + SKL_TKN_MM_U32_FMT_ID "10" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_10_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_10_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_11" { + SKL_TKN_MM_U32_FMT_ID "11" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_11_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_11_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_12" { + SKL_TKN_MM_U32_FMT_ID "12" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_2_intf_12_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_2_intf_12_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "16" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "16" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_3" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."byte.u8_mod_type_3" { + SKL_TKN_MM_U8_MOD_IDX "3" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_3_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_MM_U32_CPS "100000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "2106" + } + + tuples."word.u32_mod_type_3_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_3_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_3_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_3_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_3_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."uuid.mod_4" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."byte.u8_mod_type_4" { + SKL_TKN_MM_U8_MOD_IDX "4" + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_MM_U8_NUM_RES "1" + SKL_TKN_MM_U8_NUM_INTF "1" + } + + tuples."word.u32_mod_type_4_res_0" { + SKL_TKN_MM_U32_RES_ID "0" + SKL_TKN_U32_MEM_PAGES "4" + SKL_TKN_MM_U32_CPS "100000" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_OBS "384" + SKL_TKN_MM_U32_DMA_SIZE "0" + SKL_TKN_MM_U32_CPC "10157" + } + + tuples."word.u32_mod_type_4_res_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_4_res_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_RES_PIN_ID "0" + SKL_TKN_MM_U32_PIN_BUF "384" + } + + tuples."word.u32_mod_type_4_intf_0" { + SKL_TKN_MM_U32_FMT_ID "0" + SKL_TKN_MM_U32_NUM_IN_FMT "1" + SKL_TKN_MM_U32_NUM_OUT_FMT "1" + } + + tuples."word.u32_mod_type_4_intf_0_input_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } + + tuples."word.u32_mod_type_4_intf_0_output_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_MM_U32_INTF_PIN_ID "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_CH_CONFIG "1" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "4294967056" + } +} + +SectionData."mod_type_data" { + tuples "mod_type_data" +} + +SectionVendorTuples."media0_in cpr 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in cpr 0 num_desc" { + tuples "media0_in cpr 0 num_desc" +} + +SectionVendorTuples."media0_in cpr 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media0_in cpr 0_size_desc" { + tuples "media0_in cpr 0_size_desc" +} + +SectionVendorTuples."media0_in cpr 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "7" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media0_in cpr 0" { + tuples "media0_in cpr 0" +} + +SectionWidget."media0_in cpr 0" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media0_in cpr 0 num_desc" + "media0_in cpr 0_size_desc" + "media0_in cpr 0" + ] +} + +SectionVendorTuples."media0_in updwmix 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in updwmix 0 num_desc" { + tuples "media0_in updwmix 0 num_desc" +} + +SectionVendorTuples."media0_in updwmix 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "388" + } +} + +SectionData."media0_in updwmix 0_size_desc" { + tuples "media0_in updwmix 0_size_desc" +} + +SectionVendorTuples."media0_in updwmix 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "2" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "8" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } +} + +SectionData."media0_in updwmix 0" { + tuples "media0_in updwmix 0" +} + +SectionWidget."media0_in updwmix 0" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_in updwmix 0 num_desc" + "media0_in updwmix 0_size_desc" + "media0_in updwmix 0" + ] +} + +SectionVendorTuples."media0_in srcintc 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in srcintc 0 num_desc" { + tuples "media0_in srcintc 0 num_desc" +} + +SectionVendorTuples."media0_in srcintc 0_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "388" + } +} + +SectionData."media0_in srcintc 0_size_desc" { + tuples "media0_in srcintc 0_size_desc" +} + +SectionVendorTuples."media0_in srcintc 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "3" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "1" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "7" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "12, 6, 248, 66, 47, 131, 191, 77, 178, 71, 81, 233, 97, 153, 123, 52" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } +} + +SectionData."media0_in srcintc 0" { + tuples "media0_in srcintc 0" +} + +SectionWidget."media0_in srcintc 0" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_in srcintc 0 num_desc" + "media0_in srcintc 0_size_desc" + "media0_in srcintc 0" + ] +} + +SectionVendorTuples."media0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_in mi num_desc" { + tuples "media0_in mi num_desc" +} + +SectionVendorTuples."media0_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media0_in mi_size_desc" { + tuples "media0_in mi_size_desc" +} + +SectionVendorTuples."media0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "0" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "8" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "8" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "141, 178, 27, 230, 154, 20, 31, 76, 183, 9, 70, 130, 62, 245, 245, 174" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media0_in mi" { + tuples "media0_in mi" +} + +SectionWidget."media0_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media0_in mi num_desc" + "media0_in mi_size_desc" + "media0_in mi" + ] +} + +SectionVendorTuples."codec0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_out mo num_desc" { + tuples "codec0_out mo num_desc" +} + +SectionVendorTuples."codec0_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec0_out mo_size_desc" { + tuples "codec0_out mo_size_desc" +} + +SectionVendorTuples."codec0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec0_out mo" { + tuples "codec0_out mo" +} + +SectionWidget."codec0_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media0_in mi Switch" + ] + + data [ + "codec0_out mo num_desc" + "codec0_out mo_size_desc" + "codec0_out mo" + ] +} + +SectionVendorTuples."codec0_out cpr 1 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_out cpr 1 num_desc" { + tuples "codec0_out cpr 1 num_desc" +} + +SectionVendorTuples."codec0_out cpr 1_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec0_out cpr 1_size_desc" { + tuples "codec0_out cpr 1_size_desc" +} + +SectionVendorTuples."codec0_out cpr 1" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec0_out cpr 1" { + tuples "codec0_out cpr 1" +} + +SectionWidget."codec0_out cpr 1" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec0_out cpr 1 num_desc" + "codec0_out cpr 1_size_desc" + "codec0_out cpr 1" + ] +} + +SectionWidget."codec0_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."media1_in cpr 2 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_in cpr 2 num_desc" { + tuples "media1_in cpr 2 num_desc" +} + +SectionVendorTuples."media1_in cpr 2_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media1_in cpr 2_size_desc" { + tuples "media1_in cpr 2_size_desc" +} + +SectionVendorTuples."media1_in cpr 2" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media1_in cpr 2" { + tuples "media1_in cpr 2" +} + +SectionWidget."media1_in cpr 2" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media1_in cpr 2 num_desc" + "media1_in cpr 2_size_desc" + "media1_in cpr 2" + ] +} + +SectionVendorTuples."media1_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_in mi num_desc" { + tuples "media1_in mi num_desc" +} + +SectionVendorTuples."media1_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media1_in mi_size_desc" { + tuples "media1_in mi_size_desc" +} + +SectionVendorTuples."media1_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media1_in mi" { + tuples "media1_in mi" +} + +SectionWidget."media1_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media1_in mi num_desc" + "media1_in mi_size_desc" + "media1_in mi" + ] +} + +SectionVendorTuples."codec1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_out mo num_desc" { + tuples "codec1_out mo num_desc" +} + +SectionVendorTuples."codec1_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec1_out mo_size_desc" { + tuples "codec1_out mo_size_desc" +} + +SectionVendorTuples."codec1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec1_out mo" { + tuples "codec1_out mo" +} + +SectionWidget."codec1_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media1_in mi Switch" + ] + + data [ + "codec1_out mo num_desc" + "codec1_out mo_size_desc" + "codec1_out mo" + ] +} + +SectionVendorTuples."codec1_out cpr 3 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_out cpr 3 num_desc" { + tuples "codec1_out cpr 3 num_desc" +} + +SectionVendorTuples."codec1_out cpr 3_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec1_out cpr 3_size_desc" { + tuples "codec1_out cpr 3_size_desc" +} + +SectionVendorTuples."codec1_out cpr 3" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "1" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec1_out cpr 3" { + tuples "codec1_out cpr 3" +} + +SectionWidget."codec1_out cpr 3" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec1_out cpr 3 num_desc" + "codec1_out cpr 3_size_desc" + "codec1_out cpr 3" + ] +} + +SectionWidget."codec1_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."media2_in cpr 4 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_in cpr 4 num_desc" { + tuples "media2_in cpr 4 num_desc" +} + +SectionVendorTuples."media2_in cpr 4_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."media2_in cpr 4_size_desc" { + tuples "media2_in cpr 4_size_desc" +} + +SectionVendorTuples."media2_in cpr 4" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."media2_in cpr 4" { + tuples "media2_in cpr 4" +} + +SectionWidget."media2_in cpr 4" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "media2_in cpr 4 num_desc" + "media2_in cpr 4_size_desc" + "media2_in cpr 4" + ] +} + +SectionVendorTuples."media2_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_in mi num_desc" { + tuples "media2_in mi num_desc" +} + +SectionVendorTuples."media2_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."media2_in mi_size_desc" { + tuples "media2_in mi_size_desc" +} + +SectionVendorTuples."media2_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "1" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media2_in mi" { + tuples "media2_in mi" +} + +SectionWidget."media2_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "media2_in mi num_desc" + "media2_in mi_size_desc" + "media2_in mi" + ] +} + +SectionVendorTuples."codec2_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_out mo num_desc" { + tuples "codec2_out mo num_desc" +} + +SectionVendorTuples."codec2_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."codec2_out mo_size_desc" { + tuples "codec2_out mo_size_desc" +} + +SectionVendorTuples."codec2_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."codec2_out mo" { + tuples "codec2_out mo" +} + +SectionWidget."codec2_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "media2_in mi Switch" + ] + + data [ + "codec2_out mo num_desc" + "codec2_out mo_size_desc" + "codec2_out mo" + ] +} + +SectionVendorTuples."codec2_out cpr 5 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_out cpr 5 num_desc" { + tuples "codec2_out cpr 5 num_desc" +} + +SectionVendorTuples."codec2_out cpr 5_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."codec2_out cpr 5_size_desc" { + tuples "codec2_out cpr 5_size_desc" +} + +SectionVendorTuples."codec2_out cpr 5" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "1" + SKL_TKN_CFG_MOD_FMT_ID "1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "2" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec2_out cpr 5" { + tuples "codec2_out cpr 5" +} + +SectionWidget."codec2_out cpr 5" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "codec2_out cpr 5 num_desc" + "codec2_out cpr 5_size_desc" + "codec2_out cpr 5" + ] +} + +SectionWidget."codec2_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."codec0_in cpr 6 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_in cpr 6 num_desc" { + tuples "codec0_in cpr 6 num_desc" +} + +SectionVendorTuples."codec0_in cpr 6_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec0_in cpr 6_size_desc" { + tuples "codec0_in cpr 6_size_desc" +} + +SectionVendorTuples."codec0_in cpr 6" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "9" + SKL_TKN_CFG_MOD_FMT_ID "9" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec0_in cpr 6" { + tuples "codec0_in cpr 6" +} + +SectionWidget."codec0_in cpr 6" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec0_in cpr 6 num_desc" + "codec0_in cpr 6_size_desc" + "codec0_in cpr 6" + ] +} + +SectionVendorTuples."codec0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec0_in mi num_desc" { + tuples "codec0_in mi num_desc" +} + +SectionVendorTuples."codec0_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec0_in mi_size_desc" { + tuples "codec0_in mi_size_desc" +} + +SectionVendorTuples."codec0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec0_in mi" { + tuples "codec0_in mi" +} + +SectionWidget."codec0_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec0_in mi num_desc" + "codec0_in mi_size_desc" + "codec0_in mi" + ] +} + +SectionWidget."codec0_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_out mo num_desc" { + tuples "media0_out mo num_desc" +} + +SectionVendorTuples."media0_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media0_out mo_size_desc" { + tuples "media0_out mo_size_desc" +} + +SectionVendorTuples."media0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "7" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media0_out mo" { + tuples "media0_out mo" +} + +SectionWidget."media0_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec0_in mi Switch" + ] + + data [ + "media0_out mo num_desc" + "media0_out mo_size_desc" + "media0_out mo" + ] +} + +SectionVendorTuples."media0_out cpr 7 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media0_out cpr 7 num_desc" { + tuples "media0_out cpr 7 num_desc" +} + +SectionVendorTuples."media0_out cpr 7_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media0_out cpr 7_size_desc" { + tuples "media0_out cpr 7_size_desc" +} + +SectionVendorTuples."media0_out cpr 7" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "7" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "8" + SKL_TKN_CFG_MOD_FMT_ID "8" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "3" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media0_out cpr 7" { + tuples "media0_out cpr 7" +} + +SectionWidget."media0_out cpr 7" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media0_out cpr 7 num_desc" + "media0_out cpr 7_size_desc" + "media0_out cpr 7" + ] +} + +SectionVendorTuples."codec1_in cpr 8 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_in cpr 8 num_desc" { + tuples "codec1_in cpr 8 num_desc" +} + +SectionVendorTuples."codec1_in cpr 8_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec1_in cpr 8_size_desc" { + tuples "codec1_in cpr 8_size_desc" +} + +SectionVendorTuples."codec1_in cpr 8" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "8" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "2" + SKL_TKN_CFG_MOD_FMT_ID "2" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec1_in cpr 8" { + tuples "codec1_in cpr 8" +} + +SectionWidget."codec1_in cpr 8" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec1_in cpr 8 num_desc" + "codec1_in cpr 8_size_desc" + "codec1_in cpr 8" + ] +} + +SectionVendorTuples."codec1_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec1_in mi num_desc" { + tuples "codec1_in mi num_desc" +} + +SectionVendorTuples."codec1_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec1_in mi_size_desc" { + tuples "codec1_in mi_size_desc" +} + +SectionVendorTuples."codec1_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "8" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec1_in mi" { + tuples "codec1_in mi" +} + +SectionWidget."codec1_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec1_in mi num_desc" + "codec1_in mi_size_desc" + "codec1_in mi" + ] +} + +SectionWidget."codec1_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_out mo num_desc" { + tuples "media1_out mo num_desc" +} + +SectionVendorTuples."media1_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media1_out mo_size_desc" { + tuples "media1_out mo_size_desc" +} + +SectionVendorTuples."media1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "9" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media1_out mo" { + tuples "media1_out mo" +} + +SectionWidget."media1_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec1_in mi Switch" + ] + + data [ + "media1_out mo num_desc" + "media1_out mo_size_desc" + "media1_out mo" + ] +} + +SectionVendorTuples."media1_out cpr 9 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media1_out cpr 9 num_desc" { + tuples "media1_out cpr 9 num_desc" +} + +SectionVendorTuples."media1_out cpr 9_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media1_out cpr 9_size_desc" { + tuples "media1_out cpr 9_size_desc" +} + +SectionVendorTuples."media1_out cpr 9" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "9" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "3" + SKL_TKN_CFG_MOD_FMT_ID "3" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "4" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media1_out cpr 9" { + tuples "media1_out cpr 9" +} + +SectionWidget."media1_out cpr 9" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media1_out cpr 9 num_desc" + "media1_out cpr 9_size_desc" + "media1_out cpr 9" + ] +} + +SectionVendorTuples."codec2_in cpr 10 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_in cpr 10 num_desc" { + tuples "codec2_in cpr 10 num_desc" +} + +SectionVendorTuples."codec2_in cpr 10_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."codec2_in cpr 10_size_desc" { + tuples "codec2_in cpr 10_size_desc" +} + +SectionVendorTuples."codec2_in cpr 10" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "10" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "2" + SKL_TKN_CFG_MOD_FMT_ID "2" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."codec2_in cpr 10" { + tuples "codec2_in cpr 10" +} + +SectionWidget."codec2_in cpr 10" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "codec2_in cpr 10 num_desc" + "codec2_in cpr 10_size_desc" + "codec2_in cpr 10" + ] +} + +SectionVendorTuples."codec2_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."codec2_in mi num_desc" { + tuples "codec2_in mi num_desc" +} + +SectionVendorTuples."codec2_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."codec2_in mi_size_desc" { + tuples "codec2_in mi_size_desc" +} + +SectionVendorTuples."codec2_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "10" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."codec2_in mi" { + tuples "codec2_in mi" +} + +SectionWidget."codec2_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "codec2_in mi num_desc" + "codec2_in mi_size_desc" + "codec2_in mi" + ] +} + +SectionWidget."codec2_in" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."media2_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_out mo num_desc" { + tuples "media2_out mo num_desc" +} + +SectionVendorTuples."media2_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."media2_out mo_size_desc" { + tuples "media2_out mo_size_desc" +} + +SectionVendorTuples."media2_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "11" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "11" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."media2_out mo" { + tuples "media2_out mo" +} + +SectionWidget."media2_out mo" { + index "0" + type "mixer" + no_pm "true" + subseq "10" + event_type "1" + event_flags "15" + + mixer [ + "codec2_in mi Switch" + ] + + data [ + "media2_out mo num_desc" + "media2_out mo_size_desc" + "media2_out mo" + ] +} + +SectionVendorTuples."media2_out cpr 11 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."media2_out cpr 11 num_desc" { + tuples "media2_out cpr 11 num_desc" +} + +SectionVendorTuples."media2_out cpr 11_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."media2_out cpr 11_size_desc" { + tuples "media2_out cpr 11_size_desc" +} + +SectionVendorTuples."media2_out cpr 11" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "11" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "11" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "1" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "32" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "24" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "3" + SKL_TKN_CFG_MOD_FMT_ID "3" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "5" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."media2_out cpr 11" { + tuples "media2_out cpr 11" +} + +SectionWidget."media2_out cpr 11" { + index "0" + type "pga" + no_pm "true" + event_type "4" + + data [ + "media2_out cpr 11 num_desc" + "media2_out cpr 11_size_desc" + "media2_out cpr 11" + ] +} + +SectionVendorTuples."hdmi1_out cpr 12 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi1_out cpr 12 num_desc" { + tuples "hdmi1_out cpr 12 num_desc" +} + +SectionVendorTuples."hdmi1_out cpr 12_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."hdmi1_out cpr 12_size_desc" { + tuples "hdmi1_out cpr 12_size_desc" +} + +SectionVendorTuples."hdmi1_out cpr 12" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "12" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "12" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "13" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi1_out cpr 12" { + tuples "hdmi1_out cpr 12" +} + +SectionWidget."hdmi1_out cpr 12" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi1_out cpr 12 num_desc" + "hdmi1_out cpr 12_size_desc" + "hdmi1_out cpr 12" + ] +} + +SectionVendorTuples."hdmi1_out cpr 13 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi1_out cpr 13 num_desc" { + tuples "hdmi1_out cpr 13 num_desc" +} + +SectionVendorTuples."hdmi1_out cpr 13_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."hdmi1_out cpr 13_size_desc" { + tuples "hdmi1_out cpr 13_size_desc" +} + +SectionVendorTuples."hdmi1_out cpr 13" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "13" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "12" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "12" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi1_out cpr 13" { + tuples "hdmi1_out cpr 13" +} + +SectionWidget."hdmi1_out cpr 13" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi1_out cpr 13 num_desc" + "hdmi1_out cpr 13_size_desc" + "hdmi1_out cpr 13" + ] +} + +SectionWidget."iDisp1_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."hdmi2_out cpr 14 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi2_out cpr 14 num_desc" { + tuples "hdmi2_out cpr 14 num_desc" +} + +SectionVendorTuples."hdmi2_out cpr 14_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."hdmi2_out cpr 14_size_desc" { + tuples "hdmi2_out cpr 14_size_desc" +} + +SectionVendorTuples."hdmi2_out cpr 14" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "14" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "13" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "15" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi2_out cpr 14" { + tuples "hdmi2_out cpr 14" +} + +SectionWidget."hdmi2_out cpr 14" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi2_out cpr 14 num_desc" + "hdmi2_out cpr 14_size_desc" + "hdmi2_out cpr 14" + ] +} + +SectionVendorTuples."hdmi2_out cpr 15 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi2_out cpr 15 num_desc" { + tuples "hdmi2_out cpr 15 num_desc" +} + +SectionVendorTuples."hdmi2_out cpr 15_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."hdmi2_out cpr 15_size_desc" { + tuples "hdmi2_out cpr 15_size_desc" +} + +SectionVendorTuples."hdmi2_out cpr 15" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "15" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "13" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "14" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi2_out cpr 15" { + tuples "hdmi2_out cpr 15" +} + +SectionWidget."hdmi2_out cpr 15" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi2_out cpr 15 num_desc" + "hdmi2_out cpr 15_size_desc" + "hdmi2_out cpr 15" + ] +} + +SectionWidget."iDisp2_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."hdmi3_out cpr 16 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi3_out cpr 16 num_desc" { + tuples "hdmi3_out cpr 16 num_desc" +} + +SectionVendorTuples."hdmi3_out cpr 16_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."hdmi3_out cpr 16_size_desc" { + tuples "hdmi3_out cpr 16_size_desc" +} + +SectionVendorTuples."hdmi3_out cpr 16" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "16" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "14" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "17" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."hdmi3_out cpr 16" { + tuples "hdmi3_out cpr 16" +} + +SectionWidget."hdmi3_out cpr 16" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "hdmi3_out cpr 16 num_desc" + "hdmi3_out cpr 16_size_desc" + "hdmi3_out cpr 16" + ] +} + +SectionVendorTuples."hdmi3_out cpr 17 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."hdmi3_out cpr 17 num_desc" { + tuples "hdmi3_out cpr 17 num_desc" +} + +SectionVendorTuples."hdmi3_out cpr 17_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."hdmi3_out cpr 17_size_desc" { + tuples "hdmi3_out cpr 17_size_desc" +} + +SectionVendorTuples."hdmi3_out cpr 17" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "17" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "14" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "0" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "4" + SKL_TKN_CFG_MOD_FMT_ID "4" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "16" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."hdmi3_out cpr 17" { + tuples "hdmi3_out cpr 17" +} + +SectionWidget."hdmi3_out cpr 17" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "hdmi3_out cpr 17 num_desc" + "hdmi3_out cpr 17_size_desc" + "hdmi3_out cpr 17" + ] +} + +SectionWidget."iDisp3_out" { + index "0" + type "aif_out" + no_pm "true" +} + +SectionVendorTuples."mch_cap_in cpr 18 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_in cpr 18 num_desc" { + tuples "mch_cap_in cpr 18 num_desc" +} + +SectionVendorTuples."mch_cap_in cpr 18_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "500" + } +} + +SectionData."mch_cap_in cpr 18_size_desc" { + tuples "mch_cap_in cpr 18_size_desc" +} + +SectionVendorTuples."mch_cap_in cpr 18" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "1" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "18" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "0" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "15" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "11" + SKL_TKN_CFG_MOD_FMT_ID "11" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_1" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_2" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."uuid.out_pin_3" { + SKL_TKN_UUID "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0" + } +} + +SectionData."mch_cap_in cpr 18" { + tuples "mch_cap_in cpr 18" +} + +SectionWidget."mch_cap_in cpr 18" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + data [ + "mch_cap_in cpr 18 num_desc" + "mch_cap_in cpr 18_size_desc" + "mch_cap_in cpr 18" + ] +} + +SectionVendorTuples."mch_cap_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_in mi num_desc" { + tuples "mch_cap_in mi num_desc" +} + +SectionVendorTuples."mch_cap_in mi_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "416" + } +} + +SectionData."mch_cap_in mi_size_desc" { + tuples "mch_cap_in mi_size_desc" +} + +SectionVendorTuples."mch_cap_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "15" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "18" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."mch_cap_in mi" { + tuples "mch_cap_in mi" +} + +SectionWidget."mch_cap_in mi" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "mch_cap_in mi num_desc" + "mch_cap_in mi_size_desc" + "mch_cap_in mi" + ] +} + +SectionWidget."dmic01_hifi" { + index "0" + type "aif_in" + no_pm "true" +} + +SectionVendorTuples."mch_cap_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_out mo num_desc" { + tuples "mch_cap_out mo num_desc" +} + +SectionVendorTuples."mch_cap_out mo_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "536" + } +} + +SectionData."mch_cap_out mo_size_desc" { + tuples "mch_cap_out mo_size_desc" +} + +SectionVendorTuples."mch_cap_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "0" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "16" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "0" + SKL_TKN_CFG_MOD_FMT_ID "0" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "2" + SKL_TKN_U32_PIN_INST_ID "19" + } + + tuples."uuid.out_pin_0" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } +} + +SectionData."mch_cap_out mo" { + tuples "mch_cap_out mo" +} + +SectionWidget."mch_cap_out mo" { + index "0" + type "mixer" + no_pm "true" + event_type "3" + event_flags "9" + + mixer [ + "mch_cap_in mi Switch" + ] + + data [ + "mch_cap_out mo num_desc" + "mch_cap_out mo_size_desc" + "mch_cap_out mo" + ] +} + +SectionVendorTuples."mch_cap_out cpr 19 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."mch_cap_out cpr 19 num_desc" { + tuples "mch_cap_out cpr 19 num_desc" +} + +SectionVendorTuples."mch_cap_out cpr 19_size_desc" { + tokens "skl_tokens" + + tuples."byte.u8_block_type" { + SKL_TKN_U8_BLOCK_TYPE "0" + } + + tuples."short.u16_size_desc" { + SKL_TKN_U16_BLOCK_SIZE "440" + } +} + +SectionData."mch_cap_out cpr 19_size_desc" { + tuples "mch_cap_out cpr 19_size_desc" +} + +SectionVendorTuples."mch_cap_out cpr 19" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_DYN_IN_PIN "0" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "19" + } + + tuples."word.u32_data" { + SKL_TKN_U32_VBUS_ID "4294967295" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "16" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PMODE "0" + SKL_TKN_U32_D0I3_CAPS "0" + SKL_TKN_U32_PROC_DOMAIN "0" + SKL_TKN_U32_PIPE_DIRECTION "1" + SKL_TKN_U32_NUM_CONFIGS "1" + SKL_TKN_U32_DMA_BUF_SIZE "2" + } + + tuples."word._pipe_0" { + SKL_TKN_U32_PIPE_CONFIG_ID "0" + SKL_TKN_U32_PATH_MEM_PGS "2" + } + + tuples."word._pipe_u32_cfg_in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_in_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."word._pipe_u32_cfg_out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_CFG_FREQ "48000" + } + + tuples."word._pipe_u8_cfg_out_fmt_0" { + SKL_TKN_U8_CFG_BPS "16" + SKL_TKN_U8_CFG_CHAN "2" + } + + tuples."short.u16_pipe_mod_cfg_0" { + SKL_TKN_CFG_MOD_RES_ID "12" + SKL_TKN_CFG_MOD_FMT_ID "12" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "1" + SKL_TKN_U32_PIN_INST_ID "6" + } + + tuples."uuid.in_pin_0" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "33" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "49" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionData."mch_cap_out cpr 19" { + tuples "mch_cap_out cpr 19" +} + +SectionWidget."mch_cap_out cpr 19" { + index "0" + type "pga" + no_pm "true" + subseq "10" + event_type "4" + event_flags "9" + + data [ + "mch_cap_out cpr 19 num_desc" + "mch_cap_out cpr 19_size_desc" + "mch_cap_out cpr 19" + ] +} + +SectionControlMixer."media0_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."media1_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."media2_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec0_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec1_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."codec2_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionControlMixer."mch_cap_in mi Switch" { + max "1" + invert "false" + index "0" + + channel."fl" { + reg "-1" + shift "0" + } + + channel."fr" { + reg "-1" + shift "0" + } + + ops."ctl" { + get "64" + put "64" + info "1" + } +} + +SectionGraph."Pipeline 1 Graph" { + index "0" + + lines [ + "media0_in cpr 0, , hda-dsp-analog-playback" + "media0_in updwmix 0, , media0_in cpr 0" + "media0_in srcintc 0, , media0_in updwmix 0" + "media0_in mi, , media0_in srcintc 0" + "codec0_out cpr 1, , codec0_out mo" + "codec0_out, , codec0_out cpr 1" + "media1_in cpr 2, , hda-dsp-digital-playback" + "media1_in mi, , media1_in cpr 2" + "codec1_out cpr 3, , codec1_out mo" + "codec1_out, , codec1_out cpr 3" + "media2_in cpr 4, , hda-dsp-alt-analog-playback" + "media2_in mi, , media2_in cpr 4" + "codec2_out cpr 5, , codec2_out mo" + "codec2_out, , codec2_out cpr 5" + "codec0_in cpr 6, , codec0_in" + "codec0_in mi, , codec0_in cpr 6" + "media0_out cpr 7, , media0_out mo" + "hda-dsp-audio-analog-capture, , media0_out cpr 7" + "codec1_in cpr 8, , codec1_in" + "codec1_in mi, , codec1_in cpr 8" + "media1_out cpr 9, , media1_out mo" + "hda-dsp-audio-digital-capture, , media1_out cpr 9" + "codec2_in cpr 10, , codec2_in" + "codec2_in mi, , codec2_in cpr 10" + "media2_out cpr 11, , media2_out mo" + "hda-dsp-audio-alt-analog-capture, , media2_out cpr 11" + "hdmi1_out cpr 12, , HDMI1 Playback" + "hdmi1_out cpr 13, , hdmi1_out cpr 12" + "iDisp1_out, , hdmi1_out cpr 13" + "hdmi2_out cpr 14, , HDMI2 Playback" + "hdmi2_out cpr 15, , hdmi2_out cpr 14" + "iDisp2_out, , hdmi2_out cpr 15" + "hdmi3_out cpr 16, , HDMI3 Playback" + "hdmi3_out cpr 17, , hdmi3_out cpr 16" + "iDisp3_out, , hdmi3_out cpr 17" + "mch_cap_in cpr 18, , dmic01_hifi" + "mch_cap_in mi, , mch_cap_in cpr 18" + "mch_cap_out cpr 19, , mch_cap_out mo" + "DMIC-PT-Capture, , mch_cap_out cpr 19" + "codec0_out mo, media0_in mi Switch, media0_in mi" + "codec1_out mo, media1_in mi Switch, media1_in mi" + "codec2_out mo, media2_in mi Switch, media2_in mi" + "media0_out mo, codec0_in mi Switch, codec0_in mi" + "media1_out mo, codec1_in mi Switch, codec1_in mi" + "media2_out mo, codec2_in mi Switch, codec2_in mi" + "mch_cap_out mo, mch_cap_in mi Switch, mch_cap_in mi" + ] +} + +SectionPCMCapabilities."hda-dsp-analog-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-analog-capture" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."Analog HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-analog-dai" { + id "0" + } + + pcm."playback" { + capabilities "hda-dsp-analog-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-analog-capture" + } +} + +SectionPCMCapabilities."hda-dsp-digital-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-digital-capture" { + formats "S24_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "24" +} + +SectionPCM."Digital HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-digital-dai" { + id "1" + } + + pcm."playback" { + capabilities "hda-dsp-digital-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-digital-capture" + } +} + +SectionPCMCapabilities."hda-dsp-alt-analog-playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCMCapabilities."hda-dsp-audio-alt-analog-capture" { + formats "S24_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "24" +} + +SectionPCM."Alt Analog HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-alt-analog-dai" { + id "2" + } + + pcm."playback" { + capabilities "hda-dsp-alt-analog-playback" + } + + pcm."capture" { + capabilities "hda-dsp-audio-alt-analog-capture" + } +} + +SectionPCMCapabilities."HDMI1 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."HDA DSP HDMI1" { + index "0" + id "255" + + dai."hdmi1" { + id "3" + } + + pcm."playback" { + capabilities "HDMI1 Playback" + } +} + +SectionPCMCapabilities."HDMI2 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."HDA DSP HDMI2" { + index "0" + id "255" + + dai."hdmi2" { + id "4" + } + + pcm."playback" { + capabilities "HDMI2 Playback" + } +} + +SectionPCMCapabilities."HDMI3 Playback" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."HDA DSP HDMI3" { + index "0" + id "255" + + dai."hdmi3" { + id "5" + } + + pcm."playback" { + capabilities "HDMI3 Playback" + } +} + +SectionPCMCapabilities."DMIC-PT-Capture" { + formats "S16_LE" + rates "48000" + channels_min "2" + channels_max "2" + sig_bits "16" +} + +SectionPCM."DMIC HDA DSP" { + index "0" + id "0" + + dai."hda-dsp-dmic-dai" { + id "6" + } + + pcm."capture" { + capabilities "DMIC-PT-Capture" + } +} + +SectionVendorTuples."manifest_data num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionData."manifest_data num_desc" { + tuples "manifest_data num_desc" +} + +SectionManifest."manifest_data" { + + data [ + "manifest_data num_desc" + "mod_type_data_size_desc" + "mod_type_data" + ] +} -- 2.17.1

1 0

[PATCH] ALSA: sgio2audio: Remove usage of dropped hw_params/hw_free functions
by Thomas Bogendoerfer 06 Mar '20

06 Mar '20

Commit ee88f4ebe575 ("ALSA: mips: Use managed buffer allocation") removed superfluous hw_params/hw_free callbacks, but forgot to remove them where they were used. Fixes: ee88f4ebe575 ("ALSA: mips: Use managed buffer allocation") Signed-off-by: Thomas Bogendoerfer <tsbogend(a)alpha.franken.de> --- sound/mips/sgio2audio.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/sound/mips/sgio2audio.c b/sound/mips/sgio2audio.c index 9f60a5037f8b..5bf1ea150f26 100644 --- a/sound/mips/sgio2audio.c +++ b/sound/mips/sgio2audio.c @@ -649,8 +649,6 @@ snd_sgio2audio_pcm_pointer(struct snd_pcm_substream *substream) static const struct snd_pcm_ops snd_sgio2audio_playback1_ops = { .open = snd_sgio2audio_playback1_open, .close = snd_sgio2audio_pcm_close, - .hw_params = snd_sgio2audio_pcm_hw_params, - .hw_free = snd_sgio2audio_pcm_hw_free, .prepare = snd_sgio2audio_pcm_prepare, .trigger = snd_sgio2audio_pcm_trigger, .pointer = snd_sgio2audio_pcm_pointer, @@ -659,8 +657,6 @@ static const struct snd_pcm_ops snd_sgio2audio_playback1_ops = { static const struct snd_pcm_ops snd_sgio2audio_playback2_ops = { .open = snd_sgio2audio_playback2_open, .close = snd_sgio2audio_pcm_close, - .hw_params = snd_sgio2audio_pcm_hw_params, - .hw_free = snd_sgio2audio_pcm_hw_free, .prepare = snd_sgio2audio_pcm_prepare, .trigger = snd_sgio2audio_pcm_trigger, .pointer = snd_sgio2audio_pcm_pointer, @@ -669,8 +665,6 @@ static const struct snd_pcm_ops snd_sgio2audio_playback2_ops = { static const struct snd_pcm_ops snd_sgio2audio_capture_ops = { .open = snd_sgio2audio_capture_open, .close = snd_sgio2audio_pcm_close, - .hw_params = snd_sgio2audio_pcm_hw_params, - .hw_free = snd_sgio2audio_pcm_hw_free, .prepare = snd_sgio2audio_pcm_prepare, .trigger = snd_sgio2audio_pcm_trigger, .pointer = snd_sgio2audio_pcm_pointer, -- 2.25.0

2 1

strange loopback behaviour seen in alsamixer
by Dr. Jochen Blödorn 06 Mar '20

06 Mar '20

hi, while debugging my sound setup in Xubuntu 18.4, I came up on some strange behaviour. Reason for debugging was, I couldn't play rear line input to line output. To check, if I missed some basic settings I started alsamixer. As I always do, I toggled each setting, to make sure, that the displayed status reflects it's actual state. This routine is one relict from my old windows times :-) When I applied this method to "loopback", which initially was displayed as "enabled" ( switch from enabled to disabled and back to enabled), I instantly got sound output. This can, and must be, reproduced after every restart of the desktop. Sorry, if I posted this mail wrong way, wrong place, but I thought, the observation might be of interest. Jochen

1 0

Automatically switching snd_hda_intel.power_save value when switching from battery to ac ?
by Hans de Goede 06 Mar '20

06 Mar '20

Hi, Because of a bug-report about power-saving related plops/clocks on a Lenovo T470s, I've asked inside Red Hat if people with a T470s and running a recent kernel were also experiencing this. Most people are happy with the audio, but I did get a few bug reports about plops on the headphones-jack. One of the suggestions which I got from 2 different users is to disable power-saving for the HDA driver when on AC, esp. since most headphones-jack use (esp. with an external amplifier which amplifies the problem) is done while the laptop is sitting on a desk and thus typically is connected to a charger. I'm personally not necessarily a fan of changing settings based on being connected to ac or not, but I guess that in this case it might not be such a bad idea ? Regards, Hans

2 4

[PATCH] ALSA: usb-audio: Fix missing braces in some struct inits
by Takashi Iwai 06 Mar '20

06 Mar '20

The struct s1810c_state_packet contains the array in the first field hence zero-initialization requires a more couple of braces. Fix the compile warning pointing it out: sound/usb/mixer_s1810c.c: In function 'snd_sc1810c_get_status_field': sound/usb/mixer_s1810c.c:178:9: warning: missing braces around initializer [-Wmissing-braces] Reported-by: kbuild test robot <lkp(a)intel.com> Fixes: 8dc5efe3d17c ("ALSA: usb-audio: Add support for Presonus Studio 1810c") Link: https://lore.kernel.org/r/202002210251.WgMfvKJP%lkp@intel.com Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/usb/mixer_s1810c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/usb/mixer_s1810c.c b/sound/usb/mixer_s1810c.c index 816879a07f82..6483e47bafd0 100644 --- a/sound/usb/mixer_s1810c.c +++ b/sound/usb/mixer_s1810c.c @@ -175,8 +175,8 @@ static int snd_sc1810c_get_status_field(struct usb_device *dev, u32 *field, int field_idx, uint16_t *seqnum) { - struct s1810c_state_packet pkt_out = { 0 }; - struct s1810c_state_packet pkt_in = { 0 }; + struct s1810c_state_packet pkt_out = { { 0 } }; + struct s1810c_state_packet pkt_in = { { 0 } }; int ret = 0; pkt_out.fields[SC1810C_STATE_F1_IDX] = SC1810C_SET_STATE_F1; -- 2.16.4

1 0

[PATCH] ALSA: usb-audio: Add support for MOTU MicroBook IIc
by Alexander Tsoy 06 Mar '20

06 Mar '20

MicroBook IIc operates in UAC2 mode by default. This patch addresses several issues with it: - MicroBook II and IIc shares the same USB ID. We can distinguish them by interface class. - MaxPacketsOnly attribute is erroneously set in endpoint descriptors. As a result this card produces noise with all sample rates other than 96 KHz. This also causes issues like IOMMU page faults and other problems with host controller. - Sample rate changes takes more than 2 seconds for this device. Clock validity request returns false during that period, so the clock validity quirk is required. Signed-off-by: Alexander Tsoy <alexander(a)tsoy.me> --- sound/usb/clock.c | 59 ++++++++++++++++++++++++++++++++-------- sound/usb/pcm.c | 7 ++++- sound/usb/quirks-table.h | 2 +- sound/usb/quirks.c | 18 +++++++++++- 4 files changed, 72 insertions(+), 14 deletions(-) diff --git a/sound/usb/clock.c b/sound/usb/clock.c index a48313dfa967..b118cf97607f 100644 --- a/sound/usb/clock.c +++ b/sound/usb/clock.c @@ -151,16 +151,15 @@ static int uac_clock_selector_set_val(struct snd_usb_audio *chip, int selector_i return ret; } -/* - * Assume the clock is valid if clock source supports only one single sample - * rate, the terminal is connected directly to it (there is no clock selector) - * and clock type is internal. This is to deal with some Denon DJ controllers - * that always reports that clock is invalid. - */ static bool uac_clock_source_is_valid_quirk(struct snd_usb_audio *chip, struct audioformat *fmt, int source_id) { + bool ret = false; + int count; + unsigned char data; + struct usb_device *dev = chip->dev; + if (fmt->protocol == UAC_VERSION_2) { struct uac_clock_source_descriptor *cs_desc = snd_usb_find_clock_source(chip->ctrl_intf, source_id); @@ -168,13 +167,51 @@ static bool uac_clock_source_is_valid_quirk(struct snd_usb_audio *chip, if (!cs_desc) return false; - return (fmt->nr_rates == 1 && - (fmt->clock & 0xff) == cs_desc->bClockID && - (cs_desc->bmAttributes & 0x3) != - UAC_CLOCK_SOURCE_TYPE_EXT); + /* + * Assume the clock is valid if clock source supports only one + * single sample rate, the terminal is connected directly to it + * (there is no clock selector) and clock type is internal. + * This is to deal with some Denon DJ controllers that always + * reports that clock is invalid. + */ + if (fmt->nr_rates == 1 && + (fmt->clock & 0xff) == cs_desc->bClockID && + (cs_desc->bmAttributes & 0x3) != + UAC_CLOCK_SOURCE_TYPE_EXT) + return true; + } + + /* + * MOTU MicroBook IIc + * Sample rate changes takes more than 2 seconds for this device. Clock + * validity request returns false during that period. + */ + if (chip->usb_id == USB_ID(0x07fd, 0x0004)) { + count = 0; + + while ((!ret) && (count < 50)) { + int err; + + msleep(100); + + err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR, + USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN, + UAC2_CS_CONTROL_CLOCK_VALID << 8, + snd_usb_ctrl_intf(chip) | (source_id << 8), + &data, sizeof(data)); + if (err < 0) { + dev_warn(&dev->dev, + "%s(): cannot get clock validity for id %d\n", + __func__, source_id); + return false; + } + + ret = !!data; + count++; + } } - return false; + return ret; } static bool uac_clock_source_is_valid(struct snd_usb_audio *chip, diff --git a/sound/usb/pcm.c b/sound/usb/pcm.c index bd258f1ec2dd..a4e4064f9aee 100644 --- a/sound/usb/pcm.c +++ b/sound/usb/pcm.c @@ -357,7 +357,12 @@ static int set_sync_ep_implicit_fb_quirk(struct snd_usb_substream *subs, ep = 0x81; ifnum = 1; goto add_sync_ep_from_ifnum; - case USB_ID(0x07fd, 0x0004): /* MOTU MicroBook II */ + case USB_ID(0x07fd, 0x0004): /* MOTU MicroBook II/IIc */ + /* MicroBook IIc */ + if (altsd->bInterfaceClass == USB_CLASS_AUDIO) + return 0; + + /* MicroBook II */ ep = 0x84; ifnum = 0; goto add_sync_ep_from_ifnum; diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h index d187aa6d50db..1c8719292eee 100644 --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h @@ -3472,7 +3472,7 @@ AU0828_DEVICE(0x2040, 0x7270, "Hauppauge", "HVR-950Q"), }, /* MOTU Microbook II */ { - USB_DEVICE(0x07fd, 0x0004), + USB_DEVICE_VENDOR_SPEC(0x07fd, 0x0004), .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { .vendor_name = "MOTU", .product_name = "MicroBookII", diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c index 7f558f4b4520..a7bd32bd301c 100644 --- a/sound/usb/quirks.c +++ b/sound/usb/quirks.c @@ -1316,7 +1316,15 @@ int snd_usb_apply_boot_quirk(struct usb_device *dev, case USB_ID(0x2466, 0x8010): /* Fractal Audio Axe-Fx 3 */ return snd_usb_axefx3_boot_quirk(dev); case USB_ID(0x07fd, 0x0004): /* MOTU MicroBook II */ - return snd_usb_motu_microbookii_boot_quirk(dev); + /* + * For some reason interface 3 with vendor-spec class is + * detected on MicroBook IIc. + */ + if (get_iface_desc(intf->altsetting)->bInterfaceClass == + USB_CLASS_VENDOR_SPEC && + get_iface_desc(intf->altsetting)->bInterfaceNumber < 3) + return snd_usb_motu_microbookii_boot_quirk(dev); + break; } return 0; @@ -1754,5 +1762,13 @@ void snd_usb_audioformat_attributes_quirk(struct snd_usb_audio *chip, else fp->ep_attr |= USB_ENDPOINT_SYNC_SYNC; break; + case USB_ID(0x07fd, 0x0004): /* MOTU MicroBook IIc */ + /* + * MaxPacketsOnly attribute is erroneously set in endpoint + * descriptors. As a result this card produces noise with + * all sample rates other than 96 KHz. + */ + fp->attributes &= ~UAC_EP_CS_ATTR_FILL_MAX; + break; } } -- 2.24.1

2 1

Re: [PATCH v4 10/10] sound: bt87x: use pci_status_get_and_clear_errors
by Takashi Iwai 06 Mar '20

06 Mar '20

On Sat, 29 Feb 2020 23:29:07 +0100, Heiner Kallweit wrote: > > Use new helper pci_status_get_and_clear_errors() to simplify the code. > > Signed-off-by: Heiner Kallweit <hkallweit1(a)gmail.com> Acked-by: Takashi Iwai <tiwai(a)suse.de> thanks, Takashi > --- > sound/pci/bt87x.c | 7 +------ > 1 file changed, 1 insertion(+), 6 deletions(-) > > diff --git a/sound/pci/bt87x.c b/sound/pci/bt87x.c > index 8c48864c8..656750466 100644 > --- a/sound/pci/bt87x.c > +++ b/sound/pci/bt87x.c > @@ -271,13 +271,8 @@ static void snd_bt87x_free_risc(struct snd_bt87x *chip) > > static void snd_bt87x_pci_error(struct snd_bt87x *chip, unsigned int status) > { > - u16 pci_status; > + int pci_status = pci_status_get_and_clear_errors(chip->pci); > > - pci_read_config_word(chip->pci, PCI_STATUS, &pci_status); > - pci_status &= PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | > - PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | > - PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY; > - pci_write_config_word(chip->pci, PCI_STATUS, pci_status); > if (pci_status != PCI_STATUS_DETECTED_PARITY) > dev_err(chip->card->dev, > "Aieee - PCI error! status %#08x, PCI status %#04x\n", > -- > 2.25.1 > >

1 0

[PATCH v2 0/1] Fix silent output on Gigabyte X570 Aorus Master
by Christian Lachner 06 Mar '20

06 Mar '20

The Gigabyte X570 Aorus Master motherboard with ALC1220 codec requires a similar workaround for Clevo laptops to enforce the DAC/mixer connection path. This patch sets up a quirk entry for that. It was tested by myself on my own hardware for some time and it works just fine. We should probably rename ALC1220_FIXUP_CLEVO_P950 at some point as the amount of non-Clevo hardware needing this workaround is growing. Christian Lachner (1): ALSA: hda/realtek - Fix silent output on Gigabyte X570 Aorus Master sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) base-commit: 98d54f81e36ba3bf92172791eba5ca5bd813989b -- 2.25.1

3 4

[PATCH] sound: korg1212: fix if-statement empty body warnings
by Randy Dunlap 06 Mar '20

06 Mar '20

From: Randy Dunlap <rdunlap(a)infradead.org> Fix gcc warnings when -Wextra is used by using an empty do-while block instead of <nothing>. Fixes these build warnings: ../sound/pci/korg1212/korg1212.c:674:44: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:708:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:730:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:853:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:1013:44: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:1035:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:1052:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:1066:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:1087:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:1094:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:1208:43: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] ../sound/pci/korg1212/korg1212.c:2360:102: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] Signed-off-by: Randy Dunlap <rdunlap(a)infradead.org> Cc: Jaroslav Kysela <perex(a)perex.cz> Cc: Takashi Iwai <tiwai(a)suse.com> Cc: alsa-devel(a)alsa-project.org --- sound/pci/korg1212/korg1212.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- linux-next-20200225.orig/sound/pci/korg1212/korg1212.c +++ linux-next-20200225/sound/pci/korg1212/korg1212.c @@ -30,7 +30,7 @@ #if K1212_DEBUG_LEVEL > 0 #define K1212_DEBUG_PRINTK(fmt,args...) printk(KERN_DEBUG fmt,##args) #else -#define K1212_DEBUG_PRINTK(fmt,...) +#define K1212_DEBUG_PRINTK(fmt,...) do { } while (0) #endif #if K1212_DEBUG_LEVEL > 1 #define K1212_DEBUG_PRINTK_VERBOSE(fmt,args...) printk(KERN_DEBUG fmt,##args)

2 1

Get cross compilation to work
by GitHub pull_request - opened 06 Mar '20

06 Mar '20

alsa-project/alsa-firmware pull request #1 was opened from matthewbauer: Rebased version of original patch by Ding Xiang Fei found in https://github.com/NixOS/nixpkgs/pull/63866. This version applies in alsa-firmware-1.2.1. Co-authored-by: Ding Xiang Fei <dingxiangfei2009(a)users.noreply.github.com> Request URL : https://github.com/alsa-project/alsa-firmware/pull/1 Patch URL : https://github.com/alsa-project/alsa-firmware/pull/1.patch Repository URL: https://github.com/alsa-project/alsa-firmware

1 0

[PATCH] ASoC: Intel: boards: Use FS as nau8825 sysclk in nau88125_ssm4567 machine
by Radoslaw Biernacki 05 Mar '20

05 Mar '20

From: Ben Zhang <benzh(a)chromium.org> This single fix address two issues on machine with nau88125 + ssm4567: 1) Audio distortion, due to lack of required clock rate on MCLK line 2) Loud audible "pops" on headphones if there is no sysclk during nau8825 playback power up sequence Explanation for: 1) Due to Skylake HW limitation, MCLK pin can only output 24MHz clk rate (it can be only connected to XTAL parent clk). The BCLK pin can be driven by dividers and therefore FW is able to set it to rate required by chosen audio format. According to nau8825 datasheet, 256*FS sysclk gives the best audio quality and the only way to achieve this (taking into account the above limitations) its to regenerate the MCLK from BCLK on nau8825 side by FFL. Without required clk rate, audio is distorted by added harmonics. 2) Currently Skylake does not output MCLK/FS when the back-end DAI op hw_param is called, so we cannot switch to MCLK/FS in hw_param. This patch reduces pop by letting nau8825 keep using its internal VCO clock during widget power up sequence, until SNDRV_PCM_TRIGGER_START when MCLK/FS is available. Once device resumes, the system will only enable power sequence for playback without doing hardware parameter, audio format, and PLL configure. In the mean time, the jack detecion sequence has changed PLL parameters and switched to internal clock. Thus, the playback signal distorted without correct PLL parameters. That is why we need to configure the PLL again in SNDRV_PCM_TRIGGER_RESUME case. Signed-off-by: John Hsu <KCHSU0(a)nuvoton.com> Signed-off-by: Yong Zhi <yong.zhi(a)intel.com> Signed-off-by: Mac Chiang <mac.chiang(a)intel.com> Signed-off-by: Ben Zhang <benzh(a)chromium.org> Signed-off-by: Radoslaw Biernacki <rad(a)semihalf.com> --- sound/soc/intel/boards/skl_nau88l25_ssm4567.c | 71 ++++++++++++++----- 1 file changed, 52 insertions(+), 19 deletions(-) diff --git a/sound/soc/intel/boards/skl_nau88l25_ssm4567.c b/sound/soc/intel/boards/skl_nau88l25_ssm4567.c index c99c8b23e509..c5354da49670 100644 --- a/sound/soc/intel/boards/skl_nau88l25_ssm4567.c +++ b/sound/soc/intel/boards/skl_nau88l25_ssm4567.c @@ -12,6 +12,7 @@ #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/delay.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/soc.h> @@ -57,7 +58,7 @@ static const struct snd_kcontrol_new skylake_controls[] = { }; static int platform_clock_control(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *k, int event) + struct snd_kcontrol *k, int event) { struct snd_soc_dapm_context *dapm = w->dapm; struct snd_soc_card *card = dapm->card; @@ -70,14 +71,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, return -EIO; } - if (SND_SOC_DAPM_EVENT_ON(event)) { - ret = snd_soc_dai_set_sysclk(codec_dai, - NAU8825_CLK_MCLK, 24000000, SND_SOC_CLOCK_IN); - if (ret < 0) { - dev_err(card->dev, "set sysclk err = %d\n", ret); - return -EIO; - } - } else { + if (!SND_SOC_DAPM_EVENT_ON(event)) { ret = snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_INTERNAL, 0, SND_SOC_CLOCK_IN); if (ret < 0) { @@ -85,6 +79,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, return -EIO; } } + return ret; } @@ -344,24 +339,40 @@ static int skylake_dmic_fixup(struct snd_soc_pcm_runtime *rtd, return 0; } -static int skylake_nau8825_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) +static int skylake_nau8825_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_pcm_runtime *runtime = substream->runtime; struct snd_soc_dai *codec_dai = rtd->codec_dai; - int ret; - - ret = snd_soc_dai_set_sysclk(codec_dai, - NAU8825_CLK_MCLK, 24000000, SND_SOC_CLOCK_IN); + int ret = 0; - if (ret < 0) - dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n", ret); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + ret = snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_FLL_FS, 0, + SND_SOC_CLOCK_IN); + if (ret < 0) { + dev_err(codec_dai->dev, "can't set FS clock %d\n", ret); + break; + } + ret = snd_soc_dai_set_pll(codec_dai, 0, 0, runtime->rate, + runtime->rate * 256); + if (ret < 0) + dev_err(codec_dai->dev, "can't set FLL: %d\n", ret); + break; + case SNDRV_PCM_TRIGGER_RESUME: + ret = snd_soc_dai_set_pll(codec_dai, 0, 0, runtime->rate, + runtime->rate * 256); + if (ret < 0) + dev_err(codec_dai->dev, "can't set FLL: %d\n", ret); + msleep(20); + break; + } return ret; } -static const struct snd_soc_ops skylake_nau8825_ops = { - .hw_params = skylake_nau8825_hw_params, +static struct snd_soc_ops skylake_nau8825_ops = { + .trigger = skylake_nau8825_trigger, }; static const unsigned int channels_dmic[] = { @@ -671,10 +682,32 @@ static int skylake_card_late_probe(struct snd_soc_card *card) return hdac_hdmi_jack_port_init(component, &card->dapm); } +static int __maybe_unused skylake_nau8825_resume_post(struct snd_soc_card *card) +{ + struct snd_soc_dai *codec_dai; + + codec_dai = snd_soc_card_get_codec_dai(card, SKL_NUVOTON_CODEC_DAI); + if (!codec_dai) { + dev_err(card->dev, "Codec dai not found\n"); + return -EIO; + } + + dev_dbg(codec_dai->dev, "playback_active:%d playback_widget->active:%d codec_dai->rate:%d\n", + codec_dai->playback_active, codec_dai->playback_widget->active, + codec_dai->rate); + + if (codec_dai->playback_active && codec_dai->playback_widget->active) + snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_FLL_FS, 0, + SND_SOC_CLOCK_IN); + + return 0; +} + /* skylake audio machine driver for SPT + NAU88L25 */ static struct snd_soc_card skylake_audio_card = { .name = "sklnau8825adi", .owner = THIS_MODULE, + .resume_post = skylake_nau8825_resume_post, .dai_link = skylake_dais, .num_links = ARRAY_SIZE(skylake_dais), .controls = skylake_controls, -- 2.17.1

1 0

[PATCH] ALSA: hda/realtek - Enable the headset of ASUS B9450FA with ALC294
by Jian-Hong Pan 05 Mar '20

05 Mar '20

A headset on the laptop like ASUS B9450FA does not work, until quirk ALC294_FIXUP_ASUS_HPE is applied. Signed-off-by: Jian-Hong Pan <jian-hong(a)endlessm.com> Singed-off-by: Kailang Yang <kailang(a)realtek.com> --- sound/pci/hda/patch_realtek.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 477589e7ec1d..a47f6404aea9 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -5920,7 +5920,7 @@ enum { ALC289_FIXUP_DUAL_SPK, ALC294_FIXUP_SPK2_TO_DAC1, ALC294_FIXUP_ASUS_DUAL_SPK, - + ALC294_FIXUP_ASUS_HPE, }; static const struct hda_fixup alc269_fixups[] = { @@ -7040,7 +7040,17 @@ static const struct hda_fixup alc269_fixups[] = { .chained = true, .chain_id = ALC294_FIXUP_SPK2_TO_DAC1 }, - + [ALC294_FIXUP_ASUS_HPE] = { + .type = HDA_FIXUP_VERBS, + .v.verbs = (const struct hda_verb[]) { + /* Set EAPD high */ + { 0x20, AC_VERB_SET_COEF_INDEX, 0x0f }, + { 0x20, AC_VERB_SET_PROC_COEF, 0x7774 }, + { } + }, + .chained = true, + .chain_id = ALC294_FIXUP_ASUS_HEADSET_MIC + }, }; static const struct snd_pci_quirk alc269_fixup_tbl[] = { @@ -7204,6 +7214,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x1043, 0x17d1, "ASUS UX431FL", ALC294_FIXUP_ASUS_DUAL_SPK), SND_PCI_QUIRK(0x1043, 0x18b1, "Asus MJ401TA", ALC256_FIXUP_ASUS_HEADSET_MIC), + SND_PCI_QUIRK(0x1043, 0x19ce, "ASUS B9450FA", ALC294_FIXUP_ASUS_HPE), SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW), SND_PCI_QUIRK(0x1043, 0x1a30, "ASUS X705UD", ALC256_FIXUP_ASUS_MIC), SND_PCI_QUIRK(0x1043, 0x1b13, "Asus U41SV", ALC269_FIXUP_INV_DMIC), -- 2.25.1

2 1

Re: [PATCH 1/1] ALSA: hda/realtek - Fix silent output on Gigabyte X570 Aorus Master
by Takashi Iwai 05 Mar '20

05 Mar '20

On Sun, 23 Feb 2020 10:24:16 +0100, Christian Lachner wrote: > > The Gigabyte X570 Aorus Master motherboard with ALC1220 codec > requires a similar workaround for Clevo laptops to enforce the > DAC/mixer connection path. Set up a quirk entry for that. > > BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=205275 > Signed-off-by: Christian Lachner <gladiac(a)gmail.com> Applied now. Thanks. Takashi

1 0

Enable Headset Button for ThinkPad X1
by Kailang 05 Mar '20

05 Mar '20

Hi Takashi, Lenovo ThinkPad X1 want to support Headset Button. Attach patch will enable it. BR, Kailang

2 1

RE: Enable Headset Mic for Dell desktop
by Kailang 05 Mar '20

05 Mar '20

Sorry! Forgot attach file. > -----Original Message----- > From: Kailang > Sent: Thursday, February 20, 2020 4:30 PM > To: Takashi Iwai (tiwai(a)suse.de) <tiwai(a)suse.de> > Cc: (alsa-devel(a)alsa-project.org) <alsa-devel(a)alsa-project.org> > Subject: Enable Headset Mic for Dell desktop > > Hi Takashi, > > Attach patch was supported headset Mic. > > BR, > Kailang

2 1

snd_hda_intel.power_save=1 causes pops/clicks on Lenovo T470s headphone jack?
by Hans de Goede 05 Mar '20

05 Mar '20

Hi, Because of a bug-report about power-saving related plops/clocks on a Lenovo T470s, I've asked inside Red Hat if people with a T470s and running a recent kernel were also experiencing this. Most people are happy with the audio, but I did get a few bug reports about plops on the headphones-jack. Is this a know issue? and/or is there anything we can do about this? Regards, Hans

1 1

[PATCH for-next] ASoC: tlv320adcx140: Fix mic_bias and vref device tree verification
by Dan Murphy 05 Mar '20

05 Mar '20

Fix the range verification check for the mic_bias and vref device tree entries. Fixes 37bde5acf040 ("ASoC: tlv320adcx140: Add the tlv320adcx140 codec driver family") Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- sound/soc/codecs/tlv320adcx140.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/sound/soc/codecs/tlv320adcx140.c b/sound/soc/codecs/tlv320adcx140.c index 93a0cb8e662c..38897568ee96 100644 --- a/sound/soc/codecs/tlv320adcx140.c +++ b/sound/soc/codecs/tlv320adcx140.c @@ -748,9 +748,8 @@ static int adcx140_codec_probe(struct snd_soc_component *component) if (ret) bias_source = ADCX140_MIC_BIAS_VAL_VREF; - if (bias_source != ADCX140_MIC_BIAS_VAL_VREF && - bias_source != ADCX140_MIC_BIAS_VAL_VREF_1096 && - bias_source != ADCX140_MIC_BIAS_VAL_AVDD) { + if (bias_source < ADCX140_MIC_BIAS_VAL_VREF || + bias_source > ADCX140_MIC_BIAS_VAL_AVDD) { dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); return -EINVAL; } @@ -760,9 +759,8 @@ static int adcx140_codec_probe(struct snd_soc_component *component) if (ret) vref_source = ADCX140_MIC_BIAS_VREF_275V; - if (vref_source != ADCX140_MIC_BIAS_VREF_275V && - vref_source != ADCX140_MIC_BIAS_VREF_25V && - vref_source != ADCX140_MIC_BIAS_VREF_1375V) { + if (vref_source < ADCX140_MIC_BIAS_VREF_275V || + vref_source > ADCX140_MIC_BIAS_VREF_1375V) { dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); return -EINVAL; } -- 2.25.1

2 1

[PATCH] ASoC: sprd: Allow the MCDT driver to build into modules
by Baolin Wang 05 Mar '20

05 Mar '20

Change the config to 'tristate' for MCDT driver to allow it to build into modules, as well as changing to use IS_ENABLED() to validate if need supply dummy functions when building the MCDT driver as a module. Signed-off-by: Baolin Wang <baolin.wang7(a)gmail.com> --- sound/soc/sprd/Kconfig | 2 +- sound/soc/sprd/sprd-mcdt.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/sprd/Kconfig b/sound/soc/sprd/Kconfig index 5474fd3..5e0ac82 100644 --- a/sound/soc/sprd/Kconfig +++ b/sound/soc/sprd/Kconfig @@ -8,7 +8,7 @@ config SND_SOC_SPRD the Spreadtrum SoCs' Audio interfaces. config SND_SOC_SPRD_MCDT - bool "Spreadtrum multi-channel data transfer support" + tristate "Spreadtrum multi-channel data transfer support" depends on SND_SOC_SPRD help Say y here to enable multi-channel data transfer support. It diff --git a/sound/soc/sprd/sprd-mcdt.h b/sound/soc/sprd/sprd-mcdt.h index 9cc7e207..679e3af 100644 --- a/sound/soc/sprd/sprd-mcdt.h +++ b/sound/soc/sprd/sprd-mcdt.h @@ -48,7 +48,7 @@ struct sprd_mcdt_chan { struct list_head list; }; -#ifdef CONFIG_SND_SOC_SPRD_MCDT +#if IS_ENABLED(CONFIG_SND_SOC_SPRD_MCDT) struct sprd_mcdt_chan *sprd_mcdt_request_chan(u8 channel, enum sprd_mcdt_channel_type type); void sprd_mcdt_free_chan(struct sprd_mcdt_chan *chan); -- 1.9.1

2 1

Applied "ASoC: soc-pcm: use defined stream" to the asoc tree
by Mark Brown 05 Mar '20

05 Mar '20

The patch ASoC: soc-pcm: use defined stream has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 25c2f5156dd57f03aee2de079248c23a56222c92 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Date: Thu, 27 Feb 2020 10:54:38 +0900 Subject: [PATCH] ASoC: soc-pcm: use defined stream Many functions defines "stream = substream->stream", but some of them is using "substream->stream" instead of "stream". It is pointless. This patch uses defined stream. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Link: https://lore.kernel.org/r/87mu947q1t.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie(a)kernel.org> --- sound/soc/soc-pcm.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c index 90857138c823..8c27eb4d5e4c 100644 --- a/sound/soc/soc-pcm.c +++ b/sound/soc/soc-pcm.c @@ -644,8 +644,7 @@ static void soc_pcm_init_runtime_hw(struct snd_pcm_substream *substream) * bailed out on a higher level, since there would be no * CODEC to support the transfer direction in that case. */ - if (!snd_soc_dai_stream_valid(codec_dai, - substream->stream)) + if (!snd_soc_dai_stream_valid(codec_dai, stream)) continue; codec_stream = snd_soc_dai_get_pcm_stream(codec_dai, stream); @@ -2149,7 +2148,7 @@ static int dpcm_fe_dai_startup(struct snd_pcm_substream *fe_substream) dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_FE); - ret = dpcm_be_dai_startup(fe, fe_substream->stream); + ret = dpcm_be_dai_startup(fe, stream); if (ret < 0) { dev_err(fe->dev,"ASoC: failed to start some BEs %d\n", ret); goto be_err; @@ -2180,7 +2179,7 @@ static int dpcm_fe_dai_startup(struct snd_pcm_substream *fe_substream) return 0; unwind: - dpcm_be_dai_startup_unwind(fe, fe_substream->stream); + dpcm_be_dai_startup_unwind(fe, stream); be_err: dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_NO); return ret; @@ -2234,7 +2233,7 @@ static int dpcm_fe_dai_shutdown(struct snd_pcm_substream *substream) dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_FE); /* shutdown the BEs */ - dpcm_be_dai_shutdown(fe, substream->stream); + dpcm_be_dai_shutdown(fe, stream); dev_dbg(fe->dev, "ASoC: close FE %s\n", fe->dai_link->name); @@ -2412,9 +2411,9 @@ static int dpcm_fe_dai_hw_params(struct snd_pcm_substream *substream, mutex_lock_nested(&fe->card->mutex, SND_SOC_CARD_CLASS_RUNTIME); dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_FE); - memcpy(&fe->dpcm[substream->stream].hw_params, params, + memcpy(&fe->dpcm[stream].hw_params, params, sizeof(struct snd_pcm_hw_params)); - ret = dpcm_be_dai_hw_params(fe, substream->stream); + ret = dpcm_be_dai_hw_params(fe, stream); if (ret < 0) { dev_err(fe->dev,"ASoC: hw_params BE failed %d\n", ret); goto out; @@ -2736,7 +2735,7 @@ static int dpcm_fe_dai_prepare(struct snd_pcm_substream *substream) goto out; } - ret = dpcm_be_dai_prepare(fe, substream->stream); + ret = dpcm_be_dai_prepare(fe, stream); if (ret < 0) goto out; -- 2.20.1

1 0

Applied "ASoC: soc-pcm: remove duplicate be check from dpcm_add_paths()" to the asoc tree
by Mark Brown 05 Mar '20

05 Mar '20

The patch ASoC: soc-pcm: remove duplicate be check from dpcm_add_paths() has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 6e02feb0d2663c1b7caa5e271c2a60e219f0ca07 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Date: Thu, 27 Feb 2020 10:54:48 +0900 Subject: [PATCH] ASoC: soc-pcm: remove duplicate be check from dpcm_add_paths() dpcm_add_paths() checks returned be from dpcm_get_be() static int dpcm_add_paths(...) { ... for_each_dapm_widgets(list, i, widget) { ... be = dpcm_get_be(...); ... /* make sure BE is a real BE */ => if (!be->dai_link->no_pcm) continue; ... } ... } But, dpcm_get_be() itself is checking it already. dpcm_get_be(...) { ... for_each_card_rtds(card, be) { => if (!be->dai_link->no_pcm) continue; ... if (...) => return be; } return NULL } This patch removes duplicate check Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Link: https://lore.kernel.org/r/87lfoo7q1j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie(a)kernel.org> --- sound/soc/soc-pcm.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c index 8c27eb4d5e4c..e3a2c4f7757b 100644 --- a/sound/soc/soc-pcm.c +++ b/sound/soc/soc-pcm.c @@ -1690,10 +1690,6 @@ static int dpcm_add_paths(struct snd_soc_pcm_runtime *fe, int stream, continue; } - /* make sure BE is a real BE */ - if (!be->dai_link->no_pcm) - continue; - /* don't connect if FE is not running */ if (!fe->dpcm[stream].runtime && !fe->fe_compr) continue; -- 2.20.1

1 0

sof-hda-dsp: Support systems without integrated graphics audio
by GitHub pull_request - opened 05 Mar '20

05 Mar '20

alsa-project/alsa-ucm-conf pull request #15 was opened from kv2019i: On systems where integrated graphics audio is not present or is disabled, the HDMI PCM nodes are disabled. Add rules to detect these systems by checking presence of HDMI jack controls with UCM2 rules. Signed-off-by: Kai Vehmanen <kai.vehmanen(a)linux.intel.com> Request URL : https://github.com/alsa-project/alsa-ucm-conf/pull/15 Patch URL : https://github.com/alsa-project/alsa-ucm-conf/pull/15.patch Repository URL: https://github.com/alsa-project/alsa-ucm-conf

1 0

[PATCH v2 0/8] ASoC: soc-pcm cleanup step5
by Kuninori Morimoto 05 Mar '20

05 Mar '20

Hi Mark These are v2 of soc-pcm cleanup step5. These are based on latest for-5.7 branch. Mainly v2 fixed the points reviewed in v1. [7/8] patch might exchange the behavior Kuninori Morimoto (8): 1) ASoC: soc-pcm: use defined stream 2) ASoC: soc-pcm: remove duplicate be check from dpcm_add_paths() 3) ASoC: soc-pcm: move dpcm_fe_dai_close() 4) ASoC: soc-pcm: add dpcm_fe_dai_cleanup() 5) ASoC: soc-pcm: use snd_soc_dai_get_pcm_stream() at dpcm_set_fe_runtime() 6) ASoC: soc-pcm: check DAI's activity more simply 7) ASoC: soc-pcm: Do Digital Mute for both CPU/Codec in same timing. 8) ASoC: soc-pcm: tidyup dulicate handing at dpcm_fe_dai_startup() sound/soc/soc-pcm.c | 114 +++++++++++++++++++------------------------- 1 file changed, 50 insertions(+), 64 deletions(-) -- 2.17.1

2 12

[PATCH] ASoC: wm8741: Fix typo in Kconfig prompt
by Axel Lin 05 Mar '20

05 Mar '20

Fix trivial copy-n-paste mistake. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- sound/soc/codecs/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 6aee70ed43df..fd09656d2f6b 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1486,7 +1486,7 @@ config SND_SOC_WM8737 depends on SND_SOC_I2C_AND_SPI config SND_SOC_WM8741 - tristate "Wolfson Microelectronics WM8737 DAC" + tristate "Wolfson Microelectronics WM8741 DAC" depends on SND_SOC_I2C_AND_SPI config SND_SOC_WM8750 -- 2.20.1

2 2

[PATCH] ASoc: amd: acp3x: Add missing include <linux/io.h>
by YueHaibing 05 Mar '20

05 Mar '20

gcc 7.4.0 build fails: In file included from sound/soc/amd/acp3x-rt5682-max9836.c:20:0: sound/soc/amd/raven/acp3x.h: In function rv_readl: sound/soc/amd/raven/acp3x.h:113:9: error: implicit declaration of function readl; did you mean rv_readl? [-Werror=implicit-function-declaration] return readl(base_addr - ACP3x_PHY_BASE_ADDRESS); ^~~~~ rv_readl sound/soc/amd/raven/acp3x.h: In function rv_writel: sound/soc/amd/raven/acp3x.h:118:2: error: implicit declaration of function writel; did you mean rv_writel? [-Werror=implicit-function-declaration] writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS); ^~~~~~ rv_writel Add <linux/io.h> to fix this. Reported-by: Hulk Robot <hulkci(a)huawei.com> Fixes: 6b8e4e7db3cd ("ASoC: amd: Add machine driver for Raven based platform") Signed-off-by: YueHaibing <yuehaibing(a)huawei.com> --- sound/soc/amd/acp3x-rt5682-max9836.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/amd/acp3x-rt5682-max9836.c b/sound/soc/amd/acp3x-rt5682-max9836.c index 511b8b1..b4f68c5 100644 --- a/sound/soc/amd/acp3x-rt5682-max9836.c +++ b/sound/soc/amd/acp3x-rt5682-max9836.c @@ -16,6 +16,7 @@ #include <linux/module.h> #include <linux/i2c.h> #include <linux/input.h> +#include <linux/io.h> #include <linux/acpi.h> #include "raven/acp3x.h" -- 2.7.4

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