April 2018 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCH 0/3] ASoC: Intel: Skylake: Driver updates for new DSP FW
by Sriram Periyasamy 17 Apr '18

17 Apr '18

The series contains driver changes which are needed to be compatible with the new DSP Firmware. Divya Prakash (1): ASoC: Intel: Skylake: Reset DSP pipe in skl_pcm_hw_free Pardha Saradhi K (1): ASoC: Intel: Skylake: Reset DSP Pipelines in prepare Pradeep Tewani (1): ASoC: Intel: Skylake: Unify the fw ops for SKL and KBL sound/soc/intel/skylake/skl-messages.c | 2 +- sound/soc/intel/skylake/skl-pcm.c | 36 ++++++++++++++++++++++++++++++---- sound/soc/intel/skylake/skl-sst-dsp.h | 3 --- sound/soc/intel/skylake/skl-sst.c | 34 ++------------------------------ 4 files changed, 35 insertions(+), 40 deletions(-) -- 2.7.4

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[alsa-devel] [PATCH] ASoC: Intel: Skylake: Reset stream to link mapping
by Sanyog Kale 17 Apr '18

17 Apr '18

From: Rakesh Ughreja <rakesh.a.ughreja(a)intel.com> By default all the streams are mapped to all links after controller is reset which causes stream to be broadcast on all the links. This patch resets the stream-link mapping after controller reset. The stream is mapped later to the appropriate link as part of stream setup. Tested-by: Abhijeet Kumar <abhijeet.kumar(a)intel.com> Signed-off-by: Rakesh Ughreja <rakesh.a.ughreja(a)intel.com> Signed-off-by: Sanyog Kale <sanyog.r.kale(a)intel.com> --- sound/soc/intel/skylake/skl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c index abf324747b29..f0d9793f872a 100644 --- a/sound/soc/intel/skylake/skl.c +++ b/sound/soc/intel/skylake/skl.c @@ -127,10 +127,17 @@ static void skl_clock_power_gating(struct device *dev, bool enable) */ static int skl_init_chip(struct hdac_bus *bus, bool full_reset) { + struct hdac_ext_bus *ebus = hbus_to_ebus(bus); + struct hdac_ext_link *hlink; int ret; skl_enable_miscbdcge(bus->dev, false); ret = snd_hdac_bus_init_chip(bus, full_reset); + + /* Reset stream-to-link mapping */ + list_for_each_entry(hlink, &ebus->hlink_list, list) + bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); + skl_enable_miscbdcge(bus->dev, true); return ret; -- 2.13.0

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[alsa-devel] [PATCH 0/3] PCM cleanups
by Takashi Iwai 17 Apr '18

17 Apr '18

Hi, this is a patch series for minor cleanups of PCM core codes. Mostly to unify the direction-separated PCM callbacks to unified ones. Takashi === Takashi Iwai (3): ALSA: pcm: Clean up with snd_pcm_avail() and snd_pcm_hw_avail() helpers ALSA: pcm: Unify playback and capture poll callbacks ALSA: pcm: Unify delay calculation in snd_pcm_status() and snd_pcm_delay() sound/core/pcm_compat.c | 10 +-- sound/core/pcm_lib.c | 15 +---- sound/core/pcm_local.h | 18 +++++ sound/core/pcm_native.c | 175 ++++++++++++------------------------------------ 4 files changed, 67 insertions(+), 151 deletions(-) -- 2.16.3

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[alsa-devel] [PATCH v3 1/3] dell-led: Change dell-led.h to dell-common.h
by Kai-Heng Feng 17 Apr '18

17 Apr '18

This header will be used for more than just led. Change it to a more generic name. Cc: Mario Limonciello <mario.limonciello(a)dell.com> Signed-off-by: Kai-Heng Feng <kai.heng.feng(a)canonical.com> --- v3: Simplify dell_switchable_gfx_is_enabled() by returning bool instead of error code. Use DMI_DEV_TYPE_OEM_STRING to match Dell System. v2: Mario suggested to squash the HDA part into the same series. drivers/platform/x86/dell-laptop.c | 2 +- include/linux/{dell-led.h => dell-common.h} | 4 ++-- sound/pci/hda/dell_wmi_helper.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) rename include/linux/{dell-led.h => dell-common.h} (61%) diff --git a/drivers/platform/x86/dell-laptop.c b/drivers/platform/x86/dell-laptop.c index c52c6723374b..8ba820e6c3d0 100644 --- a/drivers/platform/x86/dell-laptop.c +++ b/drivers/platform/x86/dell-laptop.c @@ -29,7 +29,7 @@ #include <linux/mm.h> #include <linux/i8042.h> #include <linux/debugfs.h> -#include <linux/dell-led.h> +#include <linux/dell-common.h> #include <linux/seq_file.h> #include <acpi/video.h> #include "dell-rbtn.h" diff --git a/include/linux/dell-led.h b/include/linux/dell-common.h similarity index 61% rename from include/linux/dell-led.h rename to include/linux/dell-common.h index 92521471517f..37e4b614dd74 100644 --- a/include/linux/dell-led.h +++ b/include/linux/dell-common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DELL_LED_H__ -#define __DELL_LED_H__ +#ifndef __DELL_COMMON_H__ +#define __DELL_COMMON_H__ int dell_micmute_led_set(int on); diff --git a/sound/pci/hda/dell_wmi_helper.c b/sound/pci/hda/dell_wmi_helper.c index 1b48a8c19d28..56050cc3c0ee 100644 --- a/sound/pci/hda/dell_wmi_helper.c +++ b/sound/pci/hda/dell_wmi_helper.c @@ -4,7 +4,7 @@ */ #if IS_ENABLED(CONFIG_DELL_LAPTOP) -#include <linux/dell-led.h> +#include <linux/dell-common.h> enum { MICMUTE_LED_ON, -- 2.17.0

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[alsa-devel] [PATCH V2] ASoC: amd: dma driver changes for BT I2S controller instance
by Vijendar Mukunda 17 Apr '18

17 Apr '18

With in ACP, There are three I2S controllers can be configured/enabled ( I2S SP, I2S MICSP, I2S BT). Default enabled I2S controller instance is I2S SP. This patch provides required changes to support I2S BT controller Instance. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda(a)amd.com> Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> Reviewed-by: Alex Deucher <alexander.deucher(a)amd.com> v1->v2: fixed kbuild errors --- sound/soc/amd/acp-pcm-dma.c | 116 +++++++++++++++++++++++++++++++++++--------- sound/soc/amd/acp.h | 17 +++++++ 2 files changed, 111 insertions(+), 22 deletions(-) diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index 540088d..cad995e 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -697,6 +697,9 @@ static int acp_dma_open(struct snd_pcm_substream *substream) struct snd_soc_pcm_runtime *prtd = substream->private_data; struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME); struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); +#ifdef CONFIG_SND_DESIGNWARE_PCM + struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(prtd->cpu_dai); +#endif struct audio_substream_data *adata = kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); if (adata == NULL) @@ -710,7 +713,29 @@ static int acp_dma_open(struct snd_pcm_substream *substream) default: runtime->hw = acp_pcm_hardware_playback; } +#ifdef CONFIG_SND_DESIGNWARE_PCM + adata->i2s_play_instance = dev->i2s_instance; +#else + adata->i2s_play_instance = I2S_SP_INSTANCE; +#endif + if (adata->i2s_play_instance == I2S_SP_INSTANCE) + adata->i2ssp_renderbytescount = 0; + else if (adata->i2s_play_instance == I2S_BT_INSTANCE) + adata->i2sbt_renderbytescount = 0; + else + return -EINVAL; } else { +#ifdef CONFIG_SND_DESIGNWARE_PCM + adata->i2s_capture_instance = dev->i2s_instance; +#else + adata->i2s_capture_instance = I2S_SP_INSTANCE; +#endif + if (adata->i2s_capture_instance == I2S_SP_INSTANCE) + adata->i2ssp_capturebytescount = 0; + else if (adata->i2s_capture_instance == I2S_BT_INSTANCE) + adata->i2sbt_capturebytescount = 0; + else + return -EINVAL; switch (intr_data->asic_type) { case CHIP_STONEY: runtime->hw = acp_st_pcm_hardware_capture; @@ -736,11 +761,20 @@ static int acp_dma_open(struct snd_pcm_substream *substream) * This enablement is not required for another stream, if current * stream is not closed */ - if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream) + if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && + !intr_data->play_i2sbt_stream && + !intr_data->capture_i2sbt_stream) acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - intr_data->play_i2ssp_stream = substream; + switch (adata->i2s_play_instance) { + case I2S_BT_INSTANCE: + intr_data->play_i2sbt_stream = substream; + break; + case I2S_SP_INSTANCE: + default: + intr_data->play_i2ssp_stream = substream; + } /* For Stoney, Memory gating is disabled,i.e SRAM Banks * won't be turned off. The default state for SRAM banks is ON. * Setting SRAM bank state code skipped for STONEY platform. @@ -751,7 +785,14 @@ static int acp_dma_open(struct snd_pcm_substream *substream) bank, true); } } else { - intr_data->capture_i2ssp_stream = substream; + switch (adata->i2s_capture_instance) { + case I2S_BT_INSTANCE: + intr_data->capture_i2sbt_stream = substream; + break; + case I2S_SP_INSTANCE: + default: + intr_data->capture_i2ssp_stream = substream; + } if (intr_data->asic_type != CHIP_STONEY) { for (bank = 5; bank <= 8; bank++) acp_set_sram_bank_state(intr_data->acp_mmio, @@ -1010,34 +1051,49 @@ static int acp_dma_close(struct snd_pcm_substream *substream) struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME); struct audio_drv_data *adata = dev_get_drvdata(component->dev); - kfree(rtd); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - adata->play_i2ssp_stream = NULL; - /* For Stoney, Memory gating is disabled,i.e SRAM Banks - * won't be turned off. The default state for SRAM banks is ON. - * Setting SRAM bank state code skipped for STONEY platform. - * added condition checks for Carrizo platform only - */ - if (adata->asic_type != CHIP_STONEY) { - for (bank = 1; bank <= 4; bank++) - acp_set_sram_bank_state(adata->acp_mmio, bank, - false); + switch (rtd->i2s_play_instance) { + case I2S_BT_INSTANCE: + adata->play_i2sbt_stream = NULL; + break; + case I2S_SP_INSTANCE: + default: + adata->play_i2ssp_stream = NULL; + /* For Stoney, Memory gating is disabled,i.e SRAM Banks + * won't be turned off. The default state for SRAM banks + * is ON.Setting SRAM bank state code skipped for STONEY + * platform.Added condition checks for Carrizo platform + * only. + */ + if (adata->asic_type != CHIP_STONEY) { + for (bank = 1; bank <= 4; bank++) + acp_set_sram_bank_state(adata->acp_mmio, + bank, false); + } } } else { - adata->capture_i2ssp_stream = NULL; - if (adata->asic_type != CHIP_STONEY) { - for (bank = 5; bank <= 8; bank++) - acp_set_sram_bank_state(adata->acp_mmio, bank, - false); + switch (rtd->i2s_capture_instance) { + case I2S_BT_INSTANCE: + adata->capture_i2sbt_stream = NULL; + break; + case I2S_SP_INSTANCE: + default: + adata->capture_i2ssp_stream = NULL; + if (adata->asic_type != CHIP_STONEY) { + for (bank = 5; bank <= 8; bank++) + acp_set_sram_bank_state(adata->acp_mmio, + bank, false); + } } } /* Disable ACP irq, when the current stream is being closed and * another stream is also not active. - */ - if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream) + */ + if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && + !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); + kfree(rtd); return 0; } @@ -1089,6 +1145,8 @@ static int acp_audio_probe(struct platform_device *pdev) audio_drv_data->play_i2ssp_stream = NULL; audio_drv_data->capture_i2ssp_stream = NULL; + audio_drv_data->play_i2sbt_stream = NULL; + audio_drv_data->capture_i2sbt_stream = NULL; audio_drv_data->asic_type = *pdata; @@ -1177,6 +1235,20 @@ static int acp_pcm_resume(struct device *dev) adata->capture_i2ssp_stream->runtime->private_data, adata->asic_type); } + if (adata->asic_type != CHIP_CARRIZO) { + if (adata->play_i2sbt_stream && + adata->play_i2sbt_stream->runtime) { + config_acp_dma(adata->acp_mmio, + adata->play_i2sbt_stream->runtime->private_data, + adata->asic_type); + } + if (adata->capture_i2sbt_stream && + adata->capture_i2sbt_stream->runtime) { + config_acp_dma(adata->acp_mmio, + adata->capture_i2sbt_stream->runtime->private_data, + adata->asic_type); + } + } acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); return 0; } diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h index ba01510..7ad165b 100644 --- a/sound/soc/amd/acp.h +++ b/sound/soc/amd/acp.h @@ -4,6 +4,17 @@ #include "include/acp_2_2_d.h" #include "include/acp_2_2_sh_mask.h" +#ifdef CONFIG_SND_DESIGNWARE_PCM +#include "../dwc/local.h" +#endif + +#ifndef I2S_SP_INSTANCE +#define I2S_SP_INSTANCE 0x01 +#endif + +#ifndef I2S_BT_INSTANCE +#define I2S_BT_INSTANCE 0x02 +#endif #define ACP_PAGE_SIZE_4K_ENABLE 0x02 @@ -88,12 +99,18 @@ struct audio_substream_data { uint64_t size; u64 i2ssp_renderbytescount; u64 i2ssp_capturebytescount; + u64 i2sbt_renderbytescount; + u64 i2sbt_capturebytescount; void __iomem *acp_mmio; + u16 i2s_play_instance; + u16 i2s_capture_instance; }; struct audio_drv_data { struct snd_pcm_substream *play_i2ssp_stream; struct snd_pcm_substream *capture_i2ssp_stream; + struct snd_pcm_substream *play_i2sbt_stream; + struct snd_pcm_substream *capture_i2sbt_stream; void __iomem *acp_mmio; u32 asic_type; }; -- 2.7.4

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[alsa-devel] [PATCH 3/4] ASoC: amd: dma driver changes for BT I2S instance
by Vijendar Mukunda 17 Apr '18

17 Apr '18

With in ACP, There are three I2S controllers can be configured/enabled ( I2S SP, I2S MICSP, I2S BT). Default enabled I2S controller instance is I2S SP. This patch provides required changes to support I2S BT controller Instance. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda(a)amd.com> --- sound/soc/amd/Kconfig | 1 + sound/soc/amd/acp-pcm-dma.c | 388 +++++++++++++++++++++++++++----------------- sound/soc/amd/acp.h | 64 +++++++- 3 files changed, 295 insertions(+), 158 deletions(-) diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig index 6cbf9cf..6b7c620 100644 --- a/sound/soc/amd/Kconfig +++ b/sound/soc/amd/Kconfig @@ -1,5 +1,6 @@ config SND_SOC_AMD_ACP tristate "AMD Audio Coprocessor support" + select SND_DESIGNWARE_PCM help This option enables ACP DMA support on AMD platform. diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index 5ffe2ef..7c392fe 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -23,6 +23,8 @@ #include <drm/amd_asic_type.h> #include "acp.h" +#include "../dwc/local.h" + #define DRV_NAME "acp_audio_dma" #define PLAYBACK_MIN_NUM_PERIODS 2 @@ -37,13 +39,14 @@ #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) #define MIN_BUFFER MAX_BUFFER -#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192 +#define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) #define ST_MIN_BUFFER ST_MAX_BUFFER #define DRV_NAME "acp_audio_dma" + static const struct snd_pcm_hardware acp_pcm_hardware_playback = { .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | @@ -317,54 +320,21 @@ static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, } static void config_acp_dma(void __iomem *acp_mmio, - struct audio_substream_data *audio_config, + struct audio_substream_data *rtd, u32 asic_type) { - u32 pte_offset, sram_bank; - u16 ch1, ch2, destination, dma_dscr_idx; - - if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) { - pte_offset = ACP_PLAYBACK_PTE_OFFSET; - ch1 = SYSRAM_TO_ACP_CH_NUM; - ch2 = ACP_TO_I2S_DMA_CH_NUM; - sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS; - destination = TO_ACP_I2S_1; - - } else { - pte_offset = ACP_CAPTURE_PTE_OFFSET; - ch1 = SYSRAM_TO_ACP_CH_NUM; - ch2 = ACP_TO_I2S_DMA_CH_NUM; - switch (asic_type) { - case CHIP_STONEY: - sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS; - break; - default: - sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS; - } - destination = FROM_ACP_I2S_1; - } - - acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, - pte_offset); - if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) - dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; - else - dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14; - + acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages, + rtd->pte_offset); /* Configure System memory <-> ACP SRAM DMA descriptors */ - set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, - audio_config->direction, pte_offset, ch1, - sram_bank, dma_dscr_idx, asic_type); - - if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) - dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; - else - dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15; + set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, + rtd->direction, rtd->pte_offset, + rtd->ch1, rtd->sram_bank, + rtd->dma_dscr_idx_1, asic_type); /* Configure ACP SRAM <-> I2S DMA descriptors */ - set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, - audio_config->direction, sram_bank, - destination, ch2, dma_dscr_idx, - asic_type); + set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, + rtd->direction, rtd->sram_bank, + rtd->destination, rtd->ch2, + rtd->dma_dscr_idx_2, asic_type); } /* Start a given DMA channel transfer */ @@ -390,6 +360,9 @@ static void acp_dma_start(void __iomem *acp_mmio, case ACP_TO_I2S_DMA_CH_NUM: case ACP_TO_SYSRAM_CH_NUM: case I2S_TO_ACP_DMA_CH_NUM: + case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: + case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM: + case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; break; default: @@ -670,6 +643,24 @@ static irqreturn_t dma_irq_handler(int irq, void *arg) acp_mmio, mmACP_EXTERNAL_INTR_STAT); } + if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { + valid_irq = true; + if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_9) == + PLAYBACK_START_DMA_DESCR_CH9) + dscr_idx = PLAYBACK_END_DMA_DESCR_CH8; + else + dscr_idx = PLAYBACK_START_DMA_DESCR_CH8; + config_acp_dma_channel(acp_mmio, + SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM, + dscr_idx, 1, 0); + acp_dma_start(acp_mmio, SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM, + false); + snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); + acp_reg_write((intr_flag & + BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, + acp_mmio, mmACP_EXTERNAL_INTR_STAT); + } + if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { valid_irq = true; if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) == @@ -692,6 +683,31 @@ static irqreturn_t dma_irq_handler(int irq, void *arg) acp_mmio, mmACP_EXTERNAL_INTR_STAT); } + if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { + valid_irq = true; + if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_11) == + CAPTURE_START_DMA_DESCR_CH11) + dscr_idx = CAPTURE_END_DMA_DESCR_CH10; + else + dscr_idx = CAPTURE_START_DMA_DESCR_CH10; + config_acp_dma_channel(acp_mmio, + ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, + dscr_idx, 1, 0); + acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, + false); + acp_reg_write((intr_flag & + BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, + acp_mmio, mmACP_EXTERNAL_INTR_STAT); + } + + if ((intr_flag & BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) != 0) { + valid_irq = true; + snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); + acp_reg_write((intr_flag & + BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) << 16, + acp_mmio, mmACP_EXTERNAL_INTR_STAT); + } + if (valid_irq) return IRQ_HANDLED; else @@ -707,6 +723,7 @@ static int acp_dma_open(struct snd_pcm_substream *substream) struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME); struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); + struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(prtd->cpu_dai); struct audio_substream_data *adata = kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); if (!adata) @@ -720,6 +737,8 @@ static int acp_dma_open(struct snd_pcm_substream *substream) default: runtime->hw = acp_pcm_hardware_playback; } + adata->i2s_play_instance = dev->i2s_instance; + adata->bytescount = 0; } else { switch (intr_data->asic_type) { case CHIP_STONEY: @@ -728,6 +747,8 @@ static int acp_dma_open(struct snd_pcm_substream *substream) default: runtime->hw = acp_pcm_hardware_capture; } + adata->i2s_capture_instance = dev->i2s_instance; + adata->bytescount = 0; } ret = snd_pcm_hw_constraint_integer(runtime, @@ -747,11 +768,46 @@ static int acp_dma_open(struct snd_pcm_substream *substream) * This enablement is not required for another stream, if current * stream is not closed */ - if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream) + if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && + !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - intr_data->play_i2ssp_stream = substream; + switch (adata->i2s_play_instance) { + case I2S_BT_INSTANCE: + adata->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; + adata->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; + adata->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; + adata->sram_bank = ACP_SRAM_BANK_3_ADDRESS; + adata->destination = TO_BLUETOOTH; + adata->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; + adata->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; + adata->byte_cnt_high = + mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; + adata->byte_cnt_low = + mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; + intr_data->play_i2sbt_stream = substream; + break; + case I2S_SP_INSTANCE: + default: + switch (intr_data->asic_type) { + case CHIP_STONEY: + adata->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; + break; + default: + adata->pte_offset = ACP_PLAYBACK_PTE_OFFSET; + } + adata->ch1 = SYSRAM_TO_ACP_CH_NUM; + adata->ch2 = ACP_TO_I2S_DMA_CH_NUM; + adata->sram_bank = ACP_SRAM_BANK_1_ADDRESS; + adata->destination = TO_ACP_I2S_1; + adata->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; + adata->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; + adata->byte_cnt_high = mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; + adata->byte_cnt_low = mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; + intr_data->play_i2ssp_stream = substream; + break; + } /* * For Stoney, Memory gating is disabled,i.e SRAM Banks * won't be turned off. The default state for SRAM banks is ON. @@ -763,7 +819,40 @@ static int acp_dma_open(struct snd_pcm_substream *substream) bank, true); } } else { - intr_data->capture_i2ssp_stream = substream; + switch (adata->i2s_capture_instance) { + case I2S_BT_INSTANCE: + adata->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; + adata->ch1 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; + adata->ch2 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; + adata->sram_bank = ACP_SRAM_BANK_4_ADDRESS; + adata->destination = FROM_BLUETOOTH; + adata->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; + adata->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; + adata->byte_cnt_high = + mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; + adata->byte_cnt_low = + mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; + intr_data->capture_i2sbt_stream = substream; + break; + case I2S_SP_INSTANCE: + default: + adata->pte_offset = ACP_CAPTURE_PTE_OFFSET; + adata->ch1 = SYSRAM_TO_ACP_CH_NUM; + adata->ch2 = ACP_TO_I2S_DMA_CH_NUM; + switch (intr_data->asic_type) { + case CHIP_STONEY: + adata->sram_bank = ACP_SRAM_BANK_2_ADDRESS; + break; + default: + adata->sram_bank = ACP_SRAM_BANK_5_ADDRESS; + } + adata->destination = FROM_ACP_I2S_1; + adata->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; + adata->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; + adata->byte_cnt_high = mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; + adata->byte_cnt_low = mmACP_I2S_RECEIVED_BYTE_CNT_LOW; + intr_data->capture_i2ssp_stream = substream; + } if (intr_data->asic_type != CHIP_STONEY) { for (bank = 5; bank <= 8; bank++) acp_set_sram_bank_state(intr_data->acp_mmio, @@ -797,10 +886,25 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream, if (adata->asic_type == CHIP_STONEY) { val = acp_reg_read(adata->acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; - else - val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + switch (rtd->i2s_play_instance) { + case I2S_BT_INSTANCE: + val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; + break; + case I2S_SP_INSTANCE: + default: + val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; + } + } else { + switch (rtd->i2s_capture_instance) { + case I2S_BT_INSTANCE: + val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; + break; + case I2S_SP_INSTANCE: + default: + val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; + } + } acp_reg_write(val, adata->acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN); } @@ -837,26 +941,15 @@ static int acp_dma_hw_free(struct snd_pcm_substream *substream) return snd_pcm_lib_free_pages(substream); } -static u64 acp_get_byte_count(void __iomem *acp_mmio, int stream) +static u64 acp_get_byte_count(struct audio_substream_data *rtd) { - union acp_dma_count playback_dma_count; - union acp_dma_count capture_dma_count; - u64 bytescount = 0; + union acp_dma_count byte_count; - if (stream == SNDRV_PCM_STREAM_PLAYBACK) { - playback_dma_count.bcount.high = acp_reg_read(acp_mmio, - mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH); - playback_dma_count.bcount.low = acp_reg_read(acp_mmio, - mmACP_I2S_TRANSMIT_BYTE_CNT_LOW); - bytescount = playback_dma_count.bytescount; - } else { - capture_dma_count.bcount.high = acp_reg_read(acp_mmio, - mmACP_I2S_RECEIVED_BYTE_CNT_HIGH); - capture_dma_count.bcount.low = acp_reg_read(acp_mmio, - mmACP_I2S_RECEIVED_BYTE_CNT_LOW); - bytescount = capture_dma_count.bytescount; - } - return bytescount; + byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, + rtd->byte_cnt_high); + byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, + rtd->byte_cnt_low); + return byte_count.bytescount; } static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) @@ -872,15 +965,10 @@ static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) return -EINVAL; buffersize = frames_to_bytes(runtime, runtime->buffer_size); - bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream); + bytescount = acp_get_byte_count(rtd); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - if (bytescount > rtd->i2ssp_renderbytescount) - bytescount = bytescount - rtd->i2ssp_renderbytescount; - } else { - if (bytescount > rtd->i2ssp_capturebytescount) - bytescount = bytescount - rtd->i2ssp_capturebytescount; - } + if (bytescount > rtd->bytescount) + bytescount = bytescount - rtd->bytescount; pos = do_div(bytescount, buffersize); return bytes_to_frames(runtime, pos); } @@ -898,21 +986,14 @@ static int acp_dma_prepare(struct snd_pcm_substream *substream) if (!rtd) return -EINVAL; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, - PLAYBACK_START_DMA_DESCR_CH12, - NUM_DSCRS_PER_CHANNEL, 0); - config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM, - PLAYBACK_START_DMA_DESCR_CH13, - NUM_DSCRS_PER_CHANNEL, 0); - } else { - config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM, - CAPTURE_START_DMA_DESCR_CH14, - NUM_DSCRS_PER_CHANNEL, 0); - config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM, - CAPTURE_START_DMA_DESCR_CH15, - NUM_DSCRS_PER_CHANNEL, 0); - } + config_acp_dma_channel(rtd->acp_mmio, + rtd->ch1, + rtd->dma_dscr_idx_1, + NUM_DSCRS_PER_CHANNEL, 0); + config_acp_dma_channel(rtd->acp_mmio, + rtd->ch2, + rtd->dma_dscr_idx_2, + NUM_DSCRS_PER_CHANNEL, 0); return 0; } @@ -934,15 +1015,13 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: case SNDRV_PCM_TRIGGER_RESUME: - bytescount = acp_get_byte_count(rtd->acp_mmio, - substream->stream); + bytescount = acp_get_byte_count(rtd); + if (rtd->bytescount == 0) + rtd->bytescount = bytescount; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - if (rtd->i2ssp_renderbytescount == 0) - rtd->i2ssp_renderbytescount = bytescount; - acp_dma_start(rtd->acp_mmio, - SYSRAM_TO_ACP_CH_NUM, false); + acp_dma_start(rtd->acp_mmio, rtd->ch1, false); while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) & - BIT(SYSRAM_TO_ACP_CH_NUM)) { + BIT(rtd->ch1)) { if (!loops--) { dev_err(component->dev, "acp dma start timeout\n"); @@ -950,40 +1029,21 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) } cpu_relax(); } - - acp_dma_start(rtd->acp_mmio, - ACP_TO_I2S_DMA_CH_NUM, true); - - } else { - if (rtd->i2ssp_capturebytescount == 0) - rtd->i2ssp_capturebytescount = bytescount; - acp_dma_start(rtd->acp_mmio, - I2S_TO_ACP_DMA_CH_NUM, true); } + acp_dma_start(rtd->acp_mmio, rtd->ch2, true); ret = 0; break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: case SNDRV_PCM_TRIGGER_SUSPEND: - /* - * Need to stop only circular DMA channels : - * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular - * channels will stopped automatically after its transfer - * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM - */ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - ret = acp_dma_stop(rtd->acp_mmio, - SYSRAM_TO_ACP_CH_NUM); - ret = acp_dma_stop(rtd->acp_mmio, - ACP_TO_I2S_DMA_CH_NUM); - rtd->i2ssp_renderbytescount = 0; + acp_dma_stop(rtd->acp_mmio, rtd->ch1); + ret = acp_dma_stop(rtd->acp_mmio, rtd->ch2); } else { - ret = acp_dma_stop(rtd->acp_mmio, - I2S_TO_ACP_DMA_CH_NUM); - ret = acp_dma_stop(rtd->acp_mmio, - ACP_TO_SYSRAM_CH_NUM); - rtd->i2ssp_capturebytescount = 0; + acp_dma_stop(rtd->acp_mmio, rtd->ch2); + ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); } + rtd->bytescount = 0; break; default: ret = -EINVAL; @@ -1028,27 +1088,40 @@ static int acp_dma_close(struct snd_pcm_substream *substream) DRV_NAME); struct audio_drv_data *adata = dev_get_drvdata(component->dev); - kfree(rtd); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - adata->play_i2ssp_stream = NULL; - /* - * For Stoney, Memory gating is disabled,i.e SRAM Banks - * won't be turned off. The default state for SRAM banks is ON. - * Setting SRAM bank state code skipped for STONEY platform. - * added condition checks for Carrizo platform only - */ - if (adata->asic_type != CHIP_STONEY) { - for (bank = 1; bank <= 4; bank++) - acp_set_sram_bank_state(adata->acp_mmio, bank, - false); + switch (rtd->i2s_play_instance) { + case I2S_BT_INSTANCE: + adata->play_i2sbt_stream = NULL; + break; + case I2S_SP_INSTANCE: + default: + adata->play_i2ssp_stream = NULL; + /* + * For Stoney, Memory gating is disabled,i.e SRAM Banks + * won't be turned off. The default state for SRAM banks + * is ON.Setting SRAM bank state code skipped for STONEY + * platform. Added condition checks for Carrizo platform + * only. + */ + if (adata->asic_type != CHIP_STONEY) { + for (bank = 1; bank <= 4; bank++) + acp_set_sram_bank_state(adata->acp_mmio, + bank, false); + } } } else { - adata->capture_i2ssp_stream = NULL; - if (adata->asic_type != CHIP_STONEY) { - for (bank = 5; bank <= 8; bank++) - acp_set_sram_bank_state(adata->acp_mmio, bank, - false); + switch (rtd->i2s_capture_instance) { + case I2S_BT_INSTANCE: + adata->capture_i2sbt_stream = NULL; + break; + case I2S_SP_INSTANCE: + default: + adata->capture_i2ssp_stream = NULL; + if (adata->asic_type != CHIP_STONEY) { + for (bank = 5; bank <= 8; bank++) + acp_set_sram_bank_state(adata->acp_mmio, + bank, false); + } } } @@ -1056,8 +1129,10 @@ static int acp_dma_close(struct snd_pcm_substream *substream) * Disable ACP irq, when the current stream is being closed and * another stream is also not active. */ - if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream) + if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && + !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); + kfree(rtd); return 0; } @@ -1110,6 +1185,8 @@ static int acp_audio_probe(struct platform_device *pdev) audio_drv_data->play_i2ssp_stream = NULL; audio_drv_data->capture_i2ssp_stream = NULL; + audio_drv_data->play_i2sbt_stream = NULL; + audio_drv_data->capture_i2sbt_stream = NULL; audio_drv_data->asic_type = *pdata; @@ -1166,6 +1243,7 @@ static int acp_pcm_resume(struct device *dev) { u16 bank; int status; + struct audio_substream_data *rtd; struct audio_drv_data *adata = dev_get_drvdata(dev); status = acp_init(adata->acp_mmio, adata->asic_type); @@ -1185,9 +1263,8 @@ static int acp_pcm_resume(struct device *dev) acp_set_sram_bank_state(adata->acp_mmio, bank, true); } - config_acp_dma(adata->acp_mmio, - adata->play_i2ssp_stream->runtime->private_data, - adata->asic_type); + rtd = adata->play_i2ssp_stream->runtime->private_data; + config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); } if (adata->capture_i2ssp_stream && adata->capture_i2ssp_stream->runtime) { @@ -1196,9 +1273,20 @@ static int acp_pcm_resume(struct device *dev) acp_set_sram_bank_state(adata->acp_mmio, bank, true); } - config_acp_dma(adata->acp_mmio, - adata->capture_i2ssp_stream->runtime->private_data, - adata->asic_type); + rtd = adata->capture_i2ssp_stream->runtime->private_data; + config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); + } + if (adata->asic_type != CHIP_CARRIZO) { + if (adata->play_i2sbt_stream && + adata->play_i2sbt_stream->runtime) { + rtd = adata->play_i2sbt_stream->runtime->private_data; + config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); + } + if (adata->capture_i2sbt_stream && + adata->capture_i2sbt_stream->runtime) { + rtd = adata->capture_i2sbt_stream->runtime->private_data; + config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); + } } acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); return 0; diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h index 0e6089b..460365c 100644 --- a/sound/soc/amd/acp.h +++ b/sound/soc/amd/acp.h @@ -10,17 +10,30 @@ #define ACP_PLAYBACK_PTE_OFFSET 10 #define ACP_CAPTURE_PTE_OFFSET 0 +/* Playback and Capture Offset for Stoney */ +#define ACP_ST_PLAYBACK_PTE_OFFSET 0x04 +#define ACP_ST_CAPTURE_PTE_OFFSET 0x00 +#define ACP_ST_BT_PLAYBACK_PTE_OFFSET 0x08 +#define ACP_ST_BT_CAPTURE_PTE_OFFSET 0x0c + #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4 #define ACP_ONION_CNTL_DEFAULT 0x00000FB4 #define ACP_PHYSICAL_BASE 0x14000 -/* Playback SRAM address (as a destination in dma descriptor) */ -#define ACP_SHARED_RAM_BANK_1_ADDRESS 0x4002000 - -/* Capture SRAM address (as a source in dma descriptor) */ -#define ACP_SHARED_RAM_BANK_5_ADDRESS 0x400A000 -#define ACP_SHARED_RAM_BANK_3_ADDRESS 0x4006000 +/* + * In case of I2S SP controller instance, Stoney uses SRAM bank 1 for + * playback and SRAM Bank 2 for capture where as in case of BT I2S + * Instance, Stoney uses SRAM Bank 3 for playback & SRAM Bank 4 will + * be used for capture. Carrizo uses I2S SP controller instance. SRAM Banks + * 1, 2, 3, 4 will be used for playback & SRAM Banks 5, 6, 7, 8 will be used + * for capture scenario. + */ +#define ACP_SRAM_BANK_1_ADDRESS 0x4002000 +#define ACP_SRAM_BANK_2_ADDRESS 0x4004000 +#define ACP_SRAM_BANK_3_ADDRESS 0x4006000 +#define ACP_SRAM_BANK_4_ADDRESS 0x4008000 +#define ACP_SRAM_BANK_5_ADDRESS 0x400A000 #define ACP_DMA_RESET_TIME 10000 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF @@ -35,8 +48,10 @@ #define TO_ACP_I2S_1 0x2 #define TO_ACP_I2S_2 0x4 +#define TO_BLUETOOTH 0x3 #define FROM_ACP_I2S_1 0xa #define FROM_ACP_I2S_2 0xb +#define FROM_BLUETOOTH 0xb #define ACP_TILE_ON_MASK 0x03 #define ACP_TILE_OFF_MASK 0x02 @@ -57,6 +72,14 @@ #define ACP_TO_SYSRAM_CH_NUM 14 #define I2S_TO_ACP_DMA_CH_NUM 15 +/* Playback DMA Channels for I2S BT instance */ +#define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM 8 +#define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM 9 + +/* Capture DMA Channels for I2S BT Instance */ +#define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 10 +#define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 11 + #define NUM_DSCRS_PER_CHANNEL 2 #define PLAYBACK_START_DMA_DESCR_CH12 0 @@ -69,9 +92,22 @@ #define CAPTURE_START_DMA_DESCR_CH15 6 #define CAPTURE_END_DMA_DESCR_CH15 7 +/* I2S BT Instance DMA Descriptors */ +#define PLAYBACK_START_DMA_DESCR_CH8 8 +#define PLAYBACK_END_DMA_DESCR_CH8 9 +#define PLAYBACK_START_DMA_DESCR_CH9 10 +#define PLAYBACK_END_DMA_DESCR_CH9 11 + +#define CAPTURE_START_DMA_DESCR_CH10 12 +#define CAPTURE_END_DMA_DESCR_CH10 13 +#define CAPTURE_START_DMA_DESCR_CH11 14 +#define CAPTURE_END_DMA_DESCR_CH11 15 + #define mmACP_I2S_16BIT_RESOLUTION_EN 0x5209 #define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01 #define ACP_I2S_SP_16BIT_RESOLUTION_EN 0x02 +#define ACP_I2S_BT_16BIT_RESOLUTION_EN 0x04 + enum acp_dma_priority_level { /* 0x0 Specifies the DMA channel is given normal priority */ ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0, @@ -84,16 +120,28 @@ struct audio_substream_data { struct page *pg; unsigned int order; u16 num_of_pages; + u16 i2s_play_instance; + u16 i2s_capture_instance; u16 direction; + u16 ch1; + u16 ch2; + u16 destination; + u16 dma_dscr_idx_1; + u16 dma_dscr_idx_2; + u32 pte_offset; + u32 sram_bank; + u32 byte_cnt_high; + u32 byte_cnt_low; uint64_t size; - u64 i2ssp_renderbytescount; - u64 i2ssp_capturebytescount; + u64 bytescount; void __iomem *acp_mmio; }; struct audio_drv_data { struct snd_pcm_substream *play_i2ssp_stream; struct snd_pcm_substream *capture_i2ssp_stream; + struct snd_pcm_substream *play_i2sbt_stream; + struct snd_pcm_substream *capture_i2sbt_stream; void __iomem *acp_mmio; u32 asic_type; }; -- 2.7.4

1 0

[alsa-devel] alsa-lib: add-on configs directory changed to /etc/alsa/conf.d
by Jaroslav Kysela 17 Apr '18

17 Apr '18

Hi, I pushed two commits to the alsa-lib package which changes the default location for the add-on config files to /etc/alsa/conf.d from /usr/share/alsa/alsa.conf.d . The reason is to follow the scheme like in other packages. Also, the users might want to change or disable contents in those 'default' files. Example paths from other packages: # find /etc -type d -name conf.d /etc/fonts/conf.d /etc/NetworkManager/conf.d /etc/libblockdev/conf.d /etc/sssd/conf.d /etc/httpd/conf.d Commmits: http://git.alsa-project.org/?p=alsa-lib.git;a=commit;h=93e03bdc2a3dcd5d1251… http://git.alsa-project.org/?p=alsa-lib.git;a=commit;h=78505dccd23546cc77e5… Jaroslav -- Jaroslav Kysela <perex(a)perex.cz> Linux Sound Maintainer; ALSA Project; Red Hat, Inc.

2 5

[alsa-devel] [asoc:for-4.18 35/37] sound/soc/codecs/rt1305.c:1068:15: sparse: constant 562949953421312 is so big it is long
by kbuild test robot 16 Apr '18

16 Apr '18

tree: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-4.18 head: fbeabd09236664f34ea3e4a9f7dcf5a0cdb7fc47 commit: 29bc643ddd7efb741d07c8b2d9a4c3dd9228865b [35/37] ASoC: rt1305: Add RT1305/RT1306 amplifier driver reproduce: # apt-get install sparse git checkout 29bc643ddd7efb741d07c8b2d9a4c3dd9228865b make ARCH=x86_64 allmodconfig make C=1 CF=-D__CHECK_ENDIAN__ sparse warnings: (new ones prefixed by >>) >> sound/soc/codecs/rt1305.c:1068:15: sparse: constant 562949953421312 is so big it is long sound/soc/codecs/rt1305.c:1085:15: sparse: constant 562949953421312 is so big it is long sound/soc/codecs/rt1305.c:1179:37: sparse: undefined identifier 'ACPI_PTR' sound/soc/codecs/rt1305.c:1179:23: error: implicit declaration of function 'ACPI_PTR'; did you mean 'ERR_PTR'? [-Werror=implicit-function-declaration] .acpi_match_table = ACPI_PTR(rt1305_acpi_match) ^~~~~~~~ ERR_PTR sound/soc/codecs/rt1305.c:1179:23: warning: initialization makes pointer from integer without a cast [-Wint-conversion] sound/soc/codecs/rt1305.c:1179:23: note: (near initialization for 'rt1305_i2c_driver.driver.acpi_match_table') sound/soc/codecs/rt1305.c:1179:23: error: initializer element is not constant sound/soc/codecs/rt1305.c:1179:23: note: (near initialization for 'rt1305_i2c_driver.driver.acpi_match_table') cc1: some warnings being treated as errors vim +1068 sound/soc/codecs/rt1305.c 992 993 static void rt1305_calibrate(struct rt1305_priv *rt1305) 994 { 995 unsigned int valmsb, vallsb, offsetl, offsetr; 996 unsigned int rh, rl, rhl, r0ohm; 997 u64 r0l, r0r; 998 999 regcache_cache_bypass(rt1305->regmap, true); 1000 1001 rt1305_reset(rt1305->regmap); 1002 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219); 1003 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548); 1004 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); 1005 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000); 1006 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600); 1007 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0); 1008 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); 1009 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); 1010 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); 1011 1012 /* Sin Gen */ 1013 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); 1014 1015 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000); 1016 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0); 1017 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc); 1018 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); 1019 regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000); 1020 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); 1021 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); 1022 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0); 1023 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); 1024 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); 1025 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); 1026 1027 /* EFUSE read */ 1028 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); 1029 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); 1030 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); 1031 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); 1032 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); 1033 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); 1034 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000); 1035 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000); 1036 1037 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb); 1038 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb); 1039 offsetl = valmsb << 16 | vallsb; 1040 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb); 1041 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb); 1042 offsetr = valmsb << 16 | vallsb; 1043 pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr); 1044 1045 /* R0 calibration */ 1046 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542); 1047 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); 1048 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); 1049 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe); 1050 regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13); 1051 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650); 1052 1053 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064); 1054 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770); 1055 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c); 1056 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200); 1057 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); 1058 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); 1059 msleep(2000); 1060 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); 1061 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); 1062 rhl = (rh << 16) | rl; 1063 r0ohm = (rhl*10) / 33554432; 1064 1065 pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl); 1066 pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10)); 1067 > 1068 r0l = 562949953421312; 1069 if (rhl != 0) 1070 do_div(r0l, rhl); 1071 pr_debug("Left_r0 = 0x%llx\n", r0l); 1072 1073 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200); 1074 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); 1075 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); 1076 msleep(2000); 1077 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); 1078 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); 1079 rhl = (rh << 16) | rl; 1080 r0ohm = (rhl*10) / 33554432; 1081 1082 pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl); 1083 pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10)); 1084 1085 r0r = 562949953421312; 1086 if (rhl != 0) 1087 do_div(r0r, rhl); 1088 pr_debug("Right_r0 = 0x%llx\n", r0r); 1089 1090 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec); 1091 1092 if ((r0l > R0_UPPER) && (r0l < R0_LOWER) && 1093 (r0r > R0_UPPER) && (r0r < R0_LOWER)) { 1094 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e, 1095 (r0l >> 16) & 0xffff); 1096 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f, 1097 r0l & 0xffff); 1098 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe, 1099 ((r0r >> 16) & 0xffff) | 0xf800); 1100 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd, 1101 r0r & 0xffff); 1102 } else { 1103 pr_err("R0 calibration failed\n"); 1104 } 1105 1106 /* restore some registers */ 1107 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); 1108 usleep_range(200000, 400000); 1109 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); 1110 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000); 1111 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400); 1112 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000); 1113 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000); 1114 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020); 1115 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000); 1116 1117 regcache_cache_bypass(rt1305->regmap, false); 1118 } 1119 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[alsa-devel] [PATCH v4 0/3] ASoC: topology: Improve hw_configs
by Kirill Marinushkin 16 Apr '18

16 Apr '18

Hello Mark, This patch series waits since 20th of February, because it modifies UAPI headers and should be done in sync with ALSA. I see that previously there was no clear understanding, how to do this in sync. Two days ago I discussed with Takashi, and he suggested the following steps: Step 1. A person from Intel, who knows the topic (Pierre), adds his "Reviewed-by" or "Acked-by" tags Step 2. I clarify with you to apply the Linux part (this patch series) Step 3. After that, I clarify with Takashi to apply the ALSA part (it is ready, but not sent untill we apply the Linux part) The step 1 is done. Old patches are reviewed by Pierre, so they have his "Reviewed-by" tag. New patches are suggested by him, and we agreed on the implementation, so they have his "Acked-by" tag. Now we are on the step 2. If you don't have anything against this patch series, please apply it to Linux. Best Regards, Kirill Kirill Marinushkin (3): ASoC: topology: Fix bclk and fsync inversion in set_link_hw_format() ASoC: topology: Add missing clock gating parameter when parsing hw_configs ASoC: topology: Add definitions for mclk_direction values include/uapi/sound/asoc.h | 29 +++++++++++++++++++++++++---- sound/soc/soc-topology.c | 19 ++++++++++++++----- 2 files changed, 39 insertions(+), 9 deletions(-) -- 2.13.6

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[alsa-devel] [PATCH] [PATCH] ASoC: rt1305: Add RT1305/RT1306 amplifier driver
by shumingf＠realtek.com 16 Apr '18

16 Apr '18

From: Shuming Fan <shumingf(a)realtek.com> This is the initial amplifier driver for rt1305/rt1306. Signed-off-by: Shuming Fan <shumingf(a)realtek.com> --- sound/soc/codecs/Kconfig | 6 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt1305.c | 1191 +++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/rt1305.h | 276 +++++++++++ 4 files changed, 1475 insertions(+) create mode 100644 sound/soc/codecs/rt1305.c create mode 100644 sound/soc/codecs/rt1305.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 9548f63..665edb5 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -126,6 +126,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_RT274 if I2C select SND_SOC_RT286 if I2C select SND_SOC_RT298 if I2C + select SND_SOC_RT1305 if I2C select SND_SOC_RT5514 if I2C select SND_SOC_RT5616 if I2C select SND_SOC_RT5631 if I2C @@ -772,6 +773,7 @@ config SND_SOC_RL6231 default y if SND_SOC_RT5665=y default y if SND_SOC_RT5670=y default y if SND_SOC_RT5677=y + default y if SND_SOC_RT1305=y default m if SND_SOC_RT5514=m default m if SND_SOC_RT5616=m default m if SND_SOC_RT5640=m @@ -783,6 +785,7 @@ config SND_SOC_RL6231 default m if SND_SOC_RT5665=m default m if SND_SOC_RT5670=m default m if SND_SOC_RT5677=m + default m if SND_SOC_RT1305=m config SND_SOC_RL6347A tristate @@ -805,6 +808,9 @@ config SND_SOC_RT298 tristate depends on I2C +config SND_SOC_RT1305 + tristate + config SND_SOC_RT5514 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index e849d14..cccd774 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -126,6 +126,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o snd-soc-pcm512x-spi-objs := pcm512x-spi.o snd-soc-rl6231-objs := rl6231.o snd-soc-rl6347a-objs := rl6347a.o +snd-soc-rt1305-objs := rt1305.o snd-soc-rt274-objs := rt274.o snd-soc-rt286-objs := rt286.o snd-soc-rt298-objs := rt298.o @@ -379,6 +380,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o +obj-$(CONFIG_SND_SOC_RT1305) += snd-soc-rt1305.o obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o diff --git a/sound/soc/codecs/rt1305.c b/sound/soc/codecs/rt1305.c new file mode 100644 index 0000000..90baab9 --- /dev/null +++ b/sound/soc/codecs/rt1305.c @@ -0,0 +1,1191 @@ +/* + * rt1305.c -- RT1305 ALSA SoC amplifier component driver + * + * Copyright 2018 Realtek Semiconductor Corp. + * Author: Shuming Fan <shumingf(a)realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/firmware.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#include "rl6231.h" +#include "rt1305.h" + + +#define RT1305_PR_RANGE_BASE (0xff + 1) +#define RT1305_PR_SPACING 0x100 + +#define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING)) + + +static const struct regmap_range_cfg rt1305_ranges[] = { + { + .name = "PR", + .range_min = RT1305_PR_BASE, + .range_max = RT1305_PR_BASE + 0xff, + .selector_reg = RT1305_PRIV_INDEX, + .selector_mask = 0xff, + .selector_shift = 0x0, + .window_start = RT1305_PRIV_DATA, + .window_len = 0x1, + }, +}; + + +static const struct reg_sequence init_list[] = { + + { RT1305_PR_BASE + 0xcf, 0x5548 }, + { RT1305_PR_BASE + 0x5d, 0x0442 }, + { RT1305_PR_BASE + 0xc1, 0x0320 }, + + { RT1305_POWER_STATUS, 0x0000 }, + + { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de }, + { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 }, + { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 }, + + { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */ + { RT1305_ADC_SET_3, 0x0219 }, + { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/ + +}; +#define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list) + +struct rt1305_priv { + struct snd_soc_component *component; + struct regmap *regmap; + + int sysclk; + int sysclk_src; + int lrck; + int bclk; + int master; + + int pll_src; + int pll_in; + int pll_out; +}; + +static const struct reg_default rt1305_reg[] = { + + { 0x04, 0x0400 }, + { 0x05, 0x0880 }, + { 0x06, 0x0000 }, + { 0x07, 0x3100 }, + { 0x08, 0x8000 }, + { 0x09, 0x0000 }, + { 0x0a, 0x087e }, + { 0x0b, 0x0020 }, + { 0x0c, 0x0802 }, + { 0x0d, 0x0020 }, + { 0x10, 0x1d1d }, + { 0x11, 0x1d1d }, + { 0x12, 0xffff }, + { 0x14, 0x000c }, + { 0x16, 0x1717 }, + { 0x17, 0x4000 }, + { 0x18, 0x0019 }, + { 0x20, 0x0000 }, + { 0x22, 0x0000 }, + { 0x24, 0x0000 }, + { 0x26, 0x0000 }, + { 0x28, 0x0000 }, + { 0x2a, 0x4000 }, + { 0x2b, 0x3000 }, + { 0x2d, 0x6000 }, + { 0x2e, 0x0000 }, + { 0x2f, 0x8000 }, + { 0x32, 0x0000 }, + { 0x39, 0x0001 }, + { 0x3a, 0x0000 }, + { 0x3b, 0x1020 }, + { 0x3c, 0x0000 }, + { 0x3d, 0x0000 }, + { 0x3e, 0x4c00 }, + { 0x3f, 0x3000 }, + { 0x40, 0x000c }, + { 0x42, 0x0400 }, + { 0x46, 0xc22c }, + { 0x47, 0x0000 }, + { 0x4b, 0x0000 }, + { 0x4c, 0x0300 }, + { 0x4f, 0xf000 }, + { 0x50, 0xc200 }, + { 0x51, 0x1f1f }, + { 0x52, 0x01f0 }, + { 0x53, 0x407f }, + { 0x54, 0xffff }, + { 0x58, 0x4005 }, + { 0x5e, 0x0000 }, + { 0x5f, 0x0000 }, + { 0x60, 0xee13 }, + { 0x62, 0x0000 }, + { 0x63, 0x5f5f }, + { 0x64, 0x0040 }, + { 0x65, 0x4000 }, + { 0x66, 0x4004 }, + { 0x67, 0x0306 }, + { 0x68, 0x8c04 }, + { 0x69, 0xe021 }, + { 0x6a, 0x0000 }, + { 0x6c, 0xaaaa }, + { 0x70, 0x0333 }, + { 0x71, 0x3330 }, + { 0x72, 0x3333 }, + { 0x73, 0x3300 }, + { 0x74, 0x0000 }, + { 0x75, 0x0000 }, + { 0x76, 0x0000 }, + { 0x7a, 0x0003 }, + { 0x7c, 0x10ec }, + { 0x7e, 0x6251 }, + { 0x80, 0x0800 }, + { 0x81, 0x4000 }, + { 0x82, 0x0000 }, + { 0x90, 0x7a01 }, + { 0x91, 0x8431 }, + { 0x92, 0x0180 }, + { 0x93, 0x0000 }, + { 0x94, 0x0000 }, + { 0x95, 0x0000 }, + { 0x96, 0x0000 }, + { 0x97, 0x0000 }, + { 0x98, 0x0000 }, + { 0x99, 0x0000 }, + { 0x9a, 0x0000 }, + { 0x9b, 0x0000 }, + { 0x9c, 0x0000 }, + { 0x9d, 0x0000 }, + { 0x9e, 0x0000 }, + { 0x9f, 0x0000 }, + { 0xa0, 0x0000 }, + { 0xb0, 0x8200 }, + { 0xb1, 0x00ff }, + { 0xb2, 0x0008 }, + { 0xc0, 0x0200 }, + { 0xc1, 0x0000 }, + { 0xc2, 0x0000 }, + { 0xc3, 0x0000 }, + { 0xc4, 0x0000 }, + { 0xc5, 0x0000 }, + { 0xc6, 0x0000 }, + { 0xc7, 0x0000 }, + { 0xc8, 0x0000 }, + { 0xc9, 0x0000 }, + { 0xca, 0x0200 }, + { 0xcb, 0x0000 }, + { 0xcc, 0x0000 }, + { 0xcd, 0x0000 }, + { 0xce, 0x0000 }, + { 0xcf, 0x0000 }, + { 0xd0, 0x0000 }, + { 0xd1, 0x0000 }, + { 0xd2, 0x0000 }, + { 0xd3, 0x0000 }, + { 0xd4, 0x0200 }, + { 0xd5, 0x0000 }, + { 0xd6, 0x0000 }, + { 0xd7, 0x0000 }, + { 0xd8, 0x0000 }, + { 0xd9, 0x0000 }, + { 0xda, 0x0000 }, + { 0xdb, 0x0000 }, + { 0xdc, 0x0000 }, + { 0xdd, 0x0000 }, + { 0xde, 0x0200 }, + { 0xdf, 0x0000 }, + { 0xe0, 0x0000 }, + { 0xe1, 0x0000 }, + { 0xe2, 0x0000 }, + { 0xe3, 0x0000 }, + { 0xe4, 0x0000 }, + { 0xe5, 0x0000 }, + { 0xe6, 0x0000 }, + { 0xe7, 0x0000 }, + { 0xe8, 0x0200 }, + { 0xe9, 0x0000 }, + { 0xea, 0x0000 }, + { 0xeb, 0x0000 }, + { 0xec, 0x0000 }, + { 0xed, 0x0000 }, + { 0xee, 0x0000 }, + { 0xef, 0x0000 }, + { 0xf0, 0x0000 }, + { 0xf1, 0x0000 }, + { 0xf2, 0x0200 }, + { 0xf3, 0x0000 }, + { 0xf4, 0x0000 }, + { 0xf5, 0x0000 }, + { 0xf6, 0x0000 }, + { 0xf7, 0x0000 }, + { 0xf8, 0x0000 }, + { 0xf9, 0x0000 }, + { 0xfa, 0x0000 }, + { 0xfb, 0x0000 }, +}; + +static int rt1305_reg_init(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN); + return 0; +} + +static bool rt1305_volatile_register(struct device *dev, unsigned int reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) { + if (reg >= rt1305_ranges[i].range_min && + reg <= rt1305_ranges[i].range_max) { + return true; + } + } + + switch (reg) { + case RT1305_RESET: + case RT1305_SPDIF_IN_SET_1: + case RT1305_SPDIF_IN_SET_2: + case RT1305_SPDIF_IN_SET_3: + case RT1305_POWER_CTRL_2: + case RT1305_CLOCK_DETECT: + case RT1305_BIQUAD_SET_1: + case RT1305_BIQUAD_SET_2: + case RT1305_EQ_SET_2: + case RT1305_SPK_TEMP_PROTECTION_0: + case RT1305_SPK_TEMP_PROTECTION_2: + case RT1305_SPK_DC_DETECT_1: + case RT1305_SILENCE_DETECT: + case RT1305_VERSION_ID: + case RT1305_VENDOR_ID: + case RT1305_DEVICE_ID: + case RT1305_EFUSE_1: + case RT1305_EFUSE_3: + case RT1305_DC_CALIB_1: + case RT1305_DC_CALIB_3: + case RT1305_DAC_OFFSET_1: + case RT1305_DAC_OFFSET_2: + case RT1305_DAC_OFFSET_3: + case RT1305_DAC_OFFSET_4: + case RT1305_DAC_OFFSET_5: + case RT1305_DAC_OFFSET_6: + case RT1305_DAC_OFFSET_7: + case RT1305_DAC_OFFSET_8: + case RT1305_DAC_OFFSET_9: + case RT1305_DAC_OFFSET_10: + case RT1305_DAC_OFFSET_11: + case RT1305_TRIM_1: + case RT1305_TRIM_2: + return true; + + default: + return false; + } +} + +static bool rt1305_readable_register(struct device *dev, unsigned int reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) { + if (reg >= rt1305_ranges[i].range_min && + reg <= rt1305_ranges[i].range_max) { + return true; + } + } + + switch (reg) { + case RT1305_RESET: + case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK: + case RT1305_PLL0_1 ... RT1305_PLL1_2: + case RT1305_MIXER_CTRL_1: + case RT1305_MIXER_CTRL_2: + case RT1305_DAC_SET_1: + case RT1305_DAC_SET_2: + case RT1305_ADC_SET_1: + case RT1305_ADC_SET_2: + case RT1305_ADC_SET_3: + case RT1305_PATH_SET: + case RT1305_SPDIF_IN_SET_1: + case RT1305_SPDIF_IN_SET_2: + case RT1305_SPDIF_IN_SET_3: + case RT1305_SPDIF_OUT_SET_1: + case RT1305_SPDIF_OUT_SET_2: + case RT1305_SPDIF_OUT_SET_3: + case RT1305_I2S_SET_1: + case RT1305_I2S_SET_2: + case RT1305_PBTL_MONO_MODE_SRC: + case RT1305_MANUALLY_I2C_DEVICE: + case RT1305_POWER_STATUS: + case RT1305_POWER_CTRL_1: + case RT1305_POWER_CTRL_2: + case RT1305_POWER_CTRL_3: + case RT1305_POWER_CTRL_4: + case RT1305_POWER_CTRL_5: + case RT1305_CLOCK_DETECT: + case RT1305_BIQUAD_SET_1: + case RT1305_BIQUAD_SET_2: + case RT1305_ADJUSTED_HPF_1: + case RT1305_ADJUSTED_HPF_2: + case RT1305_EQ_SET_1: + case RT1305_EQ_SET_2: + case RT1305_SPK_TEMP_PROTECTION_0: + case RT1305_SPK_TEMP_PROTECTION_1: + case RT1305_SPK_TEMP_PROTECTION_2: + case RT1305_SPK_TEMP_PROTECTION_3: + case RT1305_SPK_DC_DETECT_1: + case RT1305_SPK_DC_DETECT_2: + case RT1305_LOUDNESS: + case RT1305_THERMAL_FOLD_BACK_1: + case RT1305_THERMAL_FOLD_BACK_2: + case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7: + case RT1305_VERSION_ID: + case RT1305_VENDOR_ID: + case RT1305_DEVICE_ID: + case RT1305_EFUSE_1: + case RT1305_EFUSE_2: + case RT1305_EFUSE_3: + case RT1305_DC_CALIB_1: + case RT1305_DC_CALIB_2: + case RT1305_DC_CALIB_3: + case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14: + case RT1305_TRIM_1: + case RT1305_TRIM_2: + case RT1305_TUNE_INTERNAL_OSC: + case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0: + return true; + default: + return false; + } +} + +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0); + +static const char * const rt1305_rx_data_ch_select[] = { + "LR", + "RL", + "Copy L", + "Copy R", +}; + +static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2, + rt1305_rx_data_ch_select); + +static void rt1305_reset(struct regmap *regmap) +{ + regmap_write(regmap, RT1305_RESET, 0); +} + +static const struct snd_kcontrol_new rt1305_snd_controls[] = { + SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1, + 8, 0, 0xff, 0, dac_vol_tlv), + + /* I2S Data Channel Selection */ + SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum), +}; + +static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(source->dapm); + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int val; + + snd_soc_component_read(component, RT1305_CLK_1, &val); + + if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 && + (val & RT1305_SEL_PLL_SRC_2_RCCLK)) + return 1; + else + return 0; +} + +static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(source->dapm); + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1) + return 1; + else + return 0; +} + +static int rt1305_classd_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1, + RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1, + RT1305_POW_PDB_JD_MASK, 0); + usleep_range(150000, 200000); + break; + + default: + return 0; + } + + return 0; +} + +static const struct snd_kcontrol_new rt1305_sto_dac_l = + SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2, + RT1305_DVOL_MUTE_L_EN_SFT, 1, 1); + +static const struct snd_kcontrol_new rt1305_sto_dac_r = + SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2, + RT1305_DVOL_MUTE_R_EN_SFT, 1, 1); + +static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1, + RT1305_POW_PLL0_EN_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1, + RT1305_POW_PLL1_EN_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1, + RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1, + RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1, + RT1305_POW_LDO2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1, + RT1305_POW_BG2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1, + RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1, + RT1305_POW_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1, + RT1305_POW_VREF1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1, + RT1305_POW_VREF2_BIT, 0, NULL, 0), + + + SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2, + RT1305_POW_DISC_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2, + RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2, + RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2, + RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2, + RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2, + RT1305_POW_CLAMP_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2, + RT1305_POW_BUFL_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2, + RT1305_POW_BUFR_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2, + RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2, + RT1305_POW_ADC3_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2, + RT1305_POW_ADC3_R_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2, + RT1305_POW_TRIOSC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2, + RT1305_POR_AVDD1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2, + RT1305_POR_AVDD2_BIT, 0, NULL, 0), + + + SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3, + RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3, + RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3, + RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3, + RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3, + RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3, + RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3, + RT1305_EN_VCM_6172_BIT, 0, NULL, 0), + + + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + + /* Digital Interface */ + SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2, + RT1305_POW_DAC1_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2, + RT1305_POW_DAC1_R_BIT, 0, NULL, 0), + SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l), + SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r), + + /* Output Lines */ + SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, + rt1305_classd_event, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_OUTPUT("SPOL"), + SND_SOC_DAPM_OUTPUT("SPOR"), +}; + +static const struct snd_soc_dapm_route rt1305_dapm_routes[] = { + + { "DAC", NULL, "AIF1RX" }, + + { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll }, + { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll }, + + { "DAC", NULL, "MBIAS" }, + { "DAC", NULL, "BG MBIAS" }, + { "DAC", NULL, "LDO2" }, + { "DAC", NULL, "BG2" }, + { "DAC", NULL, "LDO2 IB2" }, + { "DAC", NULL, "VREF" }, + { "DAC", NULL, "VREF1" }, + { "DAC", NULL, "VREF2" }, + + { "DAC", NULL, "DISC VREF" }, + { "DAC", NULL, "FASTB VREF" }, + { "DAC", NULL, "ULTRA FAST VREF" }, + { "DAC", NULL, "CHOP DAC" }, + { "DAC", NULL, "CKGEN DAC" }, + { "DAC", NULL, "CLAMP" }, + { "DAC", NULL, "CKGEN ADC" }, + { "DAC", NULL, "TRIOSC" }, + { "DAC", NULL, "AVDD1" }, + { "DAC", NULL, "AVDD2" }, + + { "DAC", NULL, "POR AVDD1" }, + { "DAC", NULL, "POR AVDD2" }, + { "DAC", NULL, "VCM 6172" }, + + { "DAC L", "Switch", "DAC" }, + { "DAC R", "Switch", "DAC" }, + + { "DAC R", NULL, "VSENSE R" }, + { "DAC L", NULL, "VSENSE L" }, + { "DAC R", NULL, "ISENSE R" }, + { "DAC L", NULL, "ISENSE L" }, + { "DAC L", NULL, "ADC3 L" }, + { "DAC R", NULL, "ADC3 R" }, + { "DAC L", NULL, "BUFL" }, + { "DAC R", NULL, "BUFR" }, + { "DAC L", NULL, "DAC L Power" }, + { "DAC R", NULL, "DAC R Power" }, + + { "CLASS D", NULL, "DAC L" }, + { "CLASS D", NULL, "DAC R" }, + + { "SPOL", NULL, "CLASS D" }, + { "SPOR", NULL, "CLASS D" }, +}; + +static int rt1305_get_clk_info(int sclk, int rate) +{ + int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; + + if (sclk <= 0 || rate <= 0) + return -EINVAL; + + rate = rate << 8; + for (i = 0; i < ARRAY_SIZE(pd); i++) + if (sclk == rate * pd[i]) + return i; + + return -EINVAL; +} + +static int rt1305_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int val_len = 0, val_clk, mask_clk; + int pre_div, bclk_ms, frame_size; + + rt1305->lrck = params_rate(params); + pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck); + if (pre_div < 0) { + dev_warn(component->dev, "Force using PLL "); + snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK, + rt1305->lrck * 64, rt1305->lrck * 256); + snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1, + rt1305->lrck * 256, SND_SOC_CLOCK_IN); + pre_div = 0; + } + frame_size = snd_soc_params_to_frame_size(params); + if (frame_size < 0) { + dev_err(component->dev, "Unsupported frame size: %d\n", + frame_size); + return -EINVAL; + } + + bclk_ms = frame_size > 32; + rt1305->bclk = rt1305->lrck * (32 << bclk_ms); + + dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", + bclk_ms, pre_div, dai->id); + + dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", + rt1305->lrck, pre_div, dai->id); + + switch (params_width(params)) { + case 16: + val_len |= RT1305_I2S_DL_SEL_16B; + break; + case 20: + val_len |= RT1305_I2S_DL_SEL_20B; + break; + case 24: + val_len |= RT1305_I2S_DL_SEL_24B; + break; + case 8: + val_len |= RT1305_I2S_DL_SEL_8B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT1305_AIF1: + mask_clk = RT1305_DIV_FS_SYS_MASK; + val_clk = pre_div << RT1305_DIV_FS_SYS_SFT; + snd_soc_component_update_bits(component, RT1305_I2S_SET_2, + RT1305_I2S_DL_SEL_MASK, + val_len); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + + snd_soc_component_update_bits(component, RT1305_CLK_2, + mask_clk, val_clk); + + return 0; +} + +static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0, reg1_val = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + reg_val |= RT1305_SEL_I2S_OUT_MODE_M; + rt1305->master = 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + reg_val |= RT1305_SEL_I2S_OUT_MODE_S; + rt1305->master = 0; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + reg1_val |= RT1305_I2S_BCLK_INV; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + break; + case SND_SOC_DAIFMT_LEFT_J: + reg1_val |= RT1305_I2S_DF_SEL_LEFT; + break; + case SND_SOC_DAIFMT_DSP_A: + reg1_val |= RT1305_I2S_DF_SEL_PCM_A; + break; + case SND_SOC_DAIFMT_DSP_B: + reg1_val |= RT1305_I2S_DF_SEL_PCM_B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT1305_AIF1: + snd_soc_component_update_bits(component, RT1305_I2S_SET_1, + RT1305_SEL_I2S_OUT_MODE_MASK, reg_val); + snd_soc_component_update_bits(component, RT1305_I2S_SET_2, + RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK, + reg1_val); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + return 0; +} + +static int rt1305_set_component_sysclk(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0; + + if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src) + return 0; + + switch (clk_id) { + case RT1305_FS_SYS_PRE_S_MCLK: + reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK; + snd_soc_component_update_bits(component, + RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK, + RT1305_SEL_CLK_DET_SRC_MCLK); + break; + case RT1305_FS_SYS_PRE_S_PLL1: + reg_val |= RT1305_SEL_FS_SYS_PRE_PLL; + break; + case RT1305_FS_SYS_PRE_S_RCCLK: + reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK; + break; + default: + dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); + return -EINVAL; + } + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_FS_SYS_PRE_MASK, reg_val); + rt1305->sysclk = freq; + rt1305->sysclk_src = clk_id; + + dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", + freq, clk_id); + + return 0; +} + +static int rt1305_set_component_pll(struct snd_soc_component *component, + int pll_id, int source, unsigned int freq_in, + unsigned int freq_out) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + struct rl6231_pll_code pll_code; + int ret; + + if (source == rt1305->pll_src && freq_in == rt1305->pll_in && + freq_out == rt1305->pll_out) + return 0; + + if (!freq_in || !freq_out) { + dev_dbg(component->dev, "PLL disabled\n"); + + rt1305->pll_in = 0; + rt1305->pll_out = 0; + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK, + RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK); + return 0; + } + + switch (source) { + case RT1305_PLL2_S_MCLK: + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK | + RT1305_DIV_PLL_SRC_2_MASK, + RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2); + snd_soc_component_update_bits(component, + RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK, + RT1305_SEL_CLK_DET_SRC_MCLK); + break; + case RT1305_PLL1_S_BCLK: + snd_soc_component_update_bits(component, + RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK, + RT1305_SEL_PLL_SRC_1_BCLK); + break; + case RT1305_PLL2_S_RCCLK: + snd_soc_component_update_bits(component, RT1305_CLK_1, + RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK | + RT1305_DIV_PLL_SRC_2_MASK, + RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2); + freq_in = 98304000; + break; + default: + dev_err(component->dev, "Unknown PLL Source %d\n", source); + return -EINVAL; + } + + ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); + if (ret < 0) { + dev_err(component->dev, "Unsupport input clock %d\n", freq_in); + return ret; + } + + dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", + pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), + pll_code.n_code, pll_code.k_code); + + snd_soc_component_write(component, RT1305_PLL1_1, + (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT | + pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT | + pll_code.n_code); + snd_soc_component_write(component, RT1305_PLL1_2, + pll_code.k_code); + + rt1305->pll_in = freq_in; + rt1305->pll_out = freq_out; + rt1305->pll_src = source; + + return 0; +} + +static int rt1305_probe(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + rt1305->component = component; + + /* initial settings */ + rt1305_reg_init(component); + + return 0; +} + +static void rt1305_remove(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + rt1305_reset(rt1305->regmap); +} + +#ifdef CONFIG_PM +static int rt1305_suspend(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt1305->regmap, true); + regcache_mark_dirty(rt1305->regmap); + + return 0; +} + +static int rt1305_resume(struct snd_soc_component *component) +{ + struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt1305->regmap, false); + regcache_sync(rt1305->regmap); + + return 0; +} +#else +#define rt1305_suspend NULL +#define rt1305_resume NULL +#endif + +#define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000 +#define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +static const struct snd_soc_dai_ops rt1305_aif_dai_ops = { + .hw_params = rt1305_hw_params, + .set_fmt = rt1305_set_dai_fmt, +}; + +static struct snd_soc_dai_driver rt1305_dai[] = { + { + .name = "rt1305-aif", + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1305_STEREO_RATES, + .formats = RT1305_FORMATS, + }, + .ops = &rt1305_aif_dai_ops, + }, +}; + +static const struct snd_soc_component_driver soc_component_dev_rt1305 = { + .probe = rt1305_probe, + .remove = rt1305_remove, + .suspend = rt1305_suspend, + .resume = rt1305_resume, + .controls = rt1305_snd_controls, + .num_controls = ARRAY_SIZE(rt1305_snd_controls), + .dapm_widgets = rt1305_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets), + .dapm_routes = rt1305_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes), + .set_sysclk = rt1305_set_component_sysclk, + .set_pll = rt1305_set_component_pll, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, +}; + +static const struct regmap_config rt1305_regmap = { + .reg_bits = 8, + .val_bits = 16, + .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) * + RT1305_PR_SPACING), + .volatile_reg = rt1305_volatile_register, + .readable_reg = rt1305_readable_register, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = rt1305_reg, + .num_reg_defaults = ARRAY_SIZE(rt1305_reg), + .ranges = rt1305_ranges, + .num_ranges = ARRAY_SIZE(rt1305_ranges), + .use_single_rw = true, +}; + +#if defined(CONFIG_OF) +static const struct of_device_id rt1305_of_match[] = { + { .compatible = "realtek,rt1305", }, + { .compatible = "realtek,rt1306", }, + {}, +}; +MODULE_DEVICE_TABLE(of, rt1305_of_match); +#endif + +#ifdef CONFIG_ACPI +static struct acpi_device_id rt1305_acpi_match[] = { + {"10EC1305", 0,}, + {"10EC1306", 0,}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match); +#endif + +static const struct i2c_device_id rt1305_i2c_id[] = { + { "rt1305", 0 }, + { "rt1306", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id); + +static void rt1305_calibrate(struct rt1305_priv *rt1305) +{ + unsigned int valmsb, vallsb, offsetl, offsetr; + unsigned int rh, rl, rhl, r0ohm; + u64 r0l, r0r; + + regcache_cache_bypass(rt1305->regmap, true); + + rt1305_reset(rt1305->regmap); + regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); + regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000); + regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); + + /* Sin Gen */ + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); + + regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); + regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); + + /* EFUSE read */ + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000); + regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000); + + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb); + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb); + offsetl = valmsb << 16 | vallsb; + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb); + regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb); + offsetr = valmsb << 16 | vallsb; + pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr); + + /* R0 calibration */ + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe); + regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13); + regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650); + + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c); + regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); + msleep(2000); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); + rhl = (rh << 16) | rl; + r0ohm = (rhl*10) / 33554432; + + pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl); + pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10)); + + r0l = 562949953421312; + if (rhl != 0) + do_div(r0l, rhl); + pr_debug("Left_r0 = 0x%llx\n", r0l); + + regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); + msleep(2000); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); + regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); + rhl = (rh << 16) | rl; + r0ohm = (rhl*10) / 33554432; + + pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl); + pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10)); + + r0r = 562949953421312; + if (rhl != 0) + do_div(r0r, rhl); + pr_debug("Right_r0 = 0x%llx\n", r0r); + + regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec); + + if ((r0l > R0_UPPER) && (r0l < R0_LOWER) && + (r0r > R0_UPPER) && (r0r < R0_LOWER)) { + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e, + (r0l >> 16) & 0xffff); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f, + r0l & 0xffff); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe, + ((r0r >> 16) & 0xffff) | 0xf800); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd, + r0r & 0xffff); + } else { + pr_err("R0 calibration failed\n"); + } + + /* restore some registers */ + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); + usleep_range(200000, 400000); + regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); + regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000); + regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000); + regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020); + regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000); + + regcache_cache_bypass(rt1305->regmap, false); +} + +static int rt1305_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct rt1305_priv *rt1305; + int ret; + unsigned int val; + + rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv), + GFP_KERNEL); + if (rt1305 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, rt1305); + + rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap); + if (IS_ERR(rt1305->regmap)) { + ret = PTR_ERR(rt1305->regmap); + dev_err(&i2c->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val); + if (val != RT1305_DEVICE_ID_NUM) { + dev_err(&i2c->dev, + "Device with ID register %x is not rt1305\n", val); + return -ENODEV; + } + + rt1305_reset(rt1305->regmap); + rt1305_calibrate(rt1305); + + return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt1305, + rt1305_dai, ARRAY_SIZE(rt1305_dai)); +} + +static int rt1305_i2c_remove(struct i2c_client *i2c) +{ + snd_soc_unregister_component(&i2c->dev); + + return 0; +} + +static void rt1305_i2c_shutdown(struct i2c_client *client) +{ + struct rt1305_priv *rt1305 = i2c_get_clientdata(client); + + rt1305_reset(rt1305->regmap); +} + + +static struct i2c_driver rt1305_i2c_driver = { + .driver = { + .name = "rt1305", + .owner = THIS_MODULE, +#if defined(CONFIG_OF) + .of_match_table = rt1305_of_match, +#endif +#if defined(CONFIG_ACPI) + .acpi_match_table = ACPI_PTR(rt1305_acpi_match) +#endif + }, + .probe = rt1305_i2c_probe, + .remove = rt1305_i2c_remove, + .shutdown = rt1305_i2c_shutdown, + .id_table = rt1305_i2c_id, +}; +module_i2c_driver(rt1305_i2c_driver); + +MODULE_DESCRIPTION("ASoC RT1305 amplifier driver"); +MODULE_AUTHOR("Shuming Fan <shumingf(a)realtek.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/rt1305.h b/sound/soc/codecs/rt1305.h new file mode 100644 index 0000000..bde86f9 --- /dev/null +++ b/sound/soc/codecs/rt1305.h @@ -0,0 +1,276 @@ +/* + * RT1305.h -- RT1305 ALSA SoC amplifier component driver + * + * Copyright 2018 Realtek Semiconductor Corp. + * Author: Shuming Fan <shumingf(a)realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _RT1305_H_ +#define _RT1305_H_ + +#define RT1305_DEVICE_ID_NUM 0x6251 + +#define RT1305_RESET 0x00 +#define RT1305_CLK_1 0x04 +#define RT1305_CLK_2 0x05 +#define RT1305_CLK_3 0x06 +#define RT1305_DFLL_REG 0x07 +#define RT1305_CAL_EFUSE_CLOCK 0x08 +#define RT1305_PLL0_1 0x0a +#define RT1305_PLL0_2 0x0b +#define RT1305_PLL1_1 0x0c +#define RT1305_PLL1_2 0x0d +#define RT1305_MIXER_CTRL_1 0x10 +#define RT1305_MIXER_CTRL_2 0x11 +#define RT1305_DAC_SET_1 0x12 +#define RT1305_DAC_SET_2 0x14 +#define RT1305_ADC_SET_1 0x16 +#define RT1305_ADC_SET_2 0x17 +#define RT1305_ADC_SET_3 0x18 +#define RT1305_PATH_SET 0x20 +#define RT1305_SPDIF_IN_SET_1 0x22 +#define RT1305_SPDIF_IN_SET_2 0x24 +#define RT1305_SPDIF_IN_SET_3 0x26 +#define RT1305_SPDIF_OUT_SET_1 0x28 +#define RT1305_SPDIF_OUT_SET_2 0x2a +#define RT1305_SPDIF_OUT_SET_3 0x2b +#define RT1305_I2S_SET_1 0x2d +#define RT1305_I2S_SET_2 0x2e +#define RT1305_PBTL_MONO_MODE_SRC 0x2f +#define RT1305_MANUALLY_I2C_DEVICE 0x32 +#define RT1305_POWER_STATUS 0x39 +#define RT1305_POWER_CTRL_1 0x3a +#define RT1305_POWER_CTRL_2 0x3b +#define RT1305_POWER_CTRL_3 0x3c +#define RT1305_POWER_CTRL_4 0x3d +#define RT1305_POWER_CTRL_5 0x3e +#define RT1305_CLOCK_DETECT 0x3f +#define RT1305_BIQUAD_SET_1 0x40 +#define RT1305_BIQUAD_SET_2 0x42 +#define RT1305_ADJUSTED_HPF_1 0x46 +#define RT1305_ADJUSTED_HPF_2 0x47 +#define RT1305_EQ_SET_1 0x4b +#define RT1305_EQ_SET_2 0x4c +#define RT1305_SPK_TEMP_PROTECTION_0 0x4f +#define RT1305_SPK_TEMP_PROTECTION_1 0x50 +#define RT1305_SPK_TEMP_PROTECTION_2 0x51 +#define RT1305_SPK_TEMP_PROTECTION_3 0x52 +#define RT1305_SPK_DC_DETECT_1 0x53 +#define RT1305_SPK_DC_DETECT_2 0x54 +#define RT1305_LOUDNESS 0x58 +#define RT1305_THERMAL_FOLD_BACK_1 0x5e +#define RT1305_THERMAL_FOLD_BACK_2 0x5f +#define RT1305_SILENCE_DETECT 0x60 +#define RT1305_ALC_DRC_1 0x62 +#define RT1305_ALC_DRC_2 0x63 +#define RT1305_ALC_DRC_3 0x64 +#define RT1305_ALC_DRC_4 0x65 +#define RT1305_PRIV_INDEX 0x6a +#define RT1305_PRIV_DATA 0x6c +#define RT1305_SPK_EXCURSION_LIMITER_7 0x76 +#define RT1305_VERSION_ID 0x7a +#define RT1305_VENDOR_ID 0x7c +#define RT1305_DEVICE_ID 0x7e +#define RT1305_EFUSE_1 0x80 +#define RT1305_EFUSE_2 0x81 +#define RT1305_EFUSE_3 0x82 +#define RT1305_DC_CALIB_1 0x90 +#define RT1305_DC_CALIB_2 0x91 +#define RT1305_DC_CALIB_3 0x92 +#define RT1305_DAC_OFFSET_1 0x93 +#define RT1305_DAC_OFFSET_2 0x94 +#define RT1305_DAC_OFFSET_3 0x95 +#define RT1305_DAC_OFFSET_4 0x96 +#define RT1305_DAC_OFFSET_5 0x97 +#define RT1305_DAC_OFFSET_6 0x98 +#define RT1305_DAC_OFFSET_7 0x99 +#define RT1305_DAC_OFFSET_8 0x9a +#define RT1305_DAC_OFFSET_9 0x9b +#define RT1305_DAC_OFFSET_10 0x9c +#define RT1305_DAC_OFFSET_11 0x9d +#define RT1305_DAC_OFFSET_12 0x9e +#define RT1305_DAC_OFFSET_13 0x9f +#define RT1305_DAC_OFFSET_14 0xa0 +#define RT1305_TRIM_1 0xb0 +#define RT1305_TRIM_2 0xb1 +#define RT1305_TUNE_INTERNAL_OSC 0xb2 +#define RT1305_BIQUAD1_H0_L_28_16 0xc0 +#define RT1305_BIQUAD3_A2_R_15_0 0xfb +#define RT1305_MAX_REG 0xff + +/* CLOCK-1 (0x04) */ +#define RT1305_SEL_PLL_SRC_2_MASK (0x1 << 15) +#define RT1305_SEL_PLL_SRC_2_SFT 15 +#define RT1305_SEL_PLL_SRC_2_MCLK (0x0 << 15) +#define RT1305_SEL_PLL_SRC_2_RCCLK (0x1 << 15) +#define RT1305_DIV_PLL_SRC_2_MASK (0x3 << 13) +#define RT1305_DIV_PLL_SRC_2_SFT 13 +#define RT1305_SEL_PLL_SRC_1_MASK (0x3 << 10) +#define RT1305_SEL_PLL_SRC_1_SFT 10 +#define RT1305_SEL_PLL_SRC_1_PLL2 (0x0 << 10) +#define RT1305_SEL_PLL_SRC_1_BCLK (0x1 << 10) +#define RT1305_SEL_PLL_SRC_1_DFLL (0x2 << 10) +#define RT1305_SEL_FS_SYS_PRE_MASK (0x3 << 8) +#define RT1305_SEL_FS_SYS_PRE_SFT 8 +#define RT1305_SEL_FS_SYS_PRE_MCLK (0x0 << 8) +#define RT1305_SEL_FS_SYS_PRE_PLL (0x1 << 8) +#define RT1305_SEL_FS_SYS_PRE_RCCLK (0x2 << 8) +#define RT1305_DIV_FS_SYS_MASK (0x7 << 4) +#define RT1305_DIV_FS_SYS_SFT 4 + +/* PLL1M/N/K Code-1 (0x0c) */ +#define RT1305_PLL_1_M_SFT 12 +#define RT1305_PLL_1_M_BYPASS_MASK (0x1 << 11) +#define RT1305_PLL_1_M_BYPASS_SFT 11 +#define RT1305_PLL_1_M_BYPASS (0x1 << 11) +#define RT1305_PLL_1_N_MASK (0x1ff << 0) + +/* DAC Setting (0x14) */ +#define RT1305_DVOL_MUTE_L_EN_SFT 15 +#define RT1305_DVOL_MUTE_R_EN_SFT 14 + +/* I2S Setting-1 (0x2d) */ +#define RT1305_SEL_I2S_OUT_MODE_MASK (0x1 << 15) +#define RT1305_SEL_I2S_OUT_MODE_SFT 15 +#define RT1305_SEL_I2S_OUT_MODE_S (0x0 << 15) +#define RT1305_SEL_I2S_OUT_MODE_M (0x1 << 15) + +/* I2S Setting-2 (0x2e) */ +#define RT1305_I2S_DF_SEL_MASK (0x3 << 12) +#define RT1305_I2S_DF_SEL_SFT 12 +#define RT1305_I2S_DF_SEL_I2S (0x0 << 12) +#define RT1305_I2S_DF_SEL_LEFT (0x1 << 12) +#define RT1305_I2S_DF_SEL_PCM_A (0x2 << 12) +#define RT1305_I2S_DF_SEL_PCM_B (0x3 << 12) +#define RT1305_I2S_DL_SEL_MASK (0x3 << 10) +#define RT1305_I2S_DL_SEL_SFT 10 +#define RT1305_I2S_DL_SEL_16B (0x0 << 10) +#define RT1305_I2S_DL_SEL_20B (0x1 << 10) +#define RT1305_I2S_DL_SEL_24B (0x2 << 10) +#define RT1305_I2S_DL_SEL_8B (0x3 << 10) +#define RT1305_I2S_BCLK_MASK (0x1 << 9) +#define RT1305_I2S_BCLK_SFT 9 +#define RT1305_I2S_BCLK_NORMAL (0x0 << 9) +#define RT1305_I2S_BCLK_INV (0x1 << 9) + +/* Power Control-1 (0x3a) */ +#define RT1305_POW_PDB_JD_MASK (0x1 << 12) +#define RT1305_POW_PDB_JD (0x1 << 12) +#define RT1305_POW_PDB_JD_BIT 12 +#define RT1305_POW_PLL0_EN (0x1 << 11) +#define RT1305_POW_PLL0_EN_BIT 11 +#define RT1305_POW_PLL1_EN (0x1 << 10) +#define RT1305_POW_PLL1_EN_BIT 10 +#define RT1305_POW_PDB_JD_POLARITY (0x1 << 9) +#define RT1305_POW_PDB_JD_POLARITY_BIT 9 +#define RT1305_POW_MBIAS_LV (0x1 << 8) +#define RT1305_POW_MBIAS_LV_BIT 8 +#define RT1305_POW_BG_MBIAS_LV (0x1 << 7) +#define RT1305_POW_BG_MBIAS_LV_BIT 7 +#define RT1305_POW_LDO2 (0x1 << 6) +#define RT1305_POW_LDO2_BIT 6 +#define RT1305_POW_BG2 (0x1 << 5) +#define RT1305_POW_BG2_BIT 5 +#define RT1305_POW_LDO2_IB2 (0x1 << 4) +#define RT1305_POW_LDO2_IB2_BIT 4 +#define RT1305_POW_VREF (0x1 << 3) +#define RT1305_POW_VREF_BIT 3 +#define RT1305_POW_VREF1 (0x1 << 2) +#define RT1305_POW_VREF1_BIT 2 +#define RT1305_POW_VREF2 (0x1 << 1) +#define RT1305_POW_VREF2_BIT 1 + +/* Power Control-2 (0x3b) */ +#define RT1305_POW_DISC_VREF (1 << 15) +#define RT1305_POW_DISC_VREF_BIT 15 +#define RT1305_POW_FASTB_VREF (1 << 14) +#define RT1305_POW_FASTB_VREF_BIT 14 +#define RT1305_POW_ULTRA_FAST_VREF (1 << 13) +#define RT1305_POW_ULTRA_FAST_VREF_BIT 13 +#define RT1305_POW_CKXEN_DAC (1 << 12) +#define RT1305_POW_CKXEN_DAC_BIT 12 +#define RT1305_POW_EN_CKGEN_DAC (1 << 11) +#define RT1305_POW_EN_CKGEN_DAC_BIT 11 +#define RT1305_POW_DAC1_L (1 << 10) +#define RT1305_POW_DAC1_L_BIT 10 +#define RT1305_POW_DAC1_R (1 << 9) +#define RT1305_POW_DAC1_R_BIT 9 +#define RT1305_POW_CLAMP (1 << 8) +#define RT1305_POW_CLAMP_BIT 8 +#define RT1305_POW_BUFL (1 << 7) +#define RT1305_POW_BUFL_BIT 7 +#define RT1305_POW_BUFR (1 << 6) +#define RT1305_POW_BUFR_BIT 6 +#define RT1305_POW_EN_CKGEN_ADC (1 << 5) +#define RT1305_POW_EN_CKGEN_ADC_BIT 5 +#define RT1305_POW_ADC3_L (1 << 4) +#define RT1305_POW_ADC3_L_BIT 4 +#define RT1305_POW_ADC3_R (1 << 3) +#define RT1305_POW_ADC3_R_BIT 3 +#define RT1305_POW_TRIOSC (1 << 2) +#define RT1305_POW_TRIOSC_BIT 2 +#define RT1305_POR_AVDD1 (1 << 1) +#define RT1305_POR_AVDD1_BIT 1 +#define RT1305_POR_AVDD2 (1 << 0) +#define RT1305_POR_AVDD2_BIT 0 + +/* Power Control-3 (0x3c) */ +#define RT1305_POW_VSENSE_RCH (1 << 15) +#define RT1305_POW_VSENSE_RCH_BIT 15 +#define RT1305_POW_VSENSE_LCH (1 << 14) +#define RT1305_POW_VSENSE_LCH_BIT 14 +#define RT1305_POW_ISENSE_RCH (1 << 13) +#define RT1305_POW_ISENSE_RCH_BIT 13 +#define RT1305_POW_ISENSE_LCH (1 << 12) +#define RT1305_POW_ISENSE_LCH_BIT 12 +#define RT1305_POW_POR_AVDD1 (1 << 11) +#define RT1305_POW_POR_AVDD1_BIT 11 +#define RT1305_POW_POR_AVDD2 (1 << 10) +#define RT1305_POW_POR_AVDD2_BIT 10 +#define RT1305_EN_K_HV (1 << 9) +#define RT1305_EN_K_HV_BIT 9 +#define RT1305_EN_PRE_K_HV (1 << 8) +#define RT1305_EN_PRE_K_HV_BIT 8 +#define RT1305_EN_EFUSE_1P8V (1 << 7) +#define RT1305_EN_EFUSE_1P8V_BIT 7 +#define RT1305_EN_EFUSE_5V (1 << 6) +#define RT1305_EN_EFUSE_5V_BIT 6 +#define RT1305_EN_VCM_6172 (1 << 5) +#define RT1305_EN_VCM_6172_BIT 5 +#define RT1305_POR_EFUSE (1 << 4) +#define RT1305_POR_EFUSE_BIT 4 + +/* Clock Detect (0x3f) */ +#define RT1305_SEL_CLK_DET_SRC_MASK (0x1 << 12) +#define RT1305_SEL_CLK_DET_SRC_SFT 12 +#define RT1305_SEL_CLK_DET_SRC_MCLK (0x0 << 12) +#define RT1305_SEL_CLK_DET_SRC_BCLK (0x1 << 12) + + +/* System Clock Source */ +enum { + RT1305_FS_SYS_PRE_S_MCLK, + RT1305_FS_SYS_PRE_S_PLL1, + RT1305_FS_SYS_PRE_S_RCCLK, /* 98.304M Hz */ +}; + +/* PLL Source 1/2 */ +enum { + RT1305_PLL1_S_BCLK, + RT1305_PLL2_S_MCLK, + RT1305_PLL2_S_RCCLK, /* 98.304M Hz */ +}; + +enum { + RT1305_AIF1, + RT1305_AIFS +}; + +#define R0_UPPER 0x2E8BA2 //5.5 ohm +#define R0_LOWER 0x666666 //2.5 ohm + +#endif /* end of _RT1305_H_ */ -- 2.7.4

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