October 2018 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [asoc:for-4.20 519/524] sound/soc//stm/stm32_sai_sub.c:379:2: error: unknown field 'recalc_rate' specified in initializer
by kbuild test robot 19 Oct '18

19 Oct '18

tree: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-4.20 head: 318e741ee13b5a72f3051d9bb6852b1f4d02d0bb commit: 8307b2afd386ccce369821daa2196068c47fe8cd [519/524] ASoC: stm32: sai: set sai as mclk clock provider config: openrisc-allyesconfig (attached as .config) compiler: or1k-linux-gcc (GCC) 6.0.0 20160327 (experimental) reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 8307b2afd386ccce369821daa2196068c47fe8cd # save the attached .config to linux build tree make.cross ARCH=openrisc All errors (new ones prefixed by >>): sound/soc//stm/stm32_sai_sub.c:260:16: error: field 'hw' has incomplete type struct clk_hw hw; ^~ In file included from include/linux/err.h:5:0, from include/linux/clk.h:15, from sound/soc//stm/stm32_sai_sub.c:19: sound/soc//stm/stm32_sai_sub.c: In function 'stm32_sai_mclk_round_rate': include/linux/kernel.h:997:32: error: dereferencing pointer to incomplete type 'struct clk_hw' BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \ ^~~~~~ include/linux/compiler.h:335:18: note: in definition of macro '__compiletime_assert' int __cond = !(condition); \ ^~~~~~~~~ include/linux/compiler.h:358:2: note: in expansion of macro '_compiletime_assert' _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__) ^~~~~~~~~~~~~~~~~~~ include/linux/build_bug.h:45:37: note: in expansion of macro 'compiletime_assert' #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ^~~~~~~~~~~~~~~~~~ include/linux/kernel.h:997:2: note: in expansion of macro 'BUILD_BUG_ON_MSG' BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \ ^~~~~~~~~~~~~~~~ include/linux/kernel.h:997:20: note: in expansion of macro '__same_type' BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \ ^~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:265:27: note: in expansion of macro 'container_of' #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) ^~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:313:37: note: in expansion of macro 'to_mclk_data' struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); ^~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c: At top level: sound/soc//stm/stm32_sai_sub.c:376:21: error: variable 'mclk_ops' has initializer but incomplete type static const struct clk_ops mclk_ops = { ^~~~~~~ >> sound/soc//stm/stm32_sai_sub.c:377:2: error: unknown field 'enable' specified in initializer .enable = stm32_sai_mclk_enable, ^ sound/soc//stm/stm32_sai_sub.c:377:12: warning: excess elements in struct initializer .enable = stm32_sai_mclk_enable, ^~~~~~~~~~~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:377:12: note: (near initialization for 'mclk_ops') >> sound/soc//stm/stm32_sai_sub.c:378:2: error: unknown field 'disable' specified in initializer .disable = stm32_sai_mclk_disable, ^ sound/soc//stm/stm32_sai_sub.c:378:13: warning: excess elements in struct initializer .disable = stm32_sai_mclk_disable, ^~~~~~~~~~~~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:378:13: note: (near initialization for 'mclk_ops') >> sound/soc//stm/stm32_sai_sub.c:379:2: error: unknown field 'recalc_rate' specified in initializer .recalc_rate = stm32_sai_mclk_recalc_rate, ^ sound/soc//stm/stm32_sai_sub.c:379:17: warning: excess elements in struct initializer .recalc_rate = stm32_sai_mclk_recalc_rate, ^~~~~~~~~~~~~~~~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:379:17: note: (near initialization for 'mclk_ops') >> sound/soc//stm/stm32_sai_sub.c:380:2: error: unknown field 'round_rate' specified in initializer .round_rate = stm32_sai_mclk_round_rate, ^ sound/soc//stm/stm32_sai_sub.c:380:16: warning: excess elements in struct initializer .round_rate = stm32_sai_mclk_round_rate, ^~~~~~~~~~~~~~~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:380:16: note: (near initialization for 'mclk_ops') >> sound/soc//stm/stm32_sai_sub.c:381:2: error: unknown field 'set_rate' specified in initializer .set_rate = stm32_sai_mclk_set_rate, ^ sound/soc//stm/stm32_sai_sub.c:381:14: warning: excess elements in struct initializer .set_rate = stm32_sai_mclk_set_rate, ^~~~~~~~~~~~~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:381:14: note: (near initialization for 'mclk_ops') sound/soc//stm/stm32_sai_sub.c: In function 'stm32_sai_add_mclk_provider': >> sound/soc//stm/stm32_sai_sub.c:389:22: error: implicit declaration of function '__clk_get_name' [-Werror=implicit-function-declaration] const char *pname = __clk_get_name(sai->sai_ck); ^~~~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:389:22: warning: initialization makes pointer from integer without a cast [-Wint-conversion] >> sound/soc//stm/stm32_sai_sub.c:414:18: error: implicit declaration of function 'CLK_HW_INIT' [-Werror=implicit-function-declaration] mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); ^~~~~~~~~~~ >> sound/soc//stm/stm32_sai_sub.c:419:8: error: implicit declaration of function 'devm_clk_hw_register' [-Werror=implicit-function-declaration] ret = devm_clk_hw_register(&sai->pdev->dev, hw); ^~~~~~~~~~~~~~~~~~~~ >> sound/soc//stm/stm32_sai_sub.c:427:9: error: implicit declaration of function 'devm_of_clk_add_hw_provider' [-Werror=implicit-function-declaration] return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); ^~~~~~~~~~~~~~~~~~~~~~~~~~~ >> sound/soc//stm/stm32_sai_sub.c:427:42: error: 'of_clk_hw_simple_get' undeclared (first use in this function) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); ^~~~~~~~~~~~~~~~~~~~ sound/soc//stm/stm32_sai_sub.c:427:42: note: each undeclared identifier is reported only once for each function it appears in sound/soc//stm/stm32_sai_sub.c: At top level: sound/soc//stm/stm32_sai_sub.c:376:29: error: storage size of 'mclk_ops' isn't known static const struct clk_ops mclk_ops = { ^~~~~~~~ sound/soc//stm/stm32_sai_sub.c: In function 'stm32_sai_add_mclk_provider': sound/soc//stm/stm32_sai_sub.c:428:1: warning: control reaches end of non-void function [-Wreturn-type] } ^ cc1: some warnings being treated as errors vim +/recalc_rate +379 sound/soc//stm/stm32_sai_sub.c 309 310 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 311 unsigned long *prate) 312 { > 313 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 314 struct stm32_sai_sub_data *sai = mclk->sai_data; 315 int div; 316 317 div = stm32_sai_get_clk_div(sai, *prate, rate); 318 if (div < 0) 319 return div; 320 321 mclk->freq = *prate / div; 322 323 return mclk->freq; 324 } 325 326 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 327 unsigned long parent_rate) 328 { 329 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 330 331 return mclk->freq; 332 } 333 334 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 335 unsigned long parent_rate) 336 { 337 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 338 struct stm32_sai_sub_data *sai = mclk->sai_data; 339 unsigned int div; 340 int ret; 341 342 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 343 if (div < 0) 344 return div; 345 346 ret = stm32_sai_set_clk_div(sai, div); 347 if (ret) 348 return ret; 349 350 mclk->freq = rate; 351 352 return 0; 353 } 354 355 static int stm32_sai_mclk_enable(struct clk_hw *hw) 356 { 357 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 358 struct stm32_sai_sub_data *sai = mclk->sai_data; 359 360 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 361 362 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 363 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 364 } 365 366 static void stm32_sai_mclk_disable(struct clk_hw *hw) 367 { 368 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 369 struct stm32_sai_sub_data *sai = mclk->sai_data; 370 371 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 372 373 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 374 } 375 376 static const struct clk_ops mclk_ops = { > 377 .enable = stm32_sai_mclk_enable, > 378 .disable = stm32_sai_mclk_disable, > 379 .recalc_rate = stm32_sai_mclk_recalc_rate, > 380 .round_rate = stm32_sai_mclk_round_rate, > 381 .set_rate = stm32_sai_mclk_set_rate, 382 }; 383 384 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 385 { 386 struct clk_hw *hw; 387 struct stm32_sai_mclk_data *mclk; 388 struct device *dev = &sai->pdev->dev; > 389 const char *pname = __clk_get_name(sai->sai_ck); 390 char *mclk_name, *p, *s = (char *)pname; 391 int ret, i = 0; 392 393 mclk = devm_kzalloc(dev, sizeof(mclk), GFP_KERNEL); 394 if (!mclk) 395 return -ENOMEM; 396 397 mclk_name = devm_kcalloc(dev, sizeof(char), 398 SAI_MCLK_NAME_LEN, GFP_KERNEL); 399 if (!mclk_name) 400 return -ENOMEM; 401 402 /* 403 * Forge mclk clock name from parent clock name and suffix. 404 * String after "_" char is stripped in parent name. 405 */ 406 p = mclk_name; 407 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 6))) { 408 *p++ = *s++; 409 i++; 410 } 411 STM_SAI_IS_SUB_A(sai) ? 412 strncat(p, "a_mclk", 6) : strncat(p, "b_mclk", 6); 413 > 414 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 415 mclk->sai_data = sai; 416 hw = &mclk->hw; 417 418 dev_dbg(dev, "Register master clock %s\n", mclk_name); > 419 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 420 if (ret) { 421 dev_err(dev, "mclk register returned %d\n", ret); 422 return ret; 423 } 424 sai->sai_mclk = hw->clk; 425 426 /* register mclk provider */ > 427 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 428 } 429 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[alsa-devel] [PATCH v2 0/9] Add support for audiocodec in Allwinner A64
by Vasily Khoruzhick 19 Oct '18

19 Oct '18

This series adds Allwinner A64 audiocodec support into sun4i-i2s, sun8i-codec drivers, introduces new sun50i-codec-analog driver and enables sound on Pine64, SoPine boards and Pinebook. I2S for audiocodec in A64 is different from other 3 I2S modules but similar to one in A10, digital part of codec is compatible with A33 and analog controls part is completely different from other SoCs - it shares only few bits in few registers, so adding support for it into existing sun8i-codec-analog would mean duplicating all the widgets, controls and some routes and making it hard to read. Therefore it makes sense to introduce new driver. v2: - Use simple-amplifier for speaker amp on Pinebook - Rename sun50i-a64-i2s to sun50i-a64-codec-i2s to preserve compatible string for other 3 I2S modules in A64 in case if there's any incompatibility with H3 Marcus Cooper (1): ASoC: sun4i-i2s: Add compatibility with A64 codec I2S Vasily Khoruzhick (8): ASoC: sun8i-codec: Don't hardcode BCLK / LRCK ratio ASoC: sun8i-codec-analog: split regmap code into separate driver ASoC: dt-binding: Add bindings for Allwinner A64 codec's analog path controls ASoC: sunxi: Add new driver for Allwinner A64 codec's analog path controls ASoC: sunxi: allow the sun8i-codec driver to be built on ARM64 arm64: dts: allwinner: a64: add nodes necessary for analog sound support arm64: dts: allwinner: a64: enable sound on Pine64 and SoPine arm64: dts: allwinner: a64: enable sound on Pinebook .../devicetree/bindings/sound/sun4i-i2s.txt | 2 + .../bindings/sound/sun50i-codec-analog.txt | 12 + .../boot/dts/allwinner/sun50i-a64-pine64.dts | 30 ++ .../dts/allwinner/sun50i-a64-pinebook.dts | 42 ++ .../allwinner/sun50i-a64-sopine-baseboard.dts | 30 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 58 +++ sound/soc/sunxi/Kconfig | 17 +- sound/soc/sunxi/Makefile | 2 + sound/soc/sunxi/sun4i-i2s.c | 21 + sound/soc/sunxi/sun50i-codec-analog.c | 444 ++++++++++++++++++ sound/soc/sunxi/sun8i-codec-analog.c | 79 +--- sound/soc/sunxi/sun8i-codec.c | 35 +- sound/soc/sunxi/sunxi-adda-pr-regmap.c | 102 ++++ sound/soc/sunxi/sunxi-adda-pr-regmap.h | 7 + 14 files changed, 798 insertions(+), 83 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/sun50i-codec-analog.txt create mode 100644 sound/soc/sunxi/sun50i-codec-analog.c create mode 100644 sound/soc/sunxi/sunxi-adda-pr-regmap.c create mode 100644 sound/soc/sunxi/sunxi-adda-pr-regmap.h -- 2.19.0

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[alsa-devel] [PATCH 1/1] ASoC: cs42l51: fix mclk support
by Olivier Moysan 19 Oct '18

19 Oct '18

Fixes: 5e8d63a726f8 ("ASoC: cs42l51: add mclk support") The MCLK clock is made optional for cs42l51 codec. However, ASoC DAPM clock supply widget, expects the clock to be defined unconditionally. Register MCLK DAPM conditionally in codec driver, depending on clock presence in DT. Signed-off-by: Olivier Moysan <olivier.moysan(a)st.com> --- sound/soc/codecs/cs42l51.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c index eb40bff54cec..fd2bd74024c1 100644 --- a/sound/soc/codecs/cs42l51.c +++ b/sound/soc/codecs/cs42l51.c @@ -21,6 +21,7 @@ * - master mode *NOT* supported */ +#include <linux/clk.h> #include <linux/module.h> #include <linux/slab.h> #include <sound/core.h> @@ -41,6 +42,7 @@ enum master_slave_mode { struct cs42l51_private { unsigned int mclk; + struct clk *mclk_handle; unsigned int audio_mode; /* The mode (I2S or left-justified) */ enum master_slave_mode func; }; @@ -492,9 +494,13 @@ static int cs42l51_component_probe(struct snd_soc_component *component) { int ret, reg; struct snd_soc_dapm_context *dapm; + struct cs42l51_private *cs42l51; + cs42l51 = snd_soc_component_get_drvdata(component); dapm = snd_soc_component_get_dapm(component); - snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1); + + if (cs42l51->mclk_handle) + snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1); /* * DAC configuration @@ -548,6 +554,13 @@ int cs42l51_probe(struct device *dev, struct regmap *regmap) dev_set_drvdata(dev, cs42l51); + cs42l51->mclk_handle = devm_clk_get(dev, "MCLK"); + if (IS_ERR(cs42l51->mclk_handle)) { + if (PTR_ERR(cs42l51->mclk_handle) != -ENOENT) + return PTR_ERR(cs42l51->mclk_handle); + cs42l51->mclk_handle = NULL; + } + /* Verify that we have a CS42L51 */ ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val); if (ret < 0) { -- 2.7.4

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[alsa-devel] [asoc:for-4.20 519/523] sound/soc/stm/stm32_sai_sub.c:260:16: error: field 'hw' has incomplete type
by kbuild test robot 19 Oct '18

19 Oct '18

tree: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-4.20 head: 7ece50c9f790270e82b77589d34e54547c895a66 commit: 8307b2afd386ccce369821daa2196068c47fe8cd [519/523] ASoC: stm32: sai: set sai as mclk clock provider config: powerpc-allyesconfig (attached as .config) compiler: powerpc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 8307b2afd386ccce369821daa2196068c47fe8cd # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=powerpc All error/warnings (new ones prefixed by >>): >> sound/soc/stm/stm32_sai_sub.c:260:16: error: field 'hw' has incomplete type struct clk_hw hw; ^~ In file included from include/linux/err.h:5:0, from include/linux/clk.h:15, from sound/soc/stm/stm32_sai_sub.c:19: sound/soc/stm/stm32_sai_sub.c: In function 'stm32_sai_mclk_round_rate': include/linux/kernel.h:997:32: error: dereferencing pointer to incomplete type 'struct clk_hw' BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \ ^~~~~~ include/linux/compiler.h:335:18: note: in definition of macro '__compiletime_assert' int __cond = !(condition); \ ^~~~~~~~~ include/linux/compiler.h:358:2: note: in expansion of macro '_compiletime_assert' _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__) ^~~~~~~~~~~~~~~~~~~ include/linux/build_bug.h:45:37: note: in expansion of macro 'compiletime_assert' #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ^~~~~~~~~~~~~~~~~~ include/linux/kernel.h:997:2: note: in expansion of macro 'BUILD_BUG_ON_MSG' BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \ ^~~~~~~~~~~~~~~~ include/linux/kernel.h:997:20: note: in expansion of macro '__same_type' BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \ ^~~~~~~~~~~ >> sound/soc/stm/stm32_sai_sub.c:265:27: note: in expansion of macro 'container_of' #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) ^~~~~~~~~~~~ >> sound/soc/stm/stm32_sai_sub.c:313:37: note: in expansion of macro 'to_mclk_data' struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); ^~~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c: At top level: >> sound/soc/stm/stm32_sai_sub.c:376:21: error: variable 'mclk_ops' has initializer but incomplete type static const struct clk_ops mclk_ops = { ^~~~~~~ >> sound/soc/stm/stm32_sai_sub.c:377:3: error: 'const struct clk_ops' has no member named 'enable' .enable = stm32_sai_mclk_enable, ^~~~~~ >> sound/soc/stm/stm32_sai_sub.c:377:12: warning: excess elements in struct initializer .enable = stm32_sai_mclk_enable, ^~~~~~~~~~~~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:377:12: note: (near initialization for 'mclk_ops') >> sound/soc/stm/stm32_sai_sub.c:378:3: error: 'const struct clk_ops' has no member named 'disable' .disable = stm32_sai_mclk_disable, ^~~~~~~ sound/soc/stm/stm32_sai_sub.c:378:13: warning: excess elements in struct initializer .disable = stm32_sai_mclk_disable, ^~~~~~~~~~~~~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:378:13: note: (near initialization for 'mclk_ops') >> sound/soc/stm/stm32_sai_sub.c:379:3: error: 'const struct clk_ops' has no member named 'recalc_rate' .recalc_rate = stm32_sai_mclk_recalc_rate, ^~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:379:17: warning: excess elements in struct initializer .recalc_rate = stm32_sai_mclk_recalc_rate, ^~~~~~~~~~~~~~~~~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:379:17: note: (near initialization for 'mclk_ops') >> sound/soc/stm/stm32_sai_sub.c:380:3: error: 'const struct clk_ops' has no member named 'round_rate' .round_rate = stm32_sai_mclk_round_rate, ^~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:380:16: warning: excess elements in struct initializer .round_rate = stm32_sai_mclk_round_rate, ^~~~~~~~~~~~~~~~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:380:16: note: (near initialization for 'mclk_ops') >> sound/soc/stm/stm32_sai_sub.c:381:3: error: 'const struct clk_ops' has no member named 'set_rate' .set_rate = stm32_sai_mclk_set_rate, ^~~~~~~~ sound/soc/stm/stm32_sai_sub.c:381:14: warning: excess elements in struct initializer .set_rate = stm32_sai_mclk_set_rate, ^~~~~~~~~~~~~~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:381:14: note: (near initialization for 'mclk_ops') sound/soc/stm/stm32_sai_sub.c: In function 'stm32_sai_add_mclk_provider': >> sound/soc/stm/stm32_sai_sub.c:389:22: error: implicit declaration of function '__clk_get_name'; did you mean 'clk_get_rate'? [-Werror=implicit-function-declaration] const char *pname = __clk_get_name(sai->sai_ck); ^~~~~~~~~~~~~~ clk_get_rate >> sound/soc/stm/stm32_sai_sub.c:389:22: warning: initialization makes pointer from integer without a cast [-Wint-conversion] >> sound/soc/stm/stm32_sai_sub.c:414:18: error: implicit declaration of function 'CLK_HW_INIT'; did you mean 'KLIST_INIT'? [-Werror=implicit-function-declaration] mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); ^~~~~~~~~~~ KLIST_INIT >> sound/soc/stm/stm32_sai_sub.c:419:8: error: implicit declaration of function 'devm_clk_hw_register'; did you mean 'device_unregister'? [-Werror=implicit-function-declaration] ret = devm_clk_hw_register(&sai->pdev->dev, hw); ^~~~~~~~~~~~~~~~~~~~ device_unregister >> sound/soc/stm/stm32_sai_sub.c:427:9: error: implicit declaration of function 'devm_of_clk_add_hw_provider'; did you mean 'of_clk_get_from_provider'? [-Werror=implicit-function-declaration] return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); ^~~~~~~~~~~~~~~~~~~~~~~~~~~ of_clk_get_from_provider >> sound/soc/stm/stm32_sai_sub.c:427:42: error: 'of_clk_hw_simple_get' undeclared (first use in this function); did you mean 'ida_simple_get'? return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); ^~~~~~~~~~~~~~~~~~~~ ida_simple_get sound/soc/stm/stm32_sai_sub.c:427:42: note: each undeclared identifier is reported only once for each function it appears in sound/soc/stm/stm32_sai_sub.c: At top level: >> sound/soc/stm/stm32_sai_sub.c:376:29: error: storage size of 'mclk_ops' isn't known static const struct clk_ops mclk_ops = { ^~~~~~~~ sound/soc/stm/stm32_sai_sub.c: In function 'stm32_sai_add_mclk_provider': >> sound/soc/stm/stm32_sai_sub.c:428:1: warning: control reaches end of non-void function [-Wreturn-type] } ^ cc1: some warnings being treated as errors vim +/hw +260 sound/soc/stm/stm32_sai_sub.c 258 259 struct stm32_sai_mclk_data { > 260 struct clk_hw hw; 261 unsigned long freq; 262 struct stm32_sai_sub_data *sai_data; 263 }; 264 > 265 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 266 #define STM32_SAI_MAX_CLKS 1 267 268 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 269 unsigned long input_rate, 270 unsigned long output_rate) 271 { 272 int version = sai->pdata->conf->version; 273 int div; 274 275 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 276 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 277 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 278 return -EINVAL; 279 } 280 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 281 282 if (input_rate % div) 283 dev_dbg(&sai->pdev->dev, 284 "Rate not accurate. requested (%ld), actual (%ld)\n", 285 output_rate, input_rate / div); 286 287 return div; 288 } 289 290 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 291 unsigned int div) 292 { 293 int version = sai->pdata->conf->version; 294 int ret, cr1, mask; 295 296 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 297 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 298 return -EINVAL; 299 } 300 301 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 302 cr1 = SAI_XCR1_MCKDIV_SET(div); 303 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 304 if (ret < 0) 305 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 306 307 return ret; 308 } 309 310 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 311 unsigned long *prate) 312 { > 313 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 314 struct stm32_sai_sub_data *sai = mclk->sai_data; 315 int div; 316 317 div = stm32_sai_get_clk_div(sai, *prate, rate); 318 if (div < 0) 319 return div; 320 321 mclk->freq = *prate / div; 322 323 return mclk->freq; 324 } 325 326 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 327 unsigned long parent_rate) 328 { 329 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 330 331 return mclk->freq; 332 } 333 334 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 335 unsigned long parent_rate) 336 { 337 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 338 struct stm32_sai_sub_data *sai = mclk->sai_data; 339 unsigned int div; 340 int ret; 341 342 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 343 if (div < 0) 344 return div; 345 346 ret = stm32_sai_set_clk_div(sai, div); 347 if (ret) 348 return ret; 349 350 mclk->freq = rate; 351 352 return 0; 353 } 354 355 static int stm32_sai_mclk_enable(struct clk_hw *hw) 356 { 357 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 358 struct stm32_sai_sub_data *sai = mclk->sai_data; 359 360 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 361 362 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 363 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 364 } 365 366 static void stm32_sai_mclk_disable(struct clk_hw *hw) 367 { 368 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 369 struct stm32_sai_sub_data *sai = mclk->sai_data; 370 371 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 372 373 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 374 } 375 > 376 static const struct clk_ops mclk_ops = { > 377 .enable = stm32_sai_mclk_enable, > 378 .disable = stm32_sai_mclk_disable, > 379 .recalc_rate = stm32_sai_mclk_recalc_rate, > 380 .round_rate = stm32_sai_mclk_round_rate, > 381 .set_rate = stm32_sai_mclk_set_rate, 382 }; 383 384 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 385 { 386 struct clk_hw *hw; 387 struct stm32_sai_mclk_data *mclk; 388 struct device *dev = &sai->pdev->dev; > 389 const char *pname = __clk_get_name(sai->sai_ck); 390 char *mclk_name, *p, *s = (char *)pname; 391 int ret, i = 0; 392 393 mclk = devm_kzalloc(dev, sizeof(mclk), GFP_KERNEL); 394 if (!mclk) 395 return -ENOMEM; 396 397 mclk_name = devm_kcalloc(dev, sizeof(char), 398 SAI_MCLK_NAME_LEN, GFP_KERNEL); 399 if (!mclk_name) 400 return -ENOMEM; 401 402 /* 403 * Forge mclk clock name from parent clock name and suffix. 404 * String after "_" char is stripped in parent name. 405 */ 406 p = mclk_name; 407 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 6))) { 408 *p++ = *s++; 409 i++; 410 } 411 STM_SAI_IS_SUB_A(sai) ? 412 strncat(p, "a_mclk", 6) : strncat(p, "b_mclk", 6); 413 > 414 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 415 mclk->sai_data = sai; 416 hw = &mclk->hw; 417 418 dev_dbg(dev, "Register master clock %s\n", mclk_name); > 419 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 420 if (ret) { 421 dev_err(dev, "mclk register returned %d\n", ret); 422 return ret; 423 } 424 sai->sai_mclk = hw->clk; 425 426 /* register mclk provider */ > 427 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); > 428 } 429 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[alsa-devel] [asoc:for-4.20 519/523] sound/soc/stm/stm32_sai_sub.c:412:3: warning: 'strncat' specified bound 6 equals source length
by kbuild test robot 19 Oct '18

19 Oct '18

tree: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-4.20 head: 7ece50c9f790270e82b77589d34e54547c895a66 commit: 8307b2afd386ccce369821daa2196068c47fe8cd [519/523] ASoC: stm32: sai: set sai as mclk clock provider config: microblaze-allyesconfig (attached as .config) compiler: microblaze-linux-gcc (GCC) 8.1.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 8307b2afd386ccce369821daa2196068c47fe8cd # save the attached .config to linux build tree GCC_VERSION=8.1.0 make.cross ARCH=microblaze All warnings (new ones prefixed by >>): sound/soc/stm/stm32_sai_sub.c: In function 'stm32_sai_add_mclk_provider': >> sound/soc/stm/stm32_sai_sub.c:412:3: warning: 'strncat' specified bound 6 equals source length [-Wstringop-overflow=] strncat(p, "a_mclk", 6) : strncat(p, "b_mclk", 6); ^~~~~~~~~~~~~~~~~~~~~~~ sound/soc/stm/stm32_sai_sub.c:412:29: warning: 'strncat' specified bound 6 equals source length [-Wstringop-overflow=] strncat(p, "a_mclk", 6) : strncat(p, "b_mclk", 6); ^~~~~~~~~~~~~~~~~~~~~~~ vim +/strncat +412 sound/soc/stm/stm32_sai_sub.c 383 384 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 385 { 386 struct clk_hw *hw; 387 struct stm32_sai_mclk_data *mclk; 388 struct device *dev = &sai->pdev->dev; 389 const char *pname = __clk_get_name(sai->sai_ck); 390 char *mclk_name, *p, *s = (char *)pname; 391 int ret, i = 0; 392 393 mclk = devm_kzalloc(dev, sizeof(mclk), GFP_KERNEL); 394 if (!mclk) 395 return -ENOMEM; 396 397 mclk_name = devm_kcalloc(dev, sizeof(char), 398 SAI_MCLK_NAME_LEN, GFP_KERNEL); 399 if (!mclk_name) 400 return -ENOMEM; 401 402 /* 403 * Forge mclk clock name from parent clock name and suffix. 404 * String after "_" char is stripped in parent name. 405 */ 406 p = mclk_name; 407 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 6))) { 408 *p++ = *s++; 409 i++; 410 } 411 STM_SAI_IS_SUB_A(sai) ? > 412 strncat(p, "a_mclk", 6) : strncat(p, "b_mclk", 6); 413 414 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 415 mclk->sai_data = sai; 416 hw = &mclk->hw; 417 418 dev_dbg(dev, "Register master clock %s\n", mclk_name); 419 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 420 if (ret) { 421 dev_err(dev, "mclk register returned %d\n", ret); 422 return ret; 423 } 424 sai->sai_mclk = hw->clk; 425 426 /* register mclk provider */ 427 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 428 } 429 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

1 0

[alsa-devel] Applied "ASoC: tegra_sgtl5000: fix device_node refcounting" to the asoc tree
by Mark Brown 19 Oct '18

19 Oct '18

The patch ASoC: tegra_sgtl5000: fix device_node refcounting has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From a85227da2dcc291b762c8482a505bc7d0d2d4b07 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Date: Tue, 16 Oct 2018 12:47:29 +0200 Subject: [PATCH] ASoC: tegra_sgtl5000: fix device_node refcounting Similar to the following: commit 4321723648b0 ("ASoC: tegra_alc5632: fix device_node refcounting") commit 7c5dfd549617 ("ASoC: tegra: fix device_node refcounting") Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Acked-by: Jon Hunter <jonathanh(a)nvidia.com> Signed-off-by: Mark Brown <broonie(a)kernel.org> --- sound/soc/tegra/tegra_sgtl5000.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/sound/soc/tegra/tegra_sgtl5000.c b/sound/soc/tegra/tegra_sgtl5000.c index 45a4aa9d2a47..901457da25ec 100644 --- a/sound/soc/tegra/tegra_sgtl5000.c +++ b/sound/soc/tegra/tegra_sgtl5000.c @@ -149,14 +149,14 @@ static int tegra_sgtl5000_driver_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Property 'nvidia,i2s-controller' missing/invalid\n"); ret = -EINVAL; - goto err; + goto err_put_codec_of_node; } tegra_sgtl5000_dai.platform_of_node = tegra_sgtl5000_dai.cpu_of_node; ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev); if (ret) - goto err; + goto err_put_cpu_of_node; ret = snd_soc_register_card(card); if (ret) { @@ -169,6 +169,13 @@ static int tegra_sgtl5000_driver_probe(struct platform_device *pdev) err_fini_utils: tegra_asoc_utils_fini(&machine->util_data); +err_put_cpu_of_node: + of_node_put(tegra_sgtl5000_dai.cpu_of_node); + tegra_sgtl5000_dai.cpu_of_node = NULL; + tegra_sgtl5000_dai.platform_of_node = NULL; +err_put_codec_of_node: + of_node_put(tegra_sgtl5000_dai.codec_of_node); + tegra_sgtl5000_dai.codec_of_node = NULL; err: return ret; } @@ -183,6 +190,12 @@ static int tegra_sgtl5000_driver_remove(struct platform_device *pdev) tegra_asoc_utils_fini(&machine->util_data); + of_node_put(tegra_sgtl5000_dai.cpu_of_node); + tegra_sgtl5000_dai.cpu_of_node = NULL; + tegra_sgtl5000_dai.platform_of_node = NULL; + of_node_put(tegra_sgtl5000_dai.codec_of_node); + tegra_sgtl5000_dai.codec_of_node = NULL; + return ret; } -- 2.19.0.rc2

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[alsa-devel] [PATCH] ASoC: nau8822: new codec driver
by David Lin 19 Oct '18

19 Oct '18

Add driver for NAU88C22. Signed-off-by: David Lin <CTLIN0(a)nuvoton.com> --- .../devicetree/bindings/sound/nau8822.txt | 16 + sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/nau8822.c | 1136 +++++++++++++++++ sound/soc/codecs/nau8822.h | 204 +++ 5 files changed, 1363 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/nau8822.txt create mode 100644 sound/soc/codecs/nau8822.c create mode 100644 sound/soc/codecs/nau8822.h diff --git a/Documentation/devicetree/bindings/sound/nau8822.txt b/Documentation/devicetree/bindings/sound/nau8822.txt new file mode 100644 index 000000000000..a471d162d4e5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nau8822.txt @@ -0,0 +1,16 @@ +NAU8822 audio CODEC + +This device supports I2C only. + +Required properties: + + - compatible : "nuvoton,nau8822" + + - reg : the I2C address of the device. + +Example: + +codec: nau8822@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; +}; diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index efb095dbcd71..57365dbc1581 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -109,6 +109,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_MT6351 if MTK_PMIC_WRAP select SND_SOC_NAU8540 if I2C select SND_SOC_NAU8810 if I2C + select SND_SOC_NAU8822 if I2C select SND_SOC_NAU8824 if I2C select SND_SOC_NAU8825 if I2C select SND_SOC_HDMI_CODEC @@ -1299,6 +1300,10 @@ config SND_SOC_NAU8810 tristate "Nuvoton Technology Corporation NAU88C10 CODEC" depends on I2C +config SND_SOC_NAU8822 + tristate "Nuvoton Technology Corporation NAU88C22 CODEC" + depends on I2C + config SND_SOC_NAU8824 tristate "Nuvoton Technology Corporation NAU88L24 CODEC" depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 7ae7c85e8219..181a7d222fd7 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -106,6 +106,7 @@ snd-soc-msm8916-digital-objs := msm8916-wcd-digital.o snd-soc-mt6351-objs := mt6351.o snd-soc-nau8540-objs := nau8540.o snd-soc-nau8810-objs := nau8810.o +snd-soc-nau8822-objs := nau8822.o snd-soc-nau8824-objs := nau8824.o snd-soc-nau8825-objs := nau8825.o snd-soc-hdmi-codec-objs := hdmi-codec.o @@ -366,6 +367,7 @@ obj-$(CONFIG_SND_SOC_MSM8916_WCD_DIGITAL) +=snd-soc-msm8916-digital.o obj-$(CONFIG_SND_SOC_MT6351) += snd-soc-mt6351.o obj-$(CONFIG_SND_SOC_NAU8540) += snd-soc-nau8540.o obj-$(CONFIG_SND_SOC_NAU8810) += snd-soc-nau8810.o +obj-$(CONFIG_SND_SOC_NAU8822) += snd-soc-nau8822.o obj-$(CONFIG_SND_SOC_NAU8824) += snd-soc-nau8824.o obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o diff --git a/sound/soc/codecs/nau8822.c b/sound/soc/codecs/nau8822.c new file mode 100644 index 000000000000..622ce947f134 --- /dev/null +++ b/sound/soc/codecs/nau8822.c @@ -0,0 +1,1136 @@ +/* + * nau8822.c -- NAU8822 ALSA Soc Audio Codec driver + * + * Copyright 2017 Nuvoton Technology Corp. + * + * Author: David Lin <ctlin0(a)nuvoton.com> + * Co-author: John Hsu <kchsu0(a)nuvoton.com> + * Co-author: Seven Li <wtli(a)nuvoton.com> + * + * Based on WM8974.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <asm/div64.h> +#include "nau8822.h" + +#define NAU_PLL_FREQ_MAX 100000000 +#define NAU_PLL_FREQ_MIN 90000000 +#define NAU_PLL_REF_MAX 33000000 +#define NAU_PLL_REF_MIN 8000000 +#define NAU_PLL_OPTOP_MIN 6 + +static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 }; + +static const struct reg_default nau8822_reg_defaults[] = { + { NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 }, + { NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 }, + { NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 }, + { NAU8822_REG_AUDIO_INTERFACE, 0x0050 }, + { NAU8822_REG_COMPANDING_CONTROL, 0x0000 }, + { NAU8822_REG_CLOCKING, 0x0140 }, + { NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 }, + { NAU8822_REG_GPIO_CONTROL, 0x0000 }, + { NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 }, + { NAU8822_REG_DAC_CONTROL, 0x0000 }, + { NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff }, + { NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff }, + { NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 }, + { NAU8822_REG_ADC_CONTROL, 0x0100 }, + { NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff }, + { NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff }, + { NAU8822_REG_EQ1, 0x012c }, + { NAU8822_REG_EQ2, 0x002c }, + { NAU8822_REG_EQ3, 0x002c }, + { NAU8822_REG_EQ4, 0x002c }, + { NAU8822_REG_EQ5, 0x002c }, + { NAU8822_REG_DAC_LIMITER_1, 0x0032 }, + { NAU8822_REG_DAC_LIMITER_2, 0x0000 }, + { NAU8822_REG_NOTCH_FILTER_1, 0x0000 }, + { NAU8822_REG_NOTCH_FILTER_2, 0x0000 }, + { NAU8822_REG_NOTCH_FILTER_3, 0x0000 }, + { NAU8822_REG_NOTCH_FILTER_4, 0x0000 }, + { NAU8822_REG_ALC_CONTROL_1, 0x0038 }, + { NAU8822_REG_ALC_CONTROL_2, 0x000b }, + { NAU8822_REG_ALC_CONTROL_3, 0x0032 }, + { NAU8822_REG_NOISE_GATE, 0x0010 }, + { NAU8822_REG_PLL_N, 0x0008 }, + { NAU8822_REG_PLL_K1, 0x000c }, + { NAU8822_REG_PLL_K2, 0x0093 }, + { NAU8822_REG_PLL_K3, 0x00e9 }, + { NAU8822_REG_3D_CONTROL, 0x0000 }, + { NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 }, + { NAU8822_REG_INPUT_CONTROL, 0x0033 }, + { NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 }, + { NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 }, + { NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 }, + { NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 }, + { NAU8822_REG_OUTPUT_CONTROL, 0x0002 }, + { NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 }, + { NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 }, + { NAU8822_REG_LHP_VOLUME, 0x0039 }, + { NAU8822_REG_RHP_VOLUME, 0x0039 }, + { NAU8822_REG_LSPKOUT_VOLUME, 0x0039 }, + { NAU8822_REG_RSPKOUT_VOLUME, 0x0039 }, + { NAU8822_REG_AUX2_MIXER, 0x0001 }, + { NAU8822_REG_AUX1_MIXER, 0x0001 }, + { NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 }, + { NAU8822_REG_LEFT_TIME_SLOT, 0x0000 }, + { NAU8822_REG_MISC, 0x0020 }, + { NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 }, + { NAU8822_REG_DEVICE_REVISION, 0x007f }, + { NAU8822_REG_DEVICE_ID, 0x001a }, + { NAU8822_REG_DAC_DITHER, 0x0114 }, + { NAU8822_REG_ALC_ENHANCE_1, 0x0000 }, + { NAU8822_REG_ALC_ENHANCE_2, 0x0000 }, + { NAU8822_REG_192KHZ_SAMPLING, 0x0008 }, + { NAU8822_REG_MISC_CONTROL, 0x0000 }, + { NAU8822_REG_INPUT_TIEOFF, 0x0000 }, + { NAU8822_REG_POWER_REDUCTION, 0x0000 }, + { NAU8822_REG_AGC_PEAK2PEAK, 0x0000 }, + { NAU8822_REG_AGC_PEAK_DETECT, 0x0000 }, + { NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 }, + { NAU8822_REG_OUTPUT_TIEOFF, 0x0000 }, +}; + +static bool nau8822_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1: + case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME: + case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME: + case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5: + case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2: + case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4: + case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3: + case NAU8822_REG_3D_CONTROL: + case NAU8822_REG_RIGHT_SPEAKER_CONTROL: + case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL: + case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER: + case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID: + case NAU8822_REG_DAC_DITHER: + case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL: + case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF: + return true; + default: + return false; + } +} + +static bool nau8822_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1: + case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME: + case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME: + case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5: + case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2: + case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4: + case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3: + case NAU8822_REG_3D_CONTROL: + case NAU8822_REG_RIGHT_SPEAKER_CONTROL: + case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL: + case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER: + case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID: + case NAU8822_REG_DAC_DITHER: + case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL: + case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF: + return true; + default: + return false; + } +} + +static bool nau8822_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8822_REG_RESET: + case NAU8822_REG_DEVICE_REVISION: + case NAU8822_REG_DEVICE_ID: + case NAU8822_REG_AGC_PEAK2PEAK: + case NAU8822_REG_AGC_PEAK_DETECT: + case NAU8822_REG_AUTOMUTE_CONTROL: + return true; + default: + return false; + } +} + +/* The EQ parameters get function is to get the 5 band equalizer control. + * The regmap raw read can't work here because regmap doesn't provide + * value format for value width of 9 bits. Therefore, the driver reads data + * from cache and makes value format according to the endianness of + * bytes type control element. + */ +static int nau8822_eq_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct soc_bytes_ext *params = (void *)kcontrol->private_value; + int i, reg; + u16 reg_val, *val; + + val = (u16 *)ucontrol->value.bytes.data; + reg = NAU8822_REG_EQ1; + for (i = 0; i < params->max / sizeof(u16); i++) { + reg_val = snd_soc_component_read32(component, reg + i); + /* conversion of 16-bit integers between native CPU format + * and big endian format + */ + reg_val = cpu_to_be16(reg_val); + memcpy(val + i, &reg_val, sizeof(reg_val)); + } + + return 0; +} + +/* The EQ parameters put function is to make configuration of 5 band equalizer + * control. These configuration includes central frequency, equalizer gain, + * cut-off frequency, bandwidth control, and equalizer path. + * The regmap raw write can't work here because regmap doesn't provide + * register and value format for register with address 7 bits and value 9 bits. + * Therefore, the driver makes value format according to the endianness of + * bytes type control element and writes data to codec. + */ +static int nau8822_eq_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct soc_bytes_ext *params = (void *)kcontrol->private_value; + void *data; + u16 *val, value; + int i, reg, ret; + + data = kmemdup(ucontrol->value.bytes.data, + params->max, GFP_KERNEL | GFP_DMA); + if (!data) + return -ENOMEM; + + val = (u16 *)data; + reg = NAU8822_REG_EQ1; + for (i = 0; i < params->max / sizeof(u16); i++) { + /* conversion of 16-bit integers between native CPU format + * and big endian format + */ + value = be16_to_cpu(*(val + i)); + ret = snd_soc_component_write(component, reg + i, value); + if (ret) { + dev_err(component->dev, + "EQ configuration fail, register: %x ret: %d\n", + reg + i, ret); + kfree(data); + return ret; + } + } + kfree(data); + + return 0; +} + +static const char * const nau8822_companding[] = { + "Off", "NC", "u-law", "A-law"}; + +static const struct soc_enum nau8822_companding_adc_enum = + SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_ADCCM_SFT, + ARRAY_SIZE(nau8822_companding), nau8822_companding); + +static const struct soc_enum nau8822_companding_dac_enum = + SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_DACCM_SFT, + ARRAY_SIZE(nau8822_companding), nau8822_companding); + +static const char * const nau8822_eqmode[] = {"Capture", "Playback"}; + +static const struct soc_enum nau8822_eqmode_enum = + SOC_ENUM_SINGLE(NAU8822_REG_EQ1, NAU8822_EQM_SFT, + ARRAY_SIZE(nau8822_eqmode), nau8822_eqmode); + +static const char * const nau8822_alc1[] = {"Off", "Right", "Left", "Both"}; +static const char * const nau8822_alc3[] = {"Normal", "Limiter"}; + +static const struct soc_enum nau8822_alc_enable_enum = + SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_1, NAU8822_ALCEN_SFT, + ARRAY_SIZE(nau8822_alc1), nau8822_alc1); + +static const struct soc_enum nau8822_alc_mode_enum = + SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_3, NAU8822_ALCM_SFT, + ARRAY_SIZE(nau8822_alc3), nau8822_alc3); + +static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); +static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); +static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); +static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0); +static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1); +static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0); + +static const struct snd_kcontrol_new nau8822_snd_controls[] = { + SOC_ENUM("ADC Companding", nau8822_companding_adc_enum), + SOC_ENUM("DAC Companding", nau8822_companding_dac_enum), + + SOC_ENUM("EQ Function", nau8822_eqmode_enum), + SND_SOC_BYTES_EXT("EQ Parameters", 10, + nau8822_eq_get, nau8822_eq_put), + + SOC_DOUBLE("DAC Inversion Switch", + NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0), + SOC_DOUBLE_R_TLV("PCM Volume", + NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, + NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv), + + SOC_SINGLE("High Pass Filter Switch", + NAU8822_REG_ADC_CONTROL, 8, 1, 0), + SOC_SINGLE("High Pass Cut Off", + NAU8822_REG_ADC_CONTROL, 4, 7, 0), + + SOC_DOUBLE("ADC Inversion Switch", + NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0), + SOC_DOUBLE_R_TLV("ADC Volume", + NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, + NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv), + + SOC_SINGLE("DAC Limiter Switch", + NAU8822_REG_DAC_LIMITER_1, 8, 1, 0), + SOC_SINGLE("DAC Limiter Decay", + NAU8822_REG_DAC_LIMITER_1, 4, 15, 0), + SOC_SINGLE("DAC Limiter Attack", + NAU8822_REG_DAC_LIMITER_1, 0, 15, 0), + SOC_SINGLE("DAC Limiter Threshold", + NAU8822_REG_DAC_LIMITER_2, 4, 7, 0), + SOC_SINGLE_TLV("DAC Limiter Volume", + NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv), + + SOC_ENUM("ALC Mode", nau8822_alc_mode_enum), + SOC_ENUM("ALC Enable Switch", nau8822_alc_enable_enum), + SOC_SINGLE("ALC Min Gain", + NAU8822_REG_ALC_CONTROL_1, 0, 7, 0), + SOC_SINGLE("ALC Max Gain", + NAU8822_REG_ALC_CONTROL_1, 3, 7, 0), + SOC_SINGLE("ALC Hold", + NAU8822_REG_ALC_CONTROL_2, 4, 10, 0), + SOC_SINGLE("ALC Target", + NAU8822_REG_ALC_CONTROL_2, 0, 15, 0), + SOC_SINGLE("ALC Decay", + NAU8822_REG_ALC_CONTROL_3, 4, 10, 0), + SOC_SINGLE("ALC Attack", + NAU8822_REG_ALC_CONTROL_3, 0, 10, 0), + SOC_SINGLE("ALC Noise Gate Switch", + NAU8822_REG_NOISE_GATE, 3, 1, 0), + SOC_SINGLE("ALC Noise Gate Threshold", + NAU8822_REG_NOISE_GATE, 0, 7, 0), + + SOC_DOUBLE_R("PGA ZC Switch", + NAU8822_REG_LEFT_INP_PGA_CONTROL, + NAU8822_REG_RIGHT_INP_PGA_CONTROL, + 7, 1, 0), + SOC_DOUBLE_R_TLV("PGA Volume", + NAU8822_REG_LEFT_INP_PGA_CONTROL, + NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0, 63, 0, inpga_tlv), + + SOC_DOUBLE_R("Headphone ZC Switch", + NAU8822_REG_LHP_VOLUME, + NAU8822_REG_RHP_VOLUME, 7, 1, 0), + SOC_DOUBLE_R("Headphone Playback Switch", + NAU8822_REG_LHP_VOLUME, + NAU8822_REG_RHP_VOLUME, 6, 1, 1), + SOC_DOUBLE_R_TLV("Headphone Volume", + NAU8822_REG_LHP_VOLUME, + NAU8822_REG_RHP_VOLUME, 0, 63, 0, spk_tlv), + + SOC_DOUBLE_R("Speaker ZC Switch", + NAU8822_REG_LSPKOUT_VOLUME, + NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0), + SOC_DOUBLE_R("Speaker Playback Switch", + NAU8822_REG_LSPKOUT_VOLUME, + NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1), + SOC_DOUBLE_R_TLV("Speaker Volume", + NAU8822_REG_LSPKOUT_VOLUME, + NAU8822_REG_RSPKOUT_VOLUME, 0, 63, 0, spk_tlv), + + SOC_DOUBLE_R("AUXOUT Playback Switch", + NAU8822_REG_AUX2_MIXER, + NAU8822_REG_AUX1_MIXER, 6, 1, 1), + + SOC_DOUBLE_R_TLV("PGA Boost Volume", + NAU8822_REG_LEFT_ADC_BOOST_CONTROL, + NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 8, 1, 0, pga_boost_tlv), + SOC_DOUBLE_R_TLV("L2/R2 Boost Volume", + NAU8822_REG_LEFT_ADC_BOOST_CONTROL, + NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 4, 7, 0, boost_tlv), + SOC_DOUBLE_R_TLV("Aux Boost Volume", + NAU8822_REG_LEFT_ADC_BOOST_CONTROL, + NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0, 7, 0, boost_tlv), + + SOC_SINGLE("DAC 128x Oversampling Switch", + NAU8822_REG_DAC_CONTROL, 5, 1, 0), + SOC_SINGLE("ADC 128x Oversampling Switch", + NAU8822_REG_ADC_CONTROL, 5, 1, 0), +}; + +/* LMAIN and RMAIN Mixer */ +static const struct snd_kcontrol_new nau8822_left_out_mixer[] = { + SOC_DAPM_SINGLE("LINMIX Switch", + NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0), + SOC_DAPM_SINGLE("LAUX Switch", + NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0), + SOC_DAPM_SINGLE("LDAC Switch", + NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0), + SOC_DAPM_SINGLE("RDAC Switch", + NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0), +}; + +static const struct snd_kcontrol_new nau8822_right_out_mixer[] = { + SOC_DAPM_SINGLE("RINMIX Switch", + NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0), + SOC_DAPM_SINGLE("RAUX Switch", + NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0), + SOC_DAPM_SINGLE("RDAC Switch", + NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0), + SOC_DAPM_SINGLE("LDAC Switch", + NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0), +}; + +/* AUX1 and AUX2 Mixer */ +static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = { + SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0), + SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0), + SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0), + SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0), + SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0), +}; + +static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = { + SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0), + SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0), + SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0), + SOC_DAPM_SINGLE("AUX1MIX Output Switch", + NAU8822_REG_AUX2_MIXER, 3, 1, 0), +}; + +/* Input PGA */ +static const struct snd_kcontrol_new nau8822_left_input_mixer[] = { + SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0), + SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0), + SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0), +}; +static const struct snd_kcontrol_new nau8822_right_input_mixer[] = { + SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0), + SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0), + SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0), +}; + +/* Loopback Switch */ +static const struct snd_kcontrol_new nau8822_loopback = + SOC_DAPM_SINGLE("Switch", NAU8822_REG_COMPANDING_CONTROL, + NAU8822_ADDAP_SFT, 1, 0); + +static int check_mclk_select_pll(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(source->dapm); + unsigned int value; + + value = snd_soc_component_read32(component, NAU8822_REG_CLOCKING); + + return (value & NAU8822_CLKM_MASK); +} + +static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = { + SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", + NAU8822_REG_POWER_MANAGEMENT_3, 0, 0), + SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", + NAU8822_REG_POWER_MANAGEMENT_3, 1, 0), + SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", + NAU8822_REG_POWER_MANAGEMENT_2, 0, 0), + SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", + NAU8822_REG_POWER_MANAGEMENT_2, 1, 0), + + SOC_MIXER_ARRAY("Left Output Mixer", + NAU8822_REG_POWER_MANAGEMENT_3, 2, 0, nau8822_left_out_mixer), + SOC_MIXER_ARRAY("Right Output Mixer", + NAU8822_REG_POWER_MANAGEMENT_3, 3, 0, nau8822_right_out_mixer), + SOC_MIXER_ARRAY("AUX1 Output Mixer", + NAU8822_REG_POWER_MANAGEMENT_1, 7, 0, nau8822_auxout1_mixer), + SOC_MIXER_ARRAY("AUX2 Output Mixer", + NAU8822_REG_POWER_MANAGEMENT_1, 6, 0, nau8822_auxout2_mixer), + + SOC_MIXER_ARRAY("Left Input Mixer", + NAU8822_REG_POWER_MANAGEMENT_2, + 2, 0, nau8822_left_input_mixer), + SOC_MIXER_ARRAY("Right Input Mixer", + NAU8822_REG_POWER_MANAGEMENT_2, + 3, 0, nau8822_right_input_mixer), + + SND_SOC_DAPM_PGA("Left Boost Mixer", + NAU8822_REG_POWER_MANAGEMENT_2, 4, 0, NULL, 0), + SND_SOC_DAPM_PGA("Right Boost Mixer", + NAU8822_REG_POWER_MANAGEMENT_2, 5, 0, NULL, 0), + + SND_SOC_DAPM_PGA("Left Capture PGA", + NAU8822_REG_LEFT_INP_PGA_CONTROL, 6, 1, NULL, 0), + SND_SOC_DAPM_PGA("Right Capture PGA", + NAU8822_REG_RIGHT_INP_PGA_CONTROL, 6, 1, NULL, 0), + + SND_SOC_DAPM_PGA("Left Headphone Out", + NAU8822_REG_POWER_MANAGEMENT_2, 7, 0, NULL, 0), + SND_SOC_DAPM_PGA("Right Headphone Out", + NAU8822_REG_POWER_MANAGEMENT_2, 8, 0, NULL, 0), + + SND_SOC_DAPM_PGA("Left Speaker Out", + NAU8822_REG_POWER_MANAGEMENT_3, 6, 0, NULL, 0), + SND_SOC_DAPM_PGA("Right Speaker Out", + NAU8822_REG_POWER_MANAGEMENT_3, 5, 0, NULL, 0), + + SND_SOC_DAPM_PGA("AUX1 Out", + NAU8822_REG_POWER_MANAGEMENT_3, 8, 0, NULL, 0), + SND_SOC_DAPM_PGA("AUX2 Out", + NAU8822_REG_POWER_MANAGEMENT_3, 7, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("Mic Bias", + NAU8822_REG_POWER_MANAGEMENT_1, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PLL", + NAU8822_REG_POWER_MANAGEMENT_1, 5, 0, NULL, 0), + + SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0, + &nau8822_loopback), + + SND_SOC_DAPM_INPUT("LMICN"), + SND_SOC_DAPM_INPUT("LMICP"), + SND_SOC_DAPM_INPUT("RMICN"), + SND_SOC_DAPM_INPUT("RMICP"), + SND_SOC_DAPM_INPUT("LAUX"), + SND_SOC_DAPM_INPUT("RAUX"), + SND_SOC_DAPM_INPUT("L2"), + SND_SOC_DAPM_INPUT("R2"), + SND_SOC_DAPM_OUTPUT("LHP"), + SND_SOC_DAPM_OUTPUT("RHP"), + SND_SOC_DAPM_OUTPUT("LSPK"), + SND_SOC_DAPM_OUTPUT("RSPK"), + SND_SOC_DAPM_OUTPUT("AUXOUT1"), + SND_SOC_DAPM_OUTPUT("AUXOUT2"), +}; + +static const struct snd_soc_dapm_route nau8822_dapm_routes[] = { + {"Right DAC", NULL, "PLL", check_mclk_select_pll}, + {"Left DAC", NULL, "PLL", check_mclk_select_pll}, + + /* LMAIN and RMAIN Mixer */ + {"Right Output Mixer", "LDAC Switch", "Left DAC"}, + {"Right Output Mixer", "RDAC Switch", "Right DAC"}, + {"Right Output Mixer", "RAUX Switch", "RAUX"}, + {"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"}, + + {"Left Output Mixer", "LDAC Switch", "Left DAC"}, + {"Left Output Mixer", "RDAC Switch", "Right DAC"}, + {"Left Output Mixer", "LAUX Switch", "LAUX"}, + {"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"}, + + /* AUX1 and AUX2 Mixer */ + {"AUX1 Output Mixer", "RDAC Switch", "Right DAC"}, + {"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"}, + {"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"}, + {"AUX1 Output Mixer", "LDAC Switch", "Left DAC"}, + {"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"}, + + {"AUX2 Output Mixer", "LDAC Switch", "Left DAC"}, + {"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"}, + {"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"}, + {"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"}, + + /* Outputs */ + {"Right Headphone Out", NULL, "Right Output Mixer"}, + {"RHP", NULL, "Right Headphone Out"}, + + {"Left Headphone Out", NULL, "Left Output Mixer"}, + {"LHP", NULL, "Left Headphone Out"}, + + {"Right Speaker Out", NULL, "Right Output Mixer"}, + {"RSPK", NULL, "Right Speaker Out"}, + + {"Left Speaker Out", NULL, "Left Output Mixer"}, + {"LSPK", NULL, "Left Speaker Out"}, + + {"AUX1 Out", NULL, "AUX1 Output Mixer"}, + {"AUX2 Out", NULL, "AUX2 Output Mixer"}, + {"AUXOUT1", NULL, "AUX1 Out"}, + {"AUXOUT2", NULL, "AUX2 Out"}, + + /* Boost Mixer */ + {"Right ADC", NULL, "PLL", check_mclk_select_pll}, + {"Left ADC", NULL, "PLL", check_mclk_select_pll}, + + {"Right ADC", NULL, "Right Boost Mixer"}, + + {"Right Boost Mixer", NULL, "RAUX"}, + {"Right Boost Mixer", NULL, "Right Capture PGA"}, + {"Right Boost Mixer", NULL, "R2"}, + + {"Left ADC", NULL, "Left Boost Mixer"}, + + {"Left Boost Mixer", NULL, "LAUX"}, + {"Left Boost Mixer", NULL, "Left Capture PGA"}, + {"Left Boost Mixer", NULL, "L2"}, + + /* Input PGA */ + {"Right Capture PGA", NULL, "Right Input Mixer"}, + {"Left Capture PGA", NULL, "Left Input Mixer"}, + + /* Enable Microphone Power */ + {"Right Capture PGA", NULL, "Mic Bias"}, + {"Left Capture PGA", NULL, "Mic Bias"}, + + {"Right Input Mixer", "R2 Switch", "R2"}, + {"Right Input Mixer", "MicN Switch", "RMICN"}, + {"Right Input Mixer", "MicP Switch", "RMICP"}, + + {"Left Input Mixer", "L2 Switch", "L2"}, + {"Left Input Mixer", "MicN Switch", "LMICN"}, + {"Left Input Mixer", "MicP Switch", "LMICP"}, + + /* Digital Loopback */ + {"Digital Loopback", "Switch", "Left ADC"}, + {"Digital Loopback", "Switch", "Right ADC"}, + {"Left DAC", NULL, "Digital Loopback"}, + {"Right DAC", NULL, "Digital Loopback"}, +}; + +static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct snd_soc_component *component = dai->component; + struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); + + nau8822->div_id = clk_id; + nau8822->sysclk = freq; + dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq, + clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK"); + + return 0; +} + +static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs, + struct nau8822_pll *pll_param) +{ + u64 f2, f2_max, pll_ratio; + int i, scal_sel; + + if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN) + return -EINVAL; + f2_max = 0; + scal_sel = ARRAY_SIZE(nau8822_mclk_scaler); + + for (i = 0; i < scal_sel; i++) { + f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10; + if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX && + f2_max < f2) { + f2_max = f2; + scal_sel = i; + } + } + + if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel) + return -EINVAL; + pll_param->mclk_scaler = scal_sel; + f2 = f2_max; + + /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional + * input; round up the 24+4bit. + */ + pll_ratio = div_u64(f2 << 28, pll_in); + pll_param->pre_factor = 0; + if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) { + pll_ratio <<= 1; + pll_param->pre_factor = 1; + } + pll_param->pll_int = (pll_ratio >> 28) & 0xF; + pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4); + + return 0; +} + +static int nau8822_config_clkdiv(struct snd_soc_dai *dai, int div, int rate) +{ + struct snd_soc_component *component = dai->component; + struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); + struct nau8822_pll *pll = &nau8822->pll; + int i, sclk, imclk; + + switch (nau8822->div_id) { + case NAU8822_CLK_MCLK: + /* Configure the master clock prescaler div to make system + * clock to approximate the internal master clock (IMCLK); + * and large or equal to IMCLK. + */ + div = 0; + imclk = rate * 256; + for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) { + sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i]; + if (sclk < imclk) + break; + div = i; + } + dev_dbg(component->dev, "master clock prescaler %x for fs %d\n", + div, rate); + + /* master clock from MCLK and disable PLL */ + snd_soc_component_update_bits(component, + NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK, + (div << NAU8822_MCLKSEL_SFT)); + snd_soc_component_update_bits(component, + NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, + NAU8822_CLKM_MCLK); + break; + + case NAU8822_CLK_PLL: + /* master clock from PLL and enable PLL */ + if (pll->mclk_scaler != div) { + dev_err(component->dev, + "master clock prescaler not meet PLL parameters\n"); + return -EINVAL; + } + snd_soc_component_update_bits(component, + NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK, + (div << NAU8822_MCLKSEL_SFT)); + snd_soc_component_update_bits(component, + NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, + NAU8822_CLKM_PLL); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int nau8822_set_pll(struct snd_soc_dai *dai, int pll_id, int source, + unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_component *component = dai->component; + struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); + struct nau8822_pll *pll_param = &nau8822->pll; + int ret, fs; + + fs = freq_out / 256; + + ret = nau8822_calc_pll(freq_in, fs, pll_param); + if (ret < 0) { + dev_err(component->dev, "Unsupported input clock %d\n", + freq_in); + return ret; + } + + dev_info(component->dev, + "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n", + pll_param->pll_int, pll_param->pll_frac, + pll_param->mclk_scaler, pll_param->pre_factor); + + snd_soc_component_update_bits(component, + NAU8822_REG_PLL_N, NAU8822_PLLMCLK_DIV2 | NAU8822_PLLN_MASK, + (pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) | + pll_param->pll_int); + snd_soc_component_write(component, + NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) & + NAU8822_PLLK1_MASK); + snd_soc_component_write(component, + NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) & + NAU8822_PLLK2_MASK); + snd_soc_component_write(component, + NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK); + snd_soc_component_update_bits(component, + NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK, + pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT); + snd_soc_component_update_bits(component, + NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, NAU8822_CLKM_PLL); + + return 0; +} + +static int nau8822_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + u16 ctrl1_val = 0, ctrl2_val = 0; + + dev_dbg(component->dev, "%s\n", __func__); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + ctrl2_val |= 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + ctrl2_val &= ~1; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + ctrl1_val |= 0x10; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + ctrl1_val |= 0x8; + break; + case SND_SOC_DAIFMT_DSP_A: + ctrl1_val |= 0x18; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + ctrl1_val |= 0x180; + break; + case SND_SOC_DAIFMT_IB_NF: + ctrl1_val |= 0x100; + break; + case SND_SOC_DAIFMT_NB_IF: + ctrl1_val |= 0x80; + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, + NAU8822_REG_AUDIO_INTERFACE, + NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK, + ctrl1_val); + snd_soc_component_update_bits(component, + NAU8822_REG_CLOCKING, NAU8822_CLKIOEN_MASK, ctrl2_val); + + return 0; +} + +static int nau8822_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); + int val_len = 0, val_rate = 0; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + val_len |= NAU8822_WLEN_20; + break; + case SNDRV_PCM_FORMAT_S24_LE: + val_len |= NAU8822_WLEN_24; + break; + case SNDRV_PCM_FORMAT_S32_LE: + val_len |= NAU8822_WLEN_32; + break; + default: + return -EINVAL; + } + + switch (params_rate(params)) { + case 8000: + val_rate |= NAU8822_SMPLR_8K; + break; + case 11025: + val_rate |= NAU8822_SMPLR_12K; + break; + case 16000: + val_rate |= NAU8822_SMPLR_16K; + break; + case 22050: + val_rate |= NAU8822_SMPLR_24K; + break; + case 32000: + val_rate |= NAU8822_SMPLR_32K; + break; + case 44100: + case 48000: + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, + NAU8822_REG_AUDIO_INTERFACE, NAU8822_WLEN_MASK, val_len); + snd_soc_component_update_bits(component, + NAU8822_REG_ADDITIONAL_CONTROL, NAU8822_SMPLR_MASK, val_rate); + + /* If the master clock is from MCLK, provide the runtime FS for driver + * to get the master clock prescaler configuration. + */ + if (nau8822->div_id == NAU8822_CLK_MCLK) + nau8822_config_clkdiv(dai, 0, params_rate(params)); + + return 0; +} + +static int nau8822_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_component *component = dai->component; + + dev_dbg(component->dev, "%s: %d\n", __func__, mute); + + if (mute) + snd_soc_component_update_bits(component, + NAU8822_REG_DAC_CONTROL, 0x40, 0x40); + else + snd_soc_component_update_bits(component, + NAU8822_REG_DAC_CONTROL, 0x40, 0); + + return 0; +} + +static int nau8822_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + snd_soc_component_update_bits(component, + NAU8822_REG_POWER_MANAGEMENT_1, + NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K); + break; + + case SND_SOC_BIAS_STANDBY: + snd_soc_component_update_bits(component, + NAU8822_REG_POWER_MANAGEMENT_1, + NAU8822_IOBUF_EN | NAU8822_ABIAS_EN, + NAU8822_IOBUF_EN | NAU8822_ABIAS_EN); + + if (snd_soc_component_get_bias_level(component) == + SND_SOC_BIAS_OFF) { + snd_soc_component_update_bits(component, + NAU8822_REG_POWER_MANAGEMENT_1, + NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K); + mdelay(100); + } + snd_soc_component_update_bits(component, + NAU8822_REG_POWER_MANAGEMENT_1, + NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K); + break; + + case SND_SOC_BIAS_OFF: + snd_soc_component_write(component, + NAU8822_REG_POWER_MANAGEMENT_1, 0); + snd_soc_component_write(component, + NAU8822_REG_POWER_MANAGEMENT_2, 0); + snd_soc_component_write(component, + NAU8822_REG_POWER_MANAGEMENT_3, 0); + break; + } + + dev_dbg(component->dev, "%s: %d\n", __func__, level); + + return 0; +} + +#define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000) + +#define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dai_ops nau8822_dai_ops = { + .hw_params = nau8822_hw_params, + .digital_mute = nau8822_mute, + .set_fmt = nau8822_set_dai_fmt, + .set_sysclk = nau8822_set_dai_sysclk, + .set_pll = nau8822_set_pll, +}; + +static struct snd_soc_dai_driver nau8822_dai = { + .name = "nau8822-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = NAU8822_RATES, + .formats = NAU8822_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = NAU8822_RATES, + .formats = NAU8822_FORMATS, + }, + .ops = &nau8822_dai_ops, + .symmetric_rates = 1, +}; + +static int nau8822_suspend(struct snd_soc_component *component) +{ + struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); + + snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); + + regcache_mark_dirty(nau8822->regmap); + + return 0; +} + +static int nau8822_resume(struct snd_soc_component *component) +{ + struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); + + regcache_sync(nau8822->regmap); + + snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY); + + return 0; +} + +/* + * These registers contain an "update" bit - bit 8. This means, for example, + * that one can write new DAC digital volume for both channels, but only when + * the update bit is set, will also the volume be updated - simultaneously for + * both channels. + */ +static const int update_reg[] = { + NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, + NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, + NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, + NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, + NAU8822_REG_LEFT_INP_PGA_CONTROL, + NAU8822_REG_RIGHT_INP_PGA_CONTROL, + NAU8822_REG_LHP_VOLUME, + NAU8822_REG_RHP_VOLUME, + NAU8822_REG_LSPKOUT_VOLUME, + NAU8822_REG_RSPKOUT_VOLUME, +}; + +static int nau8822_probe(struct snd_soc_component *component) +{ + int i; + + /* + * Set the update bit in all registers, that have one. This way all + * writes to those registers will also cause the update bit to be + * written. + */ + for (i = 0; i < ARRAY_SIZE(update_reg); i++) + snd_soc_component_update_bits(component, + update_reg[i], 0x100, 0x100); + + return 0; +} + +static const struct snd_soc_component_driver soc_component_dev_nau8822 = { + .probe = nau8822_probe, + .suspend = nau8822_suspend, + .resume = nau8822_resume, + .set_bias_level = nau8822_set_bias_level, + .controls = nau8822_snd_controls, + .num_controls = ARRAY_SIZE(nau8822_snd_controls), + .dapm_widgets = nau8822_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(nau8822_dapm_widgets), + .dapm_routes = nau8822_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(nau8822_dapm_routes), + .idle_bias_on = 1, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, +}; + +static const struct regmap_config nau8822_regmap_config = { + .reg_bits = 7, + .val_bits = 9, + + .max_register = NAU8822_REG_MAX_REGISTER, + .volatile_reg = nau8822_volatile, + + .readable_reg = nau8822_readable_reg, + .writeable_reg = nau8822_writeable_reg, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = nau8822_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults), +}; + +static int nau8822_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct device *dev = &i2c->dev; + struct nau8822 *nau8822 = dev_get_platdata(dev); + int ret; + + if (!nau8822) { + nau8822 = devm_kzalloc(dev, sizeof(*nau8822), GFP_KERNEL); + if (nau8822 == NULL) + return -ENOMEM; + } + i2c_set_clientdata(i2c, nau8822); + + nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config); + if (IS_ERR(nau8822->regmap)) { + ret = PTR_ERR(nau8822->regmap); + dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); + return ret; + } + nau8822->dev = dev; + + /* Reset the codec */ + ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00); + if (ret != 0) { + dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); + return ret; + } + + ret = devm_snd_soc_register_component(dev, &soc_component_dev_nau8822, + &nau8822_dai, 1); + if (ret != 0) { + dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct i2c_device_id nau8822_i2c_id[] = { + { "nau8822", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id); + +#ifdef CONFIG_OF +static const struct of_device_id nau8822_of_match[] = { + { .compatible = "nuvoton,nau8822", }, + { } +}; +MODULE_DEVICE_TABLE(of, nau8822_of_match); +#endif + +static struct i2c_driver nau8822_i2c_driver = { + .driver = { + .name = "nau8822", + .of_match_table = of_match_ptr(nau8822_of_match), + }, + .probe = nau8822_i2c_probe, + .id_table = nau8822_i2c_id, +}; +module_i2c_driver(nau8822_i2c_driver); + +MODULE_DESCRIPTION("ASoC NAU8822 codec driver"); +MODULE_AUTHOR("David Lin <ctlin0(a)nuvoton.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/nau8822.h b/sound/soc/codecs/nau8822.h new file mode 100644 index 000000000000..aa79c969cd44 --- /dev/null +++ b/sound/soc/codecs/nau8822.h @@ -0,0 +1,204 @@ +/* + * nau8822.h -- NAU8822 Soc Audio Codec driver + * + * Author: David Lin <ctlin0(a)nuvoton.com> + * Co-author: John Hsu <kchsu0(a)nuvoton.com> + * Co-author: Seven Li <wtli(a)nuvoton.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __NAU8822_H__ +#define __NAU8822_H__ + +#define NAU8822_REG_RESET 0x00 +#define NAU8822_REG_POWER_MANAGEMENT_1 0x01 +#define NAU8822_REG_POWER_MANAGEMENT_2 0x02 +#define NAU8822_REG_POWER_MANAGEMENT_3 0x03 +#define NAU8822_REG_AUDIO_INTERFACE 0x04 +#define NAU8822_REG_COMPANDING_CONTROL 0x05 +#define NAU8822_REG_CLOCKING 0x06 +#define NAU8822_REG_ADDITIONAL_CONTROL 0x07 +#define NAU8822_REG_GPIO_CONTROL 0x08 +#define NAU8822_REG_JACK_DETECT_CONTROL_1 0x09 +#define NAU8822_REG_DAC_CONTROL 0x0A +#define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME 0x0B +#define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME 0x0C +#define NAU8822_REG_JACK_DETECT_CONTROL_2 0x0D +#define NAU8822_REG_ADC_CONTROL 0x0E +#define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME 0x0F +#define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME 0x10 +#define NAU8822_REG_EQ1 0x12 +#define NAU8822_REG_EQ2 0x13 +#define NAU8822_REG_EQ3 0x14 +#define NAU8822_REG_EQ4 0x15 +#define NAU8822_REG_EQ5 0x16 +#define NAU8822_REG_DAC_LIMITER_1 0x18 +#define NAU8822_REG_DAC_LIMITER_2 0x19 +#define NAU8822_REG_NOTCH_FILTER_1 0x1B +#define NAU8822_REG_NOTCH_FILTER_2 0x1C +#define NAU8822_REG_NOTCH_FILTER_3 0x1D +#define NAU8822_REG_NOTCH_FILTER_4 0x1E +#define NAU8822_REG_ALC_CONTROL_1 0x20 +#define NAU8822_REG_ALC_CONTROL_2 0x21 +#define NAU8822_REG_ALC_CONTROL_3 0x22 +#define NAU8822_REG_NOISE_GATE 0x23 +#define NAU8822_REG_PLL_N 0x24 +#define NAU8822_REG_PLL_K1 0x25 +#define NAU8822_REG_PLL_K2 0x26 +#define NAU8822_REG_PLL_K3 0x27 +#define NAU8822_REG_3D_CONTROL 0x29 +#define NAU8822_REG_RIGHT_SPEAKER_CONTROL 0x2B +#define NAU8822_REG_INPUT_CONTROL 0x2C +#define NAU8822_REG_LEFT_INP_PGA_CONTROL 0x2D +#define NAU8822_REG_RIGHT_INP_PGA_CONTROL 0x2E +#define NAU8822_REG_LEFT_ADC_BOOST_CONTROL 0x2F +#define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL 0x30 +#define NAU8822_REG_OUTPUT_CONTROL 0x31 +#define NAU8822_REG_LEFT_MIXER_CONTROL 0x32 +#define NAU8822_REG_RIGHT_MIXER_CONTROL 0x33 +#define NAU8822_REG_LHP_VOLUME 0x34 +#define NAU8822_REG_RHP_VOLUME 0x35 +#define NAU8822_REG_LSPKOUT_VOLUME 0x36 +#define NAU8822_REG_RSPKOUT_VOLUME 0x37 +#define NAU8822_REG_AUX2_MIXER 0x38 +#define NAU8822_REG_AUX1_MIXER 0x39 +#define NAU8822_REG_POWER_MANAGEMENT_4 0x3A +#define NAU8822_REG_LEFT_TIME_SLOT 0x3B +#define NAU8822_REG_MISC 0x3C +#define NAU8822_REG_RIGHT_TIME_SLOT 0x3D +#define NAU8822_REG_DEVICE_REVISION 0x3E +#define NAU8822_REG_DEVICE_ID 0x3F +#define NAU8822_REG_DAC_DITHER 0x41 +#define NAU8822_REG_ALC_ENHANCE_1 0x46 +#define NAU8822_REG_ALC_ENHANCE_2 0x47 +#define NAU8822_REG_192KHZ_SAMPLING 0x48 +#define NAU8822_REG_MISC_CONTROL 0x49 +#define NAU8822_REG_INPUT_TIEOFF 0x4A +#define NAU8822_REG_POWER_REDUCTION 0x4B +#define NAU8822_REG_AGC_PEAK2PEAK 0x4C +#define NAU8822_REG_AGC_PEAK_DETECT 0x4D +#define NAU8822_REG_AUTOMUTE_CONTROL 0x4E +#define NAU8822_REG_OUTPUT_TIEOFF 0x4F +#define NAU8822_REG_MAX_REGISTER NAU8822_REG_OUTPUT_TIEOFF + +/* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */ +#define NAU8822_REFIMP_MASK 0x3 +#define NAU8822_REFIMP_80K 0x1 +#define NAU8822_REFIMP_300K 0x2 +#define NAU8822_REFIMP_3K 0x3 +#define NAU8822_IOBUF_EN (0x1 << 2) +#define NAU8822_ABIAS_EN (0x1 << 3) + +/* NAU8822_REG_AUDIO_INTERFACE (0x4) */ +#define NAU8822_AIFMT_MASK (0x3 << 3) +#define NAU8822_WLEN_MASK (0x3 << 5) +#define NAU8822_WLEN_20 (0x1 << 5) +#define NAU8822_WLEN_24 (0x2 << 5) +#define NAU8822_WLEN_32 (0x3 << 5) +#define NAU8822_LRP_MASK (0x1 << 7) +#define NAU8822_BCLKP_MASK (0x1 << 8) + +/* NAU8822_REG_COMPANDING_CONTROL (0x5) */ +#define NAU8822_ADDAP_SFT 0 +#define NAU8822_ADCCM_SFT 1 +#define NAU8822_DACCM_SFT 3 + +/* NAU8822_REG_CLOCKING (0x6) */ +#define NAU8822_CLKIOEN_MASK 0x1 +#define NAU8822_MCLKSEL_SFT 5 +#define NAU8822_MCLKSEL_MASK (0x7 << 5) +#define NAU8822_BCLKSEL_SFT 2 +#define NAU8822_BCLKSEL_MASK (0x7 << 2) +#define NAU8822_CLKM_MASK (0x1 << 8) +#define NAU8822_CLKM_MCLK (0x0 << 8) +#define NAU8822_CLKM_PLL (0x1 << 8) + +/* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */ +#define NAU8822_SMPLR_SFT 1 +#define NAU8822_SMPLR_MASK (0x7 << 1) +#define NAU8822_SMPLR_48K (0x0 << 1) +#define NAU8822_SMPLR_32K (0x1 << 1) +#define NAU8822_SMPLR_24K (0x2 << 1) +#define NAU8822_SMPLR_16K (0x3 << 1) +#define NAU8822_SMPLR_12K (0x4 << 1) +#define NAU8822_SMPLR_8K (0x5 << 1) + +/* NAU8822_REG_EQ1 (0x12) */ +#define NAU8822_EQ1GC_SFT 0 +#define NAU8822_EQ1CF_SFT 5 +#define NAU8822_EQM_SFT 8 + +/* NAU8822_REG_EQ2 (0x13) */ +#define NAU8822_EQ2GC_SFT 0 +#define NAU8822_EQ2CF_SFT 5 +#define NAU8822_EQ2BW_SFT 8 + +/* NAU8822_REG_EQ3 (0x14) */ +#define NAU8822_EQ3GC_SFT 0 +#define NAU8822_EQ3CF_SFT 5 +#define NAU8822_EQ3BW_SFT 8 + +/* NAU8822_REG_EQ4 (0x15) */ +#define NAU8822_EQ4GC_SFT 0 +#define NAU8822_EQ4CF_SFT 5 +#define NAU8822_EQ4BW_SFT 8 + +/* NAU8822_REG_EQ5 (0x16) */ +#define NAU8822_EQ5GC_SFT 0 +#define NAU8822_EQ5CF_SFT 5 + +/* NAU8822_REG_ALC_CONTROL_1 (0x20) */ +#define NAU8822_ALCMINGAIN_SFT 0 +#define NAU8822_ALCMXGAIN_SFT 3 +#define NAU8822_ALCEN_SFT 7 + +/* NAU8822_REG_ALC_CONTROL_2 (0x21) */ +#define NAU8822_ALCSL_SFT 0 +#define NAU8822_ALCHT_SFT 4 + +/* NAU8822_REG_ALC_CONTROL_3 (0x22) */ +#define NAU8822_ALCATK_SFT 0 +#define NAU8822_ALCDCY_SFT 4 +#define NAU8822_ALCM_SFT 8 + +/* NAU8822_REG_PLL_N (0x24) */ +#define NAU8822_PLLMCLK_DIV2 (0x1 << 4) +#define NAU8822_PLLN_MASK 0xF + +#define NAU8822_PLLK1_SFT 18 +#define NAU8822_PLLK1_MASK 0x3F + +/* NAU8822_REG_PLL_K2 (0x26) */ +#define NAU8822_PLLK2_SFT 9 +#define NAU8822_PLLK2_MASK 0x1FF + +/* NAU8822_REG_PLL_K3 (0x27) */ +#define NAU8822_PLLK3_MASK 0x1FF + +/* System Clock Source */ +enum { + NAU8822_CLK_MCLK, + NAU8822_CLK_PLL, +}; + +struct nau8822_pll { + int pre_factor; + int mclk_scaler; + int pll_frac; + int pll_int; +}; + +/* Codec Private Data */ +struct nau8822 { + struct device *dev; + struct regmap *regmap; + int mclk_idx; + struct nau8822_pll pll; + int sysclk; + int div_id; +}; + +#endif /* __NAU8822_H__ */ -- 2.18.0

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[alsa-devel] Applied "ASoC: sta32x: Add support for XTI clock" to the asoc tree
by Mark Brown 19 Oct '18

19 Oct '18

The patch ASoC: sta32x: Add support for XTI clock has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From fce9ec954a8af7e04cbf5b9daa8bec9c1df5cfe6 Mon Sep 17 00:00:00 2001 From: Daniel Mack <daniel(a)zonque.org> Date: Wed, 17 Oct 2018 13:37:03 +0200 Subject: [PATCH] ASoC: sta32x: Add support for XTI clock The STA32x chips feature an XTI clock input that needs to be stable before the reset signal is released. Therefore, the chip driver needs to get a handle to the clock. Instead of relying on other parts of the system to enable the clock, let the codec driver grab a handle itself. In order to keep existing boards working, clock support is made optional. Signed-off-by: Daniel Mack <daniel(a)zonque.org> Signed-off-by: Mark Brown <broonie(a)kernel.org> --- .../devicetree/bindings/sound/st,sta32x.txt | 6 ++++ sound/soc/codecs/sta32x.c | 28 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/st,sta32x.txt b/Documentation/devicetree/bindings/sound/st,sta32x.txt index ff4a685a4303..52265fb757c5 100644 --- a/Documentation/devicetree/bindings/sound/st,sta32x.txt +++ b/Documentation/devicetree/bindings/sound/st,sta32x.txt @@ -19,6 +19,10 @@ Required properties: Optional properties: + - clocks, clock-names: Clock specifier for XTI input clock. + If specified, the clock will be enabled when the codec is probed, + and disabled when it is removed. The 'clock-names' must be set to 'xti'. + - st,output-conf: number, Selects the output configuration: 0: 2-channel (full-bridge) power, 2-channel data-out 1: 2 (half-bridge). 1 (full-bridge) on-board power @@ -79,6 +83,8 @@ Example: codec: sta32x@38 { compatible = "st,sta32x"; reg = <0x1c>; + clocks = <&clock>; + clock-names = "xti"; reset-gpios = <&gpio1 19 0>; power-down-gpios = <&gpio1 16 0>; st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel diff --git a/sound/soc/codecs/sta32x.c b/sound/soc/codecs/sta32x.c index 22de1593443c..f753d2db0a5a 100644 --- a/sound/soc/codecs/sta32x.c +++ b/sound/soc/codecs/sta32x.c @@ -21,6 +21,7 @@ #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/init.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/pm.h> #include <linux/i2c.h> @@ -142,6 +143,7 @@ static const char *sta32x_supply_names[] = { /* codec private data */ struct sta32x_priv { struct regmap *regmap; + struct clk *xti_clk; struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)]; struct snd_soc_component *component; struct sta32x_platform_data *pdata; @@ -879,6 +881,18 @@ static int sta32x_probe(struct snd_soc_component *component) struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); struct sta32x_platform_data *pdata = sta32x->pdata; int i, ret = 0, thermal = 0; + + sta32x->component = component; + + if (sta32x->xti_clk) { + ret = clk_prepare_enable(sta32x->xti_clk); + if (ret != 0) { + dev_err(component->dev, + "Failed to enable clock: %d\n", ret); + return ret; + } + } + ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); if (ret != 0) { @@ -981,6 +995,9 @@ static void sta32x_remove(struct snd_soc_component *component) sta32x_watchdog_stop(sta32x); regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); + + if (sta32x->xti_clk) + clk_disable_unprepare(sta32x->xti_clk); } static const struct snd_soc_component_driver sta32x_component = { @@ -1097,6 +1114,17 @@ static int sta32x_i2c_probe(struct i2c_client *i2c, } #endif + /* Clock */ + sta32x->xti_clk = devm_clk_get(dev, "xti"); + if (IS_ERR(sta32x->xti_clk)) { + ret = PTR_ERR(sta32x->xti_clk); + + if (ret == -EPROBE_DEFER) + return ret; + + sta32x->xti_clk = NULL; + } + /* GPIOs */ sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); -- 2.19.0.rc2

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[alsa-devel] [PATCH] ASoC: pcm3168a: add hw constraint for capture channel
by Kuninori Morimoto 19 Oct '18

19 Oct '18

From: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> LEFT_J / I2S only can use TDM. commit 594680ea4a394 ("ASoC: pcm3168a: add hw constraint for channel") commit 3809688980205 ("ASoC: pcm3168a: add HW constraint for non RIGHT_J") added channel constraint for it, but, it was only for playback. This patch adds constraint for capture. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> --- sound/soc/codecs/pcm3168a.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/pcm3168a.c b/sound/soc/codecs/pcm3168a.c index 63aa025..52cc950 100644 --- a/sound/soc/codecs/pcm3168a.c +++ b/sound/soc/codecs/pcm3168a.c @@ -529,11 +529,17 @@ static int pcm3168a_startup(struct snd_pcm_substream *substream, break; case PCM3168A_FMT_LEFT_J: sample_min = 24; - channel_max = 8; + if (tx) + channel_max = 8; + else + channel_max = 6; break; case PCM3168A_FMT_I2S: sample_min = 24; - channel_max = 8; + if (tx) + channel_max = 8; + else + channel_max = 6; break; default: sample_min = 24; @@ -559,6 +565,7 @@ static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = { }; static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = { + .startup = pcm3168a_startup, .set_fmt = pcm3168a_set_dai_fmt_adc, .set_sysclk = pcm3168a_set_dai_sysclk, .hw_params = pcm3168a_hw_params -- 2.7.4

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[alsa-devel] Applied "ASoC: rsnd: enable TDM settings for SSI parent" to the asoc tree
by Mark Brown 19 Oct '18

19 Oct '18

The patch ASoC: rsnd: enable TDM settings for SSI parent has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 6817d7593f3e3c8a9c11e7a07cb5646c70371f0a Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Date: Wed, 17 Oct 2018 01:55:37 +0000 Subject: [PATCH] ASoC: rsnd: enable TDM settings for SSI parent Some SSIs are sharing each pins (= WS/CLK pin for playback/capture). Then, SSI parent needs control WS/CLK setting for SSI slave. In such case, SSI parent needs TDM settings if SSI slave is working as TDM mode. But it is not cared in current driver. It can't capture TDM sound without this patch if SSIs were pin sharing. This patch is tested on R-Car H3 ulcb-kf board, SSI3/4 with TDM sound. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Signed-off-by: Mark Brown <broonie(a)kernel.org> --- sound/soc/sh/rcar/ssi.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c index 3adcc4f778f7..b42a0e0feab7 100644 --- a/sound/soc/sh/rcar/ssi.c +++ b/sound/soc/sh/rcar/ssi.c @@ -399,6 +399,17 @@ static void rsnd_ssi_config_init(struct rsnd_mod *mod, if (rdai->sys_delay) cr_own |= DEL; + /* + * TDM Mode + * see + * rsnd_ssiu_init_gen2() + */ + wsr = ssi->wsr; + if (is_tdm) { + wsr |= WS_MODE; + cr_own |= CHNL_8; + } + /* * We shouldn't exchange SWSP after running. * This means, parent needs to care it. @@ -429,16 +440,6 @@ static void rsnd_ssi_config_init(struct rsnd_mod *mod, cr_mode = DIEN; /* PIO : enable Data interrupt */ } - /* - * TDM Extend Mode - * see - * rsnd_ssiu_init_gen2() - */ - wsr = ssi->wsr; - if (is_tdm) { - wsr |= WS_MODE; - cr_own |= CHNL_8; - } init_end: ssi->cr_own = cr_own; ssi->cr_mode = cr_mode; -- 2.19.0.rc2

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