January 2017 - Alsa-devel - mailman.alsa-project.org

Re: [alsa-devel] [linux-sunxi] Re: [PATCH v3 05/10] arm: dts: sun8i: split Allwinner H3 .dtsi
by Icenowy Zheng 30 Jan '17

30 Jan '17

2017年1月30日 09:42于 André Przywara <andre.przywara(a)arm.com>写道： > > On 29/01/17 02:33, Icenowy Zheng wrote: > > From: Andre Przywara <andre.przywara(a)arm.com> > > (Adding DT folks to CC:) > > see below ... > > > The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the > > Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller > > updated. So we should really share almost the whole .dtsi. > > In preparation for that move the peripheral parts of the existing > > sun8i-h3.dtsi into a new sun8i-h3-h5.dtsi. > > The actual sun8i-h3.dtsi then includes that and defines the H3 specific > > parts on top of it. > > On the way get rid of skeleton.dtsi, as recommended in that very file. > > > > Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> > > [Icenowy: also split out mmc, as well as pio and ccu's compatible] > > Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> > > --- > > Changes in v3: > > - Use label-based syntax to reference nodes in H3 DTSI file. > > Changes in v2: > > - Rebase on current linux-next (because of the add of audio codec) > > > > arch/arm/boot/dts/sun8i-h3.dtsi | 571 +++---------------------------------- > > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 557 ++++++++++++++++++++++++++++++++++++ > > 2 files changed, 598 insertions(+), 530 deletions(-) > > create mode 100644 arch/arm/boot/dts/sunxi-h3-h5.dtsi > > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > > index 08fd0860bb6b..f3a3033789b9 100644 > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > > @@ -40,12 +40,7 @@ > > * OTHER DEALINGS IN THE SOFTWARE. > > */ > > > > -#include "skeleton.dtsi" > > - > > -#include <dt-bindings/clock/sun8i-h3-ccu.h> > > -#include <dt-bindings/interrupt-controller/arm-gic.h> > > -#include <dt-bindings/pinctrl/sun4i-a10.h> > > -#include <dt-bindings/reset/sun8i-h3-ccu.h> > > +#include "sunxi-h3-h5.dtsi" > > > > / { > > interrupt-parent = <&gic>; > > @@ -87,489 +82,7 @@ > > <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > > }; > > > > - clocks { > > - #address-cells = <1>; > > - #size-cells = <1>; > > - ranges; > > - > > - osc24M: osc24M_clk { > > - #clock-cells = <0>; > > - compatible = "fixed-clock"; > > - clock-frequency = <24000000>; > > - clock-output-names = "osc24M"; > > - }; > > - > > - osc32k: osc32k_clk { > > - #clock-cells = <0>; > > - compatible = "fixed-clock"; > > - clock-frequency = <32768>; > > - clock-output-names = "osc32k"; > > - }; > > - > > - apb0: apb0_clk { > > - compatible = "fixed-factor-clock"; > > - #clock-cells = <0>; > > - clock-div = <1>; > > - clock-mult = <1>; > > - clocks = <&osc24M>; > > - clock-output-names = "apb0"; > > - }; > > - > > - apb0_gates: clk@01f01428 { > > - compatible = "allwinner,sun8i-h3-apb0-gates-clk", > > - "allwinner,sun4i-a10-gates-clk"; > > - reg = <0x01f01428 0x4>; > > - #clock-cells = <1>; > > - clocks = <&apb0>; > > - clock-indices = <0>, <1>; > > - clock-output-names = "apb0_pio", "apb0_ir"; > > - }; > > - > > - ir_clk: ir_clk@01f01454 { > > - compatible = "allwinner,sun4i-a10-mod0-clk"; > > - reg = <0x01f01454 0x4>; > > - #clock-cells = <0>; > > - clocks = <&osc32k>, <&osc24M>; > > - clock-output-names = "ir"; > > - }; > > - }; > > - > > soc { > > - compatible = "simple-bus"; > > - #address-cells = <1>; > > - #size-cells = <1>; > > - ranges; > > - > > - dma: dma-controller@01c02000 { > > - compatible = "allwinner,sun8i-h3-dma"; > > - reg = <0x01c02000 0x1000>; > > - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_DMA>; > > - resets = <&ccu RST_BUS_DMA>; > > - #dma-cells = <1>; > > - }; > > - > > - mmc0: mmc@01c0f000 { > > - compatible = "allwinner,sun7i-a20-mmc"; > > - reg = <0x01c0f000 0x1000>; > > - clocks = <&ccu CLK_BUS_MMC0>, > > - <&ccu CLK_MMC0>, > > - <&ccu CLK_MMC0_OUTPUT>, > > - <&ccu CLK_MMC0_SAMPLE>; > > - clock-names = "ahb", > > - "mmc", > > - "output", > > - "sample"; > > - resets = <&ccu RST_BUS_MMC0>; > > - reset-names = "ahb"; > > - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > - mmc1: mmc@01c10000 { > > - compatible = "allwinner,sun7i-a20-mmc"; > > - reg = <0x01c10000 0x1000>; > > - clocks = <&ccu CLK_BUS_MMC1>, > > - <&ccu CLK_MMC1>, > > - <&ccu CLK_MMC1_OUTPUT>, > > - <&ccu CLK_MMC1_SAMPLE>; > > - clock-names = "ahb", > > - "mmc", > > - "output", > > - "sample"; > > - resets = <&ccu RST_BUS_MMC1>; > > - reset-names = "ahb"; > > - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > - mmc2: mmc@01c11000 { > > - compatible = "allwinner,sun7i-a20-mmc"; > > - reg = <0x01c11000 0x1000>; > > - clocks = <&ccu CLK_BUS_MMC2>, > > - <&ccu CLK_MMC2>, > > - <&ccu CLK_MMC2_OUTPUT>, > > - <&ccu CLK_MMC2_SAMPLE>; > > - clock-names = "ahb", > > - "mmc", > > - "output", > > - "sample"; > > - resets = <&ccu RST_BUS_MMC2>; > > - reset-names = "ahb"; > > - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > - usbphy: phy@01c19400 { > > - compatible = "allwinner,sun8i-h3-usb-phy"; > > - reg = <0x01c19400 0x2c>, > > - <0x01c1a800 0x4>, > > - <0x01c1b800 0x4>, > > - <0x01c1c800 0x4>, > > - <0x01c1d800 0x4>; > > - reg-names = "phy_ctrl", > > - "pmu0", > > - "pmu1", > > - "pmu2", > > - "pmu3"; > > - clocks = <&ccu CLK_USB_PHY0>, > > - <&ccu CLK_USB_PHY1>, > > - <&ccu CLK_USB_PHY2>, > > - <&ccu CLK_USB_PHY3>; > > - clock-names = "usb0_phy", > > - "usb1_phy", > > - "usb2_phy", > > - "usb3_phy"; > > - resets = <&ccu RST_USB_PHY0>, > > - <&ccu RST_USB_PHY1>, > > - <&ccu RST_USB_PHY2>, > > - <&ccu RST_USB_PHY3>; > > - reset-names = "usb0_reset", > > - "usb1_reset", > > - "usb2_reset", > > - "usb3_reset"; > > - status = "disabled"; > > - #phy-cells = <1>; > > - }; > > - > > - ehci1: usb@01c1b000 { > > - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; > > - reg = <0x01c1b000 0x100>; > > - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; > > - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; > > - phys = <&usbphy 1>; > > - phy-names = "usb"; > > - status = "disabled"; > > - }; > > - > > - ohci1: usb@01c1b400 { > > - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; > > - reg = <0x01c1b400 0x100>; > > - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, > > - <&ccu CLK_USB_OHCI1>; > > - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; > > - phys = <&usbphy 1>; > > - phy-names = "usb"; > > - status = "disabled"; > > - }; > > - > > - ehci2: usb@01c1c000 { > > - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; > > - reg = <0x01c1c000 0x100>; > > - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; > > - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; > > - phys = <&usbphy 2>; > > - phy-names = "usb"; > > - status = "disabled"; > > - }; > > - > > - ohci2: usb@01c1c400 { > > - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; > > - reg = <0x01c1c400 0x100>; > > - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, > > - <&ccu CLK_USB_OHCI2>; > > - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; > > - phys = <&usbphy 2>; > > - phy-names = "usb"; > > - status = "disabled"; > > - }; > > - > > - ehci3: usb@01c1d000 { > > - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; > > - reg = <0x01c1d000 0x100>; > > - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; > > - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; > > - phys = <&usbphy 3>; > > - phy-names = "usb"; > > - status = "disabled"; > > - }; > > - > > - ohci3: usb@01c1d400 { > > - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; > > - reg = <0x01c1d400 0x100>; > > - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, > > - <&ccu CLK_USB_OHCI3>; > > - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; > > - phys = <&usbphy 3>; > > - phy-names = "usb"; > > - status = "disabled"; > > - }; > > - > > - ccu: clock@01c20000 { > > - compatible = "allwinner,sun8i-h3-ccu"; > > - reg = <0x01c20000 0x400>; > > - clocks = <&osc24M>, <&osc32k>; > > - clock-names = "hosc", "losc"; > > - #clock-cells = <1>; > > - #reset-cells = <1>; > > - }; > > - > > - pio: pinctrl@01c20800 { > > - compatible = "allwinner,sun8i-h3-pinctrl"; > > - reg = <0x01c20800 0x400>; > > - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > > - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; > > - clock-names = "apb", "hosc", "losc"; > > - gpio-controller; > > - #gpio-cells = <3>; > > - interrupt-controller; > > - #interrupt-cells = <3>; > > - > > - i2c0_pins: i2c0 { > > - pins = "PA11", "PA12"; > > - function = "i2c0"; > > - }; > > - > > - i2c1_pins: i2c1 { > > - pins = "PA18", "PA19"; > > - function = "i2c1"; > > - }; > > - > > - i2c2_pins: i2c2 { > > - pins = "PE12", "PE13"; > > - function = "i2c2"; > > - }; > > - > > - mmc0_pins_a: mmc0@0 { > > - pins = "PF0", "PF1", "PF2", "PF3", > > - "PF4", "PF5"; > > - function = "mmc0"; > > - drive-strength = <30>; > > - bias-pull-up; > > - }; > > - > > - mmc0_cd_pin: mmc0_cd_pin@0 { > > - pins = "PF6"; > > - function = "gpio_in"; > > - bias-pull-up; > > - }; > > - > > - mmc1_pins_a: mmc1@0 { > > - pins = "PG0", "PG1", "PG2", "PG3", > > - "PG4", "PG5"; > > - function = "mmc1"; > > - drive-strength = <30>; > > - bias-pull-up; > > - }; > > - > > - mmc2_8bit_pins: mmc2_8bit { > > - pins = "PC5", "PC6", "PC8", > > - "PC9", "PC10", "PC11", > > - "PC12", "PC13", "PC14", > > - "PC15", "PC16"; > > - function = "mmc2"; > > - drive-strength = <30>; > > - bias-pull-up; > > - }; > > - > > - spi0_pins: spi0 { > > - pins = "PC0", "PC1", "PC2", "PC3"; > > - function = "spi0"; > > - }; > > - > > - spi1_pins: spi1 { > > - pins = "PA15", "PA16", "PA14", "PA13"; > > - function = "spi1"; > > - }; > > - > > - uart0_pins_a: uart0@0 { > > - pins = "PA4", "PA5"; > > - function = "uart0"; > > - }; > > - > > - uart1_pins: uart1 { > > - pins = "PG6", "PG7"; > > - function = "uart1"; > > - }; > > - > > - uart1_rts_cts_pins: uart1_rts_cts { > > - pins = "PG8", "PG9"; > > - function = "uart1"; > > - }; > > - > > - uart2_pins: uart2 { > > - pins = "PA0", "PA1"; > > - function = "uart2"; > > - }; > > - > > - uart3_pins: uart3 { > > - pins = "PA13", "PA14"; > > - function = "uart3"; > > - }; > > - }; > > - > > - timer@01c20c00 { > > - compatible = "allwinner,sun4i-a10-timer"; > > - reg = <0x01c20c00 0xa0>; > > - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, > > - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&osc24M>; > > - }; > > - > > - spi0: spi@01c68000 { > > - compatible = "allwinner,sun8i-h3-spi"; > > - reg = <0x01c68000 0x1000>; > > - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > > - clock-names = "ahb", "mod"; > > - dmas = <&dma 23>, <&dma 23>; > > - dma-names = "rx", "tx"; > > - pinctrl-names = "default"; > > - pinctrl-0 = <&spi0_pins>; > > - resets = <&ccu RST_BUS_SPI0>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > - spi1: spi@01c69000 { > > - compatible = "allwinner,sun8i-h3-spi"; > > - reg = <0x01c69000 0x1000>; > > - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > > - clock-names = "ahb", "mod"; > > - dmas = <&dma 24>, <&dma 24>; > > - dma-names = "rx", "tx"; > > - pinctrl-names = "default"; > > - pinctrl-0 = <&spi1_pins>; > > - resets = <&ccu RST_BUS_SPI1>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > - wdt0: watchdog@01c20ca0 { > > - compatible = "allwinner,sun6i-a31-wdt"; > > - reg = <0x01c20ca0 0x20>; > > - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > > - }; > > - > > - pwm: pwm@01c21400 { > > - compatible = "allwinner,sun8i-h3-pwm"; > > - reg = <0x01c21400 0x8>; > > - clocks = <&osc24M>; > > - #pwm-cells = <3>; > > - status = "disabled"; > > - }; > > - > > - codec: codec@01c22c00 { > > - #sound-dai-cells = <0>; > > - compatible = "allwinner,sun8i-h3-codec"; > > - reg = <0x01c22c00 0x400>; > > - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; > > - clock-names = "apb", "codec"; > > - resets = <&ccu RST_BUS_CODEC>; > > - dmas = <&dma 15>, <&dma 15>; > > - dma-names = "rx", "tx"; > > - allwinner,codec-analog-controls = <&codec_analog>; > > - status = "disabled"; > > - }; > > - > > - uart0: serial@01c28000 { > > - compatible = "snps,dw-apb-uart"; > > - reg = <0x01c28000 0x400>; > > - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > > - reg-shift = <2>; > > - reg-io-width = <4>; > > - clocks = <&ccu CLK_BUS_UART0>; > > - resets = <&ccu RST_BUS_UART0>; > > - dmas = <&dma 6>, <&dma 6>; > > - dma-names = "rx", "tx"; > > - status = "disabled"; > > - }; > > - > > - uart1: serial@01c28400 { > > - compatible = "snps,dw-apb-uart"; > > - reg = <0x01c28400 0x400>; > > - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > > - reg-shift = <2>; > > - reg-io-width = <4>; > > - clocks = <&ccu CLK_BUS_UART1>; > > - resets = <&ccu RST_BUS_UART1>; > > - dmas = <&dma 7>, <&dma 7>; > > - dma-names = "rx", "tx"; > > - status = "disabled"; > > - }; > > - > > - uart2: serial@01c28800 { > > - compatible = "snps,dw-apb-uart"; > > - reg = <0x01c28800 0x400>; > > - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > > - reg-shift = <2>; > > - reg-io-width = <4>; > > - clocks = <&ccu CLK_BUS_UART2>; > > - resets = <&ccu RST_BUS_UART2>; > > - dmas = <&dma 8>, <&dma 8>; > > - dma-names = "rx", "tx"; > > - status = "disabled"; > > - }; > > - > > - uart3: serial@01c28c00 { > > - compatible = "snps,dw-apb-uart"; > > - reg = <0x01c28c00 0x400>; > > - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > > - reg-shift = <2>; > > - reg-io-width = <4>; > > - clocks = <&ccu CLK_BUS_UART3>; > > - resets = <&ccu RST_BUS_UART3>; > > - dmas = <&dma 9>, <&dma 9>; > > - dma-names = "rx", "tx"; > > - status = "disabled"; > > - }; > > - > > - i2c0: i2c@01c2ac00 { > > - compatible = "allwinner,sun6i-a31-i2c"; > > - reg = <0x01c2ac00 0x400>; > > - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_I2C0>; > > - resets = <&ccu RST_BUS_I2C0>; > > - pinctrl-names = "default"; > > - pinctrl-0 = <&i2c0_pins>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > - i2c1: i2c@01c2b000 { > > - compatible = "allwinner,sun6i-a31-i2c"; > > - reg = <0x01c2b000 0x400>; > > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_I2C1>; > > - resets = <&ccu RST_BUS_I2C1>; > > - pinctrl-names = "default"; > > - pinctrl-0 = <&i2c1_pins>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > - i2c2: i2c@01c2b400 { > > - compatible = "allwinner,sun6i-a31-i2c"; > > - reg = <0x01c2b000 0x400>; > > - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&ccu CLK_BUS_I2C2>; > > - resets = <&ccu RST_BUS_I2C2>; > > - pinctrl-names = "default"; > > - pinctrl-0 = <&i2c2_pins>; > > - status = "disabled"; > > - #address-cells = <1>; > > - #size-cells = <0>; > > - }; > > - > > gic: interrupt-controller@01c81000 { > > compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > > reg = <0x01c81000 0x1000>, > > @@ -580,51 +93,49 @@ > > #interrupt-cells = <3>; > > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > }; > > + }; > > +}; > > > > - rtc: rtc@01f00000 { > > - compatible = "allwinner,sun6i-a31-rtc"; > > - reg = <0x01f00000 0x54>; > > - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > > - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > > - }; > > - > > - apb0_reset: reset@01f014b0 { > > - reg = <0x01f014b0 0x4>; > > - compatible = "allwinner,sun6i-a31-clock-reset"; > > - #reset-cells = <1>; > > - }; > > +&ccu { > > + compatible = "allwinner,sun8i-h3-ccu"; > > +}; > > I believe this kind of sharing nodes is a bit frowned upon in connection > with sharing .dtsi's. If the compatible name differs, I think it > deserves to be a separate node spelt out in each SoC's .dtsi. > This also makes the DT more readable, since a reader doesn't have to > refer to two files to see what's in that node. For such a device tree, see sun8i-a23-a33.c . > > > > > - codec_analog: codec-analog@01f015c0 { > > - compatible = "allwinner,sun8i-h3-codec-analog"; > > - reg = <0x01f015c0 0x4>; > > - }; > > +&mmc0 { > > + compatible = "allwinner,sun7i-a20-mmc"; > > + clocks = <&ccu CLK_BUS_MMC0>, > > + <&ccu CLK_MMC0>, > > + <&ccu CLK_MMC0_OUTPUT>, > > + <&ccu CLK_MMC0_SAMPLE>; > > + clock-names = "ahb", > > + "mmc", > > + "output", > > + "sample"; > > This applies even more here, since the MMC controllers also have > different clock requirements. > > So why can't we just leave the CCU, MMC and possibly the pinctrl nodes > completely out of the shared h3-h5.dtsi and introduce them from scratch > in the SoC specific .dtsi? > > I think we still have enough identical nodes to justify this kind of > .dtsi sharing. > > Cheers, > Andre. > > > +}; > > > > - ir: ir@01f02000 { > > - compatible = "allwinner,sun5i-a13-ir"; > > - clocks = <&apb0_gates 1>, <&ir_clk>; > > - clock-names = "apb", "ir"; > > - resets = <&apb0_reset 1>; > > - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > > - reg = <0x01f02000 0x40>; > > - status = "disabled"; > > - }; > > +&mmc1 { > > + compatible = "allwinner,sun7i-a20-mmc"; > > + clocks = <&ccu CLK_BUS_MMC1>, > > + <&ccu CLK_MMC1>, > > + <&ccu CLK_MMC1_OUTPUT>, > > + <&ccu CLK_MMC1_SAMPLE>; > > + clock-names = "ahb", > > + "mmc", > > + "output", > > + "sample"; > > +}; > > > > - r_pio: pinctrl@01f02c00 { > > - compatible = "allwinner,sun8i-h3-r-pinctrl"; > > - reg = <0x01f02c00 0x400>; > > - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; > > - clock-names = "apb", "hosc", "losc"; > > - resets = <&apb0_reset 0>; > > - gpio-controller; > > - #gpio-cells = <3>; > > - interrupt-controller; > > - #interrupt-cells = <3>; > > +&mmc2 { > > + compatible = "allwinner,sun7i-a20-mmc"; > > + clocks = <&ccu CLK_BUS_MMC2>, > > + <&ccu CLK_MMC2>, > > + <&ccu CLK_MMC2_OUTPUT>, > > + <&ccu CLK_MMC2_SAMPLE>; > > + clock-names = "ahb", > > + "mmc", > > + "output", > > + "sample"; > > +}; > > > > - ir_pins_a: ir@0 { > > - pins = "PL11"; > > - function = "s_cir_rx"; > > - }; > > - }; > > - }; > > +&pio { > > + compatible = "allwinner,sun8i-h3-pinctrl"; > > }; > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > new file mode 100644 > > index 000000000000..4a57c65e8869 > > --- /dev/null > > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > @@ -0,0 +1,557 @@ > > +/* > > + * Copyright (C) 2015 Jens Kuske <jenskuske(a)gmail.com> > > + * > > + * This file is dual-licensed: you can use it either under the terms > > + * of the GPL or the X11 license, at your option. Note that this dual > > + * licensing only applies to this file, and not this project as a > > + * whole. > > + * > > + * a) This file is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation; either version 2 of the > > + * License, or (at your option) any later version. > > + * > > + * This file is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * Or, alternatively, > > + * > > + * b) Permission is hereby granted, free of charge, to any person > > + * obtaining a copy of this software and associated documentation > > + * files (the "Software"), to deal in the Software without > > + * restriction, including without limitation the rights to use, > > + * copy, modify, merge, publish, distribute, sublicense, and/or > > + * sell copies of the Software, and to permit persons to whom the > > + * Software is furnished to do so, subject to the following > > + * conditions: > > + * > > + * The above copyright notice and this permission notice shall be > > + * included in all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > > + * OTHER DEALINGS IN THE SOFTWARE. > > + */ > > + > > +#include <dt-bindings/clock/sunxi-h3-h5-ccu.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include <dt-bindings/pinctrl/sun4i-a10.h> > > +#include <dt-bindings/reset/sunxi-h3-h5-ccu.h> > > + > > +/ { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + clocks { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + osc24M: osc24M_clk { > > + #clock-cells = <0>; > > + compatible = "fixed-clock"; > > + clock-frequency = <24000000>; > > + clock-output-names = "osc24M"; > > + }; > > + > > + osc32k: osc32k_clk { > > + #clock-cells = <0>; > > + compatible = "fixed-clock"; > > + clock-frequency = <32768>; > > + clock-output-names = "osc32k"; > > + }; > > + > > + apb0: apb0_clk { > > + compatible = "fixed-factor-clock"; > > + #clock-cells = <0>; > > + clock-div = <1>; > > + clock-mult = <1>; > > + clocks = <&osc24M>; > > + clock-output-names = "apb0"; > > + }; > > + > > + apb0_gates: clk@01f01428 { > > + compatible = "allwinner,sun8i-h3-apb0-gates-clk", > > + "allwinner,sun4i-a10-gates-clk"; > > + reg = <0x01f01428 0x4>; > > + #clock-cells = <1>; > > + clocks = <&apb0>; > > + clock-indices = <0>, <1>; > > + clock-output-names = "apb0_pio", "apb0_ir"; > > + }; > > + > > + ir_clk: ir_clk@01f01454 { > > + compatible = "allwinner,sun4i-a10-mod0-clk"; > > + reg = <0x01f01454 0x4>; > > + #clock-cells = <0>; > > + clocks = <&osc32k>, <&osc24M>; > > + clock-output-names = "ir"; > > + }; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + dma: dma-controller@01c02000 { > > + compatible = "allwinner,sun8i-h3-dma"; > > + reg = <0x01c02000 0x1000>; > > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_DMA>; > > + resets = <&ccu RST_BUS_DMA>; > > + #dma-cells = <1>; > > + }; > > + > > + mmc0: mmc@01c0f000 { > > + /* compatible and clocks are in per SoC .dtsi file */ > > + reg = <0x01c0f000 0x1000>; > > + resets = <&ccu RST_BUS_MMC0>; > > + reset-names = "ahb"; > > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + mmc1: mmc@01c10000 { > > + /* compatible and clocks are in per SoC .dtsi file */ > > + reg = <0x01c10000 0x1000>; > > + resets = <&ccu RST_BUS_MMC1>; > > + reset-names = "ahb"; > > + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + mmc2: mmc@01c11000 { > > + /* compatible and clocks are in per SoC .dtsi file */ > > + reg = <0x01c11000 0x1000>; > > + resets = <&ccu RST_BUS_MMC2>; > > + reset-names = "ahb"; > > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + usbphy: phy@01c19400 { > > + compatible = "allwinner,sun8i-h3-usb-phy"; > > + reg = <0x01c19400 0x2c>, > > + <0x01c1a800 0x4>, > > + <0x01c1b800 0x4>, > > + <0x01c1c800 0x4>, > > + <0x01c1d800 0x4>; > > + reg-names = "phy_ctrl", > > + "pmu0", > > + "pmu1", > > + "pmu2", > > + "pmu3"; > > + clocks = <&ccu CLK_USB_PHY0>, > > + <&ccu CLK_USB_PHY1>, > > + <&ccu CLK_USB_PHY2>, > > + <&ccu CLK_USB_PHY3>; > > + clock-names = "usb0_phy", > > + "usb1_phy", > > + "usb2_phy", > > + "usb3_phy"; > > + resets = <&ccu RST_USB_PHY0>, > > + <&ccu RST_USB_PHY1>, > > + <&ccu RST_USB_PHY2>, > > + <&ccu RST_USB_PHY3>; > > + reset-names = "usb0_reset", > > + "usb1_reset", > > + "usb2_reset", > > + "usb3_reset"; > > + status = "disabled"; > > + #phy-cells = <1>; > > + }; > > + > > + ehci1: usb@01c1b000 { > > + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; > > + reg = <0x01c1b000 0x100>; > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; > > + resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; > > + phys = <&usbphy 1>; > > + phy-names = "usb"; > > + status = "disabled"; > > + }; > > + > > + ohci1: usb@01c1b400 { > > + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; > > + reg = <0x01c1b400 0x100>; > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, > > + <&ccu CLK_USB_OHCI1>; > > + resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; > > + phys = <&usbphy 1>; > > + phy-names = "usb"; > > + status = "disabled"; > > + }; > > + > > + ehci2: usb@01c1c000 { > > + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; > > + reg = <0x01c1c000 0x100>; > > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; > > + resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; > > + phys = <&usbphy 2>; > > + phy-names = "usb"; > > + status = "disabled"; > > + }; > > + > > + ohci2: usb@01c1c400 { > > + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; > > + reg = <0x01c1c400 0x100>; > > + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, > > + <&ccu CLK_USB_OHCI2>; > > + resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; > > + phys = <&usbphy 2>; > > + phy-names = "usb"; > > + status = "disabled"; > > + }; > > + > > + ehci3: usb@01c1d000 { > > + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; > > + reg = <0x01c1d000 0x100>; > > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; > > + resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; > > + phys = <&usbphy 3>; > > + phy-names = "usb"; > > + status = "disabled"; > > + }; > > + > > + ohci3: usb@01c1d400 { > > + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; > > + reg = <0x01c1d400 0x100>; > > + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, > > + <&ccu CLK_USB_OHCI3>; > > + resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; > > + phys = <&usbphy 3>; > > + phy-names = "usb"; > > + status = "disabled"; > > + }; > > + > > + ccu: clock@01c20000 { > > + /* compatible is in per SoC .dtsi file */ > > + reg = <0x01c20000 0x400>; > > + clocks = <&osc24M>, <&osc32k>; > > + clock-names = "hosc", "losc"; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > + > > + pio: pinctrl@01c20800 { > > + /* compatible is in per SoC .dtsi file */ > > + reg = <0x01c20800 0x400>; > > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; > > + clock-names = "apb", "hosc", "losc"; > > + gpio-controller; > > + #gpio-cells = <3>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + i2c0_pins: i2c0 { > > + pins = "PA11", "PA12"; > > + function = "i2c0"; > > + }; > > + > > + i2c1_pins: i2c1 { > > + pins = "PA18", "PA19"; > > + function = "i2c1"; > > + }; > > + > > + i2c2_pins: i2c2 { > > + pins = "PE12", "PE13"; > > + function = "i2c2"; > > + }; > > + > > + mmc0_pins_a: mmc0@0 { > > + pins = "PF0", "PF1", "PF2", "PF3", > > + "PF4", "PF5"; > > + function = "mmc0"; > > + drive-strength = <30>; > > + bias-pull-up; > > + }; > > + > > + mmc0_cd_pin: mmc0_cd_pin@0 { > > + pins = "PF6"; > > + function = "gpio_in"; > > + bias-pull-up; > > + }; > > + > > + mmc1_pins_a: mmc1@0 { > > + pins = "PG0", "PG1", "PG2", "PG3", > > + "PG4", "PG5"; > > + function = "mmc1"; > > + drive-strength = <30>; > > + bias-pull-up; > > + }; > > + > > + mmc2_8bit_pins: mmc2_8bit { > > + pins = "PC5", "PC6", "PC8", > > + "PC9", "PC10", "PC11", > > + "PC12", "PC13", "PC14", > > + "PC15", "PC16"; > > + function = "mmc2"; > > + drive-strength = <30>; > > + bias-pull-up; > > + }; > > + > > + spi0_pins: spi0 { > > + pins = "PC0", "PC1", "PC2", "PC3"; > > + function = "spi0"; > > + }; > > + > > + spi1_pins: spi1 { > > + pins = "PA15", "PA16", "PA14", "PA13"; > > + function = "spi1"; > > + }; > > + > > + uart0_pins_a: uart0@0 { > > + pins = "PA4", "PA5"; > > + function = "uart0"; > > + }; > > + > > + uart1_pins: uart1 { > > + pins = "PG6", "PG7"; > > + function = "uart1"; > > + }; > > + > > + uart1_rts_cts_pins: uart1_rts_cts { > > + pins = "PG8", "PG9"; > > + function = "uart1"; > > + }; > > + > > + uart2_pins: uart2 { > > + pins = "PA0", "PA1"; > > + function = "uart2"; > > + }; > > + > > + uart3_pins: uart3 { > > + pins = "PA13", "PA14"; > > + function = "uart3"; > > + }; > > + }; > > + > > + timer@01c20c00 { > > + compatible = "allwinner,sun4i-a10-timer"; > > + reg = <0x01c20c00 0xa0>; > > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&osc24M>; > > + }; > > + > > + spi0: spi@01c68000 { > > + compatible = "allwinner,sun8i-h3-spi"; > > + reg = <0x01c68000 0x1000>; > > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 23>, <&dma 23>; > > + dma-names = "rx", "tx"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&spi0_pins>; > > + resets = <&ccu RST_BUS_SPI0>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + spi1: spi@01c69000 { > > + compatible = "allwinner,sun8i-h3-spi"; > > + reg = <0x01c69000 0x1000>; > > + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > > + clock-names = "ahb", "mod"; > > + dmas = <&dma 24>, <&dma 24>; > > + dma-names = "rx", "tx"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&spi1_pins>; > > + resets = <&ccu RST_BUS_SPI1>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + wdt0: watchdog@01c20ca0 { > > + compatible = "allwinner,sun6i-a31-wdt"; > > + reg = <0x01c20ca0 0x20>; > > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + pwm: pwm@01c21400 { > > + compatible = "allwinner,sun8i-h3-pwm"; > > + reg = <0x01c21400 0x8>; > > + clocks = <&osc24M>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + codec: codec@01c22c00 { > > + #sound-dai-cells = <0>; > > + compatible = "allwinner,sun8i-h3-codec"; > > + reg = <0x01c22c00 0x400>; > > + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; > > + clock-names = "apb", "codec"; > > + resets = <&ccu RST_BUS_CODEC>; > > + dmas = <&dma 15>, <&dma 15>; > > + dma-names = "rx", "tx"; > > + allwinner,codec-analog-controls = <&codec_analog>; > > + status = "disabled"; > > + }; > > + > > + uart0: serial@01c28000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x01c28000 0x400>; > > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + clocks = <&ccu CLK_BUS_UART0>; > > + resets = <&ccu RST_BUS_UART0>; > > + dmas = <&dma 6>, <&dma 6>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + uart1: serial@01c28400 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x01c28400 0x400>; > > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + clocks = <&ccu CLK_BUS_UART1>; > > + resets = <&ccu RST_BUS_UART1>; > > + dmas = <&dma 7>, <&dma 7>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + uart2: serial@01c28800 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x01c28800 0x400>; > > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + clocks = <&ccu CLK_BUS_UART2>; > > + resets = <&ccu RST_BUS_UART2>; > > + dmas = <&dma 8>, <&dma 8>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + uart3: serial@01c28c00 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x01c28c00 0x400>; > > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + clocks = <&ccu CLK_BUS_UART3>; > > + resets = <&ccu RST_BUS_UART3>; > > + dmas = <&dma 9>, <&dma 9>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + i2c0: i2c@01c2ac00 { > > + compatible = "allwinner,sun6i-a31-i2c"; > > + reg = <0x01c2ac00 0x400>; > > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_I2C0>; > > + resets = <&ccu RST_BUS_I2C0>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&i2c0_pins>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + i2c1: i2c@01c2b000 { > > + compatible = "allwinner,sun6i-a31-i2c"; > > + reg = <0x01c2b000 0x400>; > > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_I2C1>; > > + resets = <&ccu RST_BUS_I2C1>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&i2c1_pins>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + i2c2: i2c@01c2b400 { > > + compatible = "allwinner,sun6i-a31-i2c"; > > + reg = <0x01c2b000 0x400>; > > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_I2C2>; > > + resets = <&ccu RST_BUS_I2C2>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&i2c2_pins>; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + rtc: rtc@01f00000 { > > + compatible = "allwinner,sun6i-a31-rtc"; > > + reg = <0x01f00000 0x54>; > > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + apb0_reset: reset@01f014b0 { > > + reg = <0x01f014b0 0x4>; > > + compatible = "allwinner,sun6i-a31-clock-reset"; > > + #reset-cells = <1>; > > + }; > > + > > + codec_analog: codec-analog@01f015c0 { > > + compatible = "allwinner,sun8i-h3-codec-analog"; > > + reg = <0x01f015c0 0x4>; > > + }; > > + > > + ir: ir@01f02000 { > > + compatible = "allwinner,sun5i-a13-ir"; > > + clocks = <&apb0_gates 1>, <&ir_clk>; > > + clock-names = "apb", "ir"; > > + resets = <&apb0_reset 1>; > > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > > + reg = <0x01f02000 0x40>; > > + status = "disabled"; > > + }; > > + > > + r_pio: pinctrl@01f02c00 { > > + compatible = "allwinner,sun8i-h3-r-pinctrl"; > > + reg = <0x01f02c00 0x400>; > > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; > > + clock-names = "apb", "hosc", "losc"; > > + resets = <&apb0_reset 0>; > > + gpio-controller; > > + #gpio-cells = <3>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + ir_pins_a: ir@0 { > > + pins = "PL11"; > > + function = "s_cir_rx"; > > + }; > > + }; > > + }; > > +}; > > > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe(a)googlegroups.com. > For more options, visit https://groups.google.com/d/optout.

1 0

[alsa-devel] [PATCH 00/19][RFC v2] ALSA: firewire-motu: new driver for MOTU FireWire series
by Takashi Sakamoto 30 Jan '17

30 Jan '17

Hi, This patchset updates a part of my previous RFC, just for MOTU FireWire series. [RFC][PATCH 00/37] ALSA: firewire: support AMDTP variants http://mailman.alsa-project.org/pipermail/alsa-devel/2015-July/094789.html This patchset adds support for a part of MOTU FireWire series with their functionality of packet streaming. Below models are newly supported: - 828 - 828mk2 - 828mk3 (FireWire/Hybrid) However, this module cannot handle 828 correctly to generate sound. The reason is not clear yet. On the other hand, 828mk2 and 828mk3 can be handled most properly via ALSA PCM/MIDI/HwDep interfaces. Currently, I have a plan to post this patchset to merge into Linux 4.12. Corresponding merge window will be estimated to open this April. If you're willing to test this module, please report the result till then. For testers, I prepared for backport modules in my repository. Please follow instructions in README. https://github.com/takaswie/snd-firewire-improve/tree/topic/motu As user land tools, I added some stuffs to libhinawa and hinawa-utils. Please refer to 'topic/motu' branch of these repositories. You can use 'hinawa-motu-common-cui' to configure some streaming-related features of the above units: * https://github.com/takaswie/libhinawa/tree/topic/motu * https://github.com/takaswie/hinawa-utils/tree/topic/motu Takashi Sakamoto (19): firewire-motu: add skeleton for Mark of the unicorn (MOTU) FireWire series firewire-motu: postpone sound card registration firewire-motu: add a structure for model-dependent parameters. firewire-motu: add an abstraction layer for three types of protocols firewire-lib: record cycle count for the first packet firewire-lib: add support for source packet header field in CIP header firewire-lib: enable CIP_DBC_IS_END_EVENT for both directions of stream firewire-motu: add MOTU specific protocol layer firewire-motu: handle transactions specific for MOTU FireWire models firewire-motu: add stream management functionality firewire-motu: add proc node to show current statuc of clock and packet formats firewire-motu: add PCM functionality firewire-motu: add MIDI functionality firewire-motu: add hwdep interface firewire-motu: enable to read transaction cache via hwdep interface firewire-motu: add support for MOTU 828 as a model with protocol version 1 firewire-motu: add support for MOTU 828mk2 as a model with protocol version 2 firewire-lib: add a quirk of packet without valid EOH in CIP format firewire-motu: add support for MOTU 828mk3 (FireWire/Hybrid) as a model with protocol version 3 include/uapi/sound/asound.h | 3 +- include/uapi/sound/firewire.h | 10 +- sound/firewire/Kconfig | 13 ++ sound/firewire/Makefile | 1 + sound/firewire/amdtp-stream.c | 36 ++- sound/firewire/amdtp-stream.h | 9 +- sound/firewire/motu/Makefile | 5 + sound/firewire/motu/amdtp-motu.c | 388 ++++++++++++++++++++++++++++++++ sound/firewire/motu/motu-hwdep.c | 198 ++++++++++++++++ sound/firewire/motu/motu-midi.c | 169 ++++++++++++++ sound/firewire/motu/motu-pcm.c | 398 +++++++++++++++++++++++++++++++++ sound/firewire/motu/motu-proc.c | 118 ++++++++++ sound/firewire/motu/motu-protocol-v1.c | 204 +++++++++++++++++ sound/firewire/motu/motu-protocol-v2.c | 237 ++++++++++++++++++++ sound/firewire/motu/motu-protocol-v3.c | 312 ++++++++++++++++++++++++++ sound/firewire/motu/motu-stream.c | 381 +++++++++++++++++++++++++++++++ sound/firewire/motu/motu-transaction.c | 137 ++++++++++++ sound/firewire/motu/motu.c | 273 ++++++++++++++++++++++ sound/firewire/motu/motu.h | 161 +++++++++++++ 19 files changed, 3042 insertions(+), 11 deletions(-) create mode 100644 sound/firewire/motu/Makefile create mode 100644 sound/firewire/motu/amdtp-motu.c create mode 100644 sound/firewire/motu/motu-hwdep.c create mode 100644 sound/firewire/motu/motu-midi.c create mode 100644 sound/firewire/motu/motu-pcm.c create mode 100644 sound/firewire/motu/motu-proc.c create mode 100644 sound/firewire/motu/motu-protocol-v1.c create mode 100644 sound/firewire/motu/motu-protocol-v2.c create mode 100644 sound/firewire/motu/motu-protocol-v3.c create mode 100644 sound/firewire/motu/motu-stream.c create mode 100644 sound/firewire/motu/motu-transaction.c create mode 100644 sound/firewire/motu/motu.c create mode 100644 sound/firewire/motu/motu.h -- 2.9.3

2 27

Re: [alsa-devel] [linux-sunxi] Re: [PATCH v2 4/9] arm: dts: sun8i: split Allwinner H3 .dtsi
by Icenowy Zheng 27 Jan '17

27 Jan '17

2017年1月27日 23:55于 Maxime Ripard <maxime.ripard(a)free-electrons.com>写道： > > On Thu, Jan 26, 2017 at 11:48:54PM +0800, Icenowy Zheng wrote: > > - mmc0: mmc@01c0f000 { > > + mmc@01c0f000 { > > There's no point in removing the labels, and you can even use the > label-based syntax to reference them, instead of using the path. I think keeping a tree structure in sub dtsi file will make it more pretty and easy to use :-) > > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe(a)googlegroups.com. > For more options, visit https://groups.google.com/d/optout.

2 1

Re: [alsa-devel] [linux-sunxi] Re: [PATCH v2 6/9] arm64: dts: allwinner: add Allwinner H5 .dtsi
by Icenowy Zheng 27 Jan '17

27 Jan '17

2017年1月27日 23:58于 Maxime Ripard <maxime.ripard(a)free-electrons.com>写道： > > On Thu, Jan 26, 2017 at 11:48:56PM +0800, Icenowy Zheng wrote: > > + mmc@01c0f000 { > > Please use a label based syntax here too. > > > + compatible = "allwinner,sun50i-a64-mmc", > > + "allwinner,sun5i-a13-mmc"; > > The compatibility with the A13 has never been true, and the compatible > should be "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc". > > > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > > + clock-names = "ahb", "mmc"; > > + }; > > + > > + mmc@01c10000 { > > + compatible = "allwinner,sun50i-a64-mmc", > > + "allwinner,sun5i-a13-mmc"; > > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; > > + clock-names = "ahb", "mmc"; > > + }; > > + > > + mmc@01c11000 { > > + compatible = "allwinner,sun50i-a64-mmc", > > And this is very likely to use the emmc compatible. > > > + "allwinner,sun5i-a13-mmc"; > > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; > > + clock-names = "ahb", "mmc"; > > + }; > > + > > + clock@01c20000 { > > + compatible = "allwinner,sun50i-h5-ccu", > > + "allwinner,sun8i-h3-ccu"; > > + }; > > If it doesn't have the same clocks, it's not compatible with the H3. I'll drop it. It's from the original patch from Andre. > > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe(a)googlegroups.com. > For more options, visit https://groups.google.com/d/optout.

1 0

[alsa-devel] [RFC PATCH 0/5] DisplayPort Audio on Cherrytrail
by Pierre-Louis Bossart 27 Jan '17

27 Jan '17

The following patches enable DisplayPort Audio on Cherrytrail machines when applied on top of Takashi's topic/intel-lpe-audio branch (tested on Zotac PI330) There are a couple of opens where I could use some help: - is it necessary to set a valid_bit which is used only for DP audio? - is the sequence to set the chicken bits and unmute the amplifier ok or can it be improved by being moved somewhere else in the i915 driver? - the register offset to be used by the audio driver depends on a combination of port/pipe/output type. Do we need to get access to the pipe information and when is it available (initial trials showed the pipe is still invalid when the audio notification happens) Feedback welcome! Pierre-Louis Bossart (5): drm: i915: add DP support in LPE audio mode ALSA: x86: intel_hdmi: add definitions and logic for DP audio ALSA: x86: intel_hdmi: set config bitfields for DP mode drm: i915: add DisplayPort amp unmute for LPE audio mode ALSA: x86: hdmi: hack to enable DP audio on CHT drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_reg.h | 12 +++ drivers/gpu/drm/i915/intel_audio.c | 19 +++- drivers/gpu/drm/i915/intel_lpe_audio.c | 34 ++++++- include/drm/intel_lpe_audio.h | 2 + sound/x86/intel_hdmi_audio.c | 174 ++++++++++++++++++++++++++++----- sound/x86/intel_hdmi_audio.h | 8 +- sound/x86/intel_hdmi_lpe_audio.c | 44 ++++++++- sound/x86/intel_hdmi_lpe_audio.h | 29 ++++++ 9 files changed, 288 insertions(+), 37 deletions(-) -- 2.7.4

4 16

[alsa-devel] [PATCH RFC 0/3] Pass pipe to LPE audio
by Takashi Iwai 27 Jan '17

27 Jan '17

Hi, this is a patch series to pass the pipe over LPE audio notification, based on Pierre's latest patchset ("[RFC PATCH 0/5] DisplayPort Audio on Cherrytrail"). Takashi === Takashi Iwai (3): drm/i915: Avoid MST pipe handling for LPE audio drm/i915: Pass pipe to LPE audio notification ALSA: x86: Use config base depending on the pipe drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_audio.c | 27 ++++++++++++++------------- drivers/gpu/drm/i915/intel_lpe_audio.c | 3 ++- include/drm/intel_lpe_audio.h | 1 + sound/x86/intel_hdmi_lpe_audio.c | 32 +++++++++++++++++++++----------- 5 files changed, 39 insertions(+), 26 deletions(-) -- 2.11.0

2 5

[alsa-devel] [PATCH v7 0/5] Add platform clock for BayTrail platforms
by Pierre-Louis Bossart 27 Jan '17

27 Jan '17

These patches specifically enable the audio MCLK required by Baytrail CR devices. It is the remaining part of a bigger set of patches (already merged in Mark Brown's tree) that enable sound for Baytrail CR devices (especially Asus T100TAF) [1]. They include the clock driver and clock enabling in the pmc_atom code (along with moving of the non-architectural pmc_atom driver code into drivers/platform/x86 as suggested by Thomas Gleixner [2]). This move includes a new header in include/linux/platform_data/x86/. While there is an agreement that the definitions for PMC clocks are not really platform data this location is seen as a good-enough compromise with an agreement between Darren Hart and Andy Shevchenko [3] [1] http://mailman.alsa-project.org/pipermail/alsa-devel/2016-August/111704.html [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2016-October/113936.ht… [3] http://mailman.alsa-project.org/pipermail/alsa-devel/2016-December/115892.h… Changes from v6: - Addressed comments from Stephen Boyd, Andy Shevchenko and Vinod Koul - Renamed clk-byt-plt to clk-pmc-atom - Rebase to 4.10-rc3 (broonie/for-next) - Added helper functions to make error handling more compact - Removed module-related code since it's not possible/supported - Removed useless tests on remove - PMC_CLK_OFFSET move to clk-pcm-atom (more logical) - Split typo correction and makefile fix in separate patches - small fixes (spaces, defaults in switches, alphabetical order, use of clk_writel/readl and no test on write, simpler error handling, use of while(i--), unsigned loop variables, kernel doc fields, format-patch -M -C -D, use of PLATFORM_DEVID_NONE) Changes from v5: - fix build error reported by kbuild test robot - split the clk driver code from x86 platform changes Changes from v4: - move the pmc_atom driver from arch/x86/platform/atom to drivers/platform/x86 Changes from v3: - replace devm_kzalloc with devm_kcalloc - add x86 architecture maintainers Changes from v2: - move clk platform data structures to a separate include file - store clk_hw pointer for the fixed rate clocks Changes from v1: - register the clk device as child of pmc device - pass iomem pointer from pmc driver to clk driver to avoid using pmc_atom_read()/write() and use readl/writel API instead - use devm_clk_hw_register/clkdev_hw_create instead of clk_register/clkdev_create Irina Tirdea (3): clk: x86: Add Atom PMC platform clocks arch/x86/platform/atom: Move pmc_atom to drivers/platform/x86 platform/x86: Enable Atom PMC platform clocks Pierre-Louis Bossart (2): clk: Make x86/ conditional on CONFIG_COMMON_CLK platform/x86: fix typo in comment arch/x86/Kconfig | 4 - arch/x86/platform/atom/Makefile | 1 - drivers/acpi/acpi_lpss.c | 2 +- drivers/clk/Makefile | 2 + drivers/clk/x86/Makefile | 1 + drivers/clk/x86/clk-pmc-atom.c | 373 +++++++++++++++++++++ drivers/platform/x86/Kconfig | 5 + drivers/platform/x86/Makefile | 1 + .../atom => drivers/platform/x86}/pmc_atom.c | 88 ++++- include/linux/platform_data/x86/clk-pmc-atom.h | 44 +++ .../linux/platform_data/x86}/pmc_atom.h | 2 +- 11 files changed, 508 insertions(+), 15 deletions(-) create mode 100644 drivers/clk/x86/clk-pmc-atom.c rename {arch/x86/platform/atom => drivers/platform/x86}/pmc_atom.c (87%) create mode 100644 include/linux/platform_data/x86/clk-pmc-atom.h rename {arch/x86/include/asm => include/linux/platform_data/x86}/pmc_atom.h (98%) -- 2.7.4

5 13

[alsa-devel] [PATCH] sound: pci: cs46xx: constify snd_pcm_ops structures
by Bhumika Goyal 26 Jan '17

26 Jan '17

Declare snd_pcm_ops structures as const as they are either stored in the ops field of a snd_pcm_substream structure or passed as an argument to the function snd_pcm_set_ops. The function argument and the ops field are of type const, so snd_pcm_ops structures having this property can be made const too. File size before: sound/pci/cs46xx/cs46xx_lib.o text data bss dec hex filename 13669 1712 0 15381 3c15 sound/pci/cs46xx/cs46xx_lib.o File size after: sound/pci/cs46xx/cs46xx_lib.o text data bss dec hex filename 14181 1216 0 15397 3c25 sound/pci/cs46xx/cs46xx_lib.o Signed-off-by: Bhumika Goyal <bhumirks(a)gmail.com> --- sound/pci/cs46xx/cs46xx_lib.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/sound/pci/cs46xx/cs46xx_lib.c b/sound/pci/cs46xx/cs46xx_lib.c index fde3cd4..5d012f5 100644 --- a/sound/pci/cs46xx/cs46xx_lib.c +++ b/sound/pci/cs46xx/cs46xx_lib.c @@ -72,18 +72,18 @@ static void amp_voyetra(struct snd_cs46xx *chip, int change); #ifdef CONFIG_SND_CS46XX_NEW_DSP -static struct snd_pcm_ops snd_cs46xx_playback_rear_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; -static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; -static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; #endif -static struct snd_pcm_ops snd_cs46xx_playback_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; -static struct snd_pcm_ops snd_cs46xx_capture_ops; -static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; +static const struct snd_pcm_ops snd_cs46xx_capture_ops; +static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, unsigned short reg, @@ -1665,7 +1665,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { .open = snd_cs46xx_playback_open_rear, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1677,7 +1677,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { .ack = snd_cs46xx_playback_transfer, }; -static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { .open = snd_cs46xx_playback_open_clfe, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1688,7 +1688,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { .open = snd_cs46xx_playback_open_clfe, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1700,7 +1700,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { .ack = snd_cs46xx_playback_transfer, }; -static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { .open = snd_cs46xx_playback_open_iec958, .close = snd_cs46xx_playback_close_iec958, .ioctl = snd_pcm_lib_ioctl, @@ -1711,7 +1711,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { .open = snd_cs46xx_playback_open_iec958, .close = snd_cs46xx_playback_close_iec958, .ioctl = snd_pcm_lib_ioctl, @@ -1725,7 +1725,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { #endif -static struct snd_pcm_ops snd_cs46xx_playback_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_ops = { .open = snd_cs46xx_playback_open, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1736,7 +1736,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_ops = { .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { .open = snd_cs46xx_playback_open, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1748,7 +1748,7 @@ static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { .ack = snd_cs46xx_playback_transfer, }; -static struct snd_pcm_ops snd_cs46xx_capture_ops = { +static const struct snd_pcm_ops snd_cs46xx_capture_ops = { .open = snd_cs46xx_capture_open, .close = snd_cs46xx_capture_close, .ioctl = snd_pcm_lib_ioctl, @@ -1759,7 +1759,7 @@ static struct snd_pcm_ops snd_cs46xx_capture_ops = { .pointer = snd_cs46xx_capture_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { +static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { .open = snd_cs46xx_capture_open, .close = snd_cs46xx_capture_close, .ioctl = snd_pcm_lib_ioctl, -- 2.7.4

3 2

[alsa-devel] [PATCH v2] sound: pci: cs46xx: constify snd_pcm_ops structures
by Bhumika Goyal 26 Jan '17

26 Jan '17

Declare snd_pcm_ops structures as const as they are either stored in the ops field of a snd_pcm_substream structure or passed as an argument to the function snd_pcm_set_ops. The function argument and the ops field are of type const, so snd_pcm_ops structures having this property can be made const too. File size before: sound/pci/cs46xx/cs46xx_lib.o text data bss dec hex filename 26047 5304 16 31367 7a87 sound/pci/cs46xx/cs46xx_lib.o File size after: sound/pci/cs46xx/cs46xx_lib.o text data bss dec hex filename 27335 4036 16 31387 7a9b sound/pci/cs46xx/cs46xx_lib.o Signed-off-by: Bhumika Goyal <bhumirks(a)gmail.com> --- Changes in v2: * test build the patch with CONFIG_SND_CS46XX_NEW_DSP=y sound/pci/cs46xx/cs46xx_lib.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/sound/pci/cs46xx/cs46xx_lib.c b/sound/pci/cs46xx/cs46xx_lib.c index fde3cd4..9a8b41f 100644 --- a/sound/pci/cs46xx/cs46xx_lib.c +++ b/sound/pci/cs46xx/cs46xx_lib.c @@ -72,18 +72,18 @@ static void amp_voyetra(struct snd_cs46xx *chip, int change); #ifdef CONFIG_SND_CS46XX_NEW_DSP -static struct snd_pcm_ops snd_cs46xx_playback_rear_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; -static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; -static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; #endif -static struct snd_pcm_ops snd_cs46xx_playback_ops; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; -static struct snd_pcm_ops snd_cs46xx_capture_ops; -static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_ops; +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; +static const struct snd_pcm_ops snd_cs46xx_capture_ops; +static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, unsigned short reg, @@ -1654,7 +1654,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) } #ifdef CONFIG_SND_CS46XX_NEW_DSP -static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { .open = snd_cs46xx_playback_open_rear, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1665,7 +1665,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { .open = snd_cs46xx_playback_open_rear, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1677,7 +1677,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .ack = snd_cs46xx_playback_transfer, }; -static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { .open = snd_cs46xx_playback_open_clfe, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1688,7 +1688,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { .open = snd_cs46xx_playback_open_clfe, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1700,7 +1700,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .ack = snd_cs46xx_playback_transfer, }; -static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { .open = snd_cs46xx_playback_open_iec958, .close = snd_cs46xx_playback_close_iec958, .ioctl = snd_pcm_lib_ioctl, @@ -1711,7 +1711,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { .open = snd_cs46xx_playback_open_iec958, .close = snd_cs46xx_playback_close_iec958, .ioctl = snd_pcm_lib_ioctl, @@ -1725,7 +1725,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) #endif -static struct snd_pcm_ops snd_cs46xx_playback_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_ops = { .open = snd_cs46xx_playback_open, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1736,7 +1736,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .pointer = snd_cs46xx_playback_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { +static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { .open = snd_cs46xx_playback_open, .close = snd_cs46xx_playback_close, .ioctl = snd_pcm_lib_ioctl, @@ -1748,7 +1748,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .ack = snd_cs46xx_playback_transfer, }; -static struct snd_pcm_ops snd_cs46xx_capture_ops = { +static const struct snd_pcm_ops snd_cs46xx_capture_ops = { .open = snd_cs46xx_capture_open, .close = snd_cs46xx_capture_close, .ioctl = snd_pcm_lib_ioctl, @@ -1759,7 +1759,7 @@ static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) .pointer = snd_cs46xx_capture_direct_pointer, }; -static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { +static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { .open = snd_cs46xx_capture_open, .close = snd_cs46xx_capture_close, .ioctl = snd_pcm_lib_ioctl, -- 1.9.1

2 1

[alsa-devel] [PATCH v2 1/7] drivers: pinctrl: add driver for Allwinner H5 SoC
by Icenowy Zheng 26 Jan '17

26 Jan '17

Based on the Allwinner H5 datasheet and the pinctrl driver of the backward-compatible H3 this introduces the pin multiplex assignments for the H5 SoC. H5 introduced some more pin functions (e.g. three more groups of TS pins, and one more groups of SIM pins) than H3. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> --- Changes in v2: - Fixed interrupt banks. (There's one more GPIO banks (PF) that can do interrupt handling on H5) .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 558 +++++++++++++++++++++ 4 files changed, 564 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index c931fb1c01a6..2fd688c8dbdb 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -23,6 +23,7 @@ Required properties: "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" "allwinner,sun50i-a64-pinctrl" + "allwinner,sun50i-h5-r-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 8ba10d830ce2..92d845827577 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -72,4 +72,8 @@ config PINCTRL_SUN50I_A64 bool select PINCTRL_SUNXI +config PINCTRL_SUN50I_H5 + bool + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 7bcb4683bce5..f9a3855c42f1 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o +obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c new file mode 100644 index 000000000000..ccf9419e9418 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -0,0 +1,558 @@ +/* + * Allwinner H5 SoC pinctrl driver. + * + * Copyright (C) 2016 Icenowy Zheng <icenowy(a)aosc.xyz> + * + * Based on pinctrl-sun8i-h3.c, which is: + * Copyright (C) 2015 Jens Kuske <jenskuske(a)gmail.com> + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai <wens(a)csie.org> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard(a)free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun50i_h5_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "pwm0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x3, "di"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x3, "di"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x4, "mmc2")), /* DS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */ + SUNXI_FUNCTION(0x3, "di"), /* TX */ + SUNXI_FUNCTION(0x4, "ts2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */ + SUNXI_FUNCTION(0x3, "di"), /* RX */ + SUNXI_FUNCTION(0x4, "ts2")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */ + SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */ + SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXCK */ + SUNXI_FUNCTION(0x4, "ts2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */ + SUNXI_FUNCTION(0x4, "ts2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXERR */ + SUNXI_FUNCTION(0x4, "ts2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D3 */ + SUNXI_FUNCTION(0x5, "ts3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D4 */ + SUNXI_FUNCTION(0x5, "ts3")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D5 */ + SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D6 */ + SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* CRS */ + SUNXI_FUNCTION(0x4, "ts2"), /* D7 */ + SUNXI_FUNCTION(0x5, "ts3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXCK */ + SUNXI_FUNCTION(0x4, "sim")), /* PWREN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */ + SUNXI_FUNCTION(0x4, "sim")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXERR */ + SUNXI_FUNCTION(0x4, "sim")), /* DATA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */ + SUNXI_FUNCTION(0x4, "sim")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* MDC */ + SUNXI_FUNCTION(0x4, "sim")), /* DET */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "ts0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ts0")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x4, "ts1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x4, "ts1")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "ts"), /* D7 */ + SUNXI_FUNCTION(0x4, "ts1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ +}; + +static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { + .pins = sun50i_h5_pins, + .npins = ARRAY_SIZE(sun50i_h5_pins), + .irq_banks = 2, + .irq_read_needs_mux = true +}; + +static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun50i_h5_pinctrl_data); +} + +static const struct of_device_id sun50i_h5_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-h5-pinctrl", }, + {} +}; + +static struct platform_driver sun50i_h5_pinctrl_driver = { + .probe = sun50i_h5_pinctrl_probe, + .driver = { + .name = "sun50i-h5-pinctrl", + .of_match_table = sun50i_h5_pinctrl_match, + }, +}; +builtin_platform_driver(sun50i_h5_pinctrl_driver); -- 2.11.0

1 3