June 2016 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] ASoC: sgtl5000: SMALL_POP and loud click noise 5 secs after playback stopped
by Clemens Gruber 07 Jun '16

07 Jun '16

Hi, since commit b101acfabc9377469af3abfb7cb63112da367284 I can hear a loud click / pop noise, always occuring 5 seconds after playback stopped. Hardware: i.MX6Q board with SGTL5000 Kernel: 4.7-rc2 master In the commit history of sgtl5000.h I saw that SGTL5000_SMALL_POP was previously 0 and that Fabio, who changed it to 0, had a similar problem back then. Now with SGTL5000_SMALL_POP at 1, the problem reappeared. Changing it back to 0 fixes the problem for me, but as Axel Lin explained in the commit mentioned above, having 0 as mask leads to not writing anything to the CHIP_REF_CTRL register and the SMALL_POP bit stays as it was. So why does this help? Maybe having SMALL_POP active causes that noise in some circumstances? Then we could add a devicetree property to turn it on or off as needed. Or, the documentation of the SMALL_POP bit in the datasheet is not correct / inverted? Then we could remove that write to the CHIP_REF_CTRL register and leave the SMALL_POP bit at its default value? Axel: Did changing SGTL5000_SMALL_POP to 1 remove a click/pop noise on your board or did you just notice the error with the mask argument of snd_soc_update_bits and fixed it? Thanks, Clemens

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[alsa-devel] [PATCH v6 1/2] ASoC: cs35l33: Initial commit of the cs35l33 CODEC driver.
by Paul.Handrigan＠cirrus.com 07 Jun '16

07 Jun '16

From: Paul Handrigan <Paul.Handrigan(a)cirrus.com> Initial commit of the Cirrus Logic cs35l33 8V boosted class D amplifier. Signed-off-by: Paul Handrigan <Paul.Handrigan(a)cirrus.com> --- include/sound/cs35l33.h | 48 ++ sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs35l33.c | 1300 ++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/cs35l33.h | 221 ++++++++ 5 files changed, 1576 insertions(+) create mode 100644 include/sound/cs35l33.h create mode 100644 sound/soc/codecs/cs35l33.c create mode 100644 sound/soc/codecs/cs35l33.h diff --git a/include/sound/cs35l33.h b/include/sound/cs35l33.h new file mode 100644 index 0000000..b6eadce --- /dev/null +++ b/include/sound/cs35l33.h @@ -0,0 +1,48 @@ +/* + * linux/sound/cs35l33.h -- Platform data for CS35l33 + * + * Copyright (c) 2016 Cirrus Logic Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __CS35L33_H +#define __CS35L33_H + +struct cs35l33_hg { + bool enable_hg_algo; + unsigned int mem_depth; + unsigned int release_rate; + unsigned int hd_rm; + unsigned int ldo_thld; + unsigned int ldo_path_disable; + unsigned int ldo_entry_delay; + bool vp_hg_auto; + unsigned int vp_hg; + unsigned int vp_hg_rate; + unsigned int vp_hg_va; +}; + +struct cs35l33_pdata { + /* Boost Controller Voltage Setting */ + unsigned int boost_ctl; + + /* Boost Controller Peak Current */ + unsigned int boost_ipk; + + /* Amplifier Drive Select */ + unsigned int amp_drv_sel; + + /* soft volume ramp */ + unsigned int ramp_rate; + + /* IMON adc scale */ + unsigned int imon_adc_scale; + + /* H/G algo configuration */ + struct cs35l33_hg hg_config; +}; + +#endif /* __CS35L33_H */ diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index cb57f8f..627a380 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -47,6 +47,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_BT_SCO select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC select SND_SOC_CS35L32 if I2C + select SND_SOC_CS35L33 if I2C select SND_SOC_CS42L51_I2C if I2C select SND_SOC_CS42L52 if I2C && INPUT select SND_SOC_CS42L56 if I2C && INPUT @@ -386,6 +387,10 @@ config SND_SOC_CS35L32 tristate "Cirrus Logic CS35L32 CODEC" depends on I2C +config SND_SOC_CS35L33 + tristate "Cirrus Logic CS35L33 CODEC" + depends on I2C + config SND_SOC_CS42L51 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 550a174..c279597 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -36,6 +36,7 @@ snd-soc-arizona-objs := arizona.o snd-soc-bt-sco-objs := bt-sco.o snd-soc-cq93vc-objs := cq93vc.o snd-soc-cs35l32-objs := cs35l32.o +snd-soc-cs35l33-objs := cs35l33.o snd-soc-cs42l51-objs := cs42l51.o snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o snd-soc-cs42l52-objs := cs42l52.o @@ -254,6 +255,7 @@ obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o obj-$(CONFIG_SND_SOC_CS35L32) += snd-soc-cs35l32.o +obj-$(CONFIG_SND_SOC_CS35L33) += snd-soc-cs35l33.o obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o diff --git a/sound/soc/codecs/cs35l33.c b/sound/soc/codecs/cs35l33.c new file mode 100644 index 0000000..da0262e --- /dev/null +++ b/sound/soc/codecs/cs35l33.c @@ -0,0 +1,1300 @@ +/* + * cs35l33.c -- CS35L33 ALSA SoC audio driver + * + * Copyright 2016 Cirrus Logic, Inc. + * + * Author: Paul Handrigan <paul.handrigan(a)cirrus.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/version.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/slab.h> +#include <linux/workqueue.h> +#include <linux/platform_device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <linux/gpio.h> +#include <linux/gpio/consumer.h> +#include <sound/cs35l33.h> +#include <linux/pm_runtime.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/of_gpio.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> + +#include "cs35l33.h" + +#define CS35L33_BOOT_DELAY 50 +#define CS35L33_INT_ATTEMPTS 5 + +struct cs35l33_private { + struct snd_soc_codec *codec; + struct cs35l33_pdata pdata; + struct regmap *regmap; + struct gpio_desc *reset_gpio; + bool amp_cal; + int mclk_int; + struct regulator_bulk_data core_supplies[2]; + int num_core_supplies; + bool is_tdm_mode; + bool enable_soft_ramp; +}; + +static const struct reg_default cs35l33_reg[] = { + {CS35L33_PWRCTL1, 0x85}, + {CS35L33_PWRCTL2, 0xFE}, + {CS35L33_CLK_CTL, 0x0C}, + {CS35L33_BST_PEAK_CTL, 0x90}, + {CS35L33_PROTECT_CTL, 0x55}, + {CS35L33_BST_CTL1, 0x00}, + {CS35L33_BST_CTL2, 0x01}, + {CS35L33_ADSP_CTL, 0x00}, + {CS35L33_ADC_CTL, 0xC8}, + {CS35L33_DAC_CTL, 0x14}, + {CS35L33_DIG_VOL_CTL, 0x00}, + {CS35L33_CLASSD_CTL, 0x04}, + {CS35L33_AMP_CTL, 0x90}, + {CS35L33_INT_MASK_1, 0xFF}, + {CS35L33_INT_MASK_2, 0xFF}, + {CS35L33_DIAG_LOCK, 0x00}, + {CS35L33_DIAG_CTRL_1, 0x40}, + {CS35L33_DIAG_CTRL_2, 0x00}, + {CS35L33_HG_MEMLDO_CTL, 0x62}, + {CS35L33_HG_REL_RATE, 0x03}, + {CS35L33_LDO_DEL, 0x12}, + {CS35L33_HG_HEAD, 0x0A}, + {CS35L33_HG_EN, 0x05}, + {CS35L33_TX_VMON, 0x00}, + {CS35L33_TX_IMON, 0x03}, + {CS35L33_TX_VPMON, 0x02}, + {CS35L33_TX_VBSTMON, 0x05}, + {CS35L33_TX_FLAG, 0x06}, + {CS35L33_TX_EN1, 0x00}, + {CS35L33_TX_EN2, 0x00}, + {CS35L33_TX_EN3, 0x00}, + {CS35L33_TX_EN4, 0x00}, + {CS35L33_RX_AUD, 0x40}, + {CS35L33_RX_SPLY, 0x03}, + {CS35L33_RX_ALIVE, 0x04}, + {CS35L33_BST_CTL4, 0x63}, +}; + +static const struct reg_sequence cs35l33_patch[] = { + { 0x00, 0x99, 0 }, + { 0x59, 0x02, 0 }, + { 0x52, 0x30, 0 }, + { 0x39, 0x45, 0 }, + { 0x57, 0x30, 0 }, + { 0x2C, 0x68, 0 }, + { 0x00, 0x00, 0 }, +}; + +static bool cs35l33_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L33_DEVID_AB: + case CS35L33_DEVID_CD: + case CS35L33_DEVID_E: + case CS35L33_REV_ID: + case CS35L33_INT_STATUS_1: + case CS35L33_INT_STATUS_2: + case CS35L33_HG_STATUS: + return true; + default: + return false; + } +} + +static bool cs35l33_writeable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + /* these are read only registers */ + case CS35L33_DEVID_AB: + case CS35L33_DEVID_CD: + case CS35L33_DEVID_E: + case CS35L33_REV_ID: + case CS35L33_INT_STATUS_1: + case CS35L33_INT_STATUS_2: + case CS35L33_HG_STATUS: + return false; + default: + return true; + } +} + +static bool cs35l33_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L33_DEVID_AB: + case CS35L33_DEVID_CD: + case CS35L33_DEVID_E: + case CS35L33_REV_ID: + case CS35L33_PWRCTL1: + case CS35L33_PWRCTL2: + case CS35L33_CLK_CTL: + case CS35L33_BST_PEAK_CTL: + case CS35L33_PROTECT_CTL: + case CS35L33_BST_CTL1: + case CS35L33_BST_CTL2: + case CS35L33_ADSP_CTL: + case CS35L33_ADC_CTL: + case CS35L33_DAC_CTL: + case CS35L33_DIG_VOL_CTL: + case CS35L33_CLASSD_CTL: + case CS35L33_AMP_CTL: + case CS35L33_INT_MASK_1: + case CS35L33_INT_MASK_2: + case CS35L33_INT_STATUS_1: + case CS35L33_INT_STATUS_2: + case CS35L33_DIAG_LOCK: + case CS35L33_DIAG_CTRL_1: + case CS35L33_DIAG_CTRL_2: + case CS35L33_HG_MEMLDO_CTL: + case CS35L33_HG_REL_RATE: + case CS35L33_LDO_DEL: + case CS35L33_HG_HEAD: + case CS35L33_HG_EN: + case CS35L33_TX_VMON: + case CS35L33_TX_IMON: + case CS35L33_TX_VPMON: + case CS35L33_TX_VBSTMON: + case CS35L33_TX_FLAG: + case CS35L33_TX_EN1: + case CS35L33_TX_EN2: + case CS35L33_TX_EN3: + case CS35L33_TX_EN4: + case CS35L33_RX_AUD: + case CS35L33_RX_SPLY: + case CS35L33_RX_ALIVE: + case CS35L33_BST_CTL4: + return true; + default: + return false; + } +} + +static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0); +static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0); + +static const struct snd_kcontrol_new cs35l33_snd_controls[] = { + + SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL, + 4, 0x09, 0, classd_ctl_tlv), + SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL, + 0, 0x34, 0xE4, dac_tlv), +}; + +static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (!priv->amp_cal) { + usleep_range(8000, 9000); + priv->amp_cal = true; + regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL, + CS35L33_AMP_CAL, 0); + dev_dbg(codec->dev, "Amp calibration done\n"); + } + dev_dbg(codec->dev, "Amp turned on\n"); + break; + case SND_SOC_DAPM_POST_PMD: + dev_dbg(codec->dev, "Amp turned off\n"); + break; + default: + dev_err(codec->dev, "Invalid event = 0x%x\n", event); + break; + } + + return 0; +} + +static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + unsigned int val; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, + CS35L33_PDN_BST, 0); + val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM; + regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, + CS35L33_PDN_TDM, val); + dev_dbg(codec->dev, "BST turned on\n"); + break; + case SND_SOC_DAPM_POST_PMU: + dev_dbg(codec->dev, "SDIN turned on\n"); + if (!priv->amp_cal) { + regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL, + CS35L33_AMP_CAL, CS35L33_AMP_CAL); + dev_dbg(codec->dev, "Amp calibration started\n"); + usleep_range(10000, 11000); + } + break; + case SND_SOC_DAPM_POST_PMD: + regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, + CS35L33_PDN_TDM, CS35L33_PDN_TDM); + usleep_range(4000, 4100); + regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, + CS35L33_PDN_BST, CS35L33_PDN_BST); + dev_dbg(codec->dev, "BST and SDIN turned off\n"); + break; + default: + dev_err(codec->dev, "Invalid event = 0x%x\n", event); + + } + + return 0; +} + +static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; + unsigned int mask2 = CS35L33_SDOUT_3ST_TDM; + unsigned int val, val2; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (priv->is_tdm_mode) { + /* set sdout_3st_i2s and reset pdn_tdm */ + val = CS35L33_SDOUT_3ST_I2S; + /* reset sdout_3st_tdm */ + val2 = 0; + } else { + /* reset sdout_3st_i2s and set pdn_tdm */ + val = CS35L33_PDN_TDM; + /* set sdout_3st_tdm */ + val2 = CS35L33_SDOUT_3ST_TDM; + } + dev_dbg(codec->dev, "SDOUT turned on\n"); + break; + case SND_SOC_DAPM_PRE_PMD: + val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; + val2 = CS35L33_SDOUT_3ST_TDM; + dev_dbg(codec->dev, "SDOUT turned off\n"); + break; + default: + dev_err(codec->dev, "Invalid event = 0x%x\n", event); + return 0; + } + + regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, + mask, val); + regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, + mask2, val2); + + return 0; +} + +static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = { + + SND_SOC_DAPM_OUTPUT("SPK"), + SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0, + cs35l33_spkrdrv_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2, + 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_INPUT("MON"), + + SND_SOC_DAPM_ADC("VMON", NULL, + CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1), + SND_SOC_DAPM_ADC("IMON", NULL, + CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1), + SND_SOC_DAPM_ADC("VPMON", NULL, + CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1), + SND_SOC_DAPM_ADC("VBSTMON", NULL, + CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1), + + SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0, + cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_PRE_PMD), +}; + +static const struct snd_soc_dapm_route cs35l33_audio_map[] = { + {"SDIN", NULL, "CS35L33 Playback"}, + {"SPKDRV", NULL, "SDIN"}, + {"SPK", NULL, "SPKDRV"}, + + {"VMON", NULL, "MON"}, + {"IMON", NULL, "MON"}, + + {"SDOUT", NULL, "VMON"}, + {"SDOUT", NULL, "IMON"}, + {"CS35L33 Capture", NULL, "SDOUT"}, +}; + +static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = { + {"SPKDRV", NULL, "VPMON"}, + {"VPMON", NULL, "CS35L33 Playback"}, +}; + +static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = { + {"SDOUT", NULL, "VPMON"}, + {"VPMON", NULL, "MON"}, + {"SDOUT", NULL, "VBSTMON"}, + {"VBSTMON", NULL, "MON"}, +}; + +static int cs35l33_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + unsigned int val; + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + + switch (level) { + case SND_SOC_BIAS_ON: + break; + case SND_SOC_BIAS_PREPARE: + regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, + CS35L33_PDN_ALL, 0); + regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, + CS35L33_MCLKDIS, 0); + break; + case SND_SOC_BIAS_STANDBY: + regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, + CS35L33_PDN_ALL, CS35L33_PDN_ALL); + regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val); + usleep_range(1000, 1100); + if (val & CS35L33_PDN_DONE) + regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, + CS35L33_MCLKDIS, CS35L33_MCLKDIS); + break; + case SND_SOC_BIAS_OFF: + break; + default: + return -EINVAL; + } + + dapm->bias_level = level; + + return 0; +} + +struct cs35l33_mclk_div { + int mclk; + int srate; + u8 adsp_rate; + u8 int_fs_ratio; +}; + +static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = { + /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */ + {5644800, 11025, 0x4, CS35L33_INT_FS_RATE}, + {5644800, 22050, 0x8, CS35L33_INT_FS_RATE}, + {5644800, 44100, 0xC, CS35L33_INT_FS_RATE}, + + {6000000, 8000, 0x1, 0}, + {6000000, 11025, 0x2, 0}, + {6000000, 11029, 0x3, 0}, + {6000000, 12000, 0x4, 0}, + {6000000, 16000, 0x5, 0}, + {6000000, 22050, 0x6, 0}, + {6000000, 22059, 0x7, 0}, + {6000000, 24000, 0x8, 0}, + {6000000, 32000, 0x9, 0}, + {6000000, 44100, 0xA, 0}, + {6000000, 44118, 0xB, 0}, + {6000000, 48000, 0xC, 0}, + + {6144000, 8000, 0x1, CS35L33_INT_FS_RATE}, + {6144000, 12000, 0x4, CS35L33_INT_FS_RATE}, + {6144000, 16000, 0x5, CS35L33_INT_FS_RATE}, + {6144000, 24000, 0x8, CS35L33_INT_FS_RATE}, + {6144000, 32000, 0x9, CS35L33_INT_FS_RATE}, + {6144000, 48000, 0xC, CS35L33_INT_FS_RATE}, +}; + +static int cs35l33_get_mclk_coeff(int mclk, int srate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) { + if (cs35l33_mclk_coeffs[i].mclk == mclk && + cs35l33_mclk_coeffs[i].srate == srate) + return i; + } + return -EINVAL; +} + +static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL, + CS35L33_MS_MASK, CS35L33_MS_MASK); + dev_dbg(codec->dev, "Audio port in master mode\n"); + break; + case SND_SOC_DAIFMT_CBS_CFS: + regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL, + CS35L33_MS_MASK, 0); + dev_dbg(codec->dev, "Audio port in slave mode\n"); + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + /* + * tdm mode in cs35l33 resembles dsp-a mode very + * closely, it is dsp-a with fsync shifted left by half bclk + */ + priv->is_tdm_mode = true; + dev_dbg(codec->dev, "Audio port in TDM mode\n"); + break; + case SND_SOC_DAIFMT_I2S: + priv->is_tdm_mode = false; + dev_dbg(codec->dev, "Audio port in I2S mode\n"); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + int sample_size = params_width(params); + int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params)); + + if (coeff < 0) + return coeff; + + regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, + CS35L33_ADSP_FS | CS35L33_INT_FS_RATE, + cs35l33_mclk_coeffs[coeff].int_fs_ratio + | cs35l33_mclk_coeffs[coeff].adsp_rate); + + if (priv->is_tdm_mode) { + sample_size = (sample_size / 8) - 1; + if (sample_size > 2) + sample_size = 2; + regmap_update_bits(priv->regmap, CS35L33_RX_AUD, + CS35L33_AUDIN_RX_DEPTH, + sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT); + } + + dev_dbg(codec->dev, "sample rate=%d, bits per sample=%d\n", + params_rate(params), params_width(params)); + + return 0; +} + +static const unsigned int cs35l33_src_rates[] = { + 8000, 11025, 11029, 12000, 16000, 22050, + 22059, 24000, 32000, 44100, 44118, 48000 +}; + +static const struct snd_pcm_hw_constraint_list cs35l33_constraints = { + .count = ARRAY_SIZE(cs35l33_src_rates), + .list = cs35l33_src_rates, +}; + +static int cs35l33_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &cs35l33_constraints); + return 0; +} + +static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + + if (tristate) { + regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, + CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S); + regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, + CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM); + } else { + regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, + CS35L33_SDOUT_3ST_I2S, 0); + regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, + CS35L33_SDOUT_3ST_TDM, 0); + } + + return 0; +} + +static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_codec *codec = dai->codec; + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + unsigned int reg, bit_pos, i; + int slot, slot_num; + + if (slot_width != 8) + return -EINVAL; + + /* scan rx_mask for aud slot */ + slot = ffs(rx_mask) - 1; + if (slot >= 0) { + regmap_update_bits(priv->regmap, CS35L33_RX_AUD, + CS35L33_X_LOC, slot); + dev_dbg(codec->dev, "Audio starts from slots %d", slot); + } + + /* + * scan tx_mask: vmon(2 slots); imon (2 slots); + * vpmon (1 slot) vbstmon (1 slot) + */ + slot = ffs(tx_mask) - 1; + slot_num = 0; + + for (i = 0; i < 2 ; i++) { + /* disable vpmon/vbstmon: enable later if set in tx_mask */ + regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i, + CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE + | CS35L33_X_LOC); + } + + /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/ + snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route, + ARRAY_SIZE(cs35l33_vp_vbst_mon_route)); + + while (slot >= 0) { + /* configure VMON_TX_LOC */ + if (slot_num == 0) { + regmap_update_bits(priv->regmap, CS35L33_TX_VMON, + CS35L33_X_STATE | CS35L33_X_LOC, slot); + dev_dbg(codec->dev, "VMON enabled in slots %d-%d", + slot, slot + 1); + } + + /* configure IMON_TX_LOC */ + if (slot_num == 3) { + regmap_update_bits(priv->regmap, CS35L33_TX_IMON, + CS35L33_X_STATE | CS35L33_X_LOC, slot); + dev_dbg(codec->dev, "IMON enabled in slots %d-%d", + slot, slot + 1); + } + + /* configure VPMON_TX_LOC */ + if (slot_num == 4) { + regmap_update_bits(priv->regmap, CS35L33_TX_VPMON, + CS35L33_X_STATE | CS35L33_X_LOC, slot); + snd_soc_dapm_add_routes(dapm, + &cs35l33_vp_vbst_mon_route[0], 2); + dev_dbg(codec->dev, "VPMON enabled in slots %d", slot); + } + + /* configure VBSTMON_TX_LOC */ + if (slot_num == 5) { + regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON, + CS35L33_X_STATE | CS35L33_X_LOC, slot); + snd_soc_dapm_add_routes(dapm, + &cs35l33_vp_vbst_mon_route[2], 2); + dev_dbg(codec->dev, + "VBSTMON enabled in slots %d", slot); + } + + /* Enable the relevant tx slot */ + reg = CS35L33_TX_EN4 - (slot/8); + bit_pos = slot - ((slot / 8) * (8)); + regmap_update_bits(priv->regmap, reg, + 1 << bit_pos, 1 << bit_pos); + + tx_mask &= ~(1 << slot); + slot = ffs(tx_mask) - 1; + slot_num++; + } + + return 0; +} + +static int cs35l33_codec_set_sysclk(struct snd_soc_codec *codec, + int clk_id, int source, unsigned int freq, int dir) +{ + struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec); + + switch (freq) { + case CS35L33_MCLK_5644: + case CS35L33_MCLK_6: + case CS35L33_MCLK_6144: + regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, + CS35L33_MCLKDIV2, 0); + cs35l33->mclk_int = freq; + break; + case CS35L33_MCLK_11289: + case CS35L33_MCLK_12: + case CS35L33_MCLK_12288: + regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, + CS35L33_MCLKDIV2, CS35L33_MCLKDIV2); + cs35l33->mclk_int = freq/2; + break; + default: + cs35l33->mclk_int = 0; + return -EINVAL; + } + + dev_dbg(codec->dev, "external mclk freq=%d, internal mclk freq=%d\n", + freq, cs35l33->mclk_int); + + return 0; +} + +static const struct snd_soc_dai_ops cs35l33_ops = { + .startup = cs35l33_pcm_startup, + .set_tristate = cs35l33_set_tristate, + .set_fmt = cs35l33_set_dai_fmt, + .hw_params = cs35l33_pcm_hw_params, + .set_tdm_slot = cs35l33_set_tdm_slot, +}; + +static struct snd_soc_dai_driver cs35l33_dai = { + .name = "cs35l33-dai", + .id = 0, + .playback = { + .stream_name = "CS35L33 Playback", + .channels_min = 1, + .channels_max = 1, + .rates = CS35L33_RATES, + .formats = CS35L33_FORMATS, + }, + .capture = { + .stream_name = "CS35L33 Capture", + .channels_min = 2, + .channels_max = 2, + .rates = CS35L33_RATES, + .formats = CS35L33_FORMATS, + }, + .ops = &cs35l33_ops, + .symmetric_rates = 1, +}; + +static int cs35l33_set_hg_data(struct snd_soc_codec *codec, + struct cs35l33_pdata *pdata) +{ + struct cs35l33_hg *hg_config = &pdata->hg_config; + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec); + + if (hg_config->enable_hg_algo) { + regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, + CS35L33_MEM_DEPTH_MASK, + hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT); + regmap_write(priv->regmap, CS35L33_HG_REL_RATE, + hg_config->release_rate); + regmap_update_bits(priv->regmap, CS35L33_HG_HEAD, + CS35L33_HD_RM_MASK, + hg_config->hd_rm << CS35L33_HD_RM_SHIFT); + regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, + CS35L33_LDO_THLD_MASK, + hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT); + regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, + CS35L33_LDO_DISABLE_MASK, + hg_config->ldo_path_disable << + CS35L33_LDO_DISABLE_SHIFT); + regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, + CS35L33_LDO_ENTRY_DELAY_MASK, + hg_config->ldo_entry_delay << + CS35L33_LDO_ENTRY_DELAY_SHIFT); + if (hg_config->vp_hg_auto) { + regmap_update_bits(priv->regmap, CS35L33_HG_EN, + CS35L33_VP_HG_AUTO_MASK, + CS35L33_VP_HG_AUTO_MASK); + snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route, + ARRAY_SIZE(cs35l33_vphg_auto_route)); + } + regmap_update_bits(priv->regmap, CS35L33_HG_EN, + CS35L33_VP_HG_MASK, + hg_config->vp_hg << CS35L33_VP_HG_SHIFT); + regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, + CS35L33_VP_HG_RATE_MASK, + hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT); + regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, + CS35L33_VP_HG_VA_MASK, + hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT); + regmap_update_bits(priv->regmap, CS35L33_HG_EN, + CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK); + } + return 0; +} + +static int cs35l33_probe(struct snd_soc_codec *codec) +{ + struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec); + + cs35l33->codec = codec; + pm_runtime_get_sync(codec->dev); + + regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL, + CS35L33_ALIVE_WD_DIS, 0x8); + regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2, + CS35L33_ALIVE_WD_DIS2, + CS35L33_ALIVE_WD_DIS2); + + /* Set Platform Data */ + regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1, + CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl); + regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL, + CS35L33_AMP_DRV_SEL_MASK, + cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT); + + if (cs35l33->pdata.boost_ipk) + regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL, + cs35l33->pdata.boost_ipk); + + if (cs35l33->enable_soft_ramp) { + snd_soc_update_bits(codec, CS35L33_DAC_CTL, + CS35L33_DIGSFT, CS35L33_DIGSFT); + snd_soc_update_bits(codec, CS35L33_DAC_CTL, + CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate); + } else { + snd_soc_update_bits(codec, CS35L33_DAC_CTL, + CS35L33_DIGSFT, 0); + } + + /* update IMON scaling rate if different from default of 0x8 */ + if (cs35l33->pdata.imon_adc_scale != 0x8) + snd_soc_update_bits(codec, CS35L33_ADC_CTL, + CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale); + + cs35l33_set_hg_data(codec, &(cs35l33->pdata)); + + /* + * unmask important interrupts that causes the chip to enter + * speaker safe mode and hence deserves user attention + */ + regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1, + CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT | + CS35L33_M_CAL_ERR, 0); + + pm_runtime_put_sync(codec->dev); + + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_cs35l33 = { + .probe = cs35l33_probe, + + .set_bias_level = cs35l33_set_bias_level, + .set_sysclk = cs35l33_codec_set_sysclk, + + .dapm_widgets = cs35l33_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs35l33_dapm_widgets), + .dapm_routes = cs35l33_audio_map, + .num_dapm_routes = ARRAY_SIZE(cs35l33_audio_map), + .controls = cs35l33_snd_controls, + .num_controls = ARRAY_SIZE(cs35l33_snd_controls), + + .idle_bias_off = true, +}; + +static const struct regmap_config cs35l33_regmap = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = CS35L33_MAX_REGISTER, + .reg_defaults = cs35l33_reg, + .num_reg_defaults = ARRAY_SIZE(cs35l33_reg), + .volatile_reg = cs35l33_volatile_register, + .readable_reg = cs35l33_readable_register, + .writeable_reg = cs35l33_writeable_register, + .cache_type = REGCACHE_RBTREE, + .use_single_rw = true, +}; + +static int cs35l33_runtime_resume(struct device *dev) +{ + struct cs35l33_private *cs35l33 = dev_get_drvdata(dev); + int ret; + + dev_dbg(dev, "%s\n", __func__); + + if (cs35l33->reset_gpio) + gpiod_set_value_cansleep(cs35l33->reset_gpio, 0); + + ret = regulator_bulk_enable(cs35l33->num_core_supplies, + cs35l33->core_supplies); + if (ret != 0) { + dev_err(dev, "Failed to enable core supplies: %d\n", ret); + return ret; + } + + regcache_cache_only(cs35l33->regmap, false); + + if (cs35l33->reset_gpio) + gpiod_set_value_cansleep(cs35l33->reset_gpio, 1); + + msleep(CS35L33_BOOT_DELAY); + + ret = regcache_sync(cs35l33->regmap); + if (ret != 0) { + dev_err(dev, "Failed to restore register cache\n"); + goto err; + } + + return 0; + +err: + regcache_cache_only(cs35l33->regmap, true); + regulator_bulk_disable(cs35l33->num_core_supplies, + cs35l33->core_supplies); + + return ret; +} + +static int cs35l33_runtime_suspend(struct device *dev) +{ + struct cs35l33_private *cs35l33 = dev_get_drvdata(dev); + + dev_dbg(dev, "%s\n", __func__); + + /* redo the calibration in next power up */ + cs35l33->amp_cal = false; + + regcache_cache_only(cs35l33->regmap, true); + regcache_mark_dirty(cs35l33->regmap); + regulator_bulk_disable(cs35l33->num_core_supplies, + cs35l33->core_supplies); + + return 0; +} + +static const struct dev_pm_ops cs35l33_pm_ops = { + SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend, + cs35l33_runtime_resume, + NULL) +}; + +static int cs35l33_get_hg_data(const struct device_node *np, + struct cs35l33_pdata *pdata) +{ + struct device_node *hg; + struct cs35l33_hg *hg_config = &pdata->hg_config; + u32 val32; + + hg = of_get_child_by_name(np, "hg-algo"); + hg_config->enable_hg_algo = hg ? true : false; + + if (hg_config->enable_hg_algo) { + if (of_property_read_u32(hg, "mem-depth", &val32) >= 0) + hg_config->mem_depth = val32; + if (of_property_read_u32(hg, "release-rate", &val32) >= 0) + hg_config->release_rate = val32; + if (of_property_read_u32(hg, "hd-rm", &val32) >= 0) + hg_config->hd_rm = val32; + if (of_property_read_u32(hg, "ldo-thld", &val32) >= 0) + hg_config->ldo_thld = val32; + if (of_property_read_u32(hg, "ldo-path-disable", &val32) >= 0) + hg_config->ldo_path_disable = val32; + if (of_property_read_u32(hg, "ldo-entry-delay", &val32) >= 0) + hg_config->ldo_entry_delay = val32; + hg_config->vp_hg_auto = of_property_read_bool(hg, "vp-hg-auto"); + if (of_property_read_u32(hg, "vp-hg", &val32) >= 0) + hg_config->vp_hg = val32; + if (of_property_read_u32(hg, "vp-hg-rate", &val32) >= 0) + hg_config->vp_hg_rate = val32; + if (of_property_read_u32(hg, "vp-hg-va", &val32) >= 0) + hg_config->vp_hg_va = val32; + } + + of_node_put(hg); + + return 0; +} + +static irqreturn_t cs35l33_irq_thread(int irq, void *data) +{ + struct cs35l33_private *cs35l33 = data; + struct snd_soc_codec *codec = cs35l33->codec; + unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2; + int i; + + regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2, + &sticky_val2); + regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1, + &sticky_val1); + regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2); + regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1); + + /* Check to see if the unmasked bits are active, + * if not then exit. + */ + if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2)) + return IRQ_NONE; + + regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1, + &current_val); + + /* handle the interrupts */ + + if (sticky_val1 & CS35L33_AMP_SHORT) { + dev_crit(codec->dev, "Amp short error\n"); + if (!(current_val & CS35L33_AMP_SHORT)) { + dev_dbg(codec->dev, + "Amp short error release\n"); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, + CS35L33_AMP_SHORT_RLS, 0); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, + CS35L33_AMP_SHORT_RLS, + CS35L33_AMP_SHORT_RLS); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS, + 0); + } + } + + if (sticky_val1 & CS35L33_CAL_ERR) { + dev_err(codec->dev, "Cal error\n"); + + /* redo the calibration in next power up */ + cs35l33->amp_cal = false; + + if (!(current_val & CS35L33_CAL_ERR)) { + dev_dbg(codec->dev, "Cal error release\n"); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, + 0); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, + CS35L33_CAL_ERR_RLS); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, + 0); + } + } + + if (sticky_val1 & CS35L33_OTE) { + dev_crit(codec->dev, "Over temperature error\n"); + if (!(current_val & CS35L33_OTE)) { + dev_dbg(codec->dev, + "Over temperature error release\n"); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_OTE_RLS, + CS35L33_OTE_RLS); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0); + } + } + + if (sticky_val1 & CS35L33_OTW) { + dev_err(codec->dev, "Over temperature warning\n"); + if (!(current_val & CS35L33_OTW)) { + dev_dbg(codec->dev, + "Over temperature warning release\n"); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_OTW_RLS, + CS35L33_OTW_RLS); + regmap_update_bits(cs35l33->regmap, + CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0); + } + } + if (CS35L33_ALIVE_ERR & sticky_val1) + dev_err(codec->dev, "ERROR: ADSPCLK Interrupt\n"); + + if (CS35L33_MCLK_ERR & sticky_val1) + dev_err(codec->dev, "ERROR: MCLK Interrupt\n"); + + if (CS35L33_VMON_OVFL & sticky_val2) + dev_err(codec->dev, + "ERROR: VMON Overflow Interrupt\n"); + + if (CS35L33_IMON_OVFL & sticky_val2) + dev_err(codec->dev, + "ERROR: IMON Overflow Interrupt\n"); + + if (CS35L33_VPMON_OVFL & sticky_val2) + dev_err(codec->dev, + "ERROR: VPMON Overflow Interrupt\n"); + + if (CS35L33_VBSTMON_OVFL & sticky_val2) + dev_err(codec->dev, + "ERROR: VPMON Overflow Interrupt\n"); + + /* Make sure that the bits are cleared */ + for (i = 0; i < CS35L33_INT_ATTEMPTS; i++) { + regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1, + &sticky_val1); + regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2, + &sticky_val2); + + if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2)) + break; + } + + if (i == CS35L33_INT_ATTEMPTS) + dev_warn(codec->dev, "WARN: Interrupts may not be cleared\n"); + + return IRQ_HANDLED; +} + +static const char * const cs35l33_core_supplies[] = { + "VA", + "VP", +}; + +static int cs35l33_of_get_pdata(struct device *dev, + struct cs35l33_private *cs35l33) +{ + struct device_node *np = dev->of_node; + struct cs35l33_pdata *pdata = &cs35l33->pdata; + u32 val32; + + if (!np) + return 0; + + if (of_property_read_u32(np, "boost-ctl", &val32) >= 0) { + pdata->boost_ctl = val32; + pdata->amp_drv_sel = 1; + } + + if (of_property_read_u32(np, "ramp-rate", &val32) >= 0) { + pdata->ramp_rate = val32; + cs35l33->enable_soft_ramp = true; + } + + if (of_property_read_u32(np, "boost-ipk", &val32) >= 0) + pdata->boost_ipk = val32; + + if (of_property_read_u32(np, "imon-adc-scale", &val32) >= 0) { + if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6)) + pdata->imon_adc_scale = val32; + else + /* use default value */ + pdata->imon_adc_scale = 0x8; + } else { + /* use default value */ + pdata->imon_adc_scale = 0x8; + } + + cs35l33_get_hg_data(np, pdata); + + return 0; +} + +static int cs35l33_i2c_probe(struct i2c_client *i2c_client, + const struct i2c_device_id *id) +{ + struct cs35l33_private *cs35l33; + struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev); + int ret, devid, i; + unsigned int reg; + + cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private), + GFP_KERNEL); + if (!cs35l33) + return -ENOMEM; + + i2c_set_clientdata(i2c_client, cs35l33); + cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap); + if (IS_ERR(cs35l33->regmap)) { + ret = PTR_ERR(cs35l33->regmap); + dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); + return ret; + } + + regcache_cache_only(cs35l33->regmap, true); + + for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++) + cs35l33->core_supplies[i].supply + = cs35l33_core_supplies[i]; + cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies); + + ret = devm_regulator_bulk_get(&i2c_client->dev, + cs35l33->num_core_supplies, + cs35l33->core_supplies); + if (ret != 0) { + dev_err(&i2c_client->dev, + "Failed to request core supplies: %d\n", + ret); + return ret; + } + + if (pdata) { + cs35l33->pdata = *pdata; + } else { + cs35l33_of_get_pdata(&i2c_client->dev, cs35l33); + pdata = &cs35l33->pdata; + } + + ret = request_threaded_irq(i2c_client->irq, NULL, cs35l33_irq_thread, + IRQF_ONESHOT | IRQF_TRIGGER_LOW, "cs35l33", cs35l33); + if (ret != 0) + dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret); + + /* We could issue !RST or skip it based on AMP topology */ + cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, + "reset-gpios", GPIOD_OUT_HIGH); + + if (PTR_ERR(cs35l33->reset_gpio) == -ENOENT) { + dev_warn(&i2c_client->dev, + "%s WARNING: No reset gpio assigned\n", __func__); + } else if (IS_ERR(cs35l33->reset_gpio)) { + dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n", + __func__); + return PTR_ERR(cs35l33->reset_gpio); + } + + ret = regulator_bulk_enable(cs35l33->num_core_supplies, + cs35l33->core_supplies); + if (ret != 0) { + dev_err(&i2c_client->dev, + "Failed to enable core supplies: %d\n", + ret); + goto err_irq; + } + + if (cs35l33->reset_gpio) + gpiod_set_value_cansleep(cs35l33->reset_gpio, 1); + + msleep(CS35L33_BOOT_DELAY); + regcache_cache_only(cs35l33->regmap, false); + + /* initialize codec */ + ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_AB, &reg); + devid = (reg & 0xFF) << 12; + ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_CD, &reg); + devid |= (reg & 0xFF) << 4; + ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_E, &reg); + devid |= (reg & 0xF0) >> 4; + + if (devid != CS35L33_CHIP_ID) { + dev_err(&i2c_client->dev, + "CS35L33 Device ID (%X). Expected ID %X\n", + devid, CS35L33_CHIP_ID); + goto err_enable; + } + + ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg); + if (ret < 0) { + dev_err(&i2c_client->dev, "Get Revision ID failed\n"); + goto err_enable; + } + + dev_info(&i2c_client->dev, + "Cirrus Logic CS35L33, Revision: %02X\n", ret & 0xFF); + + ret = regmap_register_patch(cs35l33->regmap, + cs35l33_patch, ARRAY_SIZE(cs35l33_patch)); + if (ret < 0) { + dev_err(&i2c_client->dev, + "Error in applying regmap patch: %d\n", ret); + goto err_enable; + } + + /* disable mclk and tdm */ + regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, + CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM, + CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM); + + pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100); + pm_runtime_use_autosuspend(&i2c_client->dev); + pm_runtime_set_active(&i2c_client->dev); + pm_runtime_enable(&i2c_client->dev); + + ret = snd_soc_register_codec(&i2c_client->dev, + &soc_codec_dev_cs35l33, &cs35l33_dai, 1); + if (ret < 0) { + dev_err(&i2c_client->dev, "%s: Register codec failed\n", + __func__); + goto err_irq; + } + + return 0; + +err_enable: + regulator_bulk_disable(cs35l33->num_core_supplies, + cs35l33->core_supplies); +err_irq: + free_irq(i2c_client->irq, cs35l33); + + return ret; +} + +static int cs35l33_i2c_remove(struct i2c_client *client) +{ + struct cs35l33_private *cs35l33 = i2c_get_clientdata(client); + + snd_soc_unregister_codec(&client->dev); + + if (cs35l33->reset_gpio) + gpiod_set_value_cansleep(cs35l33->reset_gpio, 0); + + pm_runtime_disable(&client->dev); + regulator_bulk_disable(cs35l33->num_core_supplies, + cs35l33->core_supplies); + free_irq(client->irq, cs35l33); + + return 0; +} + +static const struct of_device_id cs35l33_of_match[] = { + { .compatible = "cirrus,cs35l33", }, + {}, +}; +MODULE_DEVICE_TABLE(of, cs35l33_of_match); + +static const struct i2c_device_id cs35l33_id[] = { + {"cs35l33", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, cs35l33_id); + +static struct i2c_driver cs35l33_i2c_driver = { + .driver = { + .name = "cs35l33", + .owner = THIS_MODULE, + .pm = &cs35l33_pm_ops, + .of_match_table = cs35l33_of_match, + + }, + .id_table = cs35l33_id, + .probe = cs35l33_i2c_probe, + .remove = cs35l33_i2c_remove, + +}; +module_i2c_driver(cs35l33_i2c_driver); + +MODULE_DESCRIPTION("ASoC CS35L33 driver"); +MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan(a)cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/cs35l33.h b/sound/soc/codecs/cs35l33.h new file mode 100644 index 0000000..c045737 --- /dev/null +++ b/sound/soc/codecs/cs35l33.h @@ -0,0 +1,221 @@ +/* + * cs35l33.h -- CS35L33 ALSA SoC audio driver + * + * Copyright 2016 Cirrus Logic, Inc. + * + * Author: Paul Handrigan <paul.handrigan(a)cirrus.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __CS35L33_H__ +#define __CS35L33_H__ + +#define CS35L33_CHIP_ID 0x00035A33 +#define CS35L33_DEVID_AB 0x01 /* Device ID A & B [RO] */ +#define CS35L33_DEVID_CD 0x02 /* Device ID C & D [RO] */ +#define CS35L33_DEVID_E 0x03 /* Device ID E [RO] */ +#define CS35L33_FAB_ID 0x04 /* Fab ID [RO] */ +#define CS35L33_REV_ID 0x05 /* Revision ID [RO] */ +#define CS35L33_PWRCTL1 0x06 /* Power Ctl 1 */ +#define CS35L33_PWRCTL2 0x07 /* Power Ctl 2 */ +#define CS35L33_CLK_CTL 0x08 /* Clock Ctl */ +#define CS35L33_BST_PEAK_CTL 0x09 /* Max Current for Boost */ +#define CS35L33_PROTECT_CTL 0x0A /* Amp Protection Parameters */ +#define CS35L33_BST_CTL1 0x0B /* Boost Converter CTL1 */ +#define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */ +#define CS35L33_ADSP_CTL 0x0D /* Serial Port Control */ +#define CS35L33_ADC_CTL 0x0E /* ADC Control */ +#define CS35L33_DAC_CTL 0x0F /* DAC Control */ +#define CS35L33_DIG_VOL_CTL 0x10 /* Digital Volume CTL */ +#define CS35L33_CLASSD_CTL 0x11 /* Class D Amp CTL */ +#define CS35L33_AMP_CTL 0x12 /* Amp Gain/Protecton Release CTL */ +#define CS35L33_INT_MASK_1 0x13 /* Interrupt Mask 1 */ +#define CS35L33_INT_MASK_2 0x14 /* Interrupt Mask 2 */ +#define CS35L33_INT_STATUS_1 0x15 /* Interrupt Status 1 [RO] */ +#define CS35L33_INT_STATUS_2 0x16 /* Interrupt Status 2 [RO] */ +#define CS35L33_DIAG_LOCK 0x17 /* Diagnostic Mode Register Lock */ +#define CS35L33_DIAG_CTRL_1 0x18 /* Diagnostic Mode Register Control */ +#define CS35L33_DIAG_CTRL_2 0x19 /* Diagnostic Mode Register Control 2 */ +#define CS35L33_HG_MEMLDO_CTL 0x23 /* H/G Memory/LDO CTL */ +#define CS35L33_HG_REL_RATE 0x24 /* H/G Release Rate */ +#define CS35L33_LDO_DEL 0x25 /* LDO Entry Delay/VPhg Control 1 */ +#define CS35L33_HG_HEAD 0x29 /* H/G Headroom */ +#define CS35L33_HG_EN 0x2A /* H/G Enable/VPhg CNT2 */ +#define CS35L33_TX_VMON 0x2D /* TDM TX Control 1 (VMON) */ +#define CS35L33_TX_IMON 0x2E /* TDM TX Control 2 (IMON) */ +#define CS35L33_TX_VPMON 0x2F /* TDM TX Control 3 (VPMON) */ +#define CS35L33_TX_VBSTMON 0x30 /* TDM TX Control 4 (VBSTMON) */ +#define CS35L33_TX_FLAG 0x31 /* TDM TX Control 5 (FLAG) */ +#define CS35L33_TX_EN1 0x32 /* TDM TX Enable 1 */ +#define CS35L33_TX_EN2 0x33 /* TDM TX Enable 2 */ +#define CS35L33_TX_EN3 0x34 /* TDM TX Enable 3 */ +#define CS35L33_TX_EN4 0x35 /* TDM TX Enable 4 */ +#define CS35L33_RX_AUD 0x36 /* TDM RX Control 1 */ +#define CS35L33_RX_SPLY 0x37 /* TDM RX Control 2 */ +#define CS35L33_RX_ALIVE 0x38 /* TDM RX Control 3 */ +#define CS35L33_BST_CTL4 0x39 /* Boost Converter Control 4 */ +#define CS35L33_HG_STATUS 0x3F /* H/G Status */ +#define CS35L33_MAX_REGISTER 0x59 + +#define CS35L33_MCLK_5644 5644800 +#define CS35L33_MCLK_6144 6144000 +#define CS35L33_MCLK_6 6000000 +#define CS35L33_MCLK_11289 11289600 +#define CS35L33_MCLK_12 12000000 +#define CS35L33_MCLK_12288 12288000 + +/* CS35L33_PWRCTL1 */ +#define CS35L33_PDN_AMP (1 << 7) +#define CS35L33_PDN_BST (1 << 2) +#define CS35L33_PDN_ALL 1 + +/* CS35L33_PWRCTL2 */ +#define CS35L33_PDN_VMON_SHIFT 7 +#define CS35L33_PDN_VMON (1 << CS35L33_PDN_VMON_SHIFT) +#define CS35L33_PDN_IMON_SHIFT 6 +#define CS35L33_PDN_IMON (1 << CS35L33_PDN_IMON_SHIFT) +#define CS35L33_PDN_VPMON_SHIFT 5 +#define CS35L33_PDN_VPMON (1 << CS35L33_PDN_VPMON_SHIFT) +#define CS35L33_PDN_VBSTMON_SHIFT 4 +#define CS35L33_PDN_VBSTMON (1 << CS35L33_PDN_VBSTMON_SHIFT) +#define CS35L33_SDOUT_3ST_I2S_SHIFT 3 +#define CS35L33_SDOUT_3ST_I2S (1 << CS35L33_SDOUT_3ST_I2S_SHIFT) +#define CS35L33_PDN_SDIN_SHIFT 2 +#define CS35L33_PDN_SDIN (1 << CS35L33_PDN_SDIN_SHIFT) +#define CS35L33_PDN_TDM_SHIFT 1 +#define CS35L33_PDN_TDM (1 << CS35L33_PDN_TDM_SHIFT) + +/* CS35L33_CLK_CTL */ +#define CS35L33_MCLKDIS (1 << 7) +#define CS35L33_MCLKDIV2 (1 << 6) +#define CS35L33_SDOUT_3ST_TDM (1 << 5) +#define CS35L33_INT_FS_RATE (1 << 4) +#define CS35L33_ADSP_FS 0xF + +/* CS35L33_PROTECT_CTL */ +#define CS35L33_ALIVE_WD_DIS (3 << 2) + +/* CS35L33_BST_CTL1 */ +#define CS35L33_BST_CTL_SRC (1 << 6) +#define CS35L33_BST_CTL_SHIFT (1 << 5) +#define CS35L33_BST_CTL_MASK 0x3F + +/* CS35L33_BST_CTL2 */ +#define CS35L33_TDM_WD_SEL (1 << 4) +#define CS35L33_ALIVE_WD_DIS2 (1 << 3) +#define CS35L33_VBST_SR_STEP 0x3 + +/* CS35L33_ADSP_CTL */ +#define CS35L33_ADSP_DRIVE (1 << 7) +#define CS35L33_MS_MASK (1 << 6) +#define CS35L33_SDIN_LOC (3 << 4) +#define CS35L33_ALIVE_RATE 0x3 + +/* CS35L33_ADC_CTL */ +#define CS35L33_INV_VMON (1 << 7) +#define CS35L33_INV_IMON (1 << 6) +#define CS35L33_ADC_NOTCH_DIS (1 << 5) +#define CS35L33_IMON_SCALE 0xF + +/* CS35L33_DAC_CTL */ +#define CS35L33_INV_DAC (1 << 7) +#define CS35L33_DAC_NOTCH_DIS (1 << 5) +#define CS35L33_DIGSFT (1 << 4) +#define CS35L33_DSR_RATE 0xF + +/* CS35L33_CLASSD_CTL */ +#define CS35L33_AMP_SD (1 << 6) +#define CS35L33_AMP_DRV_SEL_SRC (1 << 5) +#define CS35L33_AMP_DRV_SEL_MASK 0x10 +#define CS35L33_AMP_DRV_SEL_SHIFT 4 +#define CS35L33_AMP_CAL (1 << 3) +#define CS35L33_GAIN_CHG_ZC_MASK 0x04 +#define CS35L33_GAIN_CHG_ZC_SHIFT 2 +#define CS35L33_CLASS_D_CTL_MASK 0x3F + +/* CS35L33_AMP_CTL */ +#define CS35L33_AMP_GAIN 0xF0 +#define CS35L33_CAL_ERR_RLS (1 << 3) +#define CS35L33_AMP_SHORT_RLS (1 << 2) +#define CS35L33_OTW_RLS (1 << 1) +#define CS35L33_OTE_RLS 1 + +/* CS35L33_INT_MASK_1 */ +#define CS35L33_M_CAL_ERR_SHIFT 6 +#define CS35L33_M_CAL_ERR (1 << CS35L33_M_CAL_ERR_SHIFT) +#define CS35L33_M_ALIVE_ERR_SHIFT 5 +#define CS35L33_M_ALIVE_ERR (1 << CS35L33_M_ALIVE_ERR_SHIFT) +#define CS35L33_M_AMP_SHORT_SHIFT 2 +#define CS35L33_M_AMP_SHORT (1 << CS35L33_M_AMP_SHORT_SHIFT) +#define CS35L33_M_OTW_SHIFT 1 +#define CS35L33_M_OTW (1 << CS35L33_M_OTW_SHIFT) +#define CS35L33_M_OTE_SHIFT 0 +#define CS35L33_M_OTE (1 << CS35L33_M_OTE_SHIFT) + +/* CS35L33_INT_STATUS_1 */ +#define CS35L33_CAL_ERR (1 << 6) +#define CS35L33_ALIVE_ERR (1 << 5) +#define CS35L33_ADSPCLK_ERR (1 << 4) +#define CS35L33_MCLK_ERR (1 << 3) +#define CS35L33_AMP_SHORT (1 << 2) +#define CS35L33_OTW (1 << 1) +#define CS35L33_OTE (1 << 0) + +/* CS35L33_INT_STATUS_2 */ +#define CS35L33_VMON_OVFL (1 << 7) +#define CS35L33_IMON_OVFL (1 << 6) +#define CS35L33_VPMON_OVFL (1 << 5) +#define CS35L33_VBSTMON_OVFL (1 << 4) +#define CS35L33_PDN_DONE 1 + +/* CS35L33_BST_CTL4 */ +#define CS35L33_BST_RGS 0x70 +#define CS35L33_BST_COEFF3 0xF + +/* CS35L33_HG_MEMLDO_CTL */ +#define CS35L33_MEM_DEPTH_SHIFT 5 +#define CS35L33_MEM_DEPTH_MASK (0x3 << CS35L33_MEM_DEPTH_SHIFT) +#define CS35L33_LDO_THLD_SHIFT 1 +#define CS35L33_LDO_THLD_MASK (0xF << CS35L33_LDO_THLD_SHIFT) +#define CS35L33_LDO_DISABLE_SHIFT 0 +#define CS35L33_LDO_DISABLE_MASK (0x1 << CS35L33_LDO_DISABLE_SHIFT) + +/* CS35L33_LDO_DEL */ +#define CS35L33_VP_HG_VA_SHIFT 5 +#define CS35L33_VP_HG_VA_MASK (0x7 << CS35L33_VP_HG_VA_SHIFT) +#define CS35L33_LDO_ENTRY_DELAY_SHIFT 2 +#define CS35L33_LDO_ENTRY_DELAY_MASK (0x7 << CS35L33_LDO_ENTRY_DELAY_SHIFT) +#define CS35L33_VP_HG_RATE_SHIFT 0 +#define CS35L33_VP_HG_RATE_MASK (0x3 << CS35L33_VP_HG_RATE_SHIFT) + +/* CS35L33_HG_HEAD */ +#define CS35L33_HD_RM_SHIFT 0 +#define CS35L33_HD_RM_MASK (0x7F << CS35L33_HD_RM_SHIFT) + +/* CS35L33_HG_EN */ +#define CS35L33_CLASS_HG_ENA_SHIFT 7 +#define CS35L33_CLASS_HG_EN_MASK (0x1 << CS35L33_CLASS_HG_ENA_SHIFT) +#define CS35L33_VP_HG_AUTO_SHIFT 6 +#define CS35L33_VP_HG_AUTO_MASK (0x1 << 6) +#define CS35L33_VP_HG_SHIFT 0 +#define CS35L33_VP_HG_MASK (0x1F << CS35L33_VP_HG_SHIFT) + +#define CS35L33_RATES (SNDRV_PCM_RATE_8000_48000) +#define CS35L33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +/* CS35L33_{RX,TX}_X */ +#define CS35L33_X_STATE_SHIFT 7 +#define CS35L33_X_STATE (1 << CS35L33_X_STATE_SHIFT) +#define CS35L33_X_LOC_SHIFT 0 +#define CS35L33_X_LOC (0x1F << CS35L33_X_LOC_SHIFT) + +/* CS35L33_RX_AUD */ +#define CS35L33_AUDIN_RX_DEPTH_SHIFT 5 +#define CS35L33_AUDIN_RX_DEPTH (0x7 << CS35L33_AUDIN_RX_DEPTH_SHIFT) + +#endif -- 1.9.1

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[alsa-devel] [PATCH] ASoC: atmel: fix build failure
by Sudip Mukherjee 06 Jun '16

06 Jun '16

m32r allmodconfig build is failing with the error: ERROR: "bad_dma_ops" [sound/soc/atmel/snd-soc-atmel-pcm-pdc.ko] undefined! The code is using DMA but the related dependency is not mentioned in the Kconfig. Signed-off-by: Sudip Mukherjee <sudip.mukherjee(a)codethink.co.uk> --- build log is at: https://travis-ci.org/sudipm-mukherjee/parport/jobs/134651165 sound/soc/atmel/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig index 06e099e..22aec9a 100644 --- a/sound/soc/atmel/Kconfig +++ b/sound/soc/atmel/Kconfig @@ -10,6 +10,7 @@ if SND_ATMEL_SOC config SND_ATMEL_SOC_PDC tristate + depends on HAS_DMA default m if SND_ATMEL_SOC_SSC_PDC=m && SND_ATMEL_SOC_SSC=m default y if SND_ATMEL_SOC_SSC_PDC=y || (SND_ATMEL_SOC_SSC_PDC=m && SND_ATMEL_SOC_SSC=y) -- 1.9.1

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[alsa-devel] [PATCH] ASoC: rt298: remove idle_bias_off = true
by Bard Liao 06 Jun '16

06 Jun '16

From: bardliao <bardliao(a)realtek.com> Codec will not go into suspend if there is any widget forced on with idle_bias_off true. We want codec go into suspend when the system is suspend. Also, we don't do anything in bias level OFF case. So it is actually no different in bias level STANDBY or OFF case. Signed-off-by: Bard Liao <bardliao(a)realtek.com> --- sound/soc/codecs/rt298.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/soc/codecs/rt298.c b/sound/soc/codecs/rt298.c index f80cfe4..d403c20 100644 --- a/sound/soc/codecs/rt298.c +++ b/sound/soc/codecs/rt298.c @@ -1094,7 +1094,6 @@ static struct snd_soc_codec_driver soc_codec_dev_rt298 = { .suspend = rt298_suspend, .resume = rt298_resume, .set_bias_level = rt298_set_bias_level, - .idle_bias_off = true, .controls = rt298_snd_controls, .num_controls = ARRAY_SIZE(rt298_snd_controls), .dapm_widgets = rt298_dapm_widgets, -- 1.8.1.1.439.g50a6b54

3 4

[alsa-devel] [PATCH v5] ASoC: cs53l30: Add support for Cirrus Logic CS53L30
by tim.howe＠cirrus.com 06 Jun '16

06 Jun '16

From: Tim Howe <tim.howe(a)cirrus.com> Signed-off-by: Tim Howe <tim.howe(a)cirrus.com> --- .../devicetree/bindings/sound/cs53l30.txt | 21 + sound/soc/codecs/Kconfig | 6 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs53l30.c | 943 +++++++++++++++++++++ sound/soc/codecs/cs53l30.h | 282 ++++++ 5 files changed, 1254 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cs53l30.txt create mode 100644 sound/soc/codecs/cs53l30.c create mode 100644 sound/soc/codecs/cs53l30.h diff --git a/Documentation/devicetree/bindings/sound/cs53l30.txt b/Documentation/devicetree/bindings/sound/cs53l30.txt new file mode 100644 index 0000000..a2dff95 +++ b/Documentation/devicetree/bindings/sound/cs53l30.txt @@ -0,0 +1,21 @@ +CS53L30 audio CODEC + +Required properties: + + - compatible : "cirrus,cs53l30" + + - reg : the I2C address of the device + +Optional properties: + + - reset-gpios : a GPIO spec for the reset pin. + + +Example: + +codec: cs53l30@48 { + compatible = "cirrus,cs53l30"; + reg = <0x48>; + reset-gpios = <&gpio 54 0>; +}; + diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index b282169..2dd97d4 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -60,6 +60,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_CS4271_SPI if SPI_MASTER select SND_SOC_CS42XX8_I2C if I2C select SND_SOC_CS4349 if I2C + select SND_SOC_CS53L30 if I2C select SND_SOC_CX20442 if TTY select SND_SOC_DA7210 if SND_SOC_I2C_AND_SPI select SND_SOC_DA7213 if I2C @@ -449,6 +450,11 @@ config SND_SOC_CS4349 tristate "Cirrus Logic CS4349 CODEC" depends on I2C +# Cirrus Logic Quad-Channel ADC +config SND_SOC_CS53L30 + tristate "Cirrus Logic CS53L30 CODEC" + depends on I2C + config SND_SOC_CX20442 tristate depends on TTY diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 81324bc..88dff59 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -52,6 +52,7 @@ snd-soc-cs4271-spi-objs := cs4271-spi.o snd-soc-cs42xx8-objs := cs42xx8.o snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o snd-soc-cs4349-objs := cs4349.o +snd-soc-cs53l30-objs := cs53l30.o snd-soc-cx20442-objs := cx20442.o snd-soc-da7210-objs := da7210.o snd-soc-da7213-objs := da7213.o @@ -252,6 +253,7 @@ obj-$(CONFIG_SND_SOC_CS4271_SPI) += snd-soc-cs4271-spi.o obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o +obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o diff --git a/sound/soc/codecs/cs53l30.c b/sound/soc/codecs/cs53l30.c new file mode 100644 index 0000000..2002ecd +++ b/sound/soc/codecs/cs53l30.c @@ -0,0 +1,943 @@ +/* + * cs53l30.c -- CS53l30 ALSA Soc Audio driver + * + * Copyright 2015 Cirrus Logic, Inc. + * + * Authors: Paul Handrigan <Paul.Handrigan(a)cirrus.com>, + * Tim Howe <Tim.Howe(a)cirrus.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/gpio/consumer.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include "cs53l30.h" + +struct cs53l30_private { + struct regmap *regmap; + struct gpio_desc *reset_gpio; + u8 asp_config_ctl; + u32 mclk; +}; + +static const struct reg_default cs53l30_reg_defaults[] = { + { CS53L30_PWRCTL, CS53L30_THMS_PDN }, + { CS53L30_MCLKCTL, CS53L30_MCLK_DIV_DFLT }, + { CS53L30_INT_SR_CTL, CS53L30_INTRNL_FS_DFLT }, + { CS53L30_MICBIAS_CTL, CS53L30_MIC_BIAS_DFLT }, + { CS53L30_ASPCFG_CTL, CS53L30_ASP_RATE_48K }, + { CS53L30_ASP1_CTL, CS53L30_ASP1_TDM_PDN }, + { CS53L30_ASP1_TDMTX_CTL1, CS53L30_ASP1_CHTX_SLT47 }, + { CS53L30_ASP1_TDMTX_CTL2, CS53L30_ASP1_CHTX_SLT47 }, + { CS53L30_ASP1_TDMTX_CTL3, CS53L30_ASP1_CHTX_SLT47 }, + { CS53L30_ASP1_TDMTX_CTL4, CS53L30_ASP1_CHTX_SLT47 }, + { CS53L30_ASP1_TDMTX_EN1, CS53L30_ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN2, CS53L30_ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN3, CS53L30_ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN4, CS53L30_ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN5, CS53L30_ASP_TX_DISABLED }, + { CS53L30_ASP1_TDMTX_EN6, CS53L30_ASP_TX_DISABLED }, + { CS53L30_ASP2_CTL, CS53L30_ASP2_CTRL_DFLT }, + { CS53L30_SFT_RAMP, CS53L30_SFT_RMP_DFLT }, + { CS53L30_LRCLK_CTL1, CS53L30_LRCK_CTLX_DFLT }, + { CS53L30_LRCLK_CTL2, CS53L30_LRCK_CTLX_DFLT }, + { CS53L30_MUTEP_CTL1, CS53L30_MUTE_CTRL1_DFLT }, + { CS53L30_MUTEP_CTL2, CS53L30_MUTE_PDN_ULP }, + { CS53L30_INBIAS_CTL1, CS53L30_INBIAS_X_DFLT }, + { CS53L30_INBIAS_CTL2, CS53L30_INBIAS_X_DFLT }, + { CS53L30_DMIC1_STR_CTL, CS53L30_DMIC1_ST_DFLT }, + { CS53L30_DMIC2_STR_CTL, CS53L30_DMIC2_ST_DFLT }, + { CS53L30_ADCDMIC1_CTL1, CS53L30_ADC1_ON_AB_IN }, + { CS53L30_ADCDMIC1_CTL2, CS53L30_A1_D1_CTL2_DFLT }, + { CS53L30_ADC1_CTL3, CS53L30_ADC1_HPF_EN }, + { CS53L30_ADC1_NG_CTL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC1A_AFE_CTL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC1B_AFE_CTL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC1A_DIG_VOL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC1B_DIG_VOL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADCDMIC2_CTL1, CS53L30_ADC2_ON_AB_IN }, + { CS53L30_ADCDMIC2_CTL2, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC2_CTL3, CS53L30_ADC2_HPF_EN }, + { CS53L30_ADC2_NG_CTL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC2A_AFE_CTL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC2B_AFE_CTL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC2A_DIG_VOL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_ADC2B_DIG_VOL, CS53L30_ADCX_ZERO_DFLT }, + { CS53L30_INT_MASK, CS53L30_DEVICE_INT_MASK }, +}; + +static bool cs53l30_volatile_register(struct device *dev, unsigned int reg) +{ + if (reg == CS53L30_IS) + return true; + else + return false; +} + +static bool cs53l30_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS53L30_DEVID_AB: + case CS53L30_DEVID_CD: + case CS53L30_DEVID_E: + case CS53L30_REVID: + case CS53L30_PWRCTL: + case CS53L30_MCLKCTL: + case CS53L30_INT_SR_CTL: + case CS53L30_MICBIAS_CTL: + case CS53L30_ASPCFG_CTL: + case CS53L30_ASP1_CTL: + case CS53L30_ASP1_TDMTX_CTL1: + case CS53L30_ASP1_TDMTX_CTL2: + case CS53L30_ASP1_TDMTX_CTL3: + case CS53L30_ASP1_TDMTX_CTL4: + case CS53L30_ASP1_TDMTX_EN1: + case CS53L30_ASP1_TDMTX_EN2: + case CS53L30_ASP1_TDMTX_EN3: + case CS53L30_ASP1_TDMTX_EN4: + case CS53L30_ASP1_TDMTX_EN5: + case CS53L30_ASP1_TDMTX_EN6: + case CS53L30_ASP2_CTL: + case CS53L30_SFT_RAMP: + case CS53L30_LRCLK_CTL1: + case CS53L30_LRCLK_CTL2: + case CS53L30_MUTEP_CTL1: + case CS53L30_MUTEP_CTL2: + case CS53L30_INBIAS_CTL1: + case CS53L30_INBIAS_CTL2: + case CS53L30_DMIC1_STR_CTL: + case CS53L30_DMIC2_STR_CTL: + case CS53L30_ADCDMIC1_CTL1: + case CS53L30_ADCDMIC1_CTL2: + case CS53L30_ADC1_CTL3: + case CS53L30_ADC1_NG_CTL: + case CS53L30_ADC1A_AFE_CTL: + case CS53L30_ADC1B_AFE_CTL: + case CS53L30_ADC1A_DIG_VOL: + case CS53L30_ADC1B_DIG_VOL: + case CS53L30_ADCDMIC2_CTL1: + case CS53L30_ADCDMIC2_CTL2: + case CS53L30_ADC2_CTL3: + case CS53L30_ADC2_NG_CTL: + case CS53L30_ADC2A_AFE_CTL: + case CS53L30_ADC2B_AFE_CTL: + case CS53L30_ADC2A_DIG_VOL: + case CS53L30_ADC2B_DIG_VOL: + case CS53L30_INT_MASK: + return true; + default: + return false; + } +} + +static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2000, 0); +static DECLARE_TLV_DB_SCALE(adc_ng_boost_tlv, 0, 3000, 0); +static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0); + +static DECLARE_TLV_DB_SCALE(dig_tlv, -9600, 100, 1); + +static const char * const input1_sel_text[] = { "DMIC1 On AB In", + "DMIC1 On A In", "DMIC1 On B In", "ADC1 On AB In", "ADC1 On A In", + "ADC1 On B In", "DMIC1 Off ADC1 Off", }; + +unsigned int const input1_sel_values[] = { CS53L30_DMIC1_ON_AB_IN, + CS53L30_DMIC1_ON_A_IN, CS53L30_DMIC1_ON_B_IN, CS53L30_ADC1_ON_AB_IN, + CS53L30_ADC1_ON_A_IN, CS53L30_ADC1_ON_B_IN, CS53L30_D1_OFF_A1_OFF, }; + +static const char * const input2_sel_text[] = { "DMIC2 On AB In", + "DMIC2 On A In", "DMIC2 On B In", "ADC2 On AB In", "ADC2 On A In", + "ADC2 On B In", "DMIC2 Off ADC2 Off", }; + +unsigned int const input2_sel_values[] = { CS53L30_DMIC2_ON_AB_IN, + CS53L30_DMIC2_ON_A_IN, CS53L30_DMIC2_ON_B_IN, CS53L30_ADC2_ON_AB_IN, + CS53L30_ADC2_ON_A_IN, CS53L30_ADC2_ON_B_IN, CS53L30_D2_OFF_A2_OFF, }; + +static const char * const input1_route_sel_text[] = { "ADC1_SEL", + "DMIC1_SEL" }; + +static const struct soc_enum input1_route_sel_enum = + SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0, + ARRAY_SIZE(input1_route_sel_text), input1_route_sel_text); + +static SOC_VALUE_ENUM_SINGLE_DECL(input1_sel_enum, CS53L30_ADCDMIC1_CTL1, 0, + CS53L30_A1_D1_PDN_MASK, input1_sel_text, input1_sel_values); + +static const struct snd_kcontrol_new input1_route_sel_mux = + SOC_DAPM_ENUM("Input 1 Route", input1_route_sel_enum); + +static const char * const input2_route_sel_text[] = { "ADC2_SEL", + "DMIC2_SEL" }; + +/* Note: CS53L30_ADCDMIC1_CTL1 CH_TYPE controls inputs 1 and 2 */ +static const struct soc_enum input2_route_sel_enum = + SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0, + ARRAY_SIZE(input2_route_sel_text), input2_route_sel_text); + +static SOC_VALUE_ENUM_SINGLE_DECL(input2_sel_enum, CS53L30_ADCDMIC2_CTL1, 0, + CS53L30_A1_D1_PDN_MASK, input2_sel_text, input2_sel_values); + +static const struct snd_kcontrol_new input2_route_sel_mux = + SOC_DAPM_ENUM("Input 2 Route", input2_route_sel_enum); + +/* + * TB = 6144*(MCLK(int) scaling factor)/MCLK(internal) + * TB - Time base + * NOTE: If MCLK_INT_SCALE = 0, then TB=1 + */ +static const char * const cs53l30_ng_delay_text[] = { + "TB*50ms", "TB*100ms", "TB*150ms", "TB*200ms" }; + +static const struct soc_enum adc1_ng_delay_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, 0, + ARRAY_SIZE(cs53l30_ng_delay_text), cs53l30_ng_delay_text); + +static const struct soc_enum adc2_ng_delay_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, 0, + ARRAY_SIZE(cs53l30_ng_delay_text), cs53l30_ng_delay_text); + +/* The noise gate threshold selected will depend on NG Boost */ +static const char * const cs53l30_ng_thres_text[] = { + "-64dB/-34dB", "-66dB/-36dB", "-70dB/-40dB", "-73dB/-43dB", + "-76dB/-46dB", "-82dB/-52dB", "-58dB", "-64dB"}; + +static const struct soc_enum adc1_ng_thres_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, 2, + ARRAY_SIZE(cs53l30_ng_thres_text), cs53l30_ng_thres_text); + +static const struct soc_enum adc2_ng_thres_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, 2, + ARRAY_SIZE(cs53l30_ng_thres_text), cs53l30_ng_thres_text); + +/* ADC Preamp gain select */ +static const char * const cs53l30_preamp_gain_sel_text[] = { + "0dB", "10dB", "20dB"}; + +static const struct soc_enum adc1a_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1A_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +static const struct soc_enum adc1b_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1B_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +static const struct soc_enum adc2a_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2A_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +static const struct soc_enum adc2b_preamp_gain_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2B_AFE_CTL, 6, + ARRAY_SIZE(cs53l30_preamp_gain_sel_text), + cs53l30_preamp_gain_sel_text); + +/* Set MIC Bias Voltage Control */ +static const char * const cs53l30_micbias_text[] = { + "HiZ", "1.8V", "2.75V"}; + +static const struct soc_enum micbias_enum = + SOC_ENUM_SINGLE(CS53L30_MICBIAS_CTL, 0, + ARRAY_SIZE(cs53l30_micbias_text), + cs53l30_micbias_text); + +/* Corner frequencies are with an Fs of 48kHz. */ +static const char * const hpf_corner_freq_text[] = { + "1.86Hz", "120Hz", "235Hz", "466Hz"}; + +static const struct soc_enum adc1_hpf_enum = + SOC_ENUM_SINGLE(CS53L30_ADC1_CTL3, 1, + ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text); + +static const struct soc_enum adc2_hpf_enum = + SOC_ENUM_SINGLE(CS53L30_ADC2_CTL3, 1, + ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text); + +static const struct snd_kcontrol_new cs53l30_snd_controls[] = { + SOC_SINGLE("Digital Soft-Ramp Switch", CS53L30_SFT_RAMP, 5, 1, 0), + SOC_SINGLE("ADC1 Noise Gate Ganging Switch", + CS53L30_ADC1_CTL3, 0, 1, 0), + SOC_SINGLE("ADC2 Noise Gate Ganging Switch", + CS53L30_ADC2_CTL3, 0, 1, 0), + SOC_SINGLE("ADC1A Noise Gate Enable Switch", + CS53L30_ADC1_NG_CTL, 6, 1, 0), + SOC_SINGLE("ADC1B Noise Gate Enable Switch", + CS53L30_ADC1_NG_CTL, 7, 1, 0), + SOC_SINGLE("ADC2A Noise Gate Enable Switch", + CS53L30_ADC2_NG_CTL, 6, 1, 0), + SOC_SINGLE("ADC2B Noise Gate Enable Switch", + CS53L30_ADC2_NG_CTL, 7, 1, 0), + SOC_SINGLE("ADC1 Notch Filter Switch", + CS53L30_ADCDMIC1_CTL2, 7, 1, 1), + SOC_SINGLE("ADC2 Notch Filter Switch", + CS53L30_ADCDMIC2_CTL2, 7, 1, 1), + SOC_SINGLE("ADC1A Invert Switch", + CS53L30_ADCDMIC1_CTL2, 4, 1, 0), + SOC_SINGLE("ADC1B Invert Switch", + CS53L30_ADCDMIC1_CTL2, 5, 1, 0), + SOC_SINGLE("ADC2A Invert Switch", + CS53L30_ADCDMIC2_CTL2, 4, 1, 0), + SOC_SINGLE("ADC2B Invert Switch", + CS53L30_ADCDMIC2_CTL2, 5, 1, 0), + + SOC_SINGLE_TLV("ADC1A Digital Boost Volume", + CS53L30_ADCDMIC1_CTL2, 0, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC1B Digital Boost Volume", + CS53L30_ADCDMIC1_CTL2, 1, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC2A Digital Boost Volume", + CS53L30_ADCDMIC2_CTL2, 0, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC2B Digital Boost Volume", + CS53L30_ADCDMIC2_CTL2, 1, 1, 0, adc_boost_tlv), + SOC_SINGLE_TLV("ADC1 NG Boost Volume", + CS53L30_ADC1_NG_CTL, 5, 1, 0, adc_ng_boost_tlv), + SOC_SINGLE_TLV("ADC2 NG Boost Volume", + CS53L30_ADC2_NG_CTL, 5, 1, 0, adc_ng_boost_tlv), + + SOC_ENUM("Input 1 Channel Select", input1_sel_enum), + SOC_ENUM("Input 2 Channel Select", input2_sel_enum), + + SOC_ENUM("ADC1 HPF Select", adc1_hpf_enum), + SOC_ENUM("ADC2 HPF Select", adc2_hpf_enum), + SOC_ENUM("ADC1 NG Threshold", adc1_ng_thres_enum), + SOC_ENUM("ADC2 NG Threshold", adc2_ng_thres_enum), + SOC_ENUM("ADC1 NG Delay", adc1_ng_delay_enum), + SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum), + SOC_ENUM("ADC1A Pre Amp Gain", adc1a_preamp_gain_enum), + SOC_ENUM("ADC1B Pre Amp Gain", adc1b_preamp_gain_enum), + SOC_ENUM("ADC2A Pre Amp Gain", adc2a_preamp_gain_enum), + SOC_ENUM("ADC2B Pre Amp Gain", adc2b_preamp_gain_enum), + SOC_ENUM("Mic Bias Voltage Select", micbias_enum), + + SOC_SINGLE_SX_TLV("ADC1A PGA Volume", + CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + SOC_SINGLE_SX_TLV("ADC1B PGA Volume", + CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + SOC_SINGLE_SX_TLV("ADC2A PGA Volume", + CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + SOC_SINGLE_SX_TLV("ADC2B PGA Volume", + CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x18, pga_tlv), + + SOC_SINGLE_SX_TLV("ADC1A Digital Volume", + CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), + SOC_SINGLE_SX_TLV("ADC1B Digital Volume", + CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), + SOC_SINGLE_SX_TLV("ADC2A Digital Volume", + CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), + SOC_SINGLE_SX_TLV("ADC2B Digital Volume", + CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv), +}; + +static int cs53l30_asp_sdout_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + regmap_update_bits(priv->regmap, CS53L30_ASP1_CTL, + CS53L30_ASP1_3ST, 0); + break; + case SND_SOC_DAPM_POST_PMD: + regmap_update_bits(priv->regmap, CS53L30_ASP1_CTL, + CS53L30_ASP1_3ST, 1); + break; + default: + dev_err(codec->dev, "Invalid event = 0x%x\n", event); + return -EINVAL; + } + + return 0; +} + +static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("IN1_DMIC1"), + SND_SOC_DAPM_INPUT("IN2"), + SND_SOC_DAPM_INPUT("IN3_DMIC2"), + SND_SOC_DAPM_INPUT("IN4"), + SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS53L30_MICBIAS_CTL, 4, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS53L30_MICBIAS_CTL, 5, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIC3 Bias", CS53L30_MICBIAS_CTL, 6, 1, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIC4 Bias", CS53L30_MICBIAS_CTL, 7, 1, NULL, 0), + + SND_SOC_DAPM_AIF_OUT_E("ASP_SDOUT1", NULL, 0, CS53L30_ASP1_CTL, + CS53L30_ASP1_SDOUT_PDN, 1, + cs53l30_asp_sdout_event, + (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)), + SND_SOC_DAPM_AIF_OUT_E("ASP_SDOUT2", NULL, 0, CS53L30_ASP2_CTL, + CS53L30_ASP2_SDOUT_PDN, 1, + cs53l30_asp_sdout_event, + (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)), + + SND_SOC_DAPM_MUX("Input Mux 1", SND_SOC_NOPM, 0, 0, + &input1_route_sel_mux), + SND_SOC_DAPM_MUX("Input Mux 2", SND_SOC_NOPM, 0, 0, + &input2_route_sel_mux), + + SND_SOC_DAPM_ADC("ADC1A", NULL, CS53L30_ADCDMIC1_CTL1, 6, 1), + SND_SOC_DAPM_ADC("ADC1B", NULL, CS53L30_ADCDMIC1_CTL1, 7, 1), + SND_SOC_DAPM_ADC("ADC2A", NULL, CS53L30_ADCDMIC2_CTL1, 6, 1), + SND_SOC_DAPM_ADC("ADC2B", NULL, CS53L30_ADCDMIC2_CTL1, 7, 1), + SND_SOC_DAPM_ADC("DMIC1", NULL, CS53L30_ADCDMIC1_CTL1, 2, 1), + SND_SOC_DAPM_ADC("DMIC2", NULL, CS53L30_ADCDMIC2_CTL1, 2, 1), +}; + +static const struct snd_soc_dapm_route cs53l30_audio_map[] = { + + /* ADC Input Paths */ + {"ADC1A", NULL, "IN1_DMIC1"}, + {"Input Mux 1", "ADC1_SEL", "ADC1A"}, + {"ADC1B", NULL, "IN2"}, + + {"ADC2A", NULL, "IN3_DMIC2"}, + {"Input Mux 2", "ADC2_SEL", "ADC2A"}, + {"ADC2B", NULL, "IN4"}, + + /* MIC Bias Paths */ + {"ADC1A", NULL, "MIC1 Bias"}, + {"ADC1B", NULL, "MIC2 Bias"}, + {"ADC2A", NULL, "MIC3 Bias"}, + {"ADC2B", NULL, "MIC4 Bias"}, + + /* DMIC Paths */ + {"DMIC1", NULL, "IN1_DMIC1"}, + {"Input Mux 1", "DMIC1_SEL", "DMIC1"}, + + {"DMIC2", NULL, "IN3_DMIC2"}, + {"Input Mux 2", "DMIC2_SEL", "DMIC2"}, + + /* Output Paths */ + {"ASP_SDOUT1", NULL, "ADC1A" }, + {"ASP_SDOUT1", NULL, "Input Mux 1"}, + {"ASP_SDOUT1", NULL, "ADC1B"}, + + {"ASP_SDOUT2", NULL, "ADC2A"}, + {"ASP_SDOUT2", NULL, "Input Mux 2"}, + {"ASP_SDOUT2", NULL, "ADC2B"}, + + {"ASP1 Capture", NULL, "ASP_SDOUT1"}, + {"ASP2 Capture", NULL, "ASP_SDOUT2"}, +}; + +struct cs53l30_mclk_div { + u32 mclk; + u32 srate; + u8 asp_rate; + u8 internal_fs_ratio; + u8 mclk_int_scale; +}; + +static struct cs53l30_mclk_div cs53l30_mclk_coeffs[] = { + /* NOTE: Enable MCLK_INT_SCALE to save power. */ + + /* MCLK, Sample Rate, asp_rate, internal_fs_ratio, mclk_int_scale */ + {5644800, 11025, 0x4, 1, 1}, + {5644800, 22050, 0x8, 1, 1}, + {5644800, 44100, 0xC, 1, 1}, + + {6000000, 8000, 0x1, 0, 1}, + {6000000, 11025, 0x2, 0, 1}, + {6000000, 12000, 0x4, 0, 1}, + {6000000, 16000, 0x5, 0, 1}, + {6000000, 22050, 0x6, 0, 1}, + {6000000, 24000, 0x8, 0, 1}, + {6000000, 32000, 0x9, 0, 1}, + {6000000, 44100, 0xA, 0, 1}, + {6000000, 48000, 0xC, 0, 1}, + + {6144000, 8000, 0x1, 1, 1}, + {6144000, 11025, 0x2, 1, 1}, + {6144000, 12000, 0x4, 1, 1}, + {6144000, 16000, 0x5, 1, 1}, + {6144000, 22050, 0x6, 1, 1}, + {6144000, 24000, 0x8, 1, 1}, + {6144000, 32000, 0x9, 1, 1}, + {6144000, 44100, 0xA, 1, 1}, + {6144000, 48000, 0xC, 1, 1}, + + {6400000, 8000, 0x1, 1, 1}, + {6400000, 11025, 0x2, 1, 1}, + {6400000, 12000, 0x4, 1, 1}, + {6400000, 16000, 0x5, 1, 1}, + {6400000, 22050, 0x6, 1, 1}, + {6400000, 24000, 0x8, 1, 1}, + {6400000, 32000, 0x9, 1, 1}, + {6400000, 44100, 0xA, 1, 1}, + {6400000, 48000, 0xC, 1, 1}, +}; + +struct cs53l30_mclkx_div { + u32 mclkx; + u8 ratio; + u8 mclkdiv; +}; + +static struct cs53l30_mclkx_div cs53l30_mclkx_coeffs[] = { + {5644800, 1, 0}, + {6000000, 1, 0}, + {6144000, 1, 0}, + {11289600, 2, 1}, + {12288000, 2, 1}, + {12000000, 2, 1}, + {19200000, 3, 2}, +}; + +static int cs53l30_get_mclkx_coeff(int mclkx) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs53l30_mclkx_coeffs); i++) { + if (cs53l30_mclkx_coeffs[i].mclkx == mclkx) + return i; + } + return -EINVAL; +} + +static int cs53l30_get_mclk_coeff(int mclk, int srate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs53l30_mclk_coeffs); i++) { + if (cs53l30_mclk_coeffs[i].mclk == mclk && + cs53l30_mclk_coeffs[i].srate == srate) + return i; + } + return -EINVAL; + +} + +static int cs53l30_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + + int mclkx_coeff; + u32 mclk; + unsigned int mclk_ctl; + + /* MCLKX -> MCLK */ + mclkx_coeff = cs53l30_get_mclkx_coeff(freq); + if (mclkx_coeff < 0) + return mclkx_coeff; + + mclk = cs53l30_mclkx_coeffs[mclkx_coeff].mclkx / + cs53l30_mclkx_coeffs[mclkx_coeff].ratio; + + regmap_read(priv->regmap, CS53L30_MCLKCTL, &mclk_ctl); + mclk_ctl &= ~CS53L30_MCLK_DIV; + mclk_ctl |= cs53l30_mclkx_coeffs[mclkx_coeff].mclkdiv; + + regmap_update_bits(priv->regmap, CS53L30_MCLKCTL, CS53L30_MCLK_DIV, + mclk_ctl << CS53L30_MCLK_DIV); + priv->mclk = mclk; + return 0; +} + +static int cs53l30_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + unsigned int asp_config_ctl; + + regmap_read(priv->regmap, CS53L30_ASPCFG_CTL, &asp_config_ctl); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + asp_config_ctl |= CS53L30_ASP_MS; + break; + + case SND_SOC_DAIFMT_CBS_CFS: + asp_config_ctl &= ~CS53L30_ASP_MS; + break; + + default: + return -EINVAL; + } + + /* Check to see if the SCLK is inverted */ + if (fmt & (SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_IB_IF)) + asp_config_ctl |= CS53L30_ASP_SCLK_INV; + else + asp_config_ctl &= ~CS53L30_ASP_SCLK_INV; + + priv->asp_config_ctl = asp_config_ctl; + return 0; +} + +static int cs53l30_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + int mclk_coeff; + int srate = params_rate(params); + unsigned int int_sr_ctl, mclk_ctl; + + /* MCLK -> srate */ + mclk_coeff = cs53l30_get_mclk_coeff(priv->mclk, srate); + if (mclk_coeff < 0) + return -EINVAL; + + regmap_read(priv->regmap, CS53L30_INT_SR_CTL, &int_sr_ctl); + if (cs53l30_mclk_coeffs[mclk_coeff].internal_fs_ratio) + int_sr_ctl |= CS53L30_INTRNL_FS_RATIO; + else + int_sr_ctl &= ~CS53L30_INTRNL_FS_RATIO; + regmap_update_bits(priv->regmap, CS53L30_INT_SR_CTL, + CS53L30_INTL_FS_RAT_MSK, int_sr_ctl << + CS53L30_INTL_FS_RAT_SFT); + + regmap_read(priv->regmap, CS53L30_MCLKCTL, &mclk_ctl); + if (cs53l30_mclk_coeffs[mclk_coeff].mclk_int_scale) + mclk_ctl |= CS53L30_MCLK_INT_SCALE; + else + mclk_ctl &= ~CS53L30_MCLK_INT_SCALE; + regmap_update_bits(priv->regmap, CS53L30_MCLKCTL, + CS53L30_MCK_INT_SCL_MSK, mclk_ctl << + CS53L30_MCK_INT_SCL_SFT); + + priv->asp_config_ctl &= CS53L30_ASP_CNFG_MASK; + priv->asp_config_ctl |= (cs53l30_mclk_coeffs[mclk_coeff].asp_rate + & CS53L30_ASP_RATE_MASK); + regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL, + CS53L30_ASP_RATE_MASK, priv->asp_config_ctl); + + return 0; +} + +static int cs53l30_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + unsigned int reg; + int i, inter_max_check; + + switch (level) { + case SND_SOC_BIAS_ON: + break; + case SND_SOC_BIAS_PREPARE: + if (dapm->bias_level == SND_SOC_BIAS_STANDBY) + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + CS53L30_PDN_LP, 0); + break; + case SND_SOC_BIAS_STANDBY: + if (dapm->bias_level == SND_SOC_BIAS_OFF) { + regmap_update_bits(priv->regmap, CS53L30_MCLKCTL, + CS53L30_MCLK_DIS, 0); + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + CS53L30_PDN_ULP, 0); + msleep(50); + } else { + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + CS53L30_PDN_LP, CS53L30_PDN_LP); + } + break; + + case SND_SOC_BIAS_OFF: + regmap_update_bits(priv->regmap, CS53L30_INT_MASK, + CS53L30_PDN_DONE, 0); + /* If digital softramp is set, the amount of time required + * for power down increases and depends on the digital + * volume setting. + */ + + /* Set the max possible time if digsft is set */ + regmap_read(priv->regmap, CS53L30_SFT_RAMP, &reg); + if (reg & CS53L30_DIGSFT) + inter_max_check = CS53L30_PDN_POLL_MAX; + else + inter_max_check = 10; + + regmap_update_bits(priv->regmap, CS53L30_PWRCTL, + CS53L30_PDN_ULP, CS53L30_PDN_ULP); + msleep(20); /* PDN_DONE will take a min of 20ms to be set.*/ + regmap_read(priv->regmap, CS53L30_IS, &reg); /* Clr status */ + for (i = 0; i < inter_max_check; i++) { + if (inter_max_check < 10) { + usleep_range(1000, 1100); + regmap_read(priv->regmap, CS53L30_IS, &reg); + if (reg & CS53L30_PDN_DONE) + break; + } else { + usleep_range(10000, 10100); + regmap_read(priv->regmap, CS53L30_IS, &reg); + if (reg & CS53L30_PDN_DONE) + break; + } + } + /* PDN_DONE is set. We now can disable the MCLK */ + regmap_update_bits(priv->regmap, CS53L30_INT_MASK, + CS53L30_PDN_DONE, CS53L30_PDN_DONE); + regmap_update_bits(priv->regmap, CS53L30_MCLKCTL, + CS53L30_MCLK_DIS, CS53L30_MCLK_DIS); + break; + } + + return 0; +} + +static int cs53l30_set_tristate(struct snd_soc_dai *dai, int tristate) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec); + + return regmap_update_bits(priv->regmap, CS53L30_ASP1_CTL, + CS53L30_ASP1_3ST, + (CS53L30_ASP1_3ST_VAL(tristate) & + CS53L30_ASP1_3ST)); +} + +unsigned int const cs53l30_src_rates[] = { + 8000, 11025, 12000, 16000, 22050, + 24000, 32000, 44100, 48000 +}; + +static struct snd_pcm_hw_constraint_list src_constraints = { + .count = ARRAY_SIZE(cs53l30_src_rates), + .list = cs53l30_src_rates, +}; + +static int cs53l30_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &src_constraints); + + return 0; +} + +/* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */ +#define CS53L30_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT) + +#define CS53L30_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +static const struct snd_soc_dai_ops cs53l30_ops = { + .startup = cs53l30_pcm_startup, + .hw_params = cs53l30_pcm_hw_params, + .set_fmt = cs53l30_set_dai_fmt, + .set_sysclk = cs53l30_set_sysclk, + .set_tristate = cs53l30_set_tristate, +}; + +static struct snd_soc_dai_driver cs53l30_dai[] = { + { + .name = "cs53l30-asp1", + .id = CS53L30_ASP1, + .capture = { + .stream_name = "ASP1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CS53L30_RATES, + .formats = CS53L30_FORMATS, + }, + .ops = &cs53l30_ops, + .symmetric_rates = 1, + }, + { + .name = "cs53l30-asp2", + .id = CS53L30_ASP2, + .capture = { + .stream_name = "ASP2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CS53L30_RATES, + .formats = CS53L30_FORMATS, + }, + .ops = &cs53l30_ops, + .symmetric_rates = 1, + } +}; + +static struct snd_soc_codec_driver soc_codec_dev_cs53l30 = { + .set_bias_level = cs53l30_set_bias_level, + + .dapm_widgets = cs53l30_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs53l30_dapm_widgets), + .dapm_routes = cs53l30_audio_map, + .num_dapm_routes = ARRAY_SIZE(cs53l30_audio_map), + + .controls = cs53l30_snd_controls, + .num_controls = ARRAY_SIZE(cs53l30_snd_controls), +}; + +static struct regmap_config cs53l30_regmap = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = CS53L30_MAX_REGISTER, + .reg_defaults = cs53l30_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(cs53l30_reg_defaults), + .volatile_reg = cs53l30_volatile_register, + .readable_reg = cs53l30_readable_register, + .cache_type = REGCACHE_RBTREE, +}; + +static int cs53l30_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct cs53l30_private *cs53l30; + int ret = 0; + unsigned int devid = 0; + unsigned int reg; + + cs53l30 = devm_kzalloc(&client->dev, + sizeof(struct cs53l30_private), GFP_KERNEL); + if (!cs53l30) { + dev_err(&client->dev, "could not allocate codec\n"); + return -ENOMEM; + } + + /* Reset the Device */ + cs53l30->reset_gpio = devm_gpiod_get_optional(&client->dev, + "reset", GPIOD_OUT_LOW); + if (IS_ERR(cs53l30->reset_gpio)) + return PTR_ERR(cs53l30->reset_gpio); + + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 1); + + i2c_set_clientdata(client, cs53l30); + + cs53l30->mclk = 0; + + cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap); + if (IS_ERR(cs53l30->regmap)) { + ret = PTR_ERR(cs53l30->regmap); + dev_err(&client->dev, "regmap_init() failed: %d\n", ret); + return ret; + } + /* initialize codec */ + ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, &reg); + devid = reg << 12; + + ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, &reg); + devid |= reg << 4; + + ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, &reg); + devid |= (reg & 0xF0) >> 4; + + if (devid != CS53L30_DEVID) { + ret = -ENODEV; + dev_err(&client->dev, + "CS53L30 Device ID (%X). Expected %X\n", + devid, CS53L30_DEVID); + return ret; + } + + ret = regmap_read(cs53l30->regmap, CS53L30_REVID, &reg); + if (ret < 0) { + dev_err(&client->dev, "Get Revision ID failed\n"); + return ret; + } + + dev_info(&client->dev, + "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF); + + ret = snd_soc_register_codec(&client->dev, + &soc_codec_dev_cs53l30, cs53l30_dai, + ARRAY_SIZE(cs53l30_dai)); + return ret; +} + +static int cs53l30_i2c_remove(struct i2c_client *client) +{ + struct cs53l30_private *cs53l30 = i2c_get_clientdata(client); + + snd_soc_unregister_codec(&client->dev); + + /* Hold down reset */ + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 0); + + return 0; +} + +#ifdef CONFIG_PM +static int cs53l30_runtime_suspend(struct device *dev) +{ + struct cs53l30_private *cs53l30 = dev_get_drvdata(dev); + + regcache_cache_only(cs53l30->regmap, true); + + /* Hold down reset */ + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 0); + + return 0; +} + +static int cs53l30_runtime_resume(struct device *dev) +{ + struct cs53l30_private *cs53l30 = dev_get_drvdata(dev); + + if (cs53l30->reset_gpio) + gpiod_set_value_cansleep(cs53l30->reset_gpio, 1); + + regcache_cache_only(cs53l30->regmap, false); + regcache_sync(cs53l30->regmap); + + return 0; +} +#endif + +static const struct dev_pm_ops cs53l30_runtime_pm = { + SET_RUNTIME_PM_OPS(cs53l30_runtime_suspend, cs53l30_runtime_resume, + NULL) +}; + +static const struct of_device_id cs53l30_of_match[] = { + { .compatible = "cirrus,cs53l30", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, cs53l30_of_match); + +static const struct i2c_device_id cs53l30_id[] = { + {"cs53l30", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, cs53l30_id); + +static struct i2c_driver cs53l30_i2c_driver = { + .driver = { + .name = "cs53l30", + }, + .id_table = cs53l30_id, + .probe = cs53l30_i2c_probe, + .remove = cs53l30_i2c_remove, + +}; + +module_i2c_driver(cs53l30_i2c_driver); + +MODULE_DESCRIPTION("ASoC CS53L30 driver"); +MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan(a)cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/cs53l30.h b/sound/soc/codecs/cs53l30.h new file mode 100644 index 0000000..116e358 +++ b/sound/soc/codecs/cs53l30.h @@ -0,0 +1,282 @@ +/* + * ALSA SoC CS53L30 codec driver + * + * Copyright 2015 Cirrus Logic, Inc. + * + * Author: Paul Handrigan <Paul.Handrigan(a)cirrus.com>, + * Tim Howe <Tim.Howe(a)cirrus.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __CS53L30_H__ +#define __CS53L30_H__ + +/* I2C Registers */ +#define CS53L30_DEVID_AB 0x01 /* Device ID A & B [RO]. */ +#define CS53L30_DEVID_CD 0x02 /* Device ID C & D [RO]. */ +#define CS53L30_DEVID_E 0x03 /* Device ID E [RO]. */ +#define CS53L30_REVID 0x05 /* Revision ID [RO]. */ +#define CS53L30_PWRCTL 0x06 /* Power Control. */ +#define CS53L30_MCLKCTL 0x07 /* MCLK Control. */ +#define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */ +#define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */ +#define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */ +#define CS53L30_ASP1_CTL 0x0D /* ASP1 Control. */ +#define CS53L30_ASP1_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */ +#define CS53L30_ASP1_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */ +#define CS53L30_ASP1_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */ +#define CS53L30_ASP1_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */ +#define CS53L30_ASP1_TDMTX_EN1 0x12 /* ASP1 TDM TX Enable 1 */ +#define CS53L30_ASP1_TDMTX_EN2 0x13 /* ASP1 TDM TX Enable 2 */ +#define CS53L30_ASP1_TDMTX_EN3 0x14 /* ASP1 TDM TX Enable 3 */ +#define CS53L30_ASP1_TDMTX_EN4 0x15 /* ASP1 TDM TX Enable 4 */ +#define CS53L30_ASP1_TDMTX_EN5 0x16 /* ASP1 TDM TX Enable 5 */ +#define CS53L30_ASP1_TDMTX_EN6 0x17 /* ASP1 TDM TX Enable 6 */ +#define CS53L30_ASP2_CTL 0x18 /* ASP2 Control. */ +#define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */ +#define CS53L30_LRCLK_CTL1 0x1B /* LRCLK Control 1. */ +#define CS53L30_LRCLK_CTL2 0x1C /* LRCLK Control 2. */ +#define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */ +#define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */ +#define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */ +#define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */ +#define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */ +#define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */ +#define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */ +#define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */ +#define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */ +#define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */ +#define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */ +#define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */ +#define CS53L30_ADC1A_DIG_VOL 0x2B /* ADC1A Digital Volume. */ +#define CS53L30_ADC1B_DIG_VOL 0x2C /* ADC1B Digital Volume. */ +#define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */ +#define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */ +#define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */ +#define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */ +#define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */ +#define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */ +#define CS53L30_ADC2A_DIG_VOL 0x33 /* ADC2A Digital Volume. */ +#define CS53L30_ADC2B_DIG_VOL 0x34 /* ADC2B Digital Volume. */ +#define CS53L30_INT_MASK 0x35 /* Interrupt Mask. */ +#define CS53L30_IS 0x36 /* Interrupt Status. */ +#define CS53L30_MAX_REGISTER 0x36 + +/* Device ID */ +#define CS53L30_DEVID 0x53A30 + +/* PDN_DONE Poll Maximum + * If soft ramp is set it will take much longer to power down + * the system. + */ +#define CS53L30_PDN_POLL_MAX 90 + +/* Bitfield Definitions */ + +/* CS53L30_PWRCTL */ +#define CS53L30_PDN_ULP (1 << 7) +#define CS53L30_PDN_LP (1 << 6) +#define CS53L30_DISCHARGE_FILT (1 << 5) +#define CS53L30_THMS_PDN (1 << 4) + +/* CS53L30_MCLKCTL */ +#define CS53L30_MCLK_DIS (1 << 7) +#define CS53L30_MCLK_INT_SCALE (1 << 6) +#define CS53L30_DMIC_DRIVE (1 << 5) +#define CS53L30_MCLK_DIV (3 << 2) +#define CS53L30_MCLK_DIV_DFLT (1 << 2) +#define CS53L30_SYNC_EN (1 << 1) +#define CS53L30_MCK_INT_SCL_MSK 0x40 +#define CS53L30_MCK_INT_SCL_SFT 6 + +/* CS53L30_INT_SR_CTL */ +#define CS53L30_INTRNL_FS_RATIO (1 << 4) +#define CS53L30_INTRNL_FS_DFLT (7 << 2) +#define CS53L30_MCLK_19MHZ_EN (1 << 0) +#define CS53L30_INTL_FS_RAT_MSK 0x10 +#define CS53L30_INTL_FS_RAT_SFT 4 + +/* CS53L30_MICBIAS_CTL */ +#define CS53L30_MIC4_BIAS_PDN (1 << 7) +#define CS53L30_MIC3_BIAS_PDN (1 << 6) +#define CS53L30_MIC2_BIAS_PDN (1 << 5) +#define CS53L30_MIC1_BIAS_PDN (1 << 4) +#define CS53L30_VP_MIN (1 << 2) +#define CS53L30_MIC_BIAS_CTRL (3 << 0) +#define CS53L30_BIAS_ALL_PDN 0xF0 +#define CS53L30_MIC_BIAS_DFLT (CS53L30_BIAS_ALL_PDN | CS53L30_VP_MIN) + +/* CS53L30_ASPCFG_CTL */ +#define CS53L30_ASP_MS (1 << 7) +#define CS53L30_ASP_SCLK_INV (1 << 4) +#define CS53L30_ASP_RATE_48K (3 << 2) +#define CS53L30_ASP_RATE_MASK 0x0F +#define CS53L30_ASP_CNFG_MASK 0xF0 + +/* CS53L30_ASP1_CTL */ +#define CS53L30_ASP1_TDM_PDN (1 << 7) +#define CS53L30_ASP1_SDOUT_PDN (1 << 6) +#define CS53L30_ASP1_3ST (1 << 5) +#define CS53L30_SHIFT_LEFT (1 << 4) +#define CS53L30_ASP1_DRIVE (1 << 0) +#define CS53L30_ASP1_3ST_VAL(x) ((x) << 5) + +/* CS53L30_ASP1_TDMTX_CTL */ +#define CS53L30_ASP1_CHX_TX_ST (1 << 7) +#define CS53L30_ASP1_CHX_TX_LOC 0x3F +#define CS53L30_ASP1_CHTX_SLT47 0x2F +#define CS53L30_ASP_TX_DISABLED 0x00 + +/* CS53L30_ASP2_CTL */ +#define CS53L30_ASP2_SDOUT_PDN (1 << 6) +#define CS53L30_ASP2_DRIVE (1 << 0) +#define CS53L30_ASP2_CTRL_DFLT 0x00 + +/* CS53L30_SFT_RAMP */ +#define CS53L30_DIGSFT (1 << 5) +#define CS53L30_SFT_RMP_DFLT 0x00 + +/* CS53L30_LRCLK_CTL2 */ +#define CS53L30_LRCK_50_NPW (1 << 3) +#define CS53L30_LRCK_TPWH (7 << 0) +#define CS53L30_LRCK_CTLX_DFLT 0x00 + +/* CS53L30_MUTEP_CTL */ +#define CS53L30_MUTE_PDN_ULP (1 << 7) +#define CS53L30_MUTE_PDN_LP (1 << 6) +#define CS53L30_MUTE_M4B_PDN (1 << 4) +#define CS53L30_MUTE_M3B_PDN (1 << 3) +#define CS53L30_MUTE_M2B_PDN (1 << 2) +#define CS53L30_MUTE_M1B_PDN (1 << 1) +#define CS53L30_MUTE_MB_ALL_PDN (1 << 0) +#define CS53L30_MUTE_CTRL1_DFLT 0x00 + +/* CS53L30_MUTEP_CTL2 */ +#define CS53L30_MUTE_PIN_PLRTY (1 << 7) +#define CS53L30_MUTE_ASPTDM_PDN (1 << 6) +#define CS53L30_MTE_ASPSDO2_PDN (1 << 5) +#define CS53L30_MTE_ASPSDO1_PDN (1 << 4) +#define CS53L30_MUTE_ADC2B_PDN (1 << 3) +#define CS53L30_MUTE_ADC2A_PDN (1 << 2) +#define CS53L30_MUTE_ADC1B_PDN (1 << 1) +#define CS53L30_MUTE_ADC1A_PDN (1 << 0) + +/* CS53L30_INBIAS_CTL1 */ +#define CS53L30_IN4M_BIAS (3 << 6) +#define CS53L30_IN4P_BIAS (3 << 4) +#define CS53L30_IN3M_BIAS (3 << 2) +#define CS53L30_IN3P_BIAS (3 << 0) + +/* CS53L30_INBIAS_CTL2 */ +#define CS53L30_IN2M_BIAS (3 << 6) +#define CS53L30_IN2P_BIAS (3 << 4) +#define CS53L30_IN1M_BIAS (3 << 2) +#define CS53L30_IN1P_BIAS (3 << 0) +#define CS53L30_INBIAS_X_DFLT 0xAA + +/* CS53L30_DMIC1_STR_CTL */ +#define CS53L30_DMIC1_STERO_EN (1 << 5) +#define CS53L30_DMIC1_ST_DFLT 0xA8 + +/* CS53L30_DMIC2_STR_CTL */ +#define CS53L30_DMIC2_STERO_EN (1 << 5) +#define CS53L30_DMIC2_ST_DFLT 0xEC + +/* CS53L30_ADCDMIC1_CTL1 */ +#define CS53L30_ADC1B_PDN (1 << 7) +#define CS53L30_ADC1A_PDN (1 << 6) +#define CS53L30_DMIC1_PDN (1 << 2) +#define CS53L30_DMIC1_SCLK_DIV (1 << 1) +#define CS53L30_CH_TYPE (1 << 0) +#define CS53L30_DMIC1_ON_AB_IN (CS53L30_CH_TYPE) +#define CS53L30_DMIC1_ON_A_IN (CS53L30_ADC1B_PDN | CS53L30_CH_TYPE) +#define CS53L30_DMIC1_ON_B_IN (CS53L30_ADC1A_PDN | CS53L30_CH_TYPE) +#define CS53L30_ADC1_ON_AB_IN (CS53L30_DMIC1_PDN) +#define CS53L30_ADC1_ON_A_IN (CS53L30_ADC1B_PDN | CS53L30_DMIC1_PDN) +#define CS53L30_ADC1_ON_B_IN (CS53L30_ADC1A_PDN | CS53L30_DMIC1_PDN) +#define CS53L30_D1_OFF_A1_OFF (CS53L30_ADC1A_PDN | \ + CS53L30_ADC1B_PDN | \ + CS53L30_DMIC1_PDN) +#define CS53L30_A1_D1_PDN_MASK 0xFF + +/* CS53L30_ADCDMIC1_CTL2 */ +#define CS53L30_ADC1_NOTCH_DIS (1 << 7) +#define CS53L30_ADC1B_INV (1 << 5) +#define CS53L30_ADC1A_INV (1 << 4) +#define CS53L30_ADC1B_DIG_BOOST (1 << 1) +#define CS53L30_ADC1A_DIG_BOOST (1 << 0) +#define CS53L30_A1_D1_CTL2_DFLT 0x00 + +/* CS53L30_ADC1_CTL3 */ +#define CS53L30_ADC1_HPF_EN (1 << 3) +#define CS53L30_ADC1_HPF_CF (3 << 1) +#define CS53L30_ADC1_NG_ALL (1 << 0) + +/* CS53L30_ADC1_NG_CTL */ +#define CS53L30_ADC1B_NG (1 << 7) +#define CS53L30_ADC1A_NG (1 << 6) +#define CS53L30_ADC1_NG_BOOST (1 << 5) +#define CS53L30_ADC1_NG_THRESH (7 << 2) +#define CS53L30_ADC1_NG_DELAY (3 << 0) +#define CS53L30_ADCX_ZERO_DFLT 0x00 + +/* CS53L30_ADC1A_AFE_CTL */ +#define CS53L30_ADC1A_PREAMP (3 << 6) +#define CS53L30_ADC1A_PGA_VOL 0x3F + +/* CS53L30_ADC1B_AFE_CTL */ +#define CS53L30_ADC1B_PREAMP (3 << 6) +#define CS53L30_ADC1B_PGA_VOL 0x3F + +/* CS53L30_ADCXX_DIG_VOL */ +#define CS53L30_MUTE_DIG_OUT (1 << 7) + +/* CS53L30_ADCDMIC2_CTL1 */ +#define CS53L30_ADC2B_PDN (1 << 7) +#define CS53L30_ADC2A_PDN (1 << 6) +#define CS53L30_DMIC2_PDN (1 << 2) +#define CS53L30_DMIC2_CLKDIV (1 << 1) +#define CS53L30_DMIC2_ON_AB_IN 0x00 /* CH_TYPE must = 1 */ +#define CS53L30_DMIC2_ON_A_IN (CS53L30_ADC2B_PDN) /* CH_TYPE must = 1 */ +#define CS53L30_DMIC2_ON_B_IN (CS53L30_ADC2A_PDN) /* CH_TYPE must = 1 */ +#define CS53L30_ADC2_ON_AB_IN (CS53L30_DMIC2_PDN) /* CH_TYPE must = 0 */ +#define CS53L30_ADC2_ON_A_IN (CS53L30_ADC2B_PDN | \ + CS53L30_DMIC2_PDN) +#define CS53L30_ADC2_ON_B_IN (CS53L30_ADC2A_PDN | \ + CS53L30_DMIC2_PDN) +#define CS53L30_D2_OFF_A2_OFF (CS53L30_ADC2A_PDN | \ + CS53L30_ADC2B_PDN | \ + CS53L30_DMIC2_PDN) + +/* CS53L30_ADCDMIC2_CTL2 */ +#define CS53L30_ADC2_NOTCH_DIS (1 << 7) +#define CS53L30_ADC2B_INV (1 << 5) +#define CS53L30_ADC2A_INV (1 << 4) +#define CS53L30_ADC2B_DIG_BOOST (1 << 1) +#define CS53L30_ADC2A_DIG_BOOST (1 << 0) + +/* CS53L30_ADC2_CTL3 */ +#define CS53L30_ADC2_HPF_EN (1 << 3) +#define CS53L30_ADC2_HPF_CF (3 << 1) +#define CS53L30_ADC2_NG_ALL (1 << 0) + +/* CS53L30_INT */ +#define CS53L30_PDN_DONE (1 << 7) +#define CS53L30_THMS_TRIP (1 << 6) +#define CS53L30_SYNC_DONE (1 << 5) +#define CS53L30_ADC2B_OVFL (1 << 4) +#define CS53L30_ADC2A_OVFL (1 << 3) +#define CS53L30_ADC1B_OVFL (1 << 2) +#define CS53L30_ADC1A_OVFL (1 << 1) +#define CS53L30_MUTE_PIN (1 << 0) +#define CS53L30_DEVICE_INT_MASK 0xFF + +/* Serial Ports */ +#define CS53L30_ASP1 0 +#define CS53L30_ASP2 1 + +#endif /* __CS53L30_H__ */ -- 2.4.5

5 12

[alsa-devel] [PATCH V2 linux-next] ASoC: cs53l30: include gpio/consumer.h
by Fabian Frederick 06 Jun '16

06 Jun '16

cs53l30 breaks kernel compilation when CONFIG_GPIOLIB is disabled. sound/soc/codecs/cs53l30.c:931:2: error: implicit declaration of function devm_gpiod_get_optional [-Werror=implicit-function-declaration] cs53l30->reset_gpio = devm_gpiod_get_optional(dev, "reset", ^ sound/soc/codecs/cs53l30.c:932:13: error: GPIOD_OUT_LOW undeclared (first use in this function) Including gpio/consumer.h declares minimal functions in that case. Signed-off-by: Fabian Frederick <fabf(a)skynet.be> --- V2: Add in alphabetical order (suggested by Nicolin Chen) sound/soc/codecs/cs53l30.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/codecs/cs53l30.c b/sound/soc/codecs/cs53l30.c index ac90dd7..4f6ede9 100644 --- a/sound/soc/codecs/cs53l30.c +++ b/sound/soc/codecs/cs53l30.c @@ -14,6 +14,7 @@ #include <linux/clk.h> #include <linux/delay.h> +#include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/module.h> #include <linux/of_gpio.h> -- 2.1.4

3 2

[alsa-devel] [GIT PULL] Braswell audio firmware update
by Vinod Koul 06 Jun '16

06 Jun '16

Please PULL to receive the updated BSW firmware binary which contains some odd playback noise fixes The following changes since commit f5b546819836f207a6df58d48423ca6112cd2801: linux-firmware: Update firmware patch for Intel Bluetooth 7260 (B5/B6) (2016-06-02 09:51:44 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/firmware.git BSW for you to fetch changes up to 1d079ff33967673e9de44f1ac33de8b62f021b32: linux-firmware: update audio firmware for Braswell platform (2016-06-06 14:24:20 +0530) ---------------------------------------------------------------- Vinod Koul (1): linux-firmware: update audio firmware for Braswell platform WHENCE | 2 +- intel/fw_sst_22a8.bin | Bin 701614 -> 701694 bytes 2 files changed, 1 insertion(+), 1 deletion(-) Thanks -- ~Vinod

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[alsa-devel] [PATCH] ASoC: sgtl5000: only check VDDD-supply, not revision
by Clemens Gruber 06 Jun '16

06 Jun '16

Instead of checking the SGTL5000 chip revision, we should only check if the VDDD regulator exists and only call sgtl5000_replace_vddd_with_ldo if the regulator is missing. Otherwise, the user reads in the kernel log that the internal LDO is used, even though he did follow the NXP recommendation to use external VDDD and also specified VDDD-supply in the devicetree. Also remove the comment, which incorrectly states that external VDDD is only supported for SGTL5000 chip revisions < 0x11. Official NXP documentation recommends using external VDDD and not the internal LDO due to the SGTL5000 erratum ER1. This also applies to revisions >= 0x11. Tested on an i.MX6Q board with SGTL5000 rev 0x11 and external VDDD. Signed-off-by: Clemens Gruber <clemens.gruber(a)pqgruber.com> --- sound/soc/codecs/sgtl5000.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index 08b4046..fbad4fb 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -1286,17 +1286,14 @@ static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) sgtl5000->supplies[i].supply = supply_names[i]; - /* External VDDD only works before revision 0x11 */ - if (sgtl5000->revision < 0x11) { - vddd = regulator_get_optional(codec->dev, "VDDD"); - if (IS_ERR(vddd)) { - /* See if it's just not registered yet */ - if (PTR_ERR(vddd) == -EPROBE_DEFER) - return -EPROBE_DEFER; - } else { - external_vddd = 1; - regulator_put(vddd); - } + vddd = regulator_get_optional(codec->dev, "VDDD"); + if (IS_ERR(vddd)) { + /* See if it's just not registered yet */ + if (PTR_ERR(vddd) == -EPROBE_DEFER) + return -EPROBE_DEFER; + } else { + external_vddd = 1; + regulator_put(vddd); } if (!external_vddd) { -- 2.8.3

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[alsa-devel] [REGRESSION] Headphones no longer working on MacPro6, 1 with 4.4
by Laura Abbott 06 Jun '16

06 Jun '16

Hi, We received a bug report https://bugzilla.redhat.com/show_bug.cgi?id=1316119 that the headphone jack on a MacPro6,1 stopped working on an upgrade from 4.3 to 4.4. The bugzilla has the alsainfo, diffing shows that the Amp-Out vals are different. I tried a revert of 9f660a1c4 (" ALSA: hda/realtek - Fix silent headphone output on MacPro 4,1 (v2)") but that didn't help. Any ideas before asking for a bisect? Does this hardware version need to have the vref fixup as well? Thanks, Laura

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[alsa-devel] sgtl5000: probe failed with error -5
by Catalin Crenguta 06 Jun '16

06 Jun '16

I'm working with a phycore vybrid SoM and I'm having some troubles binding the sgtl5000 audio codec using devicetree. As you can see, the codec driver could not be probed due to error -5. The dts looks like this: sound { compatible = "fsl,imx-audio-sgtl5000"; model = "phycore-vybrid-sgtl5000"; audio-cpu = <&sai2>; audio-codec = <&codec>; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; mux-int-port = <1>; mux-ext-port = <3>; }; /* .... */ &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; /* ... */ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; pinctrl-names = "default"; clocks = <&clks 150>; micbias-resistor-k-ohms = <2>; micbias-voltage-m-volts = <2250>; VDDA-supply = <&reg_3p3v>; VDDIO-supply = <&reg_3p3v>; }; }; /* ... */ &iomuxc { vf610-phycore { pinctrl_i2c2: i2c2grp { fsl,pins = < VF610_PAD_PTA22__I2C2_SCL 0x34d3 VF610_PAD_PTA23__I2C2_SDA 0x34d3 >; }; }; }; After the system boot, the output of dmesg looks like this: dmesg | grep sgtl5000 [ 1.856390] bus: 'i2c': add driver sgtl5000 [ 1.856441] bus: 'i2c': driver_probe_device: matched device 0-000a with driver sgtl5000 [ 1.856462] bus: 'i2c': really_probe: probing driver sgtl5000 with device 0-000a [ 1.856512] sgtl5000 0-000a: no default pinctrl state [ 1.857164] sgtl5000: probe of 0-000a failed with error -5 dmesg | grep sai [ 1.863020] bus: 'platform': add driver fsl-sai [ 1.863098] bus: 'platform': driver_probe_device: matched device 40031000.sai with driver fsl-sai [ 1.863121] bus: 'platform': really_probe: probing driver fsl-sai with device 40031000.sai [ 1.863276] fsl-sai 40031000.sai: no sleep pinctrl state [ 1.863301] fsl-sai 40031000.sai: no idle pinctrl state [ 1.863695] driver: '40031000.sai': driver_bound: bound to device 'fsl-sai' [ 1.863726] bus: 'platform': really_probe: bound device 40031000.sai to driver fsl-sai

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