November 2013 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCHv3] dmaengine: Add support for BCM2835
by Florian Meier 13 Nov '13

13 Nov '13

Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA. Signed-off-by: Florian Meier <florian.meier(a)koalo.de> --- Thank you for your comments! I hope I have now removed all leftovers of the sg struct. Regarding the endian-ness: I have not found any hint about that in the datasheet. Therefore, I chose uint32_t. If you think fixed le32 is more likely I will change it. The PAD fields do not seem to be used, but the datasheet states they should be set to 0. .../devicetree/bindings/dma/bcm2835-dma.txt | 57 ++ arch/arm/boot/dts/bcm2835.dtsi | 23 + drivers/dma/Kconfig | 6 + drivers/dma/Makefile | 1 + drivers/dma/bcm2835-dma.c | 810 ++++++++++++++++++++ 5 files changed, 897 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/bcm2835-dma.txt create mode 100644 drivers/dma/bcm2835-dma.c diff --git a/Documentation/devicetree/bindings/dma/bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt new file mode 100644 index 0000000..9542ac8 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt @@ -0,0 +1,57 @@ +* BCM2835 DMA controller + +Required properties: +- compatible: Should be "brcm,bcm2835-dma". +- reg: Should contain DMA registers location and length. +- interrupts: Should contain all DMA interrupts. First cell is the IRQ bank + Second cell is the IRQ number. +- #dma-cells: Must be <1>, used to represent the number of integer cells in +the dmas property of client devices. +- dma-channels: Maximum number of DMA channels available +- dma-requests: Number of DMA Requests. +- dma-channel-mask: Bit mask representing the channels available. + +Example: + +dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16 + 1 17 + 1 18 + 1 19 + 1 20 + 1 21 + 1 22 + 1 23 + 1 24 + 1 25 + 1 26 + 1 27 + 1 28>; + + #dma-cells = <1>; + dma-channels = <15>; + dma-requests = <32>; + dma-channel-mask = <0x7f35>; +}; + +DMA clients connected to the BCM2835 DMA controller must use the format +described in the dma.txt file, using a two-cell specifier for each channel: +a phandle plus one integer cells. +The two cells in order are: + +1. A phandle pointing to the DMA controller. +2. The DREQ number. + +Example: + +bcm2835_i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = < 0x7e203000 0x20 + 0x7e101098 0x02>; + + dmas = <&dma 2 + &dma 3>; + dma-names = "tx", "rx"; +}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 1e12aef..7389405 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -103,6 +103,29 @@ clocks = <&clk_mmc>; status = "disabled"; }; + + dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16 + 1 17 + 1 18 + 1 19 + 1 20 + 1 21 + 1 22 + 1 23 + 1 24 + 1 25 + 1 26 + 1 27 + 1 28>; + + #dma-cells = <1>; + dma-channels = <15>; /* DMA channel 15 is not handled yet */ + dma-requests = <32>; + dma-channel-mask = <0x7f35>; + }; }; clocks { diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f238cfd..f2d253b 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -288,6 +288,12 @@ config DMA_OMAP select DMA_ENGINE select DMA_VIRTUAL_CHANNELS +config DMA_BCM2835 + tristate "BCM2835 DMA engine support" + depends on (ARCH_BCM2835 || MACH_BCM2708) + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + config TI_CPPI41 tristate "AM33xx CPPI41 DMA support" depends on ARCH_OMAP diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index db89035..6348157 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o obj-$(CONFIG_DMA_OMAP) += omap-dma.o +obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o obj-$(CONFIG_TI_CPPI41) += cppi41.o diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c new file mode 100644 index 0000000..141a698 --- /dev/null +++ b/drivers/dma/bcm2835-dma.c @@ -0,0 +1,810 @@ +/* + * BCM2835 DMA engine support + * + * This driver only supports cyclic DMA transfers + * as needed for the I2S module. + * + * Author: Florian Meier, <florian.meier(a)koalo.de> + * Copyright 2013 + * + * based on + * OMAP DMAengine support by Russell King + * + * BCM2708 DMA Driver + * Copyright (C) 2010 Broadcom + * + * Raspberry Pi PCM I2S ALSA Driver + * Copyright (c) by Phil Poole 2013 + * + * MARVELL MMP Peripheral DMA Driver + * Copyright 2012 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/dmaengine.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_dma.h> + +#include "virt-dma.h" + +struct bcm2835_dmadev { + struct dma_device ddev; + spinlock_t lock; + + uint32_t chans_available; + + void __iomem *dma_base; + int *dma_irq_numbers; + + struct device_dma_parameters dma_parms; +}; + +struct bcm2835_dma_cb { + uint32_t info; + uint32_t src; + uint32_t dst; + uint32_t length; + uint32_t stride; + uint32_t next; + uint32_t pad[2]; +}; + +struct bcm2835_chan { + struct virt_dma_chan vc; + struct list_head node; + + struct dma_slave_config cfg; + unsigned dma_sig; + bool cyclic; + unsigned dreq; + + int dma_ch; + struct bcm2835_desc *desc; + + void __iomem *dma_chan_base; + int dma_irq_number; +}; + +struct bcm2835_desc { + struct virt_dma_desc vd; + enum dma_transfer_direction dir; + dma_addr_t dev_addr; + + unsigned int control_block_size; + struct bcm2835_dma_cb *control_block_base; + dma_addr_t control_block_base_phys; + + unsigned frames; +}; + +#define BCM2835_DMA_CS 0x00 +#define BCM2835_DMA_ADDR 0x04 +#define BCM2835_DMA_SOURCE_AD 0x0c +#define BCM2835_DMA_DEST_AD 0x10 +#define BCM2835_DMA_NEXTCB 0x1C + +/* DMA CS Control and Status bits */ +#define BCM2835_DMA_ACTIVE (1 << 0) +#define BCM2835_DMA_INT (1 << 2) +#define BCM2835_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */ +#define BCM2835_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */ +#define BCM2835_DMA_ERR (1 << 8) +#define BCM2835_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */ +#define BCM2835_DMA_RESET (1 << 31) /* WO, self clearing */ + +#define BCM2835_DMA_INT_EN (1 << 0) +#define BCM2835_DMA_D_INC (1 << 4) +#define BCM2835_DMA_D_DREQ (1 << 6) +#define BCM2835_DMA_S_INC (1 << 8) +#define BCM2835_DMA_S_DREQ (1 << 6) + +#define BCM2835_DMA_PER_MAP(x) ((x) << 16) + +#define BCM2835_DMA_DATA_TYPE_S8 1 +#define BCM2835_DMA_DATA_TYPE_S16 2 +#define BCM2835_DMA_DATA_TYPE_S32 4 +#define BCM2835_DMA_DATA_TYPE_S128 16 + +/* valid only for channels 0 - 14, 15 has its own base address */ +#define BCM2835_DMA_CHAN(n) ((n) << 8) /* base address */ +#define BCM2835_DMA_CHANIO(dma_base, n) ((dma_base) + BCM2835_DMA_CHAN(n)) + +static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) +{ + return container_of(d, struct bcm2835_dmadev, ddev); +} + +static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) +{ + return container_of(c, struct bcm2835_chan, vc.chan); +} + +static inline struct bcm2835_desc *to_bcm2835_dma_desc( + struct dma_async_tx_descriptor *t) +{ + return container_of(t, struct bcm2835_desc, vd.tx); +} + +static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) +{ + struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); + dma_free_coherent(desc->vd.tx.chan->device->dev, + desc->control_block_size, + desc->control_block_base, + desc->control_block_base_phys); + kfree(desc); +} + +static int bcm2835_dma_abort(void __iomem *dma_chan_base) +{ + unsigned long int cs; + int rc = 0; + + cs = readl(dma_chan_base + BCM2835_DMA_CS); + + if (BCM2835_DMA_ACTIVE & cs) { + long int timeout = 10000; + + /* write 0 to the active bit - pause the DMA */ + writel(0, dma_chan_base + BCM2835_DMA_CS); + + /* wait for any current AXI transfer to complete */ + while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0) + cs = readl(dma_chan_base + BCM2835_DMA_CS); + + if (cs & BCM2835_DMA_ISPAUSED) { + /* we'll un-pause when we set of our next DMA */ + rc = -ETIMEDOUT; + + } else if (BCM2835_DMA_ACTIVE & cs) { + /* terminate the control block chain */ + writel(0, dma_chan_base + BCM2835_DMA_NEXTCB); + + /* abort the whole DMA */ + writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, + dma_chan_base + BCM2835_DMA_CS); + } + } + + return rc; +} + +static void bcm2835_dma_start_desc(struct bcm2835_chan *c) +{ + struct virt_dma_desc *vd = vchan_next_desc(&c->vc); + struct bcm2835_desc *d; + + if (!vd) { + c->desc = NULL; + return; + } + + list_del(&vd->node); + + c->desc = d = to_bcm2835_dma_desc(&vd->tx); + + dsb(); /* ARM data synchronization (push) operation */ + + writel(d->control_block_base_phys, c->dma_chan_base + BCM2835_DMA_ADDR); + writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS); +} + +static irqreturn_t bcm2835_dma_callback(int irq, void *data) +{ + struct bcm2835_chan *c = data; + struct bcm2835_desc *d; + unsigned long flags; + + spin_lock_irqsave(&c->vc.lock, flags); + + /* acknowledge interrupt */ + writel(BCM2835_DMA_INT, c->dma_chan_base + BCM2835_DMA_CS); + + d = c->desc; + + if (d) { + if (!c->cyclic) { + bcm2835_dma_start_desc(c); + vchan_cookie_complete(&d->vd); + } else { + vchan_cyclic_callback(&d->vd); + } + } + + /* keep the DMA engine running */ + dsb(); /* ARM synchronization barrier */ + writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS); + + spin_unlock_irqrestore(&c->vc.lock, flags); + + return IRQ_HANDLED; +} + +static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) +{ + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + int ret; + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(chan->device); + uint32_t chans = d->chans_available; + int chanID = 0; + unsigned long flags; + + spin_lock_irqsave(&d->lock, flags); + + chans = d->chans_available; + + dev_dbg(c->vc.chan.device->dev, + "allocating channel for %u\n", c->dma_sig); + + /* do not use the FIQ and BULK channels */ + chans &= ~0xD; + + if (!chans) { + spin_unlock_irqrestore(&d->lock, flags); + return -ENOMEM; + } + + /* return the ordinal of the first channel in the bitmap */ + chanID = __ffs(chans); + + /* claim the channel */ + d->chans_available &= ~(1 << chanID); + + c->dma_chan_base = BCM2835_DMA_CHANIO(d->dma_base, chanID); + c->dma_irq_number = d->dma_irq_numbers[chanID]; + c->dma_ch = chanID; + + ret = request_irq(c->dma_irq_number, + bcm2835_dma_callback, 0, "DMA IRQ", c); + + spin_unlock_irqrestore(&d->lock, flags); + + if (ret < 0) + return ret; + + return 0; +} + +static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) +{ + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(chan->device); + unsigned long flags; + + spin_lock_irqsave(&d->lock, flags); + vchan_free_chan_resources(&c->vc); + d->chans_available |= 1 << c->dma_ch; + free_irq(c->dma_irq_number, c); + spin_unlock_irqrestore(&d->lock, flags); + + dev_dbg(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig); +} + +static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) +{ + unsigned i; + size_t size; + + for (size = i = 0; i < d->frames; i++) { + struct bcm2835_dma_cb *control_block = + &d->control_block_base[i]; + + size += control_block->length; + } + + return size; +} + +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) +{ + unsigned i; + size_t size; + + for (size = i = 0; i < d->frames; i++) { + struct bcm2835_dma_cb *control_block = + &d->control_block_base[i]; + size_t this_size = control_block->length; + dma_addr_t dma; + + if (d->dir == DMA_DEV_TO_MEM) + dma = control_block->dst; + else + dma = control_block->src; + + if (size) + size += this_size; + else if (addr >= dma && addr < dma + this_size) + size += dma + this_size - addr; + } + + return size; +} + +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *txstate) +{ + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + struct virt_dma_desc *vd; + enum dma_status ret; + unsigned long flags; + + ret = dma_cookie_status(chan, cookie, txstate); + if (ret == DMA_SUCCESS || !txstate) + return ret; + + spin_lock_irqsave(&c->vc.lock, flags); + vd = vchan_find_desc(&c->vc, cookie); + if (vd) { + txstate->residue = + bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); + } else if (c->desc && c->desc->vd.tx.cookie == cookie) { + struct bcm2835_desc *d = c->desc; + dma_addr_t pos; + + if (d->dir == DMA_MEM_TO_DEV) + pos = readl(c->dma_chan_base + BCM2835_DMA_SOURCE_AD); + else if (d->dir == DMA_DEV_TO_MEM) + pos = readl(c->dma_chan_base + BCM2835_DMA_DEST_AD); + else + pos = 0; + + txstate->residue = bcm2835_dma_desc_size_pos(d, pos); + } else { + txstate->residue = 0; + } + + spin_unlock_irqrestore(&c->vc.lock, flags); + + return ret; +} + +static void bcm2835_dma_issue_pending(struct dma_chan *chan) +{ + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + unsigned long flags; + + c->cyclic = true; /* nothing else is implemented */ + + spin_lock_irqsave(&c->vc.lock, flags); + if (vchan_issue_pending(&c->vc) && !c->desc) { + bcm2835_dma_start_desc(c); + } + spin_unlock_irqrestore(&c->vc.lock, flags); +} + + +static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + enum dma_slave_buswidth dev_width; + struct bcm2835_desc *d; + dma_addr_t dev_addr; + unsigned es, sync_type; + unsigned frame; + + /* Grab configuration */ + if (direction == DMA_DEV_TO_MEM) { + dev_addr = c->cfg.src_addr; + dev_width = c->cfg.src_addr_width; + sync_type = BCM2835_DMA_S_DREQ; + } else if (direction == DMA_MEM_TO_DEV) { + dev_addr = c->cfg.dst_addr; + dev_width = c->cfg.dst_addr_width; + sync_type = BCM2835_DMA_D_DREQ; + } else { + dev_err(chan->device->dev, "%s: bad direction?\n", __func__); + return NULL; + } + + /* Bus width translates to the element size (ES) */ + switch (dev_width) { + case DMA_SLAVE_BUSWIDTH_4_BYTES: + es = BCM2835_DMA_DATA_TYPE_S32; + break; + default: + return NULL; + } + + /* Now allocate and setup the descriptor. */ + d = kzalloc(sizeof(*d), GFP_ATOMIC); + if (!d) + return NULL; + + d->dir = direction; + d->dev_addr = dev_addr; + d->frames = buf_len / period_len; + + /* Allocate memory for control blocks */ + d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); + d->control_block_base = dma_alloc_coherent(chan->device->dev, + d->control_block_size, &d->control_block_base_phys, + GFP_KERNEL); + + if (!d->control_block_base) { + dev_err(chan->device->dev, + "%s: Memory allocation error\n", __func__); + return NULL; + } + + memset(d->control_block_base, 0, d->control_block_size); + + /* + * Iterate over all frames, create a control block + * for each frame and link them together. + */ + for (frame = 0; frame < d->frames; frame++) { + struct bcm2835_dma_cb *control_block = + &d->control_block_base[frame]; + + /* Setup adresses */ + if (d->dir == DMA_DEV_TO_MEM) { + control_block->info = BCM2835_DMA_D_INC; + control_block->src = d->dev_addr; + control_block->dst = buf_addr + frame * period_len; + } else { + control_block->info = BCM2835_DMA_S_INC; + control_block->src = buf_addr + frame * period_len; + control_block->dst = d->dev_addr; + } + + /* Enable interrupt */ + control_block->info |= BCM2835_DMA_INT_EN; + + /* Setup synchronization */ + if (sync_type != 0) + control_block->info |= sync_type; + + /* Setup DREQ channel */ + if (c->dreq != 0) + control_block->info |= + BCM2835_DMA_PER_MAP(c->dreq); + + /* Length of a frame */ + control_block->length = period_len; + + /* + * Next block is the next frame. + * This DMA engine driver currently only supports cyclic DMA. + * Therefore, wrap around at number of frames. + */ + control_block->next = d->control_block_base_phys + + sizeof(struct bcm2835_dma_cb) * ((frame + 1) % (d->frames)); + + /* The following fields are not used here */ + control_block->stride = 0; + control_block->pad[0] = 0; + control_block->pad[1] = 0; + } + + return vchan_tx_prep(&c->vc, &d->vd, flags); +} + +static int bcm2835_dma_slave_config(struct bcm2835_chan *c, + struct dma_slave_config *cfg) +{ + if ((cfg->direction == DMA_DEV_TO_MEM && + cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || + (cfg->direction == DMA_MEM_TO_DEV && + cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || + (cfg->direction != DMA_DEV_TO_MEM && + cfg->direction != DMA_MEM_TO_DEV)) { + return -EINVAL; + } + + c->cfg = *cfg; + + return 0; +} + +static int bcm2835_dma_terminate_all(struct bcm2835_chan *c) +{ + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); + unsigned long flags; + int timeout = 1000; + LIST_HEAD(head); + + spin_lock_irqsave(&c->vc.lock, flags); + + /* Prevent this channel being scheduled */ + spin_lock(&d->lock); + list_del_init(&c->node); + spin_unlock(&d->lock); + + /* + * Stop DMA activity: we assume the callback will not be called + * after bcm_dma_abort() returns (even if it does, it will see + * c->desc is NULL and exit.) + */ + if (c->desc) { + c->desc = NULL; + bcm2835_dma_abort(c->dma_chan_base); + + /* Wait for stopping */ + while (timeout > 0) { + timeout--; + if(!(readl(c->dma_chan_base + BCM2835_DMA_CS) & + BCM2835_DMA_ACTIVE)) + break; + + cpu_relax(); + } + } + + vchan_get_all_descriptors(&c->vc, &head); + spin_unlock_irqrestore(&c->vc.lock, flags); + vchan_dma_desc_free_list(&c->vc, &head); + + return 0; +} + +static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) +{ + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + int ret; + + switch (cmd) { + case DMA_SLAVE_CONFIG: + return bcm2835_dma_slave_config(c, + (struct dma_slave_config *)arg); + + case DMA_TERMINATE_ALL: + bcm2835_dma_terminate_all(c); + break; + + case DMA_PAUSE: + ret = -EINVAL; + break; + + case DMA_RESUME: + ret = -EINVAL; + break; + + default: + ret = -ENXIO; + break; + } + + return ret; +} + +static int bcm2835_dma_chan_init(struct bcm2835_dmadev *od, int dma_sig) +{ + struct bcm2835_chan *c; + + c = kzalloc(sizeof(*c), GFP_KERNEL); + if (!c) + return -ENOMEM; + + c->dma_sig = dma_sig; + c->vc.desc_free = bcm2835_dma_desc_free; + vchan_init(&c->vc, &od->ddev); + INIT_LIST_HEAD(&c->node); + + od->ddev.chancnt++; + + return 0; +} + +static void bcm2835_dma_free(struct bcm2835_dmadev *od) +{ + while (!list_empty(&od->ddev.channels)) { + struct bcm2835_chan *c = list_first_entry(&od->ddev.channels, + struct bcm2835_chan, vc.chan.device_node); + + list_del(&c->vc.chan.device_node); + tasklet_kill(&c->vc.task); + kfree(c); + } +} + +#if defined(CONFIG_OF) +static const struct of_device_id bcm2835_dma_of_match[] = { + { + .compatible = "brcm,bcm2835-dma", + } +}; +MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); +#endif + +static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct bcm2835_dmadev *d = ofdma->of_dma_data; + struct dma_chan *chan, *candidate; + +retry: + candidate = NULL; + + /* walk the list of channels registered with the current instance and + * find one that is currently unused */ + list_for_each_entry(chan, &d->ddev.channels, device_node) + if (chan->client_count == 0) { + candidate = chan; + break; + } + + if (!candidate) + return NULL; + + /* dma_get_slave_channel will return NULL if we lost a race between + * the lookup and the reservation */ + chan = dma_get_slave_channel(candidate); + + if (chan) { + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + + /* Set DREQ from param */ + c->dreq = dma_spec->args[0]; + + return chan; + } + + goto retry; +} + +static int bcm2835_dma_probe(struct platform_device *pdev) +{ + struct bcm2835_dmadev *od; + struct resource *dma_res = NULL; + void __iomem *dma_base = NULL; + int rc = 0; + int i; + struct resource *irq; + int irq_resources; + + if (!pdev->dev.dma_mask) + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (rc) + return rc; + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); + if (!od) + return -ENOMEM; + + pdev->dev.dma_parms = &od->dma_parms; + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); + + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dma_base = devm_ioremap_resource(&pdev->dev, dma_res); + if (IS_ERR(dma_base)) + return PTR_ERR(dma_base); + + od->dma_base = dma_base; + + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); + od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; + od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; + od->ddev.device_tx_status = bcm2835_dma_tx_status; + od->ddev.device_issue_pending = bcm2835_dma_issue_pending; + od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; + od->ddev.device_control = bcm2835_dma_control; + od->ddev.dev = &pdev->dev; + INIT_LIST_HEAD(&od->ddev.channels); + spin_lock_init(&od->lock); + + irq_resources = 0; + + for (i = 0; i < pdev->num_resources; i++) { + if (platform_get_resource(pdev, IORESOURCE_IRQ, i) > 0) + irq_resources++; + } + + od->dma_irq_numbers = devm_kzalloc(&pdev->dev, + irq_resources*sizeof(int), GFP_KERNEL); + if (!od) + return -ENOMEM; + + for (i = 0; i < irq_resources; i++) { + rc = bcm2835_dma_chan_init(od, i); + if (rc) { + bcm2835_dma_free(od); + return rc; + } + + irq = platform_get_resource(pdev, IORESOURCE_IRQ, i); + if (!irq) { + dev_err(&pdev->dev, + "No IRQ resource for channel %i\n", i); + return -ENODEV; + } + od->dma_irq_numbers[i] = irq->start; + } + + rc = dma_async_device_register(&od->ddev); + if (rc) { + dev_err(&pdev->dev, + "Failed to register slave DMA engine device: %d\n", rc); + bcm2835_dma_free(od); + return rc; + } + + platform_set_drvdata(pdev, od); + + if (pdev->dev.of_node) { + const void *chan_mask; + + /* Device-tree DMA controller registration */ + rc = of_dma_controller_register(pdev->dev.of_node, + bcm2835_dma_xlate, od); + if (rc) { + dev_err(&pdev->dev, "Failed to register DMA controller\n"); + dma_async_device_unregister(&od->ddev); + bcm2835_dma_free(od); + return rc; + } + + /* Request DMA channel mask from device tree */ + chan_mask = of_get_property(pdev->dev.of_node, + "dma-channel-mask", NULL); + + if (!chan_mask) { + dev_err(&pdev->dev, "Failed to get channel mask\n"); + dma_async_device_unregister(&od->ddev); + bcm2835_dma_free(od); + return -EINVAL; + } + + od->chans_available = be32_to_cpup(chan_mask); + } + + dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n"); + + return rc; +} + +static int bcm2835_dma_remove(struct platform_device *pdev) +{ + struct bcm2835_dmadev *od = platform_get_drvdata(pdev); + + dma_async_device_unregister(&od->ddev); + bcm2835_dma_free(od); + + return 0; +} + +static struct platform_driver bcm2835_dma_driver = { + .probe = bcm2835_dma_probe, + .remove = bcm2835_dma_remove, + .driver = { + .name = "bcm2835-dma", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(bcm2835_dma_of_match), + }, +}; + +module_platform_driver(bcm2835_dma_driver); + +MODULE_AUTHOR("Florian Meier"); +MODULE_DESCRIPTION("BCM2835 DMA engine driver"); +MODULE_LICENSE("GPL"); + -- 1.7.9.5

4 3

[alsa-devel] [PATCH v2 1/2] ASoC: dmaengine-pcm: Add support for querying DMA capabilities
by Lars-Peter Clausen 13 Nov '13

13 Nov '13

Currently each platform making use the the generic dmaengine PCM driver still needs to provide a custom snd_pcm_hardware struct which specifies the capabilities of the DMA controller, e.g. the maximum period size that can be supported. This patch adds code which uses the newly introduced dma_get_slave_caps() API to query this information from the dmaengine driver. The new code path will only be taken if the 'pcm_hardware' field of the snd_dmaengine_pcm_config struct is NULL. The patch also introduces a new 'fifo_size' field to the snd_dmaengine_dai_dma_data struct which is used to initialize the snd_pcm_hardware 'fifo_size' field and needs to be set by the DAI driver. Signed-off-by: Lars-Peter Clausen <lars(a)metafoo.de> --- Changes since v1: * Use dma_get_max_seg_size() to get the maximum size of one period * Assume that a DMA engine driver is able to support an infinite number of periods * Increase min_period_bytes from 16 to 256. --- include/sound/dmaengine_pcm.h | 2 ++ sound/soc/soc-generic-dmaengine-pcm.c | 55 ++++++++++++++++++++++++++++------- 2 files changed, 47 insertions(+), 10 deletions(-) diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h index f11c35c..83b2c3e 100644 --- a/include/sound/dmaengine_pcm.h +++ b/include/sound/dmaengine_pcm.h @@ -61,6 +61,7 @@ struct dma_chan *snd_dmaengine_pcm_get_chan(struct snd_pcm_substream *substream) * @slave_id: Slave requester id for the DMA channel. * @filter_data: Custom DMA channel filter data, this will usually be used when * requesting the DMA channel. + * @fifo_size: FIFO size of the DAI controller in bytes */ struct snd_dmaengine_dai_dma_data { dma_addr_t addr; @@ -68,6 +69,7 @@ struct snd_dmaengine_dai_dma_data { u32 maxburst; unsigned int slave_id; void *filter_data; + unsigned int fifo_size; }; void snd_dmaengine_pcm_set_config_from_dai_data( diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c index e29ec3c..c39e19e 100644 --- a/sound/soc/soc-generic-dmaengine-pcm.c +++ b/sound/soc/soc-generic-dmaengine-pcm.c @@ -36,6 +36,15 @@ static struct dmaengine_pcm *soc_platform_to_pcm(struct snd_soc_platform *p) return container_of(p, struct dmaengine_pcm, platform); } +static struct device *dmaengine_dma_dev(struct dmaengine_pcm *pcm, + struct snd_pcm_substream *substream) +{ + if (!pcm->chan[substream->stream]) + return NULL; + + return pcm->chan[substream->stream]->device->dev; +} + /** * snd_dmaengine_pcm_prepare_slave_config() - Generic prepare_slave_config callback * @substream: PCM substream @@ -92,28 +101,54 @@ static int dmaengine_pcm_hw_params(struct snd_pcm_substream *substream, return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); } -static int dmaengine_pcm_open(struct snd_pcm_substream *substream) +static int dmaengine_pcm_set_runtime_hwparams(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct dmaengine_pcm *pcm = soc_platform_to_pcm(rtd->platform); + struct device *dma_dev = dmaengine_dma_dev(pcm, substream); struct dma_chan *chan = pcm->chan[substream->stream]; + struct snd_dmaengine_dai_dma_data *dma_data; + struct dma_slave_caps dma_caps; + struct snd_pcm_hardware hw; int ret; - ret = snd_soc_set_runtime_hwparams(substream, + if (pcm->config->pcm_hardware) + return snd_soc_set_runtime_hwparams(substream, pcm->config->pcm_hardware); - if (ret) - return ret; - return snd_dmaengine_pcm_open(substream, chan); + dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); + + memset(&hw, 0, sizeof(hw)); + hw.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED; + hw.periods_min = 2; + hw.periods_max = UINT_MAX; + hw.period_bytes_min = 256; + hw.period_bytes_max = dma_get_max_seg_size(dma_dev); + hw.buffer_bytes_max = SIZE_MAX; + hw.fifo_size = dma_data->fifo_size; + + ret = dma_get_slave_caps(chan, &dma_caps); + if (ret == 0) { + if (dma_caps.cmd_pause) + hw.info |= SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME; + } + + return snd_soc_set_runtime_hwparams(substream, &hw); } -static struct device *dmaengine_dma_dev(struct dmaengine_pcm *pcm, - struct snd_pcm_substream *substream) +static int dmaengine_pcm_open(struct snd_pcm_substream *substream) { - if (!pcm->chan[substream->stream]) - return NULL; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct dmaengine_pcm *pcm = soc_platform_to_pcm(rtd->platform); + struct dma_chan *chan = pcm->chan[substream->stream]; + int ret; - return pcm->chan[substream->stream]->device->dev; + ret = dmaengine_pcm_set_runtime_hwparams(substream); + if (ret) + return ret; + + return snd_dmaengine_pcm_open(substream, chan); } static void dmaengine_pcm_free(struct snd_pcm *pcm) -- 1.8.0

3 12

[alsa-devel] [PATCH 1/2] ALSA: hda - Don't turn off EAPD for headphone on Lenovo N100
by Takashi Iwai 13 Nov '13

13 Nov '13

The only EAPD on AD1986A is on NID 0x1b where usually the speaker. But this doesn't control only the speaker amp but may influence on all outputs, e.g. Lenovo N100 laptop seems to have this issue. Cc: <stable(a)vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_analog.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_analog.c b/sound/pci/hda/patch_analog.c index 87d2e0335ae4..ba37116168ac 100644 --- a/sound/pci/hda/patch_analog.c +++ b/sound/pci/hda/patch_analog.c @@ -219,8 +219,12 @@ static int alloc_ad_spec(struct hda_codec *codec) static void ad_fixup_inv_jack_detect(struct hda_codec *codec, const struct hda_fixup *fix, int action) { - if (action == HDA_FIXUP_ACT_PRE_PROBE) + struct ad198x_spec *spec = codec->spec; + + if (action == HDA_FIXUP_ACT_PRE_PROBE) { codec->inv_jack_detect = 1; + spec->gen.keep_eapd_on = 1; + } } enum { -- 1.8.4.2

1 1

[alsa-devel] [patch] ALSA: snd-aoa: two copy and paste bugs
by Dan Carpenter 13 Nov '13

13 Nov '13

These functions were cut and paste and the tests for NULL weren't updated properly. Signed-off-by: Dan Carpenter <dan.carpenter(a)oracle.com> diff --git a/sound/aoa/fabrics/layout.c b/sound/aoa/fabrics/layout.c index 61ab640..9dc5806 100644 --- a/sound/aoa/fabrics/layout.c +++ b/sound/aoa/fabrics/layout.c @@ -644,7 +644,7 @@ static int n##_control_put(struct snd_kcontrol *kcontrol, \ struct snd_ctl_elem_value *ucontrol) \ { \ struct gpio_runtime *gpio = snd_kcontrol_chip(kcontrol); \ - if (gpio->methods && gpio->methods->get_##n) \ + if (gpio->methods && gpio->methods->set_##n) \ gpio->methods->set_##n(gpio, \ !!ucontrol->value.integer.value[0]); \ return 1; \ @@ -1135,7 +1135,7 @@ static int aoa_fabric_layout_resume(struct soundbus_dev *sdev) { struct layout_dev *ldev = dev_get_drvdata(&sdev->ofdev.dev); - if (ldev->gpio.methods && ldev->gpio.methods->all_amps_off) + if (ldev->gpio.methods && ldev->gpio.methods->all_amps_restore) ldev->gpio.methods->all_amps_restore(&ldev->gpio); return 0;

3 2

[alsa-devel] [patch] ALSA: isa: not allocating enough space
by Dan Carpenter 13 Nov '13

13 Nov '13

We allocate only 4 bytes here "sizeof(int)" instead of WF_MSAMPLE_BYTES (259) which was intended. Signed-off-by: Dan Carpenter <dan.carpenter(a)oracle.com> diff --git a/sound/isa/wavefront/wavefront_synth.c b/sound/isa/wavefront/wavefront_synth.c index a2f87f9..e5db001 100644 --- a/sound/isa/wavefront/wavefront_synth.c +++ b/sound/isa/wavefront/wavefront_synth.c @@ -1196,7 +1196,7 @@ wavefront_send_multisample (snd_wavefront_t *dev, wavefront_patch_info *header) int num_samples; unsigned char *msample_hdr; - msample_hdr = kmalloc(sizeof(WF_MSAMPLE_BYTES), GFP_KERNEL); + msample_hdr = kmalloc(WF_MSAMPLE_BYTES, GFP_KERNEL); if (! msample_hdr) return -ENOMEM;

2 1

[alsa-devel] Can HD-A codec Realtek ALC898 support 20/24 bit playback and recording? How to verify this?
by Lin, Mengdong 13 Nov '13

13 Nov '13

Hi, I have a ALC898 codec. Can it support 20bit and 24bit playback or recording? If yes, how can I verify this? The audio input/output nodes show PCM bits [0xe]: 16 20 24 But I get error when using "-D hw" to record or play S24_LE format: $ arecord -D hw:1,0 -r 48000 -f S24_LE -c 2 test.wav Recording WAVE 'test.wav' : Signed 24 bit Little Endian, Rate 48000 Hz, Stereo arecord: set_params:1081: Sample format non available Available formats: - S16_LE - S32_LE $ aplay -t wav -D hw:1,0 test.wav Playing WAVE 'test.wav' : Signed 24 bit Little Endian, Rate 48000 Hz, Stereo aplay: set_params:1081: Sample format non available Available formats: - S16_LE - S32_LE Here is the codec info: Codec: Realtek ALC898 Address: 2 AFG Function Id: 0x1 (unsol 1) Vendor Id: 0x10ec0899 Subsystem Id: 0x80862046 Revision Id: 0x100003 No Modem Function Group found Default PCM: rates [0x5f0]: 32000 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Default Amp-In caps: N/A Default Amp-Out caps: N/A State of AFG node 0x01: Power states: D0 D1 D2 D3 CLKSTOP EPSS Power: setting=D0, actual=D0 GPIO: io=2, o=0, i=0, unsolicited=1, wake=0 IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 Node 0x02 [Audio Output] wcaps 0x411: Stereo Device: name="ALC898 Analog", type="Audio", device=0 Converter: stream=8, channel=0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x03 [Audio Output] wcaps 0x411: Stereo Converter: stream=8, channel=0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x04 [Audio Output] wcaps 0x411: Stereo Converter: stream=8, channel=0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x05 [Audio Output] wcaps 0x411: Stereo Converter: stream=8, channel=0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x06 [Audio Output] wcaps 0x611: Stereo Digital Converter: stream=8, channel=0 Digital: Digital category: 0x0 IEC Coding Type: 0x0 PCM: rates [0x5f0]: 32000 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x07 [Audio Input] wcaps 0x10051b: Stereo Amp-In Control: name="Capture Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Capture Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Device: name="ALC898 Analog", type="Audio", device=0 Amp-In caps: ofs=0x17, nsteps=0x3f, stepsize=0x02, mute=1 Amp-In vals: [0x27 0x27] Converter: stream=4, channel=0 SDI-Select: 0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x24 Node 0x08 [Audio Input] wcaps 0x10051b: Stereo Amp-In Control: name="Capture Volume", index=1, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Capture Switch", index=1, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Device: name="ALC898 Alt Analog", type="Audio", device=2 Amp-In caps: ofs=0x17, nsteps=0x3f, stepsize=0x02, mute=1 Amp-In vals: [0x80 0x80] Converter: stream=0, channel=0 SDI-Select: 0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x23 Node 0x09 [Audio Input] wcaps 0x10051b: Stereo Amp-In Control: name="Capture Volume", index=2, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Capture Switch", index=2, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Amp-In caps: ofs=0x17, nsteps=0x3f, stepsize=0x02, mute=1 Amp-In vals: [0x80 0x80] Converter: stream=0, channel=0 SDI-Select: 0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x22 Node 0x0a [Audio Input] wcaps 0x100791: Stereo Digital Converter: stream=0, channel=0 SDI-Select: 0 Digital: Digital category: 0x0 IEC Coding Type: 0x0 PCM: rates [0x570]: 32000 44100 48000 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Unsolicited: tag=00, enabled=0 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x1f Node 0x0b [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Control: name="Front Mic Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=1, ofs=0 Control: name="Front Mic Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=1, ofs=0 Control: name="Rear Mic Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Rear Mic Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Line Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Control: name="Line Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Control: name="Beep Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=5, ofs=0 Control: name="Beep Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=5, ofs=0 Amp-In caps: ofs=0x17, nsteps=0x1f, stepsize=0x05, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] Connection: 10 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x14 0x15 0x16 0x17 Node 0x0c [Audio Mixer] wcaps 0x20010f: Stereo Amp-In Amp-Out Control: name="Front Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x00 0x00] Amp-Out caps: ofs=0x57, nsteps=0x57, stepsize=0x02, mute=0 Amp-Out vals: [0x3b 0x3b] Connection: 2 0x02 0x0b Node 0x0d [Audio Mixer] wcaps 0x20010f: Stereo Amp-In Amp-Out Control: name="Surround Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x00 0x00] Amp-Out caps: ofs=0x57, nsteps=0x57, stepsize=0x02, mute=0 Amp-Out vals: [0x00 0x00] Connection: 2 0x03 0x0b Node 0x0e [Audio Mixer] wcaps 0x20010f: Stereo Amp-In Amp-Out Control: name="Center Playback Volume", index=0, device=0 ControlAmp: chs=1, dir=Out, idx=0, ofs=0 Control: name="LFE Playback Volume", index=0, device=0 ControlAmp: chs=2, dir=Out, idx=0, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x00 0x00] Amp-Out caps: ofs=0x57, nsteps=0x57, stepsize=0x02, mute=0 Amp-Out vals: [0x00 0x00] Connection: 2 0x04 0x0b Node 0x0f [Audio Mixer] wcaps 0x20010f: Stereo Amp-In Amp-Out Control: name="Headphone Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x00 0x00] Amp-Out caps: ofs=0x57, nsteps=0x57, stepsize=0x02, mute=0 Amp-Out vals: [0x3b 0x3b] Connection: 2 0x05 0x0b Node 0x10 [Audio Output] wcaps 0x611: Stereo Digital Control: name="IEC958 Playback Con Mask", index=0, device=0 Control: name="IEC958 Playback Pro Mask", index=0, device=0 Control: name="IEC958 Playback Default", index=0, device=0 Control: name="IEC958 Playback Switch", index=0, device=0 Control: name="IEC958 Default PCM Playback Switch", index=0, device=0 Device: name="ALC898 Digital", type="SPDIF", device=1 Converter: stream=8, channel=0 Digital: Digital category: 0x0 IEC Coding Type: 0x0 PCM: rates [0x5f0]: 32000 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x11 [Pin Complex] wcaps 0x400701: Stereo Digital Control: name="SPDIF Phantom Jack", index=0, device=0 Pincap 0x00000010: OUT Pin Default 0x01451120: [Jack] SPDIF Out at Ext Rear Conn = Optical, Color = Black DefAssociation = 0x2, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x40: OUT Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x10 Node 0x12 [Pin Complex] wcaps 0x400401: Stereo Pincap 0x00000020: IN Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x00: Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x13 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x14 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Control: name="Front Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Line Out Front Jack", index=0, device=0 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x0001003c: IN OUT HP EAPD Detect EAPD 0x2: EAPD Pin Default 0x01014410: [Jack] Line Out at Ext Rear Conn = 1/8, Color = Green DefAssociation = 0x1, Sequence = 0x0 Pin-ctls: 0x00: Unsolicited: tag=05, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c* 0x0d 0x0e 0x0f 0x26 Node 0x15 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Control: name="Surround Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Line Out Surround Jack", index=0, device=0 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000003c: IN OUT HP Detect Pin Default 0x01011412: [Jack] Line Out at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0x1, Sequence = 0x2 Pin-ctls: 0x00: Unsolicited: tag=06, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c 0x0d* 0x0e 0x0f 0x26 Node 0x16 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Control: name="Center Playback Switch", index=0, device=0 ControlAmp: chs=1, dir=Out, idx=0, ofs=0 Control: name="LFE Playback Switch", index=0, device=0 ControlAmp: chs=2, dir=Out, idx=0, ofs=0 Control: name="Line Out CLFE Jack", index=0, device=0 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000003c: IN OUT HP Detect Pin Default 0x01016411: [Jack] Line Out at Ext Rear Conn = 1/8, Color = Orange DefAssociation = 0x1, Sequence = 0x1 Pin-ctls: 0x00: Unsolicited: tag=07, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c 0x0d 0x0e* 0x0f 0x26 Node 0x17 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000003c: IN OUT HP Detect Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN Unsolicited: tag=00, enabled=0 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c 0x0d 0x0e 0x0f* 0x26 Node 0x18 [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Control: name="Rear Mic Boost Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Rear Mic Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000373c: IN OUT HP Detect Vref caps: HIZ 50 GRD 80 100 Pin Default 0x01a19c40: [Jack] Mic at Ext Rear Conn = 1/8, Color = Pink DefAssociation = 0x4, Sequence = 0x0 Pin-ctls: 0x21: IN VREF_50 Unsolicited: tag=03, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c* 0x0d 0x0e 0x0f 0x26 Node 0x19 [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Control: name="Front Mic Boost Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Front Mic Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000373c: IN OUT HP Detect Vref caps: HIZ 50 GRD 80 100 Pin Default 0x02a19c41: [Jack] Mic at Ext Front Conn = 1/8, Color = Pink DefAssociation = 0x4, Sequence = 0x1 Pin-ctls: 0x24: IN VREF_80 Unsolicited: tag=02, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c* 0x0d 0x0e 0x0f 0x26 Node 0x1a [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Control: name="Line Boost Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Line Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000373c: IN OUT HP Detect Vref caps: HIZ 50 GRD 80 100 Pin Default 0x0181344f: [Jack] Line In at Ext Rear Conn = 1/8, Color = Blue DefAssociation = 0x4, Sequence = 0xf Pin-ctls: 0x20: IN VREF_HIZ Unsolicited: tag=04, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c* 0x0d 0x0e 0x0f 0x26 Node 0x1b [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out Control: name="Headphone Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Front Headphone Jack", index=0, device=0 Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-In vals: [0x00 0x00] Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x0001373c: IN OUT HP EAPD Detect Vref caps: HIZ 50 GRD 80 100 EAPD 0x2: EAPD Pin Default 0x02214450: [Jack] HP Out at Ext Front Conn = 1/8, Color = Green DefAssociation = 0x5, Sequence = 0x0 Pin-ctls: 0xc0: OUT HP VREF_HIZ Unsolicited: tag=01, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 5 0x0c 0x0d 0x0e 0x0f* 0x26 Node 0x1c [Pin Complex] wcaps 0x400481: Stereo Pincap 0x00000024: IN Detect Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN Unsolicited: tag=00, enabled=0 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x1d [Pin Complex] wcaps 0x400400: Mono Pincap 0x00000020: IN Pin Default 0x4016f601: [N/A] Speaker at Ext N/A Conn = Digital, Color = Other DefAssociation = 0x0, Sequence = 0x1 Pin-ctls: 0x20: IN Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x1e [Pin Complex] wcaps 0x400701: Stereo Digital Control: name="SPDIF Phantom Jack", index=1, device=0 Pincap 0x00000010: OUT Pin Default 0x90460130: [Fixed] SPDIF Out at Int N/A Conn = Digital, Color = Unknown DefAssociation = 0x3, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x40: OUT Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 1 0x06 Node 0x1f [Pin Complex] wcaps 0x400681: Stereo Digital Pincap 0x00000020: IN Pin Default 0x411111f0: [N/A] Speaker at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN Unsolicited: tag=00, enabled=0 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x20 [Vendor Defined Widget] wcaps 0xf00040: Mono Processing caps: benign=0, ncoeff=28 Node 0x21 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x22 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x00 0x00] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] Connection: 11 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x14 0x15 0x16 0x17 0x0b Node 0x23 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x00 0x00] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] Connection: 11 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x14 0x15 0x16 0x17 0x0b Node 0x24 [Audio Selector] wcaps 0x300101: Stereo Connection: 12 0x18 0x19* 0x1a 0x1b 0x1c 0x1d 0x14 0x15 0x16 0x17 0x0b 0x12 Node 0x25 [Audio Output] wcaps 0x411: Stereo Converter: stream=0, channel=0 PCM: rates [0x5e0]: 44100 48000 88200 96000 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Node 0x26 [Audio Mixer] wcaps 0x20010f: Stereo Amp-In Amp-Out Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x80 0x80] Amp-Out caps: ofs=0x57, nsteps=0x57, stepsize=0x02, mute=0 Amp-Out vals: [0x57 0x57] Connection: 2 0x25 0x0b Regards Mengdong

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[alsa-devel] [PATCH] ALSA: pcm: retrieve true appl_ptr where stream was unlocked
by Oskar Schirmer 12 Nov '13

12 Nov '13

Calculated for data transfer, the local variable appl_ptr is reused, changed and written back later, though the lock was not held during the transfer earlier. Admitted, destiny of the lock is not obvious at all, but this looks much like a race condition candidate, so make sure to have some original appl_ptr value to work on. Two occurences. Signed-off-by: Oskar Schirmer <oskar(a)scara.com> --- sound/core/pcm_lib.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c index 6e03b46..47e836a 100644 --- a/sound/core/pcm_lib.c +++ b/sound/core/pcm_lib.c @@ -2051,6 +2051,7 @@ static snd_pcm_sframes_t snd_pcm_lib_write1(struct snd_pcm_substream *substream, default: break; } + appl_ptr = runtime->control->appl_ptr; appl_ptr += frames; if (appl_ptr >= runtime->boundary) appl_ptr -= runtime->boundary; @@ -2283,6 +2284,7 @@ static snd_pcm_sframes_t snd_pcm_lib_read1(struct snd_pcm_substream *substream, default: break; } + appl_ptr = runtime->control->appl_ptr; appl_ptr += frames; if (appl_ptr >= runtime->boundary) appl_ptr -= runtime->boundary; -- 1.7.9.5

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[alsa-devel] Please backport "ALSA: hda - Move one-time init codes from generic_hdmi_init" to 3.4/3.5
by David Henningsson 12 Nov '13

12 Nov '13

Hi, This is a real oldie, but better late than never. A while back, I discovered that this patch would help against a kernel panic when "cat /proc/asound/card0/codec0" was executed on this machine, which was running an fglrx driver. I asked for a stable backport, but Takashi wanted testing to make sure this was actually fixed by the patch [1]. And now, several months later, I have this confirmation [2]. The test was conducted on an 3.5 Ubuntu kernel, based on the 3.5 extended stable tree, but would apply equally well to 3.4. I'm attaching the backported patch - it applied cleanly, I've just added an extra section with an explanation. -- David Henningsson, Canonical Ltd. https://launchpad.net/~diwic [1] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060132.html [2] https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1212160/comments/4

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[alsa-devel] [PATCH] ASoC: fsl: set correct platform drvdata in pcm030_fabric_probe()
by Wei Yongjun 12 Nov '13

12 Nov '13

From: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> platform_set_drvdata(op, pdata) in pcm030_fabric_probe() will be overwrited when calling snd_soc_register_card(card), but cm030_fabric_remove() use drvdata as a type of struct pcm030_audio_data, so we should move platform_set_drvdata() below snd_soc_register_card() call. Signed-off-by: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> --- sound/soc/fsl/pcm030-audio-fabric.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/soc/fsl/pcm030-audio-fabric.c b/sound/soc/fsl/pcm030-audio-fabric.c index eb43738..3665f61 100644 --- a/sound/soc/fsl/pcm030-audio-fabric.c +++ b/sound/soc/fsl/pcm030-audio-fabric.c @@ -69,7 +69,6 @@ static int pcm030_fabric_probe(struct platform_device *op) return -ENOMEM; card->dev = &op->dev; - platform_set_drvdata(op, pdata); pdata->card = card; @@ -98,6 +97,8 @@ static int pcm030_fabric_probe(struct platform_device *op) if (ret) dev_err(&op->dev, "snd_soc_register_card() failed: %d\n", ret); + platform_set_drvdata(op, pdata); + return ret; }

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[alsa-devel] [PATCH] ASoC: wm8997: Correct typo in ISRC mux routes
by Charles Keepax 12 Nov '13

12 Nov '13

Signed-off-by: Charles Keepax <ckeepax(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm8997.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/sound/soc/codecs/wm8997.c b/sound/soc/codecs/wm8997.c index 6ec3de3..2e886ca 100644 --- a/sound/soc/codecs/wm8997.c +++ b/sound/soc/codecs/wm8997.c @@ -887,7 +887,7 @@ static const struct snd_soc_dapm_route wm8997_dapm_routes[] = { ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Mic"), ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), - ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), -- 1.7.2.5

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