September 2010 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCH] ASoC: Add max98088 CODEC driver
by Peter Hsiang 22 Sep '10

22 Sep '10

This patch adds the MAX98088 CODEC driver. Signed-off-by: Peter Hsiang <peter.hsiang at maxim-ic.com> --- include/sound/max98088.h | 87 ++ sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/max98088.c | 2871 +++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/max98088.h | 161 +++ 5 files changed, 3125 insertions(+), 0 deletions(-) create mode 100644 include/sound/max98088.h create mode 100644 sound/soc/codecs/max98088.c create mode 100644 sound/soc/codecs/max98088.h diff --git a/include/sound/max98088.h b/include/sound/max98088.h new file mode 100644 index 0000000..7a6c53c --- /dev/null +++ b/include/sound/max98088.h @@ -0,0 +1,87 @@ +/* + * Platform data for MAX98088 + * + * Copyright 2010 Maxim Integrated Products + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __SOUND_MAX98088_PDATA_H__ +#define __SOUND_MAX98088_PDATA_H__ + +#define EQ_CFG_MAX 32 + +/* Equalizer filter response configuration */ +struct max98088_eq_cfg { + const char *name; + unsigned int rate; + u16 band1[5]; + u16 band2[5]; + u16 band3[5]; + u16 band4[5]; + u16 band5[5]; +}; + +/* Speaker excursion limiter filter response configurations */ +#define EX_CFG_MAX 32 + +struct max98088_excursion_cfg { + const char *name; + unsigned int rate; + u16 resp[5]; +}; + +/* codec platform data */ +struct max98088_pdata { + + /* Equalizers for DAI1 and DAI2 */ + struct max98088_eq_cfg *eq1_cfg; + struct max98088_eq_cfg *eq2_cfg; + unsigned int eq1_cfgcnt; + unsigned int eq2_cfgcnt; + + /* Excursion limiters for DAI1 and DAI2 */ + struct max98088_excursion_cfg *ex1_cfg; + struct max98088_excursion_cfg *ex2_cfg; + unsigned int ex1_cfgcnt; + unsigned int ex2_cfgcnt; + + /* Receiver output can be configured as power amplifier or LINE out */ + /* Set receiver_mode to: + * 0 = amplifier output, or + * 1 = LINE level output + */ + unsigned int receiver_mode; + + /* Analog/digital microphone configuration: + * 0 = analog microphone input (normal setting) + * 1 = digital microhpone input + */ + unsigned int digmic_left_enable; + unsigned int digmic_right_enable; + + /* Normal microphone connection, or external connection through INA + * 0 = normal connection + * 1 = INA1 input + * 2 = INA2 input + */ + unsigned int extmic_mode; + + /* Bypass option for INA to MIC1 connection + * 0 = normal setting + * 1 = bypass enabled + */ + unsigned int ina_to_mic1_bypass; + + /* Bypass option for MIC1 to MIC2 connection + * 0 = normal setting + * 1 = bypass enabled + */ + unsigned int mic1_to_mic2_bypass; +}; + +#endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 155c127..e9a3c74 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -28,6 +28,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_DA7210 if I2C select SND_SOC_JZ4740 if SOC_JZ4740 select SND_SOC_MAX9877 if I2C + select SND_SOC_MAX98088 if I2C select SND_SOC_PCM3008 select SND_SOC_SPDIF select SND_SOC_SSM2602 if I2C @@ -156,6 +157,9 @@ config SND_SOC_L3 config SND_SOC_DA7210 tristate +config SND_SOC_MAX98088 + tristate + config SND_SOC_PCM3008 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 10d468e..fe9d104 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -15,6 +15,7 @@ snd-soc-cs4270-objs := cs4270.o snd-soc-cx20442-objs := cx20442.o snd-soc-da7210-objs := da7210.o snd-soc-l3-objs := l3.o +snd-soc-max98088-objs := max98088.o snd-soc-pcm3008-objs := pcm3008.o snd-soc-spdif-objs := spdif_transciever.o snd-soc-ssm2602-objs := ssm2602.o @@ -87,6 +88,7 @@ obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o +obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif.o obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c new file mode 100644 index 0000000..72f599f --- /dev/null +++ b/sound/soc/codecs/max98088.c @@ -0,0 +1,2871 @@ +/* + * max98088.c -- MAX98088 ALSA SoC Audio driver + * + * Copyright 2010 Maxim Integrated Products + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <linux/slab.h> +#include <sound/max98088.h> +#include "max98088.h" + +static struct snd_soc_codec *max98088_codec; +struct snd_soc_codec_device soc_codec_dev_max98088; + +/* configurations associated with each channel of DAI stream */ +struct max98088_cdata { + unsigned int rate; + unsigned int fmt; + + /* Equalizer parameters */ + int eq_textcnt; + const char *eq_texts[EQ_CFG_MAX]; + int eq_sel; + struct soc_enum eq_enum; + + /* Excursion limiter parameters */ + int ex_textcnt; + const char *ex_texts[EX_CFG_MAX]; + int ex_sel; + struct soc_enum ex_enum; +}; + +/* codec private data */ +struct max98088_priv { + struct snd_soc_codec codec; + struct max98088_pdata *pdata; + u8 reg_cache[M98088_REG_CNT]; + unsigned int sysclk; + struct max98088_cdata dai[2]; + u8 power_state; + unsigned int ex_mode; + unsigned int digmic_mode; +}; + +static const u8 max98088_reg[M98088_REG_CNT] = { + 0x00, /* 00 IRQ status */ + 0x00, /* 01 MIC status */ + 0x00, /* 02 jack status */ + 0x00, /* 03 battery voltage */ + 0x00, /* 04 */ + 0x00, /* 05 */ + 0x00, /* 06 */ + 0x00, /* 07 */ + 0x00, /* 08 */ + 0x00, /* 09 */ + 0x00, /* 0A */ + 0x00, /* 0B */ + 0x00, /* 0C */ + 0x00, /* 0D */ + 0x00, /* 0E */ + 0x00, /* 0F interrupt enable */ + + 0x00, /* 10 master clock */ + 0x00, /* 11 DAI1 clock mode */ + 0x00, /* 12 DAI1 clock control */ + 0x00, /* 13 DAI1 clock control */ + 0x00, /* 14 DAI1 format */ + 0x00, /* 15 DAI1 clock */ + 0x00, /* 16 DAI1 config */ + 0x00, /* 17 DAI1 TDM */ + 0x00, /* 18 DAI1 filters */ + 0x00, /* 19 DAI2 clock mode */ + 0x00, /* 1A DAI2 clock control */ + 0x00, /* 1B DAI2 clock control */ + 0x00, /* 1C DAI2 format */ + 0x00, /* 1D DAI2 clock */ + 0x00, /* 1E DAI2 config */ + 0x00, /* 1F DAI2 TDM */ + + 0x00, /* 20 DAI2 filters */ + 0x00, /* 21 data config */ + 0x00, /* 22 DAC mixer */ + 0x00, /* 23 left ADC mixer */ + 0x00, /* 24 right ADC mixer */ + 0x00, /* 25 left HP mixer */ + 0x00, /* 26 right HP mixer */ + 0x00, /* 27 HP control */ + 0x00, /* 28 left REC mixer */ + 0x00, /* 29 right REC mixer */ + 0x00, /* 2A REC control */ + 0x00, /* 2B left SPK mixer */ + 0x00, /* 2C right SPK mixer */ + 0x00, /* 2D SPK control */ + 0x00, /* 2E sidetone */ + 0x00, /* 2F DAI1 playback level */ + + 0x00, /* 30 DAI1 playback level */ + 0x00, /* 31 DAI2 playback level */ + 0x00, /* 32 DAI2 playbakc level */ + 0x00, /* 33 left ADC level */ + 0x00, /* 34 right ADC level */ + 0x00, /* 35 MIC1 level */ + 0x00, /* 36 MIC2 level */ + 0x00, /* 37 INA level */ + 0x00, /* 38 INB level */ + 0x00, /* 39 left HP volume */ + 0x00, /* 3A right HP volume */ + 0x00, /* 3B left REC volume */ + 0x00, /* 3C right REC volume */ + 0x00, /* 3D left SPK volume */ + 0x00, /* 3E right SPK volume */ + 0x00, /* 3F MIC config */ + + 0x00, /* 40 MIC threshold */ + 0x00, /* 41 excursion limiter filter */ + 0x00, /* 42 excursion limiter threshold */ + 0x00, /* 43 ALC */ + 0x00, /* 44 power limiter threshold */ + 0x00, /* 45 power limiter config */ + 0x00, /* 46 distortion limiter config */ + 0x00, /* 47 audio input */ + 0x00, /* 48 microphone */ + 0x00, /* 49 level control */ + 0x00, /* 4A bypass switches */ + 0x00, /* 4B jack detect */ + 0x00, /* 4C input enable */ + 0x00, /* 4D output enable */ + 0xF0, /* 4E bias control */ + 0x00, /* 4F DAC power */ + + 0x0F, /* 50 DAC power */ + 0x00, /* 51 system */ + 0x00, /* 52 DAI1 EQ1 */ + 0x00, /* 53 DAI1 EQ1 */ + 0x00, /* 54 DAI1 EQ1 */ + 0x00, /* 55 DAI1 EQ1 */ + 0x00, /* 56 DAI1 EQ1 */ + 0x00, /* 57 DAI1 EQ1 */ + 0x00, /* 58 DAI1 EQ1 */ + 0x00, /* 59 DAI1 EQ1 */ + 0x00, /* 5A DAI1 EQ1 */ + 0x00, /* 5B DAI1 EQ1 */ + 0x00, /* 5C DAI1 EQ2 */ + 0x00, /* 5D DAI1 EQ2 */ + 0x00, /* 5E DAI1 EQ2 */ + 0x00, /* 5F DAI1 EQ2 */ + + 0x00, /* 60 DAI1 EQ2 */ + 0x00, /* 61 DAI1 EQ2 */ + 0x00, /* 62 DAI1 EQ2 */ + 0x00, /* 63 DAI1 EQ2 */ + 0x00, /* 64 DAI1 EQ2 */ + 0x00, /* 65 DAI1 EQ2 */ + 0x00, /* 66 DAI1 EQ3 */ + 0x00, /* 67 DAI1 EQ3 */ + 0x00, /* 68 DAI1 EQ3 */ + 0x00, /* 69 DAI1 EQ3 */ + 0x00, /* 6A DAI1 EQ3 */ + 0x00, /* 6B DAI1 EQ3 */ + 0x00, /* 6C DAI1 EQ3 */ + 0x00, /* 6D DAI1 EQ3 */ + 0x00, /* 6E DAI1 EQ3 */ + 0x00, /* 6F DAI1 EQ3 */ + + 0x00, /* 70 DAI1 EQ4 */ + 0x00, /* 71 DAI1 EQ4 */ + 0x00, /* 72 DAI1 EQ4 */ + 0x00, /* 73 DAI1 EQ4 */ + 0x00, /* 74 DAI1 EQ4 */ + 0x00, /* 75 DAI1 EQ4 */ + 0x00, /* 76 DAI1 EQ4 */ + 0x00, /* 77 DAI1 EQ4 */ + 0x00, /* 78 DAI1 EQ4 */ + 0x00, /* 79 DAI1 EQ4 */ + 0x00, /* 7A DAI1 EQ5 */ + 0x00, /* 7B DAI1 EQ5 */ + 0x00, /* 7C DAI1 EQ5 */ + 0x00, /* 7D DAI1 EQ5 */ + 0x00, /* 7E DAI1 EQ5 */ + 0x00, /* 7F DAI1 EQ5 */ + + 0x00, /* 80 DAI1 EQ5 */ + 0x00, /* 81 DAI1 EQ5 */ + 0x00, /* 82 DAI1 EQ5 */ + 0x00, /* 83 DAI1 EQ5 */ + 0x00, /* 84 DAI2 EQ1 */ + 0x00, /* 85 DAI2 EQ1 */ + 0x00, /* 86 DAI2 EQ1 */ + 0x00, /* 87 DAI2 EQ1 */ + 0x00, /* 88 DAI2 EQ1 */ + 0x00, /* 89 DAI2 EQ1 */ + 0x00, /* 8A DAI2 EQ1 */ + 0x00, /* 8B DAI2 EQ1 */ + 0x00, /* 8C DAI2 EQ1 */ + 0x00, /* 8D DAI2 EQ1 */ + 0x00, /* 8E DAI2 EQ2 */ + 0x00, /* 8F DAI2 EQ2 */ + + 0x00, /* 90 DAI2 EQ2 */ + 0x00, /* 91 DAI2 EQ2 */ + 0x00, /* 92 DAI2 EQ2 */ + 0x00, /* 93 DAI2 EQ2 */ + 0x00, /* 94 DAI2 EQ2 */ + 0x00, /* 95 DAI2 EQ2 */ + 0x00, /* 96 DAI2 EQ2 */ + 0x00, /* 97 DAI2 EQ2 */ + 0x00, /* 98 DAI2 EQ3 */ + 0x00, /* 99 DAI2 EQ3 */ + 0x00, /* 9A DAI2 EQ3 */ + 0x00, /* 9B DAI2 EQ3 */ + 0x00, /* 9C DAI2 EQ3 */ + 0x00, /* 9D DAI2 EQ3 */ + 0x00, /* 9E DAI2 EQ3 */ + 0x00, /* 9F DAI2 EQ3 */ + + 0x00, /* A0 DAI2 EQ3 */ + 0x00, /* A1 DAI2 EQ3 */ + 0x00, /* A2 DAI2 EQ4 */ + 0x00, /* A3 DAI2 EQ4 */ + 0x00, /* A4 DAI2 EQ4 */ + 0x00, /* A5 DAI2 EQ4 */ + 0x00, /* A6 DAI2 EQ4 */ + 0x00, /* A7 DAI2 EQ4 */ + 0x00, /* A8 DAI2 EQ4 */ + 0x00, /* A9 DAI2 EQ4 */ + 0x00, /* AA DAI2 EQ4 */ + 0x00, /* AB DAI2 EQ4 */ + 0x00, /* AC DAI2 EQ5 */ + 0x00, /* AD DAI2 EQ5 */ + 0x00, /* AE DAI2 EQ5 */ + 0x00, /* AF DAI2 EQ5 */ + + 0x00, /* B0 DAI2 EQ5 */ + 0x00, /* B1 DAI2 EQ5 */ + 0x00, /* B2 DAI2 EQ5 */ + 0x00, /* B3 DAI2 EQ5 */ + 0x00, /* B4 DAI2 EQ5 */ + 0x00, /* B5 DAI2 EQ5 */ + 0x00, /* B6 DAI1 biquad */ + 0x00, /* B7 DAI1 biquad */ + 0x00, /* B8 DAI1 biquad */ + 0x00, /* B9 DAI1 biquad */ + 0x00, /* BA DAI1 biquad */ + 0x00, /* BB DAI1 biquad */ + 0x00, /* BC DAI1 biquad */ + 0x00, /* BD DAI1 biquad */ + 0x00, /* BE DAI1 biquad */ + 0x00, /* BF DAI1 biquad */ + + 0x00, /* C0 DAI2 biquad */ + 0x00, /* C1 DAI2 biquad */ + 0x00, /* C2 DAI2 biquad */ + 0x00, /* C3 DAI2 biquad */ + 0x00, /* C4 DAI2 biquad */ + 0x00, /* C5 DAI2 biquad */ + 0x00, /* C6 DAI2 biquad */ + 0x00, /* C7 DAI2 biquad */ + 0x00, /* C8 DAI2 biquad */ + 0x00, /* C9 DAI2 biquad */ + 0x00, /* CA */ + 0x00, /* CB */ + 0x00, /* CC */ + 0x00, /* CD */ + 0x00, /* CE */ + 0x00, /* CF */ + + 0x00, /* D0 */ + 0x00, /* D1 */ + 0x00, /* D2 */ + 0x00, /* D3 */ + 0x00, /* D4 */ + 0x00, /* D5 */ + 0x00, /* D6 */ + 0x00, /* D7 */ + 0x00, /* D8 */ + 0x00, /* D9 */ + 0x00, /* DA */ + 0x70, /* DB */ + 0x00, /* DC */ + 0x00, /* DD */ + 0x00, /* DE */ + 0x00, /* DF */ + + 0x00, /* E0 */ + 0x00, /* E1 */ + 0x00, /* E2 */ + 0x00, /* E3 */ + 0x00, /* E4 */ + 0x00, /* E5 */ + 0x00, /* E6 */ + 0x00, /* E7 */ + 0x00, /* E8 */ + 0x00, /* E9 */ + 0x00, /* EA */ + 0x00, /* EB */ + 0x00, /* EC */ + 0x00, /* ED */ + 0x00, /* EE */ + 0x00, /* EF */ + + 0x00, /* F0 */ + 0x00, /* F1 */ + 0x00, /* F2 */ + 0x00, /* F3 */ + 0x00, /* F4 */ + 0x00, /* F5 */ + 0x00, /* F6 */ + 0x00, /* F7 */ + 0x00, /* F8 */ + 0x00, /* F9 */ + 0x00, /* FA */ + 0x00, /* FB */ + 0x00, /* FC */ + 0x00, /* FD */ + 0x00, /* FE */ + 0x00, /* FF */ +}; + +static struct { + int readable; + int writable; + int vol; +} max98088_access[M98088_REG_CNT] = { + { 0xFF, 0xFF, 1 }, /* 00 IRQ status */ + { 0xFF, 0x00, 1 }, /* 01 MIC status */ + { 0xFF, 0x00, 1 }, /* 02 jack status */ + { 0x1F, 0x1F, 1 }, /* 03 battery voltage */ + { 0xFF, 0xFF, 0 }, /* 04 */ + { 0xFF, 0xFF, 0 }, /* 05 */ + { 0xFF, 0xFF, 0 }, /* 06 */ + { 0xFF, 0xFF, 0 }, /* 07 */ + { 0xFF, 0xFF, 0 }, /* 08 */ + { 0xFF, 0xFF, 0 }, /* 09 */ + { 0xFF, 0xFF, 0 }, /* 0A */ + { 0xFF, 0xFF, 0 }, /* 0B */ + { 0xFF, 0xFF, 0 }, /* 0C */ + { 0xFF, 0xFF, 0 }, /* 0D */ + { 0xFF, 0xFF, 0 }, /* 0E */ + { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */ + + { 0xFF, 0xFF, 0 }, /* 10 master clock */ + { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */ + { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */ + { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */ + { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */ + { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */ + { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */ + { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */ + { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */ + { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */ + { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */ + { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */ + { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */ + { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */ + { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */ + { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */ + + { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */ + { 0xFF, 0xFF, 0 }, /* 21 data config */ + { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */ + { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */ + { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */ + { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */ + { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */ + { 0xFF, 0xFF, 0 }, /* 27 HP control */ + { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */ + { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */ + { 0xFF, 0xFF, 0 }, /* 2A REC control */ + { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */ + { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */ + { 0xFF, 0xFF, 0 }, /* 2D SPK control */ + { 0xFF, 0xFF, 0 }, /* 2E sidetone */ + { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */ + + { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */ + { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */ + { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */ + { 0xFF, 0xFF, 0 }, /* 33 left ADC level */ + { 0xFF, 0xFF, 0 }, /* 34 right ADC level */ + { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */ + { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */ + { 0xFF, 0xFF, 0 }, /* 37 INA level */ + { 0xFF, 0xFF, 0 }, /* 38 INB level */ + { 0xFF, 0xFF, 0 }, /* 39 left HP volume */ + { 0xFF, 0xFF, 0 }, /* 3A right HP volume */ + { 0xFF, 0xFF, 0 }, /* 3B left REC volume */ + { 0xFF, 0xFF, 0 }, /* 3C right REC volume */ + { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */ + { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */ + { 0xFF, 0xFF, 0 }, /* 3F MIC config */ + + { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */ + { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */ + { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */ + { 0xFF, 0xFF, 0 }, /* 43 ALC */ + { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */ + { 0xFF, 0xFF, 0 }, /* 45 power limiter config */ + { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */ + { 0xFF, 0xFF, 0 }, /* 47 audio input */ + { 0xFF, 0xFF, 0 }, /* 48 microphone */ + { 0xFF, 0xFF, 0 }, /* 49 level control */ + { 0xFF, 0xFF, 0 }, /* 4A bypass switches */ + { 0xFF, 0xFF, 0 }, /* 4B jack detect */ + { 0xFF, 0xFF, 0 }, /* 4C input enable */ + { 0xFF, 0xFF, 0 }, /* 4D output enable */ + { 0xFF, 0xFF, 0 }, /* 4E bias control */ + { 0xFF, 0xFF, 0 }, /* 4F DAC power */ + + { 0xFF, 0xFF, 0 }, /* 50 DAC power */ + { 0xFF, 0xFF, 0 }, /* 51 system */ + { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */ + + { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */ + + { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */ + { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */ + + { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */ + { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */ + { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */ + + { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */ + { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */ + + { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */ + { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */ + { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */ + + { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */ + { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */ + { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */ + + { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */ + { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */ + { 0x00, 0x00, 0 }, /* CA */ + { 0x00, 0x00, 0 }, /* CB */ + { 0x00, 0x00, 0 }, /* CC */ + { 0x00, 0x00, 0 }, /* CD */ + { 0x00, 0x00, 0 }, /* CE */ + { 0x00, 0x00, 0 }, /* CF */ + + { 0x00, 0x00, 0 }, /* D0 */ + { 0x00, 0x00, 0 }, /* D1 */ + { 0x00, 0x00, 0 }, /* D2 */ + { 0x00, 0x00, 0 }, /* D3 */ + { 0x00, 0x00, 0 }, /* D4 */ + { 0x00, 0x00, 0 }, /* D5 */ + { 0x00, 0x00, 0 }, /* D6 */ + { 0x00, 0x00, 0 }, /* D7 */ + { 0x00, 0x00, 0 }, /* D8 */ + { 0x00, 0x00, 0 }, /* D9 */ + { 0x00, 0x00, 0 }, /* DA */ + { 0x70, 0x70, 0 }, /* DB */ + { 0x00, 0x00, 0 }, /* DC */ + { 0x00, 0x00, 0 }, /* DD */ + { 0x00, 0x00, 0 }, /* DE */ + { 0x00, 0x00, 0 }, /* DF */ + + { 0x00, 0x00, 0 }, /* E0 */ + { 0x00, 0x00, 0 }, /* E1 */ + { 0x00, 0x00, 0 }, /* E2 */ + { 0x00, 0x00, 0 }, /* E3 */ + { 0x00, 0x00, 0 }, /* E4 */ + { 0x00, 0x00, 0 }, /* E5 */ + { 0x00, 0x00, 0 }, /* E6 */ + { 0x00, 0x00, 0 }, /* E7 */ + { 0x00, 0x00, 0 }, /* E8 */ + { 0x00, 0x00, 0 }, /* E9 */ + { 0x00, 0x00, 0 }, /* EA */ + { 0x00, 0x00, 0 }, /* EB */ + { 0x00, 0x00, 0 }, /* EC */ + { 0x00, 0x00, 0 }, /* ED */ + { 0x00, 0x00, 0 }, /* EE */ + { 0x00, 0x00, 0 }, /* EF */ + + { 0x00, 0x00, 0 }, /* F0 */ + { 0x00, 0x00, 0 }, /* F1 */ + { 0x00, 0x00, 0 }, /* F2 */ + { 0x00, 0x00, 0 }, /* F3 */ + { 0x00, 0x00, 0 }, /* F4 */ + { 0x00, 0x00, 0 }, /* F5 */ + { 0x00, 0x00, 0 }, /* F6 */ + { 0x00, 0x00, 0 }, /* F7 */ + { 0x00, 0x00, 0 }, /* F8 */ + { 0x00, 0x00, 0 }, /* F9 */ + { 0x00, 0x00, 0 }, /* FA */ + { 0x00, 0x00, 0 }, /* FB */ + { 0x00, 0x00, 0 }, /* FC */ + { 0x00, 0x00, 0 }, /* FD */ + { 0x00, 0x00, 0 }, /* FE */ + { 0xFF, 0x00, 1 }, /* FF */ +}; + + +static int max98088_volatile_register(unsigned int reg) +{ + return max98088_access[reg].vol; +} + +/* + * Read the MAX98088 I2C register space + * Note: this driver source code is backward compatible to kernel + * version 2.6.32. + */ +static unsigned int max98088_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + struct max98088_priv *max98088 = codec->private_data; + struct i2c_msg msg[2]; + struct i2c_client *client; + u8 data[2]; + int ret; + + client = (struct i2c_client *)codec->control_data; + + if (max98088_volatile_register(reg)) { + data[0] = reg; + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].buf = &data[0]; + msg[0].len = 1; + + msg[1].addr = client->addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = &data[1]; + msg[1].len = 1; + + ret = i2c_transfer(client->adapter, &msg[0], 2); + return (ret == 2) ? data[1] : -EIO; + } else { + if (reg > (ARRAY_SIZE(max98088_reg))) + return -EIO; + return max98088->reg_cache[reg]; + } +} + +/* Write to the MAX98088 register space (cached) */ +static int max98088_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + struct max98088_priv *max98088 = codec->private_data; + + data[0] = reg; + data[1] = value; + if (codec->hw_write(codec->control_data, data, 2) == 2) { + max98088->reg_cache[reg] = + (value & max98088_access[reg].writable); + return 0; + } else { + return -EIO; + } +} + +/* Write to the MAX98088 I2C register space */ +static int max98088_hw_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + data[0] = reg; + data[1] = value; + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +/* + * For kernels compiled without unsigned long long int division + */ +unsigned long long int ulldiv(unsigned long long int dividend, + unsigned long long int divisor) +{ + unsigned long long int quotient = 0; + int shift = 1; + + if (divisor == 0) + return 0; + + /* result is 1.0 if divisor and dividend are equal */ + if (divisor == dividend) + return 1; + + /* Normalize divisor */ + while (!(divisor & 0x8000000000000000ULL)) { + divisor <<= 1; + ++shift; + } + + /* Shift and subtract */ + while (shift--) { + quotient <<= 1; + + if (divisor <= dividend) { + dividend -= divisor; + ++quotient; + } + divisor >>= 1; + } + + /* Round up */ + if (dividend > divisor) + ++quotient; + + return quotient; +} + +#define INA1_PGA_BIT 0x01 +#define INA2_PGA_BIT 0x02 +#define INB1_PGA_BIT 0x04 +#define INB2_PGA_BIT 0x08 +/* + * The INx1 and INx2 PGAs share a power control signal. + * This function OR's the two power events to keep an unpowered INx + * from turning off it's counterpart. + * The control names are used to identify the PGA. + */ +static int max98088_pga_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *k, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct max98088_priv *max98088 = codec->private_data; + u8 *state = &max98088->power_state; + unsigned int val; + unsigned int pga; + unsigned int mask; + + BUG_ON(w->reg != M98088_REG_4C_PWR_EN_IN); + + if (strncmp(w->name, "INA1", 4) == 0) { + pga = INA1_PGA_BIT; + mask = INA1_PGA_BIT | INA2_PGA_BIT; + } else if (strncmp(w->name, "INA2", 4) == 0) { + pga = INA2_PGA_BIT; + mask = INA1_PGA_BIT | INA2_PGA_BIT; + } else if (strncmp(w->name, "INB1", 4) == 0) { + pga = INB1_PGA_BIT; + mask = INB1_PGA_BIT | INB2_PGA_BIT; + } else if (strncmp(w->name, "INB2", 4) == 0) { + pga = INB2_PGA_BIT; + mask = INB1_PGA_BIT | INB2_PGA_BIT; + } else { + return -EINVAL; + } + + if (event == SND_SOC_DAPM_POST_PMU) { + /* ON */ + *state |= pga; + + /* Turn on, avoiding unnecessary writes */ + val = max98088_read(codec, w->reg); + if (!(val & (1 << w->shift))) { + val |= (1 << w->shift); + max98088_write(codec, w->reg, val); + } + } else if (event == SND_SOC_DAPM_POST_PMD) { + /* OFF */ + *state &= ~pga; + + /* Turn off if both are off, avoiding unnecessary writes */ + if (!(*state & mask)) { + val = max98088_read(codec, w->reg); + if (val & (1 << w->shift)) { + val &= ~(1 << w->shift); + max98088_write(codec, w->reg, val); + } + } + } else { + return -EINVAL; + } + + return 0; +} + +/* + * Load equalizer DSP coefficient configurations registers + */ +void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai, + unsigned int band, u16 *coefs) +{ + unsigned int eq_reg; + unsigned int i; + + if (band > 4) + return; + + if (dai > 1) + return; + + /* Load the base register address */ + eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; + + /* Add the band address offset, note adjustment for word address */ + eq_reg += band * (M98088_COEFS_PER_BAND << 1); + + /* Step through the registers and coefs */ + for (i = 0; i < M98088_COEFS_PER_BAND; i++) { + max98088_write(codec, eq_reg++, M98088_BYTE1(coefs[i])); + max98088_write(codec, eq_reg++, M98088_BYTE0(coefs[i])); + } + + return; +} + +/* + * Excursion limiter modes + */ +static const char *max98088_ex_mode[] = { + "Off", + "100Hz", + "400Hz", + "600Hz", + "800Hz", + "1000Hz", + "200-400Hz", + "400-600Hz", + "400-800Hz", + "user-400Hz", + "user-600Hz", + "user-800Hz", + "user-1000Hz" +}; + +static const unsigned int ex_mode_table[] = { + 0x00, /* disabled */ + (0<<4)|3, /* 100Hz */ + (1<<4)|0, /* 400Hz */ + (2<<4)|0, /* 600Hz */ + (3<<4)|0, /* 800Hz */ + (4<<4)|0, /* 1000Hz */ + (1<<4)|1, /* 200-400Hz */ + (2<<4)|2, /* 400-600Hz */ + (3<<4)|2, /* 400-800Hz */ + (1<<4)|3, /* user-400Hz */ + (2<<4)|3, /* user-600Hz */ + (3<<4)|3, /* user-800Hz */ + (4<<4)|3 /* user-1000Hz */ +}; + +static const struct soc_enum max98088_ex_mode_enum[] = { + SOC_ENUM_SINGLE_EXT(13, max98088_ex_mode), +}; + +/* + * Excursion limiter mode - set mode + */ +static int max98088_ex_mode_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + unsigned int *mode = &max98088->ex_mode; + + *mode = ucontrol->value.integer.value[0]; + + if (*mode <= ARRAY_SIZE(ex_mode_table)) + max98088_write(codec, M98088_REG_41_SPKDHP, + ex_mode_table[*mode]); + + return 0; +} + +/* + * Excursion limiter mode - get mode + */ +static int max98088_ex_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + unsigned int *mode = &max98088->ex_mode; + + ucontrol->value.integer.value[0] = *mode; + return 0; +} + +/* + * Load user programmable mode excursion limiter filter coefficients + */ +static void max98088_ex_resp_control(struct snd_soc_codec *codec, + int reg, u16 *param) +{ + max98088_write(codec, reg, M98088_BYTE1(param[0])); + max98088_write(codec, ++reg, M98088_BYTE0(param[0])); + max98088_write(codec, ++reg, M98088_BYTE1(param[1])); + max98088_write(codec, ++reg, M98088_BYTE0(param[1])); + max98088_write(codec, ++reg, M98088_BYTE1(param[2])); + max98088_write(codec, ++reg, M98088_BYTE0(param[2])); + max98088_write(codec, ++reg, M98088_BYTE1(param[3])); + max98088_write(codec, ++reg, M98088_BYTE0(param[3])); + max98088_write(codec, ++reg, M98088_BYTE1(param[4])); + max98088_write(codec, ++reg, M98088_BYTE0(param[4])); +} + +static const char *max98088_hp_spk_mute[] = {"disable", "enable"}; +static const struct soc_enum max98088_hp_spk_mute_enum[] = { + SOC_ENUM_SINGLE_EXT(2, max98088_hp_spk_mute), +}; +/* These defines correlate to the position of the like named value in + * max98088_hp_spk_mute[] */ +#define MAX98088_HP_SPK_MUTE_DISABLE 0 +#define MAX98088_HP_SPK_MUTE_ENABLE 1 + +/* + * Mute the speaker + */ +static int max98088_spk_mute_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u8 lReg = max98088_read(codec, M98088_REG_3D_LVL_SPK_L); + u8 rReg = max98088_read(codec, M98088_REG_3E_LVL_SPK_R); + + if (MAX98088_HP_SPK_MUTE_ENABLE == ucontrol->value.integer.value[0]) { + lReg |= M98088_SP_MUTE; + rReg |= M98088_SP_MUTE; + } else { + lReg &= ~M98088_SP_MUTE; + rReg &= ~M98088_SP_MUTE; + } + + max98088_write(codec, M98088_REG_3D_LVL_SPK_L, lReg); + max98088_write(codec, M98088_REG_3E_LVL_SPK_R, rReg); + + return 0; +} + +/* + * Get speaker mute status + */ +static int max98088_spk_mute_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u8 reg = max98088_read(codec, M98088_REG_3D_LVL_SPK_L); + + ucontrol->value.integer.value[0] = (reg & M98088_SP_MUTE) ? 1 : 0; + + return 0; +} + +/* + * Mute the headphone + */ +static int max98088_hp_mute_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u8 lReg = max98088_read(codec, M98088_REG_39_LVL_HP_L); + u8 rReg = max98088_read(codec, M98088_REG_3A_LVL_HP_R); + + if (MAX98088_HP_SPK_MUTE_ENABLE == ucontrol->value.integer.value[0]) { + lReg |= M98088_HP_MUTE; + rReg |= M98088_HP_MUTE; + } else { + lReg &= ~M98088_HP_MUTE; + rReg &= ~M98088_HP_MUTE; + } + + max98088_write(codec, M98088_REG_39_LVL_HP_L, lReg); + max98088_write(codec, M98088_REG_3A_LVL_HP_R, rReg); + + return 0; +} + +/* + * Get current headphone mute status + */ +static int max98088_hp_mute_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u8 reg = max98088_read(codec, M98088_REG_39_LVL_HP_L); + + ucontrol->value.integer.value[0] = (reg & M98088_HP_MUTE) ? 1 : 0; + + return 0; +} + +/* + * Mute the receiver + */ +static int max98088_rec_mute_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u8 lReg = max98088_read(codec, M98088_REG_3B_LVL_REC_L); + u8 rReg = max98088_read(codec, M98088_REG_3C_LVL_REC_R); + + if (MAX98088_HP_SPK_MUTE_ENABLE == ucontrol->value.integer.value[0]) { + lReg |= M98088_REC_MUTE; + rReg |= M98088_REC_MUTE; + } else { + lReg &= ~M98088_REC_MUTE; + rReg &= ~M98088_REC_MUTE; + } + + max98088_write(codec, M98088_REG_3B_LVL_REC_L, lReg); + max98088_write(codec, M98088_REG_3C_LVL_REC_R, rReg); + + return 0; +} + +/* + * Get current receiver mute status + */ +static int max98088_rec_mute_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u8 reg = max98088_read(codec, M98088_REG_3B_LVL_REC_L); + + ucontrol->value.integer.value[0] = (reg & M98088_REC_MUTE) ? 1 : 0; + return 0; +} + +static const char *max98088_ex_thresh[] = { /* volts PP */ + "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"}; +static const struct soc_enum max98088_ex_thresh_enum[] = { + SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8, + max98088_ex_thresh), +}; + +static const char *max98088_fltr_mode[] = {"Voice", "Music" }; +static const struct soc_enum max98088_filter_mode_enum[] = { + SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode), +}; + +static const char *max98088_dai1_fltr[] = { + "Off", "fc=258/fs=16k", "fc=500/fs=16k", + "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"}; +static const struct soc_enum max98088_dai1_dac_filter_enum[] = { + SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr), +}; +static const struct soc_enum max98088_dai1_adc_filter_enum[] = { + SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr), +}; + +static const char *max98088_dcblk[] = {"Off", "On"}; +static const struct soc_enum max98088_dcblk_enum[] = { + SOC_ENUM_SINGLE(M98088_REG_20_DAI2_FILTERS, 0, 2, max98088_dcblk), +}; + +/* amixer controls (non-dapm) */ +static const struct snd_kcontrol_new max98088_snd_controls[] = { + + /* analog output levels */ + + SOC_DOUBLE_R("Headphone volume", M98088_REG_39_LVL_HP_L, + M98088_REG_3A_LVL_HP_R, 0, 31, 0), + SOC_DOUBLE_R("Speaker volume", M98088_REG_3D_LVL_SPK_L, + M98088_REG_3E_LVL_SPK_R, 0, 31, 0), + SOC_DOUBLE_R("Receiver volume", M98088_REG_3B_LVL_REC_L, + M98088_REG_3C_LVL_REC_R, 0, 31, 0), + + SOC_ENUM_EXT("Headphone mute", max98088_hp_spk_mute_enum, + max98088_hp_mute_get, max98088_hp_mute_set), + SOC_ENUM_EXT("Speaker mute", max98088_hp_spk_mute_enum, + max98088_spk_mute_get, max98088_spk_mute_set), + SOC_ENUM_EXT("Receiver mute", max98088_hp_spk_mute_enum, + max98088_rec_mute_get, max98088_rec_mute_set), + + /* analog input levels */ + + SOC_SINGLE("MIC1 gain", M98088_REG_35_LVL_MIC1, 0, 31, 1), + SOC_SINGLE("MIC2 gain", M98088_REG_36_LVL_MIC2, 0, 31, 1), + + SOC_SINGLE("MIC1 pre", M98088_REG_35_LVL_MIC1, 5, 3, 0), + SOC_SINGLE("MIC2 pre", M98088_REG_36_LVL_MIC2, 5, 3, 0), + + SOC_SINGLE("INA gain", M98088_REG_37_LVL_INA, 0, 7, 1), + SOC_SINGLE("INB gain", M98088_REG_38_LVL_INB, 0, 7, 1), + + /* ADC input digital gains and volume control */ + + SOC_SINGLE("ADCL volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0), + SOC_SINGLE("ADCR volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0), + + SOC_SINGLE("ADCL gain", M98088_REG_33_LVL_ADC_L, 4, 3, 0), + SOC_SINGLE("ADCR gain", M98088_REG_34_LVL_ADC_R, 4, 3, 0), + + /* equalizer */ + + SOC_SINGLE("EQ1 switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0), + SOC_SINGLE("EQ2 switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0), + + /* excursion limiter */ + + SOC_ENUM_EXT("EX limiter mode", max98088_ex_mode_enum, + max98088_ex_mode_get, max98088_ex_mode_set), + SOC_ENUM("EX limiter threshold", max98088_ex_thresh_enum), + + /* voice/music filters */ + + SOC_ENUM("DAI1 filter mode", max98088_filter_mode_enum), + SOC_ENUM("DAI1 DAC filter", max98088_dai1_dac_filter_enum), + SOC_ENUM("DAI1 ADC filter", max98088_dai1_adc_filter_enum), + SOC_ENUM("DAI2 DC block", max98088_dcblk_enum), + + /* automatic level control (for both DAI1/DAI2) */ + + SOC_SINGLE("ALC switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0), + SOC_SINGLE("ALC threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0), + SOC_SINGLE("ALC multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0), + SOC_SINGLE("ALC release time", M98088_REG_43_SPKALC_COMP, 4, 7, 0), + + /* power limiter */ + + SOC_SINGLE("PWR limiter threshold", M98088_REG_44_PWRLMT_CFG, + 4, 15, 0), + SOC_SINGLE("PWR limiter weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0), + SOC_SINGLE("PWR limiter time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0), + SOC_SINGLE("PWR limiter time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0), + + /* THD distortion limiter */ + + SOC_SINGLE("THD limiter thresh", M98088_REG_46_THDLMT_CFG, 4, 15, 0), + SOC_SINGLE("THD limiter time", M98088_REG_46_THDLMT_CFG, 0, 7, 0), +}; + +/* DAPM sub-tables of the main dapm_widgets */ + +/* Left speaker mixer switch */ +static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC1", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC1", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), + SOC_DAPM_SINGLE("Left DAC2", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC2", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), + SOC_DAPM_SINGLE("MIC1", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0), +}; + +/* Right speaker mixer switch */ +static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC1", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC1", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), + SOC_DAPM_SINGLE("Left DAC2", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC2", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), + SOC_DAPM_SINGLE("MIC1", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0), +}; + +/* Left headphone mixer switch */ +static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC1", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC1", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), + SOC_DAPM_SINGLE("Left DAC2", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC2", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), + SOC_DAPM_SINGLE("MIC1", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0), +}; + +/* Right headphone mixer switch */ +static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC1", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC1", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), + SOC_DAPM_SINGLE("Left DAC2", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC2", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), + SOC_DAPM_SINGLE("MIC1", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0), +}; + +/* Left earpiece/receiver mixer switch */ +static const struct snd_kcontrol_new max98088_left_receiver_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC1", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC1", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), + SOC_DAPM_SINGLE("Left DAC2", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC2", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), + SOC_DAPM_SINGLE("MIC1", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0), +}; + +/* Right earpiece/receiver mixer switch */ +static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC1", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC1", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), + SOC_DAPM_SINGLE("Left DAC2", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), + SOC_DAPM_SINGLE("Right DAC2", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), + SOC_DAPM_SINGLE("MIC1", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0), +}; + +/* Left ADC mixer switch */ +static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = { + SOC_DAPM_SINGLE("MIC1", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0), +}; + +/* Right ADC mixer switch */ +static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = { + SOC_DAPM_SINGLE("MIC1", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0), + SOC_DAPM_SINGLE("MIC2", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0), + SOC_DAPM_SINGLE("INA1", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0), + SOC_DAPM_SINGLE("INA2", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0), + SOC_DAPM_SINGLE("INB1", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0), + SOC_DAPM_SINGLE("INB2", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0), +}; + +static int max98088_hp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + u16 status; + + BUG_ON(event != SND_SOC_DAPM_PRE_PMD); + + /* powering down headphone gracefully */ + status = max98088_read(codec, M98088_REG_4D_PWR_EN_OUT); + if ((status & M98088_HPEN) == M98088_HPEN) { + max98088_hw_write(codec, M98088_REG_4D_PWR_EN_OUT, + (status & ~M98088_HPEN)); + } + schedule_timeout_interruptible(msecs_to_jiffies(20)); + + return 0; +} + +/* DAPM widgets top level */ +static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = { + + SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0), + SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0), + + SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", + M98088_REG_4D_PWR_EN_OUT, 1, 0), + SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", + M98088_REG_4D_PWR_EN_OUT, 0, 0), + SND_SOC_DAPM_DAC("DACL2", "Aux Playback", + M98088_REG_4D_PWR_EN_OUT, 1, 0), + SND_SOC_DAPM_DAC("DACR2", "Aux Playback", + M98088_REG_4D_PWR_EN_OUT, 0, 0), + + SND_SOC_DAPM_PGA_E("HP Left Out", M98088_REG_4D_PWR_EN_OUT, + 7, 0, NULL, 0, max98088_hp_event, SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_PGA_E("HP Right Out", M98088_REG_4D_PWR_EN_OUT, + 6, 0, NULL, 0, max98088_hp_event, SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT, + 5, 0, NULL, 0), + SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT, + 4, 0, NULL, 0), + + SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT, + 3, 0, NULL, 0), + SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT, + 2, 0, NULL, 0), + + SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, + &max98088_left_hp_mixer_controls[0], + ARRAY_SIZE(max98088_left_hp_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, + &max98088_right_hp_mixer_controls[0], + ARRAY_SIZE(max98088_right_hp_mixer_controls)), + + SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0, + &max98088_left_speaker_mixer_controls[0], + ARRAY_SIZE(max98088_left_speaker_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0, + &max98088_right_speaker_mixer_controls[0], + ARRAY_SIZE(max98088_right_speaker_mixer_controls)), + + SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0, + &max98088_left_receiver_mixer_controls[0], + ARRAY_SIZE(max98088_left_receiver_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0, + &max98088_right_rec_mixer_controls[0], + ARRAY_SIZE(max98088_right_rec_mixer_controls)), + + SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, + &max98088_left_ADC_mixer_controls[0], + ARRAY_SIZE(max98088_left_ADC_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, + &max98088_right_ADC_mixer_controls[0], + ARRAY_SIZE(max98088_right_ADC_mixer_controls)), + + SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN, + 7, 0, NULL, 0, max98088_pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN, + 7, 0, NULL, 0, max98088_pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN, + 6, 0, NULL, 0, max98088_pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN, + 6, 0, NULL, 0, max98088_pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MICBIAS("Mic Bias", M98088_REG_4C_PWR_EN_IN, 3, 0), + + SND_SOC_DAPM_OUTPUT("HPL"), + SND_SOC_DAPM_OUTPUT("HPR"), + SND_SOC_DAPM_OUTPUT("SPKL"), + SND_SOC_DAPM_OUTPUT("SPKR"), + SND_SOC_DAPM_OUTPUT("RECL"), + SND_SOC_DAPM_OUTPUT("RECR"), + + SND_SOC_DAPM_INPUT("MIC1"), + SND_SOC_DAPM_INPUT("MIC2"), + SND_SOC_DAPM_INPUT("INA1"), + SND_SOC_DAPM_INPUT("INA2"), + SND_SOC_DAPM_INPUT("INB1"), + SND_SOC_DAPM_INPUT("INB2"), +}; + +/* DAPM AUDIO_MAP: */ +static const struct snd_soc_dapm_route audio_map[] = { + /* Left headphone output mixer */ + {"Left HP Mixer", "Left DAC1", "DACL1"}, + {"Left HP Mixer", "Left DAC2", "DACL2"}, + {"Left HP Mixer", "Right DAC1", "DACR1"}, + {"Left HP Mixer", "Right DAC2", "DACR2"}, + {"Left HP Mixer", "MIC1", "Mic Bias"}, + {"Left HP Mixer", "MIC2", "Mic Bias"}, + {"Left HP Mixer", "INA1", "INA1 Input"}, + {"Left HP Mixer", "INA2", "INA2 Input"}, + {"Left HP Mixer", "INB1", "INB1 Input"}, + {"Left HP Mixer", "INB2", "INB2 Input"}, + + /* Right headphone output mixer */ + {"Right HP Mixer", "Left DAC1", "DACL1"}, + {"Right HP Mixer", "Left DAC2", "DACL2" }, + {"Right HP Mixer", "Right DAC1", "DACR1"}, + {"Right HP Mixer", "Right DAC2", "DACR2"}, + {"Right HP Mixer", "MIC1", "Mic Bias"}, + {"Right HP Mixer", "MIC2", "Mic Bias"}, + {"Right HP Mixer", "INA1", "INA1 Input"}, + {"Right HP Mixer", "INA2", "INA2 Input"}, + {"Right HP Mixer", "INB1", "INB1 Input"}, + {"Right HP Mixer", "INB2", "INB2 Input"}, + + /* Left speaker output mixer */ + {"Left SPK Mixer", "Left DAC1", "DACL1"}, + {"Left SPK Mixer", "Left DAC2", "DACL2"}, + {"Left SPK Mixer", "Right DAC1", "DACR1"}, + {"Left SPK Mixer", "Right DAC2", "DACR2"}, + {"Left SPK Mixer", "MIC1", "Mic Bias"}, + {"Left SPK Mixer", "MIC2", "Mic Bias"}, + {"Left SPK Mixer", "INA1", "INA1 Input"}, + {"Left SPK Mixer", "INA2", "INA2 Input"}, + {"Left SPK Mixer", "INB1", "INB1 Input"}, + {"Left SPK Mixer", "INB2", "INB2 Input"}, + + /* Right speaker output mixer */ + {"Right SPK Mixer", "Left DAC1", "DACL1"}, + {"Right SPK Mixer", "Left DAC2", "DACL2"}, + {"Right SPK Mixer", "Right DAC1", "DACR1"}, + {"Right SPK Mixer", "Right DAC2", "DACR2"}, + {"Right SPK Mixer", "MIC1", "Mic Bias"}, + {"Right SPK Mixer", "MIC2", "Mic Bias"}, + {"Right SPK Mixer", "INA1", "INA1 Input"}, + {"Right SPK Mixer", "INA2", "INA2 Input"}, + {"Right SPK Mixer", "INB1", "INB1 Input"}, + {"Right SPK Mixer", "INB2", "INB2 Input"}, + + /* Earpiece/Receiver output mixer */ + {"Left REC Mixer", "Left DAC1", "DACL1"}, + {"Left REC Mixer", "Left DAC2", "DACL2"}, + {"Left REC Mixer", "Right DAC1", "DACR1"}, + {"Left REC Mixer", "Right DAC2", "DACR2"}, + {"Left REC Mixer", "MIC1", "Mic Bias"}, + {"Left REC Mixer", "MIC2", "Mic Bias"}, + {"Left REC Mixer", "INA1", "INA1 Input"}, + {"Left REC Mixer", "INA2", "INA2 Input"}, + {"Left REC Mixer", "INB1", "INB1 Input"}, + {"Left REC Mixer", "INB2", "INB2 Input"}, + + /* Earpiece/Receiver output mixer */ + {"Right REC Mixer", "Left DAC1", "DACL1"}, + {"Right REC Mixer", "Left DAC2", "DACL2"}, + {"Right REC Mixer", "Right DAC1", "DACR1"}, + {"Right REC Mixer", "Right DAC2", "DACR2"}, + {"Right REC Mixer", "MIC1", "Mic Bias"}, + {"Right REC Mixer", "MIC2", "Mic Bias"}, + {"Right REC Mixer", "INA1", "INA1 Input"}, + {"Right REC Mixer", "INA2", "INA2 Input"}, + {"Right REC Mixer", "INB1", "INB1 Input"}, + {"Right REC Mixer", "INB2", "INB2 Input"}, + + {"HP Left Out", NULL, "Left HP Mixer"}, + {"HP Right Out", NULL, "Right HP Mixer"}, + {"SPK Left Out", NULL, "Left SPK Mixer"}, + {"SPK Right Out", NULL, "Right SPK Mixer"}, + {"REC Left Out", NULL, "Left REC Mixer"}, + {"REC Right Out", NULL, "Right REC Mixer"}, + + {"HPL", NULL, "HP Left Out"}, + {"HPR", NULL, "HP Right Out"}, + {"SPKL", NULL, "SPK Left Out"}, + {"SPKR", NULL, "SPK Right Out"}, + {"RECL", NULL, "REC Left Out"}, + {"RECR", NULL, "REC Right Out"}, + + /* Left ADC input mixer */ + {"Left ADC Mixer", "MIC1", "Mic Bias"}, + {"Left ADC Mixer", "MIC2", "Mic Bias"}, + {"Left ADC Mixer", "INA1", "INA1 Input"}, + {"Left ADC Mixer", "INA2", "INA2 Input"}, + {"Left ADC Mixer", "INB1", "INB1 Input"}, + {"Left ADC Mixer", "INB2", "INB2 Input"}, + + /* Right ADC input mixer */ + {"Right ADC Mixer", "MIC1", "Mic Bias"}, + {"Right ADC Mixer", "MIC2", "Mic Bias"}, + {"Right ADC Mixer", "INA1", "INA1 Input"}, + {"Right ADC Mixer", "INA2", "INA2 Input"}, + {"Right ADC Mixer", "INB1", "INB1 Input"}, + {"Right ADC Mixer", "INB2", "INB2 Input"}, + + /* inputs */ + {"ADCL", NULL, "Left ADC Mixer"}, + {"ADCR", NULL, "Right ADC Mixer"}, + + {"INA1 Input", NULL, "INA1"}, + {"INA2 Input", NULL, "INA2"}, + {"INB1 Input", NULL, "INB1"}, + {"INB2 Input", NULL, "INB2"}, + + {"Mic Bias", NULL, "MIC1"}, + {"Mic Bias", NULL, "MIC2"}, +}; + +/* + * Add widgets + */ +static int max98088_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, max98088_dapm_widgets, + ARRAY_SIZE(max98088_dapm_widgets)); + + /* set up audio path interconnects */ + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +/* + * Setup DAI1 format + */ +static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + u8 regval; + + cdata = &max98088->dai[0]; + + if (fmt != cdata->fmt) { + cdata->fmt = fmt; + + /* DAI clock master/slave wrt the codec */ + switch (fmt & SND_SOC_DAIFMT_CBS_CFS) { + case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & frm slave */ + /* MAS: slave */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + M98088_DAI_MAS, 0); + /* slave mode PLL */ + max98088_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, + 0x80); + max98088_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, + 0x00); + break; + case SND_SOC_DAIFMT_CBM_CFM: /* codec clk, frm master */ + /* MAS: master */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + 0, M98088_DAI_MAS); + break; + case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slv, frm mas */ + case SND_SOC_DAIFMT_CBM_CFS: /* codec clk mas, frm slv */ + dev_err(codec->dev, "Clock mode unsupported"); + return -EINVAL;; + } + + /* I2S or TDM */ + if ((fmt & SND_SOC_DAIFMT_I2S) == SND_SOC_DAIFMT_I2S) { + /* TDM: I2S */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + M98088_DAI_TDM, 0); + } else { + /* TDM: PCM/TDM */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + 0, M98088_DAI_TDM); + } + + /* DAI hardware signal inversions */ + switch (fmt & SND_SOC_DAIFMT_NB_NF) { + case SND_SOC_DAIFMT_NB_NF: + /* BCI: normal bclk (rise) */ + /* WCI: normal frame */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + M98088_DAI_BCI|M98088_DAI_WCI, 0); + break; + case SND_SOC_DAIFMT_NB_IF: + /* BCI: normal bclk (rise) */ + /* WCI: invert frame */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + M98088_DAI_BCI, M98088_DAI_WCI); + break; + case SND_SOC_DAIFMT_IB_NF: + /* BCI: invert bclk (fall) */ + /* WCI: normal frame */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + M98088_DAI_WCI, M98088_DAI_BCI); + break; + case SND_SOC_DAIFMT_IB_IF: + /* BCI: invert bclk (fall) */ + /* WCI: invert frame */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + 0, M98088_DAI_BCI|M98088_DAI_WCI); + break; + } + + regval = (1<<0); /* BSEL : 64*LRCLK (for master mode only) */ + if (max98088->digmic_mode) + regval |= (1<<6); /* OSR : oversample ratio */ + max98088_write(codec, M98088_REG_15_DAI1_CLOCK, regval); + + max98088_write(codec, M98088_REG_16_DAI1_IOCFG, + (1<<6) | /* SEL : map DAI1 to S1 */ + (0<<5) | /* LTEN : ADC->DAC loop-through enable */ + (0<<4) | /* LBEN : loopback (0=disable, 1=enable) */ + (0<<3) | /* DMONO : DAC SDIN (0=stereo, 1=mono) */ + (0<<2) | /* HIZOFF : ADC SDOUT (0=HiZ, 1=Drive) */ + (1<<1) | /* SDOEN : serial data out ENABLE */ + (1<<0)); /* SDIEN : serial data in ENABLE */ + + max98088_write(codec, M98088_REG_17_DAI1_TDM, + (0<<6) | /* SLOTL : L in 1st slot */ + (1<<4) | /* SLOTR : R in 2nd slot */ + (0<<0)); /* SLOTDLY : no delay */ + } + + return 0; +} + +/* + * Setup DAI2 format + */ +static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + + cdata = &max98088->dai[1]; + + if (fmt != cdata->fmt) { + cdata->fmt = fmt; + + /* DAI clock master/slave wrt the codec */ + switch (fmt & SND_SOC_DAIFMT_CBS_CFS) { + case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & frm slave */ + /* MAS: slave */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + M98088_DAI_MAS, 0); + /* slave mode PLL */ + max98088_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, + 0x80); + max98088_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, + 0x00); + break; + case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & frm master */ + /* MAS: master */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + 0, M98088_DAI_MAS); + break; + case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slv & frm mas */ + case SND_SOC_DAIFMT_CBM_CFS: /* codec clk mas & frm slv */ + dev_err(codec->dev, "Clock mode unsupported"); + return -EINVAL;; + } + + /* I2S or TDM */ + if ((fmt & SND_SOC_DAIFMT_I2S) == SND_SOC_DAIFMT_I2S) { + /* TDM: I2S */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + M98088_DAI_TDM, 0); + } else { + /* TDM: PCM/TDM */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + 0, M98088_DAI_TDM); + } + + /* DAI hardware signal inversions */ + switch (fmt & SND_SOC_DAIFMT_NB_NF) { + case SND_SOC_DAIFMT_NB_NF: + /* BCI: normal bclk (rise) */ + /* WCI: normal frame */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + M98088_DAI_BCI|M98088_DAI_WCI, 0); + break; + case SND_SOC_DAIFMT_NB_IF: + /* BCI: normal bclk (rise) */ + /* WCI: invert frame */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + M98088_DAI_BCI, M98088_DAI_WCI); + break; + case SND_SOC_DAIFMT_IB_NF: + /* BCI: invert bclk (fall) */ + /* WCI: normal frame */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + M98088_DAI_WCI, M98088_DAI_BCI); + break; + case SND_SOC_DAIFMT_IB_IF: + /* BCI: invert bclk (fall) */ + /* WCI: invert frame */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + 0, M98088_DAI_BCI|M98088_DAI_WCI); + break; + } + + max98088_write(codec, M98088_REG_1D_DAI2_CLOCK, + (1<<0)); /* BSEL: 64*LRCLK (for master mode only) */ + + max98088_write(codec, M98088_REG_1E_DAI2_IOCFG, + (2<<6) | /* SEL : map DAI2 to S2 */ + (0<<4) | /* LBEN : loopback (0=disable) */ + (0<<3) | /* DMONO : DAC SDIN input */ + (0<<2) | /* HIZOFF : ADC SDOUT (0=HiZ, 1=Drive) */ + (1<<1) | /* SDOEN : serial data out ENABLE */ + (1<<0)); /* SDIEN : serial data in ENABLE */ + + max98088_write(codec, M98088_REG_1F_DAI2_TDM, + (0<<6) | /* SLOTL : L in 1st slot */ + (1<<4) | /* SLOTR : R in 2nd slot */ + (0<<0)); /* SLOTDLY : no delay */ + } + + return 0; +} + +static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct max98088_priv *max98088 = codec->private_data; + + if (freq != max98088->sysclk) { + max98088->sysclk = freq; /* remember current sysclk */ + + /* setup clocks for slave mode, and using the PLL + * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) + * 0x02 (when master clk is 20MHz to 30MHz).. + */ + if ((freq >= 10000000) && (freq < 20000000)) { + max98088_write(codec, M98088_REG_10_SYS_CLK, 0x10); + } else if ((freq >= 20000000) && (freq < 30000000)) { + max98088_write(codec, M98088_REG_10_SYS_CLK, 0x20); + } else { + dev_err(codec->dev, "Invalid master clock frequency\n"); + return -EINVAL; + } + + /* If codec is currently running, toggle reset */ + if (max98088_read(codec, M98088_REG_51_PWR_SYS) + & M98088_SHDNRUN) { + snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, + M98088_SHDNRUN, 0); + snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, + 0, M98088_SHDNRUN); + } + } + + dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); + + max98088->sysclk = freq; + return 0; +} + + +struct rate_table_struct { + u32 rate; + u8 sr1; +}; + +/* codec mclk clock divider coefficients */ +static const struct rate_table_struct rate_table[] = { + {8000, 0x1}, + {11025, 0x2}, + {16000, 0x3}, + {22050, 0x4}, + {24000, 0x5}, + {32000, 0x6}, + {44100, 0x7}, + {48000, 0x8}, + {88200, 0x9}, + {96000, 0xA}, +}; + +static inline int rate_index(int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rate_table); i++) { + if (rate_table[i].rate >= rate) + return i; + } + return 0; +} + +/* Setup hw params and sample rate */ +static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + unsigned int rate; + u8 reg11val; + u16 ni; + + cdata = &max98088->dai[0]; + + rate = params_rate(params); + + /* data 16/24 bit width */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + /* WS: 16bit */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + M98088_DAI_WS, 0); + break; + case SNDRV_PCM_FORMAT_S24_LE: + /* WS: 24bit */ + snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, + 0, M98088_DAI_WS); + break; + } + + snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); + + if (rate != cdata->rate) { + /* set DAI1 SR1 value for the DSP; FREQ1:0=anyclock */ + reg11val = (rate_table[rate_index(rate)].sr1 << 4) | 0; + max98088_write(codec, M98088_REG_11_DAI1_CLKMODE, reg11val); + cdata->rate = rate; + } + + /* Configure NI when operating as master */ + if (max98088_read(codec, M98088_REG_14_DAI1_FORMAT) + & M98088_DAI_MAS) { + BUG_ON(max98088->sysclk == 0); + ni = (u16)ulldiv(65536ULL * (rate < 50000 ? 96ULL : 48ULL) + * (unsigned long long int)rate, + (unsigned long long int)max98088->sysclk); + max98088_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, + (ni >> 8) & 0x7f); + max98088_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, + ni & 0xff); + } + + /* Update sample rate mode */ + if (rate < 50000) + snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, + (1<<3), 0); + else + snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, + 0, (1<<3)); + + snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 0, M98088_SHDNRUN); + + return 0; +} + +/* Setup hw params and sample rate */ +static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + unsigned int rate; + u8 reg19val; + u16 ni; + + cdata = &max98088->dai[1]; + + rate = params_rate(params); + + /* data 16/24 bit width */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + /* WS: 16bit */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + M98088_DAI_WS, 0); + break; + case SNDRV_PCM_FORMAT_S24_LE: + /* WS: 24bit */ + snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, + 0, M98088_DAI_WS); + break; + } + + snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); + + if (rate != cdata->rate) { + /* set DAI2 SR2 value for the DSP; FREQ1:0=anyclock */ + reg19val = (rate_table[rate_index(rate)].sr1 << 4) | 0; + max98088_write(codec, M98088_REG_19_DAI2_CLKMODE, reg19val); + cdata->rate = rate; + } + + /* Configure NI when operating as master */ + if (max98088_read(codec, M98088_REG_1C_DAI2_FORMAT) + & M98088_DAI_MAS) { + BUG_ON(max98088->sysclk == 0); + ni = (u16)ulldiv(65536ULL * (rate < 50000 ? 96ULL : 48ULL) + * (unsigned long long int)rate, + (unsigned long long int)max98088->sysclk); + max98088_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, + (ni >> 8) & 0x7f); + max98088_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, + ni & 0xff); + } + + /* Update sample rate mode */ + if (rate < 50000) + snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, + (1<<3), 0); + else + snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, + 0, (1<<3)); + + snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 0, M98088_SHDNRUN); + + return 0; +} + +static void max98088_sync_cache(struct snd_soc_codec *codec) +{ + struct max98088_priv *max98088 = codec->private_data; + int i; + + /* write back cached values if they're writeable and + * different from the hardware default. + */ + for (i = 1; i < ARRAY_SIZE(max98088->reg_cache); i++) { + if (!max98088_access[i].writable) + continue; + + if (max98088->reg_cache[i] == max98088_reg[i]) + continue; + + snd_soc_write(codec, i, max98088->reg_cache[i]); + } +} + +static int max98088_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + max98088_write(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN); + break; + + case SND_SOC_BIAS_PREPARE: + max98088_write(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN); + break; + + case SND_SOC_BIAS_STANDBY: + max98088_sync_cache(codec); + max98088_write(codec, M98088_REG_51_PWR_SYS, + M98088_SHDNRUN|M98088_PWRSV); + break; + case SND_SOC_BIAS_OFF: + max98088_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV); + break; + } + codec->bias_level = level; + return 0; +} + +#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 +#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) + +static struct snd_soc_dai_ops max98088_dai1_ops = { + .set_sysclk = max98088_dai_set_sysclk, + .set_fmt = max98088_dai1_set_fmt, + .hw_params = max98088_dai1_hw_params, +}; + +static struct snd_soc_dai_ops max98088_dai2_ops = { + .set_sysclk = max98088_dai_set_sysclk, + .set_fmt = max98088_dai2_set_fmt, + .hw_params = max98088_dai2_hw_params, +}; + +struct snd_soc_dai max98088_dai[] = { +{ + .name = "HiFi", + .playback = { + .stream_name = "HiFi Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MAX98088_RATES, + .formats = MAX98088_FORMATS, + }, + .capture = { + .stream_name = "HiFi Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MAX98088_RATES, + .formats = MAX98088_FORMATS, + }, + .ops = &max98088_dai1_ops, +}, +{ + .name = "Aux", + .playback = { + .stream_name = "Aux Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MAX98088_RATES, + .formats = MAX98088_FORMATS, + }, + .ops = &max98088_dai2_ops, +} +}; +EXPORT_SYMBOL_GPL(max98088_dai); + + +static void max98088_setup_eq1(struct snd_soc_codec *codec) +{ + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_eq_cfg *coef_set; + int best, best_val, save, i, sel, fs; + struct max98088_cdata *cdata; + + cdata = &max98088->dai[0]; + + if (!pdata || !cdata->eq_textcnt) + return; + + /* Find the selected configuration with nearest sample rate */ + fs = cdata->rate; + sel = cdata->eq_sel; + + best = 0; + best_val = INT_MAX; + for (i = 0; i < pdata->eq1_cfgcnt; i++) { + if (strcmp(pdata->eq1_cfg[i].name, cdata->eq_texts[sel]) == 0 && + abs(pdata->eq1_cfg[i].rate - fs) < best_val) { + best = i; + best_val = abs(pdata->eq1_cfg[i].rate - fs); + } + } + + dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", + pdata->eq1_cfg[best].name, + pdata->eq1_cfg[best].rate, fs); + + /* Disable EQ while configuring, and save current on/off state */ + save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); + snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); + + coef_set = &pdata->eq1_cfg[sel]; + + m98088_eq_band(codec, 0, 0, coef_set->band1); + m98088_eq_band(codec, 0, 1, coef_set->band2); + m98088_eq_band(codec, 0, 2, coef_set->band3); + m98088_eq_band(codec, 0, 3, coef_set->band4); + m98088_eq_band(codec, 0, 4, coef_set->band5); + + /* restore original on/off state */ + snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); +} + +static void max98088_setup_eq2(struct snd_soc_codec *codec) +{ + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_eq_cfg *coef_set; + int best, best_val, save, i, sel, fs; + struct max98088_cdata *cdata; + + cdata = &max98088->dai[1]; + + if (!pdata || !cdata->eq_textcnt) + return; + + /* Find the selected configuration with nearest sample rate */ + fs = cdata->rate; + + sel = cdata->eq_sel; + best = 0; + best_val = INT_MAX; + for (i = 0; i < pdata->eq2_cfgcnt; i++) { + if (strcmp(pdata->eq2_cfg[i].name, cdata->eq_texts[sel]) == 0 && + abs(pdata->eq2_cfg[i].rate - fs) < best_val) { + best = i; + best_val = abs(pdata->eq2_cfg[i].rate - fs); + } + } + + dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", + pdata->eq2_cfg[best].name, + pdata->eq2_cfg[best].rate, fs); + + /* Disable EQ while configuring, and save current on/off state */ + save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); + snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); + + coef_set = &pdata->eq2_cfg[sel]; + + m98088_eq_band(codec, 1, 0, coef_set->band1); + m98088_eq_band(codec, 1, 1, coef_set->band2); + m98088_eq_band(codec, 1, 2, coef_set->band3); + m98088_eq_band(codec, 1, 3, coef_set->band4); + m98088_eq_band(codec, 1, 4, coef_set->band5); + + /* restore original on/off state */ + snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, + save); +} + + +static int max98088_put_eq1_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int sel = ucontrol->value.integer.value[0]; + + cdata = &max98088->dai[0]; + + if (sel >= pdata->eq1_cfgcnt) + return -EINVAL; + + cdata->eq_sel = sel; + max98088_setup_eq1(codec); + return 0; +} + +static int max98088_put_eq2_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int sel = ucontrol->value.integer.value[0]; + + cdata = &max98088->dai[1]; + + if (sel >= pdata->eq2_cfgcnt) + return -EINVAL; + + cdata->eq_sel = sel; + max98088_setup_eq2(codec); + return 0; +} + +static int max98088_get_eq1_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + + cdata = &max98088->dai[0]; + + ucontrol->value.enumerated.item[0] = cdata->eq_sel; + return 0; +} + +static int max98088_get_eq2_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + + cdata = &max98088->dai[1]; + + ucontrol->value.enumerated.item[0] = cdata->eq_sel; + return 0; +} + +static void max98088_handle_eq1_pdata(struct max98088_priv *max98088) +{ + struct snd_soc_codec *codec = &max98088->codec; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int ret, i, j; + + struct snd_kcontrol_new eq1control = + SOC_ENUM_EXT("EQ1 Mode", + max98088->dai[0].eq_enum, + max98088_get_eq1_enum, + max98088_put_eq1_enum); + + cdata = &max98088->dai[0]; + + /* Build an array of texts for the enum API. The number + * of texts is likely fewer than the number of configurations + * due to multiple sample rates for the same text name. */ + cdata->eq_textcnt = 0; + for (i = 0; i < pdata->eq1_cfgcnt; i++) { + for (j = 0; j < cdata->eq_textcnt; j++) { + if (strcmp(pdata->eq1_cfg[i].name, + cdata->eq_texts[j]) == 0) { + break; + } + } + + if (j != cdata->eq_textcnt) + continue; + + /* ...and remember the new version. */ + cdata->eq_texts[i] = pdata->eq1_cfg[i].name; + cdata->eq_textcnt++; + + if (cdata->eq_textcnt >= EQ_CFG_MAX) { + dev_err(codec->dev, "Too many EQ config entries\n"); + cdata->eq_textcnt--; + break; + } + } + + dev_dbg(codec->dev, "Installed %d EQ1 configurations\n", + cdata->eq_textcnt); + + /* now point the soc_enum to .texts array items */ + cdata->eq_enum.texts = cdata->eq_texts; + cdata->eq_enum.max = cdata->eq_textcnt; + + BUG_ON(&max98088->codec == 0); + BUG_ON((max98088->codec).card == 0); + + ret = snd_soc_add_controls(&max98088->codec, &eq1control, 1); + if (ret != 0) + dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); +} + +static void max98088_handle_eq2_pdata(struct max98088_priv *max98088) +{ + struct snd_soc_codec *codec = &max98088->codec; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int ret, i, j; + + struct snd_kcontrol_new eq2control = + SOC_ENUM_EXT("EQ2 Mode", + max98088->dai[1].eq_enum, + max98088_get_eq2_enum, + max98088_put_eq2_enum); + + cdata = &max98088->dai[1]; + + /* Build an array of texts for the enum API. The number + * of texts is likely fewer than the number of configurations + * due to multiple sample rates for the same text name. */ + cdata->eq_textcnt = 0; + for (i = 0; i < pdata->eq2_cfgcnt; i++) { + for (j = 0; j < cdata->eq_textcnt; j++) { + if (strcmp(pdata->eq2_cfg[i].name, + cdata->eq_texts[j]) == 0) { + break; + } + } + + if (j != cdata->eq_textcnt) + continue; + + cdata->eq_texts[i] = pdata->eq2_cfg[i].name; + cdata->eq_textcnt++; + + if (cdata->eq_textcnt >= EQ_CFG_MAX) { + dev_err(codec->dev, "Too many EQ config entries\n"); + cdata->eq_textcnt--; + break; + } + } + + dev_dbg(codec->dev, "Installed %d EQ2 configurations\n", + cdata->eq_textcnt); + + /* now point the soc_enum to .texts array items */ + cdata->eq_enum.texts = cdata->eq_texts; + cdata->eq_enum.max = cdata->eq_textcnt; + + ret = snd_soc_add_controls(&max98088->codec, &eq2control, 1); + if (ret != 0) + printk(KERN_ERR "Failed to add EQ control: %d\n", ret); +} + + +static void max98088_setup_ex1(struct snd_soc_codec *codec) +{ + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + struct max98088_excursion_cfg *coef_set; + int best, best_val, i, sel, fs; + + cdata = &max98088->dai[0]; + + if (!pdata || !cdata->ex_textcnt) + return; + + /* Find the selected configuration with nearest sample rate */ + fs = cdata->rate; + + sel = cdata->ex_sel; + best = 0; + best_val = INT_MAX; + for (i = 0; i < pdata->ex1_cfgcnt; i++) { + if (strcmp(pdata->ex1_cfg[i].name, + cdata->ex_texts[sel]) == 0 && + abs(pdata->ex1_cfg[i].rate - fs) < best_val) { + best = i; + best_val = abs(pdata->ex1_cfg[i].rate - fs); + } + } + + dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", + pdata->ex1_cfg[best].name, + pdata->ex1_cfg[best].rate, fs); + + coef_set = &pdata->ex1_cfg[sel]; + + max98088_ex_resp_control(codec, M98088_REG_B6_DAI1_BIQUAD_BASE, + coef_set->resp); +} + +static int max98088_put_ex1_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int sel = ucontrol->value.integer.value[0]; + + cdata = &max98088->dai[0]; + + if (sel >= pdata->ex1_cfgcnt) + return -EINVAL; + + cdata->ex_sel = sel; + max98088_setup_ex1(codec); + return 0; +} + + +static int max98088_get_ex1_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + + cdata = &max98088->dai[0]; + ucontrol->value.enumerated.item[0] = cdata->ex_sel; + + return 0; +} + +static void max98088_handle_ex1_pdata(struct max98088_priv *max98088) +{ + struct snd_soc_codec *codec = &max98088->codec; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int ret, i, j; + + struct snd_kcontrol_new ex1control = + SOC_ENUM_EXT("EX1 Limiter Config", + max98088->dai[0].ex_enum, + max98088_get_ex1_enum, + max98088_put_ex1_enum); + + cdata = &max98088->dai[0]; + + /* Build an array of texts for the enum API. The number + * of texts is likely fewer than the number of configurations + * due to multiple sample rates for the same text name. */ + cdata->ex_textcnt = 0; + for (i = 0; i < pdata->ex1_cfgcnt; i++) { + for (j = 0; j < cdata->ex_textcnt; j++) { + if (strcmp(pdata->ex1_cfg[i].name, + cdata->ex_texts[j]) == 0) { + break; + } + } + + if (j != cdata->ex_textcnt) + continue; + + /* ...and remember the new version. */ + cdata->ex_texts[i] = pdata->ex1_cfg[i].name; + cdata->ex_textcnt++; + + if (cdata->ex_textcnt >= EX_CFG_MAX) { + dev_err(codec->dev, "Too many limiter configs\n"); + cdata->ex_textcnt--; + break; + } + } + + dev_dbg(codec->dev, "Installed %d EX1 configurations\n", + cdata->ex_textcnt); + + /* now point the soc_enum to .texts array */ + cdata->ex_enum.texts = cdata->ex_texts; + cdata->ex_enum.max = cdata->ex_textcnt; + ret = snd_soc_add_controls(&max98088->codec, &ex1control, 1); + if (ret != 0) + dev_err(codec->dev, "Failed to add limiter control\n"); +} + + +static void max98088_setup_ex2(struct snd_soc_codec *codec) +{ + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + struct max98088_excursion_cfg *coef_set; + int best, best_val, i, sel, fs; + + cdata = &max98088->dai[1]; + + if (!pdata || !cdata->ex_textcnt) + return; + + /* Find the selected configuration with nearest sample rate */ + fs = cdata->rate; + + sel = cdata->ex_sel; + best = 0; + best_val = INT_MAX; + for (i = 0; i < pdata->ex2_cfgcnt; i++) { + if (strcmp(pdata->ex2_cfg[i].name, + cdata->ex_texts[sel]) == 0 && + abs(pdata->ex2_cfg[i].rate - fs) < best_val) { + best = i; + best_val = abs(pdata->ex2_cfg[i].rate - fs); + } + } + + dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", + pdata->ex2_cfg[best].name, + pdata->ex2_cfg[best].rate, fs); + + coef_set = &pdata->ex2_cfg[sel]; + + max98088_ex_resp_control(codec, M98088_REG_C0_DAI2_BIQUAD_BASE, + coef_set->resp); +} + +static int max98088_put_ex2_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int sel = ucontrol->value.integer.value[0]; + + cdata = &max98088->dai[1]; + + if (sel >= pdata->ex2_cfgcnt) + return -EINVAL; + + cdata->ex_sel = sel; + max98088_setup_ex2(codec); + return 0; +} + +static int max98088_get_ex2_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98088_priv *max98088 = codec->private_data; + struct max98088_cdata *cdata; + + cdata = &max98088->dai[1]; + ucontrol->value.enumerated.item[0] = cdata->ex_sel; + + return 0; +} + +static void max98088_handle_ex2_pdata(struct max98088_priv *max98088) +{ + struct snd_soc_codec *codec = &max98088->codec; + struct max98088_pdata *pdata = max98088->pdata; + struct max98088_cdata *cdata; + int ret, i, j; + + struct snd_kcontrol_new ex2control = + SOC_ENUM_EXT("EX2 Limiter Config", + max98088->dai[1].ex_enum, + max98088_get_ex2_enum, + max98088_put_ex2_enum); + + cdata = &max98088->dai[1]; + + /* Build an array of texts for the enum API. The number + * of texts is likely fewer than the number of configurations + * due to multiple sample rates for the same text name. */ + cdata->ex_textcnt = 0; + for (i = 0; i < pdata->ex2_cfgcnt; i++) { + for (j = 0; j < cdata->ex_textcnt; j++) { + if (strcmp(pdata->ex2_cfg[i].name, + cdata->ex_texts[j]) == 0) { + break; + } + } + + if (j != cdata->ex_textcnt) + continue; + + /* ...and remember the new version. */ + cdata->ex_texts[i] = pdata->ex2_cfg[i].name; + cdata->ex_textcnt++; + + if (cdata->ex_textcnt >= EX_CFG_MAX) { + dev_err(codec->dev, "Too many limiter configs\n"); + cdata->ex_textcnt--; + break; + } + } + + dev_dbg(codec->dev, "Installed %d EX2 configurations\n", + cdata->ex_textcnt); + + /* now point the soc_enum to .texts array items */ + cdata->ex_enum.texts = cdata->ex_texts; + cdata->ex_enum.max = cdata->ex_textcnt; + + ret = snd_soc_add_controls(&max98088->codec, &ex2control, 1); + if (ret != 0) + dev_err(codec->dev, "Failed to add limiter control\n"); +} + +static void max98088_handle_pdata(struct max98088_priv *max98088) +{ + struct snd_soc_codec *codec = &max98088->codec; + struct max98088_pdata *pdata = max98088->pdata; + u8 regval; + + if (!pdata) + return; + + /* Configure digital mic / external mic */ + /* Digital mic needs REG_15 OSR1=1 */ + regval = ((0<<6) | /* digital mic clock freq = PCLK/8 */ + (0<<5) | /* DIGMICL enable */ + (0<<4) | /* DIGMICR enable */ + (0<<0)); /* external mic enable */ + + if (pdata->digmic_left_enable) + regval |= (1<<5); /* digital left mic enabled */ + + if (pdata->digmic_right_enable) + regval |= (1<<4); /* digital right mic enabled */ + + max98088->digmic_mode = (regval ? 1 : 0); + + if (pdata->extmic_mode < 3) + regval |= (pdata->extmic_mode << 0); /* external mic enabled */ + + max98088_write(codec, M98088_REG_48_CFG_MIC, regval); + + /* configure external mic to mic1 bypass, mic1 to mic2 bypass */ + regval = 0; + + if (pdata->ina_to_mic1_bypass) + regval |= (1<<7); + + if (pdata->mic1_to_mic2_bypass) + regval |= (1<<4); + + max98088_write(codec, M98088_REG_4A_CFG_BYPASS, regval); + + /* configure receiver output */ + regval = ((pdata->receiver_mode) ? (1<<7) : 0); + snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL, + (1<<7), regval); + + /* configure equalizers */ + if (pdata->eq1_cfgcnt) + max98088_handle_eq1_pdata(max98088); + + if (pdata->eq2_cfgcnt) + max98088_handle_eq2_pdata(max98088); + + /* configure excursion limiters */ + if (pdata->ex1_cfgcnt) + max98088_handle_ex1_pdata(max98088); + + if (pdata->ex2_cfgcnt) + max98088_handle_ex2_pdata(max98088); +} + +static int max98088_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int max98088_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + int i; + u8 *cache = codec->reg_cache; + + /* toggle reset the shutdown bit of the codec hardware */ + max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); + + /* Sync reg_cache with the hardware */ + for (i = 0; i < M98088_REG_CNT; i++) { + if (i == M98088_REG_51_PWR_SYS) + continue; + + if (!max98088_access[i].writable) + continue; + + max98088_hw_write(codec, i, cache[i]); + } + + /* now enter into the resume mode bias level */ + max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + return 0; +} + +/* + * Make sure that a max98088 is attached to the I2C bus. + */ +static int max98088_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + struct max98088_priv *max98088; + int ret = 0; + + dev_printk(KERN_INFO, &pdev->dev, "MAX98088 Audio CODEC\n"); + + if (!max98088_codec) { + dev_err(&pdev->dev, "Codec device is not registered\n"); + return -EINVAL; + } + + socdev->card->codec = max98088_codec; + codec = max98088_codec; + max98088 = codec->private_data; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(&pdev->dev, "failed to create pcms: %d\n", ret); + goto pcm_err; + } + + snd_soc_add_controls(codec, max98088_snd_controls, + ARRAY_SIZE(max98088_snd_controls)); + + /* install additional amixer controls: EQ and excursion limiter */ + if (max98088->pdata) + max98088_handle_pdata(max98088); + else + dev_err(&pdev->dev, "No platform data\n"); + + max98088_add_widgets(codec); + + ret = snd_soc_init_card(socdev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register card\n"); + goto card_err; + } + + return 0; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + +pcm_err: + return ret; +} + +static int max98088_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + if (codec->control_data) + max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + + return 0; +} + +/* expose to machine driver */ +struct snd_soc_codec_device soc_codec_dev_max98088 = { + .probe = max98088_probe, + .remove = max98088_remove, + .suspend = max98088_suspend, + .resume = max98088_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_max98088); + + +static int max98088_register(struct max98088_priv *max98088, + enum snd_soc_control_type control) + +{ + int ret, i, version; + struct snd_soc_codec *codec = &max98088->codec; + struct max98088_cdata *cdata; + + if (max98088_codec) { + dev_err(codec->dev, "Another MAX98088 is registered\n"); + ret = -EINVAL; + goto err; + } + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + codec->name = "MAX98088"; + codec->owner = THIS_MODULE; + codec->read = max98088_read; + codec->write = max98088_write; + + /* setup DAPM event bias level and handler function */ + codec->bias_level = SND_SOC_BIAS_STANDBY; + codec->set_bias_level = max98088_set_bias_level; + + codec->dai = max98088_dai; + codec->num_dai = ARRAY_SIZE(max98088_dai); + codec->private_data = max98088; + + codec->reg_cache_size = M98088_REG_CNT; + codec->reg_cache = &max98088->reg_cache; + codec->volatile_register = max98088_volatile_register; + + memcpy(codec->reg_cache, max98088_reg, sizeof(max98088_reg)); + + version = max98088_read(codec, M98088_REG_FF_REV_ID); + dev_dbg(codec->dev, "MAX98088 revision 0x%02X\n", version); + + /* initalize private data */ + + max98088->sysclk = (unsigned)-1; + + cdata = &max98088->dai[0]; + cdata->rate = (unsigned)-1; + cdata->fmt = (unsigned)-1; + cdata->eq_textcnt = 0; + cdata->eq_sel = 0; + cdata->ex_textcnt = 0; + cdata->ex_sel = 0; + + cdata = &max98088->dai[1]; + cdata->rate = (unsigned)-1; + cdata->fmt = (unsigned)-1; + cdata->eq_textcnt = 0; + cdata->eq_sel = 0; + cdata->ex_textcnt = 0; + cdata->ex_sel = 0; + + max98088_write(codec, M98088_REG_14_DAI1_FORMAT, M98088_DAI_DLY); + max98088_write(codec, M98088_REG_1C_DAI2_FORMAT, M98088_DAI_DLY); + + max98088->power_state = 0; /* INA INB power enable state */ + max98088->ex_mode = 0; /* excursion limiter mode */ + max98088->digmic_mode = 0; /* 0=normal, 1=digital mic used */ + + /* disable device via dapm interface */ + max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); + + /* initialize registers cache to hardware default */ + max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + max98088_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00); + + max98088_write(codec, M98088_REG_22_MIX_DAC, + M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL| + M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR); + + max98088_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0); + max98088_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F); + + /* power on device */ + max98088_codec = codec; + for (i = 0; i < codec->num_dai; i++) + max98088_dai[i].dev = codec->dev; + + ret = snd_soc_register_codec(codec); + if (ret != 0) { + dev_err(codec->dev, "Failed to register codec: %d\n", ret); + goto err; + } + + ret = snd_soc_register_dais(&max98088_dai[0], codec->num_dai); + if (ret != 0) { + dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); + goto err_codec; + } + + return ret; + +err_codec: + snd_soc_unregister_codec(codec); +err: + kfree(max98088); + + return ret; +} + +static void max98088_unregister(struct max98088_priv *max98088) +{ + struct snd_soc_codec *codec = &max98088->codec; + snd_soc_unregister_dais(max98088_dai, codec->num_dai); + snd_soc_unregister_codec(codec); + kfree(max98088); + max98088_codec = NULL; +} + +static int max98088_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct snd_soc_codec *codec; + struct max98088_priv *max98088; + + max98088 = kzalloc(sizeof(struct max98088_priv), GFP_KERNEL); + if (max98088 == NULL) + return -ENOMEM; + + /* codec structure is inside the private data */ + codec = &(max98088->codec); + + codec->private_data = max98088; + + codec->hw_write = (hw_write_t) i2c_master_send; + i2c_set_clientdata(i2c, max98088); + codec->control_data = i2c; + + max98088->pdata = i2c->dev.platform_data; + + codec->dev = &i2c->dev; + + return max98088_register(max98088, SND_SOC_I2C); +} + +static int max98088_i2c_remove(struct i2c_client *client) +{ + struct max98088_priv *max98088 = i2c_get_clientdata(client); + max98088_unregister(max98088); + return 0; +} + +static const struct i2c_device_id max98088_i2c_id[] = { + { "max98088", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, max98088_i2c_id); + + +static struct i2c_driver max98088_i2c_driver = { + .driver = { + .name = "MAX98088 I2C Codec", + .owner = THIS_MODULE, + }, + .probe = max98088_i2c_probe, + .remove = __devexit_p(max98088_i2c_remove), + .id_table = max98088_i2c_id, +}; + +static int __init max98088_init(void) +{ + int ret; + + ret = i2c_add_driver(&max98088_i2c_driver); + if (ret) + pr_err("Failed to register max98088 I2C driver: %d\n", ret); + + return ret; +} + +static void __exit max98088_exit(void) +{ + i2c_del_driver(&max98088_i2c_driver); +} + +module_init(max98088_init); +module_exit(max98088_exit); + +MODULE_DESCRIPTION("ALSA SoC MAX98088 driver"); +MODULE_AUTHOR("Peter Hsiang <peter.hsiang(a)maxim-ic.com>"); +MODULE_AUTHOR("Jesse Marroquin <jesse.marroquin(a)maxim-ic.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/max98088.h b/sound/soc/codecs/max98088.h new file mode 100644 index 0000000..f7ef4c2 --- /dev/null +++ b/sound/soc/codecs/max98088.h @@ -0,0 +1,161 @@ +/* + * max98088.h -- MAX98088 ALSA SoC Audio driver + * + * Copyright 2010 Maxim Integrated Products + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MAX98088_H +#define _MAX98088_H + +/* + * MAX98088 Registers Definition + */ +#define M98088_REG_00_IRQ_STATUS 0x00 +#define M98088_REG_01_MIC_STATUS 0x01 +#define M98088_REG_02_JACK_STAUS 0x02 +#define M98088_REG_03_BATTERY_VOLTAGE 0x03 +#define M98088_REG_0F_IRQ_ENABLE 0x0F +#define M98088_REG_10_SYS_CLK 0x10 +#define M98088_REG_11_DAI1_CLKMODE 0x11 +#define M98088_REG_12_DAI1_CLKCFG_HI 0x12 +#define M98088_REG_13_DAI1_CLKCFG_LO 0x13 +#define M98088_REG_14_DAI1_FORMAT 0x14 +#define M98088_REG_15_DAI1_CLOCK 0x15 +#define M98088_REG_16_DAI1_IOCFG 0x16 +#define M98088_REG_17_DAI1_TDM 0x17 +#define M98088_REG_18_DAI1_FILTERS 0x18 +#define M98088_REG_19_DAI2_CLKMODE 0x19 +#define M98088_REG_1A_DAI2_CLKCFG_HI 0x1A +#define M98088_REG_1B_DAI2_CLKCFG_LO 0x1B +#define M98088_REG_1C_DAI2_FORMAT 0x1C +#define M98088_REG_1D_DAI2_CLOCK 0x1D +#define M98088_REG_1E_DAI2_IOCFG 0x1E +#define M98088_REG_1F_DAI2_TDM 0x1F +#define M98088_REG_20_DAI2_FILTERS 0x20 +#define M98088_REG_21_SRC 0x21 +#define M98088_REG_22_MIX_DAC 0x22 +#define M98088_REG_23_MIX_ADC_LEFT 0x23 +#define M98088_REG_24_MIX_ADC_RIGHT 0x24 +#define M98088_REG_25_MIX_HP_LEFT 0x25 +#define M98088_REG_26_MIX_HP_RIGHT 0x26 +#define M98088_REG_27_MIX_HP_CNTL 0x27 +#define M98088_REG_28_MIX_REC_LEFT 0x28 +#define M98088_REG_29_MIX_REC_RIGHT 0x29 +#define M98088_REG_2A_MIC_REC_CNTL 0x2A +#define M98088_REG_2B_MIX_SPK_LEFT 0x2B +#define M98088_REG_2C_MIX_SPK_RIGHT 0x2C +#define M98088_REG_2D_MIX_SPK_CNTL 0x2D +#define M98088_REG_2E_LVL_SIDETONE 0x2E +#define M98088_REG_2F_LVL_DAI1_PLAY 0x2F +#define M98088_REG_30_LVL_DAI1_PLAY_EQ 0x30 +#define M98088_REG_31_LVL_DAI2_PLAY 0x31 +#define M98088_REG_32_LVL_DAI2_PLAY_EQ 0x32 +#define M98088_REG_33_LVL_ADC_L 0x33 +#define M98088_REG_34_LVL_ADC_R 0x34 +#define M98088_REG_35_LVL_MIC1 0x35 +#define M98088_REG_36_LVL_MIC2 0x36 +#define M98088_REG_37_LVL_INA 0x37 +#define M98088_REG_38_LVL_INB 0x38 +#define M98088_REG_39_LVL_HP_L 0x39 +#define M98088_REG_3A_LVL_HP_R 0x3A +#define M98088_REG_3B_LVL_REC_L 0x3B +#define M98088_REG_3C_LVL_REC_R 0x3C +#define M98088_REG_3D_LVL_SPK_L 0x3D +#define M98088_REG_3E_LVL_SPK_R 0x3E +#define M98088_REG_3F_MICAGC_CFG 0x3F +#define M98088_REG_40_MICAGC_THRESH 0x40 +#define M98088_REG_41_SPKDHP 0x41 +#define M98088_REG_42_SPKDHP_THRESH 0x42 +#define M98088_REG_43_SPKALC_COMP 0x43 +#define M98088_REG_44_PWRLMT_CFG 0x44 +#define M98088_REG_45_PWRLMT_TIME 0x45 +#define M98088_REG_46_THDLMT_CFG 0x46 +#define M98088_REG_47_CFG_AUDIO_IN 0x47 +#define M98088_REG_48_CFG_MIC 0x48 +#define M98088_REG_49_CFG_LEVEL 0x49 +#define M98088_REG_4A_CFG_BYPASS 0x4A +#define M98088_REG_4B_CFG_JACKDET 0x4B +#define M98088_REG_4C_PWR_EN_IN 0x4C +#define M98088_REG_4D_PWR_EN_OUT 0x4D +#define M98088_REG_4E_BIAS_CNTL 0x4E +#define M98088_REG_4F_DAC_BIAS1 0x4F +#define M98088_REG_50_DAC_BIAS2 0x50 +#define M98088_REG_51_PWR_SYS 0x51 +#define M98088_REG_52_DAI1_EQ_BASE 0x52 +#define M98088_REG_84_DAI2_EQ_BASE 0x84 +#define M98088_REG_B6_DAI1_BIQUAD_BASE 0xB6 +#define M98088_REG_C0_DAI2_BIQUAD_BASE 0xC0 +#define M98088_REG_FF_REV_ID 0xFF + +#define M98088_REG_CNT (0xFF+1) + +/* MAX98088 Registers Bit Fields */ + +/* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */ + #define M98088_DAI_MAS (1<<7) + #define M98088_DAI_WCI (1<<6) + #define M98088_DAI_BCI (1<<5) + #define M98088_DAI_DLY (1<<4) + #define M98088_DAI_TDM (1<<2) + #define M98088_DAI_FSW (1<<1) + #define M98088_DAI_WS (1<<0) + +/* M98088_REG_22_MIX_DAC */ + #define M98088_DAI1L_TO_DACL (1<<7) + #define M98088_DAI1R_TO_DACL (1<<6) + #define M98088_DAI2L_TO_DACL (1<<5) + #define M98088_DAI2R_TO_DACL (1<<4) + #define M98088_DAI1L_TO_DACR (1<<3) + #define M98088_DAI1R_TO_DACR (1<<2) + #define M98088_DAI2L_TO_DACR (1<<1) + #define M98088_DAI2R_TO_DACR (1<<0) + +/* M98088_REG_3A_LVL_HEADPHONE_R */ + #define M98088_HP_MUTE (1<<7) + +/* M98088_REG_3C_LVL_RECEIVER_R */ + #define M98088_REC_MUTE (1<<7) + +/* M98088_REG_3E_LVL_SPEAKER_R */ + #define M98088_SP_MUTE (1<<7) + +/* M98088_REG_49_CFG_LEVEL */ + #define M98088_VSEN (1<<6) + #define M98088_ZDEN (1<<5) + #define M98088_EQ2EN (1<<1) + #define M98088_EQ1EN (1<<0) + +/* M98088_REG_4D_PWR_EN_OUT */ + #define M98088_HPLEN (1<<7) + #define M98088_HPREN (1<<6) + #define M98088_HPEN ((1<<7)|(1<<6)) + #define M98088_SPLEN (1<<5) + #define M98088_SPREN (1<<4) + #define M98088_RECEN (1<<3) + #define M98088_DALEN (1<<1) + #define M98088_DAREN (1<<0) + +/* M98088_REG_51_PWR_SYS */ + #define M98088_SHDNRUN (1<<7) + #define M98088_PERFMODE (1<<3) + #define M98088_HPPLYBACK (1<<2) + #define M98088_PWRSV8K (1<<1) + #define M98088_PWRSV (1<<0) + +#define M98088_COEFS_PER_BAND 5 + +#define M98088_BYTE1(w) ((w >> 8) & 0xff) +#define M98088_BYTE0(w) (w & 0xff) + +struct max98088_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai max98088_dai[]; +extern struct snd_soc_codec_device soc_codec_dev_max98088; + +#endif -- 1.6.3.3

2 5

[alsa-devel] PROBLEM: snd_intel_hda audio regression in 2.6.36-rc5
by Aki Parviainen 22 Sep '10

22 Sep '10

I've noticed an audio related problem in 2.6.36-rc5: when using 2.6.36-rc5 kernel I don't get normal two channel PCM audio at all on my machine, however multichannel audio works just fine. I'm using snd_hda_intel and I've configured ALSA to send all audio to spdif output. With earlier kernel versions this kind of setup works just fine but with 2.6.36-rc5 only audio that works is digital preencoded audio (5.1 dolby digital from dvd:s / mkv:s) works. There's no errors or anything but nothing comes to my amplifier. I've also tested 2.6.36-rc4 and it has the same problem, in the past I've never had any audio problems with mainline kernels. Booting with earlier kernel solves the problem immediately. I'm using the following .asoundrc to forward all audio to spdif: pcm.!default { type plug slave { pcm "iec958" rate 48000 format S16_LE } } Kernel: Self compiled 2.6.36-rc5 Kernel version: Linux version 2.6.36-rc5 (app@ht) (gcc version 4.4.5 20100913 (prerelease) (Debian 4.4.4-15) ) #1 SMP PREEMPT Tue Sep 21 18:10:22 EEST 2010 Kernel .config at end of mail Most recent kernel version which did not have the bug: 2.6.35.5 Environment: Debian unstable x86-64, alsa-version 1.0.23 Software: Linux ht 2.6.36-rc5 #1 SMP PREEMPT Tue Sep 21 18:10:22 EEST 2010 x86_64 GNU/Linux Gnu C 4.4.5 Gnu make 3.81 binutils 2.20.1 util-linux scripts/ver_linux: 23: fdformat: not found mount support module-init-tools found Linux C Library 2.11.2 Dynamic linker (ldd) 2.11.2 Procps 3.2.8 Kbd 1.15.2 Sh-utils 8.5 Modules Loaded isofs udf i915 drm_kms_helper drm i2c_algo_bit video output acpi_cpufreq mperf sco bnep cpufreq_userspace cpufreq_stats rfcomm l2cap kvm_intel kvm fuse nls_iso8859_1 cifs fscache ipv6 hwmon_vid sbs sbshc coretemp ir_lirc_codec lirc_dev ir_sony_decoder ir_jvc_decoder ir_rc6_decoder ir_rc5_decoder ir_nec_decoder mantis mantis_core ir_core tda665x mb86a16 tda10023 zl10353 stv0299 loop snd_hda_codec_analog tda10021 snd_hda_intel snd_hda_codec snd_hwdep snd_pcm_oss snd_mixer_oss snd_pcm snd_seq_dummy snd_seq_oss snd_seq_midi snd_rawmidi snd_seq_midi_event budget_av saa7146_vv snd_seq videodev v4l1_compat v4l2_compat_ioctl32 snd_timer videobuf_dma_sg snd_seq_device videobuf_core budget_core dvb_core saa7146 ttpci_eeprom snd btusb bluetooth rfkill psmouse asus_atk0110 serio_raw intel_agp soundcore snd_page_alloc rtc_cmos rtc_core rtc_lib i2c_i801 i2c_core evdev processor button sg sr_mod cdrom sd_mod ata_generic firewire_ohci pata_acpi usbhid crc_t10dif firewire_core skge ahci libahci uhci_hcd pata_jmicron thermal ehci_hcdLinux ht 2.6.36-rc5 #1 SMP PREEMPT Tue Sep 21 18:10:22 EEST 2010 x86_64 GNU/Linux Gnu C 4.4.5 Gnu make 3.81 binutils 2.20.1 util-linux scripts/ver_linux: 23: fdformat: not found mount support module-init-tools found Linux C Library 2.11.2 Dynamic linker (ldd) 2.11.2 Procps 3.2.8 Kbd 1.15.2 Sh-utils 8.5 Modules Loaded isofs udf i915 drm_kms_helper drm i2c_algo_bit video output acpi_cpufreq mperf sco bnep cpufreq_userspace cpufreq_stats rfcomm l2cap kvm_intel kvm fuse nls_iso8859_1 cifs fscache ipv6 hwmon_vid sbs sbshc coretemp ir_lirc_codec lirc_dev ir_sony_decoder ir_jvc_decoder ir_rc6_decoder ir_rc5_decoder ir_nec_decoder mantis mantis_core ir_core tda665x mb86a16 tda10023 zl10353 stv0299 loop snd_hda_codec_analog tda10021 snd_hda_intel snd_hda_codec snd_hwdep snd_pcm_oss snd_mixer_oss snd_pcm snd_seq_dummy snd_seq_oss snd_seq_midi snd_rawmidi snd_seq_midi_event budget_av saa7146_vv snd_seq videodev v4l1_compat v4l2_compat_ioctl32 snd_timer videobuf_dma_sg snd_seq_device videobuf_core budget_core dvb_core saa7146 ttpci_eeprom snd btusb bluetooth rfkill psmouse asus_atk0110 serio_raw intel_agp soundcore snd_page_alloc rtc_cmos rtc_core rtc_lib i2c_i801 i2c_core evdev processor button sg sr_mod cdrom sd_mod ata_generic firewire_ohci pata_acpi usbhid crc_t10dif firewire_core skge ahci libahci uhci_hcd pata_jmicron thermal ehci_hcd Processor information: processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz stepping : 11 cpu MHz : 2394.000 cache size : 4096 KB Module information: isofs 28121 0 - Live 0xffffffffa0585000 udf 67899 1 - Live 0xffffffffa056c000 i915 259433 2 - Live 0xffffffffa051a000 drm_kms_helper 28230 1 i915, Live 0xffffffffa050b000 drm 181570 3 i915,drm_kms_helper, Live 0xffffffffa04c9000 i2c_algo_bit 4634 1 i915, Live 0xffffffffa04c2000 video 12424 1 i915, Live 0xffffffffa04b7000 output 2119 1 video, Live 0xffffffffa04b1000 acpi_cpufreq 5527 1 - Live 0xffffffffa04a9000 mperf 1347 1 acpi_cpufreq, Live 0xffffffffa04a3000 sco 7675 2 - Live 0xffffffffa049b000 bnep 10100 2 - Live 0xffffffffa048c000 cpufreq_userspace 2080 0 - Live 0xffffffffa0495000 cpufreq_stats 3620 0 - Live 0xffffffffa0486000 rfcomm 30076 8 - Live 0xffffffffa0476000 l2cap 31078 16 bnep,rfcomm, Live 0xffffffffa0458000 kvm_intel 42482 0 - Live 0xffffffffa0445000 kvm 174507 1 kvm_intel, Live 0xffffffffa0409000 fuse 59593 1 - Live 0xffffffffa03f0000 nls_iso8859_1 4489 2 - Live 0xffffffffa03e9000 cifs 229425 3 - Live 0xffffffffa03a4000 fscache 41602 1 cifs, Live 0xffffffffa038f000 ipv6 254704 22 - Live 0xffffffffa033b000 hwmon_vid 2090 0 - Live 0xffffffffa0329000 sbs 6278 0 - Live 0xffffffffa0322000 sbshc 4163 1 sbs, Live 0xffffffffa031b000 coretemp 5052 0 - Live 0xffffffffa0314000 ir_lirc_codec 3440 0 - Live 0xffffffffa030e000 lirc_dev 9041 1 ir_lirc_codec, Live 0xffffffffa0305000 ir_sony_decoder 2069 0 - Live 0xffffffffa02ff000 ir_jvc_decoder 2210 0 - Live 0xffffffffa02f9000 ir_rc6_decoder 2578 0 - Live 0xffffffffa02f3000 ir_rc5_decoder 2066 0 - Live 0xffffffffa02ed000 ir_nec_decoder 2386 0 - Live 0xffffffffa02e7000 mantis 16265 0 - Live 0xffffffffa02dd000 mantis_core 29516 1 mantis, Live 0xffffffffa02ce000 ir_core 16002 7 ir_lirc_codec,ir_sony_decoder,ir_jvc_decoder,ir_rc6_decoder,ir_rc5_decoder,ir_nec_decoder,mantis_core, Live 0xffffffffa02c3000 tda665x 2990 1 mantis, Live 0xffffffffa02bd000 mb86a16 17977 1 mantis, Live 0xffffffffa02b3000 tda10023 5852 1 mantis, Live 0xffffffffa02ac000 zl10353 6529 1 mantis, Live 0xffffffffa02a5000 stv0299 8898 1 mantis, Live 0xffffffffa029d000 loop 13254 0 - Live 0xffffffffa0293000 snd_hda_codec_analog 73369 1 - Live 0xffffffffa0279000 tda10021 5392 2 mantis, Live 0xffffffffa0272000 snd_hda_intel 22412 3 - Live 0xffffffffa0265000 snd_hda_codec 87688 2 snd_hda_codec_analog,snd_hda_intel, Live 0xffffffffa0241000 snd_hwdep 5594 1 snd_hda_codec, Live 0xffffffffa023a000 snd_pcm_oss 30600 0 - Live 0xffffffffa022b000 snd_mixer_oss 12612 1 snd_pcm_oss, Live 0xffffffffa0221000 snd_pcm 67021 4 snd_hda_intel,snd_hda_codec,snd_pcm_oss, Live 0xffffffffa0204000 snd_seq_dummy 1494 0 - Live 0xffffffffa01fe000 snd_seq_oss 24051 0 - Live 0xffffffffa01f1000 snd_seq_midi 4684 0 - Live 0xffffffffa018d000 snd_rawmidi 19154 1 snd_seq_midi, Live 0xffffffffa01ea000 snd_seq_midi_event 6227 2 snd_seq_oss,snd_seq_midi, Live 0xffffffffa016c000 budget_av 22791 8 - Live 0xffffffffa01e2000 saa7146_vv 41408 1 budget_av, Live 0xffffffffa01d5000 snd_seq 45334 6 snd_seq_dummy,snd_seq_oss,snd_seq_midi,snd_seq_midi_event, Live 0xffffffffa01c7000 videodev 65532 1 saa7146_vv, Live 0xffffffffa0141000 v4l1_compat 11823 1 videodev, Live 0xffffffffa013c000 v4l2_compat_ioctl32 8814 1 videodev, Live 0xffffffffa012a000 snd_timer 18556 2 snd_pcm,snd_seq, Live 0xffffffffa011e000 videobuf_dma_sg 8765 1 saa7146_vv, Live 0xffffffffa010f000 snd_seq_device 5888 5 snd_seq_dummy,snd_seq_oss,snd_seq_midi,snd_rawmidi,snd_seq, Live 0xffffffffa00ec000 videobuf_core 17336 2 saa7146_vv,videobuf_dma_sg, Live 0xffffffffa00e3000 budget_core 8310 1 budget_av, Live 0xffffffffa00c9000 dvb_core 88181 4 mantis_core,stv0299,budget_av,budget_core, Live 0xffffffffa01a7000 saa7146 14648 3 budget_av,saa7146_vv,budget_core, Live 0xffffffffa00b6000 ttpci_eeprom 1677 1 budget_core, Live 0xffffffffa009e000 snd 58773 17 snd_hda_codec_analog,snd_hda_intel,snd_hda_codec,snd_hwdep,snd_pcm_oss,snd_mixer_oss,snd_pcm,snd_seq_oss,snd_rawmidi,snd_seq,snd_timer,snd_seq_device, Live 0xffffffffa008a000 btusb 10640 2 - Live 0xffffffffa0048000 bluetooth 51576 9 sco,bnep,rfcomm,l2cap,btusb, Live 0xffffffffa005b000 rfkill 17059 2 bluetooth, Live 0xffffffffa002e000 psmouse 35356 0 - Live 0xffffffffa0018000 asus_atk0110 7194 0 - Live 0xffffffffa0007000 serio_raw 4126 0 - Live 0xffffffffa0000000 intel_agp 27303 2 i915, Live 0xffffffffa0199000 soundcore 6491 1 snd, Live 0xffffffffa0191000 snd_page_alloc 7396 2 snd_hda_intel,snd_pcm, Live 0xffffffffa0189000 rtc_cmos 8551 0 - Live 0xffffffffa0180000 rtc_core 14135 1 rtc_cmos, Live 0xffffffffa0175000 rtc_lib 2502 1 rtc_core, Live 0xffffffffa016f000 i2c_i801 7515 0 - Live 0xffffffffa0168000 i2c_core 22319 17 i915,drm_kms_helper,drm,i2c_algo_bit,mantis,mantis_core,tda665x,mb86a16,tda10023,zl10353,stv0299,tda10021,budget_av,videodev,budget_core,ttpci_eeprom,i2c_i801, Live 0xffffffffa015a000 evdev 7593 12 - Live 0xffffffffa0152000 processor 29022 1 acpi_cpufreq, Live 0xffffffffa0132000 button 5630 1 i915, Live 0xffffffffa011a000 sg 22825 0 - Live 0xffffffffa0107000 sr_mod 12173 1 - Live 0xffffffffa00fe000 cdrom 31777 1 sr_mod, Live 0xffffffffa00ef000 sd_mod 26271 6 - Live 0xffffffffa00cd000 ata_generic 3435 0 - Live 0xffffffffa00e9000 firewire_ohci 22781 0 - Live 0xffffffffa00c1000 pata_acpi 3203 0 - Live 0xffffffffa00bb000 usbhid 23926 0 - Live 0xffffffffa00a1000 crc_t10dif 1443 1 sd_mod, Live 0xffffffffa009b000 firewire_core 47389 1 firewire_ohci, Live 0xffffffffa0075000 skge 33605 0 - Live 0xffffffffa006a000 ahci 19893 0 - Live 0xffffffffa0083000 libahci 19831 5 ahci, Live 0xffffffffa0041000 uhci_hcd 18683 0 - Live 0xffffffffa004d000 pata_jmicron 2523 1 - Live 0xffffffffa0058000 thermal 8345 0 - Live 0xffffffffa0022000 ehci_hcd 30995 0 - Live 0xffffffffa000e000 Loaded driver and hardware information: 0000-0cf7 : PCI Bus 0000:00 0000-001f : dma1 0020-0021 : pic1 0040-0043 : timer0 0050-0053 : timer1 0060-0060 : keyboard 0064-0064 : keyboard 0070-0071 : rtc0 0080-008f : dma page reg 00a0-00a1 : pic2 00c0-00df : dma2 00f0-00ff : fpu 0290-0297 : pnp 00:07 03c0-03df : vesafb 03f8-03ff : serial 0400-041f : 0000:00:1f.3 0480-04bf : 0000:00:1f.0 0480-04bf : pnp 00:08 04d0-04d1 : pnp 00:08 0800-087f : 0000:00:1f.0 0800-087f : pnp 00:08 0800-0803 : ACPI PM1a_EVT_BLK 0804-0805 : ACPI PM1a_CNT_BLK 0808-080b : ACPI PM_TMR 0810-0815 : ACPI CPU throttle 0828-082f : ACPI GPE0_BLK 0cf8-0cff : PCI conf1 0d00-ffff : PCI Bus 0000:00 1000-1fff : PCI Bus 0000:02 b000-bfff : PCI Bus 0000:01 b400-b40f : 0000:01:00.1 b400-b40f : pata_jmicron b480-b483 : 0000:01:00.1 b480-b483 : pata_jmicron b800-b807 : 0000:01:00.1 b800-b807 : pata_jmicron b880-b883 : 0000:01:00.1 b880-b883 : pata_jmicron bc00-bc07 : 0000:01:00.1 bc00-bc07 : pata_jmicron c000-cfff : PCI Bus 0000:03 c000-c0ff : 0000:03:04.0 c000-c0ff : skge c400-c47f : 0000:03:03.0 c480-c4bf : 0000:03:01.0 c800-c80f : 0000:03:01.0 c880-c88f : 0000:03:01.0 cc00-cc1f : 0000:03:01.0 d480-d49f : 0000:00:1d.0 d480-d49f : uhci_hcd d800-d81f : 0000:00:1d.1 d800-d81f : uhci_hcd d880-d89f : 0000:00:1d.2 d880-d89f : uhci_hcd dc00-dc1f : 0000:00:1a.0 dc00-dc1f : uhci_hcd e000-e01f : 0000:00:1a.1 e000-e01f : uhci_hcd e080-e09f : 0000:00:1f.2 e080-e09f : ahci e400-e403 : 0000:00:1f.2 e400-e403 : ahci e480-e487 : 0000:00:1f.2 e480-e487 : ahci e800-e803 : 0000:00:1f.2 e800-e803 : ahci e880-e887 : 0000:00:1f.2 e880-e887 : ahci ec00-ec07 : 0000:00:02.0 00000000-0000ffff : reserved 00010000-0009ebff : System RAM 0009ec00-0009ffff : reserved 000a0000-000bffff : PCI Bus 0000:00 000c0000-000cffff : pnp 00:0c 000d0000-000dffff : PCI Bus 0000:00 000e4000-000fffff : reserved 00100000-7ef8ffff : System RAM 01000000-01357468 : Kernel code 01357469-01530a6f : Kernel data 015ab000-0160f51f : Kernel bss 7ef90000-7ef9dfff : ACPI Tables 7ef9e000-7efdffff : ACPI Non-volatile Storage 7efe0000-7effffff : reserved 7f000000-ffffffff : PCI Bus 0000:00 7f000000-7f3fffff : PCI Bus 0000:02 7f400000-7f5fffff : PCI Bus 0000:01 7f600000-7f6000ff : 0000:00:1f.3 7f601000-7f601fff : Intel Flush Page bfd00000-bfdfffff : PCI Bus 0000:02 bfe00000-bfefffff : PCI Bus 0000:03 bfeff000-bfefffff : 0000:03:00.0 bfeff000-bfefffff : Mantis Core d0000000-dfffffff : 0000:00:02.0 d0000000-d017ffff : vesafb e0000000-efffffff : PCI MMCONFIG 0000 [bus 00-ff] e0000000-efffffff : pnp 00:0b fec00000-fec003ff : IOAPIC 0 fed00000-fed003ff : HPET 0 fed14000-fed19fff : pnp 00:01 fed1c000-fed1ffff : pnp 00:08 fed20000-fed8ffff : pnp 00:08 fee00000-fee00fff : Local APIC fee00000-fee00fff : reserved fee00000-fee00fff : pnp 00:0a ff400000-ff4fffff : PCI Bus 0000:01 ff4e0000-ff4effff : 0000:01:00.0 ff4fe000-ff4fffff : 0000:01:00.0 ff4fe000-ff4fffff : ahci ff500000-ff5fffff : PCI Bus 0000:03 ff5c0000-ff5dffff : 0000:03:04.0 ff5f8000-ff5fbfff : 0000:03:04.0 ff5f8000-ff5fbfff : skge ff5ff000-ff5ff7ff : 0000:03:03.0 ff5ff000-ff5ff7ff : firewire_ohci ff5ffc00-ff5ffdff : 0000:03:02.0 ff5ffc00-ff5ffdff : saa7146 ff800000-ff8fffff : 0000:00:02.1 ff9f4000-ff9f7fff : 0000:00:1b.0 ff9f4000-ff9f7fff : ICH HD audio ff9fac00-ff9fafff : 0000:00:1d.7 ff9fac00-ff9fafff : ehci_hcd ff9fb000-ff9fb3ff : 0000:00:1a.7 ff9fb000-ff9fb3ff : ehci_hcd ff9fb400-ff9fb40f : 0000:00:03.0 ff9fb800-ff9fbfff : 0000:00:1f.2 ff9fb800-ff9fbfff : ahci ffa00000-ffafffff : 0000:00:02.0 ffb00000-ffffffff : reserved fff00000-fffffffe : pnp 00:08 PCI information: 00:00.0 Host bridge: Intel Corporation 82P965/G965 Memory Controller Hub (rev 02) Subsystem: ASUSTeK Computer Inc. Device 820b Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information: Len=09 <?> Kernel driver in use: agpgart-intel 00:02.0 VGA compatible controller: Intel Corporation 82G965 Integrated Graphics Controller (rev 02) (prog-if 00 [VGA controller]) Subsystem: ASUSTeK Computer Inc. Device 820b Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 42 Region 0: Memory at ffa00000 (32-bit, non-prefetchable) [size=1M] Region 2: Memory at d0000000 (64-bit, prefetchable) [size=256M] Region 4: I/O ports at ec00 [size=8] Expansion ROM at <unassigned> [disabled] Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4181 Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: i915 00:02.1 Display controller: Intel Corporation 82G965 Integrated Graphics Controller (rev 02) Subsystem: ASUSTeK Computer Inc. Device 820b Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 0: Memory at ff800000 (32-bit, non-prefetchable) [size=1M] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 00:03.0 Communication controller: Intel Corporation 82P965/G965 HECI Controller (rev 02) Subsystem: ASUSTeK Computer Inc. Device 820b Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 10 Region 0: Memory at ff9fb400 (64-bit, non-prefetchable) [size=16] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [8c] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 00:1a.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. P5B Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at dc00 [size=32] Kernel driver in use: uhci_hcd 00:1a.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. P5B Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 17 Region 4: I/O ports at e000 [size=32] Kernel driver in use: uhci_hcd 00:1a.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 (rev 02) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. P5B Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 0: Memory at ff9fb000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00:1b.0 Audio device: Intel Corporation 82801H (ICH8 Family) HD Audio Controller (rev 02) Subsystem: ASUSTeK Computer Inc. Device 821a Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 41 Region 0: Memory at ff9f4000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 4179 Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 Status: NegoPending- InProgress- Capabilities: [130 v1] Root Complex Link Desc: PortNumber=0f ComponentID=00 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c000 Kernel driver in use: HDA Intel 00:1c.0 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 (rev 02) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: 7f000000-7f3fffff Prefetchable memory behind bridge: 00000000bfd00000-00000000bfdfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x2, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #0, PowerLimit 0.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: ASUSTeK Computer Inc. Device 821a Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed+ WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Capabilities: [180 v1] Root Complex Link Desc: PortNumber=01 ComponentID=00 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c001 00:1c.4 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 5 (rev 02) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: ff400000-ff4fffff Prefetchable memory behind bridge: 000000007f400000-000000007f5fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #0, PowerLimit 0.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: ASUSTeK Computer Inc. Device 821a Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed+ WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Capabilities: [180 v1] Root Complex Link Desc: PortNumber=05 ComponentID=00 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c001 00:1d.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. P5B Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 4: I/O ports at d480 [size=32] Kernel driver in use: uhci_hcd 00:1d.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. P5B Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at d800 [size=32] Kernel driver in use: uhci_hcd 00:1d.2 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. P5B Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at d880 [size=32] Kernel driver in use: uhci_hcd 00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 02) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. P5B Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 0: Memory at ff9fac00 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev f2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=32 I/O behind bridge: 0000c000-0000cfff Memory behind bridge: ff500000-ff5fffff Prefetchable memory behind bridge: 00000000bfe00000-00000000bfefffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR+ BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Subsystem: ASUSTeK Computer Inc. Device 821a 00:1f.0 ISA bridge: Intel Corporation 82801HB/HR (ICH8/R) LPC Interface Controller (rev 02) Subsystem: ASUSTeK Computer Inc. Device 821a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information: Len=0c <?> 00:1f.2 SATA controller: Intel Corporation 82801HB (ICH8) 4 port SATA AHCI Controller (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASUSTeK Computer Inc. Device 821a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 40 Region 0: I/O ports at e880 [size=8] Region 1: I/O ports at e800 [size=4] Region 2: I/O ports at e480 [size=8] Region 3: I/O ports at e400 [size=4] Region 4: I/O ports at e080 [size=32] Region 5: Memory at ff9fb800 (32-bit, non-prefetchable) [size=2K] Capabilities: [80] MSI: Enable+ Count=1/16 Maskable- 64bit- Address: fee0f00c Data: 4161 Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a8] SATA HBA v1.0 BAR4 Offset=00000004 Kernel driver in use: ahci 00:1f.3 SMBus: Intel Corporation 82801H (ICH8 Family) SMBus Controller (rev 02) Subsystem: ASUSTeK Computer Inc. Device 821a Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 18 Region 0: Memory at 7f600000 (32-bit, non-prefetchable) [size=256] Region 4: I/O ports at 0400 [size=32] 01:00.0 SATA controller: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) (prog-if 01 [AHCI 1.0]) Subsystem: ASUSTeK Computer Inc. P5B [JMB363] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 16 Region 5: Memory at ff4fe000 (32-bit, non-prefetchable) [size=8K] Expansion ROM at ff4e0000 [disabled] [size=64K] Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Express (v1) Legacy Endpoint, MSI 01 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr+ UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Kernel driver in use: ahci 01:00.1 IDE interface: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc. P5B [JMB363] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 17 Region 0: I/O ports at bc00 [size=8] Region 1: I/O ports at b880 [size=4] Region 2: I/O ports at b800 [size=8] Region 3: I/O ports at b480 [size=4] Region 4: I/O ports at b400 [size=16] Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pata_jmicron 03:00.0 Multimedia controller: Twinhan Technology Co. Ltd Mantis DTV PCI Bridge Controller [Ver 1.0] (rev 01) Subsystem: TERRATEC Electronic GmbH Device 1178 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (2000ns min, 63750ns max) Interrupt: pin A routed to IRQ 21 Region 0: Memory at bfeff000 (32-bit, prefetchable) [size=4K] Kernel driver in use: Mantis 03:01.0 Multimedia audio controller: VIA Technologies Inc. ICE1712 [Envy24] PCI Multi-Channel I/O Controller (rev 02) Subsystem: VIA Technologies Inc. Hoontech ST Audio DSP 24 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin A routed to IRQ 3 Region 0: I/O ports at cc00 [size=32] Region 1: I/O ports at c880 [size=16] Region 2: I/O ports at c800 [size=16] Region 3: I/O ports at c480 [size=64] Capabilities: [80] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 03:02.0 Multimedia controller: Philips Semiconductors SAA7146 (rev 01) Subsystem: TERRATEC Electronic GmbH Terratec Cynergy 1200C Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (3750ns min, 9500ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at ff5ffc00 (32-bit, non-prefetchable) [size=512] Kernel driver in use: budget_av 03:03.0 FireWire (IEEE 1394): VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller (rev c0) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc. M4A series motherboard Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (8000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 21 Region 0: Memory at ff5ff000 (32-bit, non-prefetchable) [size=2K] Region 1: I/O ports at c400 [size=128] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: firewire_ohci 03:04.0 Ethernet controller: Marvell Technology Group Ltd. 88E8001 Gigabit Ethernet Controller (rev 14) Subsystem: ASUSTeK Computer Inc. Marvell 88E8001 Gigabit Ethernet Controller (Asus) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (5750ns min, 7750ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at ff5f8000 (32-bit, non-prefetchable) [size=16K] Region 1: I/O ports at c000 [size=256] Expansion ROM at ff5c0000 [disabled] [size=128K] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Product Name: Marvell Yukon 88E8001 Gigabit Ethernet Controller Read-only fields: [PN] Part number: Yukon 88E8001 [EC] Engineering changes: Rev. 1.4 [MN] Manufacture ID: 4d 61 72 76 65 6c 6c [SN] Serial number: AbCdEfG48C1DF [CP] Extended capability: 01 10 cc 03 [RV] Reserved: checksum good, 9 byte(s) reserved Read/write fields: [RW] Read-write area: 121 byte(s) free End Kernel driver in use: skge SCSI information: Attached devices: Host: scsi0 Channel: 00 Id: 00 Lun: 00 Vendor: HL-DT-ST Model: DVDRAM GSA-4163B Rev: A106 Type: CD-ROM ANSI SCSI revision: 05 Host: scsi2 Channel: 00 Id: 00 Lun: 00 Vendor: ATA Model: WDC WD2500YS-01S Rev: 20.0 Type: Direct-Access ANSI SCSI revision: 05 Host: scsi7 Channel: 00 Id: 00 Lun: 00 Vendor: ATA Model: WDC WD5000AAKS-0 Rev: 01.0 Type: Direct-Access ANSI SCSI revision: 05 Other information: Contents of /proc/asound/card0/codec#0 : Codec: Analog Devices AD1988 Address: 0 AFG Function Id: 0x1 (unsol 0) Vendor Id: 0x11d41988 Subsystem Id: 0x104381e1 Revision Id: 0x100400 No Modem Function Group found Default PCM: rates [0x7ff]: 8000 11025 16000 22050 32000 44100 48000 88200 96000 176400 192000 bits [0xe]: 16 20 24 formats [0x1]: PCM Default Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Default Amp-Out caps: ofs=0x27, nsteps=0x27, stepsize=0x05, mute=0 GPIO: io=2, o=0, i=0, unsolicited=1, wake=0 IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 IO[1]: enable=0, dir=0, wake=0, sticky=0, data=1, unsol=0 Node 0x02 [Audio Output] wcaps 0x30311: Stereo Digital Control: name="IEC958 Playback Con Mask", index=0, device=0 Control: name="IEC958 Playback Pro Mask", index=0, device=0 Control: name="IEC958 Playback Default", index=0, device=0 Control: name="IEC958 Playback Switch", index=0, device=0 Control: name="IEC958 Default PCM Playback Switch", index=0, device=0 Control: name="IEC958 Playback Source", index=0, device=0 Device: name="AD198x Digital", type="SPDIF", device=1 Converter: stream=8, channel=0 Digital: Enabled GenLevel Digital category: 0x2 PCM: rates [0x7e0]: 44100 48000 88200 96000 176400 192000 bits [0xe]: 16 20 24 formats [0x5]: PCM AC3 Delay: 3 samples Connection: 1 0x1d Node 0x03 [Audio Output] wcaps 0x405: Stereo Amp-Out Amp-Out caps: ofs=0x27, nsteps=0x27, stepsize=0x05, mute=0 Amp-Out vals: [0x27 0x27] Converter: stream=0, channel=0 Power states: D0 D3 Power: setting=D0, actual=D0 Node 0x04 [Audio Output] wcaps 0x405: Stereo Amp-Out Control: name="Front Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Device: name="AD198x Analog", type="Audio", device=0 Amp-Out caps: ofs=0x27, nsteps=0x27, stepsize=0x05, mute=0 Amp-Out vals: [0x23 0x23] Converter: stream=0, channel=0 Power states: D0 D3 Power: setting=D0, actual=D0 Node 0x05 [Audio Output] wcaps 0x405: Stereo Amp-Out Control: name="Center Playback Volume", index=0, device=0 ControlAmp: chs=1, dir=Out, idx=0, ofs=0 Control: name="LFE Playback Volume", index=0, device=0 ControlAmp: chs=2, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x27, nsteps=0x27, stepsize=0x05, mute=0 Amp-Out vals: [0x00 0x00] Converter: stream=0, channel=0 Power states: D0 D3 Power: setting=D0, actual=D0 Node 0x06 [Audio Output] wcaps 0x405: Stereo Amp-Out Control: name="Surround Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x27, nsteps=0x27, stepsize=0x05, mute=0 Amp-Out vals: [0x00 0x00] Converter: stream=0, channel=0 Power states: D0 D3 Power: setting=D0, actual=D0 Node 0x07 [Audio Input] wcaps 0x130391: Stereo Digital Converter: stream=0, channel=0 SDI-Select: 0 Digital: Digital category: 0x0 PCM: rates [0x7e0]: 44100 48000 88200 96000 176400 192000 bits [0xe]: 16 20 24 formats [0x5]: PCM AC3 Unsolicited: tag=00, enabled=0 Delay: 3 samples Connection: 1 0x1c Node 0x08 [Audio Input] wcaps 0x100501: Stereo Device: name="AD198x Analog", type="Audio", device=0 Converter: stream=0, channel=0 SDI-Select: 0 Power states: D0 D3 Power: setting=D0, actual=D0 Connection: 1 0x0c Node 0x09 [Audio Input] wcaps 0x100501: Stereo Converter: stream=0, channel=0 SDI-Select: 0 Power states: D0 D3 Power: setting=D0, actual=D0 Connection: 1 0x0d Node 0x0a [Audio Output] wcaps 0x405: Stereo Amp-Out Control: name="Side Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x27, nsteps=0x27, stepsize=0x05, mute=0 Amp-Out vals: [0x00 0x00] Converter: stream=0, channel=0 Power states: D0 D3 Power: setting=D0, actual=D0 Node 0x0b [Audio Selector] wcaps 0x300301: Stereo Digital Connection: 3 0x08* 0x09 0x0f Node 0x0c [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Control: name="Capture Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Capture Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Input Source", index=0, device=0 Amp-Out caps: ofs=0x27, nsteps=0x36, stepsize=0x05, mute=1 Amp-Out vals: [0xa7 0xa7] Connection: 10 0x38 0x39 0x3a* 0x3b 0x3c 0x18 0x24 0x25 0x3d 0x20 Node 0x0d [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Control: name="Capture Volume", index=1, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Capture Switch", index=1, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Input Source", index=1, device=0 Amp-Out caps: ofs=0x27, nsteps=0x36, stepsize=0x05, mute=1 Amp-Out vals: [0xa7 0xa7] Connection: 10 0x38 0x39 0x3a* 0x3b 0x3c 0x18 0x24 0x25 0x3d 0x20 Node 0x0e [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Control: name="Capture Volume", index=2, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Capture Switch", index=2, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Input Source", index=2, device=0 Amp-Out caps: ofs=0x27, nsteps=0x36, stepsize=0x05, mute=1 Amp-Out vals: [0xa7 0xa7] Connection: 10 0x38 0x39 0x3a* 0x3b 0x3c 0x18 0x24 0x25 0x3d 0x20 Node 0x0f [Audio Input] wcaps 0x100501: Stereo Converter: stream=0, channel=0 SDI-Select: 0 Power states: D0 D3 Power: setting=D0, actual=D0 Connection: 1 0x0e Node 0x10 [Beep Generator Widget] wcaps 0x70000c: Mono Amp-Out Control: name="Beep Playback Volume", index=0, device=0 ControlAmp: chs=1, dir=Out, idx=0, ofs=0 Control: name="Beep Playback Switch", index=0, device=0 ControlAmp: chs=1, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x0f, nsteps=0x0f, stepsize=0x0b, mute=1 Amp-Out vals: [0x00] Node 0x11 [Pin Complex] wcaps 0x40018d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x0000373f: IN OUT HP Detect Trigger ImpSense Vref caps: HIZ 50 GRD 80 100 Pin Default 0x02214030: [Jack] HP Out at Ext Front Conn = 1/8, Color = Green DefAssociation = 0x3, Sequence = 0x0 Pin-ctls: 0xc0: OUT HP VREF_HIZ Unsolicited: tag=00, enabled=0 Connection: 1 0x22 Node 0x12 [Pin Complex] wcaps 0x40018d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x0000373f: IN OUT HP Detect Trigger ImpSense Vref caps: HIZ 50 GRD 80 100 Pin Default 0x01014010: [Jack] Line Out at Ext Rear Conn = 1/8, Color = Green DefAssociation = 0x1, Sequence = 0x0 Pin-ctls: 0x40: OUT VREF_HIZ Unsolicited: tag=00, enabled=0 Connection: 1 0x29 Node 0x13 [Pin Complex] wcaps 0x40010c: Mono Amp-Out Amp-Out caps: ofs=0x1f, nsteps=0x1f, stepsize=0x05, mute=1 Amp-Out vals: [0x00] Pincap 0x00000010: OUT Pin Default 0x511711f0: [N/A] Speaker at Int Rear Conn = Analog, Color = Black DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x40: OUT Connection: 1 0x2d Node 0x14 [Pin Complex] wcaps 0x40018d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0000373f: IN OUT HP Detect Trigger ImpSense Vref caps: HIZ 50 GRD 80 100 Pin Default 0x02a19022: [Jack] Mic at Ext Front Conn = 1/8, Color = Pink DefAssociation = 0x2, Sequence = 0x2 Pin-ctls: 0x24: IN VREF_80 Unsolicited: tag=00, enabled=0 Connection: 1 0x2b Node 0x15 [Pin Complex] wcaps 0x40018d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x00003737: IN OUT Detect Trigger ImpSense Vref caps: HIZ 50 GRD 80 100 Pin Default 0x01813021: [Jack] Line In at Ext Rear Conn = 1/8, Color = Blue DefAssociation = 0x2, Sequence = 0x1 Pin-ctls: 0x20: IN VREF_HIZ Unsolicited: tag=00, enabled=0 Connection: 1 0x2c Node 0x16 [Pin Complex] wcaps 0x40018d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x00003737: IN OUT Detect Trigger ImpSense Vref caps: HIZ 50 GRD 80 100 Pin Default 0x01011012: [Jack] Line Out at Ext Rear Conn = 1/8, Color = Black DefAssociation = 0x1, Sequence = 0x2 Pin-ctls: 0x40: OUT VREF_HIZ Unsolicited: tag=00, enabled=0 Connection: 1 0x2a Node 0x17 [Pin Complex] wcaps 0x40098d: Stereo Amp-Out R/L Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x00003737: IN OUT Detect Trigger ImpSense Vref caps: HIZ 50 GRD 80 100 Pin Default 0x01a19020: [Jack] Mic at Ext Rear Conn = 1/8, Color = Pink DefAssociation = 0x2, Sequence = 0x0 Pin-ctls: 0x24: IN VREF_80 Unsolicited: tag=00, enabled=0 Connection: 1 0x26 Node 0x18 [Pin Complex] wcaps 0x400001: Stereo Pincap 0x00000020: IN Pin Default 0x9933112e: [Fixed] CD at Int ATAPI Conn = ATAPI, Color = Black DefAssociation = 0x2, Sequence = 0xe Misc = NO_PRESENCE Pin-ctls: 0x20: IN Node 0x19 [Power Widget] wcaps 0x500500: Mono Power states: D0 D3 Power: setting=D0, actual=D0 Connection: 2 0x20 0x21 Node 0x1a [Pin Complex] wcaps 0x400000: Mono Pincap 0x00000020: IN Pin Default 0x99f301f0: [Fixed] Other at Int ATAPI Conn = ATAPI, Color = Unknown DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN Node 0x1b [Pin Complex] wcaps 0x40030d: Stereo Digital Amp-Out Control: name="IEC958 Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="IEC958 Playback Source", index=0, device=0 Amp-Out caps: ofs=0x27, nsteps=0x27, stepsize=0x05, mute=1 Amp-Out vals: [0x25 0x25] Pincap 0x00000010: OUT Pin Default 0x0145f1f0: [Jack] SPDIF Out at Ext Rear Conn = Optical, Color = Other DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x40: OUT Connection: 1 0x02 Node 0x1c [Pin Complex] wcaps 0x40020b: Stereo Digital Amp-In Amp-In caps: ofs=0x17, nsteps=0x1f, stepsize=0x05, mute=1 Amp-In vals: [0x97 0x97] Pincap 0x00000020: IN Pin Default 0x41c5f1f0: [N/A] SPDIF In at Ext Rear Conn = Optical, Color = Other DefAssociation = 0xf, Sequence = 0x0 Misc = NO_PRESENCE Pin-ctls: 0x20: IN Node 0x1d [Audio Mixer] wcaps 0x200303: Stereo Digital Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x80 0x80] Connection: 2 0x01 0x0b Node 0x1e [Audio Mixer] wcaps 0x200103: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x36 0x21 Node 0x1f [Volume Knob Widget] wcaps 0x600080: Mono Volume-Knob: delta=1, steps=63, direct=0, val=0 Unsolicited: tag=00, enabled=0 Connection: 0 Node 0x20 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In Control: name="Mic Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=4, ofs=0 Control: name="Mic Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=4, ofs=0 Control: name="Front Mic Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Front Mic Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=0, ofs=0 Control: name="Line Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=1, ofs=0 Control: name="Line Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=1, ofs=0 Control: name="Front Line Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Control: name="Front Line Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Control: name="CD Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=6, ofs=0 Control: name="CD Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=6, ofs=0 Control: name="Aux Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Control: name="Aux Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Amp-In caps: ofs=0x17, nsteps=0x1f, stepsize=0x05, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] Connection: 8 0x39 0x33 0x38 0x3d 0x34 0x3b 0x18 0x1a Node 0x21 [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Control: name="Analog Mix Playback Volume", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Control: name="Analog Mix Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x1f, nsteps=0x1f, stepsize=0x05, mute=1 Amp-Out vals: [0x9f 0x9f] Connection: 1 0x20 Node 0x22 [Audio Mixer] wcaps 0x200103: Stereo Amp-In Control: name="Headphone Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x37 0x21 Node 0x23 [Vendor Defined Widget] wcaps 0xf00100: Mono Connection: 18 0x11* 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x24 0x25 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x20 0x21 Node 0x24 [Pin Complex] wcaps 0x40098d: Stereo Amp-Out R/L Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x00000037: IN OUT Detect Trigger ImpSense Pin Default 0x01016011: [Jack] Line Out at Ext Rear Conn = 1/8, Color = Orange DefAssociation = 0x1, Sequence = 0x1 Pin-ctls: 0x40: OUT Unsolicited: tag=00, enabled=0 Connection: 1 0x27 Node 0x25 [Pin Complex] wcaps 0x40018d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x00 0x00] Pincap 0x00000037: IN OUT Detect Trigger ImpSense Pin Default 0x01012013: [Jack] Line Out at Ext Rear Conn = 1/8, Color = Grey DefAssociation = 0x1, Sequence = 0x3 Pin-ctls: 0x40: OUT Unsolicited: tag=00, enabled=0 Connection: 1 0x28 Node 0x26 [Audio Mixer] wcaps 0x200103: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x32 0x21 Node 0x27 [Audio Mixer] wcaps 0x200103: Stereo Amp-In Control: name="Center Playback Switch", index=0, device=0 ControlAmp: chs=1, dir=In, idx=2, ofs=0 Control: name="LFE Playback Switch", index=0, device=0 ControlAmp: chs=2, dir=In, idx=2, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x05 0x21 Node 0x28 [Audio Mixer] wcaps 0x200103: Stereo Amp-In Control: name="Side Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x0a 0x21 Node 0x29 [Audio Mixer] wcaps 0x200103: Stereo Amp-In Control: name="Front Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x00 0x00] [0x00 0x00] Connection: 2 0x04 0x21 Node 0x2a [Audio Mixer] wcaps 0x200103: Stereo Amp-In Control: name="Surround Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=In, idx=2, ofs=0 Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x06 0x21 Node 0x2b [Audio Mixer] wcaps 0x200103: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x30 0x21 Node 0x2c [Audio Mixer] wcaps 0x200103: Stereo Amp-In Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-In vals: [0x80 0x80] [0x80 0x80] Connection: 2 0x31 0x21 Node 0x2d [Audio Mixer] wcaps 0x200100: Mono Connection: 1 0x1e Node 0x2e [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x2f [Vendor Defined Widget] wcaps 0xf00100: Mono Connection: 6 0x11* 0x12 0x14 0x15 0x16 0x17 Node 0x30 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x03* 0x04 0x06 Node 0x31 [Audio Selector] wcaps 0x300101: Stereo Connection: 2 0x04* 0x0a Node 0x32 [Audio Selector] wcaps 0x300101: Stereo Connection: 2 0x05* 0x04 Node 0x33 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x3a* 0x25 0x24 Node 0x34 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x3c* 0x25 0x24 Node 0x35 [Vendor Defined Widget] wcaps 0xf00000: Mono Node 0x36 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x03 0x04* 0x06 Node 0x37 [Audio Selector] wcaps 0x300101: Stereo Connection: 3 0x03 0x04* 0x06 Node 0x38 [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 1 0x11 Node 0x39 [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Control: name="Front Mic Boost", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=1, ofs=0 Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 1 0x14 Node 0x3a [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 1 0x15 Node 0x3b [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 1 0x16 Node 0x3c [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Control: name="Mic Boost", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=4, ofs=0 Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 1 0x17 Node 0x3d [Audio Selector] wcaps 0x30010d: Stereo Amp-Out Amp-Out caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0 Amp-Out vals: [0x00 0x00] Connection: 1 0x12 Kernel .config: # # Automatically generated make config: don't edit # Linux kernel version: 2.6.36-rc5 # Tue Sep 21 18:07:38 2010 # CONFIG_64BIT=y # CONFIG_X86_32 is not set CONFIG_X86_64=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf64-x86-64" CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_MMU=y CONFIG_ZONE_DMA=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y # CONFIG_RWSEM_GENERIC_SPINLOCK is not set CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HAS_DEFAULT_IDLE=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_HAVE_CPUMASK_OF_CPU_MAP=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ZONE_DMA32=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_AUDIT_ARCH=y CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_HAVE_EARLY_RES=y CONFIG_HAVE_INTEL_TXT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_USE_GENERIC_SMP_HELPERS=y CONFIG_X86_64_SMP=y CONFIG_X86_HT=y CONFIG_X86_TRAMPOLINE=y CONFIG_ARCH_HWEIGHT_CFLAGS="-fcall-saved-rdi -fcall-saved-rsi -fcall-saved-rdx -fcall-saved-rcx -fcall-saved-r8 -fcall-saved-r9 -fcall-saved-r10 -fcall-saved-r11" # CONFIG_KTIME_SCALAR is not set CONFIG_ARCH_CPU_PROBE_RELEASE=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_CONSTRUCTORS=y # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_CROSS_COMPILE="" CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_WATCH=y CONFIG_AUDIT_TREE=y # # RCU Subsystem # # CONFIG_TREE_RCU is not set CONFIG_TREE_PREEMPT_RCU=y # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=64 # CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y CONFIG_NET_NS=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_LZO=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_HAVE_PERF_EVENTS=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_PERF_COUNTERS is not set # CONFIG_DEBUG_PERF_USE_VMALLOC is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_PROFILING is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_USER_RETURN_NOTIFIER=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y CONFIG_HAVE_PERF_EVENTS_NMI=y # # GCOV-based kernel profiling # # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_PREEMPT_NOTIFIERS=y # CONFIG_INLINE_SPIN_TRYLOCK is not set # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK is not set # CONFIG_INLINE_SPIN_LOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK_IRQ is not set # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set # CONFIG_INLINE_SPIN_UNLOCK is not set # CONFIG_INLINE_SPIN_UNLOCK_BH is not set # CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_READ_TRYLOCK is not set # CONFIG_INLINE_READ_LOCK is not set # CONFIG_INLINE_READ_LOCK_BH is not set # CONFIG_INLINE_READ_LOCK_IRQ is not set # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set # CONFIG_INLINE_READ_UNLOCK is not set # CONFIG_INLINE_READ_UNLOCK_BH is not set # CONFIG_INLINE_READ_UNLOCK_IRQ is not set # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_WRITE_TRYLOCK is not set # CONFIG_INLINE_WRITE_LOCK is not set # CONFIG_INLINE_WRITE_LOCK_BH is not set # CONFIG_INLINE_WRITE_LOCK_IRQ is not set # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set # CONFIG_INLINE_WRITE_UNLOCK is not set # CONFIG_INLINE_WRITE_UNLOCK_BH is not set # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_FREEZER=y # # Processor type and features # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_SMP=y # CONFIG_X86_X2APIC is not set CONFIG_SPARSE_IRQ=y CONFIG_X86_MPPARSE=y # CONFIG_X86_EXTENDED_PLATFORM is not set CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_PARAVIRT_GUEST=y # CONFIG_XEN is not set CONFIG_KVM_CLOCK=y CONFIG_KVM_GUEST=y CONFIG_PARAVIRT=y CONFIG_PARAVIRT_SPINLOCKS=y CONFIG_PARAVIRT_CLOCK=y # CONFIG_PARAVIRT_DEBUG is not set CONFIG_NO_BOOTMEM=y # CONFIG_MEMTEST is not set # CONFIG_MK8 is not set # CONFIG_MPSC is not set CONFIG_MCORE2=y # CONFIG_MATOM is not set # CONFIG_GENERIC_CPU is not set CONFIG_X86_CPU=y CONFIG_X86_INTERNODE_CACHE_SHIFT=6 CONFIG_X86_CMPXCHG=y CONFIG_X86_L1_CACHE_SHIFT=6 CONFIG_X86_XADD=y CONFIG_X86_WP_WORKS_OK=y CONFIG_X86_INTEL_USERCOPY=y CONFIG_X86_USE_PPRO_CHECKSUM=y CONFIG_X86_P6_NOP=y CONFIG_X86_TSC=y CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=64 CONFIG_X86_DEBUGCTLMSR=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y CONFIG_CPU_SUP_CENTAUR=y CONFIG_HPET_TIMER=y CONFIG_HPET_EMULATE_RTC=y CONFIG_DMI=y CONFIG_GART_IOMMU=y # CONFIG_CALGARY_IOMMU is not set CONFIG_AMD_IOMMU=y # CONFIG_AMD_IOMMU_STATS is not set CONFIG_SWIOTLB=y CONFIG_IOMMU_HELPER=y CONFIG_IOMMU_API=y # CONFIG_MAXSMP is not set CONFIG_NR_CPUS=8 CONFIG_SCHED_SMT=y CONFIG_SCHED_MC=y # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_X86_LOCAL_APIC=y CONFIG_X86_IO_APIC=y CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y CONFIG_X86_MCE=y CONFIG_X86_MCE_INTEL=y CONFIG_X86_MCE_AMD=y CONFIG_X86_MCE_THRESHOLD=y # CONFIG_X86_MCE_INJECT is not set CONFIG_X86_THERMAL_VECTOR=y # CONFIG_I8K is not set CONFIG_MICROCODE=m CONFIG_MICROCODE_INTEL=y CONFIG_MICROCODE_AMD=y CONFIG_MICROCODE_OLD_INTERFACE=y CONFIG_X86_MSR=m CONFIG_X86_CPUID=m CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_DIRECT_GBPAGES=y # CONFIG_NUMA is not set CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y CONFIG_SPARSEMEM_VMEMMAP=y # CONFIG_MEMORY_HOTPLUG is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y # CONFIG_HWPOISON_INJECT is not set CONFIG_X86_CHECK_BIOS_CORRUPTION=y CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y CONFIG_X86_RESERVE_LOW_64K=y CONFIG_MTRR=y CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y # CONFIG_EFI is not set # CONFIG_SECCOMP is not set # CONFIG_CC_STACKPROTECTOR is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set CONFIG_HZ_1000=y CONFIG_HZ=1000 CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y # CONFIG_CRASH_DUMP is not set # CONFIG_KEXEC_JUMP is not set CONFIG_PHYSICAL_START=0x1000000 CONFIG_RELOCATABLE=y CONFIG_PHYSICAL_ALIGN=0x1000000 CONFIG_HOTPLUG_CPU=y # CONFIG_COMPAT_VDSO is not set # CONFIG_CMDLINE_BOOL is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # # Power management and ACPI options # CONFIG_ARCH_HIBERNATION_HEADER=y CONFIG_PM=y # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP_SMP=y CONFIG_PM_SLEEP=y CONFIG_SUSPEND_NVS=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_HIBERNATION=y CONFIG_PM_STD_PARTITION="" CONFIG_PM_RUNTIME=y CONFIG_PM_OPS=y CONFIG_ACPI=y CONFIG_ACPI_SLEEP=y # CONFIG_ACPI_PROCFS is not set # CONFIG_ACPI_PROCFS_POWER is not set CONFIG_ACPI_POWER_METER=y CONFIG_ACPI_SYSFS_POWER=y # CONFIG_ACPI_EC_DEBUGFS is not set # CONFIG_ACPI_PROC_EVENT is not set CONFIG_ACPI_AC=m CONFIG_ACPI_BATTERY=m CONFIG_ACPI_BUTTON=m CONFIG_ACPI_VIDEO=m CONFIG_ACPI_FAN=m CONFIG_ACPI_DOCK=y CONFIG_ACPI_PROCESSOR=m CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m CONFIG_ACPI_THERMAL=m # CONFIG_ACPI_CUSTOM_DSDT is not set CONFIG_ACPI_BLACKLIST_YEAR=0 # CONFIG_ACPI_DEBUG is not set CONFIG_ACPI_PCI_SLOT=m CONFIG_X86_PM_TIMER=y CONFIG_ACPI_CONTAINER=m CONFIG_ACPI_SBS=m CONFIG_ACPI_HED=m CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=m # CONFIG_ACPI_APEI_ERST_DEBUG is not set # CONFIG_SFI is not set # # CPU Frequency scaling # CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_TABLE=y # CONFIG_CPU_FREQ_DEBUG is not set CONFIG_CPU_FREQ_STAT=m CONFIG_CPU_FREQ_STAT_DETAILS=y # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set CONFIG_CPU_FREQ_GOV_USERSPACE=m CONFIG_CPU_FREQ_GOV_ONDEMAND=y # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set # # CPUFreq processor drivers # CONFIG_X86_PCC_CPUFREQ=m CONFIG_X86_ACPI_CPUFREQ=m CONFIG_X86_POWERNOW_K8=m # CONFIG_X86_SPEEDSTEP_CENTRINO is not set # CONFIG_X86_P4_CLOCKMOD is not set # # shared options # # CONFIG_X86_SPEEDSTEP_LIB is not set CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_INTEL_IDLE=y # # Memory power savings # CONFIG_I7300_IDLE_IOAT_CHANNEL=y CONFIG_I7300_IDLE=y # # Bus options (PCI etc.) # CONFIG_PCI=y CONFIG_PCI_DIRECT=y CONFIG_PCI_MMCONFIG=y CONFIG_PCI_DOMAINS=y # CONFIG_PCI_CNB20LE_QUIRK is not set CONFIG_DMAR=y CONFIG_DMAR_DEFAULT_ON=y CONFIG_DMAR_FLOPPY_WA=y CONFIG_INTR_REMAP=y CONFIG_PCIEPORTBUS=y CONFIG_PCIEAER=y CONFIG_PCIE_ECRC=y # CONFIG_PCIEAER_INJECT is not set CONFIG_PCIEASPM=y # CONFIG_PCIEASPM_DEBUG is not set CONFIG_PCIE_PME=y CONFIG_ARCH_SUPPORTS_MSI=y CONFIG_PCI_MSI=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set CONFIG_HT_IRQ=y CONFIG_PCI_IOV=y CONFIG_PCI_IOAPIC=y CONFIG_ISA_DMA_API=y CONFIG_K8_NB=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # # Executable file formats / Emulations # CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_IA32_EMULATION=y CONFIG_IA32_AOUT=y CONFIG_COMPAT=y CONFIG_COMPAT_FOR_U64_ALIGNMENT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_NET=y CONFIG_COMPAT_NETLINK_MESSAGES=y # # Networking options # CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y # CONFIG_IP_PNP is not set CONFIG_NET_IPIP=m CONFIG_NET_IPGRE=m CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_ARPD=y CONFIG_SYN_COOKIES=y CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_LRO=y CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=y CONFIG_TCP_CONG_CUBIC=m CONFIG_TCP_CONG_WESTWOOD=m CONFIG_TCP_CONG_HTCP=m CONFIG_TCP_CONG_HSTCP=m CONFIG_TCP_CONG_HYBLA=m CONFIG_TCP_CONG_VEGAS=m CONFIG_TCP_CONG_SCALABLE=m CONFIG_TCP_CONG_LP=m # CONFIG_TCP_CONG_VENO is not set # CONFIG_TCP_CONG_YEAH is not set # CONFIG_TCP_CONG_ILLINOIS is not set CONFIG_DEFAULT_BIC=y # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="bic" # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m # CONFIG_IPV6_MIP6 is not set CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=m CONFIG_INET6_XFRM_MODE_TRANSPORT=m CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set CONFIG_IPV6_SIT=m # CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y # CONFIG_IPV6_SUBTREES is not set CONFIG_IPV6_MROUTE=y # CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set # CONFIG_IPV6_PIMSM_V2 is not set CONFIG_NETWORK_SECMARK=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=y # # Core Netfilter Configuration # CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CT_PROTO_DCCP=m CONFIG_NF_CT_PROTO_SCTP=m CONFIG_NF_CT_PROTO_UDPLITE=m # CONFIG_NF_CONNTRACK_AMANDA is not set CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m # CONFIG_NF_CONNTRACK_PPTP is not set # CONFIG_NF_CONNTRACK_SANE is not set CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=m # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=m CONFIG_NETFILTER_XT_CONNMARK=m # # Xtables targets # # CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_HL=m # CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m # CONFIG_NETFILTER_XT_TARGET_TEE is not set CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m # CONFIG_NETFILTER_XT_MATCH_CPU is not set CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_HL=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m # CONFIG_NETFILTER_XT_MATCH_IPVS is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m # CONFIG_NETFILTER_XT_MATCH_OSF is not set CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m CONFIG_IP_VS=m # CONFIG_IP_VS_IPV6 is not set # CONFIG_IP_VS_DEBUG is not set CONFIG_IP_VS_TAB_BITS=12 # # IPVS transport protocol load balancing support # CONFIG_IP_VS_PROTO_TCP=y CONFIG_IP_VS_PROTO_UDP=y CONFIG_IP_VS_PROTO_AH_ESP=y CONFIG_IP_VS_PROTO_ESP=y CONFIG_IP_VS_PROTO_AH=y # CONFIG_IP_VS_PROTO_SCTP is not set # # IPVS scheduler # CONFIG_IP_VS_RR=m CONFIG_IP_VS_WRR=m CONFIG_IP_VS_LC=m CONFIG_IP_VS_WLC=m CONFIG_IP_VS_LBLC=m CONFIG_IP_VS_LBLCR=m CONFIG_IP_VS_DH=m CONFIG_IP_VS_SH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m # # IPVS application helper # CONFIG_IP_VS_FTP=m # # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_DCCP=m CONFIG_NF_NAT_PROTO_UDPLITE=m CONFIG_NF_NAT_PROTO_SCTP=m CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m CONFIG_NF_NAT_TFTP=m # CONFIG_NF_NAT_AMANDA is not set # CONFIG_NF_NAT_PPTP is not set CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m # CONFIG_IP_NF_TARGET_CLUSTERIP is not set CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m # CONFIG_BRIDGE_EBT_IP6 is not set CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m CONFIG_BRIDGE_EBT_STP=m CONFIG_BRIDGE_EBT_VLAN=m CONFIG_BRIDGE_EBT_ARPREPLY=m CONFIG_BRIDGE_EBT_DNAT=m CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m # CONFIG_BRIDGE_EBT_NFLOG is not set CONFIG_IP_DCCP=m CONFIG_INET_DCCP_DIAG=m # # DCCP CCIDs Configuration (EXPERIMENTAL) # # CONFIG_IP_DCCP_CCID2_DEBUG is not set CONFIG_IP_DCCP_CCID3=y # CONFIG_IP_DCCP_CCID3_DEBUG is not set CONFIG_IP_DCCP_CCID3_RTO=100 CONFIG_IP_DCCP_TFRC_LIB=y # # DCCP Kernel Hacking # # CONFIG_IP_DCCP_DEBUG is not set CONFIG_IP_SCTP=m # CONFIG_SCTP_DBG_MSG is not set # CONFIG_SCTP_DBG_OBJCNT is not set # CONFIG_SCTP_HMAC_NONE is not set # CONFIG_SCTP_HMAC_SHA1 is not set CONFIG_SCTP_HMAC_MD5=y # CONFIG_RDS is not set CONFIG_TIPC=m CONFIG_TIPC_ADVANCED=y CONFIG_TIPC_ZONES=3 CONFIG_TIPC_CLUSTERS=1 CONFIG_TIPC_NODES=255 CONFIG_TIPC_PORTS=8191 CONFIG_TIPC_LOG=0 # CONFIG_TIPC_DEBUG is not set CONFIG_ATM=y CONFIG_ATM_CLIP=y # CONFIG_ATM_CLIP_NO_ICMP is not set CONFIG_ATM_LANE=m CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set CONFIG_L2TP=m # CONFIG_L2TP_V3 is not set CONFIG_STP=m CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set CONFIG_LLC=m CONFIG_LLC2=m # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set CONFIG_WAN_ROUTER=m # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # # Queueing/Scheduling # CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m CONFIG_NET_SCH_MULTIQ=m CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m CONFIG_NET_SCH_TBF=m CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_DSMARK=m CONFIG_NET_SCH_NETEM=m CONFIG_NET_SCH_DRR=m CONFIG_NET_SCH_INGRESS=m # # Classification # CONFIG_NET_CLS=y CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y CONFIG_NET_CLS_FW=m CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_PERF is not set # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m # CONFIG_NET_CLS_FLOW is not set CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=m CONFIG_NET_EMATCH_NBYTE=m CONFIG_NET_EMATCH_U32=m CONFIG_NET_EMATCH_META=m CONFIG_NET_EMATCH_TEXT=m CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=m CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_IPT=m # CONFIG_NET_ACT_NAT is not set CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m # CONFIG_NET_ACT_SKBEDIT is not set # CONFIG_NET_CLS_IND is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y CONFIG_RPS=y # # Network testing # CONFIG_NET_PKTGEN=m # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set CONFIG_IRDA=m # # IrDA protocols # CONFIG_IRLAN=m CONFIG_IRCOMM=m # CONFIG_IRDA_ULTRA is not set # # IrDA options # CONFIG_IRDA_CACHE_LAST_LSAP=y CONFIG_IRDA_FAST_RR=y CONFIG_IRDA_DEBUG=y # # Infrared-port device drivers # # # SIR device drivers # CONFIG_IRTTY_SIR=m # # Dongle support # CONFIG_DONGLE=y CONFIG_ESI_DONGLE=m CONFIG_ACTISYS_DONGLE=m CONFIG_TEKRAM_DONGLE=m # CONFIG_TOIM3232_DONGLE is not set CONFIG_LITELINK_DONGLE=m CONFIG_MA600_DONGLE=m CONFIG_GIRBIL_DONGLE=m CONFIG_MCP2120_DONGLE=m CONFIG_OLD_BELKIN_DONGLE=m CONFIG_ACT200L_DONGLE=m # CONFIG_KINGSUN_DONGLE is not set # CONFIG_KSDAZZLE_DONGLE is not set # CONFIG_KS959_DONGLE is not set # # FIR device drivers # CONFIG_USB_IRDA=m CONFIG_SIGMATEL_FIR=m CONFIG_NSC_FIR=m CONFIG_WINBOND_FIR=m CONFIG_SMC_IRCC_FIR=m CONFIG_ALI_FIR=m CONFIG_VLSI_FIR=m CONFIG_VIA_FIR=m # CONFIG_MCS_FIR is not set CONFIG_BT=m CONFIG_BT_L2CAP=m CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m # # Bluetooth device drivers # CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y # CONFIG_BT_HCIUART_ATH3K is not set CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m # CONFIG_BT_MRVL_SDIO is not set CONFIG_BT_ATH3K=m # CONFIG_AF_RXRPC is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y CONFIG_WEXT_SPY=y CONFIG_WEXT_PRIV=y CONFIG_CFG80211=m # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_WEXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=m CONFIG_LIB80211_CRYPT_WEP=m CONFIG_LIB80211_CRYPT_CCMP=m CONFIG_LIB80211_CRYPT_TKIP=m # CONFIG_LIB80211_DEBUG is not set CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_MINSTREL_HT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y # CONFIG_NET_9P is not set # CONFIG_CAIF is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m # CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_PNP=y CONFIG_PNP_DEBUG_MESSAGES=y # # Protocols # CONFIG_PNPACPI=y CONFIG_BLK_DEV=y CONFIG_BLK_DEV_FD=m # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m # CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_SX8=m # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=65536 # CONFIG_BLK_DEV_XIP is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m CONFIG_VIRTIO_BLK=m # CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set CONFIG_EEPROM_93CX6=m CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # CONFIG_SCSI_MOD=y CONFIG_RAID_ATTRS=m CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set CONFIG_SCSI_NETLINK=y CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=m # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set CONFIG_BLK_DEV_SR=m CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_FC_ATTRS=m CONFIG_SCSI_ISCSI_ATTRS=m # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set # CONFIG_ATA_VERBOSE_ERROR is not set CONFIG_ATA_ACPI=y CONFIG_SATA_PMP=y # # Controllers with non-SFF native interface # CONFIG_SATA_AHCI=m CONFIG_SATA_AHCI_PLATFORM=m # CONFIG_SATA_INIC162X is not set CONFIG_SATA_SIL24=m CONFIG_ATA_SFF=y # # SFF controllers with custom DMA interface # # CONFIG_PDC_ADMA is not set # CONFIG_SATA_QSTOR is not set # CONFIG_SATA_SX4 is not set CONFIG_ATA_BMDMA=y # # SATA SFF controllers with BMDMA # CONFIG_ATA_PIIX=m # CONFIG_SATA_MV is not set CONFIG_SATA_NV=m # CONFIG_SATA_PROMISE is not set CONFIG_SATA_SIL=m # CONFIG_SATA_SIS is not set # CONFIG_SATA_SVW is not set # CONFIG_SATA_ULI is not set CONFIG_SATA_VIA=m # CONFIG_SATA_VITESSE is not set # # PATA SFF controllers with BMDMA # CONFIG_PATA_ALI=m CONFIG_PATA_AMD=m # CONFIG_PATA_ARTOP is not set CONFIG_PATA_ATIIXP=m # CONFIG_PATA_ATP867X is not set # CONFIG_PATA_CMD64X is not set CONFIG_PATA_CS5520=m # CONFIG_PATA_CS5530 is not set # CONFIG_PATA_CYPRESS is not set # CONFIG_PATA_EFAR is not set # CONFIG_PATA_HPT366 is not set # CONFIG_PATA_HPT37X is not set # CONFIG_PATA_HPT3X2N is not set # CONFIG_PATA_HPT3X3 is not set # CONFIG_PATA_IT8213 is not set # CONFIG_PATA_IT821X is not set CONFIG_PATA_JMICRON=m # CONFIG_PATA_MARVELL is not set # CONFIG_PATA_NETCELL is not set # CONFIG_PATA_NINJA32 is not set # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_OPTIDMA is not set # CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RDC is not set # CONFIG_PATA_SC1200 is not set CONFIG_PATA_SCH=m # CONFIG_PATA_SERVERWORKS is not set # CONFIG_PATA_SIL680 is not set CONFIG_PATA_SIS=m # CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_TRIFLEX is not set CONFIG_PATA_VIA=m # CONFIG_PATA_WINBOND is not set # # PIO-only SFF controllers # # CONFIG_PATA_CMD640_PCI is not set CONFIG_PATA_MPIIX=m # CONFIG_PATA_NS87410 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_RZ1000 is not set # # Generic fallback / legacy drivers # CONFIG_PATA_ACPI=m CONFIG_ATA_GENERIC=m # CONFIG_PATA_LEGACY is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m # CONFIG_MD_LINEAR is not set CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m CONFIG_MD_RAID10=m CONFIG_MD_RAID456=m # CONFIG_MULTICORE_RAID456 is not set # CONFIG_MD_MULTIPATH is not set # CONFIG_MD_FAULTY is not set CONFIG_BLK_DEV_DM=m # CONFIG_DM_DEBUG is not set CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m # CONFIG_DM_LOG_USERSPACE is not set CONFIG_DM_ZERO=m # CONFIG_DM_MULTIPATH is not set CONFIG_DM_DELAY=m # CONFIG_DM_UEVENT is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # # # You can enable one or both FireWire driver stacks. # # # The newer stack is recommended. # CONFIG_FIREWIRE=m CONFIG_FIREWIRE_OHCI=m CONFIG_FIREWIRE_OHCI_DEBUG=y CONFIG_FIREWIRE_SBP2=m # CONFIG_FIREWIRE_NET is not set # CONFIG_IEEE1394 is not set # CONFIG_FIREWIRE_NOSY is not set CONFIG_I2O=m CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y CONFIG_I2O_EXT_ADAPTEC=y CONFIG_I2O_EXT_ADAPTEC_DMA64=y CONFIG_I2O_CONFIG=m CONFIG_I2O_CONFIG_OLD_IOCTL=y CONFIG_I2O_BUS=m CONFIG_I2O_BLOCK=m CONFIG_I2O_SCSI=m CONFIG_I2O_PROC=m # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y CONFIG_IFB=m # CONFIG_DUMMY is not set CONFIG_BONDING=m CONFIG_MACVLAN=m # CONFIG_MACVTAP is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set CONFIG_VETH=m # CONFIG_NET_SB1000 is not set # CONFIG_ARCNET is not set CONFIG_PHYLIB=m # # MII PHY device drivers # CONFIG_MARVELL_PHY=m # CONFIG_DAVICOM_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_LXT_PHY=m # CONFIG_CICADA_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_SMSC_PHY is not set CONFIG_BROADCOM_PHY=m # CONFIG_ICPLUS_PHY is not set CONFIG_REALTEK_PHY=m # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=m # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set CONFIG_NET_VENDOR_3COM=y CONFIG_VORTEX=m CONFIG_TYPHOON=m # CONFIG_ETHOC is not set # CONFIG_DNET is not set CONFIG_NET_TULIP=y CONFIG_DE2104X=m CONFIG_DE2104X_DSL=0 CONFIG_TULIP=m # CONFIG_TULIP_MWI is not set # CONFIG_TULIP_MMIO is not set CONFIG_TULIP_NAPI=y CONFIG_TULIP_NAPI_HW_MITIGATION=y CONFIG_DE4X5=m CONFIG_WINBOND_840=m CONFIG_DM9102=m CONFIG_ULI526X=m CONFIG_HP100=m # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set CONFIG_AMD8111_ETH=m # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_KSZ884X_PCI is not set CONFIG_B44=m CONFIG_B44_PCI_AUTOSELECT=y CONFIG_B44_PCICORE_AUTOSELECT=y CONFIG_B44_PCI=y CONFIG_FORCEDETH=m CONFIG_E100=m # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set # CONFIG_NE2K_PCI is not set CONFIG_8139CP=m CONFIG_8139TOO=m # CONFIG_8139TOO_PIO is not set CONFIG_8139TOO_TUNE_TWISTER=y CONFIG_8139TOO_8129=y # CONFIG_8139_OLD_RX_RESET is not set # CONFIG_R6040 is not set CONFIG_SIS900=m # CONFIG_EPIC100 is not set # CONFIG_SMSC9420 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_KS8842 is not set # CONFIG_KS8851_MLL is not set CONFIG_VIA_RHINE=m # CONFIG_VIA_RHINE_MMIO is not set # CONFIG_SC92031 is not set # CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set CONFIG_DL2K=m CONFIG_E1000=m # CONFIG_E1000E is not set # CONFIG_IP1000 is not set CONFIG_IGB=m CONFIG_IGB_DCA=y CONFIG_IGBVF=m # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set CONFIG_R8169=m # CONFIG_R8169_VLAN is not set CONFIG_SIS190=m CONFIG_SKGE=m CONFIG_SKY2=m CONFIG_VIA_VELOCITY=m # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set # CONFIG_CNIC is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set CONFIG_JME=m # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set CONFIG_WLAN=y # CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_AIRO is not set # CONFIG_ATMEL is not set # CONFIG_AT76C50X_USB is not set # CONFIG_PRISM54 is not set # CONFIG_USB_ZD1201 is not set # CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_RTL8180 is not set # CONFIG_RTL8187 is not set # CONFIG_ADM8211 is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_MWL8K is not set # CONFIG_ATH_COMMON is not set CONFIG_B43=m CONFIG_B43_PCI_AUTOSELECT=y CONFIG_B43_PCICORE_AUTOSELECT=y # CONFIG_B43_SDIO is not set CONFIG_B43_PIO=y CONFIG_B43_PHY_LP=y CONFIG_B43_LEDS=y CONFIG_B43_HWRNG=y # CONFIG_B43_DEBUG is not set # CONFIG_B43LEGACY is not set CONFIG_HOSTAP=m CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m CONFIG_IPW2100=m # CONFIG_IPW2100_MONITOR is not set # CONFIG_IPW2100_DEBUG is not set CONFIG_IPW2200=m # CONFIG_IPW2200_MONITOR is not set # CONFIG_IPW2200_QOS is not set # CONFIG_IPW2200_DEBUG is not set CONFIG_LIBIPW=m # CONFIG_LIBIPW_DEBUG is not set CONFIG_IWLWIFI=m # CONFIG_IWLWIFI_DEBUG is not set CONFIG_IWLAGN=m CONFIG_IWL4965=y CONFIG_IWL5000=y CONFIG_IWL3945=m # CONFIG_IWM is not set # CONFIG_LIBERTAS is not set # CONFIG_HERMES is not set # CONFIG_P54_COMMON is not set CONFIG_RT2X00=m CONFIG_RT2400PCI=m CONFIG_RT2500PCI=m # CONFIG_RT61PCI is not set CONFIG_RT2800PCI_PCI=y # CONFIG_RT2800PCI is not set # CONFIG_RT2500USB is not set # CONFIG_RT73USB is not set # CONFIG_RT2800USB is not set CONFIG_RT2X00_LIB_PCI=m CONFIG_RT2X00_LIB=m CONFIG_RT2X00_LIB_LEDS=y # CONFIG_RT2X00_DEBUG is not set # CONFIG_WL12XX is not set # CONFIG_ZD1211RW is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # # USB Network Adapters # CONFIG_USB_CATC=m CONFIG_USB_KAWETH=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_USBNET=m CONFIG_USB_NET_AX8817X=m CONFIG_USB_NET_CDCETHER=m # CONFIG_USB_NET_CDC_EEM is not set # CONFIG_USB_NET_DM9601 is not set # CONFIG_USB_NET_SMSC75XX is not set # CONFIG_USB_NET_SMSC95XX is not set CONFIG_USB_NET_GL620A=m CONFIG_USB_NET_NET1080=m CONFIG_USB_NET_PLUSB=m # CONFIG_USB_NET_MCS7830 is not set CONFIG_USB_NET_RNDIS_HOST=m CONFIG_USB_NET_CDC_SUBSET=m CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_BELKIN=y CONFIG_USB_ARMLINUX=y CONFIG_USB_EPSON2888=y # CONFIG_USB_KC2190 is not set CONFIG_USB_NET_ZAURUS=m # CONFIG_USB_HSO is not set # CONFIG_USB_NET_INT51X1 is not set # CONFIG_USB_IPHETH is not set # CONFIG_USB_SIERRA_NET is not set # CONFIG_WAN is not set # CONFIG_ATM_DRIVERS is not set # # CAIF transport drivers # # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set CONFIG_NETCONSOLE=m # CONFIG_NETCONSOLE_DYNAMIC is not set CONFIG_NETPOLL=y # CONFIG_NETPOLL_TRAP is not set CONFIG_NET_POLL_CONTROLLER=y CONFIG_VIRTIO_NET=m # CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set CONFIG_INPUT_POLLDEV=m CONFIG_INPUT_SPARSEKMAP=m # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ADP5588 is not set CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=m CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_SENTELIC is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_APPLETOUCH is not set # CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_SYNAPTICS_I2C is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_PCSPKR is not set # CONFIG_INPUT_APANEL is not set # CONFIG_INPUT_ATLAS_BTNS is not set # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set CONFIG_INPUT_UINPUT=m # CONFIG_INPUT_WINBOND_CIR is not set # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_ADXL34X is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_I8042=y # CONFIG_SERIO_SERPORT is not set # CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=m # CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # # Serial drivers # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_PNP=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set CONFIG_SERIAL_8250_RSA=y # # Non-8250 serial port support # # CONFIG_SERIAL_MFD_HSU is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 CONFIG_HVC_DRIVER=y CONFIG_VIRTIO_CONSOLE=m CONFIG_IPMI_HANDLER=m # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m CONFIG_IPMI_WATCHDOG=m CONFIG_IPMI_POWEROFF=m CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set CONFIG_HW_RANDOM_INTEL=y CONFIG_HW_RANDOM_AMD=y CONFIG_HW_RANDOM_VIA=y CONFIG_HW_RANDOM_VIRTIO=m CONFIG_NVRAM=m # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set CONFIG_RAW_DRIVER=m CONFIG_MAX_RAW_DEVS=256 CONFIG_HPET=y CONFIG_HPET_MMAP=y CONFIG_HANGCHECK_TIMER=m # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set CONFIG_DEVPORT=y # CONFIG_RAMOOPS is not set CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_MUX=m # # Multiplexer I2C Chip support # # CONFIG_I2C_MUX_PCA954x is not set CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=m CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support # # # PC SMBus host controller drivers # CONFIG_I2C_ALI1535=m CONFIG_I2C_ALI1563=m CONFIG_I2C_ALI15X3=m CONFIG_I2C_AMD756=m CONFIG_I2C_AMD756_S4882=m CONFIG_I2C_AMD8111=m CONFIG_I2C_I801=m CONFIG_I2C_ISCH=m CONFIG_I2C_PIIX4=m CONFIG_I2C_NFORCE2=m # CONFIG_I2C_NFORCE2_S4985 is not set CONFIG_I2C_SIS5595=m CONFIG_I2C_SIS630=m CONFIG_I2C_SIS96X=m CONFIG_I2C_VIA=m CONFIG_I2C_VIAPRO=m # # ACPI drivers # # CONFIG_I2C_SCMI is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers # CONFIG_I2C_PARPORT_LIGHT=m # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set # # Other I2C/SMBus bus drivers # CONFIG_I2C_STUB=m # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_SPI is not set # # PPS support # # CONFIG_PPS is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set # CONFIG_PDA_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_BATTERY_DS2760 is not set # CONFIG_BATTERY_DS2782 is not set # CONFIG_BATTERY_BQ27x00 is not set # CONFIG_BATTERY_MAX17040 is not set CONFIG_HWMON=y CONFIG_HWMON_VID=m # CONFIG_HWMON_DEBUG_CHIP is not set # # Native drivers # # CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_ABITUGURU3 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_ADM1025=m CONFIG_SENSORS_ADM1026=m # CONFIG_SENSORS_ADM1029 is not set CONFIG_SENSORS_ADM1031=m CONFIG_SENSORS_ADM9240=m CONFIG_SENSORS_ADT7411=m # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ASC7621 is not set CONFIG_SENSORS_K8TEMP=m CONFIG_SENSORS_K10TEMP=m CONFIG_SENSORS_ASB100=m CONFIG_SENSORS_ATXP1=m CONFIG_SENSORS_DS1621=m # CONFIG_SENSORS_I5K_AMB is not set CONFIG_SENSORS_F71805F=m # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FSCHMD is not set CONFIG_SENSORS_G760A=m CONFIG_SENSORS_GL518SM=m CONFIG_SENSORS_GL520SM=m CONFIG_SENSORS_CORETEMP=m CONFIG_SENSORS_PKGTEMP=m # CONFIG_SENSORS_IBMAEM is not set # CONFIG_SENSORS_IBMPEX is not set CONFIG_SENSORS_IT87=m CONFIG_SENSORS_JC42=m CONFIG_SENSORS_LM63=m # CONFIG_SENSORS_LM73 is not set CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM77=m CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM80=m CONFIG_SENSORS_LM83=m CONFIG_SENSORS_LM85=m CONFIG_SENSORS_LM87=m CONFIG_SENSORS_LM90=m CONFIG_SENSORS_LM92=m # CONFIG_SENSORS_LM93 is not set CONFIG_SENSORS_LTC4215=m # CONFIG_SENSORS_LTC4245 is not set CONFIG_SENSORS_LM95241=m CONFIG_SENSORS_MAX1619=m CONFIG_SENSORS_MAX6650=m CONFIG_SENSORS_PC87360=m # CONFIG_SENSORS_PC87427 is not set CONFIG_SENSORS_PCF8591=m CONFIG_SENSORS_SIS5595=m # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set # CONFIG_SENSORS_EMC2103 is not set CONFIG_SENSORS_SMSC47M1=m # CONFIG_SENSORS_SMSC47M192 is not set CONFIG_SENSORS_SMSC47B397=m # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VIA_CPUTEMP is not set CONFIG_SENSORS_VIA686A=m CONFIG_SENSORS_VT1211=m CONFIG_SENSORS_VT8231=m CONFIG_SENSORS_W83781D=m CONFIG_SENSORS_W83791D=m CONFIG_SENSORS_W83792D=m CONFIG_SENSORS_W83793=m CONFIG_SENSORS_W83L785TS=m CONFIG_SENSORS_W83L786NG=m CONFIG_SENSORS_W83627HF=m CONFIG_SENSORS_W83627EHF=m CONFIG_SENSORS_HDAPS=m # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_SENSORS_APPLESMC is not set # # ACPI drivers # CONFIG_SENSORS_ATK0110=m # CONFIG_SENSORS_LIS3LV02D is not set CONFIG_THERMAL=y CONFIG_THERMAL_HWMON=y CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set # # Watchdog Device Drivers # CONFIG_SOFT_WATCHDOG=m CONFIG_ACQUIRE_WDT=m CONFIG_ADVANTECH_WDT=m CONFIG_ALIM1535_WDT=m CONFIG_ALIM7101_WDT=m # CONFIG_F71808E_WDT is not set CONFIG_SC520_WDT=m # CONFIG_SBC_FITPC2_WATCHDOG is not set CONFIG_EUROTECH_WDT=m CONFIG_IB700_WDT=m CONFIG_IBMASR=m CONFIG_WAFER_WDT=m CONFIG_I6300ESB_WDT=m # CONFIG_ITCO_WDT is not set # CONFIG_IT8712F_WDT is not set # CONFIG_IT87_WDT is not set # CONFIG_HP_WATCHDOG is not set CONFIG_SC1200_WDT=m # CONFIG_PC87413_WDT is not set CONFIG_60XX_WDT=m CONFIG_SBC8360_WDT=m CONFIG_CPU5_WDT=m # CONFIG_SMSC_SCH311X_WDT is not set # CONFIG_SMSC37B787_WDT is not set CONFIG_W83627HF_WDT=m # CONFIG_W83697HF_WDT is not set # CONFIG_W83697UG_WDT is not set CONFIG_W83877F_WDT=m CONFIG_W83977F_WDT=m CONFIG_MACHZ_WDT=m CONFIG_SBC_EPX_C3_WATCHDOG=m # # PCI-based Watchdog Cards # CONFIG_PCIPCWATCHDOG=m CONFIG_WDTPCI=m # # USB-based Watchdog Cards # CONFIG_USBPCWATCHDOG=m CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # CONFIG_SSB=m CONFIG_SSB_SPROM=y CONFIG_SSB_BLOCKIO=y CONFIG_SSB_PCIHOST_POSSIBLE=y CONFIG_SSB_PCIHOST=y CONFIG_SSB_B43_PCI_BRIDGE=y CONFIG_SSB_SDIOHOST_POSSIBLE=y # CONFIG_SSB_SDIOHOST is not set # CONFIG_SSB_DEBUG is not set CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y CONFIG_SSB_DRIVER_PCICORE=y CONFIG_MFD_SUPPORT=y CONFIG_MFD_CORE=m # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_ABX500_CORE is not set CONFIG_LPC_SCH=m # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_JANZ_CMODIO is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set # CONFIG_REGULATOR_DUMMY is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=m CONFIG_REGULATOR_USERSPACE_CONSUMER=m # CONFIG_REGULATOR_BQ24022 is not set # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_LP3971 is not set # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set # CONFIG_REGULATOR_ISL6271A is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_MEDIA_SUPPORT=m # # Multimedia core support # CONFIG_VIDEO_DEV=m CONFIG_VIDEO_V4L2_COMMON=m # CONFIG_VIDEO_ALLOW_V4L1 is not set CONFIG_VIDEO_V4L1_COMPAT=y CONFIG_DVB_CORE=m CONFIG_VIDEO_MEDIA=m # # Multimedia drivers # CONFIG_VIDEO_SAA7146=m CONFIG_VIDEO_SAA7146_VV=m CONFIG_IR_CORE=m CONFIG_VIDEO_IR=m CONFIG_LIRC=m CONFIG_RC_MAP=m CONFIG_IR_NEC_DECODER=m CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m CONFIG_IR_JVC_DECODER=m CONFIG_IR_SONY_DECODER=m CONFIG_IR_LIRC_CODEC=m CONFIG_IR_IMON=m # CONFIG_IR_MCEUSB is not set CONFIG_IR_ENE=m CONFIG_IR_STREAMZAP=m CONFIG_MEDIA_ATTACH=y CONFIG_MEDIA_TUNER=m # CONFIG_MEDIA_TUNER_CUSTOMISE is not set CONFIG_MEDIA_TUNER_SIMPLE=m CONFIG_MEDIA_TUNER_TDA8290=m CONFIG_MEDIA_TUNER_TDA827X=m CONFIG_MEDIA_TUNER_TDA18271=m CONFIG_MEDIA_TUNER_TDA9887=m CONFIG_MEDIA_TUNER_TEA5761=m CONFIG_MEDIA_TUNER_TEA5767=m CONFIG_MEDIA_TUNER_MT20XX=m CONFIG_MEDIA_TUNER_XC2028=m CONFIG_MEDIA_TUNER_XC5000=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_DMA_SG=m CONFIG_VIDEOBUF_DVB=m CONFIG_VIDEO_TVEEPROM=m CONFIG_VIDEO_TUNER=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_HELPER_CHIPS_AUTO=y CONFIG_VIDEO_IR_I2C=m CONFIG_VIDEO_SAA6588=m # CONFIG_VIDEO_VIVI is not set # CONFIG_VIDEO_BT848 is not set # CONFIG_VIDEO_SAA5246A is not set # CONFIG_VIDEO_SAA5249 is not set # CONFIG_VIDEO_ZORAN is not set CONFIG_VIDEO_SAA7134=m CONFIG_VIDEO_SAA7134_ALSA=m CONFIG_VIDEO_SAA7134_DVB=m # CONFIG_VIDEO_MXB is not set # CONFIG_VIDEO_HEXIUM_ORION is not set # CONFIG_VIDEO_HEXIUM_GEMINI is not set # CONFIG_VIDEO_CX88 is not set # CONFIG_VIDEO_CX23885 is not set # CONFIG_VIDEO_AU0828 is not set # CONFIG_VIDEO_IVTV is not set # CONFIG_VIDEO_CX18 is not set # CONFIG_VIDEO_SAA7164 is not set # CONFIG_VIDEO_CAFE_CCIC is not set # CONFIG_SOC_CAMERA is not set # CONFIG_V4L_USB_DRIVERS is not set CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_TESTDEV is not set # CONFIG_RADIO_ADAPTERS is not set CONFIG_DVB_MAX_ADAPTERS=8 CONFIG_DVB_DYNAMIC_MINORS=y CONFIG_DVB_CAPTURE_DRIVERS=y # # Supported SAA7146 based PCI Adapters # CONFIG_TTPCI_EEPROM=m CONFIG_DVB_AV7110=m CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_CORE=m CONFIG_DVB_BUDGET=m CONFIG_DVB_BUDGET_CI=m CONFIG_DVB_BUDGET_AV=m CONFIG_DVB_BUDGET_PATCH=m # # Supported USB Adapters # CONFIG_DVB_USB=m # CONFIG_DVB_USB_DEBUG is not set # CONFIG_DVB_USB_A800 is not set # CONFIG_DVB_USB_DIBUSB_MB is not set # CONFIG_DVB_USB_DIBUSB_MC is not set # CONFIG_DVB_USB_DIB0700 is not set # CONFIG_DVB_USB_UMT_010 is not set # CONFIG_DVB_USB_CXUSB is not set # CONFIG_DVB_USB_M920X is not set # CONFIG_DVB_USB_GL861 is not set # CONFIG_DVB_USB_AU6610 is not set # CONFIG_DVB_USB_DIGITV is not set # CONFIG_DVB_USB_VP7045 is not set # CONFIG_DVB_USB_VP702X is not set # CONFIG_DVB_USB_GP8PSK is not set # CONFIG_DVB_USB_NOVA_T_USB2 is not set # CONFIG_DVB_USB_TTUSB2 is not set # CONFIG_DVB_USB_DTT200U is not set # CONFIG_DVB_USB_OPERA1 is not set # CONFIG_DVB_USB_AF9005 is not set # CONFIG_DVB_USB_DW2102 is not set # CONFIG_DVB_USB_CINERGY_T2 is not set # CONFIG_DVB_USB_ANYSEE is not set # CONFIG_DVB_USB_DTV5100 is not set # CONFIG_DVB_USB_AF9015 is not set # CONFIG_DVB_USB_CE6230 is not set # CONFIG_DVB_USB_FRIIO is not set # CONFIG_DVB_USB_EC168 is not set # CONFIG_DVB_USB_AZ6027 is not set CONFIG_DVB_TTUSB_BUDGET=m CONFIG_DVB_TTUSB_DEC=m # CONFIG_SMS_SIANO_MDTV is not set # # Supported FlexCopII (B2C2) Adapters # # CONFIG_DVB_B2C2_FLEXCOP is not set # # Supported BT878 Adapters # # # Supported Pluto2 Adapters # # CONFIG_DVB_PLUTO2 is not set # # Supported SDMC DM1105 Adapters # # CONFIG_DVB_DM1105 is not set # CONFIG_DVB_FIREDTV is not set # # Supported Earthsoft PT1 Adapters # # CONFIG_DVB_PT1 is not set # # Supported Mantis Adapters # CONFIG_MANTIS_CORE=m CONFIG_DVB_MANTIS=m CONFIG_DVB_HOPPER=m # # Supported nGene Adapters # # CONFIG_DVB_NGENE is not set # # Supported DVB Frontends # CONFIG_DVB_FE_CUSTOMISE=y # # Customise DVB Frontends # # # Multistandard (satellite) frontends # # CONFIG_DVB_STB0899 is not set # CONFIG_DVB_STB6100 is not set CONFIG_DVB_STV090x=m CONFIG_DVB_STV6110x=m # # DVB-S (satellite) frontends # CONFIG_DVB_CX24110=m CONFIG_DVB_CX24123=m CONFIG_DVB_MT312=m # CONFIG_DVB_ZL10036 is not set # CONFIG_DVB_ZL10039 is not set CONFIG_DVB_S5H1420=m # CONFIG_DVB_STV0288 is not set # CONFIG_DVB_STB6000 is not set CONFIG_DVB_STV0299=m CONFIG_DVB_STV6110=m # CONFIG_DVB_STV0900 is not set CONFIG_DVB_TDA8083=m CONFIG_DVB_TDA10086=m # CONFIG_DVB_TDA8261 is not set CONFIG_DVB_VES1X93=m # CONFIG_DVB_TUNER_ITD1000 is not set # CONFIG_DVB_TUNER_CX24113 is not set CONFIG_DVB_TDA826X=m CONFIG_DVB_TUA6100=m # CONFIG_DVB_CX24116 is not set # CONFIG_DVB_SI21XX is not set CONFIG_DVB_DS3000=m CONFIG_DVB_MB86A16=m # # DVB-T (terrestrial) frontends # CONFIG_DVB_SP8870=m CONFIG_DVB_SP887X=m CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m # CONFIG_DVB_DRX397XD is not set CONFIG_DVB_L64781=m CONFIG_DVB_TDA1004X=m CONFIG_DVB_NXT6000=m CONFIG_DVB_MT352=m CONFIG_DVB_ZL10353=m CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m # CONFIG_DVB_TDA10048 is not set CONFIG_DVB_AF9013=m # CONFIG_DVB_EC100 is not set # # DVB-C (cable) frontends # CONFIG_DVB_VES1820=m CONFIG_DVB_TDA10021=m CONFIG_DVB_TDA10023=m CONFIG_DVB_STV0297=m # # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # CONFIG_DVB_NXT200X=m CONFIG_DVB_OR51211=m CONFIG_DVB_OR51132=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LGDT330X=m # CONFIG_DVB_LGDT3304 is not set # CONFIG_DVB_LGDT3305 is not set # CONFIG_DVB_S5H1409 is not set # CONFIG_DVB_AU8522 is not set # CONFIG_DVB_S5H1411 is not set # # ISDB-T (terrestrial) frontends # # CONFIG_DVB_S921 is not set # CONFIG_DVB_DIB8000 is not set # # Digital terrestrial only tuners/PLL # CONFIG_DVB_PLL=m # CONFIG_DVB_TUNER_DIB0070 is not set # CONFIG_DVB_TUNER_DIB0090 is not set # # SEC control devices for DVB-S # CONFIG_DVB_LNBP21=m # CONFIG_DVB_ISL6405 is not set CONFIG_DVB_ISL6421=m CONFIG_DVB_ISL6423=m # CONFIG_DVB_LGS8GL5 is not set # CONFIG_DVB_LGS8GXX is not set # CONFIG_DVB_ATBM8830 is not set CONFIG_DVB_TDA665x=m # # Tools to develop new frontends # # CONFIG_DVB_DUMMY_FE is not set # CONFIG_DAB is not set # # Graphics support # CONFIG_AGP=y CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=m # CONFIG_AGP_SIS is not set # CONFIG_AGP_VIA is not set CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_VGA_SWITCHEROO is not set CONFIG_DRM=m CONFIG_DRM_KMS_HELPER=m CONFIG_DRM_TTM=m CONFIG_DRM_TDFX=m CONFIG_DRM_R128=m CONFIG_DRM_RADEON=m CONFIG_DRM_RADEON_KMS=y CONFIG_DRM_I810=m CONFIG_DRM_I830=m CONFIG_DRM_I915=m CONFIG_DRM_I915_KMS=y # CONFIG_DRM_MGA is not set # CONFIG_DRM_SIS is not set # CONFIG_DRM_VIA is not set # CONFIG_DRM_SAVAGE is not set CONFIG_VGASTATE=m CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=m CONFIG_FB_BOOT_VESA_SUPPORT=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set # CONFIG_FB_SYS_IMAGEBLIT is not set # CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_SYS_FOPS is not set CONFIG_FB_SVGALIB=m # CONFIG_FB_MACMODES is not set CONFIG_FB_BACKLIGHT=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ARC is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set CONFIG_FB_VGA16=m # CONFIG_FB_UVESA is not set CONFIG_FB_VESA=y # CONFIG_FB_N411 is not set # CONFIG_FB_HGA is not set # CONFIG_FB_S1D13XXX is not set CONFIG_FB_NVIDIA=m CONFIG_FB_NVIDIA_I2C=y # CONFIG_FB_NVIDIA_DEBUG is not set CONFIG_FB_NVIDIA_BACKLIGHT=y # CONFIG_FB_RIVA is not set CONFIG_FB_LE80578=m CONFIG_FB_CARILLO_RANCH=m # CONFIG_FB_MATROX is not set CONFIG_FB_RADEON=m CONFIG_FB_RADEON_I2C=y CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_RADEON_DEBUG is not set CONFIG_FB_ATY128=m CONFIG_FB_ATY128_BACKLIGHT=y CONFIG_FB_ATY=m CONFIG_FB_ATY_CT=y # CONFIG_FB_ATY_GENERIC_LCD is not set CONFIG_FB_ATY_GX=y CONFIG_FB_ATY_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set # CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set CONFIG_FB_VT8623=m # CONFIG_FB_TRIDENT is not set # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set # CONFIG_FB_GEODE is not set # CONFIG_FB_TMIO is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m CONFIG_LCD_PLATFORM=m CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=y # CONFIG_BACKLIGHT_PROGEAR is not set # CONFIG_BACKLIGHT_CARILLO_RANCH is not set # CONFIG_BACKLIGHT_MBP_NVIDIA is not set # CONFIG_BACKLIGHT_SAHARA is not set # CONFIG_BACKLIGHT_ADP8860 is not set # # Display device support # CONFIG_DISPLAY_SUPPORT=m # # Display hardware drivers # # # Console display driver support # CONFIG_VGA_CONSOLE=y CONFIG_VGACON_SOFT_SCROLLBACK=y CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_FONTS=y # CONFIG_FONT_8x8 is not set CONFIG_FONT_8x16=y # CONFIG_FONT_6x11 is not set # CONFIG_FONT_7x14 is not set # CONFIG_FONT_PEARL_8x8 is not set # CONFIG_FONT_ACORN_8x8 is not set # CONFIG_FONT_MINI_4x6 is not set # CONFIG_FONT_SUN8x16 is not set # CONFIG_FONT_SUN12x22 is not set # CONFIG_FONT_10x18 is not set # CONFIG_LOGO is not set CONFIG_SOUND=m CONFIG_SOUND_OSS_CORE=y CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m CONFIG_SND_HWDEP=m CONFIG_SND_RAWMIDI=m CONFIG_SND_JACK=y CONFIG_SND_SEQUENCER=m CONFIG_SND_SEQ_DUMMY=m CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_SEQUENCER_OSS=y CONFIG_SND_HRTIMER=m CONFIG_SND_SEQ_HRTIMER_DEFAULT=y CONFIG_SND_DYNAMIC_MINORS=y # CONFIG_SND_SUPPORT_OLD_API is not set # CONFIG_SND_VERBOSE_PROCFS is not set # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set CONFIG_SND_VMASTER=y CONFIG_SND_DMA_SGBUF=y CONFIG_SND_RAWMIDI_SEQ=m CONFIG_SND_OPL3_LIB_SEQ=m # CONFIG_SND_OPL4_LIB_SEQ is not set # CONFIG_SND_SBAWE_SEQ is not set CONFIG_SND_EMU10K1_SEQ=m CONFIG_SND_MPU401_UART=m CONFIG_SND_OPL3_LIB=m CONFIG_SND_AC97_CODEC=m CONFIG_SND_DRIVERS=y # CONFIG_SND_PCSP is not set CONFIG_SND_DUMMY=m CONFIG_SND_VIRMIDI=m # CONFIG_SND_MTPAV is not set CONFIG_SND_SERIAL_U16550=m CONFIG_SND_MPU401=m CONFIG_SND_AC97_POWER_SAVE=y CONFIG_SND_AC97_POWER_SAVE_DEFAULT=5 CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set # CONFIG_SND_ALS300 is not set # CONFIG_SND_ALS4000 is not set # CONFIG_SND_ALI5451 is not set # CONFIG_SND_ASIHPI is not set # CONFIG_SND_ATIIXP is not set # CONFIG_SND_ATIIXP_MODEM is not set # CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8830 is not set # CONFIG_SND_AW2 is not set # CONFIG_SND_AZT3328 is not set # CONFIG_SND_BT87X is not set CONFIG_SND_CA0106=m CONFIG_SND_CMIPCI=m # CONFIG_SND_OXYGEN is not set # CONFIG_SND_CS4281 is not set # CONFIG_SND_CS46XX is not set # CONFIG_SND_CS5530 is not set # CONFIG_SND_CS5535AUDIO is not set # CONFIG_SND_CTXFI is not set # CONFIG_SND_DARLA20 is not set # CONFIG_SND_GINA20 is not set # CONFIG_SND_LAYLA20 is not set # CONFIG_SND_DARLA24 is not set # CONFIG_SND_GINA24 is not set # CONFIG_SND_LAYLA24 is not set # CONFIG_SND_MONA is not set # CONFIG_SND_MIA is not set # CONFIG_SND_ECHO3G is not set # CONFIG_SND_INDIGO is not set # CONFIG_SND_INDIGOIO is not set # CONFIG_SND_INDIGODJ is not set # CONFIG_SND_INDIGOIOX is not set # CONFIG_SND_INDIGODJX is not set CONFIG_SND_EMU10K1=m CONFIG_SND_EMU10K1X=m CONFIG_SND_ENS1370=m CONFIG_SND_ENS1371=m # CONFIG_SND_ES1938 is not set # CONFIG_SND_ES1968 is not set # CONFIG_SND_FM801 is not set CONFIG_SND_HDA_INTEL=m CONFIG_SND_HDA_HWDEP=y CONFIG_SND_HDA_RECONFIG=y CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_INPUT_BEEP_MODE=0 CONFIG_SND_HDA_INPUT_JACK=y CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_CODEC_REALTEK=y CONFIG_SND_HDA_CODEC_ANALOG=y CONFIG_SND_HDA_CODEC_SIGMATEL=y CONFIG_SND_HDA_CODEC_VIA=y CONFIG_SND_HDA_CODEC_ATIHDMI=y # CONFIG_SND_HDA_CODEC_NVHDMI is not set CONFIG_SND_HDA_CODEC_INTELHDMI=y CONFIG_SND_HDA_ELD=y CONFIG_SND_HDA_CODEC_CIRRUS=y CONFIG_SND_HDA_CODEC_CONEXANT=y CONFIG_SND_HDA_CODEC_CA0110=y CONFIG_SND_HDA_CODEC_CMEDIA=y # CONFIG_SND_HDA_CODEC_SI3054 is not set CONFIG_SND_HDA_GENERIC=y CONFIG_SND_HDA_POWER_SAVE=y CONFIG_SND_HDA_POWER_SAVE_DEFAULT=10 # CONFIG_SND_HDSP is not set CONFIG_SND_HDSPM=m # CONFIG_SND_HIFIER is not set CONFIG_SND_ICE1712=m CONFIG_SND_ICE1724=m CONFIG_SND_INTEL8X0=m # CONFIG_SND_INTEL8X0M is not set # CONFIG_SND_KORG1212 is not set # CONFIG_SND_LX6464ES is not set # CONFIG_SND_MAESTRO3 is not set # CONFIG_SND_MIXART is not set # CONFIG_SND_NM256 is not set # CONFIG_SND_PCXHR is not set # CONFIG_SND_RIPTIDE is not set # CONFIG_SND_RME32 is not set # CONFIG_SND_RME96 is not set # CONFIG_SND_RME9652 is not set # CONFIG_SND_SONICVIBES is not set # CONFIG_SND_TRIDENT is not set CONFIG_SND_VIA82XX=m # CONFIG_SND_VIA82XX_MODEM is not set # CONFIG_SND_VIRTUOSO is not set # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set CONFIG_SND_USB_UA101=m # CONFIG_SND_USB_USX2Y is not set # CONFIG_SND_USB_CAIAQ is not set # CONFIG_SND_USB_US122L is not set # CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set CONFIG_AC97_BUS=m CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HIDRAW is not set # # USB Input Devices # CONFIG_USB_HID=m # CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y # # Special HID drivers # # CONFIG_HID_3M_PCT is not set CONFIG_HID_A4TECH=m # CONFIG_HID_ACRUX_FF is not set CONFIG_HID_APPLE=m CONFIG_HID_BELKIN=m # CONFIG_HID_CANDO is not set CONFIG_HID_CHERRY=m CONFIG_HID_CHICONY=m # CONFIG_HID_PRODIKEYS is not set CONFIG_HID_CYPRESS=m CONFIG_HID_DRAGONRISE=m # CONFIG_DRAGONRISE_FF is not set # CONFIG_HID_EGALAX is not set # CONFIG_HID_ELECOM is not set CONFIG_HID_EZKEY=m CONFIG_HID_KYE=m CONFIG_HID_GYRATION=m CONFIG_HID_TWINHAN=m CONFIG_HID_KENSINGTON=m CONFIG_HID_LOGITECH=m # CONFIG_LOGITECH_FF is not set # CONFIG_LOGIRUMBLEPAD2_FF is not set # CONFIG_LOGIG940_FF is not set CONFIG_HID_MAGICMOUSE=m CONFIG_HID_MICROSOFT=m # CONFIG_HID_MOSART is not set CONFIG_HID_MONTEREY=m CONFIG_HID_NTRIG=m CONFIG_HID_ORTEK=m CONFIG_HID_PANTHERLORD=m # CONFIG_PANTHERLORD_FF is not set CONFIG_HID_PETALYNX=m # CONFIG_HID_PICOLCD is not set # CONFIG_HID_QUANTA is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_ROCCAT_KONE is not set CONFIG_HID_SAMSUNG=m CONFIG_HID_SONY=m # CONFIG_HID_STANTUM is not set CONFIG_HID_SUNPLUS=m CONFIG_HID_GREENASIA=m # CONFIG_GREENASIA_FF is not set CONFIG_HID_SMARTJOYPLUS=m # CONFIG_SMARTJOYPLUS_FF is not set CONFIG_HID_TOPSEED=m CONFIG_HID_THRUSTMASTER=m # CONFIG_THRUSTMASTER_FF is not set CONFIG_HID_WACOM=m # CONFIG_HID_WACOM_POWER_SUPPLY is not set CONFIG_HID_ZEROPLUS=m # CONFIG_ZEROPLUS_FF is not set # CONFIG_HID_ZYDACRON is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG is not set CONFIG_USB_MON=y # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_XHCI_HCD is not set CONFIG_USB_EHCI_HCD=m CONFIG_USB_EHCI_ROOT_HUB_TT=y # CONFIG_USB_EHCI_TT_NEWSCHED is not set # CONFIG_USB_OXU210HP_HCD is not set CONFIG_USB_ISP116X_HCD=m # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=m CONFIG_USB_OHCI_HCD_SSB=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=m CONFIG_USB_SL811_HCD=m # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_WHCI_HCD is not set # CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers # CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m CONFIG_USB_WDM=m # CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set CONFIG_USB_STORAGE_DATAFAB=m CONFIG_USB_STORAGE_FREECOM=m # CONFIG_USB_STORAGE_ISD200 is not set CONFIG_USB_STORAGE_USBAT=m CONFIG_USB_STORAGE_SDDR09=m CONFIG_USB_STORAGE_SDDR55=m CONFIG_USB_STORAGE_JUMPSHOT=m CONFIG_USB_STORAGE_ALAUDA=m # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # CONFIG_USB_MDC800=m CONFIG_USB_MICROTEK=m # # USB port drivers # CONFIG_USB_SERIAL=m CONFIG_USB_EZUSB=y CONFIG_USB_SERIAL_GENERIC=y # CONFIG_USB_SERIAL_AIRCABLE is not set # CONFIG_USB_SERIAL_ARK3116 is not set CONFIG_USB_SERIAL_BELKIN=m # CONFIG_USB_SERIAL_CH341 is not set CONFIG_USB_SERIAL_WHITEHEAT=m CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m # CONFIG_USB_SERIAL_FUNSOFT is not set CONFIG_USB_SERIAL_VISOR=m CONFIG_USB_SERIAL_IPAQ=m CONFIG_USB_SERIAL_IR=m CONFIG_USB_SERIAL_EDGEPORT=m CONFIG_USB_SERIAL_EDGEPORT_TI=m CONFIG_USB_SERIAL_GARMIN=m CONFIG_USB_SERIAL_IPW=m # CONFIG_USB_SERIAL_IUU is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set # CONFIG_USB_SERIAL_KEYSPAN is not set CONFIG_USB_SERIAL_KLSI=m CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m # CONFIG_USB_SERIAL_MOS7720 is not set # CONFIG_USB_SERIAL_MOS7840 is not set # CONFIG_USB_SERIAL_MOTOROLA is not set # CONFIG_USB_SERIAL_NAVMAN is not set CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_OTI6858 is not set # CONFIG_USB_SERIAL_QCAUX is not set # CONFIG_USB_SERIAL_QUALCOMM is not set # CONFIG_USB_SERIAL_SPCP8X5 is not set CONFIG_USB_SERIAL_HP4X=m CONFIG_USB_SERIAL_SAFE=m # CONFIG_USB_SERIAL_SAFE_PADDED is not set # CONFIG_USB_SERIAL_SIEMENS_MPI is not set # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set # CONFIG_USB_SERIAL_SYMBOL is not set CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_WWAN=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m # CONFIG_USB_SERIAL_OPTICON is not set # CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set # CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_DEBUG is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set CONFIG_USB_EMI26=m # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m CONFIG_USB_LED=m # CONFIG_USB_CYPRESS_CY7C63 is not set CONFIG_USB_CYTHERM=m CONFIG_USB_IDMOUSE=m # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set CONFIG_USB_SISUSBVGA=m CONFIG_USB_SISUSBVGA_CON=y CONFIG_USB_LD=m # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set CONFIG_USB_TEST=m # CONFIG_USB_ISIGHTFW is not set CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m CONFIG_USB_UEAGLEATM=m CONFIG_USB_XUSBATM=m CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y # CONFIG_USB_GADGET_R8A66597 is not set # CONFIG_USB_GADGET_M66592 is not set # CONFIG_USB_GADGET_AMD5536UDC is not set # CONFIG_USB_GADGET_CI13XXX is not set CONFIG_USB_GADGET_NET2280=y CONFIG_USB_NET2280=m # CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y CONFIG_USB_ZERO=m CONFIG_USB_AUDIO=m CONFIG_USB_ETH=m CONFIG_USB_ETH_RNDIS=y # CONFIG_USB_ETH_EEM is not set CONFIG_USB_GADGETFS=m # CONFIG_USB_FUNCTIONFS is not set CONFIG_USB_FILE_STORAGE=m # CONFIG_USB_FILE_STORAGE_TEST is not set CONFIG_USB_MASS_STORAGE=m CONFIG_USB_G_SERIAL=m # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set # CONFIG_USB_CDC_COMPOSITE is not set CONFIG_USB_G_MULTI=m CONFIG_USB_G_MULTI_RNDIS=y # CONFIG_USB_G_MULTI_CDC is not set CONFIG_USB_G_HID=m # CONFIG_USB_G_DBGP is not set CONFIG_USB_G_WEBCAM=m # # OTG and related infrastructure # # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set CONFIG_MMC=m # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set # # MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=m CONFIG_MMC_BLOCK_BOUNCE=y CONFIG_SDIO_UART=m # CONFIG_MMC_TEST is not set # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_SDHCI=m CONFIG_MMC_SDHCI_PCI=m # CONFIG_MMC_RICOH_MMC is not set CONFIG_MMC_SDHCI_PLTFM=m CONFIG_MMC_WBSD=m # CONFIG_MMC_TIFM_SD is not set # CONFIG_MMC_CB710 is not set # CONFIG_MMC_VIA_SDMMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m # # LED drivers # # CONFIG_LEDS_ALIX2 is not set # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_CLEVO_MAIL is not set # CONFIG_LEDS_PCA955X is not set CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_INTEL_SS4200 is not set # CONFIG_LEDS_DELL_NETBOOKS is not set CONFIG_LEDS_TRIGGERS=y # # LED Triggers # CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set # # iptables trigger is under Netfilter config (LED target) # # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC=y # # Reporting subsystems # # CONFIG_EDAC_DEBUG is not set CONFIG_EDAC_DECODE_MCE=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_AMD64=m # CONFIG_EDAC_AMD64_ERROR_INJECTION is not set CONFIG_EDAC_E752X=m CONFIG_EDAC_I82975X=m CONFIG_EDAC_I3000=m CONFIG_EDAC_I3200=m CONFIG_EDAC_X38=m CONFIG_EDAC_I5400=m # CONFIG_EDAC_I7CORE is not set CONFIG_EDAC_I5000=m CONFIG_EDAC_I5100=m CONFIG_RTC_LIB=m CONFIG_RTC_CLASS=m # # RTC interfaces # CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set # CONFIG_RTC_DRV_TEST is not set # # I2C RTC drivers # # CONFIG_RTC_DRV_DS1307 is not set # CONFIG_RTC_DRV_DS1374 is not set # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_MAX6900 is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set # CONFIG_RTC_DRV_X1205 is not set # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_BQ32K is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers # # # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=m # CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set # CONFIG_RTC_DRV_MSM6242 is not set # CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set # # DMA Devices # CONFIG_INTEL_MID_DMAC=m CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y CONFIG_INTEL_IOATDMA=m # CONFIG_TIMB_DMA is not set CONFIG_PCH_DMA=m CONFIG_DMA_ENGINE=y # # DMA Clients # CONFIG_NET_DMA=y CONFIG_ASYNC_TX_DMA=y # CONFIG_DMATEST is not set CONFIG_DCA=m CONFIG_AUXDISPLAY=y CONFIG_UIO=m # CONFIG_UIO_CIF is not set # CONFIG_UIO_PDRV is not set # CONFIG_UIO_PDRV_GENIRQ is not set # CONFIG_UIO_AEC is not set # CONFIG_UIO_SERCOS3 is not set CONFIG_UIO_PCI_GENERIC=m # CONFIG_UIO_NETX is not set CONFIG_STAGING=y # CONFIG_STAGING_EXCLUDE_BUILD is not set # CONFIG_ET131X is not set # CONFIG_SLICOSS is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_CX25821 is not set # CONFIG_VIDEO_TM6000 is not set # CONFIG_USB_IP_COMMON is not set # CONFIG_W35UND is not set # CONFIG_PRISM2_USB is not set # CONFIG_ECHO is not set # CONFIG_OTUS is not set # CONFIG_RT2860 is not set # CONFIG_RT2870 is not set # CONFIG_COMEDI is not set # CONFIG_ASUS_OLED is not set # CONFIG_R8187SE is not set # CONFIG_RTL8192SU is not set # CONFIG_RTL8192U is not set # CONFIG_RTL8192E is not set # CONFIG_TRANZPORT is not set # CONFIG_POHMELFS is not set # CONFIG_IDE_PHISON is not set # CONFIG_LINE6_USB is not set # CONFIG_DRM_VMWGFX is not set CONFIG_DRM_NOUVEAU=m CONFIG_DRM_NOUVEAU_BACKLIGHT=y # # I2C encoder or helper chips # # CONFIG_DRM_I2C_CH7006 is not set CONFIG_DRM_I2C_SIL164=m # CONFIG_USB_SERIAL_QUATECH2 is not set # CONFIG_USB_SERIAL_QUATECH_USB2 is not set # CONFIG_VT6655 is not set # CONFIG_VT6656 is not set # CONFIG_FB_UDL is not set # CONFIG_HYPERV is not set # CONFIG_VME_BUS is not set # CONFIG_IIO is not set CONFIG_ZRAM=m CONFIG_ZRAM_STATS=y # CONFIG_BATMAN_ADV is not set # CONFIG_SAMSUNG_LAPTOP is not set # CONFIG_FB_SM7XX is not set # CONFIG_VIDEO_DT3155 is not set # CONFIG_CRYSTALHD is not set # # Texas Instruments shared transport line discipline # # CONFIG_TI_ST is not set # CONFIG_ST_BT is not set # CONFIG_FB_XGI is not set CONFIG_LIRC_STAGING=y CONFIG_LIRC_BT829=m CONFIG_LIRC_I2C=m # CONFIG_LIRC_IGORPLUGUSB is not set # CONFIG_LIRC_IMON is not set CONFIG_LIRC_IT87=m CONFIG_LIRC_ITE8709=m # CONFIG_LIRC_SASEM is not set CONFIG_LIRC_SERIAL=m CONFIG_LIRC_SERIAL_TRANSMITTER=y CONFIG_LIRC_SIR=m # CONFIG_LIRC_TTUSBIR is not set # CONFIG_LIRC_ZILOG is not set # CONFIG_EASYCAP is not set # CONFIG_SOLO6X10 is not set # CONFIG_ACPI_QUICKSTART is not set CONFIG_X86_PLATFORM_DEVICES=y # CONFIG_ACER_WMI is not set # CONFIG_ACERHDF is not set CONFIG_ASUS_LAPTOP=m # CONFIG_DELL_WMI is not set # CONFIG_FUJITSU_LAPTOP is not set CONFIG_HP_WMI=m # CONFIG_MSI_LAPTOP is not set # CONFIG_PANASONIC_LAPTOP is not set # CONFIG_COMPAL_LAPTOP is not set # CONFIG_SONY_LAPTOP is not set # CONFIG_IDEAPAD_ACPI is not set # CONFIG_THINKPAD_ACPI is not set # CONFIG_INTEL_MENLOW is not set # CONFIG_EEEPC_WMI is not set CONFIG_ACPI_WMI=m # CONFIG_MSI_WMI is not set CONFIG_ACPI_ASUS=m # CONFIG_TOPSTAR_LAPTOP is not set # CONFIG_ACPI_TOSHIBA is not set # CONFIG_TOSHIBA_BT_RFKILL is not set # CONFIG_ACPI_CMPC is not set CONFIG_INTEL_IPS=m # # Firmware Drivers # CONFIG_EDD=m # CONFIG_EDD_OFF is not set CONFIG_FIRMWARE_MEMMAP=y # CONFIG_DELL_RBU is not set # CONFIG_DCDBAS is not set CONFIG_DMIID=y # CONFIG_ISCSI_IBFT_FIND is not set # # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_XATTR=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y # CONFIG_EXT4_DEBUG is not set CONFIG_JBD=y CONFIG_JBD2=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set CONFIG_JFS_FS=m CONFIG_JFS_POSIX_ACL=y CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y # CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_QUOTA=y # CONFIG_QUOTA_NETLINK_INTERFACE is not set CONFIG_PRINT_QUOTA_WARNING=y # CONFIG_QUOTA_DEBUG is not set CONFIG_QUOTA_TREE=m # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=m CONFIG_QUOTACTL=y CONFIG_QUOTACTL_COMPAT=y # CONFIG_AUTOFS_FS is not set CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m CONFIG_CUSE=m # # Caches # CONFIG_FSCACHE=m CONFIG_FSCACHE_STATS=y # CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set # CONFIG_FSCACHE_OBJECT_LIST is not set CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set # CONFIG_CACHEFILES_HISTOGRAM is not set # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m CONFIG_UDF_NLS=y # # DOS/FAT/NT Filesystems # CONFIG_FAT_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_NTFS_FS=m # CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLBFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_CONFIGFS_FS=m CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set CONFIG_LOGFS=m # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=m # CONFIG_SQUASHFS_XATTR is not set # CONFIG_SQUASHFS_LZO is not set # CONFIG_SQUASHFS_EMBEDDED is not set CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y # CONFIG_NFS_V4_1 is not set # CONFIG_NFS_FSCACHE is not set # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y # CONFIG_NFSD is not set CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m CONFIG_RPCSEC_GSS_KRB5=m CONFIG_RPCSEC_GSS_SPKM3=m # CONFIG_SMB_FS is not set # CONFIG_CEPH_FS is not set CONFIG_CIFS=m CONFIG_CIFS_STATS=y # CONFIG_CIFS_STATS2 is not set # CONFIG_CIFS_WEAK_PW_HASH is not set CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y # CONFIG_CIFS_DEBUG2 is not set CONFIG_CIFS_DFS_UPCALL=y CONFIG_CIFS_FSCACHE=y CONFIG_CIFS_EXPERIMENTAL=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y CONFIG_ACORN_PARTITION=y # CONFIG_ACORN_PARTITION_CUMANA is not set # CONFIG_ACORN_PARTITION_EESOX is not set CONFIG_ACORN_PARTITION_ICS=y # CONFIG_ACORN_PARTITION_ADFS is not set # CONFIG_ACORN_PARTITION_POWERTEC is not set CONFIG_ACORN_PARTITION_RISCIX=y CONFIG_OSF_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_ATARI_PARTITION=y CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y CONFIG_MINIX_SUBPARTITION=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_UNIXWARE_DISKLABEL=y CONFIG_LDM_PARTITION=y # CONFIG_LDM_DEBUG is not set CONFIG_SGI_PARTITION=y CONFIG_ULTRIX_PARTITION=y CONFIG_SUN_PARTITION=y CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y # CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=m CONFIG_NLS_CODEPAGE_775=m CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_CODEPAGE_852=m CONFIG_NLS_CODEPAGE_855=m CONFIG_NLS_CODEPAGE_857=m CONFIG_NLS_CODEPAGE_860=m CONFIG_NLS_CODEPAGE_861=m CONFIG_NLS_CODEPAGE_862=m CONFIG_NLS_CODEPAGE_863=m CONFIG_NLS_CODEPAGE_864=m CONFIG_NLS_CODEPAGE_865=m CONFIG_NLS_CODEPAGE_866=m CONFIG_NLS_CODEPAGE_869=m CONFIG_NLS_CODEPAGE_936=m CONFIG_NLS_CODEPAGE_950=m CONFIG_NLS_CODEPAGE_932=m CONFIG_NLS_CODEPAGE_949=m CONFIG_NLS_CODEPAGE_874=m CONFIG_NLS_ISO8859_8=m CONFIG_NLS_CODEPAGE_1250=m CONFIG_NLS_CODEPAGE_1251=m CONFIG_NLS_ASCII=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_ISO8859_2=m CONFIG_NLS_ISO8859_3=m CONFIG_NLS_ISO8859_4=m CONFIG_NLS_ISO8859_5=m CONFIG_NLS_ISO8859_6=m CONFIG_NLS_ISO8859_7=m CONFIG_NLS_ISO8859_9=m CONFIG_NLS_ISO8859_13=m CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m CONFIG_DLM=m # CONFIG_DLM_DEBUG is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set # CONFIG_ENABLE_WARN_DEPRECATED is not set CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 CONFIG_MAGIC_SYSRQ=y # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_LOCKUP_DETECTOR is not set # CONFIG_HARDLOCKUP_DETECTOR is not set CONFIG_DETECT_HUNG_TASK=y # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_LOCK_ALLOC is not set # CONFIG_PROVE_LOCKING is not set # CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set CONFIG_STACKTRACE=y # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_WRITECOUNT is not set CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_DEBUG_CREDENTIALS is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y # CONFIG_SYSCTL_SYSCALL_CHECK is not set # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_FTRACE_SYSCALLS is not set CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set # CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_STACK_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_MMIOTRACE is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set # CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set CONFIG_HAVE_ARCH_KMEMCHECK=y # CONFIG_STRICT_DEVMEM is not set # CONFIG_X86_VERBOSE_BOOTUP is not set CONFIG_EARLY_PRINTK=y # CONFIG_EARLY_PRINTK_DBGP is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set # CONFIG_X86_PTDUMP is not set # CONFIG_DEBUG_RODATA is not set # CONFIG_DEBUG_NX_TEST is not set # CONFIG_IOMMU_DEBUG is not set # CONFIG_IOMMU_STRESS is not set CONFIG_HAVE_MMIOTRACE_SUPPORT=y CONFIG_IO_DELAY_TYPE_0X80=0 CONFIG_IO_DELAY_TYPE_0XED=1 CONFIG_IO_DELAY_TYPE_UDELAY=2 CONFIG_IO_DELAY_TYPE_NONE=3 CONFIG_IO_DELAY_0X80=y # CONFIG_IO_DELAY_0XED is not set # CONFIG_IO_DELAY_UDELAY is not set # CONFIG_IO_DELAY_NONE is not set CONFIG_DEFAULT_IO_DELAY_TYPE=0 # CONFIG_CPA_DEBUG is not set CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_DEBUG_PROC_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set # CONFIG_INTEL_TXT is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_DEFAULT_SECURITY="" CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m CONFIG_ASYNC_MEMCPY=m CONFIG_ASYNC_XOR=m CONFIG_ASYNC_PQ=m CONFIG_ASYNC_RAID6_RECOV=m # CONFIG_ASYNC_RAID6_TEST is not set CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_PCOMP=m CONFIG_CRYPTO_PCOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m # CONFIG_CRYPTO_PCRYPT is not set CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set # # Block modes # CONFIG_CRYPTO_CBC=m # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set CONFIG_CRYPTO_ECB=m # CONFIG_CRYPTO_LRW is not set CONFIG_CRYPTO_PCBC=m # CONFIG_CRYPTO_XTS is not set # # Hash modes # CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_VMAC is not set # # Digest # CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_CRC32C_INTEL is not set # CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set # # Ciphers # CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_AES_X86_64=m # CONFIG_CRYPTO_AES_NI_INTEL is not set # CONFIG_CRYPTO_ANUBIS is not set CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_BLOWFISH=m # CONFIG_CRYPTO_CAMELLIA is not set CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SALSA20_X86_64 is not set # CONFIG_CRYPTO_SEED is not set CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_TWOFISH_X86_64 is not set # # Compression # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m # # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_HAVE_KVM=y CONFIG_HAVE_KVM_IRQCHIP=y CONFIG_HAVE_KVM_EVENTFD=y CONFIG_KVM_APIC_ARCHITECTURE=y CONFIG_KVM_MMIO=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=m CONFIG_KVM_INTEL=m # CONFIG_KVM_AMD is not set CONFIG_VHOST_NET=m CONFIG_VIRTIO=m CONFIG_VIRTIO_RING=m CONFIG_VIRTIO_PCI=m CONFIG_VIRTIO_BALLOON=m # CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_RAID6_PQ=m CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=m CONFIG_CRC_ITU_T=y CONFIG_CRC32=y # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_LZO_COMPRESS=m CONFIG_LZO_DECOMPRESS=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_LZO=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m CONFIG_BTREE=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y Yours, Aki

2 1

[alsa-devel] [PATCH] ASoC: Delegate to hw specific read for volatile registers
by Dimitris Papastamos 22 Sep '10

22 Sep '10

Ensure that reads on volatile registers will correctly delegate to the bus specific read function. Signed-off-by: Dimitris Papastamos <dp(a)opensource.wolfsonmicro.com> --- sound/soc/soc-cache.c | 76 ++++++++++++++++++++++++++++++++----------------- 1 files changed, 50 insertions(+), 26 deletions(-) diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c index 6702a3d..c4f31b8 100644 --- a/sound/soc/soc-cache.c +++ b/sound/soc/soc-cache.c @@ -19,8 +19,15 @@ static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec, unsigned int reg) { u16 *cache = codec->reg_cache; - if (reg >= codec->driver->reg_cache_size) - return -1; + + if (reg >= codec->driver->reg_cache_size || + snd_soc_codec_volatile_register(codec, reg)) { + if (codec->cache_only) + return -1; + + return codec->hw_read(codec, reg); + } + return cache[reg]; } @@ -31,13 +38,12 @@ static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg, u8 data[2]; int ret; - BUG_ON(codec->driver->volatile_register); - data[0] = (reg << 4) | ((value >> 8) & 0x000f); data[1] = value & 0x00ff; - if (reg < codec->driver->reg_cache_size) - cache[reg] = value; + if (!snd_soc_codec_volatile_register(codec, reg) && + reg < codec->driver->reg_cache_size) + cache[reg] = value; if (codec->cache_only) { codec->cache_sync = 1; @@ -89,8 +95,15 @@ static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec, unsigned int reg) { u16 *cache = codec->reg_cache; - if (reg >= codec->driver->reg_cache_size) - return -1; + + if (reg >= codec->driver->reg_cache_size || + snd_soc_codec_volatile_register(codec, reg)) { + if (codec->cache_only) + return -1; + + return codec->hw_read(codec, reg); + } + return cache[reg]; } @@ -101,13 +114,12 @@ static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg, u8 data[2]; int ret; - BUG_ON(codec->driver->volatile_register); - data[0] = (reg << 1) | ((value >> 8) & 0x0001); data[1] = value & 0x00ff; - if (reg < codec->driver->reg_cache_size) - cache[reg] = value; + if (!snd_soc_codec_volatile_register(codec, reg) && + reg < codec->driver->reg_cache_size) + cache[reg] = value; if (codec->cache_only) { codec->cache_sync = 1; @@ -161,14 +173,13 @@ static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg, u8 *cache = codec->reg_cache; u8 data[2]; - BUG_ON(codec->driver->volatile_register); - reg &= 0xff; data[0] = reg; data[1] = value & 0xff; - if (reg < codec->driver->reg_cache_size) - cache[reg] = value; + if (!snd_soc_codec_volatile_register(codec, value) && + reg < codec->driver->reg_cache_size) + cache[reg] = value; if (codec->cache_only) { codec->cache_sync = 1; @@ -187,9 +198,16 @@ static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec, unsigned int reg) { u8 *cache = codec->reg_cache; + reg &= 0xff; - if (reg >= codec->driver->reg_cache_size) - return -1; + if (reg >= codec->driver->reg_cache_size || + snd_soc_codec_volatile_register(codec, reg)) { + if (codec->cache_only) + return -1; + + return codec->hw_read(codec, reg); + } + return cache[reg]; } @@ -344,8 +362,14 @@ static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec, u8 *cache = codec->reg_cache; reg &= 0xff; - if (reg >= codec->driver->reg_cache_size) - return -1; + if (reg >= codec->driver->reg_cache_size || + snd_soc_codec_volatile_register(codec, reg)) { + if (codec->cache_only) + return -1; + + return codec->hw_read(codec, reg); + } + return cache[reg]; } @@ -356,15 +380,14 @@ static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg, u8 data[3]; int ret; - BUG_ON(codec->driver->volatile_register); - data[0] = (reg >> 8) & 0xff; data[1] = reg & 0xff; data[2] = value; reg &= 0xff; - if (reg < codec->driver->reg_cache_size) - cache[reg] = value; + if (!snd_soc_codec_volatile_register(codec, reg) && + reg < codec->driver->reg_cache_size) + cache[reg] = value; if (codec->cache_only) { codec->cache_sync = 1; @@ -475,8 +498,9 @@ static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg, data[2] = (value >> 8) & 0xff; data[3] = value & 0xff; - if (reg < codec->driver->reg_cache_size) - cache[reg] = value; + if (!snd_soc_codec_volatile_register(codec, reg) && + reg < codec->driver->reg_cache_size) + cache[reg] = value; if (codec->cache_only) { codec->cache_sync = 1; -- 1.7.3

2 1

[alsa-devel] [PATCH] ASoC: Report error codes for card DAI instantiation failures
by Mark Brown 22 Sep '10

22 Sep '10

Also clean up the error print a bit. Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/soc-core.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index 7c64e03..5c58651 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -1568,7 +1568,8 @@ static void snd_soc_instantiate_card(struct snd_soc_card *card) for (i = 0; i < card->num_links; i++) { ret = soc_probe_dai_link(card, i); if (ret < 0) { - printk(KERN_ERR "asoc: failed to instanciate card %s\n", card->name); + pr_err("asoc: failed to instantiate card %s: %d\n", + card->name, ret); goto probe_dai_err; } } -- 1.7.1

2 1

[alsa-devel] [PATCH] ASoC: Select DMA driver for Samsung DAIs
by Mark Brown 22 Sep '10

22 Sep '10

Kconfig got smart enough to do dependencies through selects so let's make use of that. Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/s3c24xx/Kconfig | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/sound/soc/s3c24xx/Kconfig b/sound/soc/s3c24xx/Kconfig index 7d8235d..1142d3e 100644 --- a/sound/soc/s3c24xx/Kconfig +++ b/sound/soc/s3c24xx/Kconfig @@ -10,6 +10,7 @@ config SND_S3C24XX_SOC config SND_S3C24XX_SOC_I2S tristate select S3C2410_DMA + select SND_S3C_SOC_PCM config SND_S3C_I2SV2_SOC tristate @@ -18,16 +19,19 @@ config SND_S3C2412_SOC_I2S tristate select SND_S3C_I2SV2_SOC select S3C2410_DMA + select SND_S3C_SOC_PCM config SND_S3C64XX_SOC_I2S tristate select SND_S3C_I2SV2_SOC select S3C64XX_DMA + select SND_S3C_SOC_PCM config SND_S3C64XX_SOC_I2S_V4 tristate select SND_S3C_I2SV2_SOC select S3C64XX_DMA + select SND_S3C_SOC_PCM config SND_S3C_SOC_PCM tristate -- 1.7.1

4 4

Re: [alsa-devel] Spurious "Unable to find definition 'defaults.pcm.dmix.device'"
by Gavin Stark 21 Sep '10

21 Sep '10

Colin, thanks for the suggestion. I tried building and running from the current git HEAD version and still had the same problem. I also noticed that my app has been causing a core dump due to an infinite recursion in snd_config_searcha_hooks. I'm not sure what would cause both of these problems. I'm trying going back to stock packages on my system (Ubuntu 9.04) to see if a version incompatibility. Gavin Stark On Sep 20, 2010, at 1:41 PM, alsa-devel-request(a)alsa-project.org wrote: > Date: Mon, 20 Sep 2010 16:22:02 +0100 > From: Colin Guthrie <gmane(a)colin.guthr.ie> > Subject: Re: [alsa-devel] Spurious "Unable to find definition > 'defaults.pcm.dmix.device'" > To: alsa-devel(a)alsa-project.org > Message-ID: <i77u6q$2ma$1(a)dough.gmane.org> > Content-Type: text/plain; charset=UTF-8 > > 'Twas brillig, and Gavin Stark at 20/09/10 16:05 did gyre and gimble: >> I am using ALSA in a gstreamer project. When playing many videos >> (with audio) in the same application and the same gstreamer instance >> every once in a while (maybe once every 500 times) I will receive the >> following errors (in a call chain that passes through snd_pcm_open) >> >> confmisc.c:1286:snd_func_refer: alsalib error: Unable to find >> definition 'defaults.pcm.dmix.device' alsa >> conf.c:4154:_snd_config_evaluate: alsalib error: function >> snd_func_refer returned error: No such file or directory alsa >> conf.c:4633:snd_config_expand: alsalib error: Evaluate error: No such >> file or directory alsa pcm.c:2211:snd_pcm_open_noupdate: alsalib >> error: Unknown PCM default >> >> The next playback will be fine. Looking through the ALSA code it >> seems that the configuration data should be cached and re-used unless >> the number of config files changes, or the files themselves change >> (name, device, inode. mtime) So I am wonder why on one instance of >> snd_pcm_open I'd end up with this error but not on most previous or >> subsequent calls. >> >> All the ALSA configuration files are the defaults, I have no >> ~/.asoundrc, and I'm running version 1.0.23 > > I guess there is an outside chance that this could be some threading > race condition in the config stuff. > > Jaroslav recently fixed some threading issues in libalsa2 and config > stuff. Perhaps it's worth pulling across those changes to your alsa lib > to see if this is related? > > Can't remember the git commit #'s off hand, but git master of libalsa2 > is probably fine. > > > Long shot maybe but an relatively easy one to test. > > Col > > -- > > Colin Guthrie > gmane(at)colin.guthr.ie > http://colin.guthr.ie/ > > Day Job: > Tribalogic Limited [http://www.tribalogic.net/] > Open Source: > Mageia Contributor [http://www.mageia.org/] > PulseAudio Hacker [http://www.pulseaudio.org/] > Trac Hacker [http://trac.edgewall.org/] > > >

1 0

[alsa-devel] [PATCH] ASoC: Fix soc-cache buffer overflow bug
by Dimitris Papastamos 21 Sep '10

21 Sep '10

Make sure we stay within the cache boundaries when updating the register cache. Signed-off-by: Dimitris Papastamos <dp(a)opensource.wolfsonmicro.com> --- sound/soc/soc-cache.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c index 1228111..28bf1ff 100644 --- a/sound/soc/soc-cache.c +++ b/sound/soc/soc-cache.c @@ -203,8 +203,9 @@ static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg, data[1] = (value >> 8) & 0xff; data[2] = value & 0xff; - if (!snd_soc_codec_volatile_register(codec, reg)) - reg_cache[reg] = value; + if (!snd_soc_codec_volatile_register(codec, reg) + && reg < codec->driver->reg_cache_size) + reg_cache[reg] = value; if (codec->cache_only) { codec->cache_sync = 1; -- 1.7.3

3 3

[alsa-devel] [PATCH] ASoC: Remove extra rtd->dev.init_name assignment in soc_probe_dai_link
by Jarkko Nikula 21 Sep '10

21 Sep '10

rtd->dev.init_name is set twice in soc_probe_dai_link. I removed the first assignement from dai_link->stream_name since then there won't be sysfs name changes and usually dai_link->name seems to fit anyway better for a sysfs directory name. Signed-off-by: Jarkko Nikula <jhnikula(a)gmail.com> --- sound/soc/soc-core.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index 6001b7f..c8d1596 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -1451,7 +1451,6 @@ static int soc_probe_dai_link(struct snd_soc_card *card, int num) snd_soc_dapm_sync(codec); /* register the rtd device */ - rtd->dev.init_name = rtd->dai_link->stream_name; rtd->dev.release = rtd_release; rtd->dev.init_name = dai_link->name; ret = device_register(&rtd->dev); -- 1.7.1

3 2

[alsa-devel] alsa-kernel repository corrupted?
by Andy Owen 21 Sep '10

21 Sep '10

Hi, I'm trying to put together a patch for the ca0106 driver, and I'm having trouble cloning the alsa-kernel repository. I've tried it a few times from different places and while it is downloading I get "fatal: delta size changed" when it is partially through. Here are two runs of git clone with slightly different output (consecutive runs on the same computer): % git clone git://git.alsa-project.org/alsa-kernel.git alsa-kernel Initialized empty Git repository in /home/andy/src/alsa-kernel/.git/ remote: Counting objects: 1708307, done. remote: Compressing objects: 100% (313659/313659), done. remote: fatal: delta size changed remote: aborting due to possible repository corruption on the remote side. fatal: early EOF fatal: index-pack failed % git clone git://git.alsa-project.org/alsa-kernel.git alsa-kernel Initialized empty Git repository in /home/andy/src/alsa-kernel/.git/ remote: Counting objects: 1708307, done. remote: Compressing objects: 100% (313659/313659), done. remote: fatal: delta size changed remote: aborting due to possible repository corruption on the remote side. fatal: early EOFs: 15% (260156/1708307), 157.79 MiB | 47 KiB/s fatal: index-pack failed Does anyone else have any luck getting the repo? Andy

2 1

[PATCH] ALSA: ca0106 - add Sound Blaster 5.1vx info.
by Andy Owen 21 Sep '10

21 Sep '10

Signed-off-by: Andy Owen <andy-alsa(a)ultra-premium.com> --- sound/pci/ca0106/ca0106_main.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/sound/pci/ca0106/ca0106_main.c b/sound/pci/ca0106/ca0106_main.c index 8e69620..6dc9a5d 100644 --- a/sound/pci/ca0106/ca0106_main.c +++ b/sound/pci/ca0106/ca0106_main.c @@ -239,6 +239,16 @@ static struct snd_ca0106_details ca0106_chip_details[] = { .gpio_type = 1, .i2c_adc = 1, .spi_dac = 1 } , + /* Sound Blaster 5.1vx + * Tested: Playback on front, rear, center/lfe speakers + * Not-Tested: Capture + */ + { .serial = 0x10041102, + .name = "Sound Blaster 5.1vx [SB1070]", + .gpio_type = 1, + .i2c_adc = 0, + .spi_dac = 1 + } , /* MSI K8N Diamond Motherboard with onboard SB Live 24bit without AC97 */ /* SB0438 * CTRL:CA0106-DAT -- 1.7.0.4 --=-g8ouaCT8rh3B1kCcOO9M--

1 0

[alsa-devel] [PATCH] ASoC: Fix merge issue with WM8962 control addition
by Mark Brown 21 Sep '10

21 Sep '10

Let's not add the core controls twice. Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm8962.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 28adc6c..c4deea1 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -1845,8 +1845,6 @@ static int wm8962_probe(struct snd_soc_codec *codec) wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU; wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU; - snd_soc_add_controls(codec, wm8962_snd_controls, - ARRAY_SIZE(wm8962_snd_controls)); wm8962_add_widgets(codec); wm8962_init_beep(codec); -- 1.7.1

2 1

[alsa-devel] [PATCH] ASoC: Report error code when failing to add controls
by Mark Brown 21 Sep '10

21 Sep '10

Helps with diagnostics. Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/soc-core.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index 8d8c5cd..7c64e03 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -1983,8 +1983,8 @@ int snd_soc_add_controls(struct snd_soc_codec *codec, const struct snd_kcontrol_new *control = &controls[i]; err = snd_ctl_add(card, snd_soc_cnew(control, codec, NULL)); if (err < 0) { - dev_err(codec->dev, "%s: Failed to add %s\n", - codec->name, control->name); + dev_err(codec->dev, "%s: Failed to add %s: %d\n", + codec->name, control->name, err); return err; } } -- 1.7.1

2 1

[alsa-devel] [PATCH] ASoC: Prototype s3c64xx_i2s_get_clock()
by Mark Brown 21 Sep '10

21 Sep '10

So machine drivers can see the declaration. Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/s3c24xx/s3c64xx-i2s.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/sound/soc/s3c24xx/s3c64xx-i2s.h b/sound/soc/s3c24xx/s3c64xx-i2s.h index 19bd444..de4075d 100644 --- a/sound/soc/s3c24xx/s3c64xx-i2s.h +++ b/sound/soc/s3c24xx/s3c64xx-i2s.h @@ -36,5 +36,6 @@ struct clk; (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ SNDRV_PCM_FMTBIT_S24_LE) +struct clk *s3c64xx_i2s_get_clock(struct snd_soc_dai *dai); #endif /* __SND_SOC_S3C24XX_S3C64XX_I2S_H */ -- 1.7.1

3 3

[alsa-devel] proposed MPD16 latency workaround
by Krzysztof Foltman 21 Sep '10

21 Sep '10

Hi all, I've played with USB MIDI driver and MPD16 a bit more. The problem is definitely triggered by submitting URBs on the configuration input endpoint - when these are killed, the latency disappears. Disabling the configuration port works, but is a bit heavy-handed, so I've implemented a workaround: initially, the URBs for the input configuration endpoint are not submitted until two conditions are met: i) the control port is actually open (I check that using input_triggered bitmask) ii) the driver is switched into config mode by sending a special SysEx message to the output port (which is intercepted by the driver and used to set a flag). This is to prevent programs that open all the MIDI ports in the system (JACK daemon with ALSA MIDI driver, a2jmidid etc.) from starting unwanted communication with configuration endpoints. Any time one of these conditions is changed, the driver may either submit the URBs or kill them or do nothing - depending on the difference between expected and current "queuing state" of the URBs. This logic is only used for MPD16, for all the other devices the driver always submit their input URBs, no matter if any input is actually wanted or not. The attached diff is relative to the Ubuntu 2.6.35 kernel, but I'm mostly interested in the review of the general approach - I have some doubts about thread-safety of calling snd_usbmidi_input_update_ep from send function and about the elegance of the SysEx approach (vs. ioctl or something else). If the approach is not too icky and doesn't have hidden flaws, I can try to create a diff relative to alsa-kernel or some other tree. Any comments? Krzysztof

2 5

[alsa-devel] [PATCH] ALSA: hda - Add Dell Latitude E6400 model quirk
by Luke Yelavich 21 Sep '10

21 Sep '10

From: Luke Yelavich <luke.yelavich(a)canonical.com> BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/643891 Set the Dell Latitude E6400 (1028:0233) SSID to use AD1984_DELL_DESKTOP Cc: stable(a)kernel.org Signed-off-by: Luke Yelavich <luke.yelavich(a)canonical.com> --- sound/pci/hda/patch_analog.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/sound/pci/hda/patch_analog.c b/sound/pci/hda/patch_analog.c index 05db1cf..507523d 100644 --- a/sound/pci/hda/patch_analog.c +++ b/sound/pci/hda/patch_analog.c @@ -3642,6 +3642,7 @@ static struct snd_pci_quirk ad1984_cfg_tbl[] = { /* Lenovo Thinkpad T61/X61 */ SND_PCI_QUIRK_VENDOR(0x17aa, "Lenovo Thinkpad", AD1984_THINKPAD), SND_PCI_QUIRK(0x1028, 0x0214, "Dell T3400", AD1984_DELL_DESKTOP), + SND_PCI_QUIRK(0x1028, 0x0233, "Dell Latitude E6400", AD1984_DELL_DESKTOP), {} }; -- 1.7.1

2 1

[alsa-devel] [PATCH] hdmi - fix surround41 channel mapping
by Wu Fengguang 21 Sep '10

21 Sep '10

From: Jerry Zhou <jerry.zhou(a)intel.com> Channel 2 and channel 3 were all wrongly mapped to HDMI slot 4. This shows up as a bug that one channel is "lost" when playing in surround41 mode. Signed-off-by: Jerry Zhou <jerry.zhou(a)intel.com> Signed-off-by: Wu Fengguang <fengguang.wu(a)intel.com> --- sound/pci/hda/patch_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- sound-2.6.orig/sound/pci/hda/patch_hdmi.c 2010-09-21 11:20:59.000000000 +0800 +++ sound-2.6/sound/pci/hda/patch_hdmi.c 2010-09-21 14:26:55.000000000 +0800 @@ -191,11 +191,11 @@ static int hdmi_channel_mapping[0x32][8] /* surround40 */ [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, /* 4ch */ [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, /* surround41 */ - [0x09] = { 0x00, 0x11, 0x24, 0x34, 0x43, 0xf2, 0xf6, 0xf7 }, + [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 }, /* surround50 */ [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, /* surround51 */ [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, /* 7.1 */

2 1

[alsa-devel] [PATCH] alsa: hdmi - support infoframe for DisplayPort
by Wu Fengguang 21 Sep '10

21 Sep '10

DisplayPort works mostly in the same way as HDMI, except that it expects a slightly different audio infoframe format. Citations from "HDA036-A: Display Port Support and HDMI Miscellaneous Corrections": The HDMI specification defines a data island packet with a header of 4 bytes (3 bytes content + 1 byte ECC) and packet body of 32 bytes (28 bytes content and 4 bytes ECC). Display Port specification on the other hand defines a data island packet (secondary data packet) with header of 4 bytes protected by 4 bytes of parity, and data of theoretically up to 1024 bytes with each 16 bytes chunk of data protected by 4 bytes of parity. Note that the ECC or parity bytes are not present in the DIP content populated by software and are hardware generated. It tests DP connection based on the ELD conn_type field, which will be set by the graphics driver and can be overriden manually by users through the /proc/asound/card0/eld* interface. The DP infoframe is tested OK on Intel SandyBridge/CougarPoint platform. Signed-off-by: Wu Fengguang <fengguang.wu(a)intel.com> --- sound/pci/hda/patch_hdmi.c | 110 +++++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 37 deletions(-) Takashi: half of the patch is harmless code refactor. The real changes happen in the first and last chunks. --- sound-2.6.orig/sound/pci/hda/patch_hdmi.c 2010-09-21 09:41:46.000000000 +0800 +++ sound-2.6/sound/pci/hda/patch_hdmi.c 2010-09-21 11:20:59.000000000 +0800 @@ -82,17 +82,29 @@ struct hdmi_spec { struct hdmi_audio_infoframe { u8 type; /* 0x84 */ u8 ver; /* 0x01 */ u8 len; /* 0x0a */ - u8 checksum; /* PB0 */ + u8 checksum; + u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ u8 SS01_SF24; u8 CXT04; u8 CA; u8 LFEPBL01_LSV36_DM_INH7; - u8 reserved[5]; /* PB6 - PB10 */ +}; + +struct dp_audio_infoframe { + u8 type; /* 0x84 */ + u8 len; /* 0x1b */ + u8 ver; /* 0x11 << 2 */ + + u8 CC02_CT47; /* match with HDMI infoframe from this on */ + u8 SS01_SF24; + u8 CXT04; + u8 CA; + u8 LFEPBL01_LSV36_DM_INH7; }; /* * CEA speaker placement: * @@ -192,11 +204,11 @@ static int hdmi_channel_mapping[0x32][8] /* * This is an ordered list! * * The preceding ones have better chances to be selected by - * hdmi_setup_channel_allocation(). + * hdmi_channel_allocation(). */ static struct cea_channel_speaker_allocation channel_allocations[] = { /* channel: 7 6 5 4 3 2 1 0 */ { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, /* 2.1 */ @@ -369,18 +381,18 @@ static void init_channel_allocations(voi * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask * spk_mask => (channel_allocations[]) => ai->CA * * TODO: it could select the wrong CA from multiple candidates. */ -static int hdmi_setup_channel_allocation(struct hda_codec *codec, hda_nid_t nid, - struct hdmi_audio_infoframe *ai) +static int hdmi_channel_allocation(struct hda_codec *codec, hda_nid_t nid, + int channels) { struct hdmi_spec *spec = codec->spec; struct hdmi_eld *eld; int i; + int ca = 0; int spk_mask = 0; - int channels = 1 + (ai->CC02_CT47 & 0x7); char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; /* * CA defaults to 0 for basic stereo audio */ @@ -414,20 +426,20 @@ static int hdmi_setup_channel_allocation /* search for the first working match in the CA table */ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { if (channels == channel_allocations[i].channels && (spk_mask & channel_allocations[i].spk_mask) == channel_allocations[i].spk_mask) { - ai->CA = channel_allocations[i].ca_index; + ca = channel_allocations[i].ca_index; break; } } snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf)); snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n", - ai->CA, channels, buf); + ca, channels, buf); - return ai->CA; + return ca; } static void hdmi_debug_channel_mapping(struct hda_codec *codec, hda_nid_t pin_nid) { @@ -445,14 +457,13 @@ static void hdmi_debug_channel_mapping(s } static void hdmi_setup_channel_mapping(struct hda_codec *codec, hda_nid_t pin_nid, - struct hdmi_audio_infoframe *ai) + int ca) { int i; - int ca = ai->CA; int err; if (hdmi_channel_mapping[ca][1] == 0) { for (i = 0; i < channel_allocations[ca].channels; i++) hdmi_channel_mapping[ca][i] = i | (i << 4); @@ -545,57 +556,53 @@ static void hdmi_clear_dip_buffers(struc i, size, j); } #endif } -static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *ai) +static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) { - u8 *bytes = (u8 *)ai; + u8 *bytes = (u8 *)hdmi_ai; u8 sum = 0; int i; - ai->checksum = 0; + hdmi_ai->checksum = 0; - for (i = 0; i < sizeof(*ai); i++) + for (i = 0; i < sizeof(*hdmi_ai); i++) sum += bytes[i]; - ai->checksum = -sum; + hdmi_ai->checksum = -sum; } static void hdmi_fill_audio_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, - struct hdmi_audio_infoframe *ai) + u8 *dip, int size) { - u8 *bytes = (u8 *)ai; int i; hdmi_debug_dip_size(codec, pin_nid); hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ - hdmi_checksum_audio_infoframe(ai); - hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); - for (i = 0; i < sizeof(*ai); i++) - hdmi_write_dip_byte(codec, pin_nid, bytes[i]); + for (i = 0; i < size; i++) + hdmi_write_dip_byte(codec, pin_nid, dip[i]); } static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, - struct hdmi_audio_infoframe *ai) + u8 *dip, int size) { - u8 *bytes = (u8 *)ai; u8 val; int i; if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) != AC_DIPXMIT_BEST) return false; hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); - for (i = 0; i < sizeof(*ai); i++) { + for (i = 0; i < size; i++) { val = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_DATA, 0); - if (val != bytes[i]) + if (val != dip[i]) return false; } return true; } @@ -603,35 +610,64 @@ static bool hdmi_infoframe_uptodate(stru static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid, struct snd_pcm_substream *substream) { struct hdmi_spec *spec = codec->spec; hda_nid_t pin_nid; + int channels = substream->runtime->channels; + int ca; int i; - struct hdmi_audio_infoframe ai = { - .type = 0x84, - .ver = 0x01, - .len = 0x0a, - .CC02_CT47 = substream->runtime->channels - 1, - }; + u8 ai[max(sizeof(struct hdmi_audio_infoframe), + sizeof(struct dp_audio_infoframe))]; - hdmi_setup_channel_allocation(codec, nid, &ai); + ca = hdmi_channel_allocation(codec, nid, channels); for (i = 0; i < spec->num_pins; i++) { if (spec->pin_cvt[i] != nid) continue; if (!spec->sink_eld[i].monitor_present) continue; pin_nid = spec->pin[i]; - if (!hdmi_infoframe_uptodate(codec, pin_nid, &ai)) { + + memset(ai, 0, sizeof(ai)); + if (spec->sink_eld[i].conn_type == 0) { /* HDMI */ + struct hdmi_audio_infoframe *hdmi_ai; + + hdmi_ai = (struct hdmi_audio_infoframe *)ai; + hdmi_ai->type = 0x84; + hdmi_ai->ver = 0x01; + hdmi_ai->len = 0x0a; + hdmi_ai->CC02_CT47 = channels - 1; + hdmi_checksum_audio_infoframe(hdmi_ai); + } else if (spec->sink_eld[i].conn_type == 1) { /* DisplayPort */ + struct dp_audio_infoframe *dp_ai; + + dp_ai = (struct dp_audio_infoframe *)ai; + dp_ai->type = 0x84; + dp_ai->len = 0x1b; + dp_ai->ver = 0x11 << 2; + dp_ai->CC02_CT47 = channels - 1; + } else { + snd_printd("HDMI: unknown connection type at pin %d\n", + pin_nid); + continue; + } + + /* + * sizeof(ai) is used instead of sizeof(*hdmi_ai) or + * sizeof(*dp_ai) to avoid partial match/update problems when + * the user switches between HDMI/DP monitors. + */ + if (!hdmi_infoframe_uptodate(codec, pin_nid, ai, sizeof(ai))) { snd_printdd("hdmi_setup_audio_infoframe: " "cvt=%d pin=%d channels=%d\n", nid, pin_nid, - substream->runtime->channels); - hdmi_setup_channel_mapping(codec, pin_nid, &ai); + channels); + hdmi_setup_channel_mapping(codec, pin_nid, ca); hdmi_stop_infoframe_trans(codec, pin_nid); - hdmi_fill_audio_infoframe(codec, pin_nid, &ai); + hdmi_fill_audio_infoframe(codec, pin_nid, + ai, sizeof(ai)); hdmi_start_infoframe_trans(codec, pin_nid); } } }

2 1

[alsa-devel] [PATCH 0/5 v2] ASoC: fsi: DMA support 1st step
by Kuninori Morimoto 20 Sep '10

20 Sep '10

Dear Mark, Liam These patches are v2 of 1st step for DMA support of FSI driver Kuninori Morimoto (5): ASoC: fsi: Add fsi_dma_get_area ASoC: fsi: modify noisy comment out ASoC: fsi: Add fsi_dma_soft_push/pop function ASoC: fsi: modify variable name to easy to understand ASoC: fsi: merge fsi_data_push/pop to fsi_fifo_data_ctrl 2nd patch modify noisy comment out which Liam said. Best regards -- Kuninori Morimoto

2 7

[alsa-devel] [PATCH] ASoC: Fix WM8978/migor driver name conflict
by Mark Brown 20 Sep '10

20 Sep '10

Standardise on 'wm8978' as the name for the CODEC. Reported-by: Guennadi Liakhovetski <g.liakhovetski(a)gmx.de> Signed-off-by: Mark Brown <broonie(a)opensource.wolfsonmicro.com> --- sound/soc/codecs/wm8978.c | 2 +- sound/soc/sh/migor.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c index 676a430..13b979a 100644 --- a/sound/soc/codecs/wm8978.c +++ b/sound/soc/codecs/wm8978.c @@ -1038,7 +1038,7 @@ MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id); static struct i2c_driver wm8978_i2c_driver = { .driver = { - .name = "WM8978-codec", + .name = "wm8978", .owner = THIS_MODULE, }, .probe = wm8978_i2c_probe, diff --git a/sound/soc/sh/migor.c b/sound/soc/sh/migor.c index f462017..ac6c49c 100644 --- a/sound/soc/sh/migor.c +++ b/sound/soc/sh/migor.c @@ -156,7 +156,7 @@ static struct snd_soc_dai_link migor_dai = { .cpu_dai_name = "siu-i2s-dai", .codec_dai_name = "wm8978-hifi", .platform_name = "siu-pcm-audio", - .codec_name = "wm8978-codec.0-001a", + .codec_name = "wm8978.0-001a", .ops = &migor_dai_ops, .init = migor_dai_init, }; -- 1.7.1

2 1

[alsa-devel] [PATCHv2 0/4] ASoC: tlv320aic3x: Add dynamic regulator control
by Jarkko Nikula 20 Sep '10

20 Sep '10

Hi I named this set as v2 since aic3x soc-cache conversion was done between v1 and this. Set goes on top of my previous aic3x one liner: http://mailman.alsa-project.org/pipermail/alsa-devel/2010-September/031749.… -- Jarkko

3 9

[alsa-devel] Creative XFi not working CA0110 IBG
by Hans-Juergen Lange 20 Sep '10

20 Sep '10

Hello, I did make the failure to not check before buy, but because the last problem reports are from about a year ago, I think the card should work. -- from lspci 86:00.0 Audio device [0403]: Creative Labs [SB X-Fi Xtreme Audio] CA0110-IBG [1102:0009] Subsystem: Creative Labs Device [1102:0018] Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B+ DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0100000 (32-bit, non-prefetchable) [size=16K] Capabilities: [dc] Power Management version 3 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Kernel modules: snd-hda-intel -- The kernel is a 64-Bit linux-2.6.33.2 original unpatched from kernel.org The mainboard is a Tyan S4985E. I dont want to fill up the message with boot log and all that stuff before there is a need. I am willing to help to find the problem in nearly any way because this is my workstation and I do need the PCI slot for some other purpose so I do want to get this card working. the alsa driver snd-hda-intel gives the following messages. [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 [ 3361.622125] hda-intel: spurious response 0x0:0x0, last cmd=0x000000 and with a quick look into the kernel I would think that the driver has a wrong idea about the interrupts received and the work that has to be done. More Infos infos if needed. Any help would be great. BR Hans-Juergen Lange

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[alsa-devel] [PATCH 0/5] fix SIU and Migo-R sound for 2.6.37
by Guennadi Liakhovetski 20 Sep '10

20 Sep '10

Conversion to the multi-component design has broken the SIU driver and its users. This patch series fixes the breakages. All patches against next/master, but one of them (#4) shall also go into 2.6.36. Thanks Guennadi --- Guennadi Liakhovetski, Ph.D. Freelance Open-Source Software Developer http://www.open-technology.de/

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[alsa-devel] [PATCH] ASoC: tlv320aic3x: Add virtual output pin Detection
by Jarkko Nikula 20 Sep '10

20 Sep '10

Purpose of this virtual Detection pin is to keep codec bias on whenever the GPIO or jack detection features are needed. Jack detection needs a mic bias so machine drivers can construct a following route for instance for keeping the path and codec bias on: "Input Jack" -> "Mic Bias xV" -> "Detection" -> detection block inside codec. For the GPIO the machine driver can force the pin on with snd_soc_dapm_force_enable_pin. Signed-off-by: Jarkko Nikula <jhnikula(a)gmail.com> --- PLL is activated when in SND_SOC_BIAS_PREPARE or _ON so it could be running but I have a vague impression that it's active only when ADC or DAC is on. I don't have at the moment possibility to measure it and don't want to move it to DAPM either before doing some oscilloscope and pop & clicks measurements. Current consumption anyway doesn't differ between standby and on when there is no active stream and other widgets are off. --- sound/soc/codecs/tlv320aic3x.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 7b5f159..6190351 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -605,6 +605,14 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { SND_SOC_DAPM_INPUT("LINE1R"), SND_SOC_DAPM_INPUT("LINE2L"), SND_SOC_DAPM_INPUT("LINE2R"), + + /* + * Virtual output pin to detection block inside codec. This can be + * used to keep codec bias on if gpio or detection features are needed. + * Force pin on or construct a path with an input jack and mic bias + * widgets. + */ + SND_SOC_DAPM_OUTPUT("Detection"), }; static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { -- 1.7.1

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[alsa-devel] ASoC update for 2.6.36
by Mark Brown 20 Sep '10

20 Sep '10

The following changes since commit 708fafb3c54039caa5dadc8e9d2dfd999f88f190: ASoC: soc-core: fix debugfs_pop_time file permissions (2010-08-27 19:58:40 +0100) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6.git for-2.6.36 Guennadi Liakhovetski (1): ASoC: fix clkdev API usage in sh/migor.c sound/soc/sh/migor.c | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-)

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[alsa-devel] Unifying sound/pci/hda/patch_*hdmi.c
by Takashi Iwai 19 Sep '10

19 Sep '10

Hi, the below is a patch for unifying three patch_*hdmi.c into a single file. I'd like to push this to 2.6.37, so please review, especially whether it can break Nvidia hardware (since I have no h/w available). In future, we can reduce ATI- and Nvidia-specific codes gradually after confirming the generic parser works. The patch is found in sound-unstable git tree, too. The corresponding alsa-driver-unstable tarball can be used for external builds. thanks, Takashi

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