April 2009 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCH v2 1/6] ARM: DaVinci: ASoC: Add mcasp support for DM646x
by Naresh Medisetty 17 Apr '09

17 Apr '09

From: Naresh.Medisetty <naresh(a)ti.com> Adds driver support for the two instances of McASP on TI's DM646x. The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio application. (http://www.ti.com/litv/pdf/spruer1b). There are two instances of McASP on DM646x. The McASP0 module includes up to 4 serializers that can be individually enabled to either transmit or receive in different modes. The McASP1 module is limited with only 1 pinned-out serializer that can be enabled to only transmit in DIT mode (neither receiving in any mode nor transmitting in either Burst or TDM mode is supported). The codec on the DM646x EVM is AIC32 which is connected to Serializer0 and Serializer1 of McASP0. The McASP0 consists of transmit and receive sections that may operate synchronized, or completely independently with separate master clocks, bit clocks, and frame syncs, and using different transmit modes with different bit-stream formats. Signed-off-by: Steve Chen <schen(a)mvista.com> Signed-off-by: Pavel Kiryukhin <pkiryukhin(a)ru.mvista.com> Signed-off-by: Naresh Medisetty <naresh(a)ti.com> --- This patch applies against ALSA mainline - that's the topic/asoc branch of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6.git sound/soc/davinci/Kconfig | 15 +- sound/soc/davinci/Makefile | 3 + sound/soc/davinci/davinci-i2s-mcasp.c | 890 +++++++++++++++++++++++++++++++++ sound/soc/davinci/davinci-i2s-mcasp.h | 56 ++ sound/soc/davinci/davinci-pcm.h | 17 +- 5 files changed, 972 insertions(+), 9 deletions(-) create mode 100644 sound/soc/davinci/davinci-i2s-mcasp.c create mode 100644 sound/soc/davinci/davinci-i2s-mcasp.h diff --git a/sound/soc/davinci/Kconfig b/sound/soc/davinci/Kconfig index bd7392c..0ae84d4 100644 --- a/sound/soc/davinci/Kconfig +++ b/sound/soc/davinci/Kconfig @@ -9,6 +9,9 @@ config SND_DAVINCI_SOC config SND_DAVINCI_SOC_I2S tristate +config SND_DAVINCI_SOC_I2S_MCASP + tristate + config SND_DAVINCI_SOC_EVM tristate "SoC Audio support for DaVinci EVM" depends on SND_DAVINCI_SOC && MACH_DAVINCI_EVM @@ -16,7 +19,17 @@ config SND_DAVINCI_SOC_EVM select SND_SOC_TLV320AIC3X help Say Y if you want to add support for SoC audio on TI - DaVinci EVM platform. + DaVinci DM6446 or DM355 EVM platforms. + +config SND_DM6467_SOC_EVM + tristate "SoC Audio support for DaVinci DM6467 EVM" + depends on SND_DAVINCI_SOC && MACH_DAVINCI_DM6467_EVM + select SND_DAVINCI_SOC_I2S_MCASP + select SND_SOC_TLV320AIC3X + help + Say Y if you want to add support for SoC audio on TI + DaVinci DM6467 EVM platform. + config SND_DAVINCI_SOC_SFFSDR tristate "SoC Audio support for SFFSDR" diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile index ca8bae1..152d59c 100644 --- a/sound/soc/davinci/Makefile +++ b/sound/soc/davinci/Makefile @@ -1,13 +1,16 @@ # DAVINCI Platform Support snd-soc-davinci-objs := davinci-pcm.o snd-soc-davinci-i2s-objs := davinci-i2s.o +snd-soc-davinci-i2s-mcasp-objs:= davinci-i2s-mcasp.o obj-$(CONFIG_SND_DAVINCI_SOC) += snd-soc-davinci.o obj-$(CONFIG_SND_DAVINCI_SOC_I2S) += snd-soc-davinci-i2s.o +obj-$(CONFIG_SND_DAVINCI_SOC_I2S_MCASP) += snd-soc-davinci-i2s-mcasp.o # DAVINCI Machine Support snd-soc-evm-objs := davinci-evm.o snd-soc-sffsdr-objs := davinci-sffsdr.o obj-$(CONFIG_SND_DAVINCI_SOC_EVM) += snd-soc-evm.o +obj-$(CONFIG_SND_DM6467_SOC_EVM) += snd-soc-evm.o obj-$(CONFIG_SND_DAVINCI_SOC_SFFSDR) += snd-soc-sffsdr.o diff --git a/sound/soc/davinci/davinci-i2s-mcasp.c b/sound/soc/davinci/davinci-i2s-mcasp.c new file mode 100644 index 0000000..5e9ba49 --- /dev/null +++ b/sound/soc/davinci/davinci-i2s-mcasp.c @@ -0,0 +1,890 @@ +/* + * ALSA SoC I2S (McASP) Audio Layer for TI DAVINCI processor + * + * Author: Nirmal Pandey <n-pandey(a)ti.com>, + * Suresh Rajashekara <suresh.r(a)ti.com> + * Steve Chen, <schen@.mvista.com> + * + * Copyright: (C) 2009 MontaVista Software, Inc., <source(a)mvista.com> + * Copyright: (C) 2009 Texas Instruments, India + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/initval.h> +#include <sound/soc.h> + +#include "davinci-pcm.h" +#include "davinci-i2s-mcasp.h" + +/* + * McASP register definitions + */ +#define DAVINCI_MCASP_PID_REG 0x00 +#define DAVINCI_MCASP_PWREMUMGT_REG 0x04 + +#define DAVINCI_MCASP_PFUNC_REG 0x10 +#define DAVINCI_MCASP_PDIR_REG 0x14 +#define DAVINCI_MCASP_PDOUT_REG 0x18 +#define DAVINCI_MCASP_PDSET_REG 0x1c + +#define DAVINCI_MCASP_PDCLR_REG 0x20 + +#define DAVINCI_MCASP_TLGC_REG 0x30 +#define DAVINCI_MCASP_TLMR_REG 0x34 + +#define DAVINCI_MCASP_GBLCTL_REG 0x44 +#define DAVINCI_MCASP_AMUTE_REG 0x48 +#define DAVINCI_MCASP_LBCTL_REG 0x4c + +#define DAVINCI_MCASP_TXDITCTL_REG 0x50 + +#define DAVINCI_MCASP_GBLCTLR_REG 0x60 +#define DAVINCI_MCASP_RXMASK_REG 0x64 +#define DAVINCI_MCASP_RXFMT_REG 0x68 +#define DAVINCI_MCASP_RXFMCTL_REG 0x6c + +#define DAVINCI_MCASP_ACLKRCTL_REG 0x70 +#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74 +#define DAVINCI_MCASP_RXTDM_REG 0x78 +#define DAVINCI_MCASP_EVTCTLR_REG 0x7c + +#define DAVINCI_MCASP_RXSTAT_REG 0x80 +#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84 +#define DAVINCI_MCASP_RXCLKCHK_REG 0x88 +#define DAVINCI_MCASP_REVTCTL_REG 0x8c + +#define DAVINCI_MCASP_GBLCTLX_REG 0xa0 +#define DAVINCI_MCASP_TXMASK_REG 0xa4 +#define DAVINCI_MCASP_TXFMT_REG 0xa8 +#define DAVINCI_MCASP_TXFMCTL_REG 0xac + +#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0 +#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4 +#define DAVINCI_MCASP_TXTDM_REG 0xb8 +#define DAVINCI_MCASP_EVTCTLX_REG 0xbc + +#define DAVINCI_MCASP_TXSTAT_REG 0xc0 +#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4 +#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8 +#define DAVINCI_MCASP_XEVTCTL_REG 0xcc + +/* Left (even TDM Slot) Channel Status Register File*/ +#define DAVINCI_MCASP_DITCSRA_REG 0x100 +/* Right (odd TDM slot) Channel Status RegisterFile*/ +#define DAVINCI_MCASP_DITCSRB_REG 0x118 +/* Left (even TDM slot) User Data Register File */ +#define DAVINCI_MCASP_DITUDRA_REG 0x130 +/* Right (odd TDM Slot) User Data Register File */ +#define DAVINCI_MCASP_DITUDRB_REG 0x148 + +/* Serializer n Control Register */ +#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180 +#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \ + (n << 2)) + +/* Transmit Buffer for Serializer n */ +#define DAVINCI_MCASP_TXBUF_REG 0x200 +/* Receive Buffer for Serializer n */ +#define DAVINCI_MCASP_RXBUF_REG 0x280 + + +/* + * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management + * Register Bits + */ +#define MCASP_FREE BIT(0) +#define MCASP_SOFT BIT(1) + +/* + * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits + */ +#define AXR(n) (1<<n) +#define PFUNC_AMUTE BIT(25) +#define ACLKX BIT(26) +#define AHCLKX BIT(27) +#define AFSX BIT(28) +#define ACLKR BIT(29) +#define AHCLKR BIT(30) +#define AFSR BIT(31) + +/* + * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits + */ +#define AXR(n) (1<<n) +#define PDIR_AMUTE BIT(25) +#define ACLKX BIT(26) +#define AHCLKX BIT(27) +#define AFSX BIT(28) +#define ACLKR BIT(29) +#define AHCLKR BIT(30) +#define AFSR BIT(31) + +/* + * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits + */ +#define DITEN BIT(0) /* Transmit DIT mode enable/disable */ +#define VA BIT(2) +#define VB BIT(3) + +/* + * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits + */ +#define TXROT(val) (val) +#define TXSEL BIT(3) +#define TXSSZ(val) (val<<4) +#define TXPBIT(val) (val<<8) +#define TXPAD(val) (val<<13) +#define TXORD BIT(15) +#define FSXDLY(val) (val<<16) + +/* + * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits + */ +#define RXROT(val) (val) +#define RXSEL BIT(3) +#define RXSSZ(val) (val<<4) +#define RXPBIT(val) (val<<8) +#define RXPAD(val) (val<<13) +#define RXORD BIT(15) +#define FSRDLY(val) (val<<16) + +/* + * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits + */ +#define FSXPOL BIT(0) +#define AFSXE BIT(1) +#define FSXDUR BIT(4) +#define FSXMOD(val) (val<<7) + +/* + * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits + */ +#define FSRPOL BIT(0) +#define AFSRE BIT(1) +#define FSRDUR BIT(4) +#define FSRMOD(val) (val<<7) + +/* + * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits + */ +#define ACLKXDIV(val) (val) +#define ACLKXE BIT(5) +#define TX_ASYNC BIT(6) +#define ACLKXPOL BIT(7) + +/* + * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits + */ +#define ACLKRDIV(val) (val) +#define ACLKRE BIT(5) +#define RX_ASYNC BIT(6) +#define ACLKRPOL BIT(7) + +/* + * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control + * Register Bits + */ +#define AHCLKXDIV(val) (val) +#define AHCLKXPOL BIT(14) +#define AHCLKXE BIT(15) + +/* + * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control + * Register Bits + */ +#define AHCLKRDIV(val) (val) +#define AHCLKRPOL BIT(14) +#define AHCLKRE BIT(15) + +/* + * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits + */ +#define MODE(val) (val) +#define DISMOD(val) (val<<2) +#define TXSTATE BIT(4) +#define RXSTATE BIT(5) + +/* + * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits + */ +#define LBEN BIT(0) +#define LBORD BIT(1) +#define LBGENMODE(val) (val<<2) + +/* + * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration + */ +#define TXTDMS(n) (1<<n) + +/* + * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration + */ +#define RXTDMS(n) (1<<n) + +/* + * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits + */ +#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */ +#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */ +#define RXSERCLR BIT(2) /* Receiver Serializer Clear */ +#define RXSMRST BIT(3) /* Receiver State Machine Reset */ +#define RXFSRST BIT(4) /* Frame Sync Generator Reset */ +#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */ +#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/ +#define TXSERCLR BIT(10) /* Transmit Serializer Clear */ +#define TXSMRST BIT(11) /* Transmitter State Machine Reset */ +#define TXFSRST BIT(12) /* Frame Sync Generator Reset */ + +/* + * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits + */ +#define MUTENA(val) (val) +#define MUTEINPOL BIT(2) +#define MUTEINENA BIT(3) +#define MUTEIN BIT(4) +#define MUTER BIT(5) +#define MUTEX BIT(6) +#define MUTEFSR BIT(7) +#define MUTEFSX BIT(8) +#define MUTEBADCLKR BIT(9) +#define MUTEBADCLKX BIT(10) +#define MUTERXDMAERR BIT(11) +#define MUTETXDMAERR BIT(12) + +/* + * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits + */ +#define RXDATADMADIS BIT(0) + +/* + * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits + */ +#define TXDATADMADIS BIT(0) + + + +#define DAVINCI_MCASP_NUM_SERIALIZER 16 + + +static inline void mcasp_set_bits(void __iomem *reg, u32 val) +{ + __raw_writel(__raw_readl(reg) | val, reg); +} + +static inline void mcasp_clr_bits(void __iomem *reg, u32 val) +{ + __raw_writel((__raw_readl(reg) & ~(val)), reg); +} + +static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask) +{ + __raw_writel((__raw_readl(reg) & ~mask) | val, reg); +} + +static inline void mcasp_set_reg(void __iomem *reg, u32 val) +{ + __raw_writel(val, reg); +} + +static inline u32 mcasp_get_reg(void __iomem *reg) +{ + return (unsigned int)__raw_readl(reg); +} + +static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val) +{ + int i = 0; + mcasp_set_bits(regs, val); + + /* programming GBLCTL needs to read back from GBLCTL and verfiy */ + /* loop count is to avoid the lock-up */ + for (i = 0; i < 1000; i++) { + if ((mcasp_get_reg(regs) & val) == val) + break; + } + if (i == 1000 && ((mcasp_get_reg(regs) & val) != val)) + printk(KERN_ERR "GBLCTL write error\n"); +} + +static int davinci_i2s_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct davinci_audio_dev *dev = cpu_dai->private_data; + cpu_dai->dma_data = dev->dma_params[substream->stream]; + return 0; +} + +static void mcasp_start_rx(struct davinci_audio_dev *dev) +{ + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); + + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); + + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); +} + +static void mcasp_start_tx(struct davinci_audio_dev *dev) +{ + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); + + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); + mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); +} + +static void davinci_mcasp_start(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + mcasp_start_tx(dev); + else + mcasp_start_rx(dev); +} + +static void mcasp_stop_rx(struct davinci_audio_dev *dev) +{ + mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); +} + +static void mcasp_stop_tx(struct davinci_audio_dev *dev) +{ + mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); +} + +static void davinci_mcasp_stop(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + mcasp_stop_tx(dev); + else + mcasp_stop_rx(dev); +} + +static int davinci_i2s_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, + unsigned int fmt) +{ + struct davinci_audio_dev *dev = cpu_dai->private_data; + void __iomem *base = dev->base; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* codec is clock and frame slave */ + mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); + mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); + + mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); + mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); + + mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26)); + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* codec is clock and frame master */ + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); + mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); + + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); + mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); + + mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26)); + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_IB_NF: + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + case SND_SOC_DAIFMT_NB_IF: + mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + case SND_SOC_DAIFMT_IB_IF: + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + case SND_SOC_DAIFMT_NB_NF: + mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); + + mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int davinci_config_channel_size(struct snd_pcm_substream *substream, + int channel_size) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + u32 fmt = 0; + + switch (channel_size) { + case DAVINCI_AUDIO_WORD_8: + fmt = 0x03; + break; + + case DAVINCI_AUDIO_WORD_12: + fmt = 0x05; + break; + + case DAVINCI_AUDIO_WORD_16: + fmt = 0x07; + break; + + case DAVINCI_AUDIO_WORD_20: + fmt = 0x09; + break; + + case DAVINCI_AUDIO_WORD_24: + fmt = 0x0B; + break; + + case DAVINCI_AUDIO_WORD_28: + fmt = 0x0D; + break; + + case DAVINCI_AUDIO_WORD_32: + fmt = 0x0F; + break; + + default: + return -1; + } + + mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, + RXSSZ(fmt), RXSSZ(0x0F)); + mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, + TXSSZ(fmt), TXSSZ(0x0F)); + return 0; +} + +static void davinci_hw_common_param(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + int i; + + /* Default configuration */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); + + /* All PINS as McASP */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, + TXDATADMADIS); + } else { + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG, + RXDATADMADIS); + } + + for (i = 0; i < dev->num_serializer; i++) { + mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), + dev->serial_dir[i]); + if (dev->serial_dir[i] == TX_MODE) + mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, + AXR(i)); + else if (dev->serial_dir[i] == RX_MODE) + mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, + AXR(i)); + } +} + +static void davinci_hw_param(struct snd_pcm_substream *substream) +{ + int i, active_slots; + u32 mask = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots; + for (i = 0; i < active_slots; i++) + mask |= (1 << i); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* bit stream is MSB first with no delay */ + /* DSP_B mode */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXE); + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask); + mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD); + + if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32)) + mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, + FSXMOD(dev->tdm_slots), FSXMOD(0x1FF)); + else + printk(KERN_ERR "playback tdm slot %d not supported\n", + dev->tdm_slots); + + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); + + } else { + /* bit stream is MSB first with no delay */ + /* DSP_B mode */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD); + mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, + AHCLKRE); + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask); + + if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32)) + mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, + FSRMOD(dev->tdm_slots), FSRMOD(0x1FF)); + else + printk(KERN_ERR "capture tdm slot %d not supported\n", + dev->tdm_slots); + + mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 0xFFFFFFFF); + mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); + } +} + +/* S/PDIF */ +static void davinci_hw_dit_param(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data; + + /* Set the PDIR for Serialiser as output */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX); + + /* TXMASK for 24 bits */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF); + + /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 + and LSB first */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, + TXROT(6) | TXSSZ(15)); + + /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG, + AFSXE | FSXMOD(0x180)); + + /* Set the TX tdm : for all the slots */ + mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); + + /* Set the TX clock controls : div = 1 and internal */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, + ACLKXE | TX_ASYNC); + + mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); + + /* Only 44100 and 48000 are valid, both have the same setting */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, + AHCLKXDIV(3)); + + /* Enable the DIT */ + mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN); +} + +static int davinci_i2s_mcasp_hw_params( + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + struct davinci_audio_dev *dev = cpu_dai->private_data; + struct davinci_pcm_dma_params *dma_params = + dev->dma_params[substream->stream]; + int word_length; + + davinci_hw_common_param(substream); + + if (dev->op_mode == DAVINCI_MCASP_DIT_MODE) + davinci_hw_dit_param(substream); + else + davinci_hw_param(substream); + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S8: + dma_params->data_type = 1; + word_length = DAVINCI_AUDIO_WORD_8; + break; + case SNDRV_PCM_FORMAT_S16_LE: + dma_params->data_type = 2; + word_length = DAVINCI_AUDIO_WORD_16; + break; + case SNDRV_PCM_FORMAT_S32_LE: + dma_params->data_type = 4; + word_length = DAVINCI_AUDIO_WORD_32; + break; + default: + printk(KERN_WARNING "davinci-i2s: unsupported PCM format"); + return -EINVAL; + } + davinci_config_channel_size(substream, word_length); + + return 0; +} + +static int davinci_i2s_mcasp_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *cpu_dai) +{ + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + davinci_mcasp_start(substream); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + davinci_mcasp_stop(substream); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static struct snd_soc_dai_ops davinci_i2s_dai_ops = { + .startup = davinci_i2s_startup, + .trigger = davinci_i2s_mcasp_trigger, + .hw_params = davinci_i2s_mcasp_hw_params, + .set_fmt = davinci_i2s_mcasp_set_dai_fmt, + +}; + +struct snd_soc_dai davinci_iis_mcasp_dai[] = { + { + .name = "davinci-i2s", + .id = 0, + .playback = { + .channels_min = 1, + .channels_max = 384, + .rates = DAVINCI_I2S_RATES, + .formats = SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + + }, + .capture = { + .channels_min = 1, + .channels_max = 384, + .rates = DAVINCI_I2S_RATES, + .formats = SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .ops = &davinci_i2s_dai_ops, + + }, + { + .name = "davinci-dit", + .id = 1, + .playback = { + .channels_min = 1, + .channels_max = 384, + .rates = DAVINCI_I2S_RATES, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &davinci_i2s_dai_ops, + }, + +}; +EXPORT_SYMBOL_GPL(davinci_iis_mcasp_dai); + +static int davinci_i2s_mcasp_probe(struct platform_device *pdev) +{ + int tmp, link_cnt, num_links = 2; + int count = 0; + struct davinci_audio_dev *dev; + struct resource *mem, *ioarea; + struct evm_snd_platform_data *parray = pdev->dev.platform_data; + struct evm_snd_platform_data *pdata; + struct davinci_pcm_dma_params *dma_data; + int ret = 0; + + dev = kzalloc(sizeof(struct davinci_audio_dev) * num_links, + GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dma_data = kzalloc(sizeof(struct davinci_pcm_dma_params) * + (num_links << 1), GFP_KERNEL); + + if (!dma_data) { + ret = -ENOMEM; + goto err_release_dev; + } + + for (link_cnt = 0; link_cnt < num_links; link_cnt++) { + mem = platform_get_resource(pdev, IORESOURCE_MEM, link_cnt); + if (!mem) { + dev_err(&pdev->dev, "no mem resource?\n"); + ret = -ENODEV; + goto err_release_data; + } + ioarea = request_mem_region(mem->start, + (mem->end - mem->start) + 1, pdev->name); + if (!ioarea) { + dev_err(&pdev->dev, "Audio region already claimed\n"); + ret = -EBUSY; + goto err_release_data; + } + + pdata = &parray[link_cnt]; + dev[link_cnt].clk = clk_get(&pdev->dev, pdata->clk_name); + + if (IS_ERR(dev[link_cnt].clk)) { + ret = -ENODEV; + goto err_release_region; + } + clk_enable(dev[link_cnt].clk); + + dev[link_cnt].base = (void __iomem *)IO_ADDRESS(mem->start); + dev[link_cnt].op_mode = pdata->op_mode; + dev[link_cnt].tdm_slots = pdata->tdm_slots; + dev[link_cnt].num_serializer = pdata->num_serializer; + dev[link_cnt].serial_dir = pdata->serial_dir; + dev[link_cnt].codec_fmt = pdata->codec_fmt; + + + dma_data[count].name = "I2S PCM Stereo out"; + dma_data[count].channel = pdata->tx_dma_ch; + dma_data[count].eventq_no = pdata->eventq_no; + dma_data[count].dma_addr = (dma_addr_t) (pdata->tx_dma_offset + + io_v2p(dev[link_cnt].base)); + dev[link_cnt].dma_params[SNDRV_PCM_STREAM_PLAYBACK] = + &dma_data[count]; + + + count++; + dma_data[count].name = "I2S PCM Stereo in"; + dma_data[count].channel = pdata->rx_dma_ch; + dma_data[count].eventq_no = pdata->eventq_no; + dma_data[count].dma_addr = (dma_addr_t)(pdata->rx_dma_offset + + io_v2p(dev[link_cnt].base)); + dev[link_cnt].dma_params[SNDRV_PCM_STREAM_CAPTURE] = + &dma_data[count]; + count++; + davinci_iis_mcasp_dai[link_cnt].private_data = &dev[link_cnt]; + } + ret = snd_soc_register_dais(davinci_iis_mcasp_dai, + ARRAY_SIZE(davinci_iis_mcasp_dai)); + if (ret != 0) + goto err_release_region; + return 0; + +err_release_region: + for (tmp = link_cnt; tmp >= 0; tmp--) { + mem = platform_get_resource(pdev, IORESOURCE_MEM, tmp); + release_mem_region(mem->start, + (mem->end - mem->start) + 1); + } +err_release_data: + kfree(dma_data); +err_release_dev: + kfree(dev); + + return ret; +} + +static int davinci_i2s_mcasp_remove(struct platform_device *pdev) +{ + int i, num_links = 2; + struct davinci_audio_dev *dev; + struct resource *mem; + struct davinci_pcm_dma_params *dma_data; + + snd_soc_unregister_dais(davinci_iis_mcasp_dai, + ARRAY_SIZE(davinci_iis_mcasp_dai)); + + for (i = 0; i < num_links; i++) { + dev = davinci_iis_mcasp_dai[i].private_data; + clk_disable(dev->clk); + clk_put(dev->clk); + dev->clk = NULL; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, i); + release_mem_region(mem->start, (mem->end - mem->start) + 1); + } + + dev = davinci_iis_mcasp_dai[0].private_data; + dma_data = dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; + kfree(dma_data); + kfree(dev); + return 0; +} + +static struct platform_driver davinci_asoc_driver = { + .probe = davinci_i2s_mcasp_probe, + .remove = davinci_i2s_mcasp_remove, + .driver = { + .name = "davinci-asoc", + .owner = THIS_MODULE, + }, +}; + +static int __init davinci_i2s_mcasp_init(void) +{ + + return platform_driver_register(&davinci_asoc_driver); + +} +module_init(davinci_i2s_mcasp_init); + +static void __exit davinci_i2s_mcasp_exit(void) +{ + + platform_driver_unregister(&davinci_asoc_driver); + +} +module_exit(davinci_i2s_mcasp_exit); + + + +MODULE_AUTHOR("Steve Chen"); +MODULE_DESCRIPTION("TI DAVINCI I2S (McASP) SoC Interface"); +MODULE_LICENSE("GPL"); + diff --git a/sound/soc/davinci/davinci-i2s-mcasp.h b/sound/soc/davinci/davinci-i2s-mcasp.h new file mode 100644 index 0000000..6469e7d --- /dev/null +++ b/sound/soc/davinci/davinci-i2s-mcasp.h @@ -0,0 +1,56 @@ +/* + * ALSA SoC I2S (McASP) Audio Layer for TI DAVINCI processor + * + * Author: Nirmal Pandey <n-pandey(a)ti.com>, + * Suresh Rajashekara <suresh.r(a)ti.com> + * Steve Chen, <schen@.mvista.com> + * + * Copyright: (C) 2008 MontaVista Software, Inc., <source(a)mvista.com> + * Copyright: (C) 2008 Texas Instruments, India + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#ifndef DAVINCI_I2S_MCASP_H +#define DAVINCI_I2S_MCASP_H + +#include <linux/io.h> +#include <mach/asp.h> +#include "davinci-pcm.h" + +extern struct snd_soc_dai davinci_iis_mcasp_dai[]; +extern struct snd_soc_dai davinci_dit_mcasp_dai; + + +#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 + +enum { + DAVINCI_AUDIO_WORD_8 = 0, + DAVINCI_AUDIO_WORD_12, + DAVINCI_AUDIO_WORD_16, + DAVINCI_AUDIO_WORD_20, + DAVINCI_AUDIO_WORD_24, + DAVINCI_AUDIO_WORD_32, + DAVINCI_AUDIO_WORD_28, /* This is only valid for McASP */ +}; + +struct davinci_audio_dev { + void __iomem *base; + int sample_rate; + struct clk *clk; + struct davinci_pcm_dma_params *dma_params[2]; + unsigned int codec_fmt; + + /* McASP specific data */ + int tdm_slots; + u8 op_mode; + u8 num_serializer; + u8 *serial_dir; +}; + + + +#endif /* DAVINCI_I2S_MCASP_H */ diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h index 62cb4eb..3cbe281 100644 --- a/sound/soc/davinci/davinci-pcm.h +++ b/sound/soc/davinci/davinci-pcm.h @@ -12,17 +12,18 @@ #ifndef _DAVINCI_PCM_H #define _DAVINCI_PCM_H +#include <mach/edma.h> +#include <mach/asp.h> + + struct davinci_pcm_dma_params { - char *name; /* stream identifier */ - int channel; /* sync dma channel ID */ - dma_addr_t dma_addr; /* device physical address for DMA */ - unsigned int data_type; /* xfer data type */ + char *name; /* stream identifier */ + int channel; /* sync dma channel ID */ + dma_addr_t dma_addr; /* device physical address for DMA */ + unsigned int data_type; /* xfer data type */ + enum dma_event_q eventq_no; /* event queue number */ }; -struct evm_snd_platform_data { - int tx_dma_ch; - int rx_dma_ch; -}; extern struct snd_soc_platform davinci_soc_platform; -- 1.5.6

1 0

[alsa-devel] /dev/snd/timer behavior
by Ron Cococcia 16 Apr '09

16 Apr '09

Hello, We have been attempting to debug an issue that we have been having for a few weeks related to audio playback. Specifically, over time, the playback of audio gets 'stuck' for a while (60 seconds or so), then quickly advances forward again (for about 60 seconds), then gets stuck again. It continues to repeat this until I either stop playback or pause/play. We have dubbed it 'skip-lock' as it skips ahead, then locks for a bit. It takes a while to reproduce this behavior, typically around 6 hours. We have about 30 of these systems setup, each with the same hardware configuration. They have a VIA C7 CPU (1.5GHz), 1GB RAM, and they are using the VIA 8233A AC97 controller with an ALC655 codec. The system is SATA based (using sata_via), and an RTL8110 gigabit ethernet controller (using rtl8169). For the OS, we are using Debian Etch with the 2.6.29 kernel, and we have tested a number of these units with 2.6.24-etchnhalf as well. ALSA lib 1.0.13 (from the install) is still in use, but I am trying out 1.0.19 on a few of the units to see if it helps. The player we use is called BlueTune, which we have used in older systems for years without trouble. I plan on trying to set up another player app to do the same testing, but haven't had the time to do that yet. On most of the systems, the player is using the default alsa output. I have configured a few systems to use plughw:0,0,0 for playback (mainly so that /dev/snd/timer is not used), and they have not had any playback issues so far (about 24 hours so far). After a bunch of other tests, we started to run strace against the player. We saw that it was repeatedly getting EAGAIN when reading from /dev/snd/timer during the 'stuck' phase. I have started to poke around a bit more in the timer code and see why EAGAIN is repeatedly being generated (in snd_timer_user_read, tu->qused is stuck at 0 for a while). I figured that if anybody had some things to try or places to look, it might save a bit of time in finding the cause of this issue. Thanks! Ron PS: I apologize if this is the wrong place to post this. I had posted a not-terribly-detailed message to alsa-user a few weeks ago, but have gained more data that I felt fit better here.

1 0

[alsa-devel] /proc/asound/* shows signs of life, but alsactl see's nothing
by Justin Mattock 16 Apr '09

16 Apr '09

This is confusing to me (with or without the imac9,1 patch for the imac) there is still entries in /proc/asound lrwxrwxrwx 1 root root 5 Apr 15 22:49 NVidia -> card0 dr-xr-xr-x 7 root root 0 Apr 15 22:49 card0 -r--r--r-- 1 root root 0 Apr 15 22:49 cards -r--r--r-- 1 root root 0 Apr 15 22:49 devices -r--r--r-- 1 root root 0 Apr 15 22:49 hwdep -r--r--r-- 1 root root 0 Apr 15 22:49 pcm -r--r--r-- 1 root root 0 Apr 15 22:49 timers -r--r--r-- 1 root root 0 Apr 15 22:49 version but when I do: sudo /usr/sbin/alsactl store /usr/sbin/alsactl: save_state:1502: No soundcards found... I this a software issue, or is this because the kernel is missing something important in patch_realtek.c ? I've moved different things around in patch_realtek.c but still no speaker sound or headphone, not even the sound during boot when the module is being loaded. Also what is the best way to find PCI SSID? under codec#0:(I have) Codec: Realtek ALC889A Address: 0 Vendor Id: 0x10ec0885 Subsystem Id: 0x106b4900 Revision Id: 0x100103 No Modem Function Group found but with lspci -nnv 00:08.0 0403: 10de:0ac0 (rev b1) Subsystem: 10de:cb79 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (500ns min, 1250ns max) Interrupt: pin A routed to IRQ 17 Region 0: Memory at d3480000 (32-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel the subsystem is 10de:cb79 but is Subsystem Id: 0x106b4900 regards, -- Justin P. Mattock

2 4

[alsa-devel] [PATCH] hdspm: native float
by Florian Faber 16 Apr '09

16 Apr '09

Adds native float support to the driver. The interface has hardware support for CoreAudio[tm], why shouldn't jack users benefit from it. diff a/sound/pci/rme9652/hdspm.c b/sound/pci/rme9652/hdspm.c 13a14,16 > * Modified 2009-04-14 for native float support by Florian Faber > * <faber(a)faberman.de> > * 39a43 > #include <sound/pcm_params.h> 198a203 > #define HDSPe_FLOAT_FORMAT 0x2000000 3726a3732,3747 > > > /* Switch to native float format if requested */ > if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { > if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) { > snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); > } > hdspm->control_register |= HDSPe_FLOAT_FORMAT; > } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { > if (hdspm->control_register & HDSPe_FLOAT_FORMAT) { > snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); > } > hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; > } > hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); > 3870c3891 < .formats = SNDRV_PCM_FMTBIT_S32_LE, --- > .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT_LE, 3895c3916 < .formats = SNDRV_PCM_FMTBIT_S32_LE, --- > .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT_LE, Flo -- Machines can do the work, so people have time to think. public key 6C002249 x-hkp://wwwkeys.eu.pgp.net

6 8

[alsa-devel] [PATCH v2 2/6] ARM: DaVinci: ASoC: Add the platform devices for ASP
by Naresh Medisetty 16 Apr '09

16 Apr '09

1)Registers the platform devices for ASP on dm355, dm644x and dm646x so that the machine driver can probe to get ASP related platform data. 2)Move towards definition of the asp clocks using phyisical name(for dm355 and dm644x) Signed-off-by: Naresh Medisetty <naresh(a)ti.com> --- This patch applies to the DaVinci git tree available at http://git.kernel.org/?p=linux/kernel/git/khilman/linux-davinci.git arch/arm/mach-davinci/dm355.c | 29 ++++++++++++- arch/arm/mach-davinci/dm644x.c | 27 +++++++++++- arch/arm/mach-davinci/dm646x.c | 67 ++++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/asp.h | 39 ++++++++++++++++- 4 files changed, 157 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index c20211c..222c3f3 100755 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -23,6 +23,7 @@ #include <mach/psc.h> #include <mach/mux.h> #include <mach/irqs.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" @@ -351,8 +352,8 @@ static struct davinci_clk dm355_clks[] = { CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart2", &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("soc-audio.0", NULL, &asp0_clk), - CLK("soc-audio.1", NULL, &asp1_clk), + CLK(NULL, "asp0", &asp0_clk), + CLK(NULL, "asp1", &asp1_clk), CLK("davinci_mmc.0", NULL, &mmcsd0_clk), CLK("davinci_mmc.1", NULL, &mmcsd1_clk), CLK(NULL, "spi0", &spi0_clk), @@ -540,6 +541,29 @@ static struct platform_device dm355_edma_device = { .resource = edma_resources, }; +/* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ +static struct resource dm355_evm_snd_resources[] = { + { + .start = DAVINCI_ASP1_BASE, + .end = DAVINCI_ASP1_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct evm_snd_platform_data dm355_evm_snd_data = { + .clk_name = "asp1", + .tx_dma_ch = DAVINCI_DMA_ASP1_TX, + .rx_dma_ch = DAVINCI_DMA_ASP1_RX, +}; + +static struct platform_device dm355_asoc_device = { + .name = "davinci-asoc", + .id = -1, + .dev.platform_data = &dm355_evm_snd_data, + .num_resources = ARRAY_SIZE(dm355_evm_snd_resources), + .resource = dm355_evm_snd_resources, +}; + /*----------------------------------------------------------------------*/ void __init dm355_init(void) @@ -555,6 +579,7 @@ static int __init dm355_init_devices(void) davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); + platform_device_register(&dm355_asoc_device); return 0; } postcore_initcall(dm355_init_devices); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 9878c17..01112ca 100755 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -20,6 +20,7 @@ #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" @@ -296,7 +297,7 @@ struct davinci_clk dm644x_clks[] = { CLK("davinci_emac.1", NULL, &emac_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK("palm_bk3710", NULL, &ide_clk), - CLK("soc-audio.0", NULL, &asp_clk), + CLK(NULL, "asp0", &asp_clk), CLK("davinci_mmc.0", NULL, &mmcsd_clk), CLK(NULL, "spi", &spi_clk), CLK(NULL, "gpio", &gpio_clk), @@ -463,6 +464,29 @@ static struct platform_device dm644x_edma_device = { .resource = edma_resources, }; +/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ +static struct resource dm644x_evm_snd_resources[] = { + { + .start = DAVINCI_ASP0_BASE, + .end = DAVINCI_ASP0_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct evm_snd_platform_data dm644x_evm_snd_data = { + .clk_name = "asp0", + .tx_dma_ch = DAVINCI_DMA_ASP0_TX, + .rx_dma_ch = DAVINCI_DMA_ASP0_RX, +}; + +static struct platform_device dm644x_asoc_device = { + .name = "davinci-asoc", + .id = -1, + .dev.platform_data = &dm644x_evm_snd_data, + .num_resources = ARRAY_SIZE(dm644x_evm_snd_resources), + .resource = dm644x_evm_snd_resources, +}; + /*----------------------------------------------------------------------*/ #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) @@ -495,6 +519,7 @@ static int __init dm644x_init_devices(void) return 0; platform_device_register(&dm644x_edma_device); + platform_device_register(&dm644x_asoc_device); return 0; } postcore_initcall(dm644x_init_devices); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 39ffd17..bb8c65a 100755 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -20,6 +20,7 @@ #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" @@ -499,6 +500,70 @@ static struct platform_device dm646x_edma_device = { .resource = edma_resources, }; +static u8 dm6467_iis_serializer_direction[] = { + TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static u8 dm6467_dit_serializer_direction[] = { + TX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct evm_snd_platform_data dm6467_evm_snd_data[] = { + { + .clk_name = "mcasp0", + .tx_dma_ch = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, + .rx_dma_ch = DAVINCI_DM646X_DMA_MCASP0_AREVT0, + .tx_dma_offset = 0x400, + .rx_dma_offset = 0x400, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = 4, + .tdm_slots = 2, + .serial_dir = dm6467_iis_serializer_direction, + .eventq_no = EVENTQ_0, + }, + { + .clk_name = "mcasp1", + .tx_dma_ch = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, + .rx_dma_ch = -1, + .tx_dma_offset = 0x400, + .rx_dma_offset = 0, + .op_mode = DAVINCI_MCASP_DIT_MODE, + .num_serializer = 4, + .tdm_slots = 32, + .serial_dir = dm6467_dit_serializer_direction, + .eventq_no = EVENTQ_0, + }, +}; + +static struct resource dm6467_evm_snd_resources[] = { + { + .name = "mcasp0", + .start = DAVINCI_DM646X_MCASP0_REG_BASE, + .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "mcasp1", + .start = DAVINCI_DM646X_MCASP1_REG_BASE, + .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm646x_asoc_device = { + .name = "davinci-asoc", + .id = -1, + .dev.platform_data = dm6467_evm_snd_data, + .num_resources = ARRAY_SIZE(dm6467_evm_snd_resources), + .resource = dm6467_evm_snd_resources, +}; + +static struct platform_device dm646x_dit_device = { + .name = "davinci-dit", + .id = -1, + +}; + /*----------------------------------------------------------------------*/ #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) @@ -532,6 +597,8 @@ static int __init dm646x_init_devices(void) return 0; platform_device_register(&dm646x_edma_device); + platform_device_register(&dm646x_asoc_device); + platform_device_register(&dm646x_dit_device); return 0; } postcore_initcall(dm646x_init_devices); diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index e0abc43..1bb1f0b 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -5,21 +5,56 @@ #define __ASM_ARCH_DAVINCI_ASP_H #include <mach/irqs.h> +#include <mach/edma.h> -/* Bases of register banks */ +/* Bases of dm644x and dm355 register banks */ #define DAVINCI_ASP0_BASE 0x01E02000 #define DAVINCI_ASP1_BASE 0x01E04000 -/* EDMA channels */ + +/* Bases of dm646x register banks */ +#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 +#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 + +/* EDMA channels of dm644x and dm355 */ #define DAVINCI_DMA_ASP0_TX 2 #define DAVINCI_DMA_ASP0_RX 3 #define DAVINCI_DMA_ASP1_TX 8 #define DAVINCI_DMA_ASP1_RX 9 + +/* EDMA channels of dm646x */ +#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 +#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 +#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 /* Interrupts */ #define DAVINCI_ASP0_RX_INT IRQ_MBRINT #define DAVINCI_ASP0_TX_INT IRQ_MBXINT #define DAVINCI_ASP1_RX_INT IRQ_MBRINT #define DAVINCI_ASP1_TX_INT IRQ_MBXINT +struct evm_snd_platform_data { + char *clk_name; + int tx_dma_ch; + int rx_dma_ch; + u32 tx_dma_offset; + u32 rx_dma_offset; + enum dma_event_q eventq_no; /* event queue number */ + unsigned int codec_fmt; + + /* McASP specific fields */ + int tdm_slots; + u8 op_mode; + u8 num_serializer; + u8 *serial_dir; +}; + +#define INACTIVE_MODE 0 +#define TX_MODE 1 +#define RX_MODE 2 + +#define DAVINCI_MCASP_IIS_MODE 0 +#define DAVINCI_MCASP_DIT_MODE 1 + + #endif /* __ASM_ARCH_DAVINCI_ASP_H */ -- 1.5.6

3 2

Re: [alsa-devel] 15 April unstable does not handle wave-in
by Susan Cragin 16 Apr '09

16 Apr '09

>Works perfectly. Thank you. >Susan > > Whoops. Spoke too soon. Does not save alsa settings. They have to be re-set after each boot. Susan

1 0

Re: [alsa-devel] 15 April unstable does not handle wave-in
by Susan Cragin 16 Apr '09

16 Apr '09

>> Meanwhile, if ca0110 worked fine with unstable tree before, it means that the hda-ca0110 patch can go in to the sound git tree. This would be a better option for both of us. >> >> Now I merged hda-ca0110 patch to sound git tree. >> So alsa-driver snapshot (no unstable version) should work for your >> CA0110 board. Give it a try. >Takashi Works perfectly. Thank you. Susan

1 0

[alsa-devel] No sound with Creative Labs CA0106 Soundblaster
by Bernhard Posselt 16 Apr '09

16 Apr '09

Hi, some months ago i bought a new soundcard for my PC which costed 20€. This card is not working. Im using Kubuntu Jaunty Beta, its a fresh install from the beta iso. I also upgraded the alsadrivers with this package http://ftp.kernel.org/pub/linux/kernel/people/tiwai/snapshot/alsa-driver-sn… Still no sound Heres my bug report: https://bugtrack.alsa-project.org/alsa-bug/view.php?id=4490 I hope you can help me regards Ray -- Psssst! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger01

2 1

[alsa-devel] ASoC updates for 2.6.31
by Mark Brown 16 Apr '09

16 Apr '09

The following changes since commit 6967963d6d5cac40a091d075326f0e3ccb95c58a: Mark Brown (1): Merge branch 'for-2.6.30' into for-2.6.31 are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6.git for-2.6.31 Ben Dooks (4): ASoC: Fix jive_wm8750.c build problems ASoC: s3c-i2s-v2.c fix for s3c_i2sv2_iis_calc_rate ASoC: Fix s3c-i2s-v2.c snd_soc_dai changes ASoC: Fix include build error in s3c2412-i2s.c Daniel Mack (1): ASoC: pxa-ssp: allow setting of dai format 0 Jarkko Nikula (2): ASoC: OMAP: Fix DSP_B format in OMAP McBSP DAI driver ASoC: OMAP: Fix FS polarity in OSK5912 machine driver Mark Brown (4): ASoC: Check we have DAI ops when calling via accessor functions ASoC: Volume controls are never of boolean type ASoC: Request shared rates for WM8903 Merge branch 'for-2.6.30' into for-2.6.31 Peter Ujfalusi (2): ASoC: OMAP: Use single-phase for DSP mode ASoC: OMAP: Add DSP_A mode support for mcbsp sound/soc/codecs/wm8903.c | 1 + sound/soc/omap/omap-mcbsp.c | 45 ++++++++++++++++++++++++++------------ sound/soc/omap/osk5912.c | 4 +- sound/soc/pxa/pxa-ssp.c | 1 + sound/soc/s3c24xx/jive_wm8750.c | 12 +++++----- sound/soc/s3c24xx/s3c-i2s-v2.c | 18 ++++++++------- sound/soc/s3c24xx/s3c2412-i2s.c | 2 +- sound/soc/soc-core.c | 20 ++++++++-------- 8 files changed, 62 insertions(+), 41 deletions(-)

2 1

[alsa-devel] ASoC updates for 2.6.30
by Mark Brown 16 Apr '09

16 Apr '09

The following changes since commit 9dd175f7d2db1826c891855d3d150da3a5792e94: Takashi Iwai (1): Merge branch 'topic/hda' into for-linus are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6.git for-2.6.30 Ben Dooks (4): ASoC: Fix jive_wm8750.c build problems ASoC: s3c-i2s-v2.c fix for s3c_i2sv2_iis_calc_rate ASoC: Fix s3c-i2s-v2.c snd_soc_dai changes ASoC: Fix include build error in s3c2412-i2s.c Daniel Mack (1): ASoC: pxa-ssp: allow setting of dai format 0 Jarkko Nikula (2): ASoC: OMAP: Fix DSP_B format in OMAP McBSP DAI driver ASoC: OMAP: Fix FS polarity in OSK5912 machine driver sound/soc/omap/omap-mcbsp.c | 7 +++++-- sound/soc/omap/osk5912.c | 4 ++-- sound/soc/pxa/pxa-ssp.c | 1 + sound/soc/s3c24xx/jive_wm8750.c | 12 ++++++------ sound/soc/s3c24xx/s3c-i2s-v2.c | 18 ++++++++++-------- sound/soc/s3c24xx/s3c2412-i2s.c | 2 +- 6 files changed, 25 insertions(+), 19 deletions(-)

2 1