March 2018 - Sound-open-firmware - mailman.alsa-project.org

[Sound-open-firmware] [PATCH] topology: break up topology builder m4 files into per component macros
by Ranjani Sridharan 06 Mar '18

06 Mar '18

This patch break up the local.m4 and build.m4 topology builder includes into per component m4 files Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- topology/m4/buffer.m4 | 29 ++ topology/m4/dai.m4 | 214 ++++++++++ topology/m4/local.m4 | 654 ------------------------------ topology/m4/mixer.m4 | 43 ++ topology/m4/mixercontrol.m4 | 49 +++ topology/m4/pcm.m4 | 161 ++++++++ topology/m4/pga.m4 | 44 ++ topology/m4/{build.m4 => pipeline.m4} | 60 +-- topology/m4/src.m4 | 41 ++ topology/m4/tone.m4 | 43 ++ topology/m4/utils.m4 | 65 +++ topology/reef-apl-nocodec.m4 | 5 +- topology/reef-bdw-rt286.m4 | 5 +- topology/reef-bdw-rt5640.m4 | 5 +- topology/reef-bxt-nocodec.m4 | 5 +- topology/reef-byt-da7212.m4 | 5 +- topology/reef-byt-nocodec.m4 | 5 +- topology/reef-byt-rt5640.m4 | 5 +- topology/reef-byt-rt5645.m4 | 5 +- topology/reef-byt-rt5651.m4 | 5 +- topology/reef-cht-max98090.m4 | 5 +- topology/reef-cht-nocodec.m4 | 5 +- topology/reef-cnl-rt274.m4 | 5 +- topology/reef-hsw-rt5640.m4 | 5 +- topology/sof/pipe-dai-capture.m4 | 4 +- topology/sof/pipe-dai-playback.m4 | 4 +- topology/sof/pipe-low-latency-capture.m4 | 6 +- topology/sof/pipe-low-latency-playback.m4 | 7 +- topology/sof/pipe-passthrough-capture.m4 | 7 +- topology/sof/pipe-passthrough-playback.m4 | 7 +- topology/sof/pipe-pcm-media.m4 | 7 +- topology/sof/pipe-src-capture.m4 | 8 +- topology/sof/pipe-src-playback.m4 | 8 +- topology/sof/pipe-tone.m4 | 7 +- topology/sof/pipe-volume-capture.m4 | 8 +- topology/sof/pipe-volume-playback.m4 | 8 +- topology/test/test-capture-ssp.m4 | 5 +- topology/test/test-playback-ssp.m4 | 5 +- topology/test/test-ssp.m4 | 5 +- topology/test/test-tone-playback-ssp.m4 | 5 +- 40 files changed, 836 insertions(+), 733 deletions(-) create mode 100644 topology/m4/buffer.m4 create mode 100644 topology/m4/dai.m4 delete mode 100644 topology/m4/local.m4 create mode 100644 topology/m4/mixer.m4 create mode 100644 topology/m4/mixercontrol.m4 create mode 100644 topology/m4/pcm.m4 create mode 100644 topology/m4/pga.m4 rename topology/m4/{build.m4 => pipeline.m4} (76%) create mode 100644 topology/m4/src.m4 create mode 100644 topology/m4/tone.m4 create mode 100644 topology/m4/utils.m4 diff --git a/topology/m4/buffer.m4 b/topology/m4/buffer.m4 new file mode 100644 index 0000000..fc06ba0 --- /dev/null +++ b/topology/m4/buffer.m4 @@ -0,0 +1,29 @@ +divert(-1) + +dnl Define the macro for buffer widget + +dnl Buffer name) +define(`N_BUFFER', `BUF'PIPELINE_ID`.'$1) + +dnl W_BUFFER(name, size, capabilities) +define(`W_BUFFER', +`SectionVendorTuples."'N_BUFFER($1)`_tuples" {' +` tokens "sof_buffer_tokens"' +` tuples."word" {' +` SOF_TKN_BUF_SIZE' STR($2) +` SOF_TKN_BUF_CAPS' STR($3) +` }' +`}' +`SectionData."'N_BUFFER($1)`_data" {' +` tuples "'N_BUFFER($1)`_tuples"' +`}' +`SectionWidget."'N_BUFFER($1)`" {' +` index "'PIPELINE_ID`"' +` type "buffer"' +` no_pm "true"' +` data [' +` "'N_BUFFER($1)`_data"' +` ]' +`}') + +divert(0)dnl diff --git a/topology/m4/dai.m4 b/topology/m4/dai.m4 new file mode 100644 index 0000000..163dfab --- /dev/null +++ b/topology/m4/dai.m4 @@ -0,0 +1,214 @@ +divert(-1) + +dnl Define macros for DAI IN/OUT widgets and DAI config + +dnl DAI name) +define(`N_DAI', DAI_NAME) +define(`N_DAI_OUT', DAI_NAME`.OUT') +define(`N_DAI_IN', DAI_NAME`.IN') + +dnl W_DAI_OUT(type, index, format, periods_sink, periods_source, preload, data) +define(`W_DAI_OUT', +`SectionVendorTuples."'N_DAI_OUT($2)`_tuples_w_comp" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($4) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($5) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($6) +` }' +`}' +`SectionData."'N_DAI_OUT($2)`_data_w_comp" {' +` tuples "'N_DAI_OUT($2)`_tuples_w_comp"' +`}' +`SectionVendorTuples."'N_DAI_OUT($2)`_tuples_w" {' +` tokens "sof_dai_tokens"' +` tuples."word" {' +` SOF_TKN_DAI_INDEX' $2 +` }' +`}' +`SectionData."'N_DAI_OUT($2)`_data_w" {' +` tuples "'N_DAI_OUT($2)`_tuples_w"' +`}' +`SectionVendorTuples."'N_DAI_OUT($2)`_tuples_str" {' +` tokens "sof_dai_tokens"' +` tuples."string" {' +` SOF_TKN_DAI_TYPE' $1 +` }' +`}' +`SectionData."'N_DAI_OUT($2)`_data_str" {' +` tuples "'N_DAI_OUT($2)`_tuples_str"' +`}' +`SectionVendorTuples."'N_DAI_OUT($2)`_tuples_comp_str" {' +` tokens "sof_comp_tokens"' +` tuples."string" {' +` SOF_TKN_COMP_FORMAT' STR($3) +` }' +`}' +`SectionData."'N_DAI_OUT($2)`_data_comp_str" {' +` tuples "'N_DAI_OUT($2)`_tuples_comp_str"' +`}' +`SectionWidget."'N_DAI_OUT`" {' +` index "'PIPELINE_ID`"' +` type "dai_in"' +` no_pm "true"' +` data [' +` "'N_DAI_OUT($2)`_data_w"' +` "'N_DAI_OUT($2)`_data_w_comp"' +` "'N_DAI_OUT($2)`_data_str"' +` "'N_DAI_OUT($2)`_data_comp_str"' +` "'$7`"' +` ]' +`}') + +dnl W_DAI_IN(type, index, format, periods_sink, periods_source, preload, data) +define(`W_DAI_IN', +`SectionVendorTuples."'N_DAI_IN($2)`_tuples_w_comp" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($4) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($5) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($6) +` }' +`}' +`SectionData."'N_DAI_IN($2)`_data_w_comp" {' +` tuples "'N_DAI_IN($2)`_tuples_w_comp"' +`}' +`SectionVendorTuples."'N_DAI_IN($2)`_tuples_w" {' +` tokens "sof_dai_tokens"' +` tuples."word" {' +` SOF_TKN_DAI_INDEX' $2 +` }' +`}' +`SectionData."'N_DAI_IN($2)`_data_w" {' +` tuples "'N_DAI_IN($2)`_tuples_w"' +`}' +`SectionVendorTuples."'N_DAI_IN($2)`_tuples_str" {' +` tokens "sof_dai_tokens"' +` tuples."string" {' +` SOF_TKN_DAI_TYPE' $1 +` }' +`}' +`SectionData."'N_DAI_IN($2)`_data_str" {' +` tuples "'N_DAI_IN($2)`_tuples_str"' +`}' +`SectionVendorTuples."'N_DAI_IN($2)`_tuples_comp_str" {' +` tokens "sof_comp_tokens"' +` tuples."string" {' +` SOF_TKN_COMP_FORMAT' STR($3) +` }' +`}' +`SectionData."'N_DAI_IN($2)`_data_comp_str" {' +` tuples "'N_DAI_IN($2)`_tuples_comp_str"' +`}' +`SectionWidget."'N_DAI_IN`" {' +` index "'PIPELINE_ID`"' +` type "dai_out"' +` no_pm "true"' +` data [' +` "'N_DAI_IN($2)`_data_w"' +` "'N_DAI_IN($2)`_data_w_comp"' +` "'N_DAI_IN($2)`_data_str"' +` "'N_DAI_IN($2)`_data_comp_str"' +` "'$7`"' +` ]' +`}') + +dnl D_DAI(id, playback, capture, data)) +define(`D_DAI', `SectionDAI."'N_DAI`" {' +` index "'PIPELINE_ID`"' +` id "'$1`"' +` playback "'$2`"' +` capture "'$3`"' +`}') + +dnl DAI_CLOCK(clock, freq, codec_master) +define(`DAI_CLOCK', + $1 STR($3) + $1_freq STR($2)) + + +dnl DAI_TDM(slots, width, tx_mask, rx_mask) +define(`DAI_TDM', +` tdm_slots 'STR($1) +` tdm_slot_width 'STR($2) +` tx_slots 'STR($3) +` rx_slots 'STR($4) +) + +dnl DAI Config) +define(`N_DAI_CONFIG', `DAICONFIG.'$1) + +dnl DAI_CONFIG(type, idx, name, format, valid bits, mclk, bclk, fsync, tdm) +define(`DAI_CONFIG', +`SectionHWConfig."'$1$2`" {' +`' +` id "'$2`"' +` format "'$4`"' +`' +` '$6 +` '$7 +` '$8 +` '$9 +`}' +`SectionVendorTuples."'N_DAI_CONFIG($1$2)`_tuples_str" {' +` tokens "sof_dai_tokens"' +` tuples."string" {' +` SOF_TKN_DAI_TYPE' STR($1) +` }' +`}' +`SectionData."'N_DAI_CONFIG($1$2)`_data_str" {' +` tuples "'N_DAI_CONFIG($1$2)`_tuples_str"' +`}' +`SectionVendorTuples."'N_DAI_CONFIG($1$2)`_tuples" {' +` tokens "sof_dai_tokens"' +` tuples."word" {' +` SOF_TKN_DAI_SAMPLE_BITS' STR($5) +` }' +`}' +`SectionData."'N_DAI_CONFIG($1$2)`_data" {' +` tuples "'N_DAI_CONFIG($1$2)`_tuples"' +`}' +`' +`SectionBE."'$3`" {' +` index "0"' +` default_hw_conf_id "'$2`"' +`' +` hw_configs [' +` "'$1$2`"' +` ]' +` data [' +` "'N_DAI_CONFIG($1$2)`_data"' +` "'N_DAI_CONFIG($1$2)`_data_str"' +` ]' +`}') + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, +dnl buffer, periods, format, +dnl frames, deadline, priority, core) +define(`DAI_ADD', +`undefine(`PIPELINE_ID')' +`undefine(`DAI_TYPE')' +`undefine(`DAI_INDEX')' +`undefine(`DAI_BUF')' +`undefine(`DAI_PERIODS')' +`undefine(`DAI_FORMAT')' +`undefine(`SCHEDULE_FRAMES')' +`undefine(`SCHEDULE_DEADLINE')' +`undefine(`SCHEDULE_PRIORITY')' +`undefine(`SCHEDULE_CORE')' +`define(`PIPELINE_ID', $2)' +`define(`DAI_TYPE', STR($3))' +`define(`DAI_INDEX', STR($4))' +`define(`DAI_BUF', $5)' +`define(`DAI_NAME', $3$4)' +`define(`DAI_PERIODS', $6)' +`define(`DAI_FORMAT', $7)' +`define(`SCHEDULE_FRAMES', $8)' +`define(`SCHEDULE_DEADLINE', $9)' +`define(`SCHEDULE_PRIORITY', $10)' +`define(`SCHEDULE_CORE', $11)' +`include($1)' +) + +divert(0)dnl diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 deleted file mode 100644 index df6ea14..0000000 diff --git a/topology/m4/mixer.m4 b/topology/m4/mixer.m4 new file mode 100644 index 0000000..1f2376e --- /dev/null +++ b/topology/m4/mixer.m4 @@ -0,0 +1,43 @@ +divert(-1) + +dnl Define macro for Mixer widget + +dnl Mixer Name) +define(`N_MIXER', `MIXER'PIPELINE_ID`.'$1) + +dnl Pipe Buffer name in pipeline (pipeline, buffer) +define(`NPIPELINE_MIXER', `MIXER'$1`.'$2) + +dnl W_MIXER(name, format, periods_sink, periods_source, preload) +define(`W_MIXER', +`SectionVendorTuples."'N_MIXER($1)`_tuples_w" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($4) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($5) +` }' +`}' +`SectionData."'N_MIXER($1)`_data_w" {' +` tuples "'N_MIXER($1)`_tuples_w"' +`}' +`SectionVendorTuples."'N_MIXER($1)`_tuples_str" {' +` tokens "sof_comp_tokens"' +` tuples."string" {' +` SOF_TKN_COMP_FORMAT' STR($2) +` }' +`}' +`SectionData."'N_MIXER($1)`_data_str" {' +` tuples "'N_MIXER($1)`_tuples_str"' +`}' +`SectionWidget."'N_MIXER($1)`" {' +` index "'PIPELINE_ID`"' +` type "mixer"' +` no_pm "true"' +` data [' +` "'N_MIXER($1)`_data_w"' +` "'N_MIXER($1)`_data_str"' +` ]' +`}') + +divert(0)dnl diff --git a/topology/m4/mixercontrol.m4 b/topology/m4/mixercontrol.m4 new file mode 100644 index 0000000..77a3784 --- /dev/null +++ b/topology/m4/mixercontrol.m4 @@ -0,0 +1,49 @@ +divert(-1) + +dnl Define macro for mixer control + +dnl KCONTROL_CHANNEL(name, reg, shift) +define(`KCONTROL_CHANNEL', +`channel.STR($1) {' +` reg STR($2)' +` shift STR($3)' +` }') + +dnl CONTROLMIXER_MAX(comment, value) +define(`CONTROLMIXER_MAX', +`#$1' +` max STR($2)') + +dnl CONTROLMIXER_TLV(comment, value) +define(`CONTROLMIXER_TLV', +`#$1' +` tlv STR($2)') + +dnl CONTROLMIXER_OPS(info, comment, get, put) +define(`CONTROLMIXER_OPS', +`ops."ctl" {' +` info STR($1)' +` #$2' +` get STR($3)' +` put STR($4)' +` }') + +dnl C_CONTROLMIXER(name, index, ops, max, invert, tlv, KCONTROL_CHANNELS) +define(`C_CONTROLMIXER', +`SectionControlMixer.STR($1) {' +`' +` # control belongs to this index group' +` index STR($2)' +`' +` #$7' +` $8' +` # control uses bespoke driver get/put/info ID' +` $3' +`' +` $4' +` invert STR($5)' +` $6' + +`}') + +divert(0)dnl diff --git a/topology/m4/pcm.m4 b/topology/m4/pcm.m4 new file mode 100644 index 0000000..d767350 --- /dev/null +++ b/topology/m4/pcm.m4 @@ -0,0 +1,161 @@ +divert(-1) + +dnl Define the macro for PCM playback/capture/capabilities + +dnl PCM name) +define(`N_PCMP', `PCM'PCM_ID`P') +define(`N_PCMC', `PCM'PCM_ID`C') + +dnl W_PCM_PLAYBACK(stream, dmac, dmac_chan, periods_sink, periods_source, preload) +dnl PCM platform configuration +define(`W_PCM_PLAYBACK', +`SectionVendorTuples."'N_PCMP($1)`_tuples_w_comp" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($4) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($5) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($6) +` }' +`}' +`SectionData."'N_PCMP($1)`_data_w_comp" {' +` tuples "'N_PCMP($1)`_tuples_w_comp"' +`}' +`SectionVendorTuples."'N_PCMP($1)`_tuples" {' +` tokens "sof_pcm_tokens"' +` tuples."word" {' +` SOF_TKN_PCM_DMAC' STR($2) +` SOF_TKN_PCM_DMAC_CHAN' STR($3) +` }' +`}' +`SectionData."'N_PCMP($1)`_data" {' +` tuples "'N_PCMP($1)`_tuples"' +`}' +`SectionWidget."'N_PCMP`" {' +` index "'PIPELINE_ID`"' +` type "aif_in"' +` no_pm "true"' +` stream_name "'$1`"' +` data [' +` "'N_PCMP($1)`_data"' +` "'N_PCMP($1)`_data_w_comp"' +` ]' +`}') + + +dnl W_PCM_CAPTURE(stream, dmac, dmac_chan, periods_sink, periods_source, preload) +define(`W_PCM_CAPTURE', +`SectionVendorTuples."'N_PCMC($1)`_tuples_w_comp" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($4) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($5) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($6) +` }' +`}' +`SectionData."'N_PCMC($1)`_data_w_comp" {' +` tuples "'N_PCMC($1)`_tuples_w_comp"' +`}' +`SectionVendorTuples."'N_PCMC($1)`_tuples" {' +` tokens "sof_pcm_tokens"' +` tuples."word" {' +` SOF_TKN_PCM_DMAC' STR($2) +` SOF_TKN_PCM_DMAC_CHAN' STR($3) +` }' +`}' +`SectionData."'N_PCMC($1)`_data" {' +` tuples "'N_PCMC($1)`_tuples"' +`}' +`SectionWidget."'N_PCMC`" {' +` index "'PIPELINE_ID`"' +` type "aif_out"' +` no_pm "true"' +` stream_name "'$1`"' +` data [' +` "'N_PCMC($1)`_data"' +` "'N_PCMC($1)`_data_w_comp"' +` ]' +`}') + +dnl PCM_CAPABILITIES(name, formats, rate_min, rate_max, channels_min, channels_max, periods_min, periods_max, period_size_min, period_size_max, buffer_size_min, buffer_size_max) +define(`PCM_CAPABILITIES', +`SectionPCMCapabilities.STR($1) {' +`' +` formats "$2"' +` rate_min STR($3)' +` rate_max STR($4)' +` channels_min STR($5)' +` channels_max STR($6)' +` periods_min STR($7)' +` periods_max STR($8)' +` period_size_min STR($9)' +` period_size_max STR($10)' +` buffer_size_min STR($11)' +` buffer_size_max STR($12)' +`}') + +dnl COMP_BUFFER_SIZE( num_periods, sample_size, channels, fmames) +define(`COMP_BUFFER_SIZE', `eval(`$1 * $2 * $3 * $4')') + +dnl PCM_PLAYBACK_ADD(name, pipeline, pcm_id, dai_id, playback) +define(`PCM_PLAYBACK_ADD', +`SectionPCM.STR($1) {' +`' +` index STR($2)' +`' +` # used for binding to the PCM' +` id STR($3)' +`' +` dai.STR($1 $3) {' +` id STR($4)' +` }' +`' +` pcm."playback" {' +`' +` capabilities STR($5)' +` }' +`}') + +dnl PCM_CAPTURE_ADD(name, pipeline, pcm_id, dai_id, capture) +define(`PCM_CAPTURE_ADD', +`SectionPCM.STR($1) {' +`' +` index STR($2)' +`' +` # used for binding to the PCM' +` id STR($3)' +`' +` dai.STR($1 $3) {' +` id STR($4)' +` }' +`' +` pcm."capture" {' +`' +` capabilities STR($5)' +` }' +`}') + +dnl PCM_DUPLEX_ADD(name, pipeline, pcm_id, dai_id, playback, capture) +define(`PCM_DUPLEX_ADD', +`SectionPCM.STR($1) {' +`' +` index STR($2)' +`' +` # used for binding to the PCM' +` id STR($3)' +`' +` dai.STR($1 $3) {' +` id STR($4)' +` }' +`' +` pcm."capture" {' +`' +` capabilities STR($6)' +` }' +`' +` pcm."playback" {' +`' +` capabilities STR($5)' +` }' +`}') + +divert(0)dnl diff --git a/topology/m4/pga.m4 b/topology/m4/pga.m4 new file mode 100644 index 0000000..f38f820 --- /dev/null +++ b/topology/m4/pga.m4 @@ -0,0 +1,44 @@ +divert(-1) + +dnl Define macro for PGA widget + +dnl PGA name) +define(`N_PGA', `PGA'PIPELINE_ID`.'$1) + +dnl W_PGA(name, format, periods_sink, periods_source, preload, kcontrol0. kcontrol1...etc) +define(`W_PGA', +`SectionVendorTuples."'N_PGA($1)`_tuples_w" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($4) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($5) +` }' +`}' +`SectionData."'N_PGA($1)`_data_w" {' +` tuples "'N_PGA($1)`_tuples_w"' +`}' +`SectionVendorTuples."'N_PGA($1)`_tuples_str" {' +` tokens "sof_comp_tokens"' +` tuples."string" {' +` SOF_TKN_COMP_FORMAT' STR($2) +` }' +`}' +`SectionData."'N_PGA($1)`_data_str" {' +` tuples "'N_PGA($1)`_tuples_str"' +`}' +`SectionWidget."'N_PGA($1)`" {' +` index "'PIPELINE_ID`"' +` type "pga"' +` no_pm "true"' +` data [' +` "'N_PGA($1)`_data_w"' +` "'N_PGA($1)`_data_str"' +` ]' +` mixer [' + $6 +` ]' + +`}') + +divert(0)dnl diff --git a/topology/m4/build.m4 b/topology/m4/pipeline.m4 similarity index 76% rename from topology/m4/build.m4 rename to topology/m4/pipeline.m4 index 9361219..7a91439 100644 --- a/topology/m4/build.m4 +++ b/topology/m4/pipeline.m4 @@ -1,5 +1,36 @@ divert(-1) +dnl Define macro for pipeline widget + +dnl Pipeline name) +define(`N_PIPELINE', `PIPELINE.'PIPELINE_ID`.'$1) + +dnl W_PIPELINE(stream, deadline, priority, frames, core, timer, platform) +define(`W_PIPELINE', +`SectionVendorTuples."'N_PIPELINE($1)`_tuples" {' +` tokens "sof_sched_tokens"' +` tuples."word" {' +` SOF_TKN_SCHED_DEADLINE' STR($2) +` SOF_TKN_SCHED_PRIORITY' STR($3) +` SOF_TKN_SCHED_CORE' STR($5) +` SOF_TKN_SCHED_FRAMES' STR($4) +` SOF_TKN_SCHED_TIMER' STR($6) +` }' +`}' +`SectionData."'N_PIPELINE($1)`_data" {' +` tuples "'N_PIPELINE($1)`_tuples"' +`}' +`SectionWidget."'N_PIPELINE($1)`" {' +` index "'PIPELINE_ID`"' +` type "scheduler"' +` no_pm "true"' +` stream_name "'$1`"' +` data [' +` "'N_PIPELINE($1)`_data"' +` "'$7`"' +` ]' +`}') + dnl PIPELINE_PCM_ADD(pipeline, dnl pipe id, pcm, max channels, format, dnl frames, deadline, priority, core, dmac, dmac_chan) @@ -85,33 +116,4 @@ define(`PIPELINE_ADD', `include($1)' ) -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, -dnl buffer, periods, format, -dnl frames, deadline, priority, core) -define(`DAI_ADD', -`undefine(`PIPELINE_ID')' -`undefine(`DAI_TYPE')' -`undefine(`DAI_INDEX')' -`undefine(`DAI_BUF')' -`undefine(`DAI_PERIODS')' -`undefine(`DAI_FORMAT')' -`undefine(`SCHEDULE_FRAMES')' -`undefine(`SCHEDULE_DEADLINE')' -`undefine(`SCHEDULE_PRIORITY')' -`undefine(`SCHEDULE_CORE')' -`define(`PIPELINE_ID', $2)' -`define(`DAI_TYPE', STR($3))' -`define(`DAI_INDEX', STR($4))' -`define(`DAI_BUF', $5)' -`define(`DAI_NAME', $3$4)' -`define(`DAI_PERIODS', $6)' -`define(`DAI_FORMAT', $7)' -`define(`SCHEDULE_FRAMES', $8)' -`define(`SCHEDULE_DEADLINE', $9)' -`define(`SCHEDULE_PRIORITY', $10)' -`define(`SCHEDULE_CORE', $11)' -`include($1)' -) - divert(0)dnl diff --git a/topology/m4/src.m4 b/topology/m4/src.m4 new file mode 100644 index 0000000..aca18e3 --- /dev/null +++ b/topology/m4/src.m4 @@ -0,0 +1,41 @@ +divert(-1) + +dnl Defines the macro for SRC widget + +dnl SRC name) +define(`N_SRC', `SRC'PIPELINE_ID`.'$1) + +dnl W_SRC(name, format, periods_sink, periods_source, data, preload) +define(`W_SRC', +`SectionVendorTuples."'N_SRC($1)`_tuples_w" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($4) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($6) +` }' +`}' +`SectionData."'N_SRC($1)`_data_w" {' +` tuples "'N_SRC($1)`_tuples_w"' +`}' +`SectionVendorTuples."'N_SRC($1)`_tuples_str" {' +` tokens "sof_comp_tokens"' +` tuples."string" {' +` SOF_TKN_COMP_FORMAT' STR($2) +` }' +`}' +`SectionData."'N_SRC($1)`_data_str" {' +` tuples "'N_SRC($1)`_tuples_str"' +`}' +`SectionWidget."'N_SRC($1)`" {' +` index "'PIPELINE_ID`"' +` type "src"' +` no_pm "true"' +` data [' +` "'N_SRC($1)`_data_w"' +` "'N_SRC($1)`_data_str"' +` "'$5`"' +` ]' +`}') + +divert(0)dnl diff --git a/topology/m4/tone.m4 b/topology/m4/tone.m4 new file mode 100644 index 0000000..6a88b37 --- /dev/null +++ b/topology/m4/tone.m4 @@ -0,0 +1,43 @@ +divert(-1) + +dnl Define macro for siggen widget + +dnl Tone name) +define(`N_TONE', `TONE'PIPELINE_ID`.'$1) + +dnl W_TONE(name, format, periods_sink, periods_source, preload, kcontrols_list) +define(`W_TONE', +`SectionVendorTuples."'N_TONE($1)`_tuples_w" {' +` tokens "sof_comp_tokens"' +` tuples."word" {' +` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3) +` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($4) +` SOF_TKN_COMP_PRELOAD_COUNT' STR($5) +` }' +`}' +`SectionData."'N_TONE($1)`_data_w" {' +` tuples "'N_TONE($1)`_tuples_w"' +`}' +`SectionVendorTuples."'N_TONE($1)`_tuples_str" {' +` tokens "sof_comp_tokens"' +` tuples."string" {' +` SOF_TKN_COMP_FORMAT' STR($2) +` }' +`}' +`SectionData."'N_TONE($1)`_data_str" {' +` tuples "'N_TONE($1)`_tuples_str"' +`}' +`SectionWidget."'N_TONE($1)`" {' +` index "'PIPELINE_ID`"' +` type "siggen"' +` no_pm "true"' +` data [' +` "'N_TONE($1)`_data_w"' +` "'N_TONE($1)`_data_str"' +` ]' +` mixer [' + $6 +` ]' +`}') + +divert(0)dnl diff --git a/topology/m4/utils.m4 b/topology/m4/utils.m4 new file mode 100644 index 0000000..e929244 --- /dev/null +++ b/topology/m4/utils.m4 @@ -0,0 +1,65 @@ +divert(-1) + +define(`concat',`$1$2') + +define(`STR', `"'$1`"') + +dnl Argument iterator. +define(`argn', `ifelse(`$1', 1, ``$2'', + `argn(decr(`$1'), shift(shift($@)))')') + +dnl Defines a list of items from a variable number of params. +dnl Use as last argument in a macro. +dnl The first argument specifies the number of tabs to be added for formatting +define(`LIST_LOOP', `argn(j,$@) +$1ifelse(i,`2', `', `define(`i', decr(i))define(`j', incr(j))$0($@)')') + +define(`LIST', `pushdef(`i', $#)pushdef(`j', `2')LIST_LOOP($@)popdef(i)popdef(j)') + +dnl Sums a list of variable arguments. Use as last argument in macro. +define(`SUM_LOOP', `eval(argn(j,$@) + ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) + $0($@)'))') + +dnl Memory capabilities +define(`MEMCAPS', `pushdef(`i', $#) pushdef(`j', `1') SUM_LOOP($@)') + +dnl create direct DAPM/pipeline link between 2 widgets) +define(`dapm', `"$1, , $2"') + +dnl COMP_SAMPLE_SIZE(FMT) +define(`COMP_SAMPLE_SIZE', +`ifelse( + $1, `s16le', `2', + $1, `s24_4le', `4', + $1, `s32le', `4', + $1, `float', `4', + `4')') + +dnl P_GRAPH(name, CONNECTIONS) +define(`P_GRAPH', +`SectionGraph.STR($1) {' +` index STR($2)' +`' +` lines [' +` $3' +` ]' +`}') + +dnl W_VENDORTUPLES(name, tokens, RATE_OUT) +define(`W_VENDORTUPLES', +`SectionVendorTuples.STR($1) {' +` tokens STR($2)' +`' +` tuples."word" {' +` $3' +` }' +`}') + +dnl W_DATA(name, tuples) +define(`W_DATA', +`SectionData.STR($1) {' +` tuples STR($2)' +`}') + +divert(0) dnl + diff --git a/topology/reef-apl-nocodec.m4 b/topology/reef-apl-nocodec.m4 index d4ac613..cf0a20e 100644 --- a/topology/reef-apl-nocodec.m4 +++ b/topology/reef-apl-nocodec.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`pipeline.m4') +include(`utils.m4') +include(`dai.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-bdw-rt286.m4 b/topology/reef-bdw-rt286.m4 index eaba2d9..fa894f6 100644 --- a/topology/reef-bdw-rt286.m4 +++ b/topology/reef-bdw-rt286.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`pipeline.m4') +include(`utils.m4') +include(`dai.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-bdw-rt5640.m4 b/topology/reef-bdw-rt5640.m4 index 5d4485b..ec920a5 100644 --- a/topology/reef-bdw-rt5640.m4 +++ b/topology/reef-bdw-rt5640.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-bxt-nocodec.m4 b/topology/reef-bxt-nocodec.m4 index dbac98a..b7717d0 100644 --- a/topology/reef-bxt-nocodec.m4 +++ b/topology/reef-bxt-nocodec.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-byt-da7212.m4 b/topology/reef-byt-da7212.m4 index 840ea69..7515c63 100644 --- a/topology/reef-byt-da7212.m4 +++ b/topology/reef-byt-da7212.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-byt-nocodec.m4 b/topology/reef-byt-nocodec.m4 index 56aee22..b3ca196 100644 --- a/topology/reef-byt-nocodec.m4 +++ b/topology/reef-byt-nocodec.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`pipeline.m4') +include(`utils.m4') +include(`dai.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-byt-rt5640.m4 b/topology/reef-byt-rt5640.m4 index f8d0e40..9fa15a2 100644 --- a/topology/reef-byt-rt5640.m4 +++ b/topology/reef-byt-rt5640.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-byt-rt5645.m4 b/topology/reef-byt-rt5645.m4 index 023d92d..c81a4db 100644 --- a/topology/reef-byt-rt5645.m4 +++ b/topology/reef-byt-rt5645.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-byt-rt5651.m4 b/topology/reef-byt-rt5651.m4 index ccac260..96147d3 100644 --- a/topology/reef-byt-rt5651.m4 +++ b/topology/reef-byt-rt5651.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-cht-max98090.m4 b/topology/reef-cht-max98090.m4 index 3218402..5690df4 100644 --- a/topology/reef-cht-max98090.m4 +++ b/topology/reef-cht-max98090.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-cht-nocodec.m4 b/topology/reef-cht-nocodec.m4 index 24560ee..32acb62 100644 --- a/topology/reef-cht-nocodec.m4 +++ b/topology/reef-cht-nocodec.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`pipeline.m4') +include(`utils.m4') +include(`dai.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-cnl-rt274.m4 b/topology/reef-cnl-rt274.m4 index f91a74f..e95363b 100644 --- a/topology/reef-cnl-rt274.m4 +++ b/topology/reef-cnl-rt274.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/reef-hsw-rt5640.m4 b/topology/reef-hsw-rt5640.m4 index 663686b..1f63820 100644 --- a/topology/reef-hsw-rt5640.m4 +++ b/topology/reef-hsw-rt5640.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/sof/pipe-dai-capture.m4 b/topology/sof/pipe-dai-capture.m4 index 3699138..a5a72d0 100644 --- a/topology/sof/pipe-dai-capture.m4 +++ b/topology/sof/pipe-dai-capture.m4 @@ -1,7 +1,9 @@ # DAI Capture connector # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # # DAI definitions diff --git a/topology/sof/pipe-dai-playback.m4 b/topology/sof/pipe-dai-playback.m4 index d35d3b1..e70998b 100644 --- a/topology/sof/pipe-dai-playback.m4 +++ b/topology/sof/pipe-dai-playback.m4 @@ -1,7 +1,9 @@ # DAI Playback connector # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') # # DAI definitions diff --git a/topology/sof/pipe-low-latency-capture.m4 b/topology/sof/pipe-low-latency-capture.m4 index 7adfd14..5619999 100644 --- a/topology/sof/pipe-low-latency-capture.m4 +++ b/topology/sof/pipe-low-latency-capture.m4 @@ -5,7 +5,11 @@ # host PCM_C <--B5-- volume(0C) <--B4-- source DAI0 # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`pga.m4') +include(`mixercontrol.m4') # # Controls diff --git a/topology/sof/pipe-low-latency-playback.m4 b/topology/sof/pipe-low-latency-playback.m4 index 11cf07d..4a4fca9 100644 --- a/topology/sof/pipe-low-latency-playback.m4 +++ b/topology/sof/pipe-low-latency-playback.m4 @@ -20,7 +20,12 @@ # # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`pga.m4') +include(`mixer.m4') +include(`mixercontrol.m4') # # Controls diff --git a/topology/sof/pipe-passthrough-capture.m4 b/topology/sof/pipe-passthrough-capture.m4 index cfa357a..a13887a 100644 --- a/topology/sof/pipe-passthrough-capture.m4 +++ b/topology/sof/pipe-passthrough-capture.m4 @@ -5,8 +5,11 @@ # host PCM_C <-- B0 <-- sink DAI0 # Include topology builder -include(`local.m4') - +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`dai.m4') +include(`pipeline.m4') # # Components and Buffers diff --git a/topology/sof/pipe-passthrough-playback.m4 b/topology/sof/pipe-passthrough-playback.m4 index 3218431..8a9e8ff 100644 --- a/topology/sof/pipe-passthrough-playback.m4 +++ b/topology/sof/pipe-passthrough-playback.m4 @@ -5,8 +5,11 @@ # host PCM_P --> B0 --> sink DAI0 # Include topology builder -include(`local.m4') - +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`dai.m4') +include(`pipeline.m4') # # Components and Buffers diff --git a/topology/sof/pipe-pcm-media.m4 b/topology/sof/pipe-pcm-media.m4 index 0196f98..f2053b7 100644 --- a/topology/sof/pipe-pcm-media.m4 +++ b/topology/sof/pipe-pcm-media.m4 @@ -8,7 +8,12 @@ # # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`src.m4') +include(`buffer.m4') +include(`pga.m4') +include(`mixercontrol.m4') +include(`pipeline.m4') # # Controls diff --git a/topology/sof/pipe-src-capture.m4 b/topology/sof/pipe-src-capture.m4 index 824dcdb..a58eb68 100644 --- a/topology/sof/pipe-src-capture.m4 +++ b/topology/sof/pipe-src-capture.m4 @@ -5,8 +5,12 @@ # host PCM_P --> SRC --> sink DAI0 # Include topology builder -include(`local.m4') - +include(`utils.m4') +include(`src.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`dai.m4') +include(`pipeline.m4') # # Components and Buffers diff --git a/topology/sof/pipe-src-playback.m4 b/topology/sof/pipe-src-playback.m4 index 3009ff7..7bf8f47 100644 --- a/topology/sof/pipe-src-playback.m4 +++ b/topology/sof/pipe-src-playback.m4 @@ -5,8 +5,12 @@ # host PCM_P --> SRC --> sink DAI0 # Include topology builder -include(`local.m4') - +include(`utils.m4') +include(`src.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`dai.m4') +include(`pipeline.m4') # # Components and Buffers diff --git a/topology/sof/pipe-tone.m4 b/topology/sof/pipe-tone.m4 index 899c426..09ed32c 100644 --- a/topology/sof/pipe-tone.m4 +++ b/topology/sof/pipe-tone.m4 @@ -8,7 +8,12 @@ # # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`buffer.m4') +include(`pga.m4') +include(`tone.m4') +include(`mixercontrol.m4') +include(`pipeline.m4') # # Controls diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 299a0f8..5aa0d12 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -5,7 +5,13 @@ # host PCM_C <-- B0 <-- Volume 0 <-- B1 <-- source DAI0 # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`pga.m4') +include(`dai.m4') +include(`mixercontrol.m4') +include(`pipeline.m4') # # Controls diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index 3e3f98e..90fe303 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -5,7 +5,13 @@ # host PCM_P --> B0 --> Volume 0 --> B1 --> sink DAI0 # Include topology builder -include(`local.m4') +include(`utils.m4') +include(`buffer.m4') +include(`pcm.m4') +include(`pga.m4') +include(`dai.m4') +include(`mixercontrol.m4') +include(`pipeline.m4') # # Controls diff --git a/topology/test/test-capture-ssp.m4 b/topology/test/test-capture-ssp.m4 index 2c808ba..8950222 100644 --- a/topology/test/test-capture-ssp.m4 +++ b/topology/test/test-capture-ssp.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`dai.m4') +include(`utils.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/test/test-playback-ssp.m4 b/topology/test/test-playback-ssp.m4 index 093ad17..db6cb6c 100644 --- a/topology/test/test-playback-ssp.m4 +++ b/topology/test/test-playback-ssp.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`pipeline.m4') +include(`dai.m4') +include(`utils.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/test/test-ssp.m4 b/topology/test/test-ssp.m4 index 304aab9..01e3a02 100644 --- a/topology/test/test-ssp.m4 +++ b/topology/test/test-ssp.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`dai.m4') +include(`utils.m4') +include(`pipeline.m4') # Include TLV library include(`common/tlv.m4') diff --git a/topology/test/test-tone-playback-ssp.m4 b/topology/test/test-tone-playback-ssp.m4 index 2fe6693..9231316 100644 --- a/topology/test/test-tone-playback-ssp.m4 +++ b/topology/test/test-tone-playback-ssp.m4 @@ -3,8 +3,9 @@ # # Include topology builder -include(`local.m4') -include(`build.m4') +include(`pipeline.m4') +include(`dai.m4') +include(`utils.m4') # Include TLV library include(`common/tlv.m4') -- 2.14.1

2 1

[Sound-open-firmware] [PATCH] dma: dw-dma: fix wrong memory capabilities flags
by Xiuli Pan 06 Mar '18

06 Mar '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> Runtime heap does not support DMA, fix this bug. Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- Test with: Mininow max rt5651 and GP-MRB with Nocodec SOF master: e92ef97834489f52c0f20445d401a8c6e0aaed62 SOF-Tool master: 5b8dfd13019cfd29999503b56c902f56209000ed https://github.com/plbossart/sound/tree/topic/sof-v4.14: d919ea06b7f79c95ab4eb68baf05e9faf3a894c1 --- src/drivers/dw-dma.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index c2d6917..18e4583 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -552,9 +552,9 @@ static int dw_dma_set_config(struct dma *dma, int channel, /* allocate descriptors for channel */ if (p->chan[channel].lli) rfree(p->chan[channel].lli); - p->chan[channel].lli = rzalloc(RZONE_RUNTIME, - SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, - sizeof(struct dw_lli2) * p->chan[channel].desc_count); + p->chan[channel].lli = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, + sizeof(struct dw_lli2) * + p->chan[channel].desc_count); if (p->chan[channel].lli == NULL) { trace_dma_error("eD1"); ret = -ENOMEM; -- 2.7.4

2 1

[Sound-open-firmware] [PATCH V3 1/2] ASoc: SOF: Add memory window for all platform
by Xiuli Pan 06 Mar '18

06 Mar '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> Add memory window handler for BYT, HSW and BDW. Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- Test with: Mininow max rt5651 GP-MRB nocodec SOF master: 1693b66bb1d804ded975767cc1e5911e6ff9c93c SOF-Tool master: a02abb799405d0e4ad0d6bb46eacf6fbe958c06e https://github.com/plbossart/sound/tree/topic/sof-v4.14: 9513a73b981bc1917705671ec54402a7e21672eb --- sound/soc/sof/hw-apl.c | 11 +++++-- sound/soc/sof/hw-bdw.c | 86 ++++++++++++++++++++++++++++++++++++++++++------- sound/soc/sof/hw-byt.c | 87 +++++++++++++++++++++++++++++++++++++++++++------- sound/soc/sof/hw-hsw.c | 85 +++++++++++++++++++++++++++++++++++++++++------- 4 files changed, 233 insertions(+), 36 deletions(-) diff --git a/sound/soc/sof/hw-apl.c b/sound/soc/sof/hw-apl.c index bfbdd915..de0efe1 100644 --- a/sound/soc/sof/hw-apl.c +++ b/sound/soc/sof/hw-apl.c @@ -1089,9 +1089,13 @@ static int apl_prepare(struct snd_sof_dev *sdev, unsigned int format, static void apl_get_windows(struct snd_sof_dev *sdev) { struct sof_ipc_window_elem *elem; + u32 outbox_offset = 0; + u32 stream_offset = 0; + u32 inbox_offset = 0; + u32 outbox_size = 0; + u32 stream_size = 0; + u32 inbox_size = 0; int i; - u32 inbox_offset = 0, outbox_offset = 0; - u32 inbox_size = 0, outbox_size = 0; if (!sdev->info_window) return; @@ -1135,6 +1139,9 @@ static void apl_get_windows(struct snd_sof_dev *sdev) elem->size, "debug"); break; case SOF_IPC_REGION_STREAM: + stream_offset = + elem->offset + SRAM_WINDOW_OFFSET(elem->id); + stream_size = elem->size; snd_sof_debugfs_create_item(sdev, sdev->bar[APL_DSP_BAR] + elem->offset + diff --git a/sound/soc/sof/hw-bdw.c b/sound/soc/sof/hw-bdw.c index bc3141f..5ec0c5b 100644 --- a/sound/soc/sof/hw-bdw.c +++ b/sound/soc/sof/hw-bdw.c @@ -63,7 +63,6 @@ static const struct snd_sof_debugfs_map bdw_debugfs[] = { {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE}, {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE}, {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE}, - {"mbox", BDW_DSP_BAR, MBOX_OFFSET, MBOX_SIZE}, }; /* @@ -379,6 +378,75 @@ static irqreturn_t bdw_irq_thread(int irq, void *context) /* * IPC Firmware ready. */ +static void bdw_get_windows(struct snd_sof_dev *sdev) +{ + struct sof_ipc_window_elem *elem; + u32 outbox_offset = 0; + u32 stream_offset = 0; + u32 inbox_offset = 0; + u32 outbox_size = 0; + u32 stream_size = 0; + u32 inbox_size = 0; + int i; + + if (sdev->info_window == NULL) + return; + + for (i = 0; i < sdev->info_window->num_windows; i++) { + + elem = &sdev->info_window->window[i]; + + switch (elem->type) { + case SOF_IPC_REGION_UPBOX: + inbox_offset = elem->offset + MBOX_OFFSET; + inbox_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[BDW_DSP_BAR] + inbox_offset, + elem->size, "inbox"); + break; + case SOF_IPC_REGION_DOWNBOX: + outbox_offset = elem->offset + MBOX_OFFSET; + outbox_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[BDW_DSP_BAR] + outbox_offset, + elem->size, "outbox"); + break; + case SOF_IPC_REGION_TRACE: + snd_sof_debugfs_create_item(sdev, + sdev->bar[BDW_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "etrace"); + break; + case SOF_IPC_REGION_DEBUG: + snd_sof_debugfs_create_item(sdev, + sdev->bar[BDW_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "debug"); + break; + case SOF_IPC_REGION_STREAM: + stream_offset = elem->offset + MBOX_OFFSET; + stream_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[BDW_DSP_BAR] + stream_offset, + elem->size, "stream"); + break; + case SOF_IPC_REGION_REGS: + snd_sof_debugfs_create_item(sdev, + sdev->bar[BDW_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "regs"); + break; + default: + break; + } + } + + snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size, + outbox_offset, outbox_size); + + dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n", + inbox_offset, inbox_size); + dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n", + outbox_offset, outbox_size); +} + static int bdw_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) { struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready; @@ -394,19 +462,15 @@ static int bdw_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) /* copy data from the DSP FW ready offset */ bdw_block_read(sdev, offset, fw_ready, sizeof(*fw_ready)); - snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset, - fw_ready->dspbox_size, - fw_ready->hostbox_offset, - fw_ready->hostbox_size); - - dev_dbg(sdev->dev, " mailbox DSP initiated 0x%x - size 0x%x\n", - fw_ready->dspbox_offset, fw_ready->dspbox_size); - dev_dbg(sdev->dev, " mailbox Host initiated 0x%x - size 0x%x\n", - fw_ready->hostbox_offset, fw_ready->hostbox_size); - dev_info(sdev->dev, " Firmware info: version %d:%d-%s build %d on %s:%s\n", v->major, v->minor, v->tag, v->build, v->date, v->time); + /* now check for extended data */ + snd_sof_fw_parse_ext_data(sdev, + MBOX_OFFSET + sizeof(struct sof_ipc_fw_ready)); + + bdw_get_windows(sdev); + return 0; } diff --git a/sound/soc/sof/hw-byt.c b/sound/soc/sof/hw-byt.c index 209f72a..031cec6 100644 --- a/sound/soc/sof/hw-byt.c +++ b/sound/soc/sof/hw-byt.c @@ -73,7 +73,6 @@ static const struct snd_sof_debugfs_map byt_debugfs[] = { {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE}, {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE}, {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE}, - {"mbox", BYT_DSP_BAR, MBOX_OFFSET, MBOX_SIZE}, }; static const struct snd_sof_debugfs_map cht_debugfs[] = { @@ -89,7 +88,6 @@ static const struct snd_sof_debugfs_map cht_debugfs[] = { {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE}, {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE}, {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE}, - {"mbox", BYT_DSP_BAR, MBOX_OFFSET, MBOX_SIZE}, }; static void byt_dump(struct snd_sof_dev *sdev, u32 flags) @@ -197,6 +195,75 @@ static void byt_block_read(struct snd_sof_dev *sdev, u32 offset, void *dest, /* * IPC Firmware ready. */ +static void byt_get_windows(struct snd_sof_dev *sdev) +{ + struct sof_ipc_window_elem *elem; + u32 outbox_offset = 0; + u32 stream_offset = 0; + u32 inbox_offset = 0; + u32 outbox_size = 0; + u32 stream_size = 0; + u32 inbox_size = 0; + int i; + + if (sdev->info_window == NULL) + return; + + for (i = 0; i < sdev->info_window->num_windows; i++) { + + elem = &sdev->info_window->window[i]; + + switch (elem->type) { + case SOF_IPC_REGION_UPBOX: + inbox_offset = elem->offset + MBOX_OFFSET; + inbox_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[BYT_DSP_BAR] + inbox_offset, + elem->size, "inbox"); + break; + case SOF_IPC_REGION_DOWNBOX: + outbox_offset = elem->offset + MBOX_OFFSET; + outbox_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[BYT_DSP_BAR] + outbox_offset, + elem->size, "outbox"); + break; + case SOF_IPC_REGION_TRACE: + snd_sof_debugfs_create_item(sdev, + sdev->bar[BYT_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "etrace"); + break; + case SOF_IPC_REGION_DEBUG: + snd_sof_debugfs_create_item(sdev, + sdev->bar[BYT_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "debug"); + break; + case SOF_IPC_REGION_STREAM: + stream_offset = elem->offset + MBOX_OFFSET; + stream_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[BYT_DSP_BAR] + stream_offset, + elem->size, "stream"); + break; + case SOF_IPC_REGION_REGS: + snd_sof_debugfs_create_item(sdev, + sdev->bar[BYT_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "regs"); + break; + default: + break; + } + } + + snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size, + outbox_offset, outbox_size); + + dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n", + inbox_offset, inbox_size); + dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n", + outbox_offset, outbox_size); +} + static int byt_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) { struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready; @@ -212,19 +279,15 @@ static int byt_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) /* copy data from the DSP FW ready offset */ byt_block_read(sdev, offset, fw_ready, sizeof(*fw_ready)); - snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset, - fw_ready->dspbox_size, - fw_ready->hostbox_offset, - fw_ready->hostbox_size); - - dev_dbg(sdev->dev, " mailbox DSP initiated 0x%x - size 0x%x\n", - fw_ready->dspbox_offset, fw_ready->dspbox_size); - dev_dbg(sdev->dev, " mailbox Host initiated 0x%x - size 0x%x\n", - fw_ready->hostbox_offset, fw_ready->hostbox_size); - dev_info(sdev->dev, " Firmware info: version %d:%d-%s build %d on %s:%s\n", v->major, v->minor, v->tag, v->build, v->date, v->time); + /* now check for extended data */ + snd_sof_fw_parse_ext_data(sdev, + MBOX_OFFSET + sizeof(struct sof_ipc_fw_ready)); + + byt_get_windows(sdev); + return 0; } diff --git a/sound/soc/sof/hw-hsw.c b/sound/soc/sof/hw-hsw.c index c6366bb..2f36216 100644 --- a/sound/soc/sof/hw-hsw.c +++ b/sound/soc/sof/hw-hsw.c @@ -63,7 +63,6 @@ static const struct snd_sof_debugfs_map hsw_debugfs[] = { {"iram", HSW_DSP_BAR, IRAM_OFFSET, HSW_IRAM_SIZE}, {"dram", HSW_DSP_BAR, DRAM_OFFSET, HSW_DRAM_SIZE}, {"shim", HSW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE}, - {"mbox", HSW_DSP_BAR, MBOX_OFFSET, MBOX_SIZE}, }; /* @@ -380,6 +379,75 @@ static irqreturn_t hsw_irq_thread(int irq, void *context) /* * IPC Firmware ready. */ +static void hsw_get_windows(struct snd_sof_dev *sdev) +{ + struct sof_ipc_window_elem *elem; + u32 outbox_offset = 0; + u32 stream_offset = 0; + u32 inbox_offset = 0; + u32 outbox_size = 0; + u32 stream_size = 0; + u32 inbox_size = 0; + int i; + + if (sdev->info_window == NULL) + return; + + for (i = 0; i < sdev->info_window->num_windows; i++) { + + elem = &sdev->info_window->window[i]; + + switch (elem->type) { + case SOF_IPC_REGION_UPBOX: + inbox_offset = elem->offset + MBOX_OFFSET; + inbox_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[HSW_DSP_BAR] + inbox_offset, + elem->size, "inbox"); + break; + case SOF_IPC_REGION_DOWNBOX: + outbox_offset = elem->offset + MBOX_OFFSET; + outbox_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[HSW_DSP_BAR] + outbox_offset, + elem->size, "outbox"); + break; + case SOF_IPC_REGION_TRACE: + snd_sof_debugfs_create_item(sdev, + sdev->bar[HSW_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "etrace"); + break; + case SOF_IPC_REGION_DEBUG: + snd_sof_debugfs_create_item(sdev, + sdev->bar[HSW_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "debug"); + break; + case SOF_IPC_REGION_STREAM: + stream_offset = elem->offset + MBOX_OFFSET; + stream_size = elem->size; + snd_sof_debugfs_create_item(sdev, + sdev->bar[HSW_DSP_BAR] + stream_offset, + elem->size, "stream"); + break; + case SOF_IPC_REGION_REGS: + snd_sof_debugfs_create_item(sdev, + sdev->bar[HSW_DSP_BAR] + elem->offset + + MBOX_OFFSET, elem->size, "regs"); + break; + default: + break; + } + } + + snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size, + outbox_offset, outbox_size); + + dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n", + inbox_offset, inbox_size); + dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n", + outbox_offset, outbox_size); +} + static int hsw_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) { struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready; @@ -395,18 +463,13 @@ static int hsw_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) /* copy data from the DSP FW ready offset */ hsw_block_read(sdev, offset, fw_ready, sizeof(*fw_ready)); - snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset, - fw_ready->dspbox_size, - fw_ready->hostbox_offset, - fw_ready->hostbox_size); - - dev_dbg(sdev->dev, " mailbox DSP initiated 0x%x - size 0x%x\n", - fw_ready->dspbox_offset, fw_ready->dspbox_size); - dev_dbg(sdev->dev, " mailbox Host initiated 0x%x - size 0x%x\n", - fw_ready->hostbox_offset, fw_ready->hostbox_size); - dev_info(sdev->dev, " Firmware info: version %d:%d-%s build %d on %s:%s\n", v->major, v->minor, v->tag, v->build, v->date, v->time); + /* now check for extended data */ + snd_sof_fw_parse_ext_data(sdev, + MBOX_OFFSET + sizeof(struct sof_ipc_fw_ready)); + + hsw_get_windows(sdev); return 0; } -- 2.7.4

5 15

[Sound-open-firmware] [PATCH v4 1/8] topology: make list loop more generic with formatting argument
by Ranjani Sridharan 05 Mar '18

05 Mar '18

This patch adds changes to make list loop more generic with format argument Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- topology/m4/local.m4 | 13 ++++++++----- topology/sof/pipe-low-latency-capture.m4 | 2 +- topology/sof/pipe-low-latency-playback.m4 | 4 ++-- topology/sof/pipe-pcm-media.m4 | 2 +- topology/sof/pipe-tone.m4 | 3 ++- topology/sof/pipe-volume-capture.m4 | 2 +- topology/sof/pipe-volume-playback.m4 | 2 +- 7 files changed, 16 insertions(+), 12 deletions(-) diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 index 31221f3..1ebe19d 100644 --- a/topology/m4/local.m4 +++ b/topology/m4/local.m4 @@ -10,16 +10,16 @@ define(`argn', `ifelse(`$1', 1, ``$2'', dnl Defines a list of items from a variable number of params. dnl Use as last argument in a macro. +dnl The first argument specifies the number of tabs to be added for formatting define(`LIST_LOOP', `argn(j,$@) - ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) $0($@)')') +$1ifelse(i,`2', `', `define(`i', decr(i))define(`j', incr(j))$0($@)')') + +define(`LIST', `pushdef(`i', $#)pushdef(`j', `2')LIST_LOOP($@)popdef(i)popdef(j)') dnl Sums a list of variable arguments. Use as last argument in macro. define(`SUM_LOOP', `eval(argn(j,$@) ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) + $0($@)'))') -dnl Support a varaible list of kcontrols. -define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') LIST_LOOP($@)') - dnl Memory capabilities define(`MEMCAPS', `pushdef(`i', $#) pushdef(`j', `1') SUM_LOOP($@)') @@ -165,7 +165,7 @@ define(`N_PGA', `PGA'PIPELINE_ID`.'$1) dnl W_PGA(name, format, periods_sink, periods_source, preload, kcontrol0. kcontrol1...etc) define(`W_PGA', -`pushdef(`args',`eval($#-6)')SectionVendorTuples."'N_PGA($1)`_tuples_w" {' +`SectionVendorTuples."'N_PGA($1)`_tuples_w" {' ` tokens "sof_comp_tokens"' ` tuples."word" {' ` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3) @@ -270,6 +270,9 @@ define(`W_TONE', ` "'N_TONE($1)`_data_w"' ` "'N_TONE($1)`_data_str"' ` ]' +` mixer [' + $6 +` ]' `}') dnl DAI name) diff --git a/topology/sof/pipe-low-latency-capture.m4 b/topology/sof/pipe-low-latency-capture.m4 index 41fc622..6bb1a3d 100644 --- a/topology/sof/pipe-low-latency-capture.m4 +++ b/topology/sof/pipe-low-latency-capture.m4 @@ -48,7 +48,7 @@ SectionControlMixer.STR(PCM PCM_ID Capture Volume) { W_PCM_CAPTURE(Low Latency Capture, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 0, 2, 0) # "Capture Volume" has 2 sink and source periods for host and DAI ping-pong -W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("PCM PCM_ID Capture Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, LIST(` ', "PCM PCM_ID Capture Volume")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, diff --git a/topology/sof/pipe-low-latency-playback.m4 b/topology/sof/pipe-low-latency-playback.m4 index 37f8be2..64761a9 100644 --- a/topology/sof/pipe-low-latency-playback.m4 +++ b/topology/sof/pipe-low-latency-playback.m4 @@ -91,10 +91,10 @@ SectionControlMixer.STR(Master Playback Volume) { W_PCM_PLAYBACK(Low Latency Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2) # "Playback Volume" has 1 sink period and 2 source periods for host ping-pong -W_PGA(0, PIPELINE_FORMAT, 1, 2, 1, KCONTROLS("PCM PCM_ID Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, 1, 2, 1, LIST(` ', "PCM PCM_ID Playback Volume")) # "Master Playback Volume" has 1 source and 2 sink periods for DAI ping-pong -W_PGA(1, PIPELINE_FORMAT, 2, 1, 1, KCONTROLS("Master Playback Volume")) +W_PGA(1, PIPELINE_FORMAT, 2, 1, 1, LIST(` ', "Master Playback Volume")) # Mixer 0 has 1 sink and source periods. W_MIXER(0, PIPELINE_FORMAT, 1, 1, 1) diff --git a/topology/sof/pipe-pcm-media.m4 b/topology/sof/pipe-pcm-media.m4 index 1766aca..c1cff33 100644 --- a/topology/sof/pipe-pcm-media.m4 +++ b/topology/sof/pipe-pcm-media.m4 @@ -68,7 +68,7 @@ SectionData."media_src_conf" { W_PCM_PLAYBACK(Media Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2) # "Playback Volume" has 2 sink period and 2 source periods for host ping-pong -W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("PCM PCM_ID Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "PCM PCM_ID Playback Volume")) # "SRC 0" has 2 sink and source periods. W_SRC(0, PIPELINE_FORMAT, 2, 2, media_src_conf, 2) diff --git a/topology/sof/pipe-tone.m4 b/topology/sof/pipe-tone.m4 index a8064ab..f53f77f 100644 --- a/topology/sof/pipe-tone.m4 +++ b/topology/sof/pipe-tone.m4 @@ -32,6 +32,7 @@ SectionControlMixer.STR(Tone Volume PIPELINE_ID) { # control uses bespoke driver get/put/info ID 0 ops."ctl" { info "volsw" + # 256 binds the mixer control to volume get/put handlers get "256" put "256" } @@ -50,7 +51,7 @@ SectionControlMixer.STR(Tone Volume PIPELINE_ID) { W_TONE(0, PIPELINE_FORMAT, 2, 0, 0) # "Tone Volume" has 2 sink period and 2 source periods -W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("Tone Volume PIPELINE_ID")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, LIST(` ', "Tone Volume PIPELINE_ID")) # Low Latency Buffers W_BUFFER(0,COMP_BUFFER_SIZE(2, diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 2fd6b98..56494b4 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -47,7 +47,7 @@ SectionControlMixer.STR(Master Capture Volume) { W_PCM_CAPTURE(Passthrough Capture, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 0, 2, 2) # "Volume" has 2 source and 2 sink periods -W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Capture Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "Master Capture Volume")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index 9431177..24ae45c 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -73,7 +73,7 @@ SectionControlMixer.STR(Master Playback Volume Switch) { W_PCM_PLAYBACK(Passthrough Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2) # "Volume" has 2 source and 2 sink periods -W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Playback Volume Switch", "Master Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "Master Playback Volume Switch", "Master Playback Volume")) # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, -- 2.14.1

1 7

[Sound-open-firmware] [PATCH v3 1/8] topology: make list loop more generic with formatting argument
by Ranjani Sridharan 05 Mar '18

05 Mar '18

This patch adds changes to make list loop more generic with format argument Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- topology/m4/local.m4 | 13 ++++++++----- topology/sof/pipe-low-latency-capture.m4 | 2 +- topology/sof/pipe-low-latency-playback.m4 | 4 ++-- topology/sof/pipe-pcm-media.m4 | 2 +- topology/sof/pipe-tone.m4 | 3 ++- topology/sof/pipe-volume-capture.m4 | 2 +- topology/sof/pipe-volume-playback.m4 | 2 +- 7 files changed, 16 insertions(+), 12 deletions(-) diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 index 31221f3..1ebe19d 100644 --- a/topology/m4/local.m4 +++ b/topology/m4/local.m4 @@ -10,16 +10,16 @@ define(`argn', `ifelse(`$1', 1, ``$2'', dnl Defines a list of items from a variable number of params. dnl Use as last argument in a macro. +dnl The first argument specifies the number of tabs to be added for formatting define(`LIST_LOOP', `argn(j,$@) - ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) $0($@)')') +$1ifelse(i,`2', `', `define(`i', decr(i))define(`j', incr(j))$0($@)')') + +define(`LIST', `pushdef(`i', $#)pushdef(`j', `2')LIST_LOOP($@)popdef(i)popdef(j)') dnl Sums a list of variable arguments. Use as last argument in macro. define(`SUM_LOOP', `eval(argn(j,$@) ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) + $0($@)'))') -dnl Support a varaible list of kcontrols. -define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') LIST_LOOP($@)') - dnl Memory capabilities define(`MEMCAPS', `pushdef(`i', $#) pushdef(`j', `1') SUM_LOOP($@)') @@ -165,7 +165,7 @@ define(`N_PGA', `PGA'PIPELINE_ID`.'$1) dnl W_PGA(name, format, periods_sink, periods_source, preload, kcontrol0. kcontrol1...etc) define(`W_PGA', -`pushdef(`args',`eval($#-6)')SectionVendorTuples."'N_PGA($1)`_tuples_w" {' +`SectionVendorTuples."'N_PGA($1)`_tuples_w" {' ` tokens "sof_comp_tokens"' ` tuples."word" {' ` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3) @@ -270,6 +270,9 @@ define(`W_TONE', ` "'N_TONE($1)`_data_w"' ` "'N_TONE($1)`_data_str"' ` ]' +` mixer [' + $6 +` ]' `}') dnl DAI name) diff --git a/topology/sof/pipe-low-latency-capture.m4 b/topology/sof/pipe-low-latency-capture.m4 index 41fc622..6bb1a3d 100644 --- a/topology/sof/pipe-low-latency-capture.m4 +++ b/topology/sof/pipe-low-latency-capture.m4 @@ -48,7 +48,7 @@ SectionControlMixer.STR(PCM PCM_ID Capture Volume) { W_PCM_CAPTURE(Low Latency Capture, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 0, 2, 0) # "Capture Volume" has 2 sink and source periods for host and DAI ping-pong -W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("PCM PCM_ID Capture Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, LIST(` ', "PCM PCM_ID Capture Volume")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, diff --git a/topology/sof/pipe-low-latency-playback.m4 b/topology/sof/pipe-low-latency-playback.m4 index 37f8be2..64761a9 100644 --- a/topology/sof/pipe-low-latency-playback.m4 +++ b/topology/sof/pipe-low-latency-playback.m4 @@ -91,10 +91,10 @@ SectionControlMixer.STR(Master Playback Volume) { W_PCM_PLAYBACK(Low Latency Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2) # "Playback Volume" has 1 sink period and 2 source periods for host ping-pong -W_PGA(0, PIPELINE_FORMAT, 1, 2, 1, KCONTROLS("PCM PCM_ID Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, 1, 2, 1, LIST(` ', "PCM PCM_ID Playback Volume")) # "Master Playback Volume" has 1 source and 2 sink periods for DAI ping-pong -W_PGA(1, PIPELINE_FORMAT, 2, 1, 1, KCONTROLS("Master Playback Volume")) +W_PGA(1, PIPELINE_FORMAT, 2, 1, 1, LIST(` ', "Master Playback Volume")) # Mixer 0 has 1 sink and source periods. W_MIXER(0, PIPELINE_FORMAT, 1, 1, 1) diff --git a/topology/sof/pipe-pcm-media.m4 b/topology/sof/pipe-pcm-media.m4 index 1766aca..c1cff33 100644 --- a/topology/sof/pipe-pcm-media.m4 +++ b/topology/sof/pipe-pcm-media.m4 @@ -68,7 +68,7 @@ SectionData."media_src_conf" { W_PCM_PLAYBACK(Media Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2) # "Playback Volume" has 2 sink period and 2 source periods for host ping-pong -W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("PCM PCM_ID Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "PCM PCM_ID Playback Volume")) # "SRC 0" has 2 sink and source periods. W_SRC(0, PIPELINE_FORMAT, 2, 2, media_src_conf, 2) diff --git a/topology/sof/pipe-tone.m4 b/topology/sof/pipe-tone.m4 index a8064ab..f53f77f 100644 --- a/topology/sof/pipe-tone.m4 +++ b/topology/sof/pipe-tone.m4 @@ -32,6 +32,7 @@ SectionControlMixer.STR(Tone Volume PIPELINE_ID) { # control uses bespoke driver get/put/info ID 0 ops."ctl" { info "volsw" + # 256 binds the mixer control to volume get/put handlers get "256" put "256" } @@ -50,7 +51,7 @@ SectionControlMixer.STR(Tone Volume PIPELINE_ID) { W_TONE(0, PIPELINE_FORMAT, 2, 0, 0) # "Tone Volume" has 2 sink period and 2 source periods -W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("Tone Volume PIPELINE_ID")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, LIST(` ', "Tone Volume PIPELINE_ID")) # Low Latency Buffers W_BUFFER(0,COMP_BUFFER_SIZE(2, diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 2fd6b98..56494b4 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -47,7 +47,7 @@ SectionControlMixer.STR(Master Capture Volume) { W_PCM_CAPTURE(Passthrough Capture, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 0, 2, 2) # "Volume" has 2 source and 2 sink periods -W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Capture Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "Master Capture Volume")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index 9431177..24ae45c 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -73,7 +73,7 @@ SectionControlMixer.STR(Master Playback Volume Switch) { W_PCM_PLAYBACK(Passthrough Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2) # "Volume" has 2 source and 2 sink periods -W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Playback Volume Switch", "Master Playback Volume")) +W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "Master Playback Volume Switch", "Master Playback Volume")) # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, -- 2.14.1

1 7

[Sound-open-firmware] [PATCH] topology: stringify buffer caps.
by Liam Girdwood 05 Mar '18

05 Mar '18

Needs to be string for proper alsa-conf parsing. Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- topology/m4/local.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 index 14d742d..31221f3 100644 --- a/topology/m4/local.m4 +++ b/topology/m4/local.m4 @@ -71,7 +71,7 @@ define(`W_BUFFER', ` tokens "sof_buffer_tokens"' ` tuples."word" {' ` SOF_TKN_BUF_SIZE' STR($2) -` SOF_TKN_BUF_CAPS' $3 +` SOF_TKN_BUF_CAPS' STR($3) ` }' `}' `SectionData."'N_BUFFER($1)`_data" {' -- 2.14.1

1 0

[Sound-open-firmware] [PATCH v2 1/5] topology: create m4 wrapper for mixer control section
by Ranjani Sridharan 05 Mar '18

05 Mar '18

This patch adds m4 wrapper for mixercontrol section in pipeline definition Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- topology/m4/local.m4 | 55 +++++++++++++++++++++-- topology/sof/pipe-low-latency-capture.m4 | 36 ++++----------- topology/sof/pipe-low-latency-playback.m4 | 73 +++++++------------------------ topology/sof/pipe-pcm-media.m4 | 37 ++++------------ topology/sof/pipe-tone.m4 | 73 +++++++------------------------ topology/sof/pipe-volume-capture.m4 | 35 ++++----------- topology/sof/pipe-volume-playback.m4 | 70 +++++++---------------------- 7 files changed, 127 insertions(+), 252 deletions(-) diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 index a340ec3..4521314 100644 --- a/topology/m4/local.m4 +++ b/topology/m4/local.m4 @@ -7,9 +7,13 @@ define(`STR', `"'$1`"') define(`argn', `ifelse(`$1', 1, ``$2'', `argn(decr(`$1'), shift(shift($@)))')') -define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') KCONTROL_LOOP($@)') -define(`KCONTROL_LOOP', `argn(j,$@) - ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) $0($@)')') +define(`KCONTROLS', `pushdef(`i', $#)pushdef(`j', `1')KCONTROL_LOOP($@)popdef(i)popdef(j)') +define(`KCONTROL_LOOP',`argn(j,$@) + ifelse(i,`1', `',`define(`i', decr(i))define(`j', incr(j))$0($@)')') + +define(`MIXERCONTROLS', `pushdef(`i', $#)pushdef(`j', `1')MIXERCONTROL_LOOP($@)popdef(i)popdef(j)') +define(`MIXERCONTROL_LOOP',`argn(j,$@) + ifelse(i,`1', `',`define(`i', decr(i))define(`j', incr(j))$0($@)')') dnl create direct DAPM/pipeline link between 2 widgets) define(`dapm', `"$1, , $2"') @@ -549,4 +553,49 @@ define(`PCM_DUPLEX_ADD', ` }' `}') +dnl KCONTROL_CHANNEL(name, reg, shift) +define(`KCONTROL_CHANNEL', +`channel.STR($1) {' +` reg STR($2)' +` shift STR($3)' +` }') + +dnl CONTROLMIXER_MAX(comment, value) +define(`CONTROLMIXER_MAX', +`#$1' +` max STR($2)') + +dnl CONTROLMIXER_TLV(comment, value) +define(`CONTROLMIXER_TLV', +`#$1' +` tlv STR($2)') + +dnl CONTROLMIXER_OPS(info, comment, get, put) +define(`CONTROLMIXER_OPS', +`ops."ctl" {' +` info STR($1)' +` #$2' +` get STR($3)' +` put STR($4)' +` }') + +dnl C_CONTROLMIXER(name, index, ops, max, invert, tlv, KCONTROL_CHANNELS) +define(`C_CONTROLMIXER', +`SectionControlMixer.STR($1) {' +`' +` # control belongs to this index group' +` index STR($2)' +`' +` #$7' +` $8' +` # control uses bespoke driver get/put/info ID' +` $3' +`' +` $4' +` invert STR($5)' +` $6' +`}') + divert(0) dnl + + diff --git a/topology/sof/pipe-low-latency-capture.m4 b/topology/sof/pipe-low-latency-capture.m4 index 2602ebd..a82dee1 100644 --- a/topology/sof/pipe-low-latency-capture.m4 +++ b/topology/sof/pipe-low-latency-capture.m4 @@ -10,34 +10,14 @@ include(`local.m4') # # Controls # - -SectionControlMixer.STR(PCM PCM_ID Capture Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "0" - shift "0" - } - channel."FR" { - reg "0" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 40 steps from -90dB to +20dB for 3dB - max "40" - invert "false" - tlv "vtlv_m90s3" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(PCM PCM_ID Capture Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 40), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 0, 0), KCONTROL_CHANNEL(FR, 0, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-low-latency-playback.m4 b/topology/sof/pipe-low-latency-playback.m4 index ebb14ec..3b8d6aa 100644 --- a/topology/sof/pipe-low-latency-playback.m4 +++ b/topology/sof/pipe-low-latency-playback.m4 @@ -25,62 +25,23 @@ include(`local.m4') # # Controls # - -SectionControlMixer.STR(PCM PCM_ID Playback Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "0" - shift "0" - } - channel."FR" { - reg "0" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - -SectionControlMixer.STR(Master Playback Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(PCM PCM_ID Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 0, 0), KCONTROL_CHANNEL(FR, 0, 1))) + +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-pcm-media.m4 b/topology/sof/pipe-pcm-media.m4 index 526ae35..65dc62d 100644 --- a/topology/sof/pipe-pcm-media.m4 +++ b/topology/sof/pipe-pcm-media.m4 @@ -13,35 +13,14 @@ include(`local.m4') # # Controls # - -SectionControlMixer.STR(PCM PCM_ID Playback Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(PCM PCM_ID Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) # # SRC Configuration diff --git a/topology/sof/pipe-tone.m4 b/topology/sof/pipe-tone.m4 index 8f92680..b735146 100644 --- a/topology/sof/pipe-tone.m4 +++ b/topology/sof/pipe-tone.m4 @@ -14,62 +14,23 @@ include(`local.m4') # Controls # -SectionControlMixer.STR(Tone Volume PIPELINE_ID) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - # 256 binds the mixer control to volume get/put handlers - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - -SectionControlMixer.STR(Tone Switch PIPELINE_ID) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "2" - shift "0" - } - channel."FR" { - reg "2" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - # 256 binds the mixer control to volume get/put handlers - get "256" - put "256" - } - - # max 1 indicates switch type mixer control - max "1" - invert "false" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Tone Volume PIPELINE_ID, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) + +# Switch type Mixer Control with max value of 1 +C_CONTROLMIXER(Tone Switch PIPELINE_ID, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(max 1 indicates switch type control, 1), + false, + , + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 2, 0), KCONTROL_CHANNEL(FR, 2, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 58e5393..1cde24e 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -10,33 +10,14 @@ include(`local.m4') # # Controls # -SectionControlMixer.STR(Master Capture Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index 8aa02fb..a6b5a1d 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -10,60 +10,24 @@ include(`local.m4') # # Controls # -SectionControlMixer.STR(Master Playback Volume) { +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) + +# Volume Mixer Switch control with max value of 1 +C_CONTROLMIXER(Master Playback Volume Switch, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(max value 1 indicates switch type control, 1), + false, + , + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - -SectionControlMixer.STR(Master Playback Volume Switch) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # Volume mute on/off - max "1" - invert "false" -} # # Components and Buffers # -- 2.14.1

2 7

[Sound-open-firmware] [PATCH] cnl: dma: refine dma interrupt processing on cnl
by Rander Wang 05 Mar '18

05 Mar '18

From: Rander Wang <rander.wang(a)intel.com> On cnl, all the dma share the same interrupt pin, so all the dma controller need to be checked in interrupt function. And also refine dma probe Signed-off-by: Rander Wang <rander.wang(a)linux.intel.com> --- src/drivers/dw-dma.c | 61 +++++++++++++++++++++----------------- src/platform/cannonlake/platform.c | 5 ++++ 2 files changed, 39 insertions(+), 27 deletions(-) diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index 15d608c..a06087e 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -1029,7 +1029,6 @@ static int dw_dma_probe(struct dma *dma) } #else - /* this will probably be called at the end of every period copied */ static void dw_dma_irq_handler(void *data) { @@ -1047,14 +1046,7 @@ static void dw_dma_irq_handler(void *data) status_intr = dw_read(dma, DW_INTR_STATUS); if (!status_intr) { -#ifdef CONFIG_CANNONLAKE - dma++; - status_intr = dw_read(dma, DW_INTR_STATUS); - if (!status_intr) - trace_dma_error("eI0"); -#else trace_dma_error("eI0"); -#endif } tracev_dma("DIr"); @@ -1144,37 +1136,52 @@ static void dw_dma_irq_handler(void *data) } } +/*All the dma share the same interrupt on CNL, so check each dma*/ +/*controller when interrupt coming, then do the work */ +static void dw_dma_irq_cnl(void *data) +{ + struct dma *dma; + uint32_t status_intr; + + /*check interrupt status of DMA controller 0*/ + dma = dma_get(DMA_GP_LP_DMAC0); + status_intr = dw_read(dma, DW_INTR_STATUS); + if (status_intr) + dw_dma_irq_handler(dma); + + /*check interrupt status of DMA controller 1*/ + dma = dma_get(DMA_GP_LP_DMAC1); + status_intr = dw_read(dma, DW_INTR_STATUS); + if (status_intr) + dw_dma_irq_handler(dma); +} + static int dw_dma_probe(struct dma *dma) { struct dma_pdata *dw_pdata; - struct dma *dmac = dma; int i; -#ifdef CONFIG_CANNONLAKE - int j; - - for (j = 0; j < MAX_GPDMA_COUNT; j++) -#endif - { - /* allocate private data */ - dw_pdata = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(*dw_pdata)); - dma_set_drvdata(dmac, dw_pdata); - spinlock_init(&dmac->lock); + /* allocate private data */ + dw_pdata = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(*dw_pdata)); + dma_set_drvdata(dma, dw_pdata); - dw_dma_setup(dmac); + spinlock_init(&dma->lock); - /* init work */ - for (i = 0; i < DW_MAX_CHAN; i++) { - dw_pdata->chan[i].dma = dmac; - dw_pdata->chan[i].channel = i; - dw_pdata->chan[i].status = COMP_STATE_INIT; - } + dw_dma_setup(dma); - dmac++; + /* init work */ + for (i = 0; i < DW_MAX_CHAN; i++) { + dw_pdata->chan[i].dma = dma; + dw_pdata->chan[i].channel = i; + dw_pdata->chan[i].status = COMP_STATE_INIT; } /* register our IRQ handler */ +#ifdef CONFIG_CANNONLAKE + interrupt_register(dma_irq(dma), dw_dma_irq_cnl, dma); +#else interrupt_register(dma_irq(dma), dw_dma_irq_handler, dma); +#endif interrupt_enable(dma_irq(dma)); return 0; diff --git a/src/platform/cannonlake/platform.c b/src/platform/cannonlake/platform.c index beb6582..1a9b88a 100644 --- a/src/platform/cannonlake/platform.c +++ b/src/platform/cannonlake/platform.c @@ -253,6 +253,11 @@ int platform_init(struct reef *reef) return -ENODEV; dma_probe(dmac); + dmac = dma_get(DMA_GP_LP_DMAC1); + if (!dmac) + return -ENODEV; + dma_probe(dmac); + dmac = dma_get(DMA_HOST_OUT_DMAC); if (!dmac) return -ENODEV; -- 2.14.1

2 1

[Sound-open-firmware] [PATCH] topology: Add support for memory capabilities
by Liam Girdwood 05 Mar '18

05 Mar '18

Add support in topology to define different memory capabilities that can be included by standard pipeline definitions to set platform specific capabilities for buffers. This patch allows memory capabilities to be defined for each platform and included by all pipeline definitions. Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- topology/Makefile.am | 2 +- topology/common/Makefile.am | 3 ++- topology/common/memory.m4 | 15 +++++++++++++++ topology/dsps/bdw.m4 | 8 ++++++++ topology/dsps/bxt.m4 | 11 +++++++++++ topology/dsps/byt.m4 | 8 ++++++++ topology/dsps/cht.m4 | 8 ++++++++ topology/dsps/hsw.m4 | 8 ++++++++ topology/m4/local.m4 | 19 ++++++++++++++++--- topology/sof/pipe-low-latency-capture.m4 | 6 ++++-- topology/sof/pipe-low-latency-playback.m4 | 12 ++++++++---- topology/sof/pipe-passthrough-capture.m4 | 3 ++- topology/sof/pipe-passthrough-playback.m4 | 3 ++- topology/sof/pipe-pcm-media.m4 | 9 ++++++--- topology/sof/pipe-src-capture.m4 | 8 +++++--- topology/sof/pipe-src-playback.m4 | 6 ++++-- topology/sof/pipe-tone.m4 | 6 ++++-- topology/sof/pipe-volume-capture.m4 | 6 ++++-- topology/sof/pipe-volume-playback.m4 | 6 ++++-- topology/sof/tokens.m4 | 1 + topology/test/tplg-build.sh | 2 +- 21 files changed, 122 insertions(+), 28 deletions(-) create mode 100644 topology/common/memory.m4 diff --git a/topology/Makefile.am b/topology/Makefile.am index 1e80d57..a62aa78 100644 --- a/topology/Makefile.am +++ b/topology/Makefile.am @@ -34,7 +34,7 @@ MACHINES = \ .PRECIOUS: %.conf %.conf : %.m4 ${DEPS} - m4 -I m4 $< > $@ + m4 -I m4 -I common $< > $@ %.tplg : %.conf alsatplg -v 1 -c $< -o $@ diff --git a/topology/common/Makefile.am b/topology/common/Makefile.am index 980f0ce..7e207a7 100644 --- a/topology/common/Makefile.am +++ b/topology/common/Makefile.am @@ -1,3 +1,4 @@ EXTRA_DIST = \ - tlv.m4 + tlv.m4 \ + memory.m4 diff --git a/topology/common/memory.m4 b/topology/common/memory.m4 new file mode 100644 index 0000000..0852dff --- /dev/null +++ b/topology/common/memory.m4 @@ -0,0 +1,15 @@ +dnl +dnl Memory capabilities. +dnl +dnl These are ORed together to create a capability mask that's sent to the +dnl SOF firmware when creating buffer or allocating other memory resources. +dnl +dnl ** Must match SOF_MEM_CAPS_ values in ipc.h ** + +define(`MEM_CAP_RAM', eval(1 << 0)) +define(`MEM_CAP_ROM', eval(1 << 1)) +define(`MEM_CAP_EXT', eval(1 << 2)) +define(`MEM_CAP_LP', eval(1 << 3)) +define(`MEM_CAP_HP', eval(1 << 4)) +define(`MEM_CAP_DMA', eval(1 << 5)) +define(`MEM_CAP_CACHE', eval(1 << 6)) diff --git a/topology/dsps/bdw.m4 b/topology/dsps/bdw.m4 index 428e8bb..ad06362 100644 --- a/topology/dsps/bdw.m4 +++ b/topology/dsps/bdw.m4 @@ -2,6 +2,14 @@ # Broadwell differentiation for pipelines and components # +include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Broadwell +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/bxt.m4 b/topology/dsps/bxt.m4 index 688e9fa..61bcb7e 100644 --- a/topology/dsps/bxt.m4 +++ b/topology/dsps/bxt.m4 @@ -2,6 +2,17 @@ # Broxton differentiation for pipelines and components # +include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Baytrail +define(`PLATFORM_DAI_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_HOST_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_PASS_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/byt.m4 b/topology/dsps/byt.m4 index b4defaa..64cee72 100644 --- a/topology/dsps/byt.m4 +++ b/topology/dsps/byt.m4 @@ -2,6 +2,14 @@ # Baytrail differentiation for pipelines and components # +include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Baytrail +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/cht.m4 b/topology/dsps/cht.m4 index fdee83d..1f461d9 100644 --- a/topology/dsps/cht.m4 +++ b/topology/dsps/cht.m4 @@ -2,6 +2,14 @@ # Cherrytrail differentiation for pipelines and components # +include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Cherrytrail +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/hsw.m4 b/topology/dsps/hsw.m4 index edb417f..074542a 100644 --- a/topology/dsps/hsw.m4 +++ b/topology/dsps/hsw.m4 @@ -2,6 +2,14 @@ # Haswell differentiation for pipelines and components # +include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Haswell +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 index 29b8b29..14d742d 100644 --- a/topology/m4/local.m4 +++ b/topology/m4/local.m4 @@ -4,13 +4,25 @@ define(`concat',`$1$2') define(`STR', `"'$1`"') +dnl Argument iterator. define(`argn', `ifelse(`$1', 1, ``$2'', `argn(decr(`$1'), shift(shift($@)))')') -define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') KCONTROL_LOOP($@)') -define(`KCONTROL_LOOP', `argn(j,$@) +dnl Defines a list of items from a variable number of params. +dnl Use as last argument in a macro. +define(`LIST_LOOP', `argn(j,$@) ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) $0($@)')') +dnl Sums a list of variable arguments. Use as last argument in macro. +define(`SUM_LOOP', `eval(argn(j,$@) + ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) + $0($@)'))') + +dnl Support a varaible list of kcontrols. +define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') LIST_LOOP($@)') + +dnl Memory capabilities +define(`MEMCAPS', `pushdef(`i', $#) pushdef(`j', `1') SUM_LOOP($@)') + dnl create direct DAPM/pipeline link between 2 widgets) define(`dapm', `"$1, , $2"') @@ -53,12 +65,13 @@ define(`W_SRC', dnl Buffer name) define(`N_BUFFER', `BUF'PIPELINE_ID`.'$1) -dnl W_BUFFER(name, size) +dnl W_BUFFER(name, size, capabilities) define(`W_BUFFER', `SectionVendorTuples."'N_BUFFER($1)`_tuples" {' ` tokens "sof_buffer_tokens"' ` tuples."word" {' ` SOF_TKN_BUF_SIZE' STR($2) +` SOF_TKN_BUF_CAPS' $3 ` }' `}' `SectionData."'N_BUFFER($1)`_data" {' diff --git a/topology/sof/pipe-low-latency-capture.m4 b/topology/sof/pipe-low-latency-capture.m4 index 2602ebd..41fc622 100644 --- a/topology/sof/pipe-low-latency-capture.m4 +++ b/topology/sof/pipe-low-latency-capture.m4 @@ -52,9 +52,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("PCM PCM_ID Capture Volume")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) # # Pipeline Graph diff --git a/topology/sof/pipe-low-latency-playback.m4 b/topology/sof/pipe-low-latency-playback.m4 index ebb14ec..37f8be2 100644 --- a/topology/sof/pipe-low-latency-playback.m4 +++ b/topology/sof/pipe-low-latency-playback.m4 @@ -101,13 +101,17 @@ W_MIXER(0, PIPELINE_FORMAT, 1, 1, 1) # Low Latency Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(1, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) W_BUFFER(2, COMP_BUFFER_SIZE(1, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) W_BUFFER(3, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP) # # Pipeline Graph diff --git a/topology/sof/pipe-passthrough-capture.m4 b/topology/sof/pipe-passthrough-capture.m4 index 2c2a495..b0dfe48 100644 --- a/topology/sof/pipe-passthrough-capture.m4 +++ b/topology/sof/pipe-passthrough-capture.m4 @@ -18,7 +18,8 @@ W_PCM_CAPTURE(Passthrough Capture, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 0, 2, 2) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_PASS_MEM_CAP) # # DAI definitions diff --git a/topology/sof/pipe-passthrough-playback.m4 b/topology/sof/pipe-passthrough-playback.m4 index 1722256..b86f1b3 100644 --- a/topology/sof/pipe-passthrough-playback.m4 +++ b/topology/sof/pipe-passthrough-playback.m4 @@ -18,7 +18,8 @@ W_PCM_PLAYBACK(Passthrough Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2) # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_PASS_MEM_CAP) # # DAI definitions diff --git a/topology/sof/pipe-pcm-media.m4 b/topology/sof/pipe-pcm-media.m4 index 526ae35..1766aca 100644 --- a/topology/sof/pipe-pcm-media.m4 +++ b/topology/sof/pipe-pcm-media.m4 @@ -75,13 +75,16 @@ W_SRC(0, PIPELINE_FORMAT, 2, 2, media_src_conf, 2) # Media Source Buffers to SRC, make them big enough to deal with 2 * rate. W_BUFFER(0, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1,COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) # Buffer B2 is on fixed rate sink side of SRC. Set it 1.5 * rate. W_BUFFER(2, COMP_BUFFER_SIZE(3, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) # # Pipeline Graph diff --git a/topology/sof/pipe-src-capture.m4 b/topology/sof/pipe-src-capture.m4 index dc55dd2..96d7ee7 100644 --- a/topology/sof/pipe-src-capture.m4 +++ b/topology/sof/pipe-src-capture.m4 @@ -37,9 +37,11 @@ W_SRC(0, PIPELINE_FORMAT, 4, 4, media_src_conf, 2) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP) # # DAI definitions @@ -56,7 +58,7 @@ W_PIPELINE(N_DAI_IN, SCHEDULE_DEADLINE, SCHEDULE_PRIORITY, SCHEDULE_FRAMES, # # Pipeline Graph # -# host PCM_P --> B0 --> SRC 0 --> B1 --> sink DAI0 +# host PCM_P <-- B0 <-- SRC 0 <-- B1 <-- sink DAI0 SectionGraph."pipe-pass-src-capture-PIPELINE_ID" { index STR(PIPELINE_ID) diff --git a/topology/sof/pipe-src-playback.m4 b/topology/sof/pipe-src-playback.m4 index d037543..a6141c9 100644 --- a/topology/sof/pipe-src-playback.m4 +++ b/topology/sof/pipe-src-playback.m4 @@ -37,9 +37,11 @@ W_SRC(0, PIPELINE_FORMAT, 4, 4, media_src_conf, 2) # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP) # # DAI definitions diff --git a/topology/sof/pipe-tone.m4 b/topology/sof/pipe-tone.m4 index e04a1b9..a8064ab 100644 --- a/topology/sof/pipe-tone.m4 +++ b/topology/sof/pipe-tone.m4 @@ -54,9 +54,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("Tone Volume PIPELINE_ID")) # Low Latency Buffers W_BUFFER(0,COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) # diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 58e5393..2fd6b98 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -51,9 +51,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Capture Volume")) # Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP) # # DAI definitions diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index 8aa02fb..9431177 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -77,9 +77,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Playback Volume Switch", "M # Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP) # # DAI definitions diff --git a/topology/sof/tokens.m4 b/topology/sof/tokens.m4 index 704effc..6b966b3 100644 --- a/topology/sof/tokens.m4 +++ b/topology/sof/tokens.m4 @@ -11,6 +11,7 @@ SectionVendorTokens."sof_buffer_tokens" { SOF_TKN_BUF_SIZE "100" + SOF_TKN_BUF_CAPS "101" } SectionVendorTokens."sof_dai_tokens" { diff --git a/topology/test/tplg-build.sh b/topology/test/tplg-build.sh index 047ef6b..9022d1c 100755 --- a/topology/test/tplg-build.sh +++ b/topology/test/tplg-build.sh @@ -8,7 +8,7 @@ set -e # M4 preprocessor flags -M4_FLAGS="-I ../ -I ../m4" +M4_FLAGS="-I ../ -I ../m4 -I ../common" # Simple component test cases # can be used on components with 1 sink and 1 source. -- 2.14.1

1 1

[Sound-open-firmware] [PATCH 1/5] topology: create m4 wrapper for mixer control section
by Ranjani Sridharan 05 Mar '18

05 Mar '18

This patch adds m4 wrapper for mixercontrol section in pipeline definition Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- topology/m4/local.m4 | 55 +++++++++++++++++++++-- topology/sof/pipe-low-latency-capture.m4 | 36 ++++----------- topology/sof/pipe-low-latency-playback.m4 | 73 +++++++------------------------ topology/sof/pipe-pcm-media.m4 | 37 ++++------------ topology/sof/pipe-tone.m4 | 73 +++++++------------------------ topology/sof/pipe-volume-capture.m4 | 35 ++++----------- topology/sof/pipe-volume-playback.m4 | 70 +++++++---------------------- 7 files changed, 127 insertions(+), 252 deletions(-) diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 index a340ec3..4521314 100644 --- a/topology/m4/local.m4 +++ b/topology/m4/local.m4 @@ -7,9 +7,13 @@ define(`STR', `"'$1`"') define(`argn', `ifelse(`$1', 1, ``$2'', `argn(decr(`$1'), shift(shift($@)))')') -define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') KCONTROL_LOOP($@)') -define(`KCONTROL_LOOP', `argn(j,$@) - ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) $0($@)')') +define(`KCONTROLS', `pushdef(`i', $#)pushdef(`j', `1')KCONTROL_LOOP($@)popdef(i)popdef(j)') +define(`KCONTROL_LOOP',`argn(j,$@) + ifelse(i,`1', `',`define(`i', decr(i))define(`j', incr(j))$0($@)')') + +define(`MIXERCONTROLS', `pushdef(`i', $#)pushdef(`j', `1')MIXERCONTROL_LOOP($@)popdef(i)popdef(j)') +define(`MIXERCONTROL_LOOP',`argn(j,$@) + ifelse(i,`1', `',`define(`i', decr(i))define(`j', incr(j))$0($@)')') dnl create direct DAPM/pipeline link between 2 widgets) define(`dapm', `"$1, , $2"') @@ -549,4 +553,49 @@ define(`PCM_DUPLEX_ADD', ` }' `}') +dnl KCONTROL_CHANNEL(name, reg, shift) +define(`KCONTROL_CHANNEL', +`channel.STR($1) {' +` reg STR($2)' +` shift STR($3)' +` }') + +dnl CONTROLMIXER_MAX(comment, value) +define(`CONTROLMIXER_MAX', +`#$1' +` max STR($2)') + +dnl CONTROLMIXER_TLV(comment, value) +define(`CONTROLMIXER_TLV', +`#$1' +` tlv STR($2)') + +dnl CONTROLMIXER_OPS(info, comment, get, put) +define(`CONTROLMIXER_OPS', +`ops."ctl" {' +` info STR($1)' +` #$2' +` get STR($3)' +` put STR($4)' +` }') + +dnl C_CONTROLMIXER(name, index, ops, max, invert, tlv, KCONTROL_CHANNELS) +define(`C_CONTROLMIXER', +`SectionControlMixer.STR($1) {' +`' +` # control belongs to this index group' +` index STR($2)' +`' +` #$7' +` $8' +` # control uses bespoke driver get/put/info ID' +` $3' +`' +` $4' +` invert STR($5)' +` $6' +`}') + divert(0) dnl + + diff --git a/topology/sof/pipe-low-latency-capture.m4 b/topology/sof/pipe-low-latency-capture.m4 index 2602ebd..a82dee1 100644 --- a/topology/sof/pipe-low-latency-capture.m4 +++ b/topology/sof/pipe-low-latency-capture.m4 @@ -10,34 +10,14 @@ include(`local.m4') # # Controls # - -SectionControlMixer.STR(PCM PCM_ID Capture Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "0" - shift "0" - } - channel."FR" { - reg "0" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 40 steps from -90dB to +20dB for 3dB - max "40" - invert "false" - tlv "vtlv_m90s3" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(PCM PCM_ID Capture Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 40), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 0, 0), KCONTROL_CHANNEL(FR, 0, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-low-latency-playback.m4 b/topology/sof/pipe-low-latency-playback.m4 index ebb14ec..3b8d6aa 100644 --- a/topology/sof/pipe-low-latency-playback.m4 +++ b/topology/sof/pipe-low-latency-playback.m4 @@ -25,62 +25,23 @@ include(`local.m4') # # Controls # - -SectionControlMixer.STR(PCM PCM_ID Playback Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "0" - shift "0" - } - channel."FR" { - reg "0" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - -SectionControlMixer.STR(Master Playback Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(PCM PCM_ID Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 0, 0), KCONTROL_CHANNEL(FR, 0, 1))) + +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-pcm-media.m4 b/topology/sof/pipe-pcm-media.m4 index 526ae35..65dc62d 100644 --- a/topology/sof/pipe-pcm-media.m4 +++ b/topology/sof/pipe-pcm-media.m4 @@ -13,35 +13,14 @@ include(`local.m4') # # Controls # - -SectionControlMixer.STR(PCM PCM_ID Playback Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(PCM PCM_ID Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) # # SRC Configuration diff --git a/topology/sof/pipe-tone.m4 b/topology/sof/pipe-tone.m4 index 8f92680..b735146 100644 --- a/topology/sof/pipe-tone.m4 +++ b/topology/sof/pipe-tone.m4 @@ -14,62 +14,23 @@ include(`local.m4') # Controls # -SectionControlMixer.STR(Tone Volume PIPELINE_ID) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - # 256 binds the mixer control to volume get/put handlers - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - -SectionControlMixer.STR(Tone Switch PIPELINE_ID) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "2" - shift "0" - } - channel."FR" { - reg "2" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - # 256 binds the mixer control to volume get/put handlers - get "256" - put "256" - } - - # max 1 indicates switch type mixer control - max "1" - invert "false" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Tone Volume PIPELINE_ID, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) + +# Switch type Mixer Control with max value of 1 +C_CONTROLMIXER(Tone Switch PIPELINE_ID, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(max 1 indicates switch type control, 1), + false, + , + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 2, 0), KCONTROL_CHANNEL(FR, 2, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 58e5393..1cde24e 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -10,33 +10,14 @@ include(`local.m4') # # Controls # -SectionControlMixer.STR(Master Capture Volume) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) # # Components and Buffers diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index 8aa02fb..a6b5a1d 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -10,60 +10,24 @@ include(`local.m4') # # Controls # -SectionControlMixer.STR(Master Playback Volume) { +# Volume Mixer control with max value of 32 +C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(, 32), + false, + CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3), + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) + +# Volume Mixer Switch control with max value of 1 +C_CONTROLMIXER(Master Playback Volume Switch, PIPELINE_ID, + CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256), + CONTROLMIXER_MAX(max value 1 indicates switch type control, 1), + false, + , + Channel register and shift for Front Left/Right, + MIXERCONTROLS(KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1))) - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # TLV 32 steps from -90dB to +6dB for 3dB - max "32" - invert "false" - tlv "vtlv_m90s3" -} - -SectionControlMixer.STR(Master Playback Volume Switch) { - - # control belongs to this index group - index STR(PIPELINE_ID) - - # Channel register and shift for Front Left/Right - channel."FL" { - reg "1" - shift "0" - } - channel."FR" { - reg "1" - shift "1" - } - - # control uses bespoke driver get/put/info ID 0 - ops."ctl" { - info "volsw" - get "256" - put "256" - } - - # Volume mute on/off - max "1" - invert "false" -} # # Components and Buffers # -- 2.14.1

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