Add support in topology to define different memory capabilities that can be included by standard pipeline definitions to set platform specific capabilities for buffers.

This patch allows memory capabilities to be defined for each platform and included by all pipeline definitions.

Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com --- topology/Makefile.am | 2 +- topology/common/Makefile.am | 3 ++- topology/common/memory.m4 | 15 +++++++++++++++ topology/dsps/bdw.m4 | 8 ++++++++ topology/dsps/bxt.m4 | 11 +++++++++++ topology/dsps/byt.m4 | 8 ++++++++ topology/dsps/cht.m4 | 8 ++++++++ topology/dsps/hsw.m4 | 8 ++++++++ topology/m4/local.m4 | 19 ++++++++++++++++--- topology/sof/pipe-low-latency-capture.m4 | 6 ++++-- topology/sof/pipe-low-latency-playback.m4 | 12 ++++++++---- topology/sof/pipe-passthrough-capture.m4 | 3 ++- topology/sof/pipe-passthrough-playback.m4 | 3 ++- topology/sof/pipe-pcm-media.m4 | 9 ++++++--- topology/sof/pipe-src-capture.m4 | 8 +++++--- topology/sof/pipe-src-playback.m4 | 6 ++++-- topology/sof/pipe-tone.m4 | 6 ++++-- topology/sof/pipe-volume-capture.m4 | 6 ++++-- topology/sof/pipe-volume-playback.m4 | 6 ++++-- topology/sof/tokens.m4 | 1 + topology/test/tplg-build.sh | 2 +- 21 files changed, 122 insertions(+), 28 deletions(-) create mode 100644 topology/common/memory.m4

diff --git a/topology/Makefile.am b/topology/Makefile.am index 1e80d57..a62aa78 100644 --- a/topology/Makefile.am +++ b/topology/Makefile.am @@ -34,7 +34,7 @@ MACHINES = \ .PRECIOUS: %.conf

%.conf : %.m4 ${DEPS} - m4 -I m4 $< > $@ + m4 -I m4 -I common $< > $@

%.tplg : %.conf alsatplg -v 1 -c $< -o $@ diff --git a/topology/common/Makefile.am b/topology/common/Makefile.am index 980f0ce..7e207a7 100644 --- a/topology/common/Makefile.am +++ b/topology/common/Makefile.am @@ -1,3 +1,4 @@ EXTRA_DIST = \ - tlv.m4 + tlv.m4 \ + memory.m4

diff --git a/topology/common/memory.m4 b/topology/common/memory.m4 new file mode 100644 index 0000000..0852dff --- /dev/null +++ b/topology/common/memory.m4 @@ -0,0 +1,15 @@ +dnl +dnl Memory capabilities. +dnl +dnl These are ORed together to create a capability mask that's sent to the +dnl SOF firmware when creating buffer or allocating other memory resources. +dnl +dnl ** Must match SOF_MEM_CAPS_ values in ipc.h ** + +define(`MEM_CAP_RAM', eval(1 << 0)) +define(`MEM_CAP_ROM', eval(1 << 1)) +define(`MEM_CAP_EXT', eval(1 << 2)) +define(`MEM_CAP_LP', eval(1 << 3)) +define(`MEM_CAP_HP', eval(1 << 4)) +define(`MEM_CAP_DMA', eval(1 << 5)) +define(`MEM_CAP_CACHE', eval(1 << 6)) diff --git a/topology/dsps/bdw.m4 b/topology/dsps/bdw.m4 index 428e8bb..ad06362 100644 --- a/topology/dsps/bdw.m4 +++ b/topology/dsps/bdw.m4 @@ -2,6 +2,14 @@ # Broadwell differentiation for pipelines and components #

+include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Broadwell +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/bxt.m4 b/topology/dsps/bxt.m4 index 688e9fa..61bcb7e 100644 --- a/topology/dsps/bxt.m4 +++ b/topology/dsps/bxt.m4 @@ -2,6 +2,17 @@ # Broxton differentiation for pipelines and components #

+include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Baytrail +define(`PLATFORM_DAI_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_HOST_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_PASS_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/byt.m4 b/topology/dsps/byt.m4 index b4defaa..64cee72 100644 --- a/topology/dsps/byt.m4 +++ b/topology/dsps/byt.m4 @@ -2,6 +2,14 @@ # Baytrail differentiation for pipelines and components #

+include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Baytrail +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/cht.m4 b/topology/dsps/cht.m4 index fdee83d..1f461d9 100644 --- a/topology/dsps/cht.m4 +++ b/topology/dsps/cht.m4 @@ -2,6 +2,14 @@ # Cherrytrail differentiation for pipelines and components #

+include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Cherrytrail +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/dsps/hsw.m4 b/topology/dsps/hsw.m4 index edb417f..074542a 100644 --- a/topology/dsps/hsw.m4 +++ b/topology/dsps/hsw.m4 @@ -2,6 +2,14 @@ # Haswell differentiation for pipelines and components #

+include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Haswell +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + # Low Latency PCM Configuration SectionVendorTuples."pipe_ll_schedule_plat_tokens" { tokens "sof_sched_tokens" diff --git a/topology/m4/local.m4 b/topology/m4/local.m4 index 29b8b29..14d742d 100644 --- a/topology/m4/local.m4 +++ b/topology/m4/local.m4 @@ -4,13 +4,25 @@ define(`concat',`$1$2')

define(`STR', `"'$1`"')

+dnl Argument iterator. define(`argn', `ifelse(`$1', 1, ``$2'', `argn(decr(`$1'), shift(shift($@)))')')

-define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') KCONTROL_LOOP($@)') -define(`KCONTROL_LOOP', `argn(j,$@) +dnl Defines a list of items from a variable number of params. +dnl Use as last argument in a macro. +define(`LIST_LOOP', `argn(j,$@) ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) $0($@)')')

+dnl Sums a list of variable arguments. Use as last argument in macro. +define(`SUM_LOOP', `eval(argn(j,$@) + ifelse(i,`1', `', `define(`i', decr(i)) define(`j', incr(j)) + $0($@)'))') + +dnl Support a varaible list of kcontrols. +define(`KCONTROLS', `pushdef(`i', $#) pushdef(`j', `1') LIST_LOOP($@)') + +dnl Memory capabilities +define(`MEMCAPS', `pushdef(`i', $#) pushdef(`j', `1') SUM_LOOP($@)') + dnl create direct DAPM/pipeline link between 2 widgets) define(`dapm', `"$1, , $2"')

@@ -53,12 +65,13 @@ define(`W_SRC', dnl Buffer name) define(`N_BUFFER', `BUF'PIPELINE_ID`.'$1)

-dnl W_BUFFER(name, size) +dnl W_BUFFER(name, size, capabilities) define(`W_BUFFER', `SectionVendorTuples."'N_BUFFER($1)`_tuples" {' ` tokens "sof_buffer_tokens"' ` tuples."word" {' ` SOF_TKN_BUF_SIZE' STR($2) +` SOF_TKN_BUF_CAPS' $3 ` }' `}' `SectionData."'N_BUFFER($1)`_data" {' diff --git a/topology/sof/pipe-low-latency-capture.m4 b/topology/sof/pipe-low-latency-capture.m4 index 2602ebd..41fc622 100644 --- a/topology/sof/pipe-low-latency-capture.m4 +++ b/topology/sof/pipe-low-latency-capture.m4 @@ -52,9 +52,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("PCM PCM_ID Capture Volume"))

# Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP)

# # Pipeline Graph diff --git a/topology/sof/pipe-low-latency-playback.m4 b/topology/sof/pipe-low-latency-playback.m4 index ebb14ec..37f8be2 100644 --- a/topology/sof/pipe-low-latency-playback.m4 +++ b/topology/sof/pipe-low-latency-playback.m4 @@ -101,13 +101,17 @@ W_MIXER(0, PIPELINE_FORMAT, 1, 1, 1)

# Low Latency Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(1, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) W_BUFFER(2, COMP_BUFFER_SIZE(1, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) W_BUFFER(3, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP)

# # Pipeline Graph diff --git a/topology/sof/pipe-passthrough-capture.m4 b/topology/sof/pipe-passthrough-capture.m4 index 2c2a495..b0dfe48 100644 --- a/topology/sof/pipe-passthrough-capture.m4 +++ b/topology/sof/pipe-passthrough-capture.m4 @@ -18,7 +18,8 @@ W_PCM_CAPTURE(Passthrough Capture, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 0, 2, 2)

# Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_PASS_MEM_CAP)

# # DAI definitions diff --git a/topology/sof/pipe-passthrough-playback.m4 b/topology/sof/pipe-passthrough-playback.m4 index 1722256..b86f1b3 100644 --- a/topology/sof/pipe-passthrough-playback.m4 +++ b/topology/sof/pipe-passthrough-playback.m4 @@ -18,7 +18,8 @@ W_PCM_PLAYBACK(Passthrough Playback, PIPELINE_DMAC, PIPELINE_DMAC_CHAN, 2, 0, 2)

# Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_PASS_MEM_CAP)

# # DAI definitions diff --git a/topology/sof/pipe-pcm-media.m4 b/topology/sof/pipe-pcm-media.m4 index 526ae35..1766aca 100644 --- a/topology/sof/pipe-pcm-media.m4 +++ b/topology/sof/pipe-pcm-media.m4 @@ -75,13 +75,16 @@ W_SRC(0, PIPELINE_FORMAT, 2, 2, media_src_conf, 2)

# Media Source Buffers to SRC, make them big enough to deal with 2 * rate. W_BUFFER(0, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1,COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP)

# Buffer B2 is on fixed rate sink side of SRC. Set it 1.5 * rate. W_BUFFER(2, COMP_BUFFER_SIZE(3, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP)

# # Pipeline Graph diff --git a/topology/sof/pipe-src-capture.m4 b/topology/sof/pipe-src-capture.m4 index dc55dd2..96d7ee7 100644 --- a/topology/sof/pipe-src-capture.m4 +++ b/topology/sof/pipe-src-capture.m4 @@ -37,9 +37,11 @@ W_SRC(0, PIPELINE_FORMAT, 4, 4, media_src_conf, 2)

# Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP)

# # DAI definitions @@ -56,7 +58,7 @@ W_PIPELINE(N_DAI_IN, SCHEDULE_DEADLINE, SCHEDULE_PRIORITY, SCHEDULE_FRAMES, # # Pipeline Graph # -# host PCM_P --> B0 --> SRC 0 --> B1 --> sink DAI0 +# host PCM_P <-- B0 <-- SRC 0 <-- B1 <-- sink DAI0

SectionGraph."pipe-pass-src-capture-PIPELINE_ID" { index STR(PIPELINE_ID) diff --git a/topology/sof/pipe-src-playback.m4 b/topology/sof/pipe-src-playback.m4 index d037543..a6141c9 100644 --- a/topology/sof/pipe-src-playback.m4 +++ b/topology/sof/pipe-src-playback.m4 @@ -37,9 +37,11 @@ W_SRC(0, PIPELINE_FORMAT, 4, 4, media_src_conf, 2)

# Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(4, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP)

# # DAI definitions diff --git a/topology/sof/pipe-tone.m4 b/topology/sof/pipe-tone.m4 index e04a1b9..a8064ab 100644 --- a/topology/sof/pipe-tone.m4 +++ b/topology/sof/pipe-tone.m4 @@ -54,9 +54,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, KCONTROLS("Tone Volume PIPELINE_ID"))

# Low Latency Buffers W_BUFFER(0,COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_COMP_MEM_CAP)

# diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 58e5393..2fd6b98 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -51,9 +51,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Capture Volume"))

# Capture Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP)

# # DAI definitions diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index 8aa02fb..9431177 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -77,9 +77,11 @@ W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, KCONTROLS("Master Playback Volume Switch", "M

# Playback Buffers W_BUFFER(0, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_HOST_MEM_CAP) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES), + PLATFORM_DAI_MEM_CAP)

# # DAI definitions diff --git a/topology/sof/tokens.m4 b/topology/sof/tokens.m4 index 704effc..6b966b3 100644 --- a/topology/sof/tokens.m4 +++ b/topology/sof/tokens.m4 @@ -11,6 +11,7 @@

SectionVendorTokens."sof_buffer_tokens" { SOF_TKN_BUF_SIZE "100" + SOF_TKN_BUF_CAPS "101" }

SectionVendorTokens."sof_dai_tokens" { diff --git a/topology/test/tplg-build.sh b/topology/test/tplg-build.sh index 047ef6b..9022d1c 100755 --- a/topology/test/tplg-build.sh +++ b/topology/test/tplg-build.sh @@ -8,7 +8,7 @@ set -e

# M4 preprocessor flags -M4_FLAGS="-I ../ -I ../m4" +M4_FLAGS="-I ../ -I ../m4 -I ../common"

# Simple component test cases # can be used on components with 1 sink and 1 source.