[PATCH] ASoC: rt711-sdca: fix the latency time of clock stop prepare state machine transitions
From: Shuming Fan shumingf@realtek.com
Due to the hardware behavior, it takes some time for CBJ detection/impedance sensing/de-bounce. The ClockStop_NotFinished flag will be raised until these functions are completed. In ClockStopMode0 mode case, the SdW controller might check this flag from D3 to D0 when the jack detection interrupt happened.
Signed-off-by: Shuming Fan shumingf@realtek.com --- sound/soc/codecs/rt711-sdca-sdw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/rt711-sdca-sdw.c b/sound/soc/codecs/rt711-sdca-sdw.c index 4120842fe699..88a8392a58ed 100644 --- a/sound/soc/codecs/rt711-sdca-sdw.c +++ b/sound/soc/codecs/rt711-sdca-sdw.c @@ -230,7 +230,7 @@ static int rt711_sdca_read_prop(struct sdw_slave *slave) }
/* set the timeout values */ - prop->clk_stop_timeout = 20; + prop->clk_stop_timeout = 700;
/* wake-up event */ prop->wake_capable = 1;
On Wed, 16 Nov 2022 17:03:18 +0800, shumingf@realtek.com wrote:
From: Shuming Fan shumingf@realtek.com
Due to the hardware behavior, it takes some time for CBJ detection/impedance sensing/de-bounce. The ClockStop_NotFinished flag will be raised until these functions are completed. In ClockStopMode0 mode case, the SdW controller might check this flag from D3 to D0 when the jack detection interrupt happened.
[...]
Applied to
broonie/sound.git for-next
Thanks!
[1/1] ASoC: rt711-sdca: fix the latency time of clock stop prepare state machine transitions commit: c7d7d4e7bb1290cc473610b0bb96d9fa606d00e7
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
On 11/16/22 03:03, shumingf@realtek.com wrote:
From: Shuming Fan shumingf@realtek.com
Due to the hardware behavior, it takes some time for CBJ detection/impedance sensing/de-bounce. The ClockStop_NotFinished flag will be raised until these functions are completed.
That's fine.
In ClockStopMode0 mode case, the SdW controller might check this flag from D3 to D0 when the jack detection interrupt happened.
That's more confusing. The clock stop sequence is only used in transitions from D0 to D3. The timeout is only meant to signal how long the controller driver needs to check the device is ready before stopping the clock. The resume operation does not require any interaction between controller and device drivers.
Is this an inversion in the wording, or a requirement for the controller driver to do something during the resume sequence from D3 to D0?
Signed-off-by: Shuming Fan shumingf@realtek.com
sound/soc/codecs/rt711-sdca-sdw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/rt711-sdca-sdw.c b/sound/soc/codecs/rt711-sdca-sdw.c index 4120842fe699..88a8392a58ed 100644 --- a/sound/soc/codecs/rt711-sdca-sdw.c +++ b/sound/soc/codecs/rt711-sdca-sdw.c @@ -230,7 +230,7 @@ static int rt711_sdca_read_prop(struct sdw_slave *slave) }
/* set the timeout values */
- prop->clk_stop_timeout = 20;
prop->clk_stop_timeout = 700;
/* wake-up event */ prop->wake_capable = 1;
Due to the hardware behavior, it takes some time for CBJ
detection/impedance sensing/de-bounce.
The ClockStop_NotFinished flag will be raised until these functions are
completed.
That's fine.
In ClockStopMode0 mode case, the SdW controller might check this flag from D3 to D0 when the jack detection interrupt happened.
That's more confusing. The clock stop sequence is only used in transitions from D0 to D3. The timeout is only meant to signal how long the controller driver needs to check the device is ready before stopping the clock. The resume operation does not require any interaction between controller and device drivers.
Is this an inversion in the wording, or a requirement for the controller driver to do something during the resume sequence from D3 to D0?
I wrote it wrongly. It is in the clock stop case, not ClockStopMode0. This issue was reported by AMD. If the jack is plugged in/plugged out when SdW controller is in D3 state, the controller will receive the wake event. They will execute the clock stop exit sequence.
participants (4)
-
Mark Brown -
Pierre-Louis Bossart -
Shuming [范書銘] -
shumingf＠realtek.com