Due to the hardware behavior, it takes some time for CBJ
detection/impedance sensing/de-bounce.
The ClockStop_NotFinished flag will be raised until these functions are
completed.
That's fine.
In ClockStopMode0 mode case, the SdW controller might check this flag from D3 to D0 when the jack detection interrupt happened.
That's more confusing. The clock stop sequence is only used in transitions from D0 to D3. The timeout is only meant to signal how long the controller driver needs to check the device is ready before stopping the clock. The resume operation does not require any interaction between controller and device drivers.
Is this an inversion in the wording, or a requirement for the controller driver to do something during the resume sequence from D3 to D0?
I wrote it wrongly. It is in the clock stop case, not ClockStopMode0. This issue was reported by AMD. If the jack is plugged in/plugged out when SdW controller is in D3 state, the controller will receive the wake event. They will execute the clock stop exit sequence.