[alsa-devel] ASoC: pxa2xx-i2s
bgr at acdstar.com
Thu Jan 22 18:03:42 CET 2009
Mark Brown wrote:
> On Wed, Jan 21, 2009 at 02:13:12PM -0600, Brian Rhodes wrote:
>> No, the 270 is the clock master on the I2S bus. The codec is sourcing
>> the clock input using the PLL. I apologize for being unclear.
> I think it's me that's not being clear, sorry - I'm trying to find out
> is if the LRCLK and BCLK signals on the I2S bus itself are being driven
> by the codec or by the I2S controller. If the codec driver is the clock
> master then your earlier speculation that your problems with the I2S
> controller may be due to some interaction with the codec driver are more
> likely to be true.
LCRK and BCLK are configured as inputs. The Codec is not the bus master.
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