[alsa-devel] ASoC: pxa2xx-i2s
bgr at acdstar.com
Fri Jan 23 17:50:39 CET 2009
Mark Brown wrote:
> On Wed, Jan 21, 2009 at 02:13:12PM -0600, Brian Rhodes wrote:
>> No, the 270 is the clock master on the I2S bus. The codec is sourcing
>> the clock input using the PLL. I apologize for being unclear.
> I think it's me that's not being clear, sorry - I'm trying to find out
> is if the LRCLK and BCLK signals on the I2S bus itself are being driven
> by the codec or by the I2S controller. If the codec driver is the clock
> master then your earlier speculation that your problems with the I2S
> controller may be due to some interaction with the codec driver are more
> likely to be true.
I'm curious if you think this problem may be arising from the toggling
of the direction of BCLK on the PXA while the I2S clock is enabled. I'm
sure there are people who have a reason for switching the bit clock
master, but I'm thinking that this should not be explicitly done if it
is not changing.
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