[alsa-devel] Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge

[Nicolin Chen]

On Thu, May 28, 2015 at 03:02:31PM +0800, Xuebing Wang wrote:

> According to iMX6SL reference manual, 'TSCKP = 1' means "Data clocked out on
> *falling* edge of bit clock." (for I2S master mode), rather than "Data on
> rising edge of bclk in the comments". This means this comment in the source
> code is *partially* WRONG, am I correct?

As you can see, it says "clock out on falling edge" which means
for the receiver is still latching the data at the rising edge.

Nicolin