[alsa-devel] Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge

[Xuebing Wang]

Nicolin and alsa-devel community:

Source code in fsl_ssi.c shows below in function fsl_ssi_set_dai_fmt():
-----------
     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
     case SND_SOC_DAIFMT_I2S:
... ...
         /* Data on rising edge of bclk, frame low, 1clk before data */
         strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP
             | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
         break;
-----------

According to iMX6SL reference manual, 'TSCKP = 1' means "Data clocked 
out on *falling* edge of bit clock." (for I2S master mode), rather than 
"Data on rising edge of bclk in the comments". This means this comment 
in the source code is *partially* WRONG, am I correct?

However, RSCKP is = 1 (for receiving), it means "Data latched on rising 
edge of bit clock", which is correct.

Also, I am not sure why there is inconsistency in iMX6SL reference 
manual (48.9 SSI Memory Map/Register Definition), that TSCKP = 1 (for 
transmitting) is FALLING_EDGE, but RSCKP = 1 (for receiving) is RISING_EDGE.

Note: SSI (I2S master mode) works perfect on my hardware, I did not 
observe anything wrong.

Thanks.

-- 
Xuebing