On Thu, 2020-06-04 at 17:42 +0300, Daniel Baluta wrote:
Hi Liam, Ranjani,
I am now looking at implementing the PM features on i.MX platforms and I have some questions.
- Where can I find some documentation about the SHIM
layer PM related registers.
Hi Daniel,
I am afraid the documentation related to these registers in Intel confidential and cannot be shared externally.
e.g apollolake/include/platform/lib/shim.h:
#define SHIM_PWRCTL 0
- I am looking if it makes sense to have some generic Xtensa
code to put the core in reset at PM suspend. I have seen this registers:
arch/xtensa/include/xtensa/xdm-regs.h: #define PWRCTL_CORE_RESET
But these are platform-specific registers and should be done in the platform-specific code isnt it?
I wonder if this would make sense for Intel side? Is there any documentation about the PM states of HIfi DSP in Intel integrations?
The power states supported by the DSP differ based on the platform. For example, the low power D0i3 state. It is Intel specific and may not apply to other architectures.
Thanks, Ranjani