[Sound-open-firmware] Generic power management layer
Hi Liam, Ranjani,
I am now looking at implementing the PM features on i.MX platforms and I have some questions.
1) Where can I find some documentation about the SHIM layer PM related registers.
e.g apollolake/include/platform/lib/shim.h:
#define SHIM_PWRCTL 0
2) I am looking if it makes sense to have some generic Xtensa code to put the core in reset at PM suspend. I have seen this registers:
arch/xtensa/include/xtensa/xdm-regs.h: #define PWRCTL_CORE_RESET
I wonder if this would make sense for Intel side? Is there any documentation about the PM states of HIfi DSP in Intel integrations?
thanks, Daniel.
On Thu, 2020-06-04 at 17:42 +0300, Daniel Baluta wrote:
Hi Liam, Ranjani,
I am now looking at implementing the PM features on i.MX platforms and I have some questions.
- Where can I find some documentation about the SHIM
layer PM related registers.
e.g apollolake/include/platform/lib/shim.h:
#define SHIM_PWRCTL 0
- I am looking if it makes sense to have some generic Xtensa
code to put the core in reset at PM suspend. I have seen this registers:
arch/xtensa/include/xtensa/xdm-regs.h: #define PWRCTL_CORE_RESET
I wonder if this would make sense for Intel side? Is there any documentation about the PM states of HIfi DSP in Intel integrations?
I think Marcin did some PM docs on sof-docs, on CC now.
Liam
thanks, Daniel. _______________________________________________ Sound-open-firmware mailing list Sound-open-firmware@alsa-project.org https://mailman.alsa-project.org/mailman/listinfo/sound-open-firmware
On Thu, 2020-06-04 at 17:42 +0300, Daniel Baluta wrote:
Hi Liam, Ranjani,
I am now looking at implementing the PM features on i.MX platforms and I have some questions.
- Where can I find some documentation about the SHIM
layer PM related registers.
Hi Daniel,
I am afraid the documentation related to these registers in Intel confidential and cannot be shared externally.
e.g apollolake/include/platform/lib/shim.h:
#define SHIM_PWRCTL 0
- I am looking if it makes sense to have some generic Xtensa
code to put the core in reset at PM suspend. I have seen this registers:
arch/xtensa/include/xtensa/xdm-regs.h: #define PWRCTL_CORE_RESET
But these are platform-specific registers and should be done in the platform-specific code isnt it?
I wonder if this would make sense for Intel side? Is there any documentation about the PM states of HIfi DSP in Intel integrations?
The power states supported by the DSP differ based on the platform. For example, the low power D0i3 state. It is Intel specific and may not apply to other architectures.
Thanks, Ranjani
On 04.06.2020 19:20, Sridharan, Ranjani wrote:
On Thu, 2020-06-04 at 17:42 +0300, Daniel Baluta wrote:
Hi Liam, Ranjani,
I am now looking at implementing the PM features on i.MX platforms and I have some questions.
- Where can I find some documentation about the SHIM
layer PM related registers.
Hi Daniel,
I am afraid the documentation related to these registers in Intel confidential and cannot be shared externally.
e.g apollolake/include/platform/lib/shim.h:
#define SHIM_PWRCTL 0
- I am looking if it makes sense to have some generic Xtensa
code to put the core in reset at PM suspend. I have seen this registers:
arch/xtensa/include/xtensa/xdm-regs.h: #define PWRCTL_CORE_RESET
But these are platform-specific registers and should be done in the platform-specific code isnt it?
It is my impression that PWRCTL_* registers from
src/xtensa/include/xtensa/xdm-regs are not platform specific
but Xtensa arch specific. So, in theory because NXP/Intel
use the same architecture we could design some basic generic
PM functions.
Anyhow, for now I will concentrate on NXP specific stuff.
Thanks a lot for your answer.
On 6/4/2020 6:27 PM, Daniel Baluta wrote:
On 04.06.2020 19:20, Sridharan, Ranjani wrote:
On Thu, 2020-06-04 at 17:42 +0300, Daniel Baluta wrote:
Hi Liam, Ranjani,
I am now looking at implementing the PM features on i.MX platforms and I have some questions.
- Where can I find some documentation about the SHIM
layer PM related registers.
Hi Daniel,
I am afraid the documentation related to these registers in Intel confidential and cannot be shared externally.
e.g apollolake/include/platform/lib/shim.h:
#define SHIM_PWRCTL 0
- I am looking if it makes sense to have some generic Xtensa
code to put the core in reset at PM suspend. I have seen this registers:
arch/xtensa/include/xtensa/xdm-regs.h: #define PWRCTL_CORE_RESET
But these are platform-specific registers and should be done in the platform-specific code isnt it?
It is my impression that PWRCTL_* registers from
src/xtensa/include/xtensa/xdm-regs are not platform specific
but Xtensa arch specific. So, in theory because NXP/Intel
use the same architecture we could design some basic generic
PM functions.
Both common PM flows implemented in the generic layer as well as Intel specific mechanisms are documented here
https://thesofproject.github.io/latest/developer_guides/firmware/pm-runtime/...
We do not use any Xtensa registers directly. All PM on Intel platforms, including things I was talking about during the last TSC meeting, is done via shim registers which are platform specific.
Regards, Marcin
Anyhow, for now I will concentrate on NXP specific stuff.
Thanks a lot for your answer.
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participants (5)
-
Daniel Baluta -
Daniel Baluta -
Liam Girdwood -
Marcin Maka -
Sridharan, Ranjani