Add differentiation M4 header macros for the Intel Cannonlake platform.
Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com --- topology/dsps/Makefile.am | 3 +- topology/dsps/cnl.m4 | 108 +++++++++++++++++++++++++++++++++++++++++++++ topology/reef-cnl-rt274.m4 | 2 +- 3 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 topology/dsps/cnl.m4
diff --git a/topology/dsps/Makefile.am b/topology/dsps/Makefile.am index 9bbade7..d4c8dd6 100644 --- a/topology/dsps/Makefile.am +++ b/topology/dsps/Makefile.am @@ -3,5 +3,6 @@ EXTRA_DIST = \ bxt.m4 \ byt.m4 \ cht.m4 \ - hsw.m4 + hsw.m4 \ + cnl.m4
diff --git a/topology/dsps/cnl.m4 b/topology/dsps/cnl.m4 new file mode 100644 index 0000000..547c689 --- /dev/null +++ b/topology/dsps/cnl.m4 @@ -0,0 +1,108 @@ +# +# Broxton differentiation for pipelines and components +# + +include(`memory.m4') + +dnl Memory capabilities for diferent buffer types on Cannonlake +define(`PLATFORM_DAI_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_HOST_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_PASS_MEM_CAP', + MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + +# Low Latency PCM Configuration +SectionVendorTuples."pipe_ll_schedule_plat_tokens" { + tokens "sof_sched_tokens" + + tuples."word" { + SOF_TKN_SCHED_MIPS "50000" + } +} + +SectionData."pipe_ll_schedule_plat" { + tuples "pipe_ll_schedule_plat_tokens" +} + +# Media PCM Configuration +SectionVendorTuples."pipe_media_schedule_plat_tokens" { + tokens "sof_sched_tokens" + + tuples."word" { + SOF_TKN_SCHED_MIPS "100000" + } +} + +SectionData."pipe_media_schedule_plat" { + tuples "pipe_media_schedule_plat_tokens" +} + +# Tone Signal Generator Configuration +SectionVendorTuples."pipe_tone_schedule_plat_tokens" { + tokens "sof_sched_tokens" + + tuples."word" { + SOF_TKN_SCHED_MIPS "200000" + } +} + +SectionData."pipe_tone_schedule_plat" { + tuples "pipe_tone_schedule_plat_tokens" +} + +# DAI0 platform playback configuration +SectionVendorTuples."dai0p_plat_tokens" { + tokens "sof_dai_tokens" + + tuples."word" { + SOF_TKN_DAI_DMAC "1" + SOF_TKN_DAI_DMAC_CHAN "0" + } +} + +SectionData."dai0p_plat_conf" { + tuples "dai0p_plat_tokens" +} + +# DAI0 platform capture configuration +SectionVendorTuples."dai0c_plat_tokens" { + tokens "sof_dai_tokens" + + tuples."word" { + SOF_TKN_DAI_DMAC "1" + SOF_TKN_DAI_DMAC_CHAN "1" + } +} + +SectionData."dai0c_plat_conf" { + tuples "dai0c_plat_tokens" +} + +# PCM platform configuration +SectionVendorTuples."pcm_plat_tokens" { + tokens "sof_dai_tokens" + + tuples."word" { + SOF_TKN_DAI_DMAC PIPELINE_DMAC + SOF_TKN_DAI_DMAC_CHAN PIPELINE_DMAC_CHAN + } +} + +SectionData."pcm_plat_conf" { + tuples "pcm_plat_tokens" +} + +# DAI schedule Configuration - scheduled by IRQ +SectionVendorTuples."pipe_dai_schedule_plat_tokens" { + tokens "sof_sched_tokens" + + tuples."word" { + SOF_TKN_SCHED_MIPS "5000" + } +} + +SectionData."pipe_dai_schedule_plat" { + tuples "pipe_dai_schedule_plat_tokens" +} diff --git a/topology/reef-cnl-rt274.m4 b/topology/reef-cnl-rt274.m4 index 67aab04..f91a74f 100644 --- a/topology/reef-cnl-rt274.m4 +++ b/topology/reef-cnl-rt274.m4 @@ -13,7 +13,7 @@ include(`common/tlv.m4') include(`sof/tokens.m4')
# Include Apollolake DSP configuration -include(`dsps/bxt.m4') +include(`dsps/cnl.m4')
# # Define the pipelines