On Thu, 2018-04-26 at 11:43 +0800, Pan, Xiuli wrote:
On 4/25/2018 22:56, Pierre-Louis Bossart wrote:
On 4/25/18 1:50 AM, Xiuli Pan wrote:
From: Pan Xiuli xiuli.pan@linux.intel.com
Send the memory window offset with the panic IPC in case the panic happen before DSP ready when the memory window info is sent.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
TODO: Need to find a register for HSW and BDW.
what do you mean with this TODO? You sent a set of kernel patches for HSW and BDW, what's missing on the firmware side then?
Yes, I was still looking for a register to handle these issues. On BYT there is 64 bit IPC message and on APL or CNL, there are two 32 bit registers. But one HSW and BDW, only one 32 bit register is used. There should be some other method or register to do the similar things.
You have IPCD and IPCX. You can encode the offset for the start of the trace mailbox in one of them (and copy the tracepoint status to mbox too).