[Sound-open-firmware] [PATCH 0/2] SOF: panic hanlder refine
From: Pan Xiuli xiuli.pan@linux.intel.com
Send exception offset via IPC in case of DPS is not ready with memory window.
Used with SOF kernel patches: ASoC: SOF: Add panic handler ops header ASoC: SOF: Add panic handler ops function ASoC: SOF: BYT: Refnie panic handler ASoC: SOF: HSW: Refnie panic handler ASoC: SOF: BDW: Refnie panic handler ASoC: SOF: APL: Refnie panic handler
Pan Xiuli (2): mailbox: use mailbox function for SW_REG platform: panice: Send exception memory offset via IPC
src/include/sof/mailbox.h | 14 ++++++++++++++ src/platform/apollolake/include/platform/platform.h | 7 +++++-- src/platform/baytrail/include/platform/platform.h | 3 ++- src/platform/cannonlake/include/platform/platform.h | 7 +++++-- 4 files changed, 26 insertions(+), 5 deletions(-)
From: Pan Xiuli xiuli.pan@linux.intel.com
SW_REG is in memory window and the cache is enabled, need to writeback the SW_REG.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
--- Test with: Mininow max rt5651 and UP2 nocodec and CNL nocodec SOF master: 3ad69eb715a09de9a0b91c56c9cca8a79ead00a9 SOF-Tool master: b327539e98f1c84e3a131dd048460189a5de8c26 https://github.com/plbossart/sound/tree/topic/sof-v4.14: 735b995d7b66485c19e0aed51131532075cfce42 --- src/include/sof/mailbox.h | 14 ++++++++++++++ src/platform/apollolake/include/platform/platform.h | 6 ++++-- src/platform/cannonlake/include/platform/platform.h | 6 ++++-- 3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/include/sof/mailbox.h b/src/include/sof/mailbox.h index 59259a0..17d9daa 100644 --- a/src/include/sof/mailbox.h +++ b/src/include/sof/mailbox.h @@ -26,6 +26,7 @@ * POSSIBILITY OF SUCH DAMAGE. * * Author: Liam Girdwood liam.r.girdwood@linux.intel.com + * Xiuli Pan xiuli.pan@linux.intel.com */
#ifndef __INCLUDE_MAILBOX__ @@ -36,6 +37,11 @@ #include <stdint.h> #include <sof/string.h>
+/* For those platform did not have SW_REG window, use DEBUG at now */ +#ifndef MAILBOX_SW_REG_BASE +#define MAILBOX_SW_REG_BASE MAILBOX_DEBUG_BASE +#endif /* MAILBOX_SW_REG_BASE */ + /* 4k should be enough for everyone ..... */ #define IPC_MAX_MAILBOX_BYTES 0x1000
@@ -100,4 +106,12 @@ void mailbox_stream_write(size_t offset, const void *src, size_t bytes) bytes); }
+static inline +void mailbox_sw_reg_write(size_t offset, uint32_t src) +{ + *((volatile uint32_t*)(MAILBOX_SW_REG_BASE + offset)) = src; + dcache_writeback_region((void *)(MAILBOX_SW_REG_BASE + offset), + sizeof(src)); +} + #endif diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 8503ce2..92f5b77 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -27,6 +27,7 @@ * * Author: Liam Girdwood liam.r.girdwood@linux.intel.com * Keyon Jie yang.jie@linux.intel.com + * Xiuli Pan xiuli.pan@linux.intel.com */
#ifndef __PLATFORM_PLATFORM_H__ @@ -117,13 +118,14 @@ struct sof;
/* Platform defined panic code */ #define platform_panic(__x) { \ - sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ + (0xdead000 | __x) & 0x3fffffff); \ ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
/* Platform defined trace code */ #define platform_trace_point(__x) \ - sw_reg_write(SRAM_REG_FW_TRACEP, __x) + mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, __x)
extern struct timer *platform_timer;
diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index c5bf42a..aff90a7 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -28,6 +28,7 @@ * Author: Liam Girdwood liam.r.girdwood@linux.intel.com * Keyon Jie yang.jie@linux.intel.com * Rander Wang rander.wang@intel.com + * Xiuli Pan xiuli.pan@linux.intel.com */
#ifndef __PLATFORM_PLATFORM_H__ @@ -112,13 +113,14 @@ struct sof;
/* Platform defined trace code */ #define platform_panic(__x) { \ - sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ + (0xdead000 | __x) & 0x3fffffff); \ ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
/* Platform defined trace code */ #define platform_trace_point(__x) \ - sw_reg_write(SRAM_REG_FW_TRACEP, __x) + mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, __x)
extern struct timer *platform_timer;
On 4/25/18 1:50 AM, Xiuli Pan wrote:
From: Pan Xiuli xiuli.pan@linux.intel.com
SW_REG is in memory window and the cache is enabled, need to writeback the SW_REG.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
Test with: Mininow max rt5651 and UP2 nocodec and CNL nocodec SOF master: 3ad69eb715a09de9a0b91c56c9cca8a79ead00a9 SOF-Tool master: b327539e98f1c84e3a131dd048460189a5de8c26 https://github.com/plbossart/sound/tree/topic/sof-v4.14: 735b995d7b66485c19e0aed51131532075cfce42
src/include/sof/mailbox.h | 14 ++++++++++++++ src/platform/apollolake/include/platform/platform.h | 6 ++++-- src/platform/cannonlake/include/platform/platform.h | 6 ++++-- 3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/include/sof/mailbox.h b/src/include/sof/mailbox.h index 59259a0..17d9daa 100644 --- a/src/include/sof/mailbox.h +++ b/src/include/sof/mailbox.h @@ -26,6 +26,7 @@
- POSSIBILITY OF SUCH DAMAGE.
- Author: Liam Girdwood liam.r.girdwood@linux.intel.com
Xiuli Pan <xiuli.pan@linux.intel.com>*/
#ifndef __INCLUDE_MAILBOX__
@@ -36,6 +37,11 @@ #include <stdint.h> #include <sof/string.h>
+/* For those platform did not have SW_REG window, use DEBUG at now */ +#ifndef MAILBOX_SW_REG_BASE +#define MAILBOX_SW_REG_BASE MAILBOX_DEBUG_BASE +#endif /* MAILBOX_SW_REG_BASE */
this is really a work-around to compile on legacy platforms, right? The value has no impact or meaning.
- /* 4k should be enough for everyone ..... */ #define IPC_MAX_MAILBOX_BYTES 0x1000
@@ -100,4 +106,12 @@ void mailbox_stream_write(size_t offset, const void *src, size_t bytes) bytes); }
+static inline +void mailbox_sw_reg_write(size_t offset, uint32_t src) +{
- *((volatile uint32_t*)(MAILBOX_SW_REG_BASE + offset)) = src;
- dcache_writeback_region((void *)(MAILBOX_SW_REG_BASE + offset),
sizeof(src));+}
- #endif
diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 8503ce2..92f5b77 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -27,6 +27,7 @@
- Author: Liam Girdwood liam.r.girdwood@linux.intel.com
Keyon Jie <yang.jie@linux.intel.com>
Xiuli Pan <xiuli.pan@linux.intel.com>*/
#ifndef __PLATFORM_PLATFORM_H__
@@ -117,13 +118,14 @@ struct sof;
/* Platform defined panic code */ #define platform_panic(__x) { \
- sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \
- mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \
(0xdead000 | __x) & 0x3fffffff); \
can you either resubmit or send a follow-up patch with the argument __x in parenthesis to protect against unintended macro expansion issues, e.g. + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \
(0xdead000 | (__x)) & 0x3fffffff); \
ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
/* Platform defined trace code */ #define platform_trace_point(__x) \
- sw_reg_write(SRAM_REG_FW_TRACEP, __x)
mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, __x)
extern struct timer *platform_timer;
diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index c5bf42a..aff90a7 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -28,6 +28,7 @@
- Author: Liam Girdwood liam.r.girdwood@linux.intel.com
Keyon Jie <yang.jie@linux.intel.com>Rander Wang <rander.wang@intel.com>
Xiuli Pan <xiuli.pan@linux.intel.com>*/
#ifndef __PLATFORM_PLATFORM_H__
@@ -112,13 +113,14 @@ struct sof;
/* Platform defined trace code */ #define platform_panic(__x) { \
- sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \
mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \
(0xdead000 | __x) & 0x3fffffff); \ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
/* Platform defined trace code */ #define platform_trace_point(__x) \
- sw_reg_write(SRAM_REG_FW_TRACEP, __x)
mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, __x)
extern struct timer *platform_timer;
On 4/25/2018 22:53, Pierre-Louis Bossart wrote:
On 4/25/18 1:50 AM, Xiuli Pan wrote:
From: Pan Xiuli xiuli.pan@linux.intel.com
SW_REG is in memory window and the cache is enabled, need to writeback the SW_REG.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
Test with: Mininow max rt5651 and UP2 nocodec and CNL nocodec SOF master: 3ad69eb715a09de9a0b91c56c9cca8a79ead00a9 SOF-Tool master: b327539e98f1c84e3a131dd048460189a5de8c26 https://github.com/plbossart/sound/tree/topic/sof-v4.14: 735b995d7b66485c19e0aed51131532075cfce42
src/include/sof/mailbox.h | 14 ++++++++++++++ src/platform/apollolake/include/platform/platform.h | 6 ++++-- src/platform/cannonlake/include/platform/platform.h | 6 ++++-- 3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/include/sof/mailbox.h b/src/include/sof/mailbox.h index 59259a0..17d9daa 100644 --- a/src/include/sof/mailbox.h +++ b/src/include/sof/mailbox.h @@ -26,6 +26,7 @@ * POSSIBILITY OF SUCH DAMAGE. * * Author: Liam Girdwood liam.r.girdwood@linux.intel.com
- * Xiuli Pan xiuli.pan@linux.intel.com
*/ #ifndef __INCLUDE_MAILBOX__ @@ -36,6 +37,11 @@ #include <stdint.h> #include <sof/string.h> +/* For those platform did not have SW_REG window, use DEBUG at now */ +#ifndef MAILBOX_SW_REG_BASE +#define MAILBOX_SW_REG_BASE MAILBOX_DEBUG_BASE +#endif /* MAILBOX_SW_REG_BASE */
this is really a work-around to compile on legacy platforms, right? The value has no impact or meaning.
Yes, this is only for the lagacy platform compiling.
/* 4k should be enough for everyone ..... */ #define IPC_MAX_MAILBOX_BYTES 0x1000 @@ -100,4 +106,12 @@ void mailbox_stream_write(size_t offset, const void *src, size_t bytes) bytes); } +static inline +void mailbox_sw_reg_write(size_t offset, uint32_t src) +{ + *((volatile uint32_t*)(MAILBOX_SW_REG_BASE + offset)) = src; + dcache_writeback_region((void *)(MAILBOX_SW_REG_BASE + offset), + sizeof(src)); +}
#endif diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 8503ce2..92f5b77 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -27,6 +27,7 @@ * * Author: Liam Girdwood liam.r.girdwood@linux.intel.com * Keyon Jie yang.jie@linux.intel.com
- * Xiuli Pan xiuli.pan@linux.intel.com
*/ #ifndef __PLATFORM_PLATFORM_H__ @@ -117,13 +118,14 @@ struct sof; /* Platform defined panic code */ #define platform_panic(__x) { \ - sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ + (0xdead000 | __x) & 0x3fffffff); \
can you either resubmit or send a follow-up patch with the argument __x in parenthesis to protect against unintended macro expansion issues, e.g. + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \
+ (0xdead000 | (__x)) & 0x3fffffff); \
work on the TODO for bdw and hsw. Will send a V2 soon.
Thanks Xiuli
ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ } /* Platform defined trace code */ #define platform_trace_point(__x) \ - sw_reg_write(SRAM_REG_FW_TRACEP, __x) + mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, __x) extern struct timer *platform_timer; diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index c5bf42a..aff90a7 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -28,6 +28,7 @@ * Author: Liam Girdwood liam.r.girdwood@linux.intel.com * Keyon Jie yang.jie@linux.intel.com * Rander Wang rander.wang@intel.com
- * Xiuli Pan xiuli.pan@linux.intel.com
*/ #ifndef __PLATFORM_PLATFORM_H__ @@ -112,13 +113,14 @@ struct sof; /* Platform defined trace code */ #define platform_panic(__x) { \ - sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ + (0xdead000 | __x) & 0x3fffffff); \ ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ } /* Platform defined trace code */ #define platform_trace_point(__x) \ - sw_reg_write(SRAM_REG_FW_TRACEP, __x) + mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, __x) extern struct timer *platform_timer;
Sound-open-firmware mailing list Sound-open-firmware@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/sound-open-firmware
From: Pan Xiuli xiuli.pan@linux.intel.com
Send the memory window offset with the panic IPC in case the panic happen before DSP ready when the memory window info is sent.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
--- TODO: Need to find a register for HSW and BDW.
Test with: Mininow max rt5651 and UP2 nocodec and CNL nocodec SOF master: 3ad69eb715a09de9a0b91c56c9cca8a79ead00a9 SOF-Tool master: b327539e98f1c84e3a131dd048460189a5de8c26 https://github.com/plbossart/sound/tree/topic/sof-v4.14: 735b995d7b66485c19e0aed51131532075cfce42 --- src/platform/apollolake/include/platform/platform.h | 1 + src/platform/baytrail/include/platform/platform.h | 3 ++- src/platform/cannonlake/include/platform/platform.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 92f5b77..fb496f5 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -120,6 +120,7 @@ struct sof; #define platform_panic(__x) { \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ (0xdead000 | __x) & 0x3fffffff); \ + ipc_write(IPC_DIPCIE, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); \ ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
diff --git a/src/platform/baytrail/include/platform/platform.h b/src/platform/baytrail/include/platform/platform.h index 4d32d5e..6a7ebc9 100644 --- a/src/platform/baytrail/include/platform/platform.h +++ b/src/platform/baytrail/include/platform/platform.h @@ -27,6 +27,7 @@ * * Author: Liam Girdwood liam.r.girdwood@linux.intel.com * Keyon Jie yang.jie@linux.intel.com + * Xiuli Pan xiuli.pan@linux.intel.com */
#ifndef __PLATFORM_PLATFORM_H__ @@ -103,7 +104,7 @@ struct sof; /* Platform defined panic code */ #define platform_panic(__x) { \ shim_write(SHIM_IPCDL, (0xdead000 | (__x & 0xfff))); \ - shim_write(SHIM_IPCDH, SHIM_IPCDH_BUSY); \ + shim_write(SHIM_IPCDH, (SHIM_IPCDH_BUSY | MAILBOX_EXCEPTION_OFFSET)); \ }
/* Platform defined trace code */ diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index aff90a7..d7fa0dd 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -115,6 +115,7 @@ struct sof; #define platform_panic(__x) { \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ (0xdead000 | __x) & 0x3fffffff); \ + ipc_write(IPC_DIPCIDD, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); \ ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
On 4/25/18 1:50 AM, Xiuli Pan wrote:
From: Pan Xiuli xiuli.pan@linux.intel.com
Send the memory window offset with the panic IPC in case the panic happen before DSP ready when the memory window info is sent.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
TODO: Need to find a register for HSW and BDW.
what do you mean with this TODO? You sent a set of kernel patches for HSW and BDW, what's missing on the firmware side then?
Test with: Mininow max rt5651 and UP2 nocodec and CNL nocodec SOF master: 3ad69eb715a09de9a0b91c56c9cca8a79ead00a9 SOF-Tool master: b327539e98f1c84e3a131dd048460189a5de8c26 https://github.com/plbossart/sound/tree/topic/sof-v4.14: 735b995d7b66485c19e0aed51131532075cfce42
src/platform/apollolake/include/platform/platform.h | 1 + src/platform/baytrail/include/platform/platform.h | 3 ++- src/platform/cannonlake/include/platform/platform.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 92f5b77..fb496f5 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -120,6 +120,7 @@ struct sof; #define platform_panic(__x) { \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ (0xdead000 | __x) & 0x3fffffff); \
- ipc_write(IPC_DIPCIE, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); \ ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
diff --git a/src/platform/baytrail/include/platform/platform.h b/src/platform/baytrail/include/platform/platform.h index 4d32d5e..6a7ebc9 100644 --- a/src/platform/baytrail/include/platform/platform.h +++ b/src/platform/baytrail/include/platform/platform.h @@ -27,6 +27,7 @@
- Author: Liam Girdwood liam.r.girdwood@linux.intel.com
Keyon Jie <yang.jie@linux.intel.com>
Xiuli Pan <xiuli.pan@linux.intel.com>*/
#ifndef __PLATFORM_PLATFORM_H__
@@ -103,7 +104,7 @@ struct sof; /* Platform defined panic code */ #define platform_panic(__x) { \ shim_write(SHIM_IPCDL, (0xdead000 | (__x & 0xfff))); \
- shim_write(SHIM_IPCDH, SHIM_IPCDH_BUSY); \
shim_write(SHIM_IPCDH, (SHIM_IPCDH_BUSY | MAILBOX_EXCEPTION_OFFSET)); \ }
/* Platform defined trace code */
diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index aff90a7..d7fa0dd 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -115,6 +115,7 @@ struct sof; #define platform_panic(__x) { \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ (0xdead000 | __x) & 0x3fffffff); \
- ipc_write(IPC_DIPCIDD, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); \ ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
On 4/25/2018 22:56, Pierre-Louis Bossart wrote:
On 4/25/18 1:50 AM, Xiuli Pan wrote:
From: Pan Xiuli xiuli.pan@linux.intel.com
Send the memory window offset with the panic IPC in case the panic happen before DSP ready when the memory window info is sent.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
TODO: Need to find a register for HSW and BDW.
what do you mean with this TODO? You sent a set of kernel patches for HSW and BDW, what's missing on the firmware side then?
Yes, I was still looking for a register to handle these issues. On BYT there is 64 bit IPC message and on APL or CNL, there are two 32 bit registers. But one HSW and BDW, only one 32 bit register is used. There should be some other method or register to do the similar things.
Thanks Xiuli
Test with: Mininow max rt5651 and UP2 nocodec and CNL nocodec SOF master: 3ad69eb715a09de9a0b91c56c9cca8a79ead00a9 SOF-Tool master: b327539e98f1c84e3a131dd048460189a5de8c26 https://github.com/plbossart/sound/tree/topic/sof-v4.14: 735b995d7b66485c19e0aed51131532075cfce42
src/platform/apollolake/include/platform/platform.h | 1 + src/platform/baytrail/include/platform/platform.h | 3 ++- src/platform/cannonlake/include/platform/platform.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 92f5b77..fb496f5 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -120,6 +120,7 @@ struct sof; #define platform_panic(__x) { \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ (0xdead000 | __x) & 0x3fffffff); \ + ipc_write(IPC_DIPCIE, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); \ ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ } diff --git a/src/platform/baytrail/include/platform/platform.h b/src/platform/baytrail/include/platform/platform.h index 4d32d5e..6a7ebc9 100644 --- a/src/platform/baytrail/include/platform/platform.h +++ b/src/platform/baytrail/include/platform/platform.h @@ -27,6 +27,7 @@ * * Author: Liam Girdwood liam.r.girdwood@linux.intel.com * Keyon Jie yang.jie@linux.intel.com
- * Xiuli Pan xiuli.pan@linux.intel.com
*/ #ifndef __PLATFORM_PLATFORM_H__ @@ -103,7 +104,7 @@ struct sof; /* Platform defined panic code */ #define platform_panic(__x) { \ shim_write(SHIM_IPCDL, (0xdead000 | (__x & 0xfff))); \ - shim_write(SHIM_IPCDH, SHIM_IPCDH_BUSY); \ + shim_write(SHIM_IPCDH, (SHIM_IPCDH_BUSY | MAILBOX_EXCEPTION_OFFSET)); \ } /* Platform defined trace code */ diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index aff90a7..d7fa0dd 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -115,6 +115,7 @@ struct sof; #define platform_panic(__x) { \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \ (0xdead000 | __x) & 0x3fffffff); \ + ipc_write(IPC_DIPCIDD, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); \ ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ }
On Thu, 2018-04-26 at 11:43 +0800, Pan, Xiuli wrote:
On 4/25/2018 22:56, Pierre-Louis Bossart wrote:
On 4/25/18 1:50 AM, Xiuli Pan wrote:
From: Pan Xiuli xiuli.pan@linux.intel.com
Send the memory window offset with the panic IPC in case the panic happen before DSP ready when the memory window info is sent.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
TODO: Need to find a register for HSW and BDW.
what do you mean with this TODO? You sent a set of kernel patches for HSW and BDW, what's missing on the firmware side then?
Yes, I was still looking for a register to handle these issues. On BYT there is 64 bit IPC message and on APL or CNL, there are two 32 bit registers. But one HSW and BDW, only one 32 bit register is used. There should be some other method or register to do the similar things.
You have IPCD and IPCX. You can encode the offset for the start of the trace mailbox in one of them (and copy the tracepoint status to mbox too).
participants (4)
-
Liam Girdwood -
Pan, Xiuli -
Pierre-Louis Bossart -
Xiuli Pan