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[Sound-open-firmware] [PATCH] apl-ssp: change and wrap status transition into ssp_stop
by Keyon Jie 09 May '18

09 May '18

This will remove manual status change, wrap them into ssp_stop(), where the status transition is protect by spin_lock. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- Tested with: APL GPMRB with TDF8532 SOF master: 8b664cee3fa34b38079ff37c624fe58b3d63362d SOF-Tool master: 13b56fa6047c566a8ba3edd0882ea786e595ee2a https://github.com/plbossart/sound/tree/topic/sof-v4.14: d09db67c5a9d6dfc85f700669fa2e43c678c8d51 --- src/drivers/apl-ssp.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/drivers/apl-ssp.c b/src/drivers/apl-ssp.c index 6e33656..a51f91c 100644 --- a/src/drivers/apl-ssp.c +++ b/src/drivers/apl-ssp.c @@ -596,23 +596,27 @@ static void ssp_start(struct dai *dai, int direction) } /* stop the SSP for either playback or capture */ -static void ssp_stop(struct dai *dai) +static void ssp_stop(struct dai *dai, int direction) { struct ssp_pdata *ssp = dai_get_drvdata(dai); spin_lock(&ssp->lock); - /* stop Rx if we are not capturing */ - if (ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE) { + /* stop Rx if neeed */ + if (direction == DAI_DIR_CAPTURE && + ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_ACTIVE) { ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0); ssp_update_bits(dai, SSRSA, 0x1 << 8, 0x0 << 8); + ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PAUSED; trace_ssp("Ss0"); } - /* stop Tx if we are not playing */ - if (ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE) { + /* stop Tx if needed */ + if (direction == DAI_DIR_PLAYBACK && + ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_ACTIVE) { ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0); ssp_update_bits(dai, SSTSA, 0x1 << 8, 0x0 << 8); + ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PAUSED; trace_ssp("Ss1"); } @@ -647,8 +651,7 @@ static int ssp_trigger(struct dai *dai, int cmd, int direction) break; case COMP_TRIGGER_STOP: case COMP_TRIGGER_PAUSE: - ssp->state[direction] = COMP_STATE_PAUSED; - ssp_stop(dai); + ssp_stop(dai, direction); break; case COMP_TRIGGER_RESUME: ssp_context_restore(dai); -- 2.14.1

3 3

[Sound-open-firmware] [PATCH] byt-ssp: change and wrap status transition into ssp_stop
by Keyon Jie 08 May '18

08 May '18

This will remove manual status change, wrap them into ssp_stop(), where the status transition is protect by spin_lock. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- src/drivers/byt-ssp.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/drivers/byt-ssp.c b/src/drivers/byt-ssp.c index 758f211..fcde98f 100644 --- a/src/drivers/byt-ssp.c +++ b/src/drivers/byt-ssp.c @@ -504,20 +504,22 @@ static void ssp_start(struct dai *dai, int direction) } /* stop the SSP for either playback or capture */ -static void ssp_stop(struct dai *dai) +static void ssp_stop(struct dai *dai, int direction) { struct ssp_pdata *ssp = dai_get_drvdata(dai); spin_lock(&ssp->lock); - /* stop Rx if we are not capturing */ - if (ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE) { + /* stop Rx if neeed */ + if (direction == DAI_DIR_CAPTURE && + ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_ACTIVE) { ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0); trace_ssp("Ss0"); } - /* stop Tx if we are not playing */ - if (ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE) { + /* stop Tx if needed */ + if (direction == DAI_DIR_PLAYBACK && + ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_ACTIVE) { ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0); trace_ssp("Ss1"); } @@ -553,8 +555,7 @@ static int ssp_trigger(struct dai *dai, int cmd, int direction) break; case COMP_TRIGGER_STOP: case COMP_TRIGGER_PAUSE: - ssp->state[direction] = COMP_STATE_PAUSED; - ssp_stop(dai); + ssp_stop(dai, direction); break; case COMP_TRIGGER_RESUME: ssp_context_restore(dai); -- 2.14.1

2 1

[Sound-open-firmware] [PATCH] scripts: Modify Docker Ubuntu version
by Liam Girdwood 08 May '18

08 May '18

From: Prashant Malani <pmalani(a)google.com> This ensures that the ubuntu version we use has the right versions of Open SSL. Without this, the rimage compilation will fail with the following error: pkcs1_5.c: In function 'pkcs_sign': pkcs1_5.c:117:20: error: dereferencing pointer to incomplete type 'RSA {aka struct rsa_st}' Signed-off-by: Prashant Malani <pmalani(a)google.com> Acked-by: Dylan Reid <dgreid(a)chromium.org> --- scripts/docker_build/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/docker_build/Dockerfile b/scripts/docker_build/Dockerfile index 6b587e29..7ee0a451 100644 --- a/scripts/docker_build/Dockerfile +++ b/scripts/docker_build/Dockerfile @@ -14,7 +14,7 @@ # docker run -it -v <insert sof dir here>:/home/sof/work/sof.git -v <soft git dir>:/home/sof/work/soft.git --user `id -u` sof ./incremental.sh # -FROM ubuntu +FROM ubuntu:16.04 ARG UID=1000 RUN apt-get -y update && \ -- 2.14.1

1 0

[Sound-open-firmware] [PATCH_V2 3/7] cnl-interrupt: refine interrupt setting for change in irq_desc
by Rander Wang 08 May '18

08 May '18

(1)Add core id check in interrupt register setting. (2)Check child list in interrupt function (3)Extend root irq_desc to support 4 core on cnl. (4)Refine macro for interrupt setting Signed-off-by: Rander Wang <rander.wang(a)linux.intel.com> Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- V2: get core id in a generic way test on CNL & APL & BYT, pass SOF: master 85ae8e74181f kernel: v4.14 2cd03d26b66f8fee2 SOF-tools: master 56e26dd528b6c77 --- src/platform/cannonlake/dma.c | 2 +- .../cannonlake/include/platform/interrupt.h | 16 +- src/platform/cannonlake/include/platform/memory.h | 2 +- .../cannonlake/include/platform/platform.h | 10 + src/platform/cannonlake/interrupt.c | 220 +++++++++++++-------- 5 files changed, 158 insertions(+), 92 deletions(-) diff --git a/src/platform/cannonlake/dma.c b/src/platform/cannonlake/dma.c index b606d1e..3f9d6cb 100644 --- a/src/platform/cannonlake/dma.c +++ b/src/platform/cannonlake/dma.c @@ -125,7 +125,7 @@ static struct dma dma[] = { .id = DMA_GP_LP_DMAC1, .base = LP_GP_DMA_BASE(1), .channels = 8, - .irq = IRQ_EXT_LP_GPDMA0_LVL5(0, 0), + .irq = IRQ_EXT_LP_GPDMA1_LVL5(0, 0), .drv_plat_data = &dmac1, }, .ops = &dw_dma_ops, diff --git a/src/platform/cannonlake/include/platform/interrupt.h b/src/platform/cannonlake/include/platform/interrupt.h index 03857a7..b14cfdf 100644 --- a/src/platform/cannonlake/include/platform/interrupt.h +++ b/src/platform/cannonlake/include/platform/interrupt.h @@ -88,7 +88,7 @@ #define IRQ_BIT_LVL5_DMIC 6 #define IRQ_BIT_LVL5_SSP(x) (0 + x) -/* Level 2 Peripheral IRQ mappings */ +/* Priority 2 Peripheral IRQ mappings */ #define IRQ_EXT_HP_GPDMA_LVL2(xcpu) \ SOF_IRQ(IRQ_BIT_LVL2_HP_GP_DMA0(0), 2, xcpu, IRQ_NUM_EXT_LEVEL2) #define IRQ_EXT_IDC_LVL2(xcpu) \ @@ -106,7 +106,7 @@ #define IRQ_EXT_SHA256_LVL2(xcpu) \ SOF_IRQ(IRQ_BIT_LVL2_SHA256, 2, xcpu, IRQ_NUM_EXT_LEVEL2) -/* Level 3 Peripheral IRQ mappings */ +/* Priority 3 Peripheral IRQ mappings */ #define IRQ_EXT_CODE_DMA_LVL3(xcpu) \ SOF_IRQ(IRQ_BIT_LVL3_CODE_LOADER, 3, xcpu, IRQ_NUM_EXT_LEVEL3) #define IRQ_EXT_HOST_DMA_IN_LVL3(xcpu, channel) \ @@ -114,17 +114,17 @@ #define IRQ_EXT_HOST_DMA_OUT_LVL3(xcpu, channel) \ SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_OUT(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3) -/* Level 4 Peripheral IRQ mappings */ +/* Priority 4 Peripheral IRQ mappings */ #define IRQ_EXT_LINK_DMA_IN_LVL4(xcpu, channel) \ SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_IN(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4) #define IRQ_EXT_LINK_DMA_OUT_LVL4(xcpu, channel) \ SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_OUT(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4) -/* Level 5 Peripheral IRQ mappings */ +/* Priority 5 Peripheral IRQ mappings */ #define IRQ_EXT_LP_GPDMA0_LVL5(xcpu, channel) \ - SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5) -#define IRQ_EXT_LP_GPDMA1_LVL4(xcpu, channel) \ - SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA1, 4, xcpu, IRQ_NUM_EXT_LEVEL4) + SOF_ID_IRQ(0, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5) +#define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \ + SOF_ID_IRQ(1, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5) #define IRQ_EXT_SSP0_LVL5(xcpu) \ SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5) #define IRQ_EXT_SSP1_LVL5(xcpu) \ @@ -161,7 +161,7 @@ void platform_interrupt_init(void); -struct irq_parent *platform_irq_get_parent(uint32_t irq); +struct irq_desc *platform_irq_get_parent(uint32_t irq); void platform_interrupt_set(int irq); void platform_interrupt_clear(uint32_t irq, uint32_t mask); uint32_t platform_interrupt_get_enabled(void); diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h index c7f4750..67f574a 100644 --- a/src/platform/cannonlake/include/platform/memory.h +++ b/src/platform/cannonlake/include/platform/memory.h @@ -240,7 +240,7 @@ #define SOF_TEXT_SIZE 0x18000 /* initialized data */ -#define SOF_DATA_SIZE 0x18000 +#define SOF_DATA_SIZE 0x19000 /* bss data */ #define SOF_BSS_DATA_SIZE 0x8000 diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index dc9a963..d157daa 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -43,6 +43,8 @@ struct sof; #define PLATFORM_SSP_COUNT 3 #define MAX_GPDMA_COUNT 2 +#define MAX_CORE_COUNT 4 + /* Host page size */ #define HOST_PAGE_SIZE 4096 #define PLATFORM_PAGE_TABLE_SIZE 256 @@ -126,6 +128,14 @@ struct sof; extern struct timer *platform_timer; +static inline int platform_get_core_id(void) +{ + int prid; + + __asm__("rsr.prid %0" : "=a"(prid)); + return prid; +} + /* * APIs declared here are defined for every platform and IPC mechanism. */ diff --git a/src/platform/cannonlake/interrupt.c b/src/platform/cannonlake/interrupt.c index 8c47e14..250e631 100644 --- a/src/platform/cannonlake/interrupt.c +++ b/src/platform/cannonlake/interrupt.c @@ -39,19 +39,22 @@ #include <stdint.h> #include <stdlib.h> -static void parent_level2_handler(void *data) +static void irq_lvl2_level2_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL2); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL2SD(0)); - irq_write(REG_IRQ_IL2MSD(0), status); + status = irq_read(REG_IRQ_IL2SD(core)); + irq_write(REG_IRQ_IL2MSD(core), status); /* handle each child */ while (status) { @@ -61,17 +64,22 @@ static void parent_level2_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL2MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL2MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -82,19 +90,22 @@ next: arch_interrupt_enable_mask(1 << IRQ_NUM_EXT_LEVEL2); } -static void parent_level3_handler(void *data) +static void irq_lvl2_level3_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL3); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL3SD(0)); - irq_write(REG_IRQ_IL3MSD(0), status); + status = irq_read(REG_IRQ_IL3SD(core)); + irq_write(REG_IRQ_IL3MSD(core), status); /* handle each child */ while (status) { @@ -104,17 +115,22 @@ static void parent_level3_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL3MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL3MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -125,19 +141,22 @@ next: arch_interrupt_enable_mask(1 << IRQ_NUM_EXT_LEVEL3); } -static void parent_level4_handler(void *data) +static void irq_lvl2_level4_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL4); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL4SD(0)); - irq_write(REG_IRQ_IL4MSD(0), status); + status = irq_read(REG_IRQ_IL4SD(core)); + irq_write(REG_IRQ_IL4MSD(core), status); /* handle each child */ while (status) { @@ -147,17 +166,22 @@ static void parent_level4_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL4MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL4MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -168,19 +192,22 @@ next: arch_interrupt_enable_mask(1 << IRQ_NUM_EXT_LEVEL4); } -static void parent_level5_handler(void *data) +static void irq_lvl2_level5_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL5); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL5SD(0)); - irq_write(REG_IRQ_IL5MSD(0), status); + status = irq_read(REG_IRQ_IL5SD(core)); + irq_write(REG_IRQ_IL5MSD(core), status); /* handle each child */ while (status) { @@ -190,17 +217,22 @@ static void parent_level5_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL5MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL5MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -212,24 +244,41 @@ next: } /* DSP internal interrupts */ -static struct irq_parent dsp_irq[4] = { - {IRQ_NUM_EXT_LEVEL2, parent_level2_handler, }, - {IRQ_NUM_EXT_LEVEL3, parent_level3_handler, }, - {IRQ_NUM_EXT_LEVEL4, parent_level4_handler, }, - {IRQ_NUM_EXT_LEVEL5, parent_level5_handler, }, +static struct irq_desc dsp_irq[MAX_CORE_COUNT][4] = { + {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, }, + {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, }, + {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, }, + {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } }, + + {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, }, + {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, }, + {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, }, + {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } }, + + {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, }, + {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, }, + {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, }, + {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } }, + + {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, }, + {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, }, + {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, }, + {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } }, }; -struct irq_parent *platform_irq_get_parent(uint32_t irq) +struct irq_desc *platform_irq_get_parent(uint32_t irq) { + int core = platform_get_core_id(); + switch (SOF_IRQ_NUMBER(irq)) { case IRQ_NUM_EXT_LEVEL2: - return &dsp_irq[0]; + return &dsp_irq[core][0]; case IRQ_NUM_EXT_LEVEL3: - return &dsp_irq[1]; + return &dsp_irq[core][1]; case IRQ_NUM_EXT_LEVEL4: - return &dsp_irq[2]; + return &dsp_irq[core][2]; case IRQ_NUM_EXT_LEVEL5: - return &dsp_irq[3]; + return &dsp_irq[core][3]; default: return NULL; } @@ -242,19 +291,21 @@ uint32_t platform_interrupt_get_enabled(void) void platform_interrupt_mask(uint32_t irq, uint32_t mask) { + int core = platform_get_core_id(); + /* mask external interrupt bit */ switch (SOF_IRQ_NUMBER(irq)) { case IRQ_NUM_EXT_LEVEL5: - irq_write(REG_IRQ_IL5MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL5MSD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL4: - irq_write(REG_IRQ_IL4MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL4MSD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL3: - irq_write(REG_IRQ_IL3MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL3MSD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL2: - irq_write(REG_IRQ_IL2MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL2MSD(core), 1 << SOF_IRQ_BIT(irq)); break; default: break; @@ -264,19 +315,21 @@ void platform_interrupt_mask(uint32_t irq, uint32_t mask) void platform_interrupt_unmask(uint32_t irq, uint32_t mask) { + int core = platform_get_core_id(); + /* unmask external interrupt bit */ switch (SOF_IRQ_NUMBER(irq)) { case IRQ_NUM_EXT_LEVEL5: - irq_write(REG_IRQ_IL5MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL5MCD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL4: - irq_write(REG_IRQ_IL4MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL4MCD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL3: - irq_write(REG_IRQ_IL3MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL3MCD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL2: - irq_write(REG_IRQ_IL2MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL2MCD(core), 1 << SOF_IRQ_BIT(irq)); break; default: break; @@ -290,15 +343,18 @@ void platform_interrupt_clear(uint32_t irq, uint32_t mask) void platform_interrupt_init(void) { - int i; + int i, j; + int core = platform_get_core_id(); /* mask all external IRQs by default */ - irq_write(REG_IRQ_IL2MSD(0), REG_IRQ_IL2MD_ALL); - irq_write(REG_IRQ_IL3MSD(0), REG_IRQ_IL3MD_ALL); - irq_write(REG_IRQ_IL4MSD(0), REG_IRQ_IL4MD_ALL); - irq_write(REG_IRQ_IL5MSD(0), REG_IRQ_IL5MD_ALL); - - for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) { - spinlock_init(&dsp_irq[i].lock); + irq_write(REG_IRQ_IL2MSD(core), REG_IRQ_IL2MD_ALL); + irq_write(REG_IRQ_IL3MSD(core), REG_IRQ_IL3MD_ALL); + irq_write(REG_IRQ_IL4MSD(core), REG_IRQ_IL4MD_ALL); + irq_write(REG_IRQ_IL5MSD(core), REG_IRQ_IL5MD_ALL); + + for (i = 0; i < ARRAY_SIZE(dsp_irq[core]); i++) { + spinlock_init(&dsp_irq[core][i].lock); + for (j = 0; j < PLATFORM_IRQ_CHILDREN; j++) + list_init(&dsp_irq[core][i].child[j]); } } -- 2.14.1

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[Sound-open-firmware] [PATCH_V2 5/7] apl-interrupt: refine interrupt code according to interrupt change
by Rander Wang 08 May '18

08 May '18

Port the change on cnl to apl Signed-off-by: Rander Wang <rander.wang(a)linux.intel.com> --- V2: get core id in a generic way test on CNL & APL & BYT, pass SOF: master 85ae8e74181f kernel: v4.14 2cd03d26b66f8fee2 SOF-tools: master 56e26dd528b6c77 --- .../apollolake/include/platform/interrupt.h | 2 +- src/platform/apollolake/include/platform/memory.h | 4 +- .../apollolake/include/platform/platform.h | 10 + src/platform/apollolake/interrupt.c | 210 +++++++++++++-------- 4 files changed, 141 insertions(+), 85 deletions(-) diff --git a/src/platform/apollolake/include/platform/interrupt.h b/src/platform/apollolake/include/platform/interrupt.h index 8e29deb..6778661 100644 --- a/src/platform/apollolake/include/platform/interrupt.h +++ b/src/platform/apollolake/include/platform/interrupt.h @@ -164,7 +164,7 @@ void platform_interrupt_init(void); -struct irq_parent *platform_irq_get_parent(uint32_t irq); +struct irq_desc *platform_irq_get_parent(uint32_t irq); void platform_interrupt_set(int irq); void platform_interrupt_clear(uint32_t irq, uint32_t mask); uint32_t platform_interrupt_get_enabled(void); diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h index c71d8c6..6b3f21f 100644 --- a/src/platform/apollolake/include/platform/memory.h +++ b/src/platform/apollolake/include/platform/memory.h @@ -171,7 +171,7 @@ #define SOF_TEXT_SIZE 0x19000 /* initialized data */ -#define SOF_DATA_SIZE 0x18000 +#define SOF_DATA_SIZE 0x19000 /* bss data */ #define SOF_BSS_DATA_SIZE 0x2800 @@ -180,7 +180,7 @@ #define HEAP_SYSTEM_BASE \ (SOF_TEXT_BASE + SOF_TEXT_SIZE +\ SOF_DATA_SIZE + SOF_BSS_DATA_SIZE) -#define HEAP_SYSTEM_SIZE 0x3200 +#define HEAP_SYSTEM_SIZE 0x5000 #define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) #define HEAP_RUNTIME_SIZE \ diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index d57b880..409422c 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -39,6 +39,8 @@ struct sof; +#define MAX_CORE_COUNT 2 + /* Host page size */ #define HOST_PAGE_SIZE 4096 #define PLATFORM_PAGE_TABLE_SIZE 256 @@ -130,6 +132,14 @@ struct sof; extern struct timer *platform_timer; +static inline int platform_get_core_id(void) +{ + int prid; + + __asm__("rsr.prid %0" : "=a"(prid)); + return prid; +} + /* * APIs declared here are defined for every platform and IPC mechanism. */ diff --git a/src/platform/apollolake/interrupt.c b/src/platform/apollolake/interrupt.c index d4af079..9ec36e7 100644 --- a/src/platform/apollolake/interrupt.c +++ b/src/platform/apollolake/interrupt.c @@ -39,19 +39,22 @@ #include <stdint.h> #include <stdlib.h> -static void parent_level2_handler(void *data) +static void irq_lvl2_level2_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL2); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL2SD(0)); - irq_write(REG_IRQ_IL2MSD(0), status); + status = irq_read(REG_IRQ_IL2SD(core)); + irq_write(REG_IRQ_IL2MSD(core), status); /* handle each child */ while (status) { @@ -61,17 +64,22 @@ static void parent_level2_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL2MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL2MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -82,19 +90,22 @@ next: arch_interrupt_enable_mask(1 << IRQ_NUM_EXT_LEVEL2); } -static void parent_level3_handler(void *data) +static void irq_lvl2_level3_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL3); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL3SD(0)); - irq_write(REG_IRQ_IL3MSD(0), status); + status = irq_read(REG_IRQ_IL3SD(core)); + irq_write(REG_IRQ_IL3MSD(core), status); /* handle each child */ while (status) { @@ -104,17 +115,22 @@ static void parent_level3_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL3MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL3MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -125,19 +141,22 @@ next: arch_interrupt_enable_mask(1 << IRQ_NUM_EXT_LEVEL3); } -static void parent_level4_handler(void *data) +static void irq_lvl2_level4_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL4); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL4SD(0)); - irq_write(REG_IRQ_IL4MSD(0), status); + status = irq_read(REG_IRQ_IL4SD(core)); + irq_write(REG_IRQ_IL4MSD(core), status); /* handle each child */ while (status) { @@ -147,17 +166,22 @@ static void parent_level4_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL4MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL4MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -168,19 +192,22 @@ next: arch_interrupt_enable_mask(1 << IRQ_NUM_EXT_LEVEL4); } -static void parent_level5_handler(void *data) +static void irq_lvl2_level5_handler(void *data) { - struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_desc *parent = (struct irq_desc *)data; + struct irq_desc *child = NULL; + struct list_item *clist; uint32_t status; uint32_t i = 0; + uint32_t unmask = 0; + int core = platform_get_core_id(); /* mask the parent IRQ */ arch_interrupt_disable_mask(1 << IRQ_NUM_EXT_LEVEL5); /* mask all child interrupts */ - status = irq_read(REG_IRQ_IL5SD(0)); - irq_write(REG_IRQ_IL5MSD(0), status); + status = irq_read(REG_IRQ_IL5SD(core)); + irq_write(REG_IRQ_IL5MSD(core), status); /* handle each child */ while (status) { @@ -190,17 +217,22 @@ static void parent_level5_handler(void *data) goto next; /* get child if any and run handler */ - child = parent->child[i]; - if (child && child->handler) { - child->handler(child->handler_arg); - - /* unmask this bit i interrupt */ - irq_write(REG_IRQ_IL5MCD(0), 0x1 << i); - } else { - /* nobody cared ? */ - trace_irq_error("nbc"); + list_for_item(clist, &parent->child[i]) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child && child->handler) { + child->handler(child->handler_arg); + unmask = 1; + } else { + /* nobody cared ? */ + trace_irq_error("nbc"); + } } + /* unmask this bit i interrupt */ + if (unmask) + irq_write(REG_IRQ_IL5MCD(core), 0x1 << i); + next: status >>= 1; i++; @@ -212,24 +244,31 @@ next: } /* DSP internal interrupts */ -static struct irq_parent dsp_irq[4] = { - {IRQ_NUM_EXT_LEVEL2, parent_level2_handler, }, - {IRQ_NUM_EXT_LEVEL3, parent_level3_handler, }, - {IRQ_NUM_EXT_LEVEL4, parent_level4_handler, }, - {IRQ_NUM_EXT_LEVEL5, parent_level5_handler, }, +static struct irq_desc dsp_irq[MAX_CORE_COUNT][4] = { + {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, }, + {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, }, + {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, }, + {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } }, + + {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, }, + {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, }, + {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, }, + {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } }, }; -struct irq_parent *platform_irq_get_parent(uint32_t irq) +struct irq_desc *platform_irq_get_parent(uint32_t irq) { + int core = platform_get_core_id(); + switch (SOF_IRQ_NUMBER(irq)) { case IRQ_NUM_EXT_LEVEL2: - return &dsp_irq[0]; + return &dsp_irq[core][0]; case IRQ_NUM_EXT_LEVEL3: - return &dsp_irq[1]; + return &dsp_irq[core][1]; case IRQ_NUM_EXT_LEVEL4: - return &dsp_irq[2]; + return &dsp_irq[core][2]; case IRQ_NUM_EXT_LEVEL5: - return &dsp_irq[3]; + return &dsp_irq[core][3]; default: return NULL; } @@ -242,19 +281,21 @@ uint32_t platform_interrupt_get_enabled(void) void platform_interrupt_mask(uint32_t irq, uint32_t mask) { + int core = platform_get_core_id(); + /* mask external interrupt bit */ switch (SOF_IRQ_NUMBER(irq)) { case IRQ_NUM_EXT_LEVEL5: - irq_write(REG_IRQ_IL5MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL5MSD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL4: - irq_write(REG_IRQ_IL4MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL4MSD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL3: - irq_write(REG_IRQ_IL3MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL3MSD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL2: - irq_write(REG_IRQ_IL2MSD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL2MSD(core), 1 << SOF_IRQ_BIT(irq)); break; default: break; @@ -264,19 +305,21 @@ void platform_interrupt_mask(uint32_t irq, uint32_t mask) void platform_interrupt_unmask(uint32_t irq, uint32_t mask) { + int core = platform_get_core_id(); + /* unmask external interrupt bit */ switch (SOF_IRQ_NUMBER(irq)) { case IRQ_NUM_EXT_LEVEL5: - irq_write(REG_IRQ_IL5MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL5MCD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL4: - irq_write(REG_IRQ_IL4MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL4MCD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL3: - irq_write(REG_IRQ_IL3MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL3MCD(core), 1 << SOF_IRQ_BIT(irq)); break; case IRQ_NUM_EXT_LEVEL2: - irq_write(REG_IRQ_IL2MCD(0), 1 << SOF_IRQ_BIT(irq)); + irq_write(REG_IRQ_IL2MCD(core), 1 << SOF_IRQ_BIT(irq)); break; default: break; @@ -290,15 +333,18 @@ void platform_interrupt_clear(uint32_t irq, uint32_t mask) void platform_interrupt_init(void) { - int i; + int i, j; + int core = platform_get_core_id(); /* mask all external IRQs by default */ - irq_write(REG_IRQ_IL2MSD(0), REG_IRQ_IL2MD_ALL); - irq_write(REG_IRQ_IL3MSD(0), REG_IRQ_IL3MD_ALL); - irq_write(REG_IRQ_IL4MSD(0), REG_IRQ_IL4MD_ALL); - irq_write(REG_IRQ_IL5MSD(0), REG_IRQ_IL5MD_ALL); - - for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) { - spinlock_init(&dsp_irq[i].lock); + irq_write(REG_IRQ_IL2MSD(core), REG_IRQ_IL2MD_ALL); + irq_write(REG_IRQ_IL3MSD(core), REG_IRQ_IL3MD_ALL); + irq_write(REG_IRQ_IL4MSD(core), REG_IRQ_IL4MD_ALL); + irq_write(REG_IRQ_IL5MSD(core), REG_IRQ_IL5MD_ALL); + + for (i = 0; i < ARRAY_SIZE(dsp_irq[core]); i++) { + spinlock_init(&dsp_irq[core][i].lock); + for (j = 0; j < PLATFORM_IRQ_CHILDREN; j++) + list_init(&dsp_irq[core][i].child[j]); } } -- 2.14.1

1 0

Re: [Sound-open-firmware] [PATCH 3/3] scripts: Add ability to build in a container
by Dylan Reid 08 May '18

08 May '18

On Wed, May 2, 2018 at 9:16 PM Pan, Xiuli <xiuli.pan(a)linux.intel.com> wrote: > On 5/3/2018 02:38, Dylan Reid wrote: > > On Tue, May 1, 2018 at 11:08 PM Pan, Xiuli <xiuli.pan(a)linux.intel.com> > > wrote: > > > >> Hi Dylan, > >> I have tried you scripts behind proxy and solve one of the apt proxy > >> problem. > >> But I still got hold by the add-apt-repository. > >> I see the Dockerfile also contains some git protocol url, and I assume > >> that this could not be supported by the proxy. > > If it's the git:// URLs that are a problem, they can probably be switched > > to https. > I got some proxy setting patch to solve apt related problem. > I will change the url to http and send few patches to fix this problem. > Could you have a try to make sure it will not break the no proxy build? I applied the patch you sent earlier this week. Everything still works with a "no proxy" build. Thanks!

2 3

[Sound-open-firmware] [PATCH 0/3] Host based component testing
by Ranjani Sridharan 07 May '18

07 May '18

This set of patches introduces the testbench for audio processing components in SOF. The testbench enables for functional/quality test of the components. The testbench reads in audio samples from a file and write out the processed samples to the output file. The common directory includes routines for topology parsing and setting up sof ipc, scheduler and processing pipelines. It also includes simpler implementations for SOF features such as tracing. It also includes the fileread/filewrite components that allow reading in or writing out samples from/to a file. The volume testbench directory includes the testbench for volume component. The volume testbench reads in input samples from a file ,schedules pipeline copy and copies the processed sample to the output file. The output file can be used to perform audio quality tests using matlab/octave. Testbench for other components such as src/eq will be added later. Ranjani Sridharan (3): [RFC]tune: add common testbench common headers and source files [RFC]tune: add fileread and filewrite components [RFC]tune: add volume testbench Makefile.am | 2 +- configure.ac | 5 +- tune/Makefile.am | 1 + tune/common/Makefile.am | 11 + tune/common/common_test.c | 461 ++++++++++++++++++++++++ tune/common/common_test.h | 125 +++++++ tune/common/common_tplg.c | 873 ++++++++++++++++++++++++++++++++++++++++++++++ tune/common/common_tplg.h | 195 +++++++++++ tune/common/fileread.c | 385 ++++++++++++++++++++ tune/common/filewrite.c | 395 +++++++++++++++++++++ tune/volume/Makefile.am | 17 + tune/volume/volume_test.c | 160 +++++++++ 12 files changed, 2628 insertions(+), 2 deletions(-) create mode 100644 tune/Makefile.am create mode 100644 tune/common/Makefile.am create mode 100644 tune/common/common_test.c create mode 100644 tune/common/common_test.h create mode 100644 tune/common/common_tplg.c create mode 100644 tune/common/common_tplg.h create mode 100644 tune/common/fileread.c create mode 100644 tune/common/filewrite.c create mode 100644 tune/volume/Makefile.am create mode 100644 tune/volume/volume_test.c -- 2.14.1

3 13

[Sound-open-firmware] [PATCH] topology: utility for visualizing topology
by Ranjani Sridharan 07 May '18

07 May '18

Add a simple utility that parses topology bin files and creates a graph using the linux dot tool. Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- topology/Makefile.am | 5 ++ topology/parse_topology.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+) create mode 100644 topology/parse_topology.c diff --git a/topology/Makefile.am b/topology/Makefile.am index 73e10e9..b69dfb4 100644 --- a/topology/Makefile.am +++ b/topology/Makefile.am @@ -59,3 +59,8 @@ EXTRA_DIST = \ sof-cnl-rt274.m4 \ sof-hsw-rt5640.m4 \ sof-apl-tdf8532.m4 + +bin_PROGRAMS = tplg_graph + +tplg_graph_SOURCES = \ + parse_topology.c diff --git a/topology/parse_topology.c b/topology/parse_topology.c new file mode 100644 index 0000000..b54ca77 --- /dev/null +++ b/topology/parse_topology.c @@ -0,0 +1,130 @@ +/* + * Utility for visualizing topology files. + * + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <stdio.h> +#include <sound/asoc.h> +#include <string.h> +#include <stdlib.h> + +/* + * The output graph is saved as "tplg.png" + * Usage: ./tplg_graph <tplg file> + */ + +int main(int argc, char **argv) +{ + struct snd_soc_tplg_hdr *hdr; + struct snd_soc_tplg_dapm_graph_elem *graph_elem; + char *filename; + char *dotfilename = "tplg.dot"; + FILE *file, *dotfile; + char *start = "digraph topology {\n"; + char *node_color = "node [color=Red,fontname=Courier]\n"; + char *edge_color = "edge [color=Blue, style=dashed]\n"; + char *end = "}\n"; + char edge[256]; + int i, status, ret; + size_t size, file_size; + + /* command line arguments */ + if (argc < 2) { + printf("usage: tplg_graph <tplg file>\n"); + exit(EXIT_FAILURE); + } + + filename = malloc(strlen(argv[1])); + strcpy(filename, argv[1]); + + /* open files */ + file = fopen(filename, "rb"); + if (!file) { + fprintf(stderr, "Unable to open file %s", filename); + return -1; + } + + dotfile = fopen(dotfilename, "w"); + if (!dotfile) { + fprintf(stderr, "Unable to open file %s", dotfilename); + return -1; + } + + fwrite(start, strlen(start), 1, dotfile); + fwrite(node_color, strlen(node_color), 1, dotfile); + fwrite(edge_color, strlen(edge_color), 1, dotfile); + + + /* file size */ + fseek(file, 0, SEEK_END); + file_size = ftell(file); + fseek(file, 0, SEEK_SET); + + /* Allocate memory */ + size = sizeof(struct snd_soc_tplg_hdr); + hdr = (struct snd_soc_tplg_hdr *)malloc(size); + if (!hdr) { + printf("error: mem alloc\n"); + return -1; + } + + size = sizeof(struct snd_soc_tplg_dapm_graph_elem); + graph_elem = (struct snd_soc_tplg_dapm_graph_elem *)malloc(size); + if (!graph_elem) { + printf("error: mem alloc\n"); + return -1; + } + + while (1) { + ret = fread(hdr, sizeof(struct snd_soc_tplg_hdr), 1, file); + if (ret != 1) + printf("error: reading header\n"); + + switch (hdr->type) { + case SND_SOC_TPLG_TYPE_DAPM_GRAPH: + size = sizeof(struct snd_soc_tplg_dapm_graph_elem); + /* parse pipeline graph */ + for (i = 0; i < hdr->count; i++) { + ret = fread(graph_elem, size, 1, file); + if (ret != 1) + printf("error: reading graph elem\n"); + + /* write route to output dot file */ + sprintf(edge, "\"%s\"->\"%s\"\n", + graph_elem->source, graph_elem->sink); + fwrite(edge, strlen(edge), 1, dotfile); + fwrite("\n", 1, 1, dotfile); + } + + if (ftell(file) == file_size) + goto finish; + break; + + default: + fseek(file, hdr->payload_size, SEEK_CUR); + if (ftell(file) == file_size) + goto finish; + break; + } + } + +finish: + fwrite(end, strlen(end), 1, dotfile); + fclose(dotfile); + fclose(file); + free(hdr); + free(graph_elem); + + /* create topology graph */ + status = system("dot tplg.dot -Tpng -o tplg.png"); +} -- 2.14.1

3 6

[Sound-open-firmware] [PATCH 0/7] interrupt refinement
by Rander Wang 07 May '18

07 May '18

The issues for original data structure and algorithm are: (1)it only supports 2 level interrupt architecture. (2)it doesn't support different HW interrupt shares one IRQ value. (3)it doesn't support multi-core. The refinement is based on the prototype provided by Liam. refine irq data structure to make it support more than 2 level and issue(2). Add multi-core support in interrupt setting test on CNL & APL & BYT, pass SOF: master 85ae8e74181f kernel: v4.14 2cd03d26b66f8fee2 SOF-tools: master 56e26dd528b6c77 Rander Wang (7): interrupt: refine irq structure and algorithm interrupt: add irq id in IRQ cnl-interrupt: refine interrupt setting for change in irq_desc cnl-dma: remove special dma code for cnl apl-interrupt: refine interrupt code according to interrupt change byt-interrupt: port irq change to byt hsw-interrupt: port irq change to hsw src/drivers/dw-dma.c | 32 +-- src/include/sof/interrupt-map.h | 17 ++ src/include/sof/interrupt.h | 32 +-- src/lib/interrupt.c | 120 +++++------ .../apollolake/include/platform/interrupt.h | 2 +- src/platform/apollolake/include/platform/memory.h | 4 +- .../apollolake/include/platform/platform.h | 2 + src/platform/apollolake/interrupt.c | 210 ++++++++++++-------- src/platform/baytrail/include/platform/interrupt.h | 2 +- src/platform/cannonlake/dma.c | 2 +- .../cannonlake/include/platform/interrupt.h | 16 +- src/platform/cannonlake/include/platform/memory.h | 2 +- .../cannonlake/include/platform/platform.h | 2 + src/platform/cannonlake/interrupt.c | 220 +++++++++++++-------- src/platform/haswell/include/platform/interrupt.h | 2 +- 15 files changed, 382 insertions(+), 283 deletions(-) -- 2.14.1

3 9

[Sound-open-firmware] [PATCH v3] topology: speed up topology build
by Ranjani Sridharan 07 May '18

07 May '18

Speed up topology with batch processing of m4 files Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- Notes: v3: check for xargs in configure and use max processes possible configure.ac | 2 ++ topology/test/Makefile.am | 4 ++- topology/test/tplg-build.sh | 65 ++++++++++++++++++++++++++++++++------------- 3 files changed, 51 insertions(+), 20 deletions(-) diff --git a/configure.ac b/configure.ac index b95c44c..cc5e59e 100644 --- a/configure.ac +++ b/configure.ac @@ -5,6 +5,8 @@ AM_INIT_AUTOMAKE([foreign]) AC_CONFIG_SRCDIR([rmbox/rmbox.c]) AC_CONFIG_HEADERS([config.h]) AC_CHECK_HEADER([sof/uapi/abi.h]) +AC_CHECK_PROG([XARGS], xargs, "yes", "no", [$PATH]) +AM_CONDITIONAL(XARGS, test "$XARGS" = "yes") AC_CANONICAL_HOST diff --git a/topology/test/Makefile.am b/topology/test/Makefile.am index 61713f9..d494fcb 100644 --- a/topology/test/Makefile.am +++ b/topology/test/Makefile.am @@ -3,7 +3,9 @@ # Dependencies # - +if XARGS +export USE_XARGS=yes +endif DEPS = \ ../dsps/*.m4 \ diff --git a/topology/test/tplg-build.sh b/topology/test/tplg-build.sh index 7c55fba..e32df81 100755 --- a/topology/test/tplg-build.sh +++ b/topology/test/tplg-build.sh @@ -8,14 +8,14 @@ set -e # M4 preprocessor flags -M4_FLAGS="-I ../ -I ../m4 -I ../common" +export M4PATH="../:../m4:../common" # Simple component test cases # can be used on components with 1 sink and 1 source. SIMPLE_TESTS=(test-ssp test-capture-ssp test-playback-ssp) TONE_TEST=test-tone-playback-ssp - - +TEST_STRINGS="" +M4_STRINGS="" # process m4 simple tests - # simple_test(name, pipe_name, be_name, format, dai_id, dai_format, dai_phy_bits, dai_data_bits dai_bclk) # 1) name - test filename suffix @@ -35,21 +35,35 @@ function simple_test { for i in ${SIMPLE_TESTS[@]} do TFILE="$i$5-${11}-$2-$4-$6-48k-$((${10} / 1000))k-$1" - echo "M4 pre-processing test $i -> ${TFILE}" - m4 ${M4_FLAGS} \ - -DTEST_PIPE_NAME="$2" \ - -DTEST_DAI_LINK_NAME="$3" \ - -DTEST_SSP_PORT=$5 \ - -DTEST_SSP_FORMAT=$6 \ - -DTEST_PIPE_FORMAT=$4 \ - -DTEST_SSP_BCLK=$9 \ - -DTEST_SSP_MCLK=${10} \ - -DTEST_SSP_PHY_BITS=$7 \ - -DTEST_SSP_DATA_BITS=$8 \ - -DTEST_SSP_MODE=${11} \ - $i.m4 > ${TFILE}.conf - echo "Compiling test $i -> ${TFILE}.tplg" - alsatplg -v 1 -c ${TFILE}.conf -o ${TFILE}.tplg + if [ "$USE_XARGS" == "yes" ] + then + #create input string for batch m4 processing + M4_STRINGS+="-DTEST_PIPE_NAME=$2,-DTEST_DAI_LINK_NAME=$3\ + -DTEST_SSP_PORT=$5,-DTEST_SSP_FORMAT=$6\ + -DTEST_PIPE_FORMAT=$4,-DTEST_SSP_BCLK=$9\ + -DTEST_SSP_MCLK=${10},-DTEST_SSP_PHY_BITS=$7\ + -DTEST_SSP_DATA_BITS=$8,-DTEST_SSP_MODE=${11}\ + $i.m4,${TFILE}," + #create input string for batch processing of conf files + TEST_STRINGS+=${TFILE}"," + else + echo "M4 pre-processing test $i -> ${TFILE}" + m4 ${M4_FLAGS} \ + -DTEST_PIPE_NAME="$2" \ + -DTEST_DAI_LINK_NAME="$3" \ + -DTEST_SSP_PORT=$5 \ + -DTEST_SSP_FORMAT=$6 \ + -DTEST_PIPE_FORMAT=$4 \ + -DTEST_SSP_BCLK=$9 \ + -DTEST_SSP_MCLK=${10} \ + -DTEST_SSP_PHY_BITS=$7 \ + -DTEST_SSP_DATA_BITS=$8 \ + -DTEST_SSP_MODE=${11} \ + $i.m4 > ${TFILE}.conf + echo "Compiling test $i -> ${TFILE}.tplg" + alsatplg -v 1 -c ${TFILE}.conf -o ${TFILE}.tplg + fi + done } @@ -69,7 +83,7 @@ function simple_test { function tone_test { TFILE="$TONE_TEST$5-$2-$4-$6-48k-$1" echo "M4 pre-processing test $TONE_TEST -> ${TFILE}" - m4 ${M4_FLAGS} \ + m4 \ -DTEST_PIPE_NAME="$2" \ -DTEST_DAI_LINK_NAME="$3" \ -DTEST_SSP_PORT=$5 \ @@ -84,6 +98,8 @@ function tone_test { alsatplg -v 1 -c ${TFILE}.conf -o ${TFILE}.tplg } +echo "Preparing topology build input..." + # Pre-process the simple tests simple_test nocodec passthrough "NoCodec" s16le 2 s16le 20 16 1920000 19200000 I2S simple_test nocodec passthrough "NoCodec" s24le 2 s24le 25 24 2400000 19200000 I2S @@ -166,4 +182,15 @@ simple_test nocodec src "NoCodec" s24le 4 s24le 25 24 2400000 24000000 I2S # Tone test: Tone component only supports s32le currently tone_test codec tone "SSP2-Codec" s32le 2 s16le 20 16 1920000 19200000 +if [ "$USE_XARGS" == "yes" ] +then + echo "Batch processing m4 files..." + M4_STRINGS=${M4_STRINGS%?}; + #m4 processing + echo $M4_STRINGS | tr " " "," | tr '\n' '\0' | xargs -P0 -d ',' -n12 bash -c 'm4 "${@:1:${#}-1}" > ${12}.conf' m4 + + #execute alsatplg to create topology binary + TEST_STRINGS=${TEST_STRINGS%?} + echo $TEST_STRINGS | tr '\n' '\0' | xargs -d ',' -P0 -n1 -I string alsatplg -v 1 -c string".conf" -o string".tplg" +fi -- 2.14.1

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