February 2018 - Sound-open-firmware - mailman.alsa-project.org

[Sound-open-firmware] [PATCH] ssp: add ssp support for APL and CNL
by Rander Wang 08 Feb '18

08 Feb '18

Now it supports I2S & TDM4 master mode and no MN devide used. For 19.2M clock, 16bit 48K stream maybe need to pack to 20bit 48K. Signed-off-by: Rander Wang <rander.wang(a)intel.com> --- configure.ac | 1 + src/drivers/Makefile.am | 9 +- src/drivers/apl-ssp.c | 547 ++++++++++++++++++++++++++++++++++++++++++++++++ src/include/reef/ssp.h | 66 +++++- 4 files changed, 612 insertions(+), 11 deletions(-) create mode 100644 src/drivers/apl-ssp.c diff --git a/configure.ac b/configure.ac index 05a3bee..1c84020 100644 --- a/configure.ac +++ b/configure.ac @@ -212,6 +212,7 @@ AM_CONDITIONAL(BUILD_APOLLOLAKE, test "$FW_NAME" = "apl") AM_CONDITIONAL(BUILD_CANNONLAKE, test "$FW_NAME" = "cnl") AM_CONDITIONAL(BUILD_BOOTLOADER, test "$FW_NAME" = "cnl") AM_CONDITIONAL(BUILD_MODULE, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl") +AM_CONDITIONAL(BUILD_APL_SSP, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl") # DSP core support (Optional) AC_ARG_WITH([dsp-core], diff --git a/src/drivers/Makefile.am b/src/drivers/Makefile.am index 8c507fa..53b52af 100644 --- a/src/drivers/Makefile.am +++ b/src/drivers/Makefile.am @@ -1,9 +1,16 @@ noinst_LIBRARIES = libdrivers.a libdrivers_a_SOURCES = \ - ssp.c \ dw-dma.c +if BUILD_APL_SSP +libdrivers_a_SOURCES += \ + apl-ssp.c +else + libdrivers_a_SOURCES += \ + ssp.c +endif + libdrivers_a_CFLAGS = \ $(ARCH_CFLAGS) \ $(REEF_INCDIR) \ diff --git a/src/drivers/apl-ssp.c b/src/drivers/apl-ssp.c new file mode 100644 index 0000000..09adee2 --- /dev/null +++ b/src/drivers/apl-ssp.c @@ -0,0 +1,547 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + * Rander Wang <rander.wang(a)linux.intel.com> + */ + +#include <errno.h> +#include <stdbool.h> +#include <reef/stream.h> +#include <reef/ssp.h> +#include <reef/alloc.h> +#include <reef/interrupt.h> + +/* tracing */ +#define trace_ssp(__e) trace_event(TRACE_CLASS_SSP, __e) +#define trace_ssp_error(__e) trace_error(TRACE_CLASS_SSP, __e) +#define tracev_ssp(__e) tracev_event(TRACE_CLASS_SSP, __e) + +/* save SSP context prior to entering D3 */ +static int ssp_context_store(struct dai *dai) +{ + struct ssp_pdata *ssp = dai_get_drvdata(dai); + + ssp->sscr0 = ssp_read(dai, SSCR0); + ssp->sscr1 = ssp_read(dai, SSCR1); + + /* FIXME: need to store sscr2,3,4,5 */ + ssp->psp = ssp_read(dai, SSPSP); + + return 0; +} + +/* restore SSP context after leaving D3 */ +static int ssp_context_restore(struct dai *dai) +{ + struct ssp_pdata *ssp = dai_get_drvdata(dai); + + ssp_write(dai, SSCR0, ssp->sscr0); + ssp_write(dai, SSCR1, ssp->sscr1); + /* FIXME: need to restore sscr2,3,4,5 */ + ssp_write(dai, SSPSP, ssp->psp); + + return 0; +} + +/* Digital Audio interface formatting */ +static inline int ssp_set_config(struct dai *dai, + struct sof_ipc_dai_config *config) +{ + struct ssp_pdata *ssp = dai_get_drvdata(dai); + uint32_t sscr0; + uint32_t sscr1; + uint32_t sscr2; + uint32_t sscr3; + uint32_t sspsp; + uint32_t sspsp2; + uint32_t sstsa; + uint32_t ssrsa; + uint32_t ssto; + uint32_t ssioc; + uint32_t mdiv; + uint32_t bdiv; + uint32_t mdivc; + uint32_t mdivr; + uint32_t i2s_m; + uint32_t i2s_n; + uint32_t data_size; + uint32_t start_delay; + uint32_t frame_len = 0; + bool inverted_frame = false; + int ret = 0; + + spin_lock(&ssp->lock); + + /* is playback/capture already running */ + if (ssp->state[DAI_DIR_PLAYBACK] == COMP_STATE_ACTIVE || + ssp->state[DAI_DIR_CAPTURE] == COMP_STATE_ACTIVE) { + trace_ssp_error("ec1"); + ret = -EINVAL; + goto out; + } + + trace_ssp("cos"); + + /* reset SSP settings */ + /* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */ + /* + * FIXME: MOD, ACS, NCS are not set, + * no support for network mode for now + */ + sscr0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM; + + /* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR */ + sscr1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_RWOT | SSCR1_TRAIL; +// sscr1 |= SSCR1_TIE | SSCR1_RIE; + + /* sscr2 dynamic setting is LJDFD */ + sscr2 = SSCR2_SDFD | SSCR2_TURM1; + + /* sscr3 dynamic settings are TFT, RFT */ + sscr3 = 0; + + /* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */ +// sspsp = SSPSP_ETDS; /* make sure SDO line is tri-stated when inactive */ + sspsp = 0; + + ssp->config = *config; + ssp->params = config->ssp[0]; + + /* sspsp2 no dynamic setting */ + sspsp2 = 0x0; + + /* ssioc dynamic setting is SFCR */ + ssioc = SSIOC_SCOE; + + /* i2s_m M divider setting, default 1 */ + i2s_m = 0x1; + + /* i2s_n N divider setting, default 1 */ + i2s_n = 0x1; + + /* ssto no dynamic setting */ + ssto = 0x0; + + /* sstsa dynamic setting is TTSA, default 2 slots */ + sstsa = config->tx_slot_mask; + + /* ssrsa dynamic setting is RTSA, default 2 slots */ + ssrsa = config->rx_slot_mask; + + /* clock masters */ + sscr1 &= ~SSCR1_SFRMDIR; + + trace_value(config->format); + switch (config->format & SOF_DAI_FMT_MASTER_MASK) { + case SOF_DAI_FMT_CBM_CFM: + sscr0 |= SSCR0_ECS; /* external clock used */ + sscr1 |= SSCR1_SCLKDIR; + /* + * FIXME: does SSRC1.SCFR need to be set + * when codec is master ? + */ + break; + case SOF_DAI_FMT_CBS_CFS: + sscr1 |= SSCR1_SCFR; + ssioc |= SSIOC_SFCR; + break; + case SOF_DAI_FMT_CBM_CFS: + sscr0 |= SSCR0_ECS; /* external clock used */ + sscr1 |= SSCR1_SCLKDIR; + /* + * FIXME: does SSRC1.SCFR need to be set + * when codec is master ? + */ + /* FIXME: this mode has not been tested */ + break; + case SOF_DAI_FMT_CBS_CFM: + sscr1 |= SSCR1_SCFR; + /* FIXME: this mode has not been tested */ + break; + default: + trace_ssp_error("ec2"); + ret = -EINVAL; + goto out; + } + + /* clock signal polarity */ + switch (config->format & SOF_DAI_FMT_INV_MASK) { + case SOF_DAI_FMT_NB_NF: + break; + case SOF_DAI_FMT_NB_IF: + break; + case SOF_DAI_FMT_IB_IF: + sspsp |= SSPSP_SCMODE(2); + inverted_frame = true; /* handled later with format */ + break; + case SOF_DAI_FMT_IB_NF: + sspsp |= SSPSP_SCMODE(2); + inverted_frame = true; /* handled later with format */ + break; + default: + trace_ssp_error("ec3"); + ret = -EINVAL; + goto out; + } + +#ifdef CLK_TYPE /* not enabled, keep the code for reference */ + /* TODO: allow topology to define SSP clock type */ + config->ssp[0].clk_id = SSP_CLK_EXT; + + /* clock source */ + switch (config->ssp[0].clk_id) { + case SSP_CLK_AUDIO: + sscr0 |= SSCR0_ACS; + break; + case SSP_CLK_NET_PLL: + sscr0 |= SSCR0_MOD; + break; + case SSP_CLK_EXT: + sscr0 |= SSCR0_ECS; + break; + case SSP_CLK_NET: + sscr0 |= SSCR0_NCS | SSCR0_MOD; + break; + default: + trace_ssp_error("ec4"); + ret = -EINVAL; + goto out; + } +#else + sscr0 |= SSCR0_MOD | SSCR0_ACS; +#endif + + /* BCLK is generated from MCLK - must be divisable */ + if (config->mclk % config->bclk) { + trace_ssp_error("ec5"); + ret = -EINVAL; + goto out; + } + + /* divisor must be within SCR range */ + mdiv = (config->mclk / config->bclk) - 1; + if (mdiv > (SSCR0_SCR_MASK >> 8)) { + trace_ssp_error("ec6"); + ret = -EINVAL; + goto out; + } + + /* set the SCR divisor */ + sscr0 |= SSCR0_SCR(mdiv); + + /* calc frame width based on BCLK and rate - must be divisable */ + if (config->bclk % config->fclk) { + trace_ssp_error("ec7"); + ret = -EINVAL; + goto out; + } + + /* must be enouch BCLKs for data */ + bdiv = config->bclk / config->fclk; + if (bdiv < config->sample_container_bits * + ((config->rx_slot_mask + 1) / 2)) { + trace_ssp_error("ec8"); + ret = -EINVAL; + goto out; + } + + /* sample_container_bits must be <= 38 for SSP */ + if (config->sample_container_bits > 38) { + trace_ssp_error("ec9"); + ret = -EINVAL; + goto out; + } + + /* format */ + switch (config->format & SOF_DAI_FMT_FORMAT_MASK) { + case SOF_DAI_FMT_I2S: + + start_delay = config->sample_container_bits > + config->sample_valid_bits ? 1 : 0; + + sscr0 |= SSCR0_FRDC(config->num_slots); + + /* set asserted frame length */ + frame_len = config->sample_container_bits; + + /* handle frame polarity, I2S default is falling/active low */ + sspsp |= SSPSP_SFRMP(!inverted_frame); + + break; + + case SOF_DAI_FMT_LEFT_J: + + start_delay = 0; + + sscr0 |= SSCR0_FRDC(config->num_slots); + + /* LJDFD enable */ + sscr2 &= ~SSCR2_LJDFD; + + /* set asserted frame length */ + frame_len = config->sample_container_bits; + + /* LEFT_J default is rising/active high, opposite of I2S */ + sspsp |= SSPSP_SFRMP(inverted_frame); + + break; + case SOF_DAI_FMT_DSP_A: + + start_delay = config->sample_container_bits > + config->sample_valid_bits ? 1 : 0; + + sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->num_slots); + + /* set asserted frame length */ + frame_len = config->sample_container_bits; + + /* handle frame polarity, DSP_A default is rising/active high */ + sspsp |= SSPSP_SFRMP(inverted_frame); + + break; + case SOF_DAI_FMT_DSP_B: + + start_delay = 0; + + sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->num_slots); + + /* set asserted frame length */ + frame_len = config->sample_container_bits; + + /* handle frame polarity, DSP_A default is rising/active high */ + sspsp |= SSPSP_SFRMP(inverted_frame); + + break; + default: + trace_ssp_error("eca"); + ret = -EINVAL; + goto out; + } + + sspsp |= SSPSP_DMYSTRT(start_delay); + sspsp |= SSPSP_SFRMWDTH(frame_len); + + data_size = config->sample_valid_bits; + + if (data_size > 16) + sscr0 |= (SSCR0_EDSS | SSCR0_DSIZE(data_size - 16)); + else + sscr0 |= SSCR0_DSIZE(data_size); + + mdivc = 0x00100001; + /* bypass divider for MCLK */ + mdivr = 0x00000fff; + + trace_ssp("coe"); + ssp_write(dai, SSCR0, sscr0); + ssp_write(dai, SSCR1, sscr1); + ssp_write(dai, SSCR2, sscr2); + ssp_write(dai, SSCR3, sscr3); + ssp_write(dai, SSPSP, sspsp); + ssp_write(dai, SSPSP2, sspsp2); + ssp_write(dai, SSIOC, ssioc); + ssp_write(dai, SSTO, ssto); + ssp_write(dai, SSTSA, sstsa); + ssp_write(dai, SSRSA, ssrsa); + + trace_value(sscr0); + trace_value(sscr1); + trace_value(ssto); + trace_value(sspsp); + trace_value(sstsa); + trace_value(ssrsa); + trace_value(sscr2); + trace_value(sspsp2); + trace_value(sscr3); + trace_value(ssioc); + + mn_reg_write(0x0, mdivc); + mn_reg_write(0x80, mdivr); + mn_reg_write(0x100 + config->id * 0x8 + 0x0, i2s_m); + mn_reg_write(0x100 + config->id * 0x8 + 0x4, i2s_n); + + ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_PREPARE; + ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_PREPARE; + +out: + spin_unlock(&ssp->lock); + + return ret; +} + +/* Digital Audio interface formatting */ +static inline int ssp_set_loopback_mode(struct dai *dai, uint32_t lbm) +{ + struct ssp_pdata *ssp = dai_get_drvdata(dai); + + trace_ssp("loo"); + spin_lock(&ssp->lock); + + ssp_update_bits(dai, SSCR1, SSCR1_LBM, lbm ? SSCR1_LBM : 0); + + spin_unlock(&ssp->lock); + + return 0; +} + +/* start the SSP for either playback or capture */ +static void ssp_start(struct dai *dai, int direction) +{ + struct ssp_pdata *ssp = dai_get_drvdata(dai); + + spin_lock(&ssp->lock); + + /* enable port */ + ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE); + ssp->state[direction] = COMP_STATE_ACTIVE; + + trace_ssp("sta"); + + /* enable DMA */ + if (direction == DAI_DIR_PLAYBACK) { + ssp_update_bits(dai, SSCR1, SSCR1_TSRE, SSCR1_TSRE); + ssp_update_bits(dai, SSTSA, 0x1 << 8, 0x1 << 8); + } else { + ssp_update_bits(dai, SSCR1, SSCR1_RSRE, SSCR1_RSRE); + ssp_update_bits(dai, SSRSA, 0x1 << 8, 0x1 << 8); + } + + spin_unlock(&ssp->lock); +} + +/* stop the SSP for either playback or capture */ +static void ssp_stop(struct dai *dai) +{ + struct ssp_pdata *ssp = dai_get_drvdata(dai); + + spin_lock(&ssp->lock); + + /* stop Rx if we are not capturing */ + if (ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE) { + ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0); + ssp_update_bits(dai, SSTSA, 0x1 << 8, 0x0 << 8); + trace_ssp("Ss0"); + } + + /* stop Tx if we are not playing */ + if (ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE) { + ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0); + ssp_update_bits(dai, SSRSA, 0x1 << 8, 0x0 << 8); + trace_ssp("Ss1"); + } + + /* disable SSP port if no users */ + if (ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE && + ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE) { + ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0); + ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PREPARE; + ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PREPARE; + trace_ssp("Ss2"); + } + + spin_unlock(&ssp->lock); +} + +static int ssp_trigger(struct dai *dai, int cmd, int direction) +{ + struct ssp_pdata *ssp = dai_get_drvdata(dai); + + trace_ssp("tri"); + + switch (cmd) { + case COMP_CMD_START: + if (ssp->state[direction] == COMP_STATE_PREPARE || + ssp->state[direction] == COMP_STATE_PAUSED) + ssp_start(dai, direction); + break; + case COMP_CMD_RELEASE: + if (ssp->state[direction] == COMP_STATE_PAUSED || + ssp->state[direction] == COMP_STATE_PREPARE) + ssp_start(dai, direction); + break; + case COMP_CMD_STOP: + case COMP_CMD_PAUSE: + ssp->state[direction] = COMP_STATE_PAUSED; + ssp_stop(dai); + break; + case COMP_CMD_RESUME: + ssp_context_restore(dai); + break; + case COMP_CMD_SUSPEND: + ssp_context_store(dai); + break; + default: + break; + } + + return 0; +} + +/* clear IRQ sources atm */ +static void ssp_irq_handler(void *data) +{ + struct dai *dai = data; + + trace_ssp("irq"); + trace_value(ssp_read(dai, SSSR)); + + /* clear IRQ */ + ssp_write(dai, SSSR, ssp_read(dai, SSSR)); + platform_interrupt_clear(ssp_irq(dai), 1); +} + +static int ssp_probe(struct dai *dai) +{ + struct ssp_pdata *ssp; + + /* allocate private data */ + ssp = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(*ssp)); + dai_set_drvdata(dai, ssp); + + spinlock_init(&ssp->lock); + + ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_READY; + ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_READY; + + /* register our IRQ handler */ + interrupt_register(ssp_irq(dai), ssp_irq_handler, dai); + platform_interrupt_unmask(ssp_irq(dai), 1); + interrupt_enable(ssp_irq(dai)); + + return 0; +} + +const struct dai_ops ssp_ops = { + .trigger = ssp_trigger, + .set_config = ssp_set_config, + .pm_context_store = ssp_context_store, + .pm_context_restore = ssp_context_restore, + .probe = ssp_probe, + .set_loopback_mode = ssp_set_loopback_mode, +}; diff --git a/src/include/reef/ssp.h b/src/include/reef/ssp.h index c00d14c..e041121 100644 --- a/src/include/reef/ssp.h +++ b/src/include/reef/ssp.h @@ -38,6 +38,8 @@ #include <reef/trace.h> #include <reef/wait.h> +#define BIT(x) (1 << (x)) + #define SSP_CLK_AUDIO 0 #define SSP_CLK_NET_PLL 1 #define SSP_CLK_EXT 2 @@ -55,11 +57,17 @@ #define SSTSA 0x30 #define SSRSA 0x34 #define SSTSS 0x38 + +#if defined CONFIG_BAYTRAIL ||\ + defined CONFIG_CHERRYTRAIL ||\ + defined CONFIG_BROADWELL ||\ + defined CONFIG_HASWELL #define SSCR2 0x40 #define SFIFOTT 0x6C #define SSCR3 0x70 #define SSCR4 0x74 #define SSCR5 0x78 +#endif extern const struct dai_ops ssp_ops; @@ -112,17 +120,28 @@ extern const struct dai_ops ssp_ops; #define SSCR1_TTE (1 << 30) #define SSCR1_TTELP (1 << 31) +#if defined CONFIG_BAYTRAIL ||\ + defined CONFIG_CHERRYTRAIL ||\ + defined CONFIG_BROADWELL ||\ + defined CONFIG_HASWELL /* SSCR2 bits */ -#define SSCR2_URUN_FIX0 (1 << 0) -#define SSCR2_URUN_FIX1 (1 << 1) -#define SSCR2_SLV_EXT_CLK_RUN_EN (1 << 2) -#define SSCR2_CLK_DEL_EN (1 << 3) -#define SSCR2_UNDRN_FIX_EN (1 << 6) -#define SSCR2_FIFO_EMPTY_FIX_EN (1 << 7) -#define SSCR2_ASRC_CNTR_EN (1 << 8) -#define SSCR2_ASRC_CNTR_CLR (1 << 9) -#define SSCR2_ASRC_FRM_CNRT_EN (1 << 10) -#define SSCR2_ASRC_INTR_MASK (1 << 11) +#define SSCR2_URUN_FIX0 BIT(0) +#define SSCR2_URUN_FIX1 BIT(1) +#define SSCR2_SLV_EXT_CLK_RUN_EN BIT(2) +#define SSCR2_CLK_DEL_EN BIT(3) +#define SSCR2_UNDRN_FIX_EN BIT(6) +#define SSCR2_FIFO_EMPTY_FIX_EN BIT(7) +#define SSCR2_ASRC_CNTR_EN BIT(8) +#define SSCR2_ASRC_CNTR_CLR BIT(9) +#define SSCR2_ASRC_FRM_CNRT_EN BIT(10) +#define SSCR2_ASRC_INTR_MASK BIT(11) +#elif defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE +#define SSCR2_TURM1 BIT(1) +#define SSCR2_SDFD BIT(14) +#define SSCR2_SDPM BIT(16) +#define SSCR2_LJDFD BIT(17) +#endif + /* SSR bits */ #define SSSR_TNF (1 << 2) @@ -143,6 +162,17 @@ extern const struct dai_ops ssp_ops; #define SSPSP_DMYSTOP(x) ((x) << 23) #define SSPSP_FSRT (1 << 25) +#if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE +#define SSPSP_EDMYSTOP(x) ((x) << 26) +#define SSTSS 0x38 +#define SSCR2 0x40 +#define SSPSP2 0x44 +#define SSCR3 0x48 +#define SSIOC 0x4C + +#define SSP_REG_MAX SSIOC +#endif + /* SSCR3 bits */ #define SSCR3_FRM_MST_EN (1 << 0) #define SSCR3_I2S_MODE_EN (1 << 1) @@ -169,6 +199,22 @@ extern const struct dai_ops ssp_ops; #define SFIFOTT_TX(x) ((x) - 1) #define SFIFOTT_RX(x) (((x) - 1) << 16) +#if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE +#define SSTSA_TSEN BIT(8) +#define SSRSA_RSEN BIT(8) + +#define SSCR3_TFL_MASK (0x0000003f) +#define SSCR3_RFL_MASK (0x00003f00) +#define SSCR3_TFT_MASK (0x003f0000) +#define SSCR3_TX(x) (((x) - 1) << 16) +#define SSCR3_RFT_MASK (0x3f000000) +#define SSCR3_RX(x) (((x) - 1) << 24) + +#define SSIOC_TXDPDEB BIT(1) +#define SSIOC_SFCR BIT(4) +#define SSIOC_SCOE BIT(5) +#endif + /* tracing */ #define trace_ssp(__e) trace_event(TRACE_CLASS_SSP, __e) #define trace_ssp_error(__e) trace_error(TRACE_CLASS_SSP, __e) -- 2.14.1

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[Sound-open-firmware] [PATCH] m4: add ax_check_compile_flag to local m4 directory.
by Liam Girdwood 07 Feb '18

07 Feb '18

ax_check_comile_flag is not widely available so package it locally. Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- .gitignore | 3 +- m4/ax_check_compile_flag.m4 | 74 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 m4/ax_check_compile_flag.m4 diff --git a/.gitignore b/.gitignore index 00afa3d..d59528a 100644 --- a/.gitignore +++ b/.gitignore @@ -31,7 +31,8 @@ ar-lib stamp-h1 CHANGELOG ltmain.sh -m4/* +m4/lt* +m4/libtool.m4 libtool src/include/version.h diff --git a/m4/ax_check_compile_flag.m4 b/m4/ax_check_compile_flag.m4 new file mode 100644 index 0000000..dcabb92 --- /dev/null +++ b/m4/ax_check_compile_flag.m4 @@ -0,0 +1,74 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_CHECK_COMPILE_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS], [INPUT]) +# +# DESCRIPTION +# +# Check whether the given FLAG works with the current language's compiler +# or gives an error. (Warnings, however, are ignored) +# +# ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on +# success/failure. +# +# If EXTRA-FLAGS is defined, it is added to the current language's default +# flags (e.g. CFLAGS) when the check is done. The check is thus made with +# the flags: "CFLAGS EXTRA-FLAGS FLAG". This can for example be used to +# force the compiler to issue an error when a bad flag is given. +# +# INPUT gives an alternative input source to AC_COMPILE_IFELSE. +# +# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this +# macro in sync with AX_CHECK_{PREPROC,LINK}_FLAG. +# +# LICENSE +# +# Copyright (c) 2008 Guido U. Draheim <guidod(a)gmx.de> +# Copyright (c) 2011 Maarten Bosmans <mkbosmans(a)gmail.com> +# +# This program is free software: you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation, either version 3 of the License, or (at your +# option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General +# Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program. If not, see <https://www.gnu.org/licenses/>. +# +# As a special exception, the respective Autoconf Macro's copyright owner +# gives unlimited permission to copy, distribute and modify the configure +# scripts that are the output of Autoconf when processing the Macro. You +# need not follow the terms of the GNU General Public License when using +# or distributing such scripts, even though portions of the text of the +# Macro appear in them. The GNU General Public License (GPL) does govern +# all other use of the material that constitutes the Autoconf Macro. +# +# This special exception to the GPL applies to versions of the Autoconf +# Macro released by the Autoconf Archive. When you make and distribute a +# modified version of the Autoconf Macro, you may extend this special +# exception to the GPL to apply to your modified version as well. + +#serial 5 + +AC_DEFUN([AX_CHECK_COMPILE_FLAG], +[AC_PREREQ(2.64)dnl for _AC_LANG_PREFIX and AS_VAR_IF +AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_[]_AC_LANG_ABBREV[]flags_$4_$1])dnl +AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], CACHEVAR, [ + ax_check_save_flags=$[]_AC_LANG_PREFIX[]FLAGS + _AC_LANG_PREFIX[]FLAGS="$[]_AC_LANG_PREFIX[]FLAGS $4 $1" + AC_COMPILE_IFELSE([m4_default([$5],[AC_LANG_PROGRAM()])], + [AS_VAR_SET(CACHEVAR,[yes])], + [AS_VAR_SET(CACHEVAR,[no])]) + _AC_LANG_PREFIX[]FLAGS=$ax_check_save_flags]) +AS_VAR_IF(CACHEVAR,yes, + [m4_default([$2], :)], + [m4_default([$3], :)]) +AS_VAR_POPDEF([CACHEVAR])dnl +])dnl AX_CHECK_COMPILE_FLAGS -- 2.14.1

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[Sound-open-firmware] [PATCH] dai: configure its frame_fmt from topology
by Xiuli Pan 06 Feb '18

06 Feb '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> For dai component, it's frame_fmt may be different with host, we usually configure it from topology, here fix it. Contributor: Keyon Jie <yang.jie(a)linux.intel.com> Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- Modify from Keyon's patch, changed to use COMP_GET_CONFIG. Test with: Mininow max rt5651 SOF master: 0505823b9667036202758ea950c3ff3347359730 SOF-Tool master: 8c9ebfe9c4f8037b0d0816dedcb87dabef347c6b https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- src/audio/dai.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/audio/dai.c b/src/audio/dai.c index d19e18a..8731ffd 100644 --- a/src/audio/dai.c +++ b/src/audio/dai.c @@ -383,6 +383,7 @@ static int dai_params(struct comp_dev *dev) { struct dai_data *dd = comp_get_drvdata(dev); struct comp_buffer *dma_buffer; + struct sof_ipc_comp_config *dconfig = COMP_GET_CONFIG(dev); trace_dai("par"); @@ -392,6 +393,9 @@ static int dai_params(struct comp_dev *dev) return -EINVAL; } + /* for DAI, we should configure its frame_fmt from topology */ + dev->params.frame_fmt = dconfig->frame_fmt; + /* calculate period size based on config */ dev->frame_bytes = comp_frame_bytes(dev); if (dev->frame_bytes == 0) { -- 2.7.4

2 1

[Sound-open-firmware] [PATCH] rimage: fix manifest header path
by Xiuli Pan 06 Feb '18

06 Feb '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> We moved header manifest.h is sof/upai now. Modify the configure path and include path. Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- Test with: GP-MRB with NoCodec, Mininow max rt5651 SOF master: 0505823b9667036202758ea950c3ff3347359730 SOF-Tool master: 8c9ebfe9c4f8037b0d0816dedcb87dabef347c6b https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- configure.ac | 2 +- rimage/manifest.c | 2 +- rimage/manifest.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configure.ac b/configure.ac index 6e9c758..f85f18c 100644 --- a/configure.ac +++ b/configure.ac @@ -4,7 +4,7 @@ AC_INIT([sof-tools], [1.0.1]) AM_INIT_AUTOMAKE([foreign]) AC_CONFIG_SRCDIR([rimage/rimage.c]) AC_CONFIG_HEADERS([config.h]) -AC_CHECK_HEADER([sof/manifest.h]) +AC_CHECK_HEADER([sof/uapi/manifest.h]) AC_CANONICAL_HOST diff --git a/rimage/manifest.c b/rimage/manifest.c index 24fb76f..68e6d8b 100644 --- a/rimage/manifest.c +++ b/rimage/manifest.c @@ -22,7 +22,7 @@ #include <string.h> #include <time.h> #include <sys/time.h> -#include <sof/manifest.h> +#include <sof/uapi/manifest.h> #include "rimage.h" #include "file_format.h" diff --git a/rimage/manifest.h b/rimage/manifest.h index 348f47f..655963f 100644 --- a/rimage/manifest.h +++ b/rimage/manifest.h @@ -15,7 +15,7 @@ #define __MANIFEST_H__ #include <stdint.h> -#include <sof/manifest.h> +#include <sof/uapi/manifest.h> #include "css.h" #include "cse.h" #include "plat_auth.h" -- 2.7.4

2 1

[Sound-open-firmware] [PATCH] Audio format: Bug fix for erroneous fractional multiplication macro
by Seppo Ingalsuo 06 Feb '18

06 Feb '18

Due to misplaced parentheses the computation gives half of correct result and omits rounding. Currently this macro is not used by code in SOF git repository. Developers who may use format.h macros should check their code. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo(a)linux.intel.com> --- src/include/reef/audio/format.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/include/reef/audio/format.h b/src/include/reef/audio/format.h index 8964f33..c9c23ec 100644 --- a/src/include/reef/audio/format.h +++ b/src/include/reef/audio/format.h @@ -85,7 +85,8 @@ /* Fractional multiplication with shift and round * Note that the parameters px and py must be cast to (int64_t) if other type. */ -#define Q_MULTSR_32X32(px, py, qx, qy, qp) (((px) * (py) >> (((qx)+(qy)-(qp)-1) +1) >> 1)) +#define Q_MULTSR_32X32(px, py, qx, qy, qp) \ + ((((px) * (py) >> ((qx)+(qy)-(qp)-1)) + 1) >> 1) /* Saturation */ #define SATP_INT32(x) (((x) > INT32_MAX) ? INT32_MAX : (x)) -- 2.11.0

2 1

[Sound-open-firmware] [PATCH] rimage: add check for .bss section
by Xiuli Pan 06 Feb '18

06 Feb '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> We may have heap buffers for base FW, but they are handled by the runtime function. We did not need to set them as bss in FW manifest. So add check to mark the .bss segment as BSS and other segment as HEAP. Then we only update manifest BSS segmet with BSS section. Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- Test with: GP-MRB with NoCodec, Mininow max rt5651 SOF master: 0505823b9667036202758ea950c3ff3347359730 SOF-Tool master: 8c9ebfe9c4f8037b0d0816dedcb87dabef347c6b https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 --- rimage/elf.c | 26 ++++++++++++++++++++------ rimage/rimage.h | 1 + 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/rimage/elf.c b/rimage/elf.c index b912477..1dc48f3 100644 --- a/rimage/elf.c +++ b/rimage/elf.c @@ -27,6 +27,7 @@ static int elf_read_sections(struct image *image, struct module *module) size_t count; int i, ret; uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + int man_section_idx; /* read in section header */ ret = fseek(module->fd, hdr->e_shoff, SEEK_SET); @@ -50,6 +51,16 @@ static int elf_read_sections(struct image *image, struct module *module) return -errno; } + /* find manifest module data */ + man_section_idx = elf_find_section(image, module, ".bss"); + if (man_section_idx < 0) { + return -EINVAL; + } + module->bss_index = man_section_idx; + + fprintf(stdout, " BSS module metadata section at index %d\n", + man_section_idx); + /* parse each section */ for (i = 0; i < hdr->e_shnum; i++) { @@ -211,7 +222,7 @@ int elf_is_rom(struct image *image, Elf32_Shdr *section) } static void elf_module_size(struct image *image, struct module *module, - Elf32_Shdr *section) + Elf32_Shdr *section, int index) { switch (section->sh_type) { case SHT_PROGBITS: @@ -236,12 +247,14 @@ static void elf_module_size(struct image *image, struct module *module, break; case SHT_NOBITS: /* bss */ - if (module->bss_start > section->sh_addr) + if (index == module->bss_index) { + /* updated the .bss segment */ module->bss_start = section->sh_addr; - if (module->bss_end < section->sh_addr + section->sh_size) module->bss_end = section->sh_addr + section->sh_size; - - fprintf(stdout, "\tBSS\n"); + fprintf(stdout, "\tBSS\n"); + } else { + fprintf(stdout, "\tHEAP\n"); + } break; default: break; @@ -282,7 +295,8 @@ static void elf_module_limits(struct image *image, struct module *module) section->sh_size); /* text or data section */ - elf_module_size(image, module, section); + elf_module_size(image, module, section, i); + } fprintf(stdout, "\n"); diff --git a/rimage/rimage.h b/rimage/rimage.h index 84ff93f..a68f1a8 100644 --- a/rimage/rimage.h +++ b/rimage/rimage.h @@ -65,6 +65,7 @@ struct module { int num_sections; int num_bss; int fw_size; + int bss_index; /* sizes do not include any gaps */ int bss_size; -- 2.7.4

2 1

[Sound-open-firmware] SOF master build REMINDER
by Pan, Xiuli 06 Feb '18

06 Feb '18

Reminder for applying this patch! On master branch Please check if you have install sudo apt-get install autoconf-archive And see this line when run ./autogen.sh aclocal: installing 'm4/ax_check_compile_flag.m4' from '/usr/share/aclocal/ax_check_compile_flag.m4' or have file 'm4/ax_check_compile_flag.m4' in your git repo. If not you will find these when configure. ./configure: line 3451: syntax error near unexpected token `-msse4.2,' ./configure: line 3451: `AX_CHECK_COMPILE_FLAG(-msse4.2, SSE42_CFLAGS="-DOPS_SSE42 -msse4.2 -ffast-math -ftree-vectorizer-verbose=0",' It seems to be some m4 expand auto check about 'AX_CHECK_COMPILE_FLAG'. If you did no install this macro it will just copy but not expand it in configure file. And then the error will occur. Synced with Keqiao to update CI environment and build guide. Thanks Xiuli >Subject: [Sound-open-firmware] [PATCH v5] build: add library build support for >host platform > >This patch provides library build support for host platform architecture. >It enables creating separate libraries for each SOF audio component. > >Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com>

2 1

[Sound-open-firmware] [PATCH v2] dw-dma: add support for interrupt per channel
by Keyon Jie 06 Feb '18

06 Feb '18

On Apollolake, the interrupt number for different channels of the same controller are different, here add implementation of it: register interrupt handler for each channel, and don't need check channel in its specific handler anymore. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- Update in v2: Fixed checkpatch.pl issues Tested on GP-MRB, SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 src/drivers/dw-dma.c | 247 +++++++++++++++++++++++++++++++++++++------------ src/include/reef/dma.h | 6 ++ 2 files changed, 195 insertions(+), 58 deletions(-) diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index 5501f8e..7a1805e 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -809,6 +809,194 @@ static inline void dw_dma_chan_reload_next(struct dma *dma, int channel, dw_write(dma, DW_DMA_CHAN_EN, CHAN_ENABLE(channel)); } +static void dw_dma_setup(struct dma *dma) +{ + struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data; + int i; + + /* we cannot config DMAC if DMAC has been already enabled by host */ + if (dw_read(dma, DW_DMA_CFG) != 0) + dw_write(dma, DW_DMA_CFG, 0x0); + + /* now check that it's 0 */ + for (i = DW_DMA_CFG_TRIES; i > 0; i--) { + if (dw_read(dma, DW_DMA_CFG) == 0) + goto found; + } + trace_dma_error("eDs"); + return; + +found: + for (i = 0; i < DW_MAX_CHAN; i++) + dw_read(dma, DW_DMA_CHAN_EN); + +#ifdef HAVE_HDDA + /* enable HDDA before DMAC */ + shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH); +#endif + + /* enable the DMA controller */ + dw_write(dma, DW_DMA_CFG, 1); + + /* mask all interrupts for all 8 channels */ + dw_write(dma, DW_MASK_TFR, INT_MASK_ALL); + dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL); + dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL); + dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL); + dw_write(dma, DW_MASK_ERR, INT_MASK_ALL); + +#ifdef DW_FIFO_PARTITION + /* TODO: we cannot config DMA FIFOs if DMAC has been already */ + /* allocate FIFO partitions, 128 bytes for each ch */ + dw_write(dma, DW_FIFO_PART1_LO, 0x100080); + dw_write(dma, DW_FIFO_PART1_HI, 0x100080); + dw_write(dma, DW_FIFO_PART0_HI, 0x100080); + dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26)); + dw_write(dma, DW_FIFO_PART0_LO, 0x100080); +#endif + + /* set channel priorities */ + for (i = 0; i < DW_MAX_CHAN; i++) { +#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL ||\ + defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE + dw_write(dma, DW_CTRL_HIGH(i), + DW_CTLH_CLASS(dp->chan[i].class)); +#elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL + dw_write(dma, DW_CFG_LOW(i), + DW_CFG_CLASS(dp->chan[i].class)); +#endif + } +} + +#ifdef CONFIG_APOLLOLAKE +/* external layer 2 interrupt for dmac */ +static void dw_dma_irq_handler(void *data) +{ + struct dma_int *dma_int = (struct dma_int *)data; + struct dma *dma = dma_int->dma; + struct dma_pdata *p = dma_get_drvdata(dma); + struct dma_sg_elem next; + uint32_t status_tfr = 0, status_block = 0, status_err = 0, status_intr; + uint32_t mask; + int i = dma_int->channel; + + status_intr = dw_read(dma, DW_INTR_STATUS); + if (!status_intr) + trace_dma_error("eDI"); + + trace_dma("irq"); + trace_value(status_intr); + + /* get the source of our IRQ. */ + status_block = dw_read(dma, DW_STATUS_BLOCK); + status_tfr = dw_read(dma, DW_STATUS_TFR); + + /* TODO: handle errors, just clear them atm */ + status_err = dw_read(dma, DW_STATUS_ERR); + if (status_err) { + trace_dma_error("eDi"); + dw_write(dma, DW_CLEAR_ERR, status_err & i); + } + + /* clear interrupts for channel*/ + dw_write(dma, DW_CLEAR_BLOCK, status_block); + dw_write(dma, DW_CLEAR_TFR, status_tfr); + + /* skip if channel is not running */ + if (p->chan[i].status != COMP_STATE_ACTIVE) { + trace_dma_error("eDs"); + return; + } + + mask = 0x1 << i; + +#if DW_USE_HW_LLI + /* end of a LLI block */ + if (status_block & mask && + p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) { + next.src = DMA_RELOAD_LLI; + next.dest = DMA_RELOAD_LLI; + /* will reload lli by default */ + next.size = DMA_RELOAD_LLI; + p->chan[i].cb(p->chan[i].cb_data, + DMA_IRQ_TYPE_BLOCK, &next); + } +#endif + /* end of a transfer */ + if ((status_tfr & mask) && + (p->chan[i].cb_type & DMA_IRQ_TYPE_LLIST)) { + trace_value(status_tfr); + + next.src = DMA_RELOAD_LLI; + next.dest = DMA_RELOAD_LLI; + next.size = DMA_RELOAD_LLI; /* will reload lli by default */ + if (p->chan[i].cb) + p->chan[i].cb(p->chan[i].cb_data, + DMA_IRQ_TYPE_LLIST, &next); + + /* check for reload channel: + * next.size is DMA_RELOAD_END, stop this dma copy; + * next.size > 0 but not DMA_RELOAD_LLI, use next + * element for next copy; + * if we are waiting for pause, pause it; + * otherwise, reload lli + */ + switch (next.size) { + case DMA_RELOAD_END: + p->chan[i].status = COMP_STATE_PREPARE; + break; + case DMA_RELOAD_LLI: + /* reload lli, but let's check if it is paused */ + if (p->chan[i].status != COMP_STATE_PAUSED) + dw_dma_chan_reload_lli(dma, i); + break; + default: + dw_dma_chan_reload_next(dma, i, &next); + break; + } + } +} + +static int dw_dma_probe(struct dma *dma) +{ + struct dma_int *dma_int[DW_MAX_CHAN]; + struct dma_pdata *dw_pdata; + int i; + + /* allocate private data */ + dw_pdata = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(*dw_pdata)); + dma_set_drvdata(dma, dw_pdata); + + spinlock_init(&dma->lock); + + dw_dma_setup(dma); + + /* init work */ + for (i = 0; i < dma->plat_data.channels; i++) { + dw_pdata->chan[i].dma = dma; + dw_pdata->chan[i].channel = i; + dw_pdata->chan[i].status = COMP_STATE_INIT; + + dma_int[i] = rzalloc(RZONE_SYS, RFLAGS_NONE, + sizeof(struct dma_int)); + + dma_int[i]->dma = dma; + dma_int[i]->channel = i; + dma_int[i]->irq = dma->plat_data.irq + + (i << REEF_IRQ_BIT_SHIFT); + + /* register our IRQ handler */ + interrupt_register(dma_int[i]->irq, + dw_dma_irq_handler, + dma_int[i]); + interrupt_enable(dma_int[i]->irq); + } + + return 0; +} + +#else + /* this will probably be called at the end of every period copied */ static void dw_dma_irq_handler(void *data) { @@ -909,64 +1097,6 @@ static void dw_dma_irq_handler(void *data) } } -static void dw_dma_setup(struct dma *dma) -{ - struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data; - int i; - - /* we cannot config DMAC if DMAC has been already enabled by host */ - if (dw_read(dma, DW_DMA_CFG) != 0) - dw_write(dma, DW_DMA_CFG, 0x0); - - /* now check that it's 0 */ - for (i = DW_DMA_CFG_TRIES; i > 0; i--) { - if (dw_read(dma, DW_DMA_CFG) == 0) - goto found; - } - trace_dma_error("eDs"); - return; - -found: - for (i = 0; i < DW_MAX_CHAN; i++) - dw_read(dma, DW_DMA_CHAN_EN); - -#ifdef HAVE_HDDA - /* enable HDDA before DMAC */ - shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH); -#endif - - /* enable the DMA controller */ - dw_write(dma, DW_DMA_CFG, 1); - - /* mask all interrupts for all 8 channels */ - dw_write(dma, DW_MASK_TFR, INT_MASK_ALL); - dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL); - dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL); - dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL); - dw_write(dma, DW_MASK_ERR, INT_MASK_ALL); - -#ifdef DW_FIFO_PARTITION - /* TODO: we cannot config DMA FIFOs if DMAC has been already */ - /* allocate FIFO partitions, 128 bytes for each ch */ - dw_write(dma, DW_FIFO_PART1_LO, 0x100080); - dw_write(dma, DW_FIFO_PART1_HI, 0x100080); - dw_write(dma, DW_FIFO_PART0_HI, 0x100080); - dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26)); - dw_write(dma, DW_FIFO_PART0_LO, 0x100080); -#endif - - /* set channel priorities */ - for (i = 0; i < DW_MAX_CHAN; i++) { -#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \ - || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE - dw_write(dma, DW_CTRL_HIGH(i), DW_CTLH_CLASS(dp->chan[i].class)); -#else - dw_write(dma, DW_CFG_LOW(i), DW_CFG_CLASS(dp->chan[i].class)); -#endif - } - -} - static int dw_dma_probe(struct dma *dma) { struct dma_pdata *dw_pdata; @@ -993,6 +1123,7 @@ static int dw_dma_probe(struct dma *dma) return 0; } +#endif const struct dma_ops dw_dma_ops = { .channel_get = dw_dma_channel_get, diff --git a/src/include/reef/dma.h b/src/include/reef/dma.h index e33adaa..77f8f71 100644 --- a/src/include/reef/dma.h +++ b/src/include/reef/dma.h @@ -128,6 +128,12 @@ struct dma { void *private; }; +struct dma_int { + struct dma *dma; + uint32_t channel; + uint32_t irq; +}; + struct dma *dma_get(int dmac_id); #define dma_set_drvdata(dma, data) \ -- 2.11.0

2 2