January 2018 - Sound-open-firmware - mailman.alsa-project.org

[Sound-open-firmware] Using the Qemu DSP emulator
by Daniel Baluta 19 Mar '18

19 Mar '18

Hi, I'm following the instruction on SOF wiki page on how to use the emulator [1] and both VM0 and VM1 are up, anyhow SOF DSP device isn't probed. How do you do it in your qemu setup? Are you using an ACPI file? (or DT?). I'm running the following commands: # ./xtensa-host.sh bxt # ./x86-host.sh bxt and pointing qemu to load my bzimage. thanks, Daniel. [1] https://www.alsa-project.org/main/index.php/Firmware#Using_the_Qemu_DSP_emu…

2 14

[Sound-open-firmware] [PATCH] ASoC: SOF: topology: add handle to buffer type
by Keyon Jie 08 Feb '18

08 Feb '18

Align with SOFT topology and SOF, add handle to buffer type. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- include/uapi/sound/sof-ipc.h | 7 +++++++ include/uapi/sound/sof-topology.h | 1 + sound/soc/sof/topology.c | 6 ++++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/include/uapi/sound/sof-ipc.h b/include/uapi/sound/sof-ipc.h index 741b412545b7..9a81896780ba 100644 --- a/include/uapi/sound/sof-ipc.h +++ b/include/uapi/sound/sof-ipc.h @@ -521,10 +521,17 @@ struct sof_ipc_comp { * Component Buffers */ +/* types of buffer */ +enum sof_buffer_type { + SOF_BUFF_GENERAL = 0, + SOF_BUFF_DMA = 1, /* dma buffer */ +}; + /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ struct sof_ipc_buffer { struct sof_ipc_comp comp; uint32_t size; /* buffer size in bytes */ + enum sof_buffer_type type; /* buffer type */ } __attribute__((packed)); diff --git a/include/uapi/sound/sof-topology.h b/include/uapi/sound/sof-topology.h index 6fe695c46386..e855ef48fd1a 100644 --- a/include/uapi/sound/sof-topology.h +++ b/include/uapi/sound/sof-topology.h @@ -33,6 +33,7 @@ /* buffers */ #define SOF_TKN_BUF_SIZE 100 +#define SOF_TKN_BUF_TYPE 101 /* DAI */ #define SOF_TKN_DAI_DMAC 151 diff --git a/sound/soc/sof/topology.c b/sound/soc/sof/topology.c index 2d813335f3d2..3f2e9d72fba5 100644 --- a/sound/soc/sof/topology.c +++ b/sound/soc/sof/topology.c @@ -150,6 +150,8 @@ static int get_token_dai_type(void *elem ,void *object, u32 offset, u32 size) static const struct sof_topology_token buffer_tokens[] = { {SOF_TKN_BUF_SIZE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, offsetof(struct sof_ipc_buffer, size), 0}, + {SOF_TKN_BUF_TYPE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, + offsetof(struct sof_ipc_buffer, type), 0}, }; /* DAI */ @@ -554,8 +556,8 @@ static int sof_widget_load_buffer(struct snd_soc_component *scomp, int index, sof_parse_tokens(scomp, &buffer, buffer_tokens, ARRAY_SIZE(buffer_tokens), private->array, private->size); - dev_dbg(sdev->dev, "buffer %s: size %d\n", - swidget->widget->name, buffer.size); + dev_dbg(sdev->dev, "buffer %s: size %d, type %d\n", + swidget->widget->name, buffer.size, buffer.type); return sof_ipc_tx_message(sdev->ipc, buffer.comp.hdr.cmd, &buffer, sizeof(buffer), r, sizeof(*r)); -- 2.11.0

2 9

[Sound-open-firmware] [PATCH] Audio format: Bug fix for erroneous fractional multiplication macro
by Seppo Ingalsuo 06 Feb '18

06 Feb '18

Due to misplaced parentheses the computation gives half of correct result and omits rounding. Currently this macro is not used by code in SOF git repository. Developers who may use format.h macros should check their code. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo(a)linux.intel.com> --- src/include/reef/audio/format.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/include/reef/audio/format.h b/src/include/reef/audio/format.h index 8964f33..c9c23ec 100644 --- a/src/include/reef/audio/format.h +++ b/src/include/reef/audio/format.h @@ -85,7 +85,8 @@ /* Fractional multiplication with shift and round * Note that the parameters px and py must be cast to (int64_t) if other type. */ -#define Q_MULTSR_32X32(px, py, qx, qy, qp) (((px) * (py) >> (((qx)+(qy)-(qp)-1) +1) >> 1)) +#define Q_MULTSR_32X32(px, py, qx, qy, qp) \ + ((((px) * (py) >> ((qx)+(qy)-(qp)-1)) + 1) >> 1) /* Saturation */ #define SATP_INT32(x) (((x) > INT32_MAX) ? INT32_MAX : (x)) -- 2.11.0

2 1

[Sound-open-firmware] [PATCH] rimage: add check for .bss section
by Xiuli Pan 06 Feb '18

06 Feb '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> We may have heap buffers for base FW, but they are handled by the runtime function. We did not need to set them as bss in FW manifest. So add check to mark the .bss segment as BSS and other segment as HEAP. Then we only update manifest BSS segmet with BSS section. Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- Test with: GP-MRB with NoCodec, Mininow max rt5651 SOF master: 0505823b9667036202758ea950c3ff3347359730 SOF-Tool master: 8c9ebfe9c4f8037b0d0816dedcb87dabef347c6b https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 --- rimage/elf.c | 26 ++++++++++++++++++++------ rimage/rimage.h | 1 + 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/rimage/elf.c b/rimage/elf.c index b912477..1dc48f3 100644 --- a/rimage/elf.c +++ b/rimage/elf.c @@ -27,6 +27,7 @@ static int elf_read_sections(struct image *image, struct module *module) size_t count; int i, ret; uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + int man_section_idx; /* read in section header */ ret = fseek(module->fd, hdr->e_shoff, SEEK_SET); @@ -50,6 +51,16 @@ static int elf_read_sections(struct image *image, struct module *module) return -errno; } + /* find manifest module data */ + man_section_idx = elf_find_section(image, module, ".bss"); + if (man_section_idx < 0) { + return -EINVAL; + } + module->bss_index = man_section_idx; + + fprintf(stdout, " BSS module metadata section at index %d\n", + man_section_idx); + /* parse each section */ for (i = 0; i < hdr->e_shnum; i++) { @@ -211,7 +222,7 @@ int elf_is_rom(struct image *image, Elf32_Shdr *section) } static void elf_module_size(struct image *image, struct module *module, - Elf32_Shdr *section) + Elf32_Shdr *section, int index) { switch (section->sh_type) { case SHT_PROGBITS: @@ -236,12 +247,14 @@ static void elf_module_size(struct image *image, struct module *module, break; case SHT_NOBITS: /* bss */ - if (module->bss_start > section->sh_addr) + if (index == module->bss_index) { + /* updated the .bss segment */ module->bss_start = section->sh_addr; - if (module->bss_end < section->sh_addr + section->sh_size) module->bss_end = section->sh_addr + section->sh_size; - - fprintf(stdout, "\tBSS\n"); + fprintf(stdout, "\tBSS\n"); + } else { + fprintf(stdout, "\tHEAP\n"); + } break; default: break; @@ -282,7 +295,8 @@ static void elf_module_limits(struct image *image, struct module *module) section->sh_size); /* text or data section */ - elf_module_size(image, module, section); + elf_module_size(image, module, section, i); + } fprintf(stdout, "\n"); diff --git a/rimage/rimage.h b/rimage/rimage.h index 84ff93f..a68f1a8 100644 --- a/rimage/rimage.h +++ b/rimage/rimage.h @@ -65,6 +65,7 @@ struct module { int num_sections; int num_bss; int fw_size; + int bss_index; /* sizes do not include any gaps */ int bss_size; -- 2.7.4

2 1

[Sound-open-firmware] SOF master build REMINDER
by Pan, Xiuli 06 Feb '18

06 Feb '18

Reminder for applying this patch! On master branch Please check if you have install sudo apt-get install autoconf-archive And see this line when run ./autogen.sh aclocal: installing 'm4/ax_check_compile_flag.m4' from '/usr/share/aclocal/ax_check_compile_flag.m4' or have file 'm4/ax_check_compile_flag.m4' in your git repo. If not you will find these when configure. ./configure: line 3451: syntax error near unexpected token `-msse4.2,' ./configure: line 3451: `AX_CHECK_COMPILE_FLAG(-msse4.2, SSE42_CFLAGS="-DOPS_SSE42 -msse4.2 -ffast-math -ftree-vectorizer-verbose=0",' It seems to be some m4 expand auto check about 'AX_CHECK_COMPILE_FLAG'. If you did no install this macro it will just copy but not expand it in configure file. And then the error will occur. Synced with Keqiao to update CI environment and build guide. Thanks Xiuli >Subject: [Sound-open-firmware] [PATCH v5] build: add library build support for >host platform > >This patch provides library build support for host platform architecture. >It enables creating separate libraries for each SOF audio component. > >Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com>

2 1

[Sound-open-firmware] [PATCH v2] dw-dma: add support for interrupt per channel
by Keyon Jie 06 Feb '18

06 Feb '18

On Apollolake, the interrupt number for different channels of the same controller are different, here add implementation of it: register interrupt handler for each channel, and don't need check channel in its specific handler anymore. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- Update in v2: Fixed checkpatch.pl issues Tested on GP-MRB, SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 src/drivers/dw-dma.c | 247 +++++++++++++++++++++++++++++++++++++------------ src/include/reef/dma.h | 6 ++ 2 files changed, 195 insertions(+), 58 deletions(-) diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index 5501f8e..7a1805e 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -809,6 +809,194 @@ static inline void dw_dma_chan_reload_next(struct dma *dma, int channel, dw_write(dma, DW_DMA_CHAN_EN, CHAN_ENABLE(channel)); } +static void dw_dma_setup(struct dma *dma) +{ + struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data; + int i; + + /* we cannot config DMAC if DMAC has been already enabled by host */ + if (dw_read(dma, DW_DMA_CFG) != 0) + dw_write(dma, DW_DMA_CFG, 0x0); + + /* now check that it's 0 */ + for (i = DW_DMA_CFG_TRIES; i > 0; i--) { + if (dw_read(dma, DW_DMA_CFG) == 0) + goto found; + } + trace_dma_error("eDs"); + return; + +found: + for (i = 0; i < DW_MAX_CHAN; i++) + dw_read(dma, DW_DMA_CHAN_EN); + +#ifdef HAVE_HDDA + /* enable HDDA before DMAC */ + shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH); +#endif + + /* enable the DMA controller */ + dw_write(dma, DW_DMA_CFG, 1); + + /* mask all interrupts for all 8 channels */ + dw_write(dma, DW_MASK_TFR, INT_MASK_ALL); + dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL); + dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL); + dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL); + dw_write(dma, DW_MASK_ERR, INT_MASK_ALL); + +#ifdef DW_FIFO_PARTITION + /* TODO: we cannot config DMA FIFOs if DMAC has been already */ + /* allocate FIFO partitions, 128 bytes for each ch */ + dw_write(dma, DW_FIFO_PART1_LO, 0x100080); + dw_write(dma, DW_FIFO_PART1_HI, 0x100080); + dw_write(dma, DW_FIFO_PART0_HI, 0x100080); + dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26)); + dw_write(dma, DW_FIFO_PART0_LO, 0x100080); +#endif + + /* set channel priorities */ + for (i = 0; i < DW_MAX_CHAN; i++) { +#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL ||\ + defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE + dw_write(dma, DW_CTRL_HIGH(i), + DW_CTLH_CLASS(dp->chan[i].class)); +#elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL + dw_write(dma, DW_CFG_LOW(i), + DW_CFG_CLASS(dp->chan[i].class)); +#endif + } +} + +#ifdef CONFIG_APOLLOLAKE +/* external layer 2 interrupt for dmac */ +static void dw_dma_irq_handler(void *data) +{ + struct dma_int *dma_int = (struct dma_int *)data; + struct dma *dma = dma_int->dma; + struct dma_pdata *p = dma_get_drvdata(dma); + struct dma_sg_elem next; + uint32_t status_tfr = 0, status_block = 0, status_err = 0, status_intr; + uint32_t mask; + int i = dma_int->channel; + + status_intr = dw_read(dma, DW_INTR_STATUS); + if (!status_intr) + trace_dma_error("eDI"); + + trace_dma("irq"); + trace_value(status_intr); + + /* get the source of our IRQ. */ + status_block = dw_read(dma, DW_STATUS_BLOCK); + status_tfr = dw_read(dma, DW_STATUS_TFR); + + /* TODO: handle errors, just clear them atm */ + status_err = dw_read(dma, DW_STATUS_ERR); + if (status_err) { + trace_dma_error("eDi"); + dw_write(dma, DW_CLEAR_ERR, status_err & i); + } + + /* clear interrupts for channel*/ + dw_write(dma, DW_CLEAR_BLOCK, status_block); + dw_write(dma, DW_CLEAR_TFR, status_tfr); + + /* skip if channel is not running */ + if (p->chan[i].status != COMP_STATE_ACTIVE) { + trace_dma_error("eDs"); + return; + } + + mask = 0x1 << i; + +#if DW_USE_HW_LLI + /* end of a LLI block */ + if (status_block & mask && + p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) { + next.src = DMA_RELOAD_LLI; + next.dest = DMA_RELOAD_LLI; + /* will reload lli by default */ + next.size = DMA_RELOAD_LLI; + p->chan[i].cb(p->chan[i].cb_data, + DMA_IRQ_TYPE_BLOCK, &next); + } +#endif + /* end of a transfer */ + if ((status_tfr & mask) && + (p->chan[i].cb_type & DMA_IRQ_TYPE_LLIST)) { + trace_value(status_tfr); + + next.src = DMA_RELOAD_LLI; + next.dest = DMA_RELOAD_LLI; + next.size = DMA_RELOAD_LLI; /* will reload lli by default */ + if (p->chan[i].cb) + p->chan[i].cb(p->chan[i].cb_data, + DMA_IRQ_TYPE_LLIST, &next); + + /* check for reload channel: + * next.size is DMA_RELOAD_END, stop this dma copy; + * next.size > 0 but not DMA_RELOAD_LLI, use next + * element for next copy; + * if we are waiting for pause, pause it; + * otherwise, reload lli + */ + switch (next.size) { + case DMA_RELOAD_END: + p->chan[i].status = COMP_STATE_PREPARE; + break; + case DMA_RELOAD_LLI: + /* reload lli, but let's check if it is paused */ + if (p->chan[i].status != COMP_STATE_PAUSED) + dw_dma_chan_reload_lli(dma, i); + break; + default: + dw_dma_chan_reload_next(dma, i, &next); + break; + } + } +} + +static int dw_dma_probe(struct dma *dma) +{ + struct dma_int *dma_int[DW_MAX_CHAN]; + struct dma_pdata *dw_pdata; + int i; + + /* allocate private data */ + dw_pdata = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(*dw_pdata)); + dma_set_drvdata(dma, dw_pdata); + + spinlock_init(&dma->lock); + + dw_dma_setup(dma); + + /* init work */ + for (i = 0; i < dma->plat_data.channels; i++) { + dw_pdata->chan[i].dma = dma; + dw_pdata->chan[i].channel = i; + dw_pdata->chan[i].status = COMP_STATE_INIT; + + dma_int[i] = rzalloc(RZONE_SYS, RFLAGS_NONE, + sizeof(struct dma_int)); + + dma_int[i]->dma = dma; + dma_int[i]->channel = i; + dma_int[i]->irq = dma->plat_data.irq + + (i << REEF_IRQ_BIT_SHIFT); + + /* register our IRQ handler */ + interrupt_register(dma_int[i]->irq, + dw_dma_irq_handler, + dma_int[i]); + interrupt_enable(dma_int[i]->irq); + } + + return 0; +} + +#else + /* this will probably be called at the end of every period copied */ static void dw_dma_irq_handler(void *data) { @@ -909,64 +1097,6 @@ static void dw_dma_irq_handler(void *data) } } -static void dw_dma_setup(struct dma *dma) -{ - struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data; - int i; - - /* we cannot config DMAC if DMAC has been already enabled by host */ - if (dw_read(dma, DW_DMA_CFG) != 0) - dw_write(dma, DW_DMA_CFG, 0x0); - - /* now check that it's 0 */ - for (i = DW_DMA_CFG_TRIES; i > 0; i--) { - if (dw_read(dma, DW_DMA_CFG) == 0) - goto found; - } - trace_dma_error("eDs"); - return; - -found: - for (i = 0; i < DW_MAX_CHAN; i++) - dw_read(dma, DW_DMA_CHAN_EN); - -#ifdef HAVE_HDDA - /* enable HDDA before DMAC */ - shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH); -#endif - - /* enable the DMA controller */ - dw_write(dma, DW_DMA_CFG, 1); - - /* mask all interrupts for all 8 channels */ - dw_write(dma, DW_MASK_TFR, INT_MASK_ALL); - dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL); - dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL); - dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL); - dw_write(dma, DW_MASK_ERR, INT_MASK_ALL); - -#ifdef DW_FIFO_PARTITION - /* TODO: we cannot config DMA FIFOs if DMAC has been already */ - /* allocate FIFO partitions, 128 bytes for each ch */ - dw_write(dma, DW_FIFO_PART1_LO, 0x100080); - dw_write(dma, DW_FIFO_PART1_HI, 0x100080); - dw_write(dma, DW_FIFO_PART0_HI, 0x100080); - dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26)); - dw_write(dma, DW_FIFO_PART0_LO, 0x100080); -#endif - - /* set channel priorities */ - for (i = 0; i < DW_MAX_CHAN; i++) { -#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \ - || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE - dw_write(dma, DW_CTRL_HIGH(i), DW_CTLH_CLASS(dp->chan[i].class)); -#else - dw_write(dma, DW_CFG_LOW(i), DW_CFG_CLASS(dp->chan[i].class)); -#endif - } - -} - static int dw_dma_probe(struct dma *dma) { struct dma_pdata *dw_pdata; @@ -993,6 +1123,7 @@ static int dw_dma_probe(struct dma *dma) return 0; } +#endif const struct dma_ops dw_dma_ops = { .channel_get = dw_dma_channel_get, diff --git a/src/include/reef/dma.h b/src/include/reef/dma.h index e33adaa..77f8f71 100644 --- a/src/include/reef/dma.h +++ b/src/include/reef/dma.h @@ -128,6 +128,12 @@ struct dma { void *private; }; +struct dma_int { + struct dma *dma; + uint32_t channel; + uint32_t irq; +}; + struct dma *dma_get(int dmac_id); #define dma_set_drvdata(dma, data) \ -- 2.11.0

2 2

[Sound-open-firmware] [PATCH] audio: fix some memcpy argument
by Xiuli Pan 31 Jan '18

31 Jan '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> memcpy argument need void * pointer. Contributor: Luo Xionghu <xionghu.luo(a)intel.com> Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- Test with: Mininow max rt5651 SOF master: 0505823b9667036202758ea950c3ff3347359730 SOF-Tool master: 8c9ebfe9c4f8037b0d0816dedcb87dabef347c6b https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 --- src/audio/dai.c | 2 +- src/audio/eq_fir.c | 2 +- src/audio/eq_iir.c | 2 +- src/audio/host.c | 2 +- src/audio/mixer.c | 2 +- src/audio/src.c | 2 +- src/audio/tone.c | 2 +- src/audio/volume.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/audio/dai.c b/src/audio/dai.c index d19e18a..4015b84 100644 --- a/src/audio/dai.c +++ b/src/audio/dai.c @@ -190,7 +190,7 @@ static struct comp_dev *dai_new(struct sof_ipc_comp *comp) return NULL; dai = (struct sof_ipc_comp_dai *)&dev->comp; - memcpy(dai, ipc_dai, sizeof(struct sof_ipc_comp_dai)); + memcpy((void *)dai, ipc_dai, sizeof(struct sof_ipc_comp_dai)); dd = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*dd)); if (dd == NULL) { diff --git a/src/audio/eq_fir.c b/src/audio/eq_fir.c index 2dfa11c..9628d13 100644 --- a/src/audio/eq_fir.c +++ b/src/audio/eq_fir.c @@ -260,7 +260,7 @@ static struct comp_dev *eq_fir_new(struct sof_ipc_comp *comp) return NULL; eq_fir = (struct sof_ipc_comp_eq_fir *) &dev->comp; - memcpy(eq_fir, ipc_eq_fir, sizeof(struct sof_ipc_comp_eq_fir)); + memcpy((void *)eq_fir, ipc_eq_fir, sizeof(struct sof_ipc_comp_eq_fir)); cd = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*cd)); if (cd == NULL) { diff --git a/src/audio/eq_iir.c b/src/audio/eq_iir.c index eb464af..3742e7a 100644 --- a/src/audio/eq_iir.c +++ b/src/audio/eq_iir.c @@ -261,7 +261,7 @@ static struct comp_dev *eq_iir_new(struct sof_ipc_comp *comp) if (dev == NULL) return NULL; - memcpy(&dev->comp, comp, sizeof(struct sof_ipc_comp_eq_iir)); + memcpy((void *)&dev->comp, comp, sizeof(struct sof_ipc_comp_eq_iir)); cd = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*cd)); if (cd == NULL) { diff --git a/src/audio/host.c b/src/audio/host.c index b3c3c83..30b2d8c 100644 --- a/src/audio/host.c +++ b/src/audio/host.c @@ -242,7 +242,7 @@ static struct comp_dev *host_new(struct sof_ipc_comp *comp) return NULL; host = (struct sof_ipc_comp_host *)&dev->comp; - memcpy(host, ipc_host, sizeof(struct sof_ipc_comp_host)); + memcpy((void *)host, ipc_host, sizeof(struct sof_ipc_comp_host)); hd = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*hd)); if (hd == NULL) { diff --git a/src/audio/mixer.c b/src/audio/mixer.c index e3611d4..26e94d8 100644 --- a/src/audio/mixer.c +++ b/src/audio/mixer.c @@ -93,7 +93,7 @@ static struct comp_dev *mixer_new(struct sof_ipc_comp *comp) return NULL; mixer = (struct sof_ipc_comp_mixer *)&dev->comp; - memcpy(mixer, ipc_mixer, sizeof(struct sof_ipc_comp_mixer)); + memcpy((void *)mixer, ipc_mixer, sizeof(struct sof_ipc_comp_mixer)); md = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*md)); if (md == NULL) { diff --git a/src/audio/src.c b/src/audio/src.c index d494d96..55fa2f8 100644 --- a/src/audio/src.c +++ b/src/audio/src.c @@ -280,7 +280,7 @@ static struct comp_dev *src_new(struct sof_ipc_comp *comp) return NULL; src = (struct sof_ipc_comp_src *) &dev->comp; - memcpy(src, ipc_src, sizeof(struct sof_ipc_comp_src)); + memcpy((void *)src, ipc_src, sizeof(struct sof_ipc_comp_src)); cd = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*cd)); if (cd == NULL) { diff --git a/src/audio/tone.c b/src/audio/tone.c index 581f87e..da8af5e 100644 --- a/src/audio/tone.c +++ b/src/audio/tone.c @@ -411,7 +411,7 @@ static struct comp_dev *tone_new(struct sof_ipc_comp *comp) return NULL; tone = (struct sof_ipc_comp_tone *) &dev->comp; - memcpy(tone, ipc_tone, sizeof(struct sof_ipc_comp_tone)); + memcpy((void *)tone, ipc_tone, sizeof(struct sof_ipc_comp_tone)); cd = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*cd)); if (cd == NULL) { diff --git a/src/audio/volume.c b/src/audio/volume.c index 3b3e2aa..f289226 100644 --- a/src/audio/volume.c +++ b/src/audio/volume.c @@ -370,7 +370,7 @@ static struct comp_dev *volume_new(struct sof_ipc_comp *comp) return NULL; vol = (struct sof_ipc_comp_volume *)&dev->comp; - memcpy(vol, ipc_vol, sizeof(struct sof_ipc_comp_volume)); + memcpy((void *)vol, ipc_vol, sizeof(struct sof_ipc_comp_volume)); cd = rzalloc(RZONE_RUNTIME, RFLAGS_NONE, sizeof(*cd)); if (cd == NULL) { -- 2.7.4

1 0

[Sound-open-firmware] [PATCH] apollolake: probe all valid SSP ports at platform init
by Keyon Jie 29 Jan '18

29 Jan '18

Add macro for apollolake valid SSP ports, and probe all of them at platform init. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- Tested on GP-MRB, SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 src/platform/apollolake/include/platform/platform.h | 2 ++ src/platform/apollolake/platform.c | 14 +++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 4165b95..f7c83e8 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -38,6 +38,8 @@ struct reef; +#define PLATFORM_SSP_COUNT 6 + /* Host page size */ #define HOST_PAGE_SIZE 4096 #define PLATFORM_PAGE_TABLE_SIZE 256 diff --git a/src/platform/apollolake/platform.c b/src/platform/apollolake/platform.c index bb44634..608695a 100644 --- a/src/platform/apollolake/platform.c +++ b/src/platform/apollolake/platform.c @@ -178,7 +178,8 @@ int platform_init(struct reef *reef) { struct dma *dmac0; struct dma *dmac1; - struct dai *ssp2; + struct dai *ssp; + int i; platform_interrupt_init(); @@ -244,9 +245,12 @@ int platform_init(struct reef *reef) /* init SSP ports */ trace_point(TRACE_BOOT_PLATFORM_SSP); - ssp2 = dai_get(SOF_DAI_INTEL_SSP, 4); - if (ssp2 == NULL) - return -ENODEV; - dai_probe(ssp2); + for (i = 0; i < PLATFORM_SSP_COUNT; i++) { + ssp = dai_get(SOF_DAI_INTEL_SSP, i); + if (!ssp) + return -ENODEV; + dai_probe(ssp); + } + return 0; } -- 2.11.0

1 0

[Sound-open-firmware] [PATCH] dw-dma: fix hardware link list mode
by Keyon Jie 29 Jan '18

29 Jan '18

For hardware link list mode, we also need to configure address and config registers for the first link list, here fix it. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- Tested on minnow turbot rt5651, SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 src/audio/dai.c | 3 ++- src/drivers/dw-dma.c | 43 +++++++++++++++++-------------------------- 2 files changed, 19 insertions(+), 27 deletions(-) diff --git a/src/audio/dai.c b/src/audio/dai.c index d19e18a..3a6b9f7 100644 --- a/src/audio/dai.c +++ b/src/audio/dai.c @@ -226,7 +226,8 @@ static struct comp_dev *dai_new(struct sof_ipc_comp *comp) } /* set up callback */ - dma_set_cb(dd->dma, dd->chan, DMA_IRQ_TYPE_LLIST, dai_dma_cb, dev); + dma_set_cb(dd->dma, dd->chan, DMA_IRQ_TYPE_BLOCK | + DMA_IRQ_TYPE_LLIST, dai_dma_cb, dev); dev->state = COMP_STATE_READY; return dev; diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index 8248461..09e441c 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -396,22 +396,11 @@ static int dw_dma_start(struct dma *dma, int channel) #if DW_USE_HW_LLI /* TODO: Revisit: are we using LLP mode or single transfer ? */ - if (p->chan[channel].lli->llp) { - /* LLP mode - only write LLP pointer */ + if (p->chan[channel].lli) { + /* LLP mode - write LLP pointer */ dw_write(dma, DW_LLP(channel), (uint32_t)p->chan[channel].lli); - } else { - /* single transfer */ - dw_write(dma, DW_LLP(channel), 0); - - /* channel needs started from scratch, so write SARn, DARn */ - dw_write(dma, DW_SAR(channel), p->chan[channel].lli->sar); - dw_write(dma, DW_DAR(channel), p->chan[channel].lli->dar); - - /* program CTLn */ - dw_write(dma, DW_CTRL_LOW(channel), p->chan[channel].lli->ctrl_lo); - dw_write(dma, DW_CTRL_HIGH(channel), p->chan[channel].lli->ctrl_hi); } -#else +#endif /* channel needs started from scratch, so write SARn, DARn */ dw_write(dma, DW_SAR(channel), p->chan[channel].lli->sar); dw_write(dma, DW_DAR(channel), p->chan[channel].lli->dar); @@ -419,7 +408,6 @@ static int dw_dma_start(struct dma *dma, int channel) /* program CTLn */ dw_write(dma, DW_CTRL_LOW(channel), p->chan[channel].lli->ctrl_lo); dw_write(dma, DW_CTRL_HIGH(channel), p->chan[channel].lli->ctrl_hi); -#endif /* write channel config */ dw_write(dma, DW_CFG_LOW(channel), p->chan[channel].cfg_lo); @@ -829,6 +817,7 @@ static void dw_dma_irq_handler(void *data) struct dma_sg_elem next; uint32_t status_tfr = 0; uint32_t status_block = 0; + uint32_t status_block_new = 0; uint32_t status_err = 0; uint32_t status_intr; uint32_t mask; @@ -861,10 +850,10 @@ static void dw_dma_irq_handler(void *data) platform_interrupt_clear(dma_irq(dma), pmask); /* confirm IRQ cleared */ - status_block = dw_read(dma, DW_STATUS_BLOCK); - if (status_block) { + status_block_new = dw_read(dma, DW_STATUS_BLOCK); + if (status_block_new) { trace_dma_error("eI2"); - trace_value(status_block); + trace_value(status_block_new); } for (i = 0; i < DW_MAX_CHAN; i++) { @@ -875,6 +864,16 @@ static void dw_dma_irq_handler(void *data) mask = 0x1 << i; +#if DW_USE_HW_LLI + /* end of a LLI block */ + if (status_block & mask && + p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) { + next.src = next.dest = DMA_RELOAD_LLI; + next.size = DMA_RELOAD_LLI; + p->chan[i].cb(p->chan[i].cb_data, + DMA_IRQ_TYPE_BLOCK, &next); + } +#endif /* end of a transfer */ if ((status_tfr & mask) && (p->chan[i].cb_type & DMA_IRQ_TYPE_LLIST)) { @@ -904,14 +903,6 @@ static void dw_dma_irq_handler(void *data) break; } } -#if DW_USE_HW_LLI - /* end of a LLI block */ - if (status_block & mask && - p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) { - p->chan[i].cb(p->chan[i].cb_data, - DMA_IRQ_TYPE_BLOCK); - } -#endif } } -- 2.11.0

2 2

[Sound-open-firmware] [PATCH] dw-dma: add support for interrupt per channel
by Keyon Jie 29 Jan '18

29 Jan '18

On Apollolake, the interrupt number for different channels of the same controller are different, here add implementation of it: register interrupt handler for each channel, and don't need check channel in its specific handler anymore. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- Tested on GP-MRB, SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 src/drivers/dw-dma.c | 244 +++++++++++++++++++++++++++++++++++++------------ src/include/reef/dma.h | 6 ++ 2 files changed, 192 insertions(+), 58 deletions(-) diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index 09e441c..a0782cb 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -809,6 +809,191 @@ static inline void dw_dma_chan_reload_next(struct dma *dma, int channel, dw_write(dma, DW_DMA_CHAN_EN, CHAN_ENABLE(channel)); } +static void dw_dma_setup(struct dma *dma) +{ + struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data; + int i; + + /* we cannot config DMAC if DMAC has been already enabled by host */ + if (dw_read(dma, DW_DMA_CFG) != 0) + dw_write(dma, DW_DMA_CFG, 0x0); + + /* now check that it's 0 */ + for (i = DW_DMA_CFG_TRIES; i > 0; i--) { + if (dw_read(dma, DW_DMA_CFG) == 0) + goto found; + } + trace_dma_error("eDs"); + return; + +found: + for (i = 0; i < DW_MAX_CHAN; i++) + dw_read(dma, DW_DMA_CHAN_EN); + +#ifdef HAVE_HDDA + /* enable HDDA before DMAC */ + shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH); +#endif + + /* enable the DMA controller */ + dw_write(dma, DW_DMA_CFG, 1); + + /* mask all interrupts for all 8 channels */ + dw_write(dma, DW_MASK_TFR, INT_MASK_ALL); + dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL); + dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL); + dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL); + dw_write(dma, DW_MASK_ERR, INT_MASK_ALL); + +#ifdef DW_FIFO_PARTITION + /* TODO: we cannot config DMA FIFOs if DMAC has been already */ + /* allocate FIFO partitions, 128 bytes for each ch */ + dw_write(dma, DW_FIFO_PART1_LO, 0x100080); + dw_write(dma, DW_FIFO_PART1_HI, 0x100080); + dw_write(dma, DW_FIFO_PART0_HI, 0x100080); + dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26)); + dw_write(dma, DW_FIFO_PART0_LO, 0x100080); +#endif + + /* set channel priorities */ + for (i = 0; i < DW_MAX_CHAN; i++) { +#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL ||\ + defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE + dw_write(dma, DW_CTRL_HIGH(i), + DW_CTLH_CLASS(dp->chan[i].class)); +#elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL + dw_write(dma, DW_CFG_LOW(i), + DW_CFG_CLASS(dp->chan[i].class)); +#endif + } +} + +#ifdef CONFIG_APOLLOLAKE +/* external layer 2 interrupt for dmac */ +static void dw_dma_irq_handler(void *data) +{ + struct dma_int *dma_int = (struct dma_int *)data; + struct dma *dma = dma_int->dma; + struct dma_pdata *p = dma_get_drvdata(dma); + struct dma_sg_elem next; + uint32_t status_tfr = 0, status_block = 0, status_err = 0, status_intr; + uint32_t mask; + int i = dma_int->channel; + + status_intr = dw_read(dma, DW_INTR_STATUS); + if (!status_intr) + trace_dma_error("eDI"); + + trace_dma("irq"); + trace_value(status_intr); + + /* get the source of our IRQ. */ + status_block = dw_read(dma, DW_STATUS_BLOCK); + status_tfr = dw_read(dma, DW_STATUS_TFR); + + /* TODO: handle errors, just clear them atm */ + status_err = dw_read(dma, DW_STATUS_ERR); + if (status_err) { + trace_dma_error("eDi"); + dw_write(dma, DW_CLEAR_ERR, status_err & i); + } + + /* clear interrupts for channel*/ + dw_write(dma, DW_CLEAR_BLOCK, status_block); + dw_write(dma, DW_CLEAR_TFR, status_tfr); + + /* skip if channel is not running */ + if (p->chan[i].status != COMP_STATE_ACTIVE) { + trace_dma_error("eDs"); + return; + } + + mask = 0x1 << i; + +#if DW_USE_HW_LLI + /* end of a LLI block */ + if (status_block & mask && + p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) { + next.src = next.dest = DMA_RELOAD_LLI; + /* will reload lli by default */ + next.size = DMA_RELOAD_LLI; + p->chan[i].cb(p->chan[i].cb_data, + DMA_IRQ_TYPE_BLOCK, &next); + } +#endif + /* end of a transfer */ + if ((status_tfr & mask) && + (p->chan[i].cb_type & DMA_IRQ_TYPE_LLIST)) { + trace_value(status_tfr); + + next.src = next.dest = DMA_RELOAD_LLI; + next.size = DMA_RELOAD_LLI; /* will reload lli by default */ + if (p->chan[i].cb) + p->chan[i].cb(p->chan[i].cb_data, + DMA_IRQ_TYPE_LLIST, &next); + + /* check for reload channel: + * next.size is DMA_RELOAD_END, stop this dma copy; + * next.size > 0 but not DMA_RELOAD_LLI, use next + * element for next copy; + * if we are waiting for pause, pause it; + * otherwise, reload lli + */ + switch (next.size) { + case DMA_RELOAD_END: + p->chan[i].status = COMP_STATE_PREPARE; + break; + case DMA_RELOAD_LLI: + /* reload lli, but let's check if it is paused */ + if (p->chan[i].status != COMP_STATE_PAUSED) + dw_dma_chan_reload_lli(dma, i); + break; + default: + dw_dma_chan_reload_next(dma, i, &next); + break; + } + } +} + +static int dw_dma_probe(struct dma *dma) +{ + struct dma_int *dma_int[DW_MAX_CHAN]; + struct dma_pdata *dw_pdata; + int i; + + /* allocate private data */ + dw_pdata = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(*dw_pdata)); + dma_set_drvdata(dma, dw_pdata); + + spinlock_init(&dma->lock); + + dw_dma_setup(dma); + + /* init work */ + for (i = 0; i < dma->plat_data.channels; i++) { + dw_pdata->chan[i].dma = dma; + dw_pdata->chan[i].channel = i; + dw_pdata->chan[i].status = COMP_STATE_INIT; + + dma_int[i] = rzalloc(RZONE_SYS, RFLAGS_NONE, + sizeof(struct dma_int)); + + dma_int[i]->dma = dma; + dma_int[i]->channel = i; + dma_int[i]->irq = dma->plat_data.irq + + (i << REEF_IRQ_BIT_SHIFT); + + /* register our IRQ handler */ + interrupt_register(dma_int[i]->irq, + dw_dma_irq_handler, dma_int[i]); + interrupt_enable(dma_int[i]->irq); + } + + return 0; +} + +#else + /* this will probably be called at the end of every period copied */ static void dw_dma_irq_handler(void *data) { @@ -906,64 +1091,6 @@ static void dw_dma_irq_handler(void *data) } } -static void dw_dma_setup(struct dma *dma) -{ - struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data; - int i; - - /* we cannot config DMAC if DMAC has been already enabled by host */ - if (dw_read(dma, DW_DMA_CFG) != 0) - dw_write(dma, DW_DMA_CFG, 0x0); - - /* now check that it's 0 */ - for (i = DW_DMA_CFG_TRIES; i > 0; i--) { - if (dw_read(dma, DW_DMA_CFG) == 0) - goto found; - } - trace_dma_error("eDs"); - return; - -found: - for (i = 0; i < DW_MAX_CHAN; i++) - dw_read(dma, DW_DMA_CHAN_EN); - -#ifdef HAVE_HDDA - /* enable HDDA before DMAC */ - shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH); -#endif - - /* enable the DMA controller */ - dw_write(dma, DW_DMA_CFG, 1); - - /* mask all interrupts for all 8 channels */ - dw_write(dma, DW_MASK_TFR, INT_MASK_ALL); - dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL); - dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL); - dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL); - dw_write(dma, DW_MASK_ERR, INT_MASK_ALL); - -#ifdef DW_FIFO_PARTITION - /* TODO: we cannot config DMA FIFOs if DMAC has been already */ - /* allocate FIFO partitions, 128 bytes for each ch */ - dw_write(dma, DW_FIFO_PART1_LO, 0x100080); - dw_write(dma, DW_FIFO_PART1_HI, 0x100080); - dw_write(dma, DW_FIFO_PART0_HI, 0x100080); - dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26)); - dw_write(dma, DW_FIFO_PART0_LO, 0x100080); -#endif - - /* set channel priorities */ - for (i = 0; i < DW_MAX_CHAN; i++) { -#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \ - || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE - dw_write(dma, DW_CTRL_HIGH(i), DW_CTLH_CLASS(dp->chan[i].class)); -#else - dw_write(dma, DW_CFG_LOW(i), DW_CFG_CLASS(dp->chan[i].class)); -#endif - } - -} - static int dw_dma_probe(struct dma *dma) { struct dma_pdata *dw_pdata; @@ -990,6 +1117,7 @@ static int dw_dma_probe(struct dma *dma) return 0; } +#endif const struct dma_ops dw_dma_ops = { .channel_get = dw_dma_channel_get, diff --git a/src/include/reef/dma.h b/src/include/reef/dma.h index e33adaa..77f8f71 100644 --- a/src/include/reef/dma.h +++ b/src/include/reef/dma.h @@ -128,6 +128,12 @@ struct dma { void *private; }; +struct dma_int { + struct dma *dma; + uint32_t channel; + uint32_t irq; +}; + struct dma *dma_get(int dmac_id); #define dma_set_drvdata(dma, data) \ -- 2.11.0

2 2

[Sound-open-firmware] fix rimage coding grammer issues.
by xionghu.luo＠linux.intel.com 28 Jan '18

28 Jan '18

From: Luo Xionghu <xionghu.luo(a)intel.com> this patchset fixes the missing logic checks in rimage. TODO: is tested on hardware needed? Luo Xionghu (3): rimage: don't add date to css if date is NULL. rimage: add return for non-void function. rimge: initial the char array. rimage/css.c | 3 +++ rimage/pkcs1_5.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) -- 2.11.0

4 7

[Sound-open-firmware] [PATCH v5] build: add library build support for host platform
by Ranjani Sridharan 27 Jan '18

27 Jan '18

This patch provides library build support for host platform architecture. It enables creating separate libraries for each SOF audio component. Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- Makefile.am | 15 +- README | 7 + build-all.sh | 4 + configure.ac | 107 +++- src/Makefile.am | 11 + src/arch/Makefile.am | 4 + src/arch/host/Makefile.am | 1 + src/arch/host/include/Makefile.am | 1 + src/arch/host/include/arch/Makefile.am | 9 + src/arch/host/include/arch/cache.h | 43 ++ src/arch/host/include/arch/interrupt.h | 56 ++ src/arch/host/include/arch/reef.h | 41 ++ src/arch/host/include/arch/spinlock.h | 46 ++ src/arch/host/include/arch/timer.h | 52 ++ src/arch/host/include/arch/wait.h | 34 + src/arch/xtensa/Makefile.am | 4 +- src/audio/Makefile.am | 1011 +++++++++++++++++++++++++++++- src/include/reef/Makefile.am | 6 +- src/include/reef/audio/Makefile.am | 8 +- src/include/uapi/Makefile.am | 2 +- src/ipc/Makefile.am | 37 +- src/library/Makefile.am | 1 + src/library/include/Makefile.am | 1 + src/library/include/platform/Makefile.am | 12 + src/library/include/platform/clk.h | 42 ++ src/library/include/platform/dma.h | 42 ++ src/library/include/platform/interrupt.h | 78 +++ src/library/include/platform/mailbox.h | 72 +++ src/library/include/platform/memory.h | 87 +++ src/library/include/platform/platform.h | 54 ++ src/library/include/platform/pmc.h | 41 ++ src/library/include/platform/shim.h | 40 ++ src/library/include/platform/timer.h | 54 ++ src/math/Makefile.am | 22 +- 34 files changed, 2004 insertions(+), 41 deletions(-) create mode 100644 src/arch/host/Makefile.am create mode 100644 src/arch/host/include/Makefile.am create mode 100644 src/arch/host/include/arch/Makefile.am create mode 100644 src/arch/host/include/arch/cache.h create mode 100644 src/arch/host/include/arch/interrupt.h create mode 100644 src/arch/host/include/arch/reef.h create mode 100644 src/arch/host/include/arch/spinlock.h create mode 100644 src/arch/host/include/arch/timer.h create mode 100644 src/arch/host/include/arch/wait.h create mode 100644 src/library/Makefile.am create mode 100644 src/library/include/Makefile.am create mode 100644 src/library/include/platform/Makefile.am create mode 100644 src/library/include/platform/clk.h create mode 100644 src/library/include/platform/dma.h create mode 100644 src/library/include/platform/interrupt.h create mode 100644 src/library/include/platform/mailbox.h create mode 100644 src/library/include/platform/memory.h create mode 100644 src/library/include/platform/platform.h create mode 100644 src/library/include/platform/pmc.h create mode 100644 src/library/include/platform/shim.h create mode 100644 src/library/include/platform/timer.h diff --git a/Makefile.am b/Makefile.am index c05f042..82ad39e 100644 --- a/Makefile.am +++ b/Makefile.am @@ -6,6 +6,19 @@ EXTRA_DIST = version.sh SRC_DIR = $(abs_top_builddir)/src +if BUILD_HOST +export ARCH_INCDIR = \ + -I $(SRC_DIR)/arch/$(ARCH)/include + +export REEF_INCDIR = \ + -I $(SRC_DIR)/include + +if BUILD_LIB +export PLATFORM_INCDIR = \ + -I $(SRC_DIR)/library/include +endif + +else export REEF_INCDIR = \ -I $(SRC_DIR)/include \ -I $(ROOT_DIR)/include @@ -13,9 +26,9 @@ export REEF_INCDIR = \ export ARCH_INCDIR = \ -I $(SRC_DIR)/arch/$(ARCH)/include \ -I $(SRC_DIR)/arch/$(ARCH)/xtos - export PLATFORM_INCDIR = \ -I $(SRC_DIR)/platform/$(PLATFORM)/include +endif dist-hook: ./version.sh $(top_srcdir) diff --git a/README b/README index 9ca5b12..463fc42 100644 --- a/README +++ b/README @@ -13,6 +13,13 @@ Cherrytrail :- ./configure --with-arch=xtensa --with-platform=cherrytrail --with-root-dir=$PWD/../xtensa-root/xtensa-byt-elf --host=xtensa-byt-elf +Library for Host Platform :- +If building library for host platform, run the following configure. Please modify +the --prefix option to choose the directory for installing the library files and +headers + +./configure --with-arch=host --enable-library=yes --host=x86_64-unknown-linux-gnu --prefix=$pwd/../host-root/ + 3) make 4) make bin diff --git a/build-all.sh b/build-all.sh index 6035c66..ce719e9 100755 --- a/build-all.sh +++ b/build-all.sh @@ -33,6 +33,10 @@ make clean make make bin +# Build library for host platform architecture +./configure --with-arch=host --enable-library=yes --host=x86_64-unknown-linux-gnu --prefix=$pwd/../host-root/ +make +make install # list all the images ls -l src/arch/xtensa/*.ri diff --git a/configure.ac b/configure.ac index d37fc67..05a3bee 100644 --- a/configure.ac +++ b/configure.ac @@ -29,10 +29,13 @@ AC_SUBST(ASFLAGS) AC_ARG_WITH([root-dir], AS_HELP_STRING([--with-root-dir], [Specify location of cross gcc libraries and headers]), [], [with_root_dir=no]) -AS_IF([test "x$with_root_dir" = xno], - AC_MSG_ERROR([Please specify cross compiler root header directory]), - [ROOT_DIR=$with_root_dir]) -AC_SUBST(ROOT_DIR) + +# check if we are building FW image or library +AC_ARG_ENABLE(library, [AS_HELP_STRING([--enable-library],[build library])], have_library=$enableval, have_library=no) +if test "$have_library" = "yes"; then + AC_DEFINE([CONFIG_LIB], [1], [Configure for Shared Library]) +fi +AM_CONDITIONAL(BUILD_LIB, test "$have_library" = "yes") # Architecture support AC_ARG_WITH([arch], @@ -57,6 +60,23 @@ case "$with_arch" in ARCH="xtensa" AC_SUBST(ARCH) + + AS_IF([test "x$with_root_dir" = xno], + AC_MSG_ERROR([Please specify cross compiler root header directory]), + [ROOT_DIR=$with_root_dir]) + AC_SUBST(ROOT_DIR) + ;; + host*) + + ARCH_CFLAGS="-g" + AC_SUBST(ARCH_CFLAGS) + + # extra CFLAGS defined here otherwise configure working gcc tests fails. + CFLAGS="${CFLAGS:+$CFLAGS } -O3" + LDFLAGS="${LDFLAGS:+$LDFLAGS }-lpthread" + + ARCH="host" + AC_SUBST(ARCH) ;; *) AC_MSG_ERROR([DSP architecture not specified]) @@ -64,7 +84,7 @@ case "$with_arch" in esac AM_CONDITIONAL(BUILD_XTENSA, test "$ARCH" = "xtensa") - +AM_CONDITIONAL(BUILD_HOST, test "$ARCH" = "host") # Platform support AC_ARG_WITH([platform], @@ -175,7 +195,12 @@ case "$with_platform" in AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps]) ;; *) - AC_MSG_ERROR([Host platform not specified]) + if test "$ARCH" = "host"; then + PLATFORM="host" + AC_SUBST(PLATFORM) + else + AC_MSG_ERROR([Host platform not specified]) + fi ;; esac @@ -215,6 +240,70 @@ AM_CONDITIONAL(BUILD_DMA_TRACE, test "x$enable_dma_trace" != "xno") PLATFORM_BOOT_LDR_LDSCRIPT="boot_ldr.x" AC_SUBST(PLATFORM_BOOT_LDR_LDSCRIPT) +# Optimisation settings and checks + +# SSE4_2 support +AC_ARG_ENABLE(sse42, [AS_HELP_STRING([--enable-sse42],[enable SSE42 optimizations])], have_sse42=$enableval, have_sse42=yes) +AX_CHECK_COMPILE_FLAG(-msse4.2, [SSE42_CFLAGS="-DOPS_SSE42 -msse4.2 -ffast-math -ftree-vectorizer-verbose=0"], + [have_sse42=no]) +if test "$have_sse42" = "yes"; then + AC_DEFINE(HAVE_SSE42,1,[Define to enable SSE42 optimizations.]) +fi +AM_CONDITIONAL(HAVE_SSE42, test "$have_sse42" = "yes") +AC_SUBST(SSE42_CFLAGS) + +# AVX support +AC_ARG_ENABLE(avx, [AS_HELP_STRING([--enable-avx],[enable AVX optimizations])], have_avx=$enableval, have_avx=yes) +AX_CHECK_COMPILE_FLAG(-mavx, [AVX_CFLAGS="-DOPS_AVX -mavx -ffast-math -ftree-vectorizer-verbose=0"], + [have_avx=no]) +if test "$have_avx" = "yes"; then + AC_DEFINE(HAVE_AVX,1,[Define to enable AVX optimizations.]) +fi +AM_CONDITIONAL(HAVE_AVX, test "$have_avx" = "yes") +AC_SUBST(AVX_CFLAGS) + + +# AVX2 support +AC_ARG_ENABLE(avx2, [AS_HELP_STRING([--enable-avx2],[enable AVX2 optimizations])], have_avx2=$enableval, have_avx2=yes) +AX_CHECK_COMPILE_FLAG(-mavx2, [AVX2_CFLAGS="-DOPS_AVX2 -mavx2 -ffast-math -ftree-vectorizer-verbose=0"], + [have_avx2=no]) +if test "$have_avx2" = "yes"; then + AC_DEFINE(HAVE_AVX2,1,[Define to enable AVX2 optimizations.]) +fi +AM_CONDITIONAL(HAVE_AVX2, test "$have_avx2" = "yes") +AC_SUBST(AVX2_CFLAGS) + + +# FMA support +AC_ARG_ENABLE(fma, [AS_HELP_STRING([--enable-fma],[enable FMA optimizations])], have_fma=$enableval, have_fma=yes) +AX_CHECK_COMPILE_FLAG(-mfma, [FMA_CFLAGS="-DOPS_FMA -mfma -ffast-math -ftree-vectorizer-verbose=0"], + [have_fma=no]) +if test "$have_fma" = "yes"; then + AC_DEFINE(HAVE_FMA,1,[Define to enable FMA optimizations.]) +fi +AM_CONDITIONAL(HAVE_FMA, test "$have_fma" = "yes") +AC_SUBST(FMA_CFLAGS) + +# Hifi2EP +AC_ARG_ENABLE(hifi2ep, [AS_HELP_STRING([--enable-hifi2ep],[enable HiFi2EP optimizations])], have_hifi2ep=$enableval, have_hifi2ep=yes) +AX_CHECK_COMPILE_FLAG(-mhifi2ep, [FMA_CFLAGS="-DOPS_HIFI2EP -mhifi2ep -ffast-math -ftree-vectorizer-verbose=0"], + [have_hifi2ep=no]) +if test "$have_hifi2ep" = "yes"; then + AC_DEFINE(HAVE_HIFI2EP,1,[Define to enable Hifi2 EP optimizations.]) +fi +AM_CONDITIONAL(HAVE_HIFI2EP, test "$have_hifi2ep" = "yes") +AC_SUBST(HIFI2EP_CFLAGS) + +# Hifi3 +AC_ARG_ENABLE(hifi3, [AS_HELP_STRING([--enable-hifi3],[enable HiFi3 optimizations])], have_hifi3=$enableval, have_hifi3=yes) +AX_CHECK_COMPILE_FLAG(-mhihi3, [FMA_CFLAGS="-DOPS_HIFI3 -mhifi3 -ffast-math -ftree-vectorizer-verbose=0"], + [have_hifi3=no]) +if test "$have_hifi3" = "yes"; then + AC_DEFINE(HAVE_HIFI3,1,[Define to enable Hifi3 optimizations.]) +fi +AM_CONDITIONAL(HAVE_HIFI3, test "$have_hifi3" = "yes") +AC_SUBST(HIFI3_CFLAGS) + # Test after CFLAGS set othewise test of cross compiler fails. AM_PROG_AS AM_PROG_AR @@ -240,6 +329,9 @@ AC_CONFIG_FILES([ src/arch/xtensa/include/xtensa/config/Makefile src/arch/xtensa/hal/Makefile src/arch/xtensa/xtos/Makefile + src/arch/host/Makefile + src/arch/host/include/Makefile + src/arch/host/include/arch/Makefile src/audio/Makefile src/math/Makefile src/drivers/Makefile @@ -251,6 +343,9 @@ AC_CONFIG_FILES([ src/include/reef/math/Makefile src/include/uapi/Makefile src/ipc/Makefile + src/library/Makefile + src/library/include/Makefile + src/library/include/platform/Makefile src/lib/Makefile src/platform/Makefile src/platform/baytrail/Makefile diff --git a/src/Makefile.am b/src/Makefile.am index fb82330..291d45e 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -1 +1,12 @@ +export COMMON_INCDIR = \ + $(REEF_INCDIR) \ + $(ARCH_INCDIR) \ + $(PLATFORM_INCDIR) + +if BUILD_LIB +SUBDIRS = ipc math audio arch include library +endif + +if BUILD_XTENSA SUBDIRS = include init math audio platform tasks drivers ipc lib arch +endif diff --git a/src/arch/Makefile.am b/src/arch/Makefile.am index d0d1b15..e924254 100644 --- a/src/arch/Makefile.am +++ b/src/arch/Makefile.am @@ -1,3 +1,7 @@ if BUILD_XTENSA SUBDIRS = xtensa endif + +if BUILD_HOST +SUBDIRS = host +endif diff --git a/src/arch/host/Makefile.am b/src/arch/host/Makefile.am new file mode 100644 index 0000000..7b92e00 --- /dev/null +++ b/src/arch/host/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = include diff --git a/src/arch/host/include/Makefile.am b/src/arch/host/include/Makefile.am new file mode 100644 index 0000000..f0ac9b7 --- /dev/null +++ b/src/arch/host/include/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = arch diff --git a/src/arch/host/include/arch/Makefile.am b/src/arch/host/include/arch/Makefile.am new file mode 100644 index 0000000..bedfa1e --- /dev/null +++ b/src/arch/host/include/arch/Makefile.am @@ -0,0 +1,9 @@ +includedir = $(prefix)/include/sof/arch + +include_HEADERS = \ + cache.h \ + interrupt.h \ + reef.h \ + spinlock.h \ + timer.h \ + wait.h diff --git a/src/arch/host/include/arch/cache.h b/src/arch/host/include/arch/cache.h new file mode 100644 index 0000000..e64a6c5 --- /dev/null +++ b/src/arch/host/include/arch/cache.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __INCLUDE_ARCH_CACHE__ +#define __INCLUDE_ARCH_CACHE__ + +#include <stdint.h> +#include <stddef.h> + +static inline void dcache_writeback_region(void *addr, size_t size) {} +static inline void dcache_invalidate_region(void *addr, size_t size) {} +static inline void icache_invalidate_region(void *addr, size_t size) {} +static inline void dcache_writeback_invalidate_region(void *addr, + size_t size) {} + +#endif diff --git a/src/arch/host/include/arch/interrupt.h b/src/arch/host/include/arch/interrupt.h new file mode 100644 index 0000000..b2bb686 --- /dev/null +++ b/src/arch/host/include/arch/interrupt.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __ARCH_INTERRUPT_H +#define __ARCH_INTERRUPT_H + +#include <reef/interrupt-map.h> +#include <stdint.h> +#include <stdlib.h> +#include <unistd.h> +#include <pthread.h> + +#define PLATFORM_IRQ_CHILDREN 0 + +static inline int arch_interrupt_register(int irq, + void (*handler)(void *arg), void *arg) {return 0; } +static inline void arch_interrupt_unregister(int irq) {} +static inline uint32_t arch_interrupt_enable_mask(uint32_t mask) {return 0; } +static inline uint32_t arch_interrupt_disable_mask(uint32_t mask) {return 0; } +static inline void arch_interrupt_set(int irq) {} +static inline void arch_interrupt_clear(int irq) {} +static inline uint32_t arch_interrupt_get_enabled(void) {return 0; } +static inline uint32_t arch_interrupt_get_status(void) {return 0; } +static inline uint32_t arch_interrupt_global_disable(void) {return 0; } +static inline void arch_interrupt_global_enable(uint32_t flags) {} +static inline int arch_interrupt_init(void) {return 0; } + +#endif diff --git a/src/arch/host/include/arch/reef.h b/src/arch/host/include/arch/reef.h new file mode 100644 index 0000000..29090a2 --- /dev/null +++ b/src/arch/host/include/arch/reef.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __INCLUDE_ARCH_REEF__ +#define __INCLUDE_ARCH_REEF__ + +#include <stdint.h> +#include <stddef.h> + +#define arch_memcpy(dest, src, size) \ + memcpy(dest, src, size) + +#endif diff --git a/src/arch/host/include/arch/spinlock.h b/src/arch/host/include/arch/spinlock.h new file mode 100644 index 0000000..ea59769 --- /dev/null +++ b/src/arch/host/include/arch/spinlock.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __ARCH_SPINLOCK_H_ +#define __ARCH_SPINLOCK_H_ + +#include <stdint.h> +#include <errno.h> +#include <pthread.h> + +typedef struct { +} spinlock_t; + +static inline void arch_spinlock_init(spinlock_t *lock) {} +static inline void arch_spin_lock(spinlock_t *lock) {} +static inline void arch_spin_unlock(spinlock_t *lock) {} + +#endif diff --git a/src/arch/host/include/arch/timer.h b/src/arch/host/include/arch/timer.h new file mode 100644 index 0000000..c650da3 --- /dev/null +++ b/src/arch/host/include/arch/timer.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __ARCH_TIMER_H_ +#define __ARCH_TIMER_H_ + +#include <arch/interrupt.h> +#include <stdint.h> +#include <errno.h> + +struct timer { +}; + +static inline int arch_timer_register(struct timer *timer, + void (*handler)(void *arg), void *arg) {return 0; } +static inline void arch_timer_unregister(struct timer *timer) {} +static inline void arch_timer_enable(struct timer *timer) {} +static inline void arch_timer_disable(struct timer *timer) {} +static inline uint32_t arch_timer_get_system(struct timer *timer) {return 0; } +static inline int arch_timer_set(struct timer *timer, + uint64_t ticks) {return 0; } +static inline void arch_timer_clear(struct timer *timer) {} + +#endif diff --git a/src/arch/host/include/arch/wait.h b/src/arch/host/include/arch/wait.h new file mode 100644 index 0000000..e1e23a1 --- /dev/null +++ b/src/arch/host/include/arch/wait.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +static inline void arch_wait_for_interrupt(int level) {} + +static inline void idelay(int n) {} + diff --git a/src/arch/xtensa/Makefile.am b/src/arch/xtensa/Makefile.am index b055a82..b94d14e 100644 --- a/src/arch/xtensa/Makefile.am +++ b/src/arch/xtensa/Makefile.am @@ -57,9 +57,9 @@ reef_LDADD = \ ../../tasks/libtasks.a \ ../../lib/libcore.a \ ../../platform/$(PLATFORM)/libplatform.a \ - ../../ipc/libipc.a \ + ../../ipc/libsof_ipc.a \ ../../audio/libaudio.a \ - ../../math/libmath.a \ + ../../math/libsof_math.a \ ../../drivers/libdrivers.a \ libreset.a \ xtos/libxtos.a \ diff --git a/src/audio/Makefile.am b/src/audio/Makefile.am index d19dff7..bccedbf 100644 --- a/src/audio/Makefile.am +++ b/src/audio/Makefile.am @@ -1,12 +1,1003 @@ -noinst_LIBRARIES = libaudio.a +includedir = $(prefix)/include/sof/audio -noinst_HEADERS = \ - eq_fir.h \ +include_HEADERS = \ eq_iir.h \ - fir.h \ - iir.h \ - src_config.h \ - src_core.h + eq_fir.h + +COMP_SRC = \ + eq_iir.c \ + iir.c \ + eq_fir.c \ + fir.c \ + tone.c \ + src.c \ + src_core.c \ + mixer.c \ + mux.c \ + volume.c \ + switch.c \ + dai.c \ + host.c \ + pipeline.c \ + component.c \ + buffer.c + +SOF_SRC = \ + dai.c \ + host.c \ + pipeline.c \ + component.c \ + buffer.c + +SRC_SRC = \ + src.c \ + src_core.c + +EQ_FIR_SRC = \ + eq_fir.c \ + fir.c + +EQ_IIR_SRC = \ + eq_iir.c \ + iir.c + +if BUILD_LIB + +# only host builds shared libraries, the rest are static +if BUILD_HOST + +# libsof +lib_LTLIBRARIES = libsof.la + +libsof_la_SOURCES = $(SOF_SRC) + +libsof_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src.la + +libsof_src_la_SOURCES = $(SRC_SRC) + +libsof_src_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir.la + +libsof_eq_fir_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir.la + +libsof_eq_iir_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume.la + +libsof_volume_la_SOURCES = volume.c + +libsof_volume_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux.la + +libsof_mux_la_SOURCES = mux.c + +libsof_mux_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch.la + +libsof_switch_la_SOURCES = switch.c + +libsof_switch_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer.la + +libsof_mixer_la_SOURCES = mixer.c + +libsof_mixer_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone.la + +libsof_tone_la_SOURCES = tone.c + +libsof_tone_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +if HAVE_SSE42 +# libsof +lib_LTLIBRARIES += libsof_sse42.la + +libsof_sse42_la_SOURCES = $(SOF_SRC) + +libsof_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_sse42.la + +libsof_src_sse42_la_SOURCES = $(SRC_SRC) + +libsof_src_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_sse42.la + +libsof_eq_fir_sse42_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_sse42.la + +libsof_eq_iir_sse42_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_sse42.la + +libsof_volume_sse42_la_SOURCES = volume.c + +libsof_volume_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_sse42.la + +libsof_mux_sse42_la_SOURCES = mux.c + +libsof_mux_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_sse42.la + +libsof_switch_sse42_la_SOURCES = switch.c + +libsof_switch_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_sse42.la + +libsof_mixer_sse42_la_SOURCES = mixer.c + +libsof_mixer_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_sse42.la + +libsof_tone_sse42_la_SOURCES = tone.c + +libsof_tone_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic +endif + +if HAVE_AVX +# libsof +lib_LTLIBRARIES += libsof_avx.la + +libsof_avx_la_SOURCES = $(SOF_SRC) + +libsof_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_avx.la + +libsof_src_avx_la_SOURCES = $(SRC_SRC) + +libsof_src_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_avx.la + +libsof_eq_fir_avx_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_avx.la + +libsof_eq_iir_avx_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_avx.la + +libsof_volume_avx_la_SOURCES = volume.c + +libsof_volume_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_avx.la + +libsof_mux_avx_la_SOURCES = mux.c + +libsof_mux_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_avx.la + +libsof_switch_avx_la_SOURCES = switch.c + +libsof_switch_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_avx.la + +libsof_mixer_avx_la_SOURCES = mixer.c + +libsof_mixer_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_avx.la + +libsof_tone_avx_la_SOURCES = tone.c + +libsof_tone_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic +endif + +if HAVE_AVX2 +# libsof +lib_LTLIBRARIES += libsof_avx2.la + +libsof_avx2_la_SOURCES = $(SOF_SRC) + +libsof_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_avx2.la + +libsof_src_avx2_la_SOURCES = $(SRC_SRC) + +libsof_src_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_avx2.la + +libsof_eq_fir_avx2_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_avx2.la + +libsof_eq_iir_avx2_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_avx2.la + +libsof_volume_avx2_la_SOURCES = volume.c + +libsof_volume_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_avx2.la + +libsof_mux_avx2_la_SOURCES = mux.c + +libsof_mux_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_avx2.la + +libsof_switch_avx2_la_SOURCES = switch.c + +libsof_switch_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_avx2.la + +libsof_mixer_avx2_la_SOURCES = mixer.c + +libsof_mixer_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_avx2.la + +libsof_tone_avx2_la_SOURCES = tone.c + +libsof_tone_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +endif + +if HAVE_FMA +# libsof +lib_LTLIBRARIES += libsof_fma.la + +libsof_fma_la_SOURCES = $(SOF_SRC) + +libsof_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_fma.la + +libsof_src_fma_la_SOURCES = $(SRC_SRC) + +libsof_src_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_fma.la + +libsof_eq_fir_fma_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_fma.la + +libsof_eq_iir_fma_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_fma.la + +libsof_volume_fma_la_SOURCES = volume.c + +libsof_volume_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_fma.la + +libsof_mux_fma_la_SOURCES = mux.c + +libsof_mux_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_fma.la + +libsof_switch_fma_la_SOURCES = switch.c + +libsof_switch_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_fma.la + +libsof_mixer_fma_la_SOURCES = mixer.c + +libsof_mixer_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_fma.la + +libsof_tone_fma_la_SOURCES = tone.c + +libsof_tone_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic +endif + +else + +# Build for non host targets + +# libsof +lib_LIBRARIES = libsof.a + +libsof_a_SOURCES = $(SOF_SRC) + +libsof_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_src +lib_LIBRARIES += libsof_src.a + +libsof_src_a_SOURCES = $(SRC_SRC) + +libsof_src_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_fir +lib_LIBRARIES += libsof_eq_fir.a + +libsof_eq_fir_a_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_iir +lib_LIBRARIES += libsof_eq_iir.a + +libsof_eq_iir_a_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_volume +lib_LIBRARIES += libsof_volume.a + +libsof_volume_a_SOURCES = volume.c + +libsof_volume_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mux +lib_LIBRARIES += libsof_mux.a + +libsof_mux_a_SOURCES = mux.c + +libsof_mux_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_switch +lib_LIBRARIES += libsof_switch.a + +libsof_switch_a_SOURCES = switch.c + +libsof_switch_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mixer +lib_LIBRARIES += libsof_mixer.a + +libsof_mixer_a_SOURCES = mixer.c + +libsof_mixer_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_tone +lib_LIBRARIES += libsof_tone.a + +libsof_tone_a_SOURCES = tone.c + +libsof_tone_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + + +if HAVE_HIFI2EP +# libsof +lib_LIBRARIES += libsof_hifi2ep.a + +libsof_hifi2ep_a_SOURCES = $(SOF_SRC) + +libsof_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_src +lib_LIBRARIES += libsof_src_hifi2ep.a + +libsof_src_hifi2ep_a_SOURCES = $(SRC_SRC) + +libsof_src_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_fir +lib_LIBRARIES += libsof_eq_fir_hifi2ep.a + +libsof_eq_fir_hifi2ep_a_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_iir +lib_LIBRARIES += libsof_eq_iir_hifi2ep.a + +libsof_eq_iir_hifi2ep_a_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_volume +lib_LIBRARIES += libsof_volume_hifi2ep.a + +libsof_volume_hifi2ep_a_SOURCES = volume.c + +libsof_volume_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mux +lib_LIBRARIES += libsof_mux_hifi2ep.a + +libsof_mux_hifi2ep_a_SOURCES = mux.c + +libsof_mux_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_switch +lib_LIBRARIES += libsof_switch_hifi2ep.a + +libsof_switch_hifi2ep_a_SOURCES = switch.c + +libsof_switch_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mixer +lib_LIBRARIES += libsof_mixer_hifi2ep.a + +libsof_mixer_hifi2ep_a_SOURCES = mixer.c + +libsof_mixer_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_tone +lib_LIBRARIES += libsof_tone_hifi2ep.a + +libsof_tone_hifi2ep_a_SOURCES = tone.c + +libsof_tone_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) +endif + +if HAVE_HIFI3 +# libsof +lib_LIBRARIES += libsof_hifi3.a + +libsof_hifi3_a_SOURCES = $(COMP_SRC) + +libsof_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_src +lib_LIBRARIES += libsof_src_hifi3.a + +libsof_src_hifi3_a_SOURCES = $(SRC_SRC) + +libsof_src_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_fir +lib_LIBRARIES += libsof_eq_fir_hifi3.a + +libsof_eq_fir_hifi3_a_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_iir +lib_LIBRARIES += libsof_eq_iir_hifi3.a + +libsof_eq_iir_hifi3_a_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_volume +lib_LIBRARIES += libsof_volume_hifi3.a + +libsof_volume_hifi3_a_SOURCES = volume.c + +libsof_volume_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mux +lib_LIBRARIES += libsof_mux_hifi3.a + +libsof_mux_hifi3_a_SOURCES = mux.c + +libsof_mux_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_switch +lib_LIBRARIES += libsof_switch_hifi3.a + +libsof_switch_hifi3_a_SOURCES = switch.c + +libsof_switch_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mixer +lib_LIBRARIES += libsof_mixer_hifi3.a + +libsof_mixer_hifi3_a_SOURCES = mixer.c + +libsof_mixer_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_tone +lib_LIBRARIES += libsof_tone_hifi3.a + +libsof_tone_hifi3_a_SOURCES = tone.c + +libsof_tone_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) +endif + +endif + +else + +# build for firmware image + +noinst_LIBRARIES = libaudio.a libaudio_a_SOURCES = \ eq_iir.c \ @@ -29,6 +1020,6 @@ libaudio_a_SOURCES = \ libaudio_a_CFLAGS = \ $(ARCH_CFLAGS) \ - $(REEF_INCDIR) \ - $(ARCH_INCDIR) \ - $(PLATFORM_INCDIR) + $(COMMON_INCDIR) + +endif diff --git a/src/include/reef/Makefile.am b/src/include/reef/Makefile.am index 50ffada..f4d46f2 100644 --- a/src/include/reef/Makefile.am +++ b/src/include/reef/Makefile.am @@ -1,7 +1,11 @@ SUBDIRS = audio math noinst_HEADERS = \ - agent.h \ + agent.h + +includedir = $(prefix)/include/sof/reef + +include_HEADERS = \ alloc.h \ clock.h \ dai.h \ diff --git a/src/include/reef/audio/Makefile.am b/src/include/reef/audio/Makefile.am index 60b7145..1d2b9cb 100644 --- a/src/include/reef/audio/Makefile.am +++ b/src/include/reef/audio/Makefile.am @@ -1,7 +1,9 @@ SUBDIRS = coefficients -noinst_HEADERS = \ +includedir = $(prefix)/include/sof/reef/audio + +include_HEADERS = \ component.h \ pipeline.h \ - buffer.h \ - format.h + format.h \ + buffer.h diff --git a/src/include/uapi/Makefile.am b/src/include/uapi/Makefile.am index 257fff0..327f97d 100644 --- a/src/include/uapi/Makefile.am +++ b/src/include/uapi/Makefile.am @@ -1,4 +1,4 @@ -includedir = $(prefix)/include/sof +includedir = $(prefix)/include/sof/uapi include_HEADERS = \ ipc.h \ diff --git a/src/ipc/Makefile.am b/src/ipc/Makefile.am index bd83f60..1d84dd0 100644 --- a/src/ipc/Makefile.am +++ b/src/ipc/Makefile.am @@ -1,7 +1,22 @@ -noinst_LIBRARIES = libipc.a +if BUILD_LIB +lib_LTLIBRARIES = libsof_ipc.la + +libsof_ipc_la_SOURCES = \ + ipc.c + +libsof_ipc_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +libsof_ipc_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) +else +noinst_LIBRARIES = libsof_ipc.a if BUILD_BAYTRAIL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ byt-ipc.c \ @@ -10,7 +25,7 @@ libipc_a_SOURCES = \ endif if BUILD_CHERRYTRAIL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ byt-ipc.c \ @@ -19,7 +34,7 @@ libipc_a_SOURCES = \ endif if BUILD_BROADWELL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ hsw-ipc.c \ @@ -27,15 +42,16 @@ libipc_a_SOURCES = \ endif if BUILD_HASWELL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ hsw-ipc.c \ dma-copy.c endif + if BUILD_APOLLOLAKE -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ apl-ipc.c \ @@ -43,16 +59,15 @@ libipc_a_SOURCES = \ endif if BUILD_CANNONLAKE -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ cnl-ipc.c \ dma-copy.c endif -libipc_a_CFLAGS = \ +libsof_ipc_a_CFLAGS = \ $(ARCH_CFLAGS) \ - $(ARCH_INCDIR) \ - $(REEF_INCDIR) \ - $(PLATFORM_INCDIR) + $(COMMON_INCDIR) +endif diff --git a/src/library/Makefile.am b/src/library/Makefile.am new file mode 100644 index 0000000..7b92e00 --- /dev/null +++ b/src/library/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = include diff --git a/src/library/include/Makefile.am b/src/library/include/Makefile.am new file mode 100644 index 0000000..912728c --- /dev/null +++ b/src/library/include/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = platform diff --git a/src/library/include/platform/Makefile.am b/src/library/include/platform/Makefile.am new file mode 100644 index 0000000..5a735ae --- /dev/null +++ b/src/library/include/platform/Makefile.am @@ -0,0 +1,12 @@ +includedir = $(prefix)/include/sof/platform + +include_HEADERS = \ + clk.h \ + dma.h \ + interrupt.h \ + mailbox.h \ + memory.h \ + platform.h \ + pmc.h \ + shim.h \ + timer.h diff --git a/src/library/include/platform/clk.h b/src/library/include/platform/clk.h new file mode 100644 index 0000000..0dd11e6 --- /dev/null +++ b/src/library/include/platform/clk.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_CLOCK__ +#define __PLATFORM_HOST_CLOCK__ + +#define CLK_CPU 0 +#define CLK_SSP 1 + +#define CLK_DEFAULT_CPU_HZ 50000000 +#define CLK_MAX_CPU_HZ 343000000 + +void init_platform_clocks(void); + +#endif diff --git a/src/library/include/platform/dma.h b/src/library/include/platform/dma.h new file mode 100644 index 0000000..457da8a --- /dev/null +++ b/src/library/include/platform/dma.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_DMA_H__ +#define __PLATFORM_HOST_DMA_H__ + +#include <stdint.h> + +#define DMA_ID_DMAC0 0 +#define DMA_ID_DMAC1 1 + +#define DMA_DEV_PCM 0 +#define DMA_DEV_WAV 1 + +#endif diff --git a/src/library/include/platform/interrupt.h b/src/library/include/platform/interrupt.h new file mode 100644 index 0000000..eb0fbfd --- /dev/null +++ b/src/library/include/platform/interrupt.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __INCLUDE_PLATFORM_HOST_INTERRUPT__ +#define __INCLUDE_PLATFORM_HOST_INTERRUPT__ + +#include <stdint.h> +#include <reef/interrupt-map.h> + +/* IRQ numbers */ +#define IRQ_NUM_SOFTWARE0 0 /* Level 1 */ +#define IRQ_NUM_TIMER1 1 /* Level 1 */ +#define IRQ_NUM_SOFTWARE1 2 /* Level 1 */ +#define IRQ_NUM_SOFTWARE2 3 /* Level 1 */ +#define IRQ_NUM_TIMER2 5 /* Level 2 */ +#define IRQ_NUM_SOFTWARE3 6 /* Level 2 */ +#define IRQ_NUM_TIMER3 7 /* Level 3 */ +#define IRQ_NUM_SOFTWARE4 8 /* Level 3 */ +#define IRQ_NUM_SOFTWARE5 9 /* Level 3 */ +#define IRQ_NUM_EXT_IA 10 /* Level 4 */ +#define IRQ_NUM_EXT_PMC 11 /* Level 4 */ +#define IRQ_NUM_SOFTWARE6 12 /* Level 5 */ +#define IRQ_NUM_EXT_DMAC0 13 /* Level 5 */ +#define IRQ_NUM_EXT_DMAC1 14 /* Level 5 */ +#define IRQ_NUM_EXT_TIMER 15 /* Level 5 */ +#define IRQ_NUM_EXT_SSP0 16 /* Level 5 */ +#define IRQ_NUM_EXT_SSP1 17 /* Level 5 */ +#define IRQ_NUM_EXT_SSP2 18 /* Level 5 */ +#define IRQ_NUM_NMI 20 /* Level 7 */ + +/* IRQ Masks */ +#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0) +#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1) +#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1) +#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2) +#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2) +#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3) +#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3) +#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4) +#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5) +#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA) +#define IRQ_MASK_EXT_PMC (1 << IRQ_NUM_EXT_PMC) +#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6) +#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0) +#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1) +#define IRQ_MASK_EXT_TIMER (1 << IRQ_NUM_EXT_TIMER) +#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0) +#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1) +#define IRQ_MASK_EXT_SSP2 (1 << IRQ_NUM_EXT_SSP2) + +#endif diff --git a/src/library/include/platform/mailbox.h b/src/library/include/platform/mailbox.h new file mode 100644 index 0000000..650ab47 --- /dev/null +++ b/src/library/include/platform/mailbox.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __INCLUDE_PLATFORM_HOST_MAILBOX__ +#define __INCLUDE_PLATFORM_HOST_MAILBOX__ + +#include <platform/memory.h> + +#define MAILBOX_HOST_OFFSET 0x144000 + +#define MAILBOX_OUTBOX_OFFSET 0x0 +#define MAILBOX_OUTBOX_SIZE 0x400 +#define MAILBOX_OUTBOX_BASE \ + (MAILBOX_BASE + MAILBOX_OUTBOX_OFFSET) + +#define MAILBOX_INBOX_OFFSET MAILBOX_OUTBOX_SIZE +#define MAILBOX_INBOX_SIZE 0x400 +#define MAILBOX_INBOX_BASE \ + (MAILBOX_BASE + MAILBOX_INBOX_OFFSET) + +#define MAILBOX_EXCEPTION_OFFSET \ + (MAILBOX_INBOX_SIZE + MAILBOX_OUTBOX_SIZE) +#define MAILBOX_EXCEPTION_SIZE 0x100 +#define MAILBOX_EXCEPTION_BASE \ + (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET) + +#define MAILBOX_DEBUG_OFFSET \ + (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET) +#define MAILBOX_DEBUG_SIZE 0x100 +#define MAILBOX_DEBUG_BASE \ + (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET) + +#define MAILBOX_STREAM_OFFSET \ + (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET) +#define MAILBOX_STREAM_SIZE 0x200 +#define MAILBOX_STREAM_BASE \ + (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) + +#define MAILBOX_TRACE_OFFSET \ + (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET) +#define MAILBOX_TRACE_SIZE 0x380 +#define MAILBOX_TRACE_BASE \ + (MAILBOX_BASE + MAILBOX_TRACE_OFFSET) + +#endif diff --git a/src/library/include/platform/memory.h b/src/library/include/platform/memory.h new file mode 100644 index 0000000..78541e7 --- /dev/null +++ b/src/library/include/platform/memory.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_MEMORY_H__ +#define __PLATFORM_HOST_MEMORY_H__ + +#include <config.h> + +#if CONFIG_HT_BAYTRAIL +#include <baytrail/include/platform/memory.h> +#endif + +#define HEAP_BUFFER_SIZE (1024 * 128) + +#if 0 +/* physical DSP addresses */ + +#define IRAM_BASE 0xFF2C0000 +#define IRAM_SIZE 0x00014000 + +#define DRAM0_BASE 0xFF300000 +#define DRAM0_SIZE 0x00028000 +#define DRAM0_VBASE 0xC0000000 + +#define MAILBOX_BASE (DRAM0_BASE + DRAM0_SIZE - 0x2000) + + +/* HEAP Constants - WARNING this MUST be aligned with the linker script */ +/* TODO:preproces linker script with this header to align automatically. */ + +/* Heap section sizes for module pool */ +#define HEAP_MOD_COUNT8 0 +#define HEAP_MOD_COUNT16 256 +#define HEAP_MOD_COUNT32 128 +#define HEAP_MOD_COUNT64 64 +#define HEAP_MOD_COUNT128 32 +#define HEAP_MOD_COUNT256 16 +#define HEAP_MOD_COUNT512 8 +#define HEAP_MOD_COUNT1024 4 + +/* total Heap for modules - must be aligned with linker script !!! */ +#define HEAP_MOD_SIZE \ + (HEAP_MOD_COUNT8 * 8 + HEAP_MOD_COUNT16 * 16 + \ + HEAP_MOD_COUNT32 * 32 + HEAP_MOD_COUNT64 * 64 + \ + HEAP_MOD_COUNT128 * 128 + HEAP_MOD_COUNT256 * 256 + \ + HEAP_MOD_COUNT512 * 512 + HEAP_MOD_COUNT1024 * 1024) + +/* Heap for buffers */ +#define HEAP_BUF_BLOCK_SIZE 1024 +#define HEAP_BUF_COUNT 111 +#define HEAP_BUF_SIZE (HEAP_BUF_BLOCK_SIZE * HEAP_BUF_COUNT) + +/* Remaining DRAM for Stack, data and BSS. + * TODO: verify no overflow during build + */ +#define SYSTEM_MEM \ + (DRAM0_SIZE - HEAP_MOD_SIZE - HEAP_BUF_SIZE) + +#endif +#endif diff --git a/src/library/include/platform/platform.h b/src/library/include/platform/platform.h new file mode 100644 index 0000000..a429e84 --- /dev/null +++ b/src/library/include/platform/platform.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_PLATFORM_H__ +#define __PLATFORM_HOST_PLATFORM_H__ + +#include <platform/shim.h> +#include <platform/interrupt.h> +#include <stdio.h> +#include <stdlib.h> + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 4 +#define PLATFORM_MAX_STREAMS 5 + +/* DMA channel drain timeout in microseconds */ +#define PLATFORM_DMA_TIMEOUT 1333 + +/* IPC page data copy timeout */ +#define PLATFORM_IPC_DMA_TIMEOUT 2000 + + +#endif diff --git a/src/library/include/platform/pmc.h b/src/library/include/platform/pmc.h new file mode 100644 index 0000000..d54fc1c --- /dev/null +++ b/src/library/include/platform/pmc.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_PMC_H__ +#define __PLATFORM_HOST_PMC_H__ + +#include <stdint.h> + + +int platform_ipc_pmc_init(void); +int ipc_pmc_send_msg(uint32_t message); +int pmc_process_msg_queue(void); + +#endif diff --git a/src/library/include/platform/shim.h b/src/library/include/platform/shim.h new file mode 100644 index 0000000..d6d94d4 --- /dev/null +++ b/src/library/include/platform/shim.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_SHIM_H__ +#define __PLATFORM_HOST_SHIM_H__ + +#include <platform/memory.h> +#include <stdint.h> + +static inline uint32_t shim_read(uint32_t reg) {return 0; } +static inline void shim_write(uint32_t reg, uint32_t val) {} + +#endif diff --git a/src/library/include/platform/timer.h b/src/library/include/platform/timer.h new file mode 100644 index 0000000..3521e4c --- /dev/null +++ b/src/library/include/platform/timer.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + + +#ifndef __PLATFORM_HOST_TIMER_H__ +#define __PLATFORM_HOST_TIMER_H__ + +#include <stdint.h> +#include <reef/timer.h> +#include <platform/interrupt.h> + +struct comp_dev; +struct sof_ipc_stream_posn; + +/* get timestamp for host stream DMA position */ +static inline void platform_host_timestamp(struct comp_dev *host, + struct sof_ipc_stream_posn *posn) {} + +/* get timestamp for DAI stream DMA position */ +static inline void platform_dai_timestamp(struct comp_dev *dai, + struct sof_ipc_stream_posn *posn) {} + +/* get current wallclock for componnent */ +static inline void platform_dai_wallclock(struct comp_dev *dai, + uint64_t *wallclock) {} + +#endif diff --git a/src/math/Makefile.am b/src/math/Makefile.am index b795afa..6a48e29 100644 --- a/src/math/Makefile.am +++ b/src/math/Makefile.am @@ -1,11 +1,21 @@ -noinst_LIBRARIES = libmath.a +if BUILD_LIB +lib_LTLIBRARIES = libsof_math.la -libmath_a_SOURCES = \ +libsof_math_la_SOURCES = \ trig.c \ numbers.c -libmath_a_CFLAGS = \ +libsof_math_la_CFLAGS = \ $(ARCH_CFLAGS) \ - $(REEF_INCDIR) \ - $(ARCH_INCDIR) \ - $(PLATFORM_INCDIR) + $(COMMON_INCDIR) +else +noinst_LIBRARIES = libsof_math.a + +libsof_math_a_SOURCES = \ + trig.c \ + numbers.c + +libsof_math_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) +endif -- 2.11.0

2 1

[Sound-open-firmware] [PATCH] topology: test: fix buffer size for volume
by Xiuli Pan 27 Jan '18

27 Jan '18

From: Pan Xiuli <xiuli.pan(a)linux.intel.com> We may have different buffer size around volume. Change the size due to the endpoint setting. Signed-off-by: Pan Xiuli <xiuli.pan(a)linux.intel.com> --- topology/sof/pipe-volume-capture.m4 | 2 +- topology/sof/pipe-volume-playback.m4 | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/topology/sof/pipe-volume-capture.m4 b/topology/sof/pipe-volume-capture.m4 index 258f8fa..8532aa3 100644 --- a/topology/sof/pipe-volume-capture.m4 +++ b/topology/sof/pipe-volume-capture.m4 @@ -53,7 +53,7 @@ W_PGA(0, Master Capture Volume, PIPELINE_FORMAT, 2, 2, 2) W_BUFFER(0, COMP_BUFFER_SIZE(2, COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) # # DAI definitions diff --git a/topology/sof/pipe-volume-playback.m4 b/topology/sof/pipe-volume-playback.m4 index b532161..54bc13d 100644 --- a/topology/sof/pipe-volume-playback.m4 +++ b/topology/sof/pipe-volume-playback.m4 @@ -53,7 +53,7 @@ W_PGA(0, Master Playback Volume, PIPELINE_FORMAT, 2, 2, 2) W_BUFFER(0, COMP_BUFFER_SIZE(2, COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) W_BUFFER(1, COMP_BUFFER_SIZE(2, - COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) + COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES)) # # DAI definitions -- 2.7.4

3 2

[Sound-open-firmware] [PATCH] Fix checkpatch warning.
by yan.wang＠linux.intel.com 27 Jan '18

27 Jan '18

From: Yan Wang <yan.wang(a)linux.intel.com> Fix coding style, typo and dos file format based on checkpatch warning. The checked commits are from f198ad907c5ad14cf7a99129ea8c17f40a632c29 to f7beb51118e6e8463a864b9416c773a508930e06. Signed-off-by: Yan Wang <yan.wang(a)linux.intel.com> --- Tested on minnow max rt5651, SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 --- src/arch/xtensa/boot_entry.S | 2 +- src/arch/xtensa/boot_loader.c | 8 +- src/arch/xtensa/crt1-boards.S | 606 ++++++++++----------- src/arch/xtensa/include/arch/wait.h | 3 +- src/ipc/apl-ipc.c | 4 +- src/ipc/byt-ipc.c | 8 +- src/ipc/cnl-ipc.c | 10 +- src/ipc/hsw-ipc.c | 8 +- src/lib/interrupt.c | 4 +- src/platform/apollolake/include/platform/memory.h | 4 +- .../apollolake/include/platform/platform.h | 2 +- src/platform/apollolake/interrupt.c | 11 +- src/platform/baytrail/include/platform/platform.h | 2 +- .../cannonlake/include/platform/platform.h | 2 +- src/platform/cannonlake/interrupt.c | 11 +- src/platform/cannonlake/platform.c | 4 +- src/platform/haswell/include/platform/platform.h | 2 +- 17 files changed, 343 insertions(+), 348 deletions(-) diff --git a/src/arch/xtensa/boot_entry.S b/src/arch/xtensa/boot_entry.S index cf793f5..5ad94bf 100644 --- a/src/arch/xtensa/boot_entry.S +++ b/src/arch/xtensa/boot_entry.S @@ -31,7 +31,7 @@ /* * Entry point from ROM - assumes :- * - * 1) C runtime environment is initalised by ROM. + * 1) C runtime environment is initialized by ROM. * 2) Stack is in first HPSRAM bank. */ diff --git a/src/arch/xtensa/boot_loader.c b/src/arch/xtensa/boot_loader.c index 5c5939c..dfaa1a7 100644 --- a/src/arch/xtensa/boot_loader.c +++ b/src/arch/xtensa/boot_loader.c @@ -90,7 +90,7 @@ static void parse_module(struct sof_man_fw_header *hdr, break; case SOF_MAN_SEGMENT_BSS: /* copy from IMR to SRAM */ - bbzero((void*)mod->segment[i].v_base_addr, + bbzero((void *)mod->segment[i].v_base_addr, mod->segment[i].flags.r.length * HOST_PAGE_SIZE); break; default: @@ -143,9 +143,8 @@ static int32_t hp_sram_init(void) idelay(delay_count); status = io_reg_read(HSPGISTS0); - if (timeout-- < 0) { + if (timeout-- < 0) return -EIO; - } } /* query the power status of second part of HP memory */ @@ -156,9 +155,8 @@ static int32_t hp_sram_init(void) idelay(delay_count); status = io_reg_read(HSPGISTS1); - if (timeout-- < 0) { + if (timeout-- < 0) return -EIO; - } } /* add some delay before touch power register */ diff --git a/src/arch/xtensa/crt1-boards.S b/src/arch/xtensa/crt1-boards.S index ff24bfd..7239f4f 100644 --- a/src/arch/xtensa/crt1-boards.S +++ b/src/arch/xtensa/crt1-boards.S @@ -1,303 +1,303 @@ -// crt1-boards.S -// -// For most hardware / boards, this code sets up the C calling context -// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start -// which sets up the C library, calls constructors and registers destructors, -// and calls main(). -// -// Control arrives here at _start from the reset vector or from crt0-app.S. - -// Copyright (c) 1998-2010 Tensilica Inc. -// -// Permission is hereby granted, free of charge, to any person obtaining -// a copy of this software and associated documentation files (the -// "Software"), to deal in the Software without restriction, including -// without limitation the rights to use, copy, modify, merge, publish, -// distribute, sublicense, and/or sell copies of the Software, and to -// permit persons to whom the Software is furnished to do so, subject to -// the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -#include <xtensa/coreasm.h> -// DF #include "xtos-internal.h" -//#include <xtensa/../../src/xtos/xtos-internal.h> - -//.global _ResetVector -#if 0 -/* - * Reset vector. - * Only a trampoline to jump to _start - * (Note that we have to mark the section writable as the section contains - * a relocatable literal) - */ - - .section .ResetVector.text, "awx" - .global _ResetVector -_ResetVector: - - j 1f - .align 4 -2: .long _start -1: l32r a2, 2b - jx a2 -#endif - -// Exports -.global _start - -// Imports -// __clibrary_init from C library (eg. newlib or uclibc) -// exit from C library -// main from user application -// board_init board-specific (uart/mingloss/tinygloss.c) -// xthal_dcache_all_writeback from HAL library -// __stack from linker script (see LSP Ref Manual) -// _bss_table_start from linker script (see LSP Ref Manual) -// _bss_table_end from linker script (see LSP Ref Manual) - -.type main, @function - -// Macros to abstract away ABI differences - -#if __XTENSA_CALL0_ABI__ -# define CALL call0 -# define ARG1 a2 /* 1st outgoing call argument */ -# define ARG2 a3 /* 2nd outgoing call argument */ -# define ARG3 a4 /* 3rd outgoing call argument */ -# define ARG4 a5 /* 4th outgoing call argument */ -# define ARG5 a6 /* 5th outgoing call argument */ -#else -# define CALL call4 -# define CALLX callx4 -# define ARG1 a6 /* 1st outgoing call argument */ -# define ARG2 a7 /* 2nd outgoing call argument */ -# define ARG3 a8 /* 3rd outgoing call argument */ -# define ARG4 a9 /* 4th outgoing call argument */ -# define ARG5 a10 /* 5th outgoing call argument */ -#endif - - -/**************************************************************************/ - - .text - .align 4 - .literal_position -_start: - // _start is typically NOT at the beginning of the text segment -- - // it is always called from either the reset vector or other code - // that does equivalent initialization (such as crt0-app.S). - // - // Assumptions on entry to _start: - // - low (level-one) and medium priority interrupts are disabled - // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to - // be zeroed, to potentially enable them, before calling main) - // - C calling context not initialized: - // - PS not initialized - // - SP not initialized - // - the following are initialized: - // - LITBASE, cache attributes, WindowBase, WindowStart, - // CPENABLE, FP's FCR and FSR, EXCSAVE[n] - - // Keep a0 zero. It is used to initialize a few things. - // It is also the return address, where zero indicates - // that the frame used by _start is the bottommost frame. - // -#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX - movi a0, 0 // keep this register zero. -#endif - -#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT -#include "reset-unneeded.S" -#endif - -#if XCHAL_HAVE_BOOTLOADER - .weak _Level2FromVector - .weak _Level3FromVector - .weak _Level4FromVector - .weak _Level5FromVector - - movi a4, _Level2FromVector - wsr a4, EXCSAVE+2 - movi a4, _Level3FromVector - wsr a4, EXCSAVE+3 - movi a4, _Level4FromVector - wsr a4, EXCSAVE+4 - movi a4, _Level5FromVector - wsr a4, EXCSAVE+5 -#endif - - // Initialize the stack pointer. - // See the "ABI and Software Conventions" chapter in the - // Xtensa ISA Reference manual for details. - - // NOTE: Because the _start routine does not use any memory in its - // stack frame, and because all of its CALL instructions use a - // window size of 4 (or zero), the stack frame for _start can be empty. - - movi sp, __stack - - /* - * Now that sp (a1) is set, we can set PS as per the application - * (user vector mode, enable interrupts, enable window exceptions if applicable). - */ -#if XCHAL_HAVE_EXCEPTIONS -# ifdef __XTENSA_CALL0_ABI__ - movi a3, PS_UM // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 -# else - movi a3, PS_UM|PS_WOE // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 -# endif - wsr a3, PS - rsync -#endif - -/* - * Do any initialization that affects the memory map, such as - * setting up TLB entries, that needs to be done before we can - * successfully clear BSS (e.g. if some BSS segments are in - * remapped areas). - * - * NOTE: This hook works where the reset vector does not unpack - * segments (see "ROM packing" in the LSP manual), or where - * unpacking of segments is not affected by memory remapping. - * If ROM unpacking is affected, TLB setup must be done in - * assembler from the reset vector. - * - * The __memmap_init() routine can be a C function, however it - * does not have BSS initialized! In particular, __memmap_init() - * cannot set BSS variables, i.e. uninitialized global variables - * (they'll be wiped out by the following BSS clear), nor can it - * assume they are yet initialized to zero. - * - * The __memmap_init() function is optional. It is marked as a - * weak symbol, so that it gets valued zero if not defined. - */ - - .weak __memmap_init - movi a4, __memmap_init - beqz a4, 1f - CALLX a4 -1: - -#if !XCHAL_HAVE_BOOTLOADER /* boot loader takes care of zeroing BSS */ - /* - * Clear the BSS (uninitialized data) segments. - * This code supports multiple zeroed sections (*.bss). - * - * Register allocation: - * a0 = 0 - * a6 = pointer to start of table, and through table - * a7 = pointer to end of table - * a8 = start address of bytes to be zeroed - * a9 = end address of bytes to be zeroed - * a10 = length of bytes to be zeroed - */ - movi a0, 0 - movi a6, _bss_table_start - movi a7, _bss_table_end - bgeu a6, a7, .L3zte - -.L0zte: l32i a8, a6, 0 // get start address, assumed multiple of 4 - l32i a9, a6, 4 // get end address, assumed multiple of 4 - addi a6, a6, 8 // next entry - sub a10, a9, a8 // a10 = length, assumed a multiple of 4 - bbci.l a10, 2, .L1zte - s32i a0, a8, 0 // clear 4 bytes to make length multiple of 8 - addi a8, a8, 4 -.L1zte: bbci.l a10, 3, .L2zte - s32i a0, a8, 0 // clear 8 bytes to make length multiple of 16 - s32i a0, a8, 4 - addi a8, a8, 8 -.L2zte: srli a10, a10, 4 // length is now multiple of 16, divide by 16 - floopnez a10, clearzte - s32i a0, a8, 0 // clear 16 bytes at a time... - s32i a0, a8, 4 - s32i a0, a8, 8 - s32i a0, a8, 12 - addi a8, a8, 16 - floopend a10, clearzte - - bltu a6, a7, .L0zte // loop until end of table of *.bss sections -.L3zte: -#endif - - - // We can now call C code, the C calling environment has been initialized. - // - // From this point on, we use ABI-specific macros to refer to registers a0 .. a15 - // (ARG#). - - -#if XCHAL_HAVE_HALT - // Assume minimalist environment for memory-constrained TX cores. - // No C library or board initialization, no parameters passed to main - // (assume declared as "void main(void)") and no call to exit(). - - CALL main - halt - -#else /* !HALT */ - - .type board_init, @function - .type __clibrary_init, @function - .type exit, @function - - - // Initialize the board (eg. the UART on the XT2000). - //CALL board_init - - /* - * Call __clibrary_init to initialize the C library: - * - * void __clibrary_init(int argc, char ** argv, char ** environ, - * void(*init_func)(void), void(*fini_func)(void)); - */ - - // Pass an empty argv array, with an empty string as the program name. -#if 0 - movi ARG1, _start_argc // argc address - movi ARG2, _start_argv // argv = ["", 0] - movi ARG3, _start_envp // envp = [0] -// movi ARG4, _init // function that calls constructors -// movi ARG5, _fini // function that calls destructors - l32i ARG1, ARG1, 0 // argc = 1 - CALL __clibrary_init -#endif - // Call: int main(int argc, char ** argv, char ** environ); - movi ARG1, _start_argc // argc address - movi ARG2, _start_argv // argv = ["", 0] - movi ARG3, _start_envp // envp = [0] - l32i ARG1, ARG1, 0 // argc = 1 - CALL main - // The return value is the same register as the first outgoing argument. -// CALL exit // exit with main's return value - // Does not return here. - - .data - // Mark argc/argv/envp parameters as weak so that an external - // object file can override them. - .weak _start_argc, _start_argv, _start_envp - .align 4 -_start_argv: - .word _start_null // empty program name -_start_null: -_start_envp: - .word 0 // end of argv array, empty string, empty environ -_start_argc: - .word 1 // one argument (program name) - .text - -#endif /* !HALT */ - - .size _start, . - _start - -//#endif +// crt1-boards.S +// +// For most hardware / boards, this code sets up the C calling context +// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start +// which sets up the C library, calls constructors and registers destructors, +// and calls main(). +// +// Control arrives here at _start from the reset vector or from crt0-app.S. + +// Copyright (c) 1998-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include <xtensa/coreasm.h> +// DF #include "xtos-internal.h" +//#include <xtensa/../../src/xtos/xtos-internal.h> + +//.global _ResetVector +#if 0 +/* + * Reset vector. + * Only a trampoline to jump to _start + * (Note that we have to mark the section writable as the section contains + * a relocatable literal) + */ + + .section .ResetVector.text, "awx" + .global _ResetVector +_ResetVector: + + j 1f + .align 4 +2: .long _start +1: l32r a2, 2b + jx a2 +#endif + +// Exports +.global _start + +// Imports +// __clibrary_init from C library (eg. newlib or uclibc) +// exit from C library +// main from user application +// board_init board-specific (uart/mingloss/tinygloss.c) +// xthal_dcache_all_writeback from HAL library +// __stack from linker script (see LSP Ref Manual) +// _bss_table_start from linker script (see LSP Ref Manual) +// _bss_table_end from linker script (see LSP Ref Manual) + +.type main, @function + +// Macros to abstract away ABI differences + +#if __XTENSA_CALL0_ABI__ +# define CALL call0 +# define ARG1 a2 /* 1st outgoing call argument */ +# define ARG2 a3 /* 2nd outgoing call argument */ +# define ARG3 a4 /* 3rd outgoing call argument */ +# define ARG4 a5 /* 4th outgoing call argument */ +# define ARG5 a6 /* 5th outgoing call argument */ +#else +# define CALL call4 +# define CALLX callx4 +# define ARG1 a6 /* 1st outgoing call argument */ +# define ARG2 a7 /* 2nd outgoing call argument */ +# define ARG3 a8 /* 3rd outgoing call argument */ +# define ARG4 a9 /* 4th outgoing call argument */ +# define ARG5 a10 /* 5th outgoing call argument */ +#endif + + +/**************************************************************************/ + + .text + .align 4 + .literal_position +_start: + // _start is typically NOT at the beginning of the text segment -- + // it is always called from either the reset vector or other code + // that does equivalent initialization (such as crt0-app.S). + // + // Assumptions on entry to _start: + // - low (level-one) and medium priority interrupts are disabled + // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to + // be zeroed, to potentially enable them, before calling main) + // - C calling context not initialized: + // - PS not initialized + // - SP not initialized + // - the following are initialized: + // - LITBASE, cache attributes, WindowBase, WindowStart, + // CPENABLE, FP's FCR and FSR, EXCSAVE[n] + + // Keep a0 zero. It is used to initialize a few things. + // It is also the return address, where zero indicates + // that the frame used by _start is the bottommost frame. + // +#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX + movi a0, 0 // keep this register zero. +#endif + +#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT +#include "reset-unneeded.S" +#endif + +#if XCHAL_HAVE_BOOTLOADER + .weak _Level2FromVector + .weak _Level3FromVector + .weak _Level4FromVector + .weak _Level5FromVector + + movi a4, _Level2FromVector + wsr a4, EXCSAVE+2 + movi a4, _Level3FromVector + wsr a4, EXCSAVE+3 + movi a4, _Level4FromVector + wsr a4, EXCSAVE+4 + movi a4, _Level5FromVector + wsr a4, EXCSAVE+5 +#endif + + // Initialize the stack pointer. + // See the "ABI and Software Conventions" chapter in the + // Xtensa ISA Reference manual for details. + + // NOTE: Because the _start routine does not use any memory in its + // stack frame, and because all of its CALL instructions use a + // window size of 4 (or zero), the stack frame for _start can be empty. + + movi sp, __stack + + /* + * Now that sp (a1) is set, we can set PS as per the application + * (user vector mode, enable interrupts, enable window exceptions if applicable). + */ +#if XCHAL_HAVE_EXCEPTIONS +# ifdef __XTENSA_CALL0_ABI__ + movi a3, PS_UM // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 +# else + movi a3, PS_UM|PS_WOE // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 +# endif + wsr a3, PS + rsync +#endif + +/* + * Do any initialization that affects the memory map, such as + * setting up TLB entries, that needs to be done before we can + * successfully clear BSS (e.g. if some BSS segments are in + * remapped areas). + * + * NOTE: This hook works where the reset vector does not unpack + * segments (see "ROM packing" in the LSP manual), or where + * unpacking of segments is not affected by memory remapping. + * If ROM unpacking is affected, TLB setup must be done in + * assembler from the reset vector. + * + * The __memmap_init() routine can be a C function, however it + * does not have BSS initialized! In particular, __memmap_init() + * cannot set BSS variables, i.e. uninitialized global variables + * (they'll be wiped out by the following BSS clear), nor can it + * assume they are yet initialized to zero. + * + * The __memmap_init() function is optional. It is marked as a + * weak symbol, so that it gets valued zero if not defined. + */ + + .weak __memmap_init + movi a4, __memmap_init + beqz a4, 1f + CALLX a4 +1: + +#if !XCHAL_HAVE_BOOTLOADER /* boot loader takes care of zeroing BSS */ + /* + * Clear the BSS (uninitialized data) segments. + * This code supports multiple zeroed sections (*.bss). + * + * Register allocation: + * a0 = 0 + * a6 = pointer to start of table, and through table + * a7 = pointer to end of table + * a8 = start address of bytes to be zeroed + * a9 = end address of bytes to be zeroed + * a10 = length of bytes to be zeroed + */ + movi a0, 0 + movi a6, _bss_table_start + movi a7, _bss_table_end + bgeu a6, a7, .L3zte + +.L0zte: l32i a8, a6, 0 // get start address, assumed multiple of 4 + l32i a9, a6, 4 // get end address, assumed multiple of 4 + addi a6, a6, 8 // next entry + sub a10, a9, a8 // a10 = length, assumed a multiple of 4 + bbci.l a10, 2, .L1zte + s32i a0, a8, 0 // clear 4 bytes to make length multiple of 8 + addi a8, a8, 4 +.L1zte: bbci.l a10, 3, .L2zte + s32i a0, a8, 0 // clear 8 bytes to make length multiple of 16 + s32i a0, a8, 4 + addi a8, a8, 8 +.L2zte: srli a10, a10, 4 // length is now multiple of 16, divide by 16 + floopnez a10, clearzte + s32i a0, a8, 0 // clear 16 bytes at a time... + s32i a0, a8, 4 + s32i a0, a8, 8 + s32i a0, a8, 12 + addi a8, a8, 16 + floopend a10, clearzte + + bltu a6, a7, .L0zte // loop until end of table of *.bss sections +.L3zte: +#endif + + + // We can now call C code, the C calling environment has been initialized. + // + // From this point on, we use ABI-specific macros to refer to registers a0 .. a15 + // (ARG#). + + +#if XCHAL_HAVE_HALT + // Assume minimalist environment for memory-constrained TX cores. + // No C library or board initialization, no parameters passed to main + // (assume declared as "void main(void)") and no call to exit(). + + CALL main + halt + +#else /* !HALT */ + + .type board_init, @function + .type __clibrary_init, @function + .type exit, @function + + + // Initialize the board (eg. the UART on the XT2000). + //CALL board_init + + /* + * Call __clibrary_init to initialize the C library: + * + * void __clibrary_init(int argc, char ** argv, char ** environ, + * void(*init_func)(void), void(*fini_func)(void)); + */ + + // Pass an empty argv array, with an empty string as the program name. +#if 0 + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv = ["", 0] + movi ARG3, _start_envp // envp = [0] +// movi ARG4, _init // function that calls constructors +// movi ARG5, _fini // function that calls destructors + l32i ARG1, ARG1, 0 // argc = 1 + CALL __clibrary_init +#endif + // Call: int main(int argc, char ** argv, char ** environ); + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv = ["", 0] + movi ARG3, _start_envp // envp = [0] + l32i ARG1, ARG1, 0 // argc = 1 + CALL main + // The return value is the same register as the first outgoing argument. +// CALL exit // exit with main's return value + // Does not return here. + + .data + // Mark argc/argv/envp parameters as weak so that an external + // object file can override them. + .weak _start_argc, _start_argv, _start_envp + .align 4 +_start_argv: + .word _start_null // empty program name +_start_null: +_start_envp: + .word 0 // end of argv array, empty string, empty environ +_start_argc: + .word 1 // one argument (program name) + .text + +#endif /* !HALT */ + + .size _start, . - _start + +//#endif diff --git a/src/arch/xtensa/include/arch/wait.h b/src/arch/xtensa/include/arch/wait.h index 2f6e4f5..2527324 100644 --- a/src/arch/xtensa/include/arch/wait.h +++ b/src/arch/xtensa/include/arch/wait.h @@ -62,8 +62,7 @@ static inline void arch_wait_for_interrupt(int level) static inline void idelay(int n) { - while (n--) { + while (n--) asm volatile("nop"); - } } diff --git a/src/ipc/apl-ipc.c b/src/ipc/apl-ipc.c index c779062..8597c27 100644 --- a/src/ipc/apl-ipc.c +++ b/src/ipc/apl-ipc.c @@ -204,8 +204,8 @@ int platform_ipc_init(struct ipc *ipc) iipc->pm_prepare_D3 = 0; /* configure interrupt */ - interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL); - interrupt_enable(PLATFORM_IPC_INTERUPT); + interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, NULL); + interrupt_enable(PLATFORM_IPC_INTERRUPT); /* enable IPC interrupts from host */ ipc_write(IPC_DIPCCTL, IPC_DIPCCTL_IPCIDIE | IPC_DIPCCTL_IPCTBIE); diff --git a/src/ipc/byt-ipc.c b/src/ipc/byt-ipc.c index 8897bb9..8760121 100644 --- a/src/ipc/byt-ipc.c +++ b/src/ipc/byt-ipc.c @@ -100,7 +100,7 @@ static void irq_handler(void *arg) /* Mask Done interrupt before return */ shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_DONE); - interrupt_clear(PLATFORM_IPC_INTERUPT); + interrupt_clear(PLATFORM_IPC_INTERRUPT); do_notify(); } @@ -108,7 +108,7 @@ static void irq_handler(void *arg) /* Mask Busy interrupt before return */ shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_BUSY); - interrupt_clear(PLATFORM_IPC_INTERUPT); + interrupt_clear(PLATFORM_IPC_INTERRUPT); /* TODO: place message in Q and process later */ /* It's not Q ATM, may overwrite */ @@ -230,8 +230,8 @@ int platform_ipc_init(struct ipc *ipc) iipc->pm_prepare_D3 = 0; /* configure interrupt */ - interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL); - interrupt_enable(PLATFORM_IPC_INTERUPT); + interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, NULL); + interrupt_enable(PLATFORM_IPC_INTERRUPT); /* Unmask Busy and Done interrupts */ imrd = shim_read(SHIM_IMRD); diff --git a/src/ipc/cnl-ipc.c b/src/ipc/cnl-ipc.c index cd5e825..3522d67 100644 --- a/src/ipc/cnl-ipc.c +++ b/src/ipc/cnl-ipc.c @@ -91,7 +91,7 @@ static void irq_handler(void *arg) ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE); /* clear DONE bit - tell host we have completed the operation */ - ipc_write(IPC_DIPCIDA, ipc_read(IPC_DIPCIDA) |IPC_DIPCIDA_DONE); + ipc_write(IPC_DIPCIDA, ipc_read(IPC_DIPCIDA) | IPC_DIPCIDA_DONE); /* unmask Done interrupt */ ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCIDIE); @@ -128,8 +128,8 @@ done: ipc->host_pending = 0; /* write 1 to clear busy, and trigger interrupt to host*/ - ipc_write(IPC_DIPCTDR, ipc_read(IPC_DIPCTDR) |IPC_DIPCTDR_BUSY); - ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) |IPC_DIPCTDA_BUSY ); + ipc_write(IPC_DIPCTDR, ipc_read(IPC_DIPCTDR) | IPC_DIPCTDR_BUSY); + ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) | IPC_DIPCTDA_BUSY); /* unmask Busy interrupt */ ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE); @@ -202,8 +202,8 @@ int platform_ipc_init(struct ipc *ipc) iipc->pm_prepare_D3 = 0; /* configure interrupt */ - interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL); - interrupt_enable(PLATFORM_IPC_INTERUPT); + interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, NULL); + interrupt_enable(PLATFORM_IPC_INTERRUPT); /* enable IPC interrupts from host */ ipc_write(IPC_DIPCCTL, IPC_DIPCCTL_IPCIDIE | IPC_DIPCCTL_IPCTBIE); diff --git a/src/ipc/hsw-ipc.c b/src/ipc/hsw-ipc.c index 4a16f41..653c215 100644 --- a/src/ipc/hsw-ipc.c +++ b/src/ipc/hsw-ipc.c @@ -99,7 +99,7 @@ static void irq_handler(void *arg) /* Mask Done interrupt before return */ shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_DONE); - interrupt_clear(PLATFORM_IPC_INTERUPT); + interrupt_clear(PLATFORM_IPC_INTERRUPT); do_notify(); } @@ -107,7 +107,7 @@ static void irq_handler(void *arg) /* Mask Busy interrupt before return */ shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_BUSY); - interrupt_clear(PLATFORM_IPC_INTERUPT); + interrupt_clear(PLATFORM_IPC_INTERRUPT); /* place message in Q and process later */ _ipc->host_msg = shim_read(SHIM_IPCX); @@ -219,8 +219,8 @@ int platform_ipc_init(struct ipc *ipc) iipc->pm_prepare_D3 = 0; /* configure interrupt */ - interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL); - interrupt_enable(PLATFORM_IPC_INTERUPT); + interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, NULL); + interrupt_enable(PLATFORM_IPC_INTERRUPT); /* Unmask Busy and Done interrupts */ imrd = shim_read(SHIM_IMRD); diff --git a/src/lib/interrupt.c b/src/lib/interrupt.c index 4516cf3..60c0a31 100644 --- a/src/lib/interrupt.c +++ b/src/lib/interrupt.c @@ -106,7 +106,7 @@ uint32_t irq_enable_child(struct irq_parent *parent, int irq) spin_lock(&parent->lock); - child =parent->child[REEF_IRQ_BIT(irq)]; + child = parent->child[REEF_IRQ_BIT(irq)]; /* already enabled ? */ if (child->enabled) @@ -133,7 +133,7 @@ uint32_t irq_disable_child(struct irq_parent *parent, int irq) spin_lock(&parent->lock); - child =parent->child[REEF_IRQ_BIT(irq)]; + child = parent->child[REEF_IRQ_BIT(irq)]; /* already disabled ? */ if (!child->enabled) diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h index eca9a53..d84ec40 100644 --- a/src/platform/apollolake/include/platform/memory.h +++ b/src/platform/apollolake/include/platform/memory.h @@ -191,8 +191,8 @@ #define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) #define HEAP_BUFFER_SIZE \ - (L2_SRAM_SIZE - L2_VECTOR_SIZE - REEF_TEXT_SIZE - REEF_DATA_SIZE - \ - REEF_BSS_DATA_SIZE - HEAP_RUNTIME_SIZE - REEF_STACK_SIZE - HEAP_SYSTEM_SIZE) + (L2_SRAM_SIZE - L2_VECTOR_SIZE - REEF_TEXT_SIZE - REEF_DATA_SIZE - \ + REEF_BSS_DATA_SIZE - HEAP_RUNTIME_SIZE - REEF_STACK_SIZE - HEAP_SYSTEM_SIZE) #define HEAP_BUFFER_BLOCK_SIZE 0x180 #define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index 4165b95..6609f33 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -43,7 +43,7 @@ struct reef; #define PLATFORM_PAGE_TABLE_SIZE 256 /* IPC Interrupt */ -#define PLATFORM_IPC_INTERUPT IRQ_EXT_IPC_LVL2(0) +#define PLATFORM_IPC_INTERRUPT IRQ_EXT_IPC_LVL2(0) /* pipeline IRQ */ #define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE5 diff --git a/src/platform/apollolake/interrupt.c b/src/platform/apollolake/interrupt.c index 3f799b7..86f8d84 100644 --- a/src/platform/apollolake/interrupt.c +++ b/src/platform/apollolake/interrupt.c @@ -42,7 +42,7 @@ static void parent_level2_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -85,7 +85,7 @@ next: static void parent_level3_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -128,7 +128,7 @@ next: static void parent_level4_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -171,7 +171,7 @@ next: static void parent_level5_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -298,7 +298,6 @@ void platform_interrupt_init(void) irq_write(REG_IRQ_IL4MSD(0), REG_IRQ_IL4MD_ALL); irq_write(REG_IRQ_IL5MSD(0), REG_IRQ_IL5MD_ALL); - for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) { + for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) spinlock_init(&dsp_irq[i].lock); - } } diff --git a/src/platform/baytrail/include/platform/platform.h b/src/platform/baytrail/include/platform/platform.h index 8b713df..59b940b 100644 --- a/src/platform/baytrail/include/platform/platform.h +++ b/src/platform/baytrail/include/platform/platform.h @@ -39,7 +39,7 @@ struct reef; /* IPC Interrupt */ -#define PLATFORM_IPC_INTERUPT IRQ_NUM_EXT_IA +#define PLATFORM_IPC_INTERRUPT IRQ_NUM_EXT_IA /* Host page size */ #define HOST_PAGE_SIZE 4096 diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index 00e0069..60b0518 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -46,7 +46,7 @@ struct reef; #define PLATFORM_PAGE_TABLE_SIZE 256 /* IPC Interrupt */ -#define PLATFORM_IPC_INTERUPT IRQ_EXT_IPC_LVL2(0) +#define PLATFORM_IPC_INTERRUPT IRQ_EXT_IPC_LVL2(0) /* pipeline IRQ */ #define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE5 diff --git a/src/platform/cannonlake/interrupt.c b/src/platform/cannonlake/interrupt.c index 3268362..381030a 100644 --- a/src/platform/cannonlake/interrupt.c +++ b/src/platform/cannonlake/interrupt.c @@ -42,7 +42,7 @@ static void parent_level2_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -85,7 +85,7 @@ next: static void parent_level3_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -128,7 +128,7 @@ next: static void parent_level4_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -171,7 +171,7 @@ next: static void parent_level5_handler(void *data) { struct irq_parent *parent = (struct irq_parent *)data; - struct irq_child * child = NULL; + struct irq_child *child = NULL; uint32_t status; uint32_t i = 0; @@ -298,7 +298,6 @@ void platform_interrupt_init(void) irq_write(REG_IRQ_IL4MSD(0), REG_IRQ_IL4MD_ALL); irq_write(REG_IRQ_IL5MSD(0), REG_IRQ_IL5MD_ALL); - for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) { + for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) spinlock_init(&dsp_irq[i].lock); - } } diff --git a/src/platform/cannonlake/platform.c b/src/platform/cannonlake/platform.c index 729364f..89aa2c3 100644 --- a/src/platform/cannonlake/platform.c +++ b/src/platform/cannonlake/platform.c @@ -178,7 +178,7 @@ static void platform_init_hw(void) GENO_MDIVOSEL | GENO_DIOPTOSEL); io_reg_write(DSP_INIT_IOPO, - IOPO_DMIC_FLAG |IOPO_I2S_FLAG); + IOPO_DMIC_FLAG | IOPO_I2S_FLAG); io_reg_write(DSP_INIT_ALHO, ALHO_ASO_FLAG | ALHO_CSO_FLAG | ALHO_CFO_FLAG); @@ -261,7 +261,7 @@ int platform_init(struct reef *reef) /* init SSP ports */ trace_point(TRACE_BOOT_PLATFORM_SSP); - for(i = 0; i < PLATFORM_SSP_COUNT; i++) { + for (i = 0; i < PLATFORM_SSP_COUNT; i++) { ssp = dai_get(SOF_DAI_INTEL_SSP, i); if (ssp == NULL) return -ENODEV; diff --git a/src/platform/haswell/include/platform/platform.h b/src/platform/haswell/include/platform/platform.h index 8475e31..01a3646 100644 --- a/src/platform/haswell/include/platform/platform.h +++ b/src/platform/haswell/include/platform/platform.h @@ -38,7 +38,7 @@ struct reef; /* IPC Interrupt */ -#define PLATFORM_IPC_INTERUPT IRQ_NUM_EXT_IA +#define PLATFORM_IPC_INTERRUPT IRQ_NUM_EXT_IA /* Host page size */ #define HOST_PAGE_SIZE 4096 -- 2.14.3

2 2

[Sound-open-firmware] [PATCH v2 3/3] rimge: initial the char array.
by xionghu.luo＠linux.intel.com 26 Jan '18

26 Jan '18

From: Luo Xionghu <xionghu.luo(a)intel.com> the variable maybe used uninitalied, initialize it to empty. If the image->key_name is NULL, restore it to NULL before return. --- v2: if path is modified in the function, strcmp returns not 0. Signed-off-by: Luo Xionghu <xionghu.luo(a)intel.com> --- rimage/pkcs1_5.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/rimage/pkcs1_5.c b/rimage/pkcs1_5.c index 0c5806b..feffb7b 100644 --- a/rimage/pkcs1_5.c +++ b/rimage/pkcs1_5.c @@ -56,7 +56,9 @@ int pkcs_sign(struct image *image, struct fw_image_manifest *man, RSA *priv_rsa = NULL; EVP_PKEY *privkey; FILE *fp; - unsigned char digest[SHA256_DIGEST_LENGTH], path[256], mod[MAN_RSA_KEY_MODULUS_LEN]; + unsigned char path[256] = ""; + unsigned char digest[SHA256_DIGEST_LENGTH]; + unsigned char mod[MAN_RSA_KEY_MODULUS_LEN]; unsigned int siglen = MAN_RSA_SIGNATURE_LEN; int ret = -EINVAL, i; @@ -80,6 +82,8 @@ int pkcs_sign(struct image *image, struct fw_image_manifest *man, fp = fopen(image->key_name, "r"); if (fp == NULL) { fprintf(stderr, "error: can't open file %s %d\n", path, -errno); + if (strcmp(path, "")) + image->key_name = NULL; return -errno; } PEM_read_PrivateKey(fp, &privkey, NULL, NULL); -- 2.11.0

2 1

[Sound-open-firmware] [PATCH] Build: update README and build-all.sh for new platforms
by Keyon Jie 25 Jan '18

25 Jan '18

Update README to add HSW/BDW/APL/CNL; Update build-all.sh to add APL/CNL. Signed-off-by: Keyon Jie <yang.jie(a)linux.intel.com> --- Tested build-all passed. Tested on minnow turbot rt5651, SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, https://github.com/plbossart/sound/tree/topic/sof-v4.14: 5a91e6776d41b0e97828882294cdc00b5c0bafd6 README | 16 ++++++++++++++++ build-all.sh | 11 +++++++++++ 2 files changed, 27 insertions(+) diff --git a/README b/README index 9ca5b12..f354057 100644 --- a/README +++ b/README @@ -13,6 +13,22 @@ Cherrytrail :- ./configure --with-arch=xtensa --with-platform=cherrytrail --with-root-dir=$PWD/../xtensa-root/xtensa-byt-elf --host=xtensa-byt-elf +Haswell :- + +./configure --with-arch=xtensa --with-platform=haswell --with-root-dir=$PWD/../xtensa-root/xtensa-hsw-elf --host=xtensa-hsw-elf host_alias=xtensa-hsw-elf + +Broadwell :- + +./configure --with-arch=xtensa --with-platform=broadwell --with-root-dir=$PWD/../xtensa-root/xtensa-hsw-elf --host=xtensa-hsw-elf host_alias=xtensa-hsw-elf + +Apollolake :- + +./configure --with-arch=xtensa --with-platform=apollolake --with-root-dir=$PWD/../xtensa-root/xtensa-bxt-elf --host=xtensa-bxt-elf host_alias=xtensa-bxt-elf --disable-dma-trace + +Cannonlake :- + +./configure --with-arch=xtensa --with-platform=cannonlake --with-root-dir=$PWD/../xtensa-root/xtensa-sue-elf --host=xtensa-sue-elf host_alias=xtensa-sue-elf --disable-dma-trace + 3) make 4) make bin diff --git a/build-all.sh b/build-all.sh index 6035c66..7555c8f 100755 --- a/build-all.sh +++ b/build-all.sh @@ -33,6 +33,17 @@ make clean make make bin +# build for Apollolake +./configure --with-arch=xtensa --with-platform=apollolake --with-root-dir=$pwd/../xtensa-root/xtensa-bxt-elf --host=xtensa-bxt-elf --disable-dma-trace +make clean +make +make bin + +# build for Cannonlake +make clean +./configure --with-arch=xtensa --with-platform=cannonlake --with-root-dir=$pwd/../xtensa-root/xtensa-sue-elf --host=xtensa-sue-elf --disable-dma-trace +make +make bin # list all the images ls -l src/arch/xtensa/*.ri -- 2.11.0

1 0

Re: [Sound-open-firmware] [PATCH] Fix checkpatch warning.
by yanwang 25 Jan '18

25 Jan '18

On Thu, 2018-01-25 at 02:44 +0000, Wang, Yan wrote: > Subject: Re: [Sound-open-firmware] [PATCH] Fix checkpatch warning. > Date: Wed, 24 Jan 2018 10:13:21 +0000 > From: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> > To: yan.wang(a)linux.intel.com, sound-open-firmware(a)alsa-project.org > > On Wed, 2018-01-24 at 17:59 +0800, yan.wang(a)linux.intel.com wrote: > > > > From: Yan Wang <yan.wang(a)linux.intel.com> > > > > Fix coding style, typo and dos file format based on checkpatch > > warning. > > The checked commits are from > > f198ad907c5ad14cf7a99129ea8c17f40a632c29 > > to f7beb51118e6e8463a864b9416c773a508930e06. > > > > Signed-off-by: Yan Wang <yan.wang(a)linux.intel.com> > > --- > > Tested on minnow max rt5651, > > SOF Master: f7beb51118e6e8463a864b9416c773a508930e06, > > SOF Tool Master: 59d81995f682876bd34f939332e8838c76f714ec, > > https://github.com/plbossart/sound/tree/topic/sof-v4.14: > > 5a91e6776d41b0e97828882294cdc00b5c0bafd6 > > --- > > src/arch/xtensa/boot_entry.S | 2 +- > > src/arch/xtensa/boot_loader.c | 8 +- > > src/arch/xtensa/crt1-boards.S | 606 > > ++++++++++----------- > > It looks like the whole crt1-boards.S file has been modified. What > was the reason for this ? Hi, Liam, It is dos format. I just changed it to Unix format by dos2unix. So the code itself isn't changed. Thanks. Yan Wang > > Thanks > > Liam > _______________________________________________ > Sound-open-firmware mailing list > Sound-open-firmware(a)alsa-project.org > http://mailman.alsa-project.org/mailman/listinfo/sound-open-firmware >

1 0

[Sound-open-firmware] [PATCH v4] build: add library build support for host platform
by Ranjani Sridharan 24 Jan '18

24 Jan '18

This patch provides library build support for host platform architecture. It enables creating separate libraries for each SOF audio component. Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- Makefile.am | 15 +- README | 7 + build-all.sh | 4 + configure.ac | 107 +++- src/Makefile.am | 11 + src/arch/Makefile.am | 4 + src/arch/host/Makefile.am | 1 + src/arch/host/include/Makefile.am | 1 + src/arch/host/include/arch/Makefile.am | 8 + src/arch/host/include/arch/cache.h | 43 ++ src/arch/host/include/arch/interrupt.h | 56 ++ src/arch/host/include/arch/reef.h | 41 ++ src/arch/host/include/arch/spinlock.h | 46 ++ src/arch/host/include/arch/timer.h | 52 ++ src/arch/host/include/arch/wait.h | 34 + src/arch/xtensa/Makefile.am | 4 +- src/audio/Makefile.am | 1011 +++++++++++++++++++++++++++++- src/include/reef/Makefile.am | 6 +- src/include/reef/audio/Makefile.am | 8 +- src/include/uapi/Makefile.am | 2 +- src/ipc/Makefile.am | 37 +- src/library/Makefile.am | 1 + src/library/include/Makefile.am | 1 + src/library/include/platform/Makefile.am | 12 + src/library/include/platform/clk.h | 42 ++ src/library/include/platform/dma.h | 42 ++ src/library/include/platform/interrupt.h | 78 +++ src/library/include/platform/mailbox.h | 72 +++ src/library/include/platform/memory.h | 87 +++ src/library/include/platform/platform.h | 54 ++ src/library/include/platform/pmc.h | 41 ++ src/library/include/platform/shim.h | 40 ++ src/library/include/platform/timer.h | 54 ++ src/math/Makefile.am | 22 +- 34 files changed, 2003 insertions(+), 41 deletions(-) create mode 100644 src/arch/host/Makefile.am create mode 100644 src/arch/host/include/Makefile.am create mode 100644 src/arch/host/include/arch/Makefile.am create mode 100644 src/arch/host/include/arch/cache.h create mode 100644 src/arch/host/include/arch/interrupt.h create mode 100644 src/arch/host/include/arch/reef.h create mode 100644 src/arch/host/include/arch/spinlock.h create mode 100644 src/arch/host/include/arch/timer.h create mode 100644 src/arch/host/include/arch/wait.h create mode 100644 src/library/Makefile.am create mode 100644 src/library/include/Makefile.am create mode 100644 src/library/include/platform/Makefile.am create mode 100644 src/library/include/platform/clk.h create mode 100644 src/library/include/platform/dma.h create mode 100644 src/library/include/platform/interrupt.h create mode 100644 src/library/include/platform/mailbox.h create mode 100644 src/library/include/platform/memory.h create mode 100644 src/library/include/platform/platform.h create mode 100644 src/library/include/platform/pmc.h create mode 100644 src/library/include/platform/shim.h create mode 100644 src/library/include/platform/timer.h diff --git a/Makefile.am b/Makefile.am index c05f042..82ad39e 100644 --- a/Makefile.am +++ b/Makefile.am @@ -6,6 +6,19 @@ EXTRA_DIST = version.sh SRC_DIR = $(abs_top_builddir)/src +if BUILD_HOST +export ARCH_INCDIR = \ + -I $(SRC_DIR)/arch/$(ARCH)/include + +export REEF_INCDIR = \ + -I $(SRC_DIR)/include + +if BUILD_LIB +export PLATFORM_INCDIR = \ + -I $(SRC_DIR)/library/include +endif + +else export REEF_INCDIR = \ -I $(SRC_DIR)/include \ -I $(ROOT_DIR)/include @@ -13,9 +26,9 @@ export REEF_INCDIR = \ export ARCH_INCDIR = \ -I $(SRC_DIR)/arch/$(ARCH)/include \ -I $(SRC_DIR)/arch/$(ARCH)/xtos - export PLATFORM_INCDIR = \ -I $(SRC_DIR)/platform/$(PLATFORM)/include +endif dist-hook: ./version.sh $(top_srcdir) diff --git a/README b/README index 9ca5b12..463fc42 100644 --- a/README +++ b/README @@ -13,6 +13,13 @@ Cherrytrail :- ./configure --with-arch=xtensa --with-platform=cherrytrail --with-root-dir=$PWD/../xtensa-root/xtensa-byt-elf --host=xtensa-byt-elf +Library for Host Platform :- +If building library for host platform, run the following configure. Please modify +the --prefix option to choose the directory for installing the library files and +headers + +./configure --with-arch=host --enable-library=yes --host=x86_64-unknown-linux-gnu --prefix=$pwd/../host-root/ + 3) make 4) make bin diff --git a/build-all.sh b/build-all.sh index 6035c66..ce719e9 100755 --- a/build-all.sh +++ b/build-all.sh @@ -33,6 +33,10 @@ make clean make make bin +# Build library for host platform architecture +./configure --with-arch=host --enable-library=yes --host=x86_64-unknown-linux-gnu --prefix=$pwd/../host-root/ +make +make install # list all the images ls -l src/arch/xtensa/*.ri diff --git a/configure.ac b/configure.ac index d37fc67..05a3bee 100644 --- a/configure.ac +++ b/configure.ac @@ -29,10 +29,13 @@ AC_SUBST(ASFLAGS) AC_ARG_WITH([root-dir], AS_HELP_STRING([--with-root-dir], [Specify location of cross gcc libraries and headers]), [], [with_root_dir=no]) -AS_IF([test "x$with_root_dir" = xno], - AC_MSG_ERROR([Please specify cross compiler root header directory]), - [ROOT_DIR=$with_root_dir]) -AC_SUBST(ROOT_DIR) + +# check if we are building FW image or library +AC_ARG_ENABLE(library, [AS_HELP_STRING([--enable-library],[build library])], have_library=$enableval, have_library=no) +if test "$have_library" = "yes"; then + AC_DEFINE([CONFIG_LIB], [1], [Configure for Shared Library]) +fi +AM_CONDITIONAL(BUILD_LIB, test "$have_library" = "yes") # Architecture support AC_ARG_WITH([arch], @@ -57,6 +60,23 @@ case "$with_arch" in ARCH="xtensa" AC_SUBST(ARCH) + + AS_IF([test "x$with_root_dir" = xno], + AC_MSG_ERROR([Please specify cross compiler root header directory]), + [ROOT_DIR=$with_root_dir]) + AC_SUBST(ROOT_DIR) + ;; + host*) + + ARCH_CFLAGS="-g" + AC_SUBST(ARCH_CFLAGS) + + # extra CFLAGS defined here otherwise configure working gcc tests fails. + CFLAGS="${CFLAGS:+$CFLAGS } -O3" + LDFLAGS="${LDFLAGS:+$LDFLAGS }-lpthread" + + ARCH="host" + AC_SUBST(ARCH) ;; *) AC_MSG_ERROR([DSP architecture not specified]) @@ -64,7 +84,7 @@ case "$with_arch" in esac AM_CONDITIONAL(BUILD_XTENSA, test "$ARCH" = "xtensa") - +AM_CONDITIONAL(BUILD_HOST, test "$ARCH" = "host") # Platform support AC_ARG_WITH([platform], @@ -175,7 +195,12 @@ case "$with_platform" in AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps]) ;; *) - AC_MSG_ERROR([Host platform not specified]) + if test "$ARCH" = "host"; then + PLATFORM="host" + AC_SUBST(PLATFORM) + else + AC_MSG_ERROR([Host platform not specified]) + fi ;; esac @@ -215,6 +240,70 @@ AM_CONDITIONAL(BUILD_DMA_TRACE, test "x$enable_dma_trace" != "xno") PLATFORM_BOOT_LDR_LDSCRIPT="boot_ldr.x" AC_SUBST(PLATFORM_BOOT_LDR_LDSCRIPT) +# Optimisation settings and checks + +# SSE4_2 support +AC_ARG_ENABLE(sse42, [AS_HELP_STRING([--enable-sse42],[enable SSE42 optimizations])], have_sse42=$enableval, have_sse42=yes) +AX_CHECK_COMPILE_FLAG(-msse4.2, [SSE42_CFLAGS="-DOPS_SSE42 -msse4.2 -ffast-math -ftree-vectorizer-verbose=0"], + [have_sse42=no]) +if test "$have_sse42" = "yes"; then + AC_DEFINE(HAVE_SSE42,1,[Define to enable SSE42 optimizations.]) +fi +AM_CONDITIONAL(HAVE_SSE42, test "$have_sse42" = "yes") +AC_SUBST(SSE42_CFLAGS) + +# AVX support +AC_ARG_ENABLE(avx, [AS_HELP_STRING([--enable-avx],[enable AVX optimizations])], have_avx=$enableval, have_avx=yes) +AX_CHECK_COMPILE_FLAG(-mavx, [AVX_CFLAGS="-DOPS_AVX -mavx -ffast-math -ftree-vectorizer-verbose=0"], + [have_avx=no]) +if test "$have_avx" = "yes"; then + AC_DEFINE(HAVE_AVX,1,[Define to enable AVX optimizations.]) +fi +AM_CONDITIONAL(HAVE_AVX, test "$have_avx" = "yes") +AC_SUBST(AVX_CFLAGS) + + +# AVX2 support +AC_ARG_ENABLE(avx2, [AS_HELP_STRING([--enable-avx2],[enable AVX2 optimizations])], have_avx2=$enableval, have_avx2=yes) +AX_CHECK_COMPILE_FLAG(-mavx2, [AVX2_CFLAGS="-DOPS_AVX2 -mavx2 -ffast-math -ftree-vectorizer-verbose=0"], + [have_avx2=no]) +if test "$have_avx2" = "yes"; then + AC_DEFINE(HAVE_AVX2,1,[Define to enable AVX2 optimizations.]) +fi +AM_CONDITIONAL(HAVE_AVX2, test "$have_avx2" = "yes") +AC_SUBST(AVX2_CFLAGS) + + +# FMA support +AC_ARG_ENABLE(fma, [AS_HELP_STRING([--enable-fma],[enable FMA optimizations])], have_fma=$enableval, have_fma=yes) +AX_CHECK_COMPILE_FLAG(-mfma, [FMA_CFLAGS="-DOPS_FMA -mfma -ffast-math -ftree-vectorizer-verbose=0"], + [have_fma=no]) +if test "$have_fma" = "yes"; then + AC_DEFINE(HAVE_FMA,1,[Define to enable FMA optimizations.]) +fi +AM_CONDITIONAL(HAVE_FMA, test "$have_fma" = "yes") +AC_SUBST(FMA_CFLAGS) + +# Hifi2EP +AC_ARG_ENABLE(hifi2ep, [AS_HELP_STRING([--enable-hifi2ep],[enable HiFi2EP optimizations])], have_hifi2ep=$enableval, have_hifi2ep=yes) +AX_CHECK_COMPILE_FLAG(-mhifi2ep, [FMA_CFLAGS="-DOPS_HIFI2EP -mhifi2ep -ffast-math -ftree-vectorizer-verbose=0"], + [have_hifi2ep=no]) +if test "$have_hifi2ep" = "yes"; then + AC_DEFINE(HAVE_HIFI2EP,1,[Define to enable Hifi2 EP optimizations.]) +fi +AM_CONDITIONAL(HAVE_HIFI2EP, test "$have_hifi2ep" = "yes") +AC_SUBST(HIFI2EP_CFLAGS) + +# Hifi3 +AC_ARG_ENABLE(hifi3, [AS_HELP_STRING([--enable-hifi3],[enable HiFi3 optimizations])], have_hifi3=$enableval, have_hifi3=yes) +AX_CHECK_COMPILE_FLAG(-mhihi3, [FMA_CFLAGS="-DOPS_HIFI3 -mhifi3 -ffast-math -ftree-vectorizer-verbose=0"], + [have_hifi3=no]) +if test "$have_hifi3" = "yes"; then + AC_DEFINE(HAVE_HIFI3,1,[Define to enable Hifi3 optimizations.]) +fi +AM_CONDITIONAL(HAVE_HIFI3, test "$have_hifi3" = "yes") +AC_SUBST(HIFI3_CFLAGS) + # Test after CFLAGS set othewise test of cross compiler fails. AM_PROG_AS AM_PROG_AR @@ -240,6 +329,9 @@ AC_CONFIG_FILES([ src/arch/xtensa/include/xtensa/config/Makefile src/arch/xtensa/hal/Makefile src/arch/xtensa/xtos/Makefile + src/arch/host/Makefile + src/arch/host/include/Makefile + src/arch/host/include/arch/Makefile src/audio/Makefile src/math/Makefile src/drivers/Makefile @@ -251,6 +343,9 @@ AC_CONFIG_FILES([ src/include/reef/math/Makefile src/include/uapi/Makefile src/ipc/Makefile + src/library/Makefile + src/library/include/Makefile + src/library/include/platform/Makefile src/lib/Makefile src/platform/Makefile src/platform/baytrail/Makefile diff --git a/src/Makefile.am b/src/Makefile.am index fb82330..291d45e 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -1 +1,12 @@ +export COMMON_INCDIR = \ + $(REEF_INCDIR) \ + $(ARCH_INCDIR) \ + $(PLATFORM_INCDIR) + +if BUILD_LIB +SUBDIRS = ipc math audio arch include library +endif + +if BUILD_XTENSA SUBDIRS = include init math audio platform tasks drivers ipc lib arch +endif diff --git a/src/arch/Makefile.am b/src/arch/Makefile.am index d0d1b15..e924254 100644 --- a/src/arch/Makefile.am +++ b/src/arch/Makefile.am @@ -1,3 +1,7 @@ if BUILD_XTENSA SUBDIRS = xtensa endif + +if BUILD_HOST +SUBDIRS = host +endif diff --git a/src/arch/host/Makefile.am b/src/arch/host/Makefile.am new file mode 100644 index 0000000..7b92e00 --- /dev/null +++ b/src/arch/host/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = include diff --git a/src/arch/host/include/Makefile.am b/src/arch/host/include/Makefile.am new file mode 100644 index 0000000..f0ac9b7 --- /dev/null +++ b/src/arch/host/include/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = arch diff --git a/src/arch/host/include/arch/Makefile.am b/src/arch/host/include/arch/Makefile.am new file mode 100644 index 0000000..6dddb35 --- /dev/null +++ b/src/arch/host/include/arch/Makefile.am @@ -0,0 +1,8 @@ +includedir = $(prefix)/include/sof/arch + +include_HEADERS = \ + cache.h \ + interrupt.h \ + reef.h \ + spinlock.h \ + timer.h diff --git a/src/arch/host/include/arch/cache.h b/src/arch/host/include/arch/cache.h new file mode 100644 index 0000000..e64a6c5 --- /dev/null +++ b/src/arch/host/include/arch/cache.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __INCLUDE_ARCH_CACHE__ +#define __INCLUDE_ARCH_CACHE__ + +#include <stdint.h> +#include <stddef.h> + +static inline void dcache_writeback_region(void *addr, size_t size) {} +static inline void dcache_invalidate_region(void *addr, size_t size) {} +static inline void icache_invalidate_region(void *addr, size_t size) {} +static inline void dcache_writeback_invalidate_region(void *addr, + size_t size) {} + +#endif diff --git a/src/arch/host/include/arch/interrupt.h b/src/arch/host/include/arch/interrupt.h new file mode 100644 index 0000000..b2bb686 --- /dev/null +++ b/src/arch/host/include/arch/interrupt.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __ARCH_INTERRUPT_H +#define __ARCH_INTERRUPT_H + +#include <reef/interrupt-map.h> +#include <stdint.h> +#include <stdlib.h> +#include <unistd.h> +#include <pthread.h> + +#define PLATFORM_IRQ_CHILDREN 0 + +static inline int arch_interrupt_register(int irq, + void (*handler)(void *arg), void *arg) {return 0; } +static inline void arch_interrupt_unregister(int irq) {} +static inline uint32_t arch_interrupt_enable_mask(uint32_t mask) {return 0; } +static inline uint32_t arch_interrupt_disable_mask(uint32_t mask) {return 0; } +static inline void arch_interrupt_set(int irq) {} +static inline void arch_interrupt_clear(int irq) {} +static inline uint32_t arch_interrupt_get_enabled(void) {return 0; } +static inline uint32_t arch_interrupt_get_status(void) {return 0; } +static inline uint32_t arch_interrupt_global_disable(void) {return 0; } +static inline void arch_interrupt_global_enable(uint32_t flags) {} +static inline int arch_interrupt_init(void) {return 0; } + +#endif diff --git a/src/arch/host/include/arch/reef.h b/src/arch/host/include/arch/reef.h new file mode 100644 index 0000000..29090a2 --- /dev/null +++ b/src/arch/host/include/arch/reef.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __INCLUDE_ARCH_REEF__ +#define __INCLUDE_ARCH_REEF__ + +#include <stdint.h> +#include <stddef.h> + +#define arch_memcpy(dest, src, size) \ + memcpy(dest, src, size) + +#endif diff --git a/src/arch/host/include/arch/spinlock.h b/src/arch/host/include/arch/spinlock.h new file mode 100644 index 0000000..ea59769 --- /dev/null +++ b/src/arch/host/include/arch/spinlock.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __ARCH_SPINLOCK_H_ +#define __ARCH_SPINLOCK_H_ + +#include <stdint.h> +#include <errno.h> +#include <pthread.h> + +typedef struct { +} spinlock_t; + +static inline void arch_spinlock_init(spinlock_t *lock) {} +static inline void arch_spin_lock(spinlock_t *lock) {} +static inline void arch_spin_unlock(spinlock_t *lock) {} + +#endif diff --git a/src/arch/host/include/arch/timer.h b/src/arch/host/include/arch/timer.h new file mode 100644 index 0000000..c650da3 --- /dev/null +++ b/src/arch/host/include/arch/timer.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * + */ + +#ifndef __ARCH_TIMER_H_ +#define __ARCH_TIMER_H_ + +#include <arch/interrupt.h> +#include <stdint.h> +#include <errno.h> + +struct timer { +}; + +static inline int arch_timer_register(struct timer *timer, + void (*handler)(void *arg), void *arg) {return 0; } +static inline void arch_timer_unregister(struct timer *timer) {} +static inline void arch_timer_enable(struct timer *timer) {} +static inline void arch_timer_disable(struct timer *timer) {} +static inline uint32_t arch_timer_get_system(struct timer *timer) {return 0; } +static inline int arch_timer_set(struct timer *timer, + uint64_t ticks) {return 0; } +static inline void arch_timer_clear(struct timer *timer) {} + +#endif diff --git a/src/arch/host/include/arch/wait.h b/src/arch/host/include/arch/wait.h new file mode 100644 index 0000000..e1e23a1 --- /dev/null +++ b/src/arch/host/include/arch/wait.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +static inline void arch_wait_for_interrupt(int level) {} + +static inline void idelay(int n) {} + diff --git a/src/arch/xtensa/Makefile.am b/src/arch/xtensa/Makefile.am index b055a82..b94d14e 100644 --- a/src/arch/xtensa/Makefile.am +++ b/src/arch/xtensa/Makefile.am @@ -57,9 +57,9 @@ reef_LDADD = \ ../../tasks/libtasks.a \ ../../lib/libcore.a \ ../../platform/$(PLATFORM)/libplatform.a \ - ../../ipc/libipc.a \ + ../../ipc/libsof_ipc.a \ ../../audio/libaudio.a \ - ../../math/libmath.a \ + ../../math/libsof_math.a \ ../../drivers/libdrivers.a \ libreset.a \ xtos/libxtos.a \ diff --git a/src/audio/Makefile.am b/src/audio/Makefile.am index d19dff7..bccedbf 100644 --- a/src/audio/Makefile.am +++ b/src/audio/Makefile.am @@ -1,12 +1,1003 @@ -noinst_LIBRARIES = libaudio.a +includedir = $(prefix)/include/sof/audio -noinst_HEADERS = \ - eq_fir.h \ +include_HEADERS = \ eq_iir.h \ - fir.h \ - iir.h \ - src_config.h \ - src_core.h + eq_fir.h + +COMP_SRC = \ + eq_iir.c \ + iir.c \ + eq_fir.c \ + fir.c \ + tone.c \ + src.c \ + src_core.c \ + mixer.c \ + mux.c \ + volume.c \ + switch.c \ + dai.c \ + host.c \ + pipeline.c \ + component.c \ + buffer.c + +SOF_SRC = \ + dai.c \ + host.c \ + pipeline.c \ + component.c \ + buffer.c + +SRC_SRC = \ + src.c \ + src_core.c + +EQ_FIR_SRC = \ + eq_fir.c \ + fir.c + +EQ_IIR_SRC = \ + eq_iir.c \ + iir.c + +if BUILD_LIB + +# only host builds shared libraries, the rest are static +if BUILD_HOST + +# libsof +lib_LTLIBRARIES = libsof.la + +libsof_la_SOURCES = $(SOF_SRC) + +libsof_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src.la + +libsof_src_la_SOURCES = $(SRC_SRC) + +libsof_src_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir.la + +libsof_eq_fir_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir.la + +libsof_eq_iir_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume.la + +libsof_volume_la_SOURCES = volume.c + +libsof_volume_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux.la + +libsof_mux_la_SOURCES = mux.c + +libsof_mux_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch.la + +libsof_switch_la_SOURCES = switch.c + +libsof_switch_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer.la + +libsof_mixer_la_SOURCES = mixer.c + +libsof_mixer_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone.la + +libsof_tone_la_SOURCES = tone.c + +libsof_tone_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +if HAVE_SSE42 +# libsof +lib_LTLIBRARIES += libsof_sse42.la + +libsof_sse42_la_SOURCES = $(SOF_SRC) + +libsof_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_sse42.la + +libsof_src_sse42_la_SOURCES = $(SRC_SRC) + +libsof_src_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_sse42.la + +libsof_eq_fir_sse42_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_sse42.la + +libsof_eq_iir_sse42_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_sse42.la + +libsof_volume_sse42_la_SOURCES = volume.c + +libsof_volume_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_sse42.la + +libsof_mux_sse42_la_SOURCES = mux.c + +libsof_mux_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_sse42.la + +libsof_switch_sse42_la_SOURCES = switch.c + +libsof_switch_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_sse42.la + +libsof_mixer_sse42_la_SOURCES = mixer.c + +libsof_mixer_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_sse42.la + +libsof_tone_sse42_la_SOURCES = tone.c + +libsof_tone_sse42_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_sse42_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic +endif + +if HAVE_AVX +# libsof +lib_LTLIBRARIES += libsof_avx.la + +libsof_avx_la_SOURCES = $(SOF_SRC) + +libsof_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_avx.la + +libsof_src_avx_la_SOURCES = $(SRC_SRC) + +libsof_src_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_avx.la + +libsof_eq_fir_avx_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_avx.la + +libsof_eq_iir_avx_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_avx.la + +libsof_volume_avx_la_SOURCES = volume.c + +libsof_volume_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_avx.la + +libsof_mux_avx_la_SOURCES = mux.c + +libsof_mux_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_avx.la + +libsof_switch_avx_la_SOURCES = switch.c + +libsof_switch_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_avx.la + +libsof_mixer_avx_la_SOURCES = mixer.c + +libsof_mixer_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_avx.la + +libsof_tone_avx_la_SOURCES = tone.c + +libsof_tone_avx_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_avx_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic +endif + +if HAVE_AVX2 +# libsof +lib_LTLIBRARIES += libsof_avx2.la + +libsof_avx2_la_SOURCES = $(SOF_SRC) + +libsof_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_avx2.la + +libsof_src_avx2_la_SOURCES = $(SRC_SRC) + +libsof_src_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_avx2.la + +libsof_eq_fir_avx2_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_avx2.la + +libsof_eq_iir_avx2_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_avx2.la + +libsof_volume_avx2_la_SOURCES = volume.c + +libsof_volume_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_avx2.la + +libsof_mux_avx2_la_SOURCES = mux.c + +libsof_mux_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_avx2.la + +libsof_switch_avx2_la_SOURCES = switch.c + +libsof_switch_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_avx2.la + +libsof_mixer_avx2_la_SOURCES = mixer.c + +libsof_mixer_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_avx2.la + +libsof_tone_avx2_la_SOURCES = tone.c + +libsof_tone_avx2_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(AVX2_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_avx2_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +endif + +if HAVE_FMA +# libsof +lib_LTLIBRARIES += libsof_fma.la + +libsof_fma_la_SOURCES = $(SOF_SRC) + +libsof_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_src +lib_LTLIBRARIES += libsof_src_fma.la + +libsof_src_fma_la_SOURCES = $(SRC_SRC) + +libsof_src_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_src_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_fir +lib_LTLIBRARIES += libsof_eq_fir_fma.la + +libsof_eq_fir_fma_la_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_fir_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_eq_iir +lib_LTLIBRARIES += libsof_eq_iir_fma.la + +libsof_eq_iir_fma_la_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_eq_iir_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_volume +lib_LTLIBRARIES += libsof_volume_fma.la + +libsof_volume_fma_la_SOURCES = volume.c + +libsof_volume_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_volume_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mux +lib_LTLIBRARIES += libsof_mux_fma.la + +libsof_mux_fma_la_SOURCES = mux.c + +libsof_mux_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mux_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_switch +lib_LTLIBRARIES += libsof_switch_fma.la + +libsof_switch_fma_la_SOURCES = switch.c + +libsof_switch_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_switch_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_mixer +lib_LTLIBRARIES += libsof_mixer_fma.la + +libsof_mixer_fma_la_SOURCES = mixer.c + +libsof_mixer_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_mixer_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +# libsof_tone +lib_LTLIBRARIES += libsof_tone_fma.la + +libsof_tone_fma_la_SOURCES = tone.c + +libsof_tone_fma_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(FMA_CFLAGS) \ + $(COMMON_INCDIR) + +libsof_tone_fma_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic +endif + +else + +# Build for non host targets + +# libsof +lib_LIBRARIES = libsof.a + +libsof_a_SOURCES = $(SOF_SRC) + +libsof_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_src +lib_LIBRARIES += libsof_src.a + +libsof_src_a_SOURCES = $(SRC_SRC) + +libsof_src_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_fir +lib_LIBRARIES += libsof_eq_fir.a + +libsof_eq_fir_a_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_iir +lib_LIBRARIES += libsof_eq_iir.a + +libsof_eq_iir_a_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_volume +lib_LIBRARIES += libsof_volume.a + +libsof_volume_a_SOURCES = volume.c + +libsof_volume_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mux +lib_LIBRARIES += libsof_mux.a + +libsof_mux_a_SOURCES = mux.c + +libsof_mux_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_switch +lib_LIBRARIES += libsof_switch.a + +libsof_switch_a_SOURCES = switch.c + +libsof_switch_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mixer +lib_LIBRARIES += libsof_mixer.a + +libsof_mixer_a_SOURCES = mixer.c + +libsof_mixer_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_tone +lib_LIBRARIES += libsof_tone.a + +libsof_tone_a_SOURCES = tone.c + +libsof_tone_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) + + +if HAVE_HIFI2EP +# libsof +lib_LIBRARIES += libsof_hifi2ep.a + +libsof_hifi2ep_a_SOURCES = $(SOF_SRC) + +libsof_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_src +lib_LIBRARIES += libsof_src_hifi2ep.a + +libsof_src_hifi2ep_a_SOURCES = $(SRC_SRC) + +libsof_src_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_fir +lib_LIBRARIES += libsof_eq_fir_hifi2ep.a + +libsof_eq_fir_hifi2ep_a_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_iir +lib_LIBRARIES += libsof_eq_iir_hifi2ep.a + +libsof_eq_iir_hifi2ep_a_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_volume +lib_LIBRARIES += libsof_volume_hifi2ep.a + +libsof_volume_hifi2ep_a_SOURCES = volume.c + +libsof_volume_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mux +lib_LIBRARIES += libsof_mux_hifi2ep.a + +libsof_mux_hifi2ep_a_SOURCES = mux.c + +libsof_mux_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_switch +lib_LIBRARIES += libsof_switch_hifi2ep.a + +libsof_switch_hifi2ep_a_SOURCES = switch.c + +libsof_switch_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mixer +lib_LIBRARIES += libsof_mixer_hifi2ep.a + +libsof_mixer_hifi2ep_a_SOURCES = mixer.c + +libsof_mixer_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_tone +lib_LIBRARIES += libsof_tone_hifi2ep.a + +libsof_tone_hifi2ep_a_SOURCES = tone.c + +libsof_tone_hifi2ep_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) +endif + +if HAVE_HIFI3 +# libsof +lib_LIBRARIES += libsof_hifi3.a + +libsof_hifi3_a_SOURCES = $(COMP_SRC) + +libsof_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_src +lib_LIBRARIES += libsof_src_hifi3.a + +libsof_src_hifi3_a_SOURCES = $(SRC_SRC) + +libsof_src_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_fir +lib_LIBRARIES += libsof_eq_fir_hifi3.a + +libsof_eq_fir_hifi3_a_SOURCES = $(EQ_FIR_SRC) + +libsof_eq_fir_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_eq_iir +lib_LIBRARIES += libsof_eq_iir_hifi3.a + +libsof_eq_iir_hifi3_a_SOURCES = $(EQ_IIR_SRC) + +libsof_eq_iir_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_volume +lib_LIBRARIES += libsof_volume_hifi3.a + +libsof_volume_hifi3_a_SOURCES = volume.c + +libsof_volume_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mux +lib_LIBRARIES += libsof_mux_hifi3.a + +libsof_mux_hifi3_a_SOURCES = mux.c + +libsof_mux_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_switch +lib_LIBRARIES += libsof_switch_hifi3.a + +libsof_switch_hifi3_a_SOURCES = switch.c + +libsof_switch_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_mixer +lib_LIBRARIES += libsof_mixer_hifi3.a + +libsof_mixer_hifi3_a_SOURCES = mixer.c + +libsof_mixer_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) + +# libsof_tone +lib_LIBRARIES += libsof_tone_hifi3.a + +libsof_tone_hifi3_a_SOURCES = tone.c + +libsof_tone_hifi3_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(SSE42_CFLAGS) \ + $(COMMON_INCDIR) +endif + +endif + +else + +# build for firmware image + +noinst_LIBRARIES = libaudio.a libaudio_a_SOURCES = \ eq_iir.c \ @@ -29,6 +1020,6 @@ libaudio_a_SOURCES = \ libaudio_a_CFLAGS = \ $(ARCH_CFLAGS) \ - $(REEF_INCDIR) \ - $(ARCH_INCDIR) \ - $(PLATFORM_INCDIR) + $(COMMON_INCDIR) + +endif diff --git a/src/include/reef/Makefile.am b/src/include/reef/Makefile.am index 50ffada..f4d46f2 100644 --- a/src/include/reef/Makefile.am +++ b/src/include/reef/Makefile.am @@ -1,7 +1,11 @@ SUBDIRS = audio math noinst_HEADERS = \ - agent.h \ + agent.h + +includedir = $(prefix)/include/sof/reef + +include_HEADERS = \ alloc.h \ clock.h \ dai.h \ diff --git a/src/include/reef/audio/Makefile.am b/src/include/reef/audio/Makefile.am index 60b7145..1d2b9cb 100644 --- a/src/include/reef/audio/Makefile.am +++ b/src/include/reef/audio/Makefile.am @@ -1,7 +1,9 @@ SUBDIRS = coefficients -noinst_HEADERS = \ +includedir = $(prefix)/include/sof/reef/audio + +include_HEADERS = \ component.h \ pipeline.h \ - buffer.h \ - format.h + format.h \ + buffer.h diff --git a/src/include/uapi/Makefile.am b/src/include/uapi/Makefile.am index 257fff0..327f97d 100644 --- a/src/include/uapi/Makefile.am +++ b/src/include/uapi/Makefile.am @@ -1,4 +1,4 @@ -includedir = $(prefix)/include/sof +includedir = $(prefix)/include/sof/uapi include_HEADERS = \ ipc.h \ diff --git a/src/ipc/Makefile.am b/src/ipc/Makefile.am index bd83f60..1d84dd0 100644 --- a/src/ipc/Makefile.am +++ b/src/ipc/Makefile.am @@ -1,7 +1,22 @@ -noinst_LIBRARIES = libipc.a +if BUILD_LIB +lib_LTLIBRARIES = libsof_ipc.la + +libsof_ipc_la_SOURCES = \ + ipc.c + +libsof_ipc_la_LDFLAGS = \ + -version-info `echo $(VERSION) | cut -d '.' -f 1` \ + -no-undefined \ + -export-dynamic + +libsof_ipc_la_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) +else +noinst_LIBRARIES = libsof_ipc.a if BUILD_BAYTRAIL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ byt-ipc.c \ @@ -10,7 +25,7 @@ libipc_a_SOURCES = \ endif if BUILD_CHERRYTRAIL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ byt-ipc.c \ @@ -19,7 +34,7 @@ libipc_a_SOURCES = \ endif if BUILD_BROADWELL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ hsw-ipc.c \ @@ -27,15 +42,16 @@ libipc_a_SOURCES = \ endif if BUILD_HASWELL -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ hsw-ipc.c \ dma-copy.c endif + if BUILD_APOLLOLAKE -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ apl-ipc.c \ @@ -43,16 +59,15 @@ libipc_a_SOURCES = \ endif if BUILD_CANNONLAKE -libipc_a_SOURCES = \ +libsof_ipc_a_SOURCES = \ ipc.c \ intel-ipc.c \ cnl-ipc.c \ dma-copy.c endif -libipc_a_CFLAGS = \ +libsof_ipc_a_CFLAGS = \ $(ARCH_CFLAGS) \ - $(ARCH_INCDIR) \ - $(REEF_INCDIR) \ - $(PLATFORM_INCDIR) + $(COMMON_INCDIR) +endif diff --git a/src/library/Makefile.am b/src/library/Makefile.am new file mode 100644 index 0000000..7b92e00 --- /dev/null +++ b/src/library/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = include diff --git a/src/library/include/Makefile.am b/src/library/include/Makefile.am new file mode 100644 index 0000000..912728c --- /dev/null +++ b/src/library/include/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = platform diff --git a/src/library/include/platform/Makefile.am b/src/library/include/platform/Makefile.am new file mode 100644 index 0000000..5a735ae --- /dev/null +++ b/src/library/include/platform/Makefile.am @@ -0,0 +1,12 @@ +includedir = $(prefix)/include/sof/platform + +include_HEADERS = \ + clk.h \ + dma.h \ + interrupt.h \ + mailbox.h \ + memory.h \ + platform.h \ + pmc.h \ + shim.h \ + timer.h diff --git a/src/library/include/platform/clk.h b/src/library/include/platform/clk.h new file mode 100644 index 0000000..0dd11e6 --- /dev/null +++ b/src/library/include/platform/clk.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_CLOCK__ +#define __PLATFORM_HOST_CLOCK__ + +#define CLK_CPU 0 +#define CLK_SSP 1 + +#define CLK_DEFAULT_CPU_HZ 50000000 +#define CLK_MAX_CPU_HZ 343000000 + +void init_platform_clocks(void); + +#endif diff --git a/src/library/include/platform/dma.h b/src/library/include/platform/dma.h new file mode 100644 index 0000000..457da8a --- /dev/null +++ b/src/library/include/platform/dma.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_DMA_H__ +#define __PLATFORM_HOST_DMA_H__ + +#include <stdint.h> + +#define DMA_ID_DMAC0 0 +#define DMA_ID_DMAC1 1 + +#define DMA_DEV_PCM 0 +#define DMA_DEV_WAV 1 + +#endif diff --git a/src/library/include/platform/interrupt.h b/src/library/include/platform/interrupt.h new file mode 100644 index 0000000..eb0fbfd --- /dev/null +++ b/src/library/include/platform/interrupt.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __INCLUDE_PLATFORM_HOST_INTERRUPT__ +#define __INCLUDE_PLATFORM_HOST_INTERRUPT__ + +#include <stdint.h> +#include <reef/interrupt-map.h> + +/* IRQ numbers */ +#define IRQ_NUM_SOFTWARE0 0 /* Level 1 */ +#define IRQ_NUM_TIMER1 1 /* Level 1 */ +#define IRQ_NUM_SOFTWARE1 2 /* Level 1 */ +#define IRQ_NUM_SOFTWARE2 3 /* Level 1 */ +#define IRQ_NUM_TIMER2 5 /* Level 2 */ +#define IRQ_NUM_SOFTWARE3 6 /* Level 2 */ +#define IRQ_NUM_TIMER3 7 /* Level 3 */ +#define IRQ_NUM_SOFTWARE4 8 /* Level 3 */ +#define IRQ_NUM_SOFTWARE5 9 /* Level 3 */ +#define IRQ_NUM_EXT_IA 10 /* Level 4 */ +#define IRQ_NUM_EXT_PMC 11 /* Level 4 */ +#define IRQ_NUM_SOFTWARE6 12 /* Level 5 */ +#define IRQ_NUM_EXT_DMAC0 13 /* Level 5 */ +#define IRQ_NUM_EXT_DMAC1 14 /* Level 5 */ +#define IRQ_NUM_EXT_TIMER 15 /* Level 5 */ +#define IRQ_NUM_EXT_SSP0 16 /* Level 5 */ +#define IRQ_NUM_EXT_SSP1 17 /* Level 5 */ +#define IRQ_NUM_EXT_SSP2 18 /* Level 5 */ +#define IRQ_NUM_NMI 20 /* Level 7 */ + +/* IRQ Masks */ +#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0) +#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1) +#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1) +#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2) +#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2) +#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3) +#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3) +#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4) +#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5) +#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA) +#define IRQ_MASK_EXT_PMC (1 << IRQ_NUM_EXT_PMC) +#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6) +#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0) +#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1) +#define IRQ_MASK_EXT_TIMER (1 << IRQ_NUM_EXT_TIMER) +#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0) +#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1) +#define IRQ_MASK_EXT_SSP2 (1 << IRQ_NUM_EXT_SSP2) + +#endif diff --git a/src/library/include/platform/mailbox.h b/src/library/include/platform/mailbox.h new file mode 100644 index 0000000..650ab47 --- /dev/null +++ b/src/library/include/platform/mailbox.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __INCLUDE_PLATFORM_HOST_MAILBOX__ +#define __INCLUDE_PLATFORM_HOST_MAILBOX__ + +#include <platform/memory.h> + +#define MAILBOX_HOST_OFFSET 0x144000 + +#define MAILBOX_OUTBOX_OFFSET 0x0 +#define MAILBOX_OUTBOX_SIZE 0x400 +#define MAILBOX_OUTBOX_BASE \ + (MAILBOX_BASE + MAILBOX_OUTBOX_OFFSET) + +#define MAILBOX_INBOX_OFFSET MAILBOX_OUTBOX_SIZE +#define MAILBOX_INBOX_SIZE 0x400 +#define MAILBOX_INBOX_BASE \ + (MAILBOX_BASE + MAILBOX_INBOX_OFFSET) + +#define MAILBOX_EXCEPTION_OFFSET \ + (MAILBOX_INBOX_SIZE + MAILBOX_OUTBOX_SIZE) +#define MAILBOX_EXCEPTION_SIZE 0x100 +#define MAILBOX_EXCEPTION_BASE \ + (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET) + +#define MAILBOX_DEBUG_OFFSET \ + (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET) +#define MAILBOX_DEBUG_SIZE 0x100 +#define MAILBOX_DEBUG_BASE \ + (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET) + +#define MAILBOX_STREAM_OFFSET \ + (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET) +#define MAILBOX_STREAM_SIZE 0x200 +#define MAILBOX_STREAM_BASE \ + (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) + +#define MAILBOX_TRACE_OFFSET \ + (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET) +#define MAILBOX_TRACE_SIZE 0x380 +#define MAILBOX_TRACE_BASE \ + (MAILBOX_BASE + MAILBOX_TRACE_OFFSET) + +#endif diff --git a/src/library/include/platform/memory.h b/src/library/include/platform/memory.h new file mode 100644 index 0000000..78541e7 --- /dev/null +++ b/src/library/include/platform/memory.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_MEMORY_H__ +#define __PLATFORM_HOST_MEMORY_H__ + +#include <config.h> + +#if CONFIG_HT_BAYTRAIL +#include <baytrail/include/platform/memory.h> +#endif + +#define HEAP_BUFFER_SIZE (1024 * 128) + +#if 0 +/* physical DSP addresses */ + +#define IRAM_BASE 0xFF2C0000 +#define IRAM_SIZE 0x00014000 + +#define DRAM0_BASE 0xFF300000 +#define DRAM0_SIZE 0x00028000 +#define DRAM0_VBASE 0xC0000000 + +#define MAILBOX_BASE (DRAM0_BASE + DRAM0_SIZE - 0x2000) + + +/* HEAP Constants - WARNING this MUST be aligned with the linker script */ +/* TODO:preproces linker script with this header to align automatically. */ + +/* Heap section sizes for module pool */ +#define HEAP_MOD_COUNT8 0 +#define HEAP_MOD_COUNT16 256 +#define HEAP_MOD_COUNT32 128 +#define HEAP_MOD_COUNT64 64 +#define HEAP_MOD_COUNT128 32 +#define HEAP_MOD_COUNT256 16 +#define HEAP_MOD_COUNT512 8 +#define HEAP_MOD_COUNT1024 4 + +/* total Heap for modules - must be aligned with linker script !!! */ +#define HEAP_MOD_SIZE \ + (HEAP_MOD_COUNT8 * 8 + HEAP_MOD_COUNT16 * 16 + \ + HEAP_MOD_COUNT32 * 32 + HEAP_MOD_COUNT64 * 64 + \ + HEAP_MOD_COUNT128 * 128 + HEAP_MOD_COUNT256 * 256 + \ + HEAP_MOD_COUNT512 * 512 + HEAP_MOD_COUNT1024 * 1024) + +/* Heap for buffers */ +#define HEAP_BUF_BLOCK_SIZE 1024 +#define HEAP_BUF_COUNT 111 +#define HEAP_BUF_SIZE (HEAP_BUF_BLOCK_SIZE * HEAP_BUF_COUNT) + +/* Remaining DRAM for Stack, data and BSS. + * TODO: verify no overflow during build + */ +#define SYSTEM_MEM \ + (DRAM0_SIZE - HEAP_MOD_SIZE - HEAP_BUF_SIZE) + +#endif +#endif diff --git a/src/library/include/platform/platform.h b/src/library/include/platform/platform.h new file mode 100644 index 0000000..a429e84 --- /dev/null +++ b/src/library/include/platform/platform.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_PLATFORM_H__ +#define __PLATFORM_HOST_PLATFORM_H__ + +#include <platform/shim.h> +#include <platform/interrupt.h> +#include <stdio.h> +#include <stdlib.h> + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 4 +#define PLATFORM_MAX_STREAMS 5 + +/* DMA channel drain timeout in microseconds */ +#define PLATFORM_DMA_TIMEOUT 1333 + +/* IPC page data copy timeout */ +#define PLATFORM_IPC_DMA_TIMEOUT 2000 + + +#endif diff --git a/src/library/include/platform/pmc.h b/src/library/include/platform/pmc.h new file mode 100644 index 0000000..d54fc1c --- /dev/null +++ b/src/library/include/platform/pmc.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_PMC_H__ +#define __PLATFORM_HOST_PMC_H__ + +#include <stdint.h> + + +int platform_ipc_pmc_init(void); +int ipc_pmc_send_msg(uint32_t message); +int pmc_process_msg_queue(void); + +#endif diff --git a/src/library/include/platform/shim.h b/src/library/include/platform/shim.h new file mode 100644 index 0000000..d6d94d4 --- /dev/null +++ b/src/library/include/platform/shim.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + +#ifndef __PLATFORM_HOST_SHIM_H__ +#define __PLATFORM_HOST_SHIM_H__ + +#include <platform/memory.h> +#include <stdint.h> + +static inline uint32_t shim_read(uint32_t reg) {return 0; } +static inline void shim_write(uint32_t reg, uint32_t val) {} + +#endif diff --git a/src/library/include/platform/timer.h b/src/library/include/platform/timer.h new file mode 100644 index 0000000..3521e4c --- /dev/null +++ b/src/library/include/platform/timer.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + */ + + +#ifndef __PLATFORM_HOST_TIMER_H__ +#define __PLATFORM_HOST_TIMER_H__ + +#include <stdint.h> +#include <reef/timer.h> +#include <platform/interrupt.h> + +struct comp_dev; +struct sof_ipc_stream_posn; + +/* get timestamp for host stream DMA position */ +static inline void platform_host_timestamp(struct comp_dev *host, + struct sof_ipc_stream_posn *posn) {} + +/* get timestamp for DAI stream DMA position */ +static inline void platform_dai_timestamp(struct comp_dev *dai, + struct sof_ipc_stream_posn *posn) {} + +/* get current wallclock for componnent */ +static inline void platform_dai_wallclock(struct comp_dev *dai, + uint64_t *wallclock) {} + +#endif diff --git a/src/math/Makefile.am b/src/math/Makefile.am index b795afa..6a48e29 100644 --- a/src/math/Makefile.am +++ b/src/math/Makefile.am @@ -1,11 +1,21 @@ -noinst_LIBRARIES = libmath.a +if BUILD_LIB +lib_LTLIBRARIES = libsof_math.la -libmath_a_SOURCES = \ +libsof_math_la_SOURCES = \ trig.c \ numbers.c -libmath_a_CFLAGS = \ +libsof_math_la_CFLAGS = \ $(ARCH_CFLAGS) \ - $(REEF_INCDIR) \ - $(ARCH_INCDIR) \ - $(PLATFORM_INCDIR) + $(COMMON_INCDIR) +else +noinst_LIBRARIES = libsof_math.a + +libsof_math_a_SOURCES = \ + trig.c \ + numbers.c + +libsof_math_a_CFLAGS = \ + $(ARCH_CFLAGS) \ + $(COMMON_INCDIR) +endif -- 2.11.0

1 0

[Sound-open-firmware] [PATCH] rimage: Add support for multiple modules with code signing
by Liam Girdwood 23 Jan '18

23 Jan '18

Add support so that rimage can take as it's input multiple ELF modules and merge them into a single signed manifest and firmware binary. Remove all hard coded module descriptions. Module metadata is now read from the ELF "module" section. Remove duplicated and unused code for creating simple firmware images as used on Baytrail and Haswell. Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- configure.ac | 10 + rimage/Makefile.am | 21 +- rimage/baytrail.c | 234 ------------------ rimage/cherrytrail.c | 63 ----- rimage/cse.c | 45 ++++ rimage/cse.h | 42 ++++ rimage/css.c | 71 ++++++ rimage/css.h | 69 ++++++ rimage/elf.c | 523 +++++++++++++++++++++++++++++++++++++++ rimage/file_format.h | 7 +- rimage/file_simple.c | 308 +++++++++++++++++++++++ rimage/hash.c | 72 ++++++ rimage/keys/Makefile.am | 9 + rimage/keys/README | 34 +++ rimage/keys/otc_private_key.pem | 28 +++ rimage/keys/otc_public_key.pem | 9 + rimage/man_apl.c | 144 +++++++++++ rimage/man_cnl.c | 143 +++++++++++ rimage/manifest.c | 532 ++++++++++++++++++++++++++++++++++++++++ rimage/manifest.h | 90 +++++++ rimage/pkcs1_5.c | 140 +++++++++++ rimage/plat_auth.c | 50 ++++ rimage/plat_auth.h | 92 +++++++ rimage/rimage.c | 258 ++++--------------- rimage/rimage.h | 146 +++++++---- 25 files changed, 2572 insertions(+), 568 deletions(-) delete mode 100644 rimage/baytrail.c delete mode 100644 rimage/cherrytrail.c create mode 100644 rimage/cse.c create mode 100644 rimage/cse.h create mode 100644 rimage/css.c create mode 100644 rimage/css.h create mode 100644 rimage/elf.c create mode 100644 rimage/file_simple.c create mode 100644 rimage/hash.c create mode 100644 rimage/keys/Makefile.am create mode 100644 rimage/keys/README create mode 100644 rimage/keys/otc_private_key.pem create mode 100644 rimage/keys/otc_public_key.pem create mode 100644 rimage/man_apl.c create mode 100644 rimage/man_cnl.c create mode 100644 rimage/manifest.c create mode 100644 rimage/manifest.h create mode 100644 rimage/pkcs1_5.c create mode 100644 rimage/plat_auth.c create mode 100644 rimage/plat_auth.h diff --git a/configure.ac b/configure.ac index 8c65760..6e9c758 100644 --- a/configure.ac +++ b/configure.ac @@ -4,6 +4,7 @@ AC_INIT([sof-tools], [1.0.1]) AM_INIT_AUTOMAKE([foreign]) AC_CONFIG_SRCDIR([rimage/rimage.c]) AC_CONFIG_HEADERS([config.h]) +AC_CHECK_HEADER([sof/manifest.h]) AC_CANONICAL_HOST @@ -12,9 +13,17 @@ AM_MAINTAINER_MODE([enable]) AC_PROG_CC +#check for openssl +AC_CHECK_LIB([crypto], [OPENSSL_config], , [AC_MSG_ERROR([Need OpenSSL libcrypto])]) + +PEM_KEY_PREFIX="/usr/local/share/rimage" +AC_DEFINE_UNQUOTED([PEM_KEY_PREFIX], ["$PEM_KEY_PREFIX"], ["Path for PEM keys"]) +AC_SUBST(PEM_KEY_PREFIX) + AC_OUTPUT([ Makefile rimage/Makefile + rimage/keys/Makefile rmbox/Makefile topology/Makefile topology/common/Makefile @@ -27,6 +36,7 @@ AC_OUTPUT([ echo " prefix: ${prefix} +PEM: ${PEM_KEY_PREFIX} Compiler: ${CC} CFLAGS: ${CFLAGS} " diff --git a/rimage/Makefile.am b/rimage/Makefile.am index 0ba8ce6..467bfe6 100644 --- a/rimage/Makefile.am +++ b/rimage/Makefile.am @@ -1,10 +1,25 @@ +SUBDIRS=keys + bin_PROGRAMS = rimage noinst_HEADERS = \ - rimage.h + rimage.h \ + css.h \ + cse.h \ + plat_auth.h \ + manifest.h \ + file_format.h rimage_SOURCES = \ - cherrytrail.c \ - baytrail.c \ + file_simple.c \ + man_apl.c \ + man_cnl.c \ + cse.c \ + css.c \ + plat_auth.c \ + hash.c \ + pkcs1_5.c \ + manifest.c \ + elf.c \ rimage.c diff --git a/rimage/baytrail.c b/rimage/baytrail.c deleted file mode 100644 index ed1c840..0000000 --- a/rimage/baytrail.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * ELF to firmware image creator. - * - * Copyright (c) 2015, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - - -#include <stdlib.h> -#include <stdio.h> -#include <unistd.h> -#include <errno.h> -#include <string.h> - -#include "rimage.h" -#include "file_format.h" - -/* taken from the linker scripts */ -static const struct section byt_sections[] = { - {"ResetVector", 0xff2c0000, 0x2e0}, - {"ResetVector.literal", 0xff2c02e0, 0x120}, - {"WindowVectors", 0xff2c0400, 0x178}, - {"Level2InterruptVector.literal", 0xff2c0578, 0x4}, - {"Level2InterruptVector", 0xff2c057c, 0x1c}, - {"Level3InterruptVector.literal", 0xff2c0598, 0x4}, - {"Level3InterruptVector", 0xff2c059c, 0x1c}, - {"Level4InterruptVector.literal", 0xff2c05b8, 0x4}, - {"Level4InterruptVector", 0xff2c05bc, 0x1c}, - {"Level5InterruptVector.literal", 0xff2c05d8, 0x4}, - {"Level5InterruptVector", 0xff2c05dc, 0x1c}, - {"DebugInterruptVector.literal", 0xff2c05d8, 0x4}, - {"NMIExceptionVector", 0xff2c061c}, -}; - -static int is_iram(struct image *image, Elf32_Shdr *section) -{ - const struct adsp *adsp = image->adsp; - uint32_t start, end; - - start = section->sh_addr; - end = section->sh_addr + section->sh_size; - - if (start < adsp->iram_base) - return 0; - if (start >= adsp->iram_base + adsp->iram_size) - return 0; - return 1; -} - -static int is_dram(struct image *image, Elf32_Shdr *section) -{ - const struct adsp *adsp = image->adsp; - uint32_t start, end; - - start = section->sh_addr; - end = section->sh_addr + section->sh_size; - - if (start < adsp->dram_base) - return 0; - if (start >= adsp->dram_base + adsp->dram_size) - return 0; - return 1; -} - -static int block_idx = 0; - -static int write_block(struct image *image, Elf32_Shdr *section) -{ - const struct adsp *adsp = image->adsp; - struct snd_sof_blk_hdr block; - size_t count; - void *buffer; - int ret; - - block.size = section->sh_size; - - if (is_iram(image, section)) { - block.type = SOF_BLK_TEXT; - block.offset = section->sh_addr - adsp->iram_base - + adsp->host_iram_offset; - } else if (is_dram(image, section)) { - block.type = SOF_BLK_DATA; - block.offset = section->sh_addr - adsp->dram_base - + adsp->host_dram_offset; - } else { - fprintf(stderr, "error: invalid block address/size 0x%x/0x%x\n", - section->sh_addr, section->sh_size); - return -EINVAL; - } - - /* write header */ - count = fwrite(&block, sizeof(block), 1, image->out_fd); - if (count != 1) - return -errno; - - /* alloc data data */ - buffer = calloc(1, section->sh_size); - if (buffer == NULL) - return -ENOMEM; - - /* read in section data */ - ret = fseek(image->in_fd, section->sh_offset, SEEK_SET); - if (ret < 0) { - fprintf(stderr, "error: cant seek to section %d\n", ret); - goto out; - } - count = fread(buffer, 1, section->sh_size, image->in_fd); - if (count != section->sh_size) { - fprintf(stderr, "error: cant read section %d\n", -errno); - ret = -errno; - goto out; - } - - /* write out section data */ - count = fwrite(buffer, 1, section->sh_size, image->out_fd); - if (count != section->sh_size) { - fprintf(stderr, "error: cant write section %d\n", -errno); - fprintf(stderr, " foffset %d size 0x%x mem addr 0x%x\n", - section->sh_offset, section->sh_size, section->sh_addr); - ret = -errno; - goto out; - } - - if (image->verbose) { - fprintf(stdout, "block: %d\n foffset %d\n size 0x%x\n mem addr 0x%x\n", - block_idx++, section->sh_offset, section->sh_size, - section->sh_addr); - } - -out: - free(buffer); - return ret; -} - -/* used by others */ -int byt_write_modules(struct image *image) -{ - const struct adsp *adsp = image->adsp; - struct snd_sof_mod_hdr hdr; - Elf32_Shdr *section; - size_t count; - int i, err; - uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); - - fprintf(stdout, "Using BYT file format\n"); - - hdr.num_blocks = image->num_sections - image->num_bss; - hdr.size = image->text_size + image->data_size + - sizeof(struct snd_sof_blk_hdr) * hdr.num_blocks; - hdr.type = SOF_FW_BASE; - - count = fwrite(&hdr, sizeof(hdr), 1, image->out_fd); - if (count != 1) { - fprintf(stderr, "error: failed to write section header %d\n", - -errno); - return -errno ; - } - - for (i = 0; i < image->hdr.e_shnum; i++) { - - section = &image->section[i]; - - /* only write valid sections */ - if (!(image->section[i].sh_flags & valid)) - continue; - - /* dont write bss */ - if (section->sh_type == SHT_NOBITS) - continue; - - err = write_block(image, section); - if (err < 0) { - fprintf(stderr, "error: failed to write section #%d\n", i); - return err; - } - } - - return 0; -} - -/* used by others */ -int byt_write_header(struct image *image) -{ - struct snd_sof_fw_header hdr; - size_t count; - - memcpy(hdr.sig, SND_SOF_FW_SIG, SND_SOF_FW_SIG_SIZE); - - hdr.num_modules = 1; - hdr.abi = SND_SOF_FW_ABI; - - image->fw_size += sizeof(struct snd_sof_blk_hdr) * - (image->num_sections - image->num_bss); - image->fw_size += sizeof(struct snd_sof_mod_hdr) * hdr.num_modules; - hdr.file_size = image->fw_size; - - fprintf(stdout, "fw: image size %ld (0x%lx) bytes %d modules\n\n", - hdr.file_size + sizeof(hdr), hdr.file_size + sizeof(hdr), - hdr.num_modules); - count = fwrite(&hdr, sizeof(hdr), 1, image->out_fd); - if (count != 1) - return -errno; - - return 0; -} - -#define IRAM_OFFSET 0x0C0000 -#define IRAM_SIZE (80 * 1024) -#define DRAM_OFFSET 0x100000 -#define DRAM_SIZE (160 * 1024) - -const struct adsp byt_machine = { - .name = "byt", - .iram_base = 0xff2c0000, - .iram_size = 0x14000, - .host_iram_offset = IRAM_OFFSET, - .dram_base = 0xff300000, - .dram_size = 0x28000, - .host_dram_offset = DRAM_OFFSET, - .machine_id = MACHINE_BAYTRAIL, - .ops = { - .write_header = byt_write_header, - .write_modules = byt_write_modules, - }, - .sections = byt_sections, -}; diff --git a/rimage/cherrytrail.c b/rimage/cherrytrail.c deleted file mode 100644 index e27bea6..0000000 --- a/rimage/cherrytrail.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * ELF to firmware image creator. - * - * Copyright (c) 2015, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - - -#include <stdlib.h> -#include <stdio.h> -#include <unistd.h> -#include <errno.h> -#include <string.h> - -#include "rimage.h" -#include "file_format.h" - -/* TODO: need to config CHT values */ -static const struct section cht_sections[] = { - {"ResetVector", 0xff2c0000, 0x2e0}, - {"ResetVector.literal", 0xff2c02e0, 0x120}, - {"WindowVectors", 0xff2c0400, 0x178}, - {"Level2InterruptVector.literal", 0xff2c0578, 0x4}, - {"Level2InterruptVector", 0xff2c057c, 0x1c}, - {"Level3InterruptVector.literal", 0xff2c0598, 0x4}, - {"Level3InterruptVector", 0xff2c059c, 0x1c}, - {"Level4InterruptVector.literal", 0xff2c05b8, 0x4}, - {"Level4InterruptVector", 0xff2c05bc, 0x1c}, - {"Level5InterruptVector.literal", 0xff2c05d8, 0x4}, - {"Level5InterruptVector", 0xff2c05dc, 0x1c}, - {"DebugInterruptVector.literal", 0xff2c05d8, 0x4}, - {"NMIExceptionVector", 0xff2c061c}, -}; - -#define IRAM_OFFSET 0x0C0000 -#define IRAM_SIZE (80 * 1024) -#define DRAM_OFFSET 0x100000 -#define DRAM_SIZE (160 * 1024) - -const struct adsp cht_machine = { - .name = "cht", - .iram_base = 0xff2c0000, - .iram_size = 0x14000, - .host_iram_offset = IRAM_OFFSET, - .dram_base = 0xff300000, - .dram_size = 0x28000, - .host_dram_offset = DRAM_OFFSET, - .machine_id = MACHINE_CHERRYTRAIL, - .ops = { - .write_header = byt_write_header, - .write_modules = byt_write_modules, - }, - .sections = cht_sections, -}; - diff --git a/rimage/cse.c b/rimage/cse.c new file mode 100644 index 0000000..b560415 --- /dev/null +++ b/rimage/cse.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#include <stdio.h> +#include "rimage.h" +#include "cse.h" +#include "manifest.h" + +void ri_cse_create(struct image *image) +{ + struct CsePartitionDirHeader *cse_hdr = image->fw_image; + struct sof_man_adsp_meta_file_ext *meta = image->fw_image + + MAN_META_EXT_OFFSET; + struct CsePartitionDirEntry *cse_entry = + image->fw_image + sizeof(*cse_hdr); + uint8_t csum = 0, *val = image->fw_image; + int i, size; + + fprintf(stdout, " cse: completing CSE manifest\n"); + + cse_entry[2].length = meta->comp_desc[0].limit_offset - + MAN_DESC_OFFSET; + + /* calculate checksum using BSD algo */ + size = sizeof(*cse_hdr) + sizeof(*cse_entry) * MAN_CSE_PARTS; + for (i = 0; i < size; i++) { + if (i == 11) + continue; + csum += val[i]; + } + cse_hdr->checksum = 0x100 - csum; +} diff --git a/rimage/cse.h b/rimage/cse.h new file mode 100644 index 0000000..28650da --- /dev/null +++ b/rimage/cse.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSE_H__ +#define __CSE_H__ + +#include <stdint.h> + +struct image; + +#define CSE_HEADER_MAKER 0x44504324 /* "DPC$" */ + +struct CsePartitionDirHeader { + uint32_t header_marker; + uint32_t nb_entries; + uint8_t header_version; + uint8_t entry_version; + uint8_t header_length; + uint8_t checksum; + uint8_t partition_name[4]; +} __attribute__((packed)); + +struct CsePartitionDirEntry { + uint8_t entry_name[12]; + uint32_t offset; + uint32_t length; + uint32_t reserved; +} __attribute__((packed)); + +void ri_cse_create(struct image *image); + +#endif diff --git a/rimage/css.c b/rimage/css.c new file mode 100644 index 0000000..f662f0b --- /dev/null +++ b/rimage/css.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#include <stdio.h> +#include <sys/time.h> +#include "rimage.h" +#include "css.h" +#include "manifest.h" + +void ri_css_hdr_create(struct image *image) +{ + struct css_header *css = image->fw_image + MAN_CSS_HDR_OFFSET; + struct tm *date; + struct timeval tv; + time_t time; + int val; + + fprintf(stdout, " cse: completing CSS manifest\n"); + + /* get local time and date */ + gettimeofday(&tv, NULL); + date = localtime(&tv.tv_sec); + date->tm_year += 1900; + fprintf(stdout, " css: set build date to %d:%2.2d:%2.2d\n", + date->tm_year, date->tm_mon, date->tm_mday); + + /* year yYyy */ + val = date->tm_year / 1000; + css->date |= val << 28; + date->tm_year -= val * 1000; + /* year yyYy */ + val = date->tm_year / 100; + css->date |= val << 24; + date->tm_year -= val * 100; + /* year yyyY */ + val = date->tm_year / 10; + css->date |= val << 20; + date->tm_year -= val * 10; + /* year Yyyy */ + val = date->tm_year; + css->date |= val << 16; + + /* month Mm - for some reason month starts at 0 */ + val = ++date->tm_mon / 10; + css->date |= val << 12; + date->tm_mon -= (val * 10); + /* month mM */ + val = date->tm_mon; + css->date |= val << 8; + + /* Day Dd */ + val = date->tm_mday / 10; + css->date |= val << 4; + date->tm_mday -= (val * 10); + /* Day dD */ + val = date->tm_mday; + css->date |= val << 0; +} diff --git a/rimage/css.h b/rimage/css.h new file mode 100644 index 0000000..0516f53 --- /dev/null +++ b/rimage/css.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSS_H__ +#define __CSS_H__ + +#include <stdint.h> + +struct image; + +#define MAN_CSS_MOD_TYPE 4 +#define MAN_CSS_HDR_SIZE 161 /* in words */ +#define MAN_CSS_HDR_VERSION 0x10000 +#define MAN_CSS_MOD_VENDOR 0x8086 +#define MAN_CSS_HDR_ID {'$', 'M', 'N', '2'} + +#define MAN_CSS_KEY_SIZE (MAN_RSA_KEY_MODULUS_LEN >> 2) +#define MAN_CSS_MOD_SIZE (MAN_RSA_KEY_MODULUS_LEN >> 2) +#define MAN_CSS_EXP_SIZE (MAN_RSA_KEY_EXPONENT_LEN >> 2) +#define MAN_CSS_MAN_SIZE \ + (sizeof(struct fw_image_manifest) >> 2) + +/* + * RSA Key and Crypto + */ +#define MAN_RSA_KEY_MODULUS_LEN 256 +#define MAN_RSA_KEY_EXPONENT_LEN 4 +#define MAN_RSA_SIGNATURE_LEN 256 + +struct fw_version { + uint16_t major_version; + uint16_t minor_version; + uint16_t hotfix_version; + uint16_t build_version; +} __attribute__((packed)); + +struct css_header { + uint32_t header_type; + uint32_t header_len; + uint32_t header_version; + uint32_t reserved0; /* must be 0x0 */ + uint32_t module_vendor; + uint32_t date; + uint32_t size; + uint8_t header_id[4]; + uint32_t padding; /* must be 0x0 */ + struct fw_version version; + uint32_t svn; + uint32_t reserved1[18]; /* must be 0x0 */ + uint32_t modulus_size; + uint32_t exponent_size; + uint8_t modulus[MAN_RSA_KEY_MODULUS_LEN]; + uint8_t exponent[MAN_RSA_KEY_EXPONENT_LEN]; + uint8_t signature[MAN_RSA_SIGNATURE_LEN]; +} __attribute__((packed)); + +void ri_css_hdr_create(struct image *image); + +#endif diff --git a/rimage/elf.c b/rimage/elf.c new file mode 100644 index 0000000..b912477 --- /dev/null +++ b/rimage/elf.c @@ -0,0 +1,523 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#include <stdio.h> +#include <string.h> +#include "rimage.h" +#include "cse.h" +#include "manifest.h" + +static int elf_read_sections(struct image *image, struct module *module) +{ + Elf32_Ehdr *hdr = &module->hdr; + Elf32_Shdr *section = module->section; + size_t count; + int i, ret; + uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + + /* read in section header */ + ret = fseek(module->fd, hdr->e_shoff, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "error: can't seek to %s section header %d\n", + module->elf_file, ret); + return ret; + } + + /* allocate space for each section header */ + section = calloc(sizeof(Elf32_Shdr), hdr->e_shnum); + if (section == NULL) + return -ENOMEM; + module->section = section; + + /* read in sections */ + count = fread(section, sizeof(Elf32_Shdr), hdr->e_shnum, module->fd); + if (count != hdr->e_shnum) { + fprintf(stderr, "error: failed to read %s section header %d\n", + module->elf_file, -errno); + return -errno; + } + + /* parse each section */ + for (i = 0; i < hdr->e_shnum; i++) { + + /* only write valid sections */ + if (!(section[i].sh_flags & valid)) + continue; + + switch (section[i].sh_type) { + case SHT_NOBITS: + /* bss */ + module->bss_size += section[i].sh_size; + module->num_bss++; + break; + case SHT_PROGBITS: + /* text or data */ + module->fw_size += section[i].sh_size; + + if (section[i].sh_flags & SHF_EXECINSTR) + module->text_size += section[i].sh_size; + else + module->data_size += section[i].sh_size; + break; + default: + continue; + } + + module->num_sections++; + + if (!image->verbose) + continue; + + fprintf(stdout, " %s section-%d: \ttype\t 0x%8.8x\n", module->elf_file, + i, section[i].sh_type); + fprintf(stdout, " %s section-%d: \tflags\t 0x%8.8x\n", module->elf_file, + i, section[i].sh_flags); + fprintf(stdout, " %s section-%d: \taddr\t 0x%8.8x\n", module->elf_file, + i, section[i].sh_addr); + fprintf(stdout, " %s section-%d: \toffset\t 0x%8.8x\n", module->elf_file, + i, section[i].sh_offset); + fprintf(stdout, " %s section-%d: \tsize\t 0x%8.8x\n", module->elf_file, + i, section[i].sh_size); + fprintf(stdout, " %s section-%d: \tlink\t 0x%8.8x\n", module->elf_file, + i, section[i].sh_link); + fprintf(stdout, " %s section-%d: \tinfo\t 0x%8.8x\n\n", module->elf_file, + i, section[i].sh_info); + } + + return 0; +} + +static int elf_read_programs(struct image *image, struct module *module) +{ + Elf32_Ehdr *hdr = &module->hdr; + Elf32_Phdr *prg = module->prg; + size_t count; + int i, ret; + + /* read in program header */ + ret = fseek(module->fd, hdr->e_phoff, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "error: cant seek to %s program header %d\n", + module->elf_file ,ret); + return ret; + } + + /* allocate space for programs */ + prg = calloc(sizeof(Elf32_Phdr), hdr->e_phnum); + if (prg == NULL) + return -ENOMEM; + module->prg = prg; + + /* read in programs */ + count = fread(prg, sizeof(Elf32_Phdr), hdr->e_phnum, module->fd); + if (count != hdr->e_phnum) { + fprintf(stderr, "error: failed to read %s program header %d\n", + module->elf_file, -errno); + return -errno; + } + + /* check each program */ + for (i = 0; i < hdr->e_phnum; i++) { + + if (prg[i].p_filesz == 0) + continue; + + if (!image->verbose) + continue; + + fprintf(stdout, "%s program-%d: \ttype\t 0x%8.8x\n", + module->elf_file, i, prg[i].p_type); + fprintf(stdout, "%s program-%d: \toffset\t 0x%8.8x\n", + module->elf_file, i, prg[i].p_offset); + fprintf(stdout, "%s program-%d: \tvaddr\t 0x%8.8x\n", + module->elf_file, i, prg[i].p_vaddr); + fprintf(stdout, "%s program-%d: \tpaddr\t 0x%8.8x\n", + module->elf_file, i, prg[i].p_paddr); + fprintf(stdout, "%s program-%d: \tfsize\t 0x%8.8x\n", + module->elf_file, i, prg[i].p_filesz); + fprintf(stdout, "%s program-%d: \tmsize\t 0x%8.8x\n", + module->elf_file, i, prg[i].p_memsz); + fprintf(stdout, "%s program-%d: \tflags\t 0x%8.8x\n\n", + module->elf_file, i, prg[i].p_flags); + } + + return 0; +} + +static int elf_read_hdr(struct image *image, struct module *module) +{ + Elf32_Ehdr *hdr = &module->hdr; + size_t count; + + /* read in elf header */ + count = fread(hdr, sizeof(*hdr), 1, module->fd); + if (count != 1) { + fprintf(stderr, "error: failed to read %s elf header %d\n", + module->elf_file, -errno); + return -errno; + } + + if (!image->verbose) + return 0; + + fprintf(stdout, "%s elf: \tentry point\t 0x%8.8x\n", + module->elf_file, hdr->e_entry); + fprintf(stdout, "%s elf: \tprogram offset\t 0x%8.8x\n", + module->elf_file, hdr->e_phoff); + fprintf(stdout, "%s elf: \tsection offset\t 0x%8.8x\n", + module->elf_file, hdr->e_shoff); + fprintf(stdout, "%s elf: \tprogram size\t 0x%8.8x\n", + module->elf_file, hdr->e_phentsize); + fprintf(stdout, "%s elf: \tprogram count\t 0x%8.8x\n", + module->elf_file, hdr->e_phnum); + fprintf(stdout, "%s elf: \tsection size\t 0x%8.8x\n", + module->elf_file, hdr->e_shentsize); + fprintf(stdout, "%s elf: \tsection count\t 0x%8.8x\n", + module->elf_file, hdr->e_shnum); + fprintf(stdout, "%s elf: \tstring index\t 0x%8.8x\n\n", + module->elf_file, hdr->e_shstrndx); + + return 0; +} + +int elf_is_rom(struct image *image, Elf32_Shdr *section) +{ + const struct adsp *adsp = image->adsp; + uint32_t start, end; + + start = section->sh_addr; + end = section->sh_addr + section->sh_size; + + if (start < image->adsp->rom_base || + start > image->adsp->rom_base + image->adsp->rom_size) + return 0; + if (end < image->adsp->rom_base || + end > image->adsp->rom_base + image->adsp->rom_size) + return 0; + return 1; +} + +static void elf_module_size(struct image *image, struct module *module, + Elf32_Shdr *section) +{ + switch (section->sh_type) { + case SHT_PROGBITS: + /* text or data */ + if (section->sh_flags & SHF_EXECINSTR) { + /* text */ + if (module->text_start > section->sh_addr) + module->text_start = section->sh_addr; + if (module->text_end < section->sh_addr + section->sh_size) + module->text_end = section->sh_addr + section->sh_size; + + fprintf(stdout, "\tTEXT\n"); + } else { + /* initialized data, also calc the writable sections */ + if (module->data_start > section->sh_addr) + module->data_start = section->sh_addr; + if (module->data_end < section->sh_addr + section->sh_size) + module->data_end = section->sh_addr + section->sh_size; + + fprintf(stdout, "\tDATA\n"); + } + break; + case SHT_NOBITS: + /* bss */ + if (module->bss_start > section->sh_addr) + module->bss_start = section->sh_addr; + if (module->bss_end < section->sh_addr + section->sh_size) + module->bss_end = section->sh_addr + section->sh_size; + + fprintf(stdout, "\tBSS\n"); + break; + default: + break; + } +} + +static void elf_module_limits(struct image *image, struct module *module) +{ + Elf32_Shdr *section; + uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + int i; + + module->text_start = module->data_start = module->bss_start = 0xffffffff; + module->text_end = module->data_end = module->bss_end = 0; + + fprintf(stdout, " Found %d sections, listing valid sections......\n", + module->hdr.e_shnum); + + fprintf(stdout, "\tNo\tStart\t\tEnd\t\tBytes\tType\n"); + + /* iterate all sections and get size of segments */ + for (i = 0; i < module->hdr.e_shnum; i++) { + + section = &module->section[i]; + + /* only check valid sections */ + if (!(section->sh_flags & valid)) + continue; + + if (section->sh_size == 0) + continue; + + if (elf_is_rom(image, section)) + continue; + + fprintf(stdout, "\t%d\t0x%8.8x\t0x%8.8x\t%d", i, + section->sh_addr, section->sh_addr + section->sh_size, + section->sh_size); + + /* text or data section */ + elf_module_size(image, module, section); + } + + fprintf(stdout, "\n"); +} + +/* make sure no section overlap from any modules */ +int elf_validate_section(struct image *image, struct module *module, + Elf32_Shdr *section) +{ + struct module *m; + Elf32_Shdr *s; + uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + int i, j, ret; + + /* for each module */ + for (i = 0; i < image->num_modules; i++) { + m = &image->module[i]; + + if (m == module) + continue; + + /* for each section */ + for (j = 0; j < m->hdr.e_shnum; j++) { + s = &m->section[j]; + + if (s == section) + continue; + + /* only check valid sections */ + if (!(section->sh_flags & valid)) + continue; + + if (section->sh_size == 0) + continue; + + /* is section non overlapping ? */ + if (section->sh_addr >= s->sh_addr && + section->sh_addr + section->sh_size <= + s->sh_addr + s->sh_size) { + goto err; + } + } + } + + return 0; + +err: + fprintf(stderr, "error: section overlap between %s and %s\n", + module->elf_file, m->elf_file); + fprintf(stderr, " [0x%x : 0x%x] overlaps with [0x%x :0x%x]\n", + section->sh_addr, section->sh_addr + section->sh_size, + s->sh_addr, s->sh_addr + s->sh_size); + return -EINVAL; +} + +/* make sure no section overlaps from any modules */ +int elf_validate_modules(struct image *image) +{ + struct module *module; + Elf32_Shdr *section; + uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + int i, j, ret; + + /* for each module */ + for (i = 0; i < image->num_modules; i++) { + module = &image->module[i]; + + /* for each section */ + for (j = 0; j < module->hdr.e_shnum; j++) { + section = &module->section[j]; + + /* only check valid sections */ + if (!(section->sh_flags & valid)) + continue; + + if (section->sh_size == 0) + continue; + + /* is section non overlapping ? */ + ret = elf_validate_section(image, module, section); + if (ret < 0) + return ret; + } + } + + return 0; +} + +int elf_find_section(struct image *image, struct module *module, + const char *name) +{ + Elf32_Ehdr *hdr = &module->hdr; + Elf32_Shdr *section, *s; + char *buffer; + size_t count; + int ret, i; + + section = &module->section[hdr->e_shstrndx]; + + /* alloc data data */ + buffer = calloc(1, section->sh_size); + if (buffer == NULL) + return -ENOMEM; + + /* read in section string data */ + ret = fseek(module->fd, section->sh_offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "error: cant seek to string section %d\n", ret); + goto out; + } + + count = fread(buffer, 1, section->sh_size, module->fd); + if (count != section->sh_size) { + fprintf(stderr, "error: can't read string section %d\n", -errno); + ret = -errno; + goto out; + } + + /* find section with name */ + for (i = 0; i < hdr->e_shnum; i++) { + s = &module->section[i]; + if (!strcmp(name, buffer + s->sh_name)) { + ret = i; + goto out; + } + } + + fprintf(stderr, "error: can't find section %s in module %s\n", name, + module->elf_file); + ret = -EINVAL; + +out: + free(buffer); + return ret; +} + +int elf_parse_module(struct image *image, int module_index, const char *name) +{ + const struct adsp *adsp = image->adsp; + struct module *module; + uint32_t rem; + int ret = 0; + + /* validate module index */ + if (module_index >= MAX_MODULES) { + fprintf(stderr, "error: too any modules\n"); + return -EINVAL; + } + + module = &image->module[module_index]; + + /* open the elf input file */ + module->fd = fopen(name, "r"); + if (module->fd == NULL) { + fprintf(stderr, "error: unable to open %s for reading %d\n", + name, errno); + return -EINVAL; + } + module->elf_file = name; + + /* read in elf header */ + ret = elf_read_hdr(image, module); + if (ret < 0) + goto hdr_err; + + /* read in programs */ + ret = elf_read_programs(image, module); + if (ret < 0) { + fprintf(stderr, "error: failed to read program sections %d\n", + ret); + goto hdr_err; + } + + /* read sections */ + ret = elf_read_sections(image, module); + if (ret < 0) { + fprintf(stderr, "error: failed to read base sections %d\n", + ret); + goto sec_err; + } + + /* check limits */ + elf_module_limits(image, module); + + elf_find_section(image, module, ""); + + fprintf(stdout, " module: input size %d (0x%x) bytes %d sections\n", + module->fw_size, module->fw_size, module->num_sections); + fprintf(stdout, " module: text %d (0x%x) bytes\n" + " data %d (0x%x) bytes\n" + " bss %d (0x%x) bytes\n\n", + module->text_size, module->text_size, + module->data_size, module->data_size, + module->bss_size, module->bss_size); + + /* file sizes round up to nearest page */ + module->text_file_size = module->text_end - module->text_start; + rem = module->text_file_size % MAN_PAGE_SIZE; + if (rem) + module->text_file_size += MAN_PAGE_SIZE - rem; + + + /* apply any base FW fixups */ + if (image->adsp->base_fw_text_size_fixup && + module->text_start == image->adsp->sram_base) { + module->text_file_size += image->adsp->base_fw_text_size_fixup; + } + + /* data section */ + module->data_file_size = module->data_end - module->data_start; + rem = module->data_file_size % MAN_PAGE_SIZE; + if (rem) + module->data_file_size += MAN_PAGE_SIZE - rem; + + /* bss section */ + module->bss_file_size = module->bss_end - module->bss_start; + rem = module->bss_file_size % MAN_PAGE_SIZE; + if (rem) + module->bss_file_size += MAN_PAGE_SIZE - rem; + + return 0; + +sec_err: + free(module->prg); +hdr_err: + fclose(module->fd); + + return ret; +} + +void elf_free_module(struct image *image, int module_index) +{ + struct module *module = &image->module[module_index]; + + free(module->prg); + free(module->section); + fclose(module->fd); +} diff --git a/rimage/file_format.h b/rimage/file_format.h index c813f49..1530258 100644 --- a/rimage/file_format.h +++ b/rimage/file_format.h @@ -55,6 +55,7 @@ * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> */ + /* * Firmware file format . */ @@ -108,9 +109,9 @@ struct snd_sof_mod_hdr { */ struct snd_sof_fw_header { unsigned char sig[SND_SOF_FW_SIG_SIZE]; /* "Reef" */ - uint32_t file_size; /* size of file minus this header */ - uint32_t num_modules; /* number of modules */ - uint32_t abi; /* version of header format */ + uint32_t file_size; /* size of file minus this header */ + uint32_t num_modules; /* number of modules */ + uint32_t abi; /* version of header format */ } __attribute__((packed)); #endif diff --git a/rimage/file_simple.c b/rimage/file_simple.c new file mode 100644 index 0000000..2c85a76 --- /dev/null +++ b/rimage/file_simple.c @@ -0,0 +1,308 @@ +/* + * ELF to firmware image creator. + * + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + + +#include <stdlib.h> +#include <stdio.h> +#include <unistd.h> +#include <errno.h> +#include <string.h> + +#include "rimage.h" +#include "file_format.h" + +#define BYT_IRAM_BASE 0xff2c0000 +#define BYT_IRAM_HOST_OFFSET 0x0C0000 +#define BYT_IRAM_SIZE (80 * 1024) +#define BYT_DRAM_BASE 0xff300000 +#define BYT_DRAM_HOST_OFFSET 0x100000 +#define BYT_DRAM_SIZE (160 * 1024) + +#define HSW_IRAM_BASE 0x00000000 +#define HSW_IRAM_HOST_OFFSET 0x00080000 +#define HSW_IRAM_SIZE (384 * 1024) +#define HSW_DRAM_BASE 0x00400000 +#define HSW_DRAM_HOST_OFFSET 0x00000000 +#define HSW_DRAM_SIZE (512 * 1024) + +#define BDW_IRAM_BASE 0x00000000 +#define BDW_IRAM_HOST_OFFSET 0x000A0000 +#define BDW_IRAM_SIZE (320 * 1024) +#define BDW_DRAM_BASE 0x00400000 +#define BDW_DRAM_HOST_OFFSET 0x00000000 +#define BDW_DRAM_SIZE (640 * 1024) + +static int is_iram(struct image *image, Elf32_Shdr *section) +{ + const struct adsp *adsp = image->adsp; + uint32_t start, end; + + start = section->sh_addr; + end = section->sh_addr + section->sh_size; + + if (start < adsp->iram_base) + return 0; + if (start >= adsp->iram_base + adsp->iram_size) + return 0; + return 1; +} + +static int is_dram(struct image *image, Elf32_Shdr *section) +{ + const struct adsp *adsp = image->adsp; + uint32_t start, end; + + start = section->sh_addr; + end = section->sh_addr + section->sh_size; + + if (start < adsp->dram_base) + return 0; + if (start >= adsp->dram_base + adsp->dram_size) + return 0; + return 1; +} + +static int block_idx = 0; + +static int write_block(struct image *image, struct module *module, + Elf32_Shdr *section) +{ + const struct adsp *adsp = image->adsp; + struct snd_sof_blk_hdr block; + size_t count; + void *buffer; + int ret; + + block.size = section->sh_size; + + if (is_iram(image, section)) { + block.type = SOF_BLK_TEXT; + block.offset = section->sh_addr - adsp->iram_base + + adsp->host_iram_offset; + } else if (is_dram(image, section)) { + block.type = SOF_BLK_DATA; + block.offset = section->sh_addr - adsp->dram_base + + adsp->host_dram_offset; + } else { + fprintf(stderr, "error: invalid block address/size 0x%x/0x%x\n", + section->sh_addr, section->sh_size); + return -EINVAL; + } + + /* write header */ + count = fwrite(&block, sizeof(block), 1, image->out_fd); + if (count != 1) + return -errno; + + /* alloc data data */ + buffer = calloc(1, section->sh_size); + if (buffer == NULL) + return -ENOMEM; + + /* read in section data */ + ret = fseek(module->fd, section->sh_offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "error: cant seek to section %d\n", ret); + goto out; + } + count = fread(buffer, 1, section->sh_size, module->fd); + if (count != section->sh_size) { + fprintf(stderr, "error: cant read section %d\n", -errno); + ret = -errno; + goto out; + } + + /* write out section data */ + count = fwrite(buffer, 1, section->sh_size, image->out_fd); + if (count != section->sh_size) { + fprintf(stderr, "error: cant write section %d\n", -errno); + fprintf(stderr, " foffset %d size 0x%x mem addr 0x%x\n", + section->sh_offset, section->sh_size, section->sh_addr); + ret = -errno; + goto out; + } + + fprintf(stdout, "\t%d\t0x%8.8x\t0x%8.8x\t0x%8.8lx\t%s\n", block_idx++, + section->sh_addr, section->sh_size, ftell(image->out_fd), + block.type == SOF_BLK_TEXT ? "TEXT" : "DATA"); + +out: + free(buffer); + return ret; +} + +static int simple_write_module(struct image *image, struct module *module) +{ + const struct adsp *adsp = image->adsp; + struct snd_sof_mod_hdr hdr; + Elf32_Shdr *section; + size_t count; + int i, err; + uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + + hdr.num_blocks = module->num_sections - module->num_bss; + hdr.size = module->text_size + module->data_size + + sizeof(struct snd_sof_blk_hdr) * hdr.num_blocks; + hdr.type = SOF_FW_BASE; + + count = fwrite(&hdr, sizeof(hdr), 1, image->out_fd); + if (count != 1) { + fprintf(stderr, "error: failed to write section header %d\n", + -errno); + return -errno ; + } + + fprintf(stdout, "\n\tTotals\tStart\t\tEnd\t\tSize"); + + fprintf(stdout, "\n\tTEXT\t0x%8.8x\t0x%8.8x\t0x%x\n", + module->text_start, module->text_end, + module->text_end - module->text_start); + fprintf(stdout, "\tDATA\t0x%8.8x\t0x%8.8x\t0x%x\n", + module->data_start, module->data_end, + module->data_end - module->data_start); + fprintf(stdout, "\tBSS\t0x%8.8x\t0x%8.8x\t0x%x\n\n ", + module->bss_start, module->bss_end, + module->bss_end - module->bss_start); + + fprintf(stdout, "\tNo\tAddress\t\tSize\t\tFile\t\tType\n"); + + for (i = 0; i < module->hdr.e_shnum; i++) { + + section = &module->section[i]; + + /* only write valid sections */ + if (!(module->section[i].sh_flags & valid)) + continue; + + /* dont write bss */ + if (section->sh_type == SHT_NOBITS) + continue; + + err = write_block(image, module, section); + if (err < 0) { + fprintf(stderr, "error: failed to write section #%d\n", i); + return err; + } + } + + fprintf(stdout, "\n"); + return 0; +} + +/* used by others */ +static int simple_write_firmware(struct image *image) +{ + struct snd_sof_fw_header hdr; + struct module *module; + size_t count; + int i, ret; + + memcpy(hdr.sig, SND_SOF_FW_SIG, SND_SOF_FW_SIG_SIZE); + + hdr.num_modules = image->num_modules; + hdr.abi = SND_SOF_FW_ABI; + hdr.file_size = 0; + + for (i = 0; i < image->num_modules; i++) { + module = &image->module[i]; + module->fw_size += sizeof(struct snd_sof_blk_hdr) * + (module->num_sections - module->num_bss); + module->fw_size += sizeof(struct snd_sof_mod_hdr) * hdr.num_modules; + hdr.file_size += module->fw_size; + } + + count = fwrite(&hdr, sizeof(hdr), 1, image->out_fd); + if (count != 1) + return -errno; + + for (i = 0; i < image->num_modules; i++) { + module = &image->module[i]; + + fprintf(stdout, "writing module %d %s\n", i, module->elf_file); + + ret = simple_write_module(image, module); + if (ret < 0) { + fprintf(stderr, "error: failed to write module %d\n", + i); + return ret; + } + } + + fprintf(stdout, "firmware: image size %ld (0x%lx) bytes %d modules\n\n", + hdr.file_size + sizeof(hdr), hdr.file_size + sizeof(hdr), + hdr.num_modules); + + return 0; +} + +const struct adsp machine_byt = { + .name = "byt", + .iram_base = BYT_IRAM_BASE, + .iram_size = BYT_IRAM_SIZE, + .host_iram_offset = BYT_IRAM_HOST_OFFSET, + .dram_base = BYT_DRAM_BASE, + .dram_size = BYT_DRAM_SIZE, + .host_dram_offset = BYT_DRAM_HOST_OFFSET, + .machine_id = MACHINE_BAYTRAIL, + .write_firmware = simple_write_firmware, +}; + +const struct adsp machine_cht = { + .name = "cht", + .iram_base = BYT_IRAM_BASE, + .iram_size = BYT_IRAM_SIZE, + .host_iram_offset = BYT_IRAM_HOST_OFFSET, + .dram_base = BYT_DRAM_BASE, + .dram_size = BYT_DRAM_SIZE, + .host_dram_offset = BYT_DRAM_HOST_OFFSET, + .machine_id = MACHINE_CHERRYTRAIL, + .write_firmware = simple_write_firmware, +}; + +const struct adsp machine_bsw = { + .name = "bsw", + .iram_base = BYT_IRAM_BASE, + .iram_size = BYT_IRAM_SIZE, + .host_iram_offset = BYT_IRAM_HOST_OFFSET, + .dram_base = BYT_DRAM_BASE, + .dram_size = BYT_DRAM_SIZE, + .host_dram_offset = BYT_DRAM_HOST_OFFSET, + .machine_id = MACHINE_BRASWELL, + .write_firmware = simple_write_firmware, +}; + +const struct adsp machine_hsw = { + .name = "hsw", + .iram_base = HSW_IRAM_BASE, + .iram_size = HSW_IRAM_SIZE, + .host_iram_offset = HSW_IRAM_HOST_OFFSET, + .dram_base = HSW_DRAM_BASE, + .dram_size = HSW_DRAM_SIZE, + .host_dram_offset = HSW_DRAM_HOST_OFFSET, + .machine_id = MACHINE_HASWELL, + .write_firmware = simple_write_firmware, +}; + +const struct adsp machine_bdw = { + .name = "bdw", + .iram_base = BDW_IRAM_BASE, + .iram_size = BDW_IRAM_SIZE, + .host_iram_offset = BDW_IRAM_HOST_OFFSET, + .dram_base = BDW_DRAM_BASE, + .dram_size = BDW_DRAM_SIZE, + .host_dram_offset = BDW_DRAM_HOST_OFFSET, + .machine_id = MACHINE_BROADWELL, + .write_firmware = simple_write_firmware, +}; diff --git a/rimage/hash.c b/rimage/hash.c new file mode 100644 index 0000000..3acf1b3 --- /dev/null +++ b/rimage/hash.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#include <stdlib.h> +#include <stdio.h> +#include <unistd.h> +#include <errno.h> +#include <string.h> +#include <time.h> +#include <sys/time.h> + +#include <openssl/conf.h> +#include <openssl/evp.h> +#include <openssl/err.h> + +#include "rimage.h" +#include "file_format.h" +#include "manifest.h" + +#define DEBUG_HASH 0 + +void module_sha256_create(struct image *image) +{ + image->md = EVP_sha256(); + image->mdctx = EVP_MD_CTX_create(); + + EVP_DigestInit_ex(image->mdctx, image->md, NULL); +} + +void module_sha256_update(struct image *image, uint8_t *data, size_t bytes) +{ + EVP_DigestUpdate(image->mdctx, data, bytes); +} + +void module_sha256_complete(struct image *image, uint8_t *hash) +{ + unsigned char md_value[EVP_MAX_MD_SIZE]; + int md_len; +#if DEBUG_HASH + int i; +#endif + EVP_DigestFinal_ex(image->mdctx, md_value, &md_len); + EVP_MD_CTX_destroy(image->mdctx); + + memcpy(hash, md_value, md_len); +#if DEBUG_HASH + fprintf(stdout, "Module digest is: "); + for (i = 0; i < md_len; i++) + fprintf(stdout, "%02x", md_value[i]); + fprintf(stdout, "\n"); +#endif +} + +void ri_hash(struct image *image, unsigned offset, unsigned size, char *hash) +{ + module_sha256_create(image); + module_sha256_update(image, image->fw_image + offset, size); + module_sha256_complete(image, hash); +} diff --git a/rimage/keys/Makefile.am b/rimage/keys/Makefile.am new file mode 100644 index 0000000..06fe307 --- /dev/null +++ b/rimage/keys/Makefile.am @@ -0,0 +1,9 @@ +install-data-local: + @$(NORMAL_INSTALL) + $(mkinstalldirs) $(PEM_KEY_PREFIX); + $(INSTALL_DATA) otc_private_key.pem $(PEM_KEY_PREFIX) + $(INSTALL_DATA) otc_public_key.pem $(PEM_KEY_PREFIX) + +EXTRA_DIST = \ + otc_private_key.pem \ + otc_public_key.pem \ No newline at end of file diff --git a/rimage/keys/README b/rimage/keys/README new file mode 100644 index 0000000..3ece70c --- /dev/null +++ b/rimage/keys/README @@ -0,0 +1,34 @@ +About +===== + +Firmware binary signing is for audio DSP is mandatory on Intel products from +Skylake onwards. i.e. no code signing on Baytrail, Cherrytrail, Braswell, +Haswell and Broadwell but mandatory on Skylake, Kabylake, Apollolake and +Cannonlake. + +rimage can now sign firmware binaries for Apollolake and Cannonlake targets. +This is done automatically as part of the "make bin" part of the build. + + +Key Pairs +========= + +The key included here is the Intel OTC (Opensource Technology Center) community +development key. It can be freely used by anyone and is intended for reference +board makers and firmware developers. + +** This key is NOT intended for locking down firmware on end user production +devices since the "private" key has been published here. A new key pair must +be genrated for securing firmware ! ** + +RSA Private and Public keys are generated as follows :- + +openssl genpkey -algorithm RSA -out private_key.pem -pkeyopt rsa_keygen_bits:2048 +openssl rsa -pubout -in private_key.pem -out public_key.pem + +The public key needs to be programmed into the OEM Key manifest (cavsManifest0) +within the BIOS in order to verify code signed with the private key. +Intel supplies tools to board makers to stitch the public key into the BIOS. + +The private key is used by rimage to sign the SOF binary. It should be kept +secret and secure for production signing. \ No newline at end of file diff --git a/rimage/keys/otc_private_key.pem b/rimage/keys/otc_private_key.pem new file mode 100644 index 0000000..03ad749 --- /dev/null +++ b/rimage/keys/otc_private_key.pem @@ -0,0 +1,28 @@ +-----BEGIN PRIVATE KEY----- +MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQC5Q68ZJyiWWrXb +TSjlj4I/UmgusmIfv5+MCtinahekLPasIvoBhmEAr/TBizlfhj2/VN4FKNsqy7HR +QGn+iLhqnVrzpEVug4EQIpkFxTnycKMQPSDvpIqq8VL9pUCvKokSMub0oTCwoxjJ +V81wJy+NE2AnamjtnuJEXqim9U5CGjsnVNSktv/YPbso/LYFjH658Fz5QGgWfbgi +BPNFwMvemSFOIXw2J2B91ayP9ZJeI2tLyEP9EMeQqU3Gd8T5LfHIUmibpPFe1JDM +s4HmIEs7Iay03EfwjEWLVd0P/fxv9I9YNTZAi+7o8IyrTNRHDsH55efW7V58GwfS +66po4QCFAgMBAAECggEBALf7IlktTR47iRv2/WUz5hnyQWoWVmHHD6+oWc2wCzhM +Os9pkLOQ+qYPF1ZZZ6mYi5uFsVKYZ0aRsM3oVRqkNdgS2m7YtObyC2q1oRdc7JX6 +C8Wlnx69XcQzEcK4qIsMB8Gd8UQBC3RvE79nxanaEFveYP/jqb5IqdVR19SuCYCU +EZurwwAnYeLg0VSSdVQHSGVMlHkDwhgVAvp5NryPXhml51pT0gzUwnvJOsUcrc0m +tqUa2yu7/Qju1/JtFL98RgW4x3mSo4TZO3B/d664pWPOxL72zCt7bD9s06ILZmga +z1oMLMwTaNaeYIBaRvjmssKOqLXmDvfc415V82SwMYUCgYEA2p2At6acrD8Xx5GO +GeCeUbZzm0Ke9zql1W+Diq89UroFX/i9XO9Mb/ZfwouC+5n3iLjyCG7jIaIwYAyV +2qim9sINeieepM54HqYz0235nX5CqLHPDobYLn5tsbNYvXYBWiyjRppG+cnprMBk +O6vLNXNc4sRemgbcmwT3sEYLLo8CgYEA2PInWZx0JoEXriEgefv/IZeyCjpaS9uH +OOaPVAJTJPaaZhazA4ANV2bzrQAigiXbOgzPkXyldy7T7d/gHfVYnHbyhGwMEa6u +WMnj5qFXPI0hYOOrJbqXofbfGkKC996eoQybnvE0WdIwscySIki1zAenE/5nVdCJ +HLwK9xXMKasCgYA/ZxSQrsqbjgTYhVdgG+vuqOqoac7uxtyXpSrSSvaPCpJKfjp1 +PJW/lwW4x3tqewH2biUL2xUWiRJcmOnRK76YrDj6Z4k0JQljYjJ/rFKLobW1dTQm +82a5PUOVGP2wnQvRWkbUUCQrh6q0xmuLfsyFqPqUbf090KWkc/Fd90KA8wKBgG6C +q9jSAbi7ebyR02FQJJ6QD3l2UBjkMvWhPNGmfYQOuofWeEoIKMOlBevSbcGuVwYz +EGkj/YXArOQ3borUN9c8ID2kbGF1ggpojVcmSLHnkmEwmDYX3rX6c5uE1gI9vMB9 +E6jbZbd7gqKPesFMGI9eNpXQugLUv4OLpmpHCEERAoGAMF5P9jSe3JirlZ7WaH7A +I1I23L3oZfkmrcxP7B860k1ZLHDtx/MtWLkb609fq1Q2lqRuvdoaur1kW+Rv9IHS +Db8cznu9jIz3OzmJ735lHDpomylzt0+nxL5rrUnoTyMsDK0kIWs03JhPYc0+S2Ip +lkkvYQHB1eUUCxMnTgzWRr4= +-----END PRIVATE KEY----- diff --git a/rimage/keys/otc_public_key.pem b/rimage/keys/otc_public_key.pem new file mode 100644 index 0000000..b8662bd --- /dev/null +++ b/rimage/keys/otc_public_key.pem @@ -0,0 +1,9 @@ +-----BEGIN PUBLIC KEY----- +MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAuUOvGScollq1200o5Y+C +P1JoLrJiH7+fjArYp2oXpCz2rCL6AYZhAK/0wYs5X4Y9v1TeBSjbKsux0UBp/oi4 +ap1a86RFboOBECKZBcU58nCjED0g76SKqvFS/aVAryqJEjLm9KEwsKMYyVfNcCcv +jRNgJ2po7Z7iRF6opvVOQho7J1TUpLb/2D27KPy2BYx+ufBc+UBoFn24IgTzRcDL +3pkhTiF8NidgfdWsj/WSXiNrS8hD/RDHkKlNxnfE+S3xyFJom6TxXtSQzLOB5iBL +OyGstNxH8IxFi1XdD/38b/SPWDU2QIvu6PCMq0zURw7B+eXn1u1efBsH0uuqaOEA +hQIDAQAB +-----END PUBLIC KEY----- diff --git a/rimage/man_apl.c b/rimage/man_apl.c new file mode 100644 index 0000000..7b32ea1 --- /dev/null +++ b/rimage/man_apl.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "css.h" +#include "cse.h" +#include "plat_auth.h" +#include "manifest.h" + +/* hard coded atm - will pass this in from cmd line and git */ +#define MAN_FW_HDR_VERSION_MAJOR 9 +#define MAN_FW_HDR_VERSION_MINOR 22 +#define MAN_FW_HDR_VERSION_HOTFIX 1 +#define MAN_FW_HDR_VERSION_BUILD 0x7da + +/* manifest template */ +struct fw_image_manifest apl_manifest = { + + .cse_partition_dir_header = { + .header_marker = CSE_HEADER_MAKER, + .nb_entries = MAN_CSE_PARTS, + .header_version = 1, + .entry_version = 1, + .header_length = sizeof(struct CsePartitionDirHeader), + .checksum = 0, + .partition_name = "ADSP", + }, + + .cse_partition_dir_entry = { + { + /* CssHeader + platformFirmwareAuthenticationExtension - padding */ + .entry_name = "ADSP.man", + .offset = MAN_CSS_HDR_OFFSET, + .length = sizeof(struct css_header) + + PLAT_AUTH_SIZE, + }, + { /* ADSPMetadataFileExtension */ + .entry_name = "cavs0015.met", + .offset = MAN_META_EXT_OFFSET, + .length = sizeof(struct sof_man_adsp_meta_file_ext), + }, + { /* AdspFwBinaryDesc */ + .entry_name = "cavs0015", + .offset = MAN_FW_DESC_OFFSET, + .length = 0, /* calculated by rimage - */ + }, + + }, + + .css = { + .header_type = MAN_CSS_MOD_TYPE, + .header_len = MAN_CSS_HDR_SIZE, + .header_version = MAN_CSS_HDR_VERSION, + .module_vendor = MAN_CSS_MOD_VENDOR, + .size = 222, + .header_id = MAN_CSS_HDR_ID, + .padding = 0, + .version = { + .major_version = MAN_FW_HDR_VERSION_MAJOR, + .minor_version = MAN_FW_HDR_VERSION_MINOR, + .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, + .build_version = MAN_FW_HDR_VERSION_BUILD, + }, + .modulus_size = MAN_CSS_MOD_SIZE, + .exponent_size = MAN_CSS_EXP_SIZE, + }, + + .signed_pkg = { + .ext_type = SIGN_PKG_EXT_TYPE, + .ext_len = sizeof(struct signed_pkg_info_ext), + .name = "ADSP", + .vcn = 0, + .bitmap = {0, 0, 0, 0, 8}, + + .module[0] = { + .name = "cavs0015.met", + .meta_size = 96, + .type = 0x03, + .hash_algo = 0x02, /* SHA 256 */ + .hash_size = 0x20, + }, + }, + + .partition_info = { + + .ext_type = PART_INFO_EXT_TYPE, + .ext_len = sizeof(struct partition_info_ext), + + .name = "ADSP", + .length = 0, /* calculated by rimage - rounded up to nearest PAGE */ + .part_version = 0x10000000, + .instance_id = 1, + .reserved[0 ... 19] = 0xff, + + .module[0] = { + .name = "cavs0015.met", + .meta_size = 96, + .type = 0x03, + .reserved = {0x00, 0xff, 0xff}, + }, + + }, + + .cse_padding[0 ... 47] = 0xff, + + .adsp_file_ext = { + .ext_type = 17, + .ext_len = sizeof(struct sof_man_adsp_meta_file_ext), + .imr_type = 3, + .comp_desc[0] = { + .version = 0, + .base_offset = MAN_DESC_OFFSET, + .limit_offset = 0, /* calculated length + MAN_DESC_OFFSET */ + }, + + }, + + .reserved[0 ... 31] = 0xff, + + .desc = { + .header = { + .header_id = SOF_MAN_FW_HDR_ID, + .header_len = sizeof(struct sof_man_fw_header), + .name = SOF_MAN_FW_HDR_NAME, + .preload_page_count = 0, /* size in pages from $CPD */ + .fw_image_flags = SOF_MAN_FW_HDR_FLAGS, + .feature_mask = SOF_MAN_FW_HDR_FEATURES, + .major_version = MAN_FW_HDR_VERSION_MAJOR, + .minor_version = MAN_FW_HDR_VERSION_MINOR, + .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, + .build_version = MAN_FW_HDR_VERSION_BUILD, + .load_offset = MAN_DESC_OFFSET, + }, + }, +}; diff --git a/rimage/man_cnl.c b/rimage/man_cnl.c new file mode 100644 index 0000000..2aec2a7 --- /dev/null +++ b/rimage/man_cnl.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "css.h" +#include "cse.h" +#include "plat_auth.h" +#include "manifest.h" + +/* hard coded atm - will pass this in from cmd line and git */ +#define MAN_FW_HDR_VERSION_MAJOR 10 +#define MAN_FW_HDR_VERSION_MINOR 23 +#define MAN_FW_HDR_VERSION_HOTFIX 0 +#define MAN_FW_HDR_VERSION_BUILD 0x2a4 + +/* manifest template */ +struct fw_image_manifest cnl_manifest = { + + .cse_partition_dir_header = { + .header_marker = CSE_HEADER_MAKER, + .nb_entries = MAN_CSE_PARTS, + .header_version = 1, + .entry_version = 1, + .header_length = sizeof(struct CsePartitionDirHeader), + .partition_name = "ADSP", + }, + + .cse_partition_dir_entry = { + { + /* CssHeader + platformFirmwareAuthenticationExtension - padding */ + .entry_name = "ADSP.man", + .offset = MAN_CSS_HDR_OFFSET, + .length = sizeof(struct css_header) + + PLAT_AUTH_SIZE, + }, + { /* ADSPMetadataFileExtension */ + .entry_name = "cavs0015.met", + .offset = MAN_META_EXT_OFFSET, + .length = sizeof(struct sof_man_adsp_meta_file_ext), + }, + { /* AdspFwBinaryDesc */ + .entry_name = "cavs0015", + .offset = MAN_FW_DESC_OFFSET, + .length = 0, /* calculated by rimage - */ + }, + + }, + + .css = { + .header_type = MAN_CSS_MOD_TYPE, + .header_len = MAN_CSS_HDR_SIZE, + .header_version = MAN_CSS_HDR_VERSION, + .module_vendor = MAN_CSS_MOD_VENDOR, + .size = 222, + .header_id = MAN_CSS_HDR_ID, + .padding = 0, + .version = { + .major_version = MAN_FW_HDR_VERSION_MAJOR, + .minor_version = MAN_FW_HDR_VERSION_MINOR, + .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, + .build_version = MAN_FW_HDR_VERSION_BUILD, + }, + .modulus_size = MAN_CSS_MOD_SIZE, + .exponent_size = MAN_CSS_EXP_SIZE, + }, + + .signed_pkg = { + .ext_type = SIGN_PKG_EXT_TYPE, + .ext_len = sizeof(struct signed_pkg_info_ext), + .name = "ADSP", + .vcn = 0, + .bitmap = {0, 0, 0, 0, 8}, + + .module[0] = { + .name = "cavs0015.met", + .meta_size = 96, + .type = 0x03, + .hash_algo = 0x02, /* SHA 256 */ + .hash_size = 0x20, + }, + }, + + .partition_info = { + + .ext_type = PART_INFO_EXT_TYPE, + .ext_len = sizeof(struct partition_info_ext), + + .name = "ADSP", + .length = 0, /* calculated by rimage - rounded up to nearest PAGE */ + .part_version = 0x10000000, + .instance_id = 1, + .reserved[0 ... 19] = 0xff, + + .module[0] = { + .name = "cavs0015.met", + .meta_size = 96, + .type = 0x03, + .reserved = {0x00, 0xff, 0xff}, + }, + + }, + + .cse_padding[0 ... 47] = 0xff, + + .adsp_file_ext = { + .ext_type = 17, + .ext_len = sizeof(struct sof_man_adsp_meta_file_ext), + .imr_type = 3, + .comp_desc[0] = { + .version = 0, + .base_offset = MAN_DESC_OFFSET, + .limit_offset = 0, /* calculated length + MAN_DESC_OFFSET */ + }, + + }, + + .reserved[0 ... 31] = 0xff, + + .desc = { + .header = { + .header_id = SOF_MAN_FW_HDR_ID, + .header_len = sizeof(struct sof_man_fw_header), + .name = SOF_MAN_FW_HDR_NAME, + .preload_page_count = 0, /* size in pages from $CPD */ + .fw_image_flags = SOF_MAN_FW_HDR_FLAGS, + .feature_mask = SOF_MAN_FW_HDR_FEATURES, + .major_version = MAN_FW_HDR_VERSION_MAJOR, + .minor_version = MAN_FW_HDR_VERSION_MINOR, + .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, + .build_version = MAN_FW_HDR_VERSION_BUILD, + .load_offset = 0x30000, + }, + }, +}; diff --git a/rimage/manifest.c b/rimage/manifest.c new file mode 100644 index 0000000..24fb76f --- /dev/null +++ b/rimage/manifest.c @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + + +#include <stdlib.h> +#include <stdio.h> +#include <unistd.h> +#include <errno.h> +#include <string.h> +#include <time.h> +#include <sys/time.h> +#include <sof/manifest.h> + +#include "rimage.h" +#include "file_format.h" +#include "css.h" +#include "cse.h" +#include "plat_auth.h" +#include "manifest.h" + +static int man_open_rom_file(struct image *image) +{ + sprintf(image->out_rom_file, "%s.rom", image->out_file); + unlink(image->out_rom_file); + + /* allocate ROM image */ + image->rom_image = calloc(image->adsp->rom_size, 1); + if (image->rom_image == NULL) + return -ENOMEM; + + /* open ROM outfile for writing */ + image->out_rom_fd = fopen(image->out_rom_file, "w"); + if (image->out_rom_fd == NULL) { + fprintf(stderr, "error: unable to open %s for writing %d\n", + image->out_rom_file, errno); + } + + return 0; +} + +static int man_open_manifest_file(struct image *image) +{ + /* open manifest outfile for writing */ + sprintf(image->out_man_file, "%s.met", image->out_file); + unlink(image->out_man_file); + + image->out_man_fd = fopen(image->out_man_file, "w"); + if (image->out_man_fd == NULL) { + fprintf(stderr, "error: unable to open %s for writing %d\n", + image->out_man_file, errno); + } + + return 0; +} + +static int man_init_image(struct image *image) +{ + /* allocate image and copy template manifest */ + image->fw_image = calloc(image->adsp->image_size, 1); + if (image->fw_image == NULL) + return -ENOMEM; + + memcpy(image->fw_image, image->adsp->man, + sizeof(struct fw_image_manifest)); + + return 0; +} + +/* we should call this after all segments size set up via iterate */ +static uint32_t elf_to_file_offset(struct image *image, + struct module *module, struct sof_man_module *man_module, + Elf32_Shdr *section) +{ + uint32_t elf_addr = section->sh_addr, file_offset = 0; + + if (section->sh_type == SHT_PROGBITS) { + if (section->sh_flags & SHF_EXECINSTR) { + /* text segment */ + file_offset = elf_addr - module->text_start + + module->foffset; + } + else { + /* rodata segment, append to text segment */ + file_offset = elf_addr - module->data_start + + module->foffset + module->text_file_size; + + } + } else if (section->sh_type == SHT_NOBITS) { + /* bss segment */ + file_offset = 0; + } + + return file_offset; +} + +/* write SRAM sections */ +static int man_copy_sram(struct image *image, Elf32_Shdr *section, + struct module *module, struct sof_man_module *man_module, + int section_idx) +{ + uint32_t offset = elf_to_file_offset(image, module, + man_module, section); + uint32_t end = offset + section->sh_size; + int seg_type = -1; + void *buffer = image->fw_image + offset; + size_t count; + + switch (section->sh_type) { + case SHT_PROGBITS: + /* text or data */ + if (section->sh_flags & SHF_EXECINSTR) + seg_type = SOF_MAN_SEGMENT_TEXT; + else + seg_type = SOF_MAN_SEGMENT_RODATA; + break; + case SHT_NOBITS: + seg_type = SOF_MAN_SEGMENT_BSS; + default: + return 0; + } + + /* file_offset for segment should not be 0s, we set it to + * the smallest offset of its modules ATM. + */ + if (man_module->segment[seg_type].file_offset > offset || + man_module->segment[seg_type].file_offset == 0) + man_module->segment[seg_type].file_offset = offset; + + count = fread(buffer, 1, section->sh_size, module->fd); + if (count != section->sh_size) { + fprintf(stderr, "error: cant read section %d\n", -errno); + return -errno; + } + + /* get module end offset ? */ + if (end > image->image_end) + image->image_end = end; + + fprintf(stdout, "\t%d\t0x%x\t0x%x\t0x%x\t%s\n", section_idx, + section->sh_addr, section->sh_size, offset, + seg_type == SOF_MAN_SEGMENT_TEXT ? "TEXT" : "DATA"); + + return 0; +} + +static int man_copy_elf_section(struct image *image, Elf32_Shdr *section, + struct module *module, struct sof_man_module *man_module, int idx) +{ + int ret; + + /* seek to ELF section */ + ret = fseek(module->fd, section->sh_offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "error: can't seek to section %d\n", ret); + return ret; + } + + /* write data to DRAM or ROM image */ + if (!elf_is_rom(image, section)) + return man_copy_sram(image, section, module, man_module, idx); + + return 0; +} + +static int man_get_module_manifest(struct image *image, struct module *module, + struct sof_man_module *man_module) +{ + Elf32_Shdr *section; + struct sof_man_segment_desc *segment; + struct sof_man_module sof_mod; + size_t count; + int ret, man_section_idx; + + fprintf(stdout, "Module Write: %s\n", module->elf_file); + + /* find manifest module data */ + man_section_idx = elf_find_section(image, module, ".module"); + if (man_section_idx < 0) { + return -EINVAL; + } + + fprintf(stdout, " Manifest module metadata section at index %d\n", + man_section_idx); + section = &module->section[man_section_idx]; + + /* load in manifest data */ + ret = fseek(module->fd, section->sh_offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "error: can't seek to section %d\n", ret); + return ret; + } + count = fread(&sof_mod, 1, sizeof(sof_mod), module->fd); + if (count != sizeof(sof_mod)) { + fprintf(stderr, "error: can't read section %d\n", -errno); + return -errno; + } + + /* configure man_module with sofmod data */ + strncpy(man_module->struct_id, "$AME", 4); + man_module->entry_point = sof_mod.entry_point; + strncpy(man_module->name, sof_mod.name, SOF_MAN_MOD_NAME_LEN); + memcpy(man_module->uuid, sof_mod.uuid, 16); + man_module->affinity_mask = sof_mod.affinity_mask; + man_module->type.auto_start = sof_mod.type.auto_start; + man_module->type.domain_dp = sof_mod.type.domain_dp; + man_module->type.domain_ll = sof_mod.type.domain_ll; + man_module->type.load_type = sof_mod.type.load_type; + + /* text segment */ + segment = &man_module->segment[SOF_MAN_SEGMENT_TEXT]; + segment->flags.r.contents = 1; + segment->flags.r.alloc = 1; + segment->flags.r.load = 1; + segment->flags.r.readonly = 1; + segment->flags.r.code = 1; + + /* data segment */ + segment = &man_module->segment[SOF_MAN_SEGMENT_RODATA]; + segment->flags.r.contents = 1; + segment->flags.r.alloc = 1; + segment->flags.r.load = 1; + segment->flags.r.readonly = 1; + segment->flags.r.data = 1; + segment->flags.r.type = 1; + + /* bss segment */ + segment = &man_module->segment[SOF_MAN_SEGMENT_BSS]; + segment->flags.r.alloc = 1; + segment->flags.r.type = 2; + + fprintf(stdout, " Entry point 0x%8.8x\n", man_module->entry_point); + + return 0; +} + +static int man_module_create(struct image *image, struct module *module, + struct sof_man_module *man_module) +{ + /* create module and segments */ + uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); + const struct adsp *adsp = image->adsp; + Elf32_Shdr *section; + size_t count; + int i, err; + unsigned pages; + + image->image_end = 0; + + err = man_get_module_manifest(image, module, man_module); + if (err < 0) + return err; + + /* stack size ??? convert sizes to PAGES */ + man_module->instance_bss_size = 1; + + /* max number of instances of this module ?? */ + man_module->instance_max_count = 1; + + fprintf(stdout, "\n\tTotals\tStart\t\tEnd\t\tSize"); + + fprintf(stdout, "\n\tTEXT\t0x%x\t0x%x\t0x%x\n", + module->text_start, module->text_end, + module->text_end - module->text_start); + fprintf(stdout, "\tDATA\t0x%x\t0x%x\t0x%x\n", + module->data_start, module->data_end, + module->data_end - module->data_start); + fprintf(stdout, "\tBSS\t0x%x\t0x%x\t0x%x\n\n ", + module->bss_start, module->bss_end, + module->bss_end - module->bss_start); + + /* main module */ + /* text section is first */ + man_module->segment[SOF_MAN_SEGMENT_TEXT].file_offset = + module->foffset; + man_module->segment[SOF_MAN_SEGMENT_TEXT].v_base_addr = + module->text_start; + + /* calculates those padding 0s by the start of next segment */ + pages = module->text_file_size / MAN_PAGE_SIZE; + if (module->text_file_size % MAN_PAGE_SIZE) + pages += 1; + + man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length = pages; + + /* data section */ + man_module->segment[SOF_MAN_SEGMENT_RODATA].v_base_addr = + module->data_start; + man_module->segment[SOF_MAN_SEGMENT_RODATA].file_offset = + module->foffset + module->text_file_size; + pages = module->data_file_size / MAN_PAGE_SIZE; + if (module->data_file_size % MAN_PAGE_SIZE) + pages += 1; + + man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length = pages; + + /* bss is last */ + man_module->segment[SOF_MAN_SEGMENT_BSS].file_offset = 0; + man_module->segment[SOF_MAN_SEGMENT_BSS].v_base_addr = module->bss_start; + pages = (module->bss_end - module->bss_start) / MAN_PAGE_SIZE; + if ((module->bss_end - module->bss_start) % MAN_PAGE_SIZE) + pages += 1; + man_module->segment[SOF_MAN_SEGMENT_BSS].flags.r.length = pages; + + fprintf(stdout, "\tNo\tAddress\t\tSize\tFile\tType\n"); + + /* find all sections and copy to corresponding segments */ + for (i = 0; i < module->hdr.e_shnum; i++) { + + section = &module->section[i]; + + /* only check valid sections */ + if (!(section->sh_flags & valid)) + continue; + + if (section->sh_size == 0) + continue; + + /* text or data section */ + if (!elf_is_rom(image, section)) + err = man_copy_elf_section(image, section, module, + man_module, i); + + if (err < 0) { + fprintf(stderr, "error: failed to write section #%d\n", i); + return err; + } + } + fprintf(stdout, "\n"); + + /* round module end upto nearest page */ + if (image->image_end % MAN_PAGE_SIZE) { + image->image_end = (image->image_end / MAN_PAGE_SIZE) + 1; + image->image_end *= MAN_PAGE_SIZE; + } + + fprintf(stdout, " Total pages text %d data %d bss %d module file limit: 0x%x\n\n", + man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length, + man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length, + man_module->segment[SOF_MAN_SEGMENT_BSS].flags.r.length, + image->image_end); + return 0; +} + +static int man_write_fw_mod(struct image *image) +{ + int count; + long unsigned int size = 0; + + /* write ROM - for VM use only */ + count = fwrite(image->rom_image, image->adsp->rom_size, 1, + image->out_rom_fd); + if (count != 1) { + fprintf(stderr, "error: failed to write rom %s %d\n", + image->out_rom_file, -errno); + return -errno; + } + fclose(image->out_rom_fd); + + /* write manifest and signed image */ + count = fwrite(image->fw_image, + image->image_end, + 1, image->out_fd); + + /* did the image write succeed ? */ + if (count != 1) { + fprintf(stderr, "error: failed to write signed firmware %s %d\n", + image->out_file, -errno); + return -errno; + } + + return 0; +} + +/* used by others */ +static int man_write_fw(struct image *image) +{ + struct sof_man_fw_desc *desc; + struct fw_image_manifest *m; + struct module *module; + struct sof_man_module *man_module; + uint8_t hash[SOF_MAN_MOD_SHA256_LEN]; + int ret, count, i, man_section_idx; + + /* init image */ + ret = man_init_image(image); + if (ret < 0) + goto err; + + /* open ROM image */ + ret = man_open_rom_file(image); + if (ret < 0) + goto err; + + /* create the manifest */ + ret = man_open_manifest_file(image); + if (ret < 0) + goto err; + + /* create the module */ + m = image->fw_image; + desc = image->fw_image + MAN_DESC_OFFSET; + + /* create each module */ + m->desc.header.num_module_entries = image->num_modules; + for (i = 0; i < image->num_modules; i++) { + + man_module = sof_man_get_module(desc, i); + module = &image->module[i]; + + /* set module file offset */ + if (i == 0) { + module->foffset = FILE_TEXT_OFFSET; + } else { + module->foffset = image->image_end; + } + + ret = man_module_create(image, module, man_module); + if (ret < 0) + goto err; + } + + fprintf(stdout, "Firmware completing manifest\n"); + + /* create structures from end of file to start of file */ + ri_adsp_meta_data_create(image); + ri_plat_ext_data_create(image); + ri_css_hdr_create(image); + ri_cse_create(image); + + fprintf(stdout, "Firmware file size 0x%x page count %d\n", + FILE_TEXT_OFFSET - MAN_DESC_OFFSET + image->image_end, + desc->header.preload_page_count); + + /* calculate hash for each module */ + for (i = 0; i < image->num_modules; i++) { + + module = &image->module[i]; + man_module = sof_man_get_module(desc, i); + + ri_hash(image, man_module->segment[SOF_MAN_SEGMENT_TEXT].file_offset, + (man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length + + man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length) * + MAN_PAGE_SIZE, man_module->hash); + } + + /* calculate hash for ADSP meta data extension - 0x480 to end */ + ri_hash(image, MAN_FW_DESC_OFFSET, image->image_end + - MAN_FW_DESC_OFFSET, m->adsp_file_ext.comp_desc[0].hash); + + /* calculate hash for platform auth data - repeated in hash 2 and 4 */ + ri_hash(image, MAN_META_EXT_OFFSET, + sizeof(struct sof_man_adsp_meta_file_ext), hash); + + /* hash values in reverse order */ + for (i = 0; i < SOF_MAN_MOD_SHA256_LEN; i++) { + m->signed_pkg.module[0].hash[i] = + m->partition_info.module[0].hash[i] = + hash[SOF_MAN_MOD_SHA256_LEN - 1 - i]; + } + + /* sign manifest */ + ret = ri_manifest_sign(image); + if (ret < 0) + goto err; + + /* write the firmware */ + ret = man_write_fw_mod(image); + if (ret < 0) + goto err; + + fprintf(stdout, "Firmware manifest and signing completed !\n"); + return 0; + +err: + free(image->rom_image); + free(image->fw_image); + unlink(image->out_file); + unlink(image->out_rom_file); + return ret; +} + +#define ADSP_APL_DSP_ROM_BASE 0xBEFE0000 +#define ADSP_APL_DSP_ROM_SIZE 0x00002000 +#define APL_DSP_BASE_ENTRY 0xa000a000 + +#define ADSP_CNL_DSP_ROM_BASE 0xBEFE0000 +#define ADSP_CNL_DSP_ROM_SIZE 0x00002000 +#define CNL_DSP_IMR_BASE_ENTRY 0xb0038000 +#define CNL_DSP_HP_BASE_ENTRY 0xbe040000 + +/* list of supported adsp */ +const struct adsp machine_apl = { + .name = "apl", + .rom_base = ADSP_APL_DSP_ROM_BASE, + .rom_size = ADSP_APL_DSP_ROM_SIZE, + .sram_base = APL_DSP_BASE_ENTRY, + .sram_size = 0x100000, + .image_size = 0x100000, + .dram_offset = 0, + .machine_id = MACHINE_APOLLOLAKE, + .write_firmware = man_write_fw, + .man = &apl_manifest, + .base_fw_text_size_fixup = 0xa000, +}; + +const struct adsp machine_cnl = { + .name = "cnl", + .rom_base = ADSP_CNL_DSP_ROM_BASE, + .rom_size = ADSP_CNL_DSP_ROM_SIZE, + .imr_base = CNL_DSP_IMR_BASE_ENTRY, + .imr_size = 0x100000, + .sram_base = CNL_DSP_HP_BASE_ENTRY, + .sram_size = 0x100000, + .image_size = 0x100000, + .dram_offset = 0, + .machine_id = MACHINE_CANNONLAKE, + .write_firmware = man_write_fw, + .man = &cnl_manifest, +}; diff --git a/rimage/manifest.h b/rimage/manifest.h new file mode 100644 index 0000000..348f47f --- /dev/null +++ b/rimage/manifest.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MANIFEST_H__ +#define __MANIFEST_H__ + +#include <stdint.h> +#include <sof/manifest.h> +#include "css.h" +#include "cse.h" +#include "plat_auth.h" + +#define MAN_PAGE_SIZE 4096 + +/* start offset for base FW module */ +#define FILE_TEXT_OFFSET 0x8000 + +/* + * CSE values for CNL + */ +#define MAN_CSE_PARTS 3 + + +#define MAN_CSE_HDR_OFFSET 0 +#define MAN_CSE_PADDING_SIZE 0x30 +#define MAN_EXT_PADDING 0x20 +#define MAN_DESC_OFFSET 0x2000 + +#define MAN_CSS_HDR_OFFSET \ + (MAN_CSE_HDR_OFFSET + \ + sizeof(struct CsePartitionDirHeader) + \ + MAN_CSE_PARTS * sizeof(struct CsePartitionDirEntry)) + +#define MAN_SIG_PKG_OFFSET \ + (MAN_CSS_HDR_OFFSET + \ + sizeof(struct css_header)) + +#define MAN_PART_INFO_OFFSET \ + (MAN_SIG_PKG_OFFSET + \ + sizeof(struct signed_pkg_info_ext)) + +#define MAN_META_EXT_OFFSET \ + (MAN_SIG_PKG_OFFSET + \ + sizeof(struct signed_pkg_info_ext) + \ + sizeof(struct partition_info_ext) + \ + MAN_CSE_PADDING_SIZE) + +#define MAN_FW_DESC_OFFSET \ + (MAN_META_EXT_OFFSET + \ + sizeof(struct sof_man_adsp_meta_file_ext) + \ + MAN_EXT_PADDING) + +#define MAN_DESC_PADDING_SIZE \ + (MAN_DESC_OFFSET - MAN_FW_DESC_OFFSET) + +/* + * Firmware manifest header. + */ +struct fw_image_manifest { + /* MEU tool needs these sections to be 0s */ + struct CsePartitionDirHeader cse_partition_dir_header; + struct CsePartitionDirEntry cse_partition_dir_entry[MAN_CSE_PARTS]; + struct css_header css; + struct signed_pkg_info_ext signed_pkg; + struct partition_info_ext partition_info; + uint8_t cse_padding[MAN_CSE_PADDING_SIZE]; + struct sof_man_adsp_meta_file_ext adsp_file_ext; + + /* reserved / pading at end of ext data - all 0s*/ + uint8_t reserved[MAN_EXT_PADDING]; + + /* start of the unsigned binary for MEU input must start at MAN_DESC_OFFSET */ + uint8_t padding[MAN_DESC_PADDING_SIZE]; + + struct sof_man_fw_desc desc; /* at offset MAN_DESC_OFFSET */ +} __attribute__((packed)); + +extern struct fw_image_manifest apl_manifest; +extern struct fw_image_manifest cnl_manifest; +#endif diff --git a/rimage/pkcs1_5.c b/rimage/pkcs1_5.c new file mode 100644 index 0000000..7783ac4 --- /dev/null +++ b/rimage/pkcs1_5.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#include <openssl/pem.h> +#include <openssl/ssl.h> +#include <openssl/rsa.h> +#include <openssl/evp.h> +#include <openssl/bio.h> +#include <openssl/sha.h> +#include <openssl/objects.h> +#include <stdio.h> +#include <errno.h> + +#include "config.h" +#include "rimage.h" +#include "css.h" +#include "manifest.h" + +#define DEBUG_PKCS 0 + +static void bytes_swap(uint8_t *ptr, uint32_t size) +{ + uint8_t tmp; + uint32_t index; + + for (index = 0; index < (size / 2); index++) { + tmp = ptr[index]; + ptr[index] = ptr[size - 1 - index]; + ptr[size - 1 - index] = tmp; + } +} + +/* + * RSA signature of manifest. The signature is an PKCS + * #1-v1_5 of the entire manifest structure, including all + * extensions, and excluding the last 3 fields of the + * manifest header (Public Key, Exponent and Signature). +*/ + +int pkcs_sign(struct image *image, struct fw_image_manifest *man, + void *ptr1, unsigned size1, void *ptr2, unsigned size2) +{ + RSA *priv_rsa = NULL; + EVP_PKEY *privkey; + FILE *fp; + unsigned char digest[SHA256_DIGEST_LENGTH], path[256], mod[MAN_RSA_KEY_MODULUS_LEN]; + unsigned int siglen = MAN_RSA_SIGNATURE_LEN; + int ret = -EINVAL, i; + +#if DEBUG_PKCS + fprintf(stdout, "offsets 0x%lx size 0x%x offset 0x%lx size 0x%x\n", + ptr1 - (void*)man, size1, ptr2 - (void*)man, size2); +#endif + + /* create new key */ + privkey = EVP_PKEY_new(); + if (privkey == NULL) + return -ENOMEM; + + /* load in RSA private key from PEM file */ + if (image->key_name == NULL) { + sprintf(path, "%s/otc_private_key.pem", PEM_KEY_PREFIX); + image->key_name = path; + } + + fprintf(stdout, " pkcs: signing with key %s\n", image->key_name); + fp = fopen(image->key_name, "r"); + if (fp == NULL) { + fprintf(stderr, "error: can't open file %s %d\n", path, -errno); + return -errno; + } + PEM_read_PrivateKey(fp, &privkey, NULL, NULL); + fclose(fp); + + /* validate RSA private key */ + priv_rsa = EVP_PKEY_get1_RSA(privkey); + if (RSA_check_key(priv_rsa)) { + fprintf(stdout, " pkcs: RSA private key is valid.\n"); + } else { + fprintf(stderr, "error: validating RSA private key.\n"); + return -EINVAL; + } + + /* calculate the digest */ + module_sha256_create(image); + module_sha256_update(image, ptr1, size1); + module_sha256_update(image, ptr2, size2); + module_sha256_complete(image, digest); + + fprintf(stdout, " pkcs: digest for manifest is "); + for (i = 0; i < SHA256_DIGEST_LENGTH; i++) + fprintf(stdout, "%02x", digest[i]); + fprintf(stdout, "\n"); + + /* sign the manifest */ + ret = RSA_sign(NID_sha256, digest, SHA256_DIGEST_LENGTH, + (unsigned char *)man->css.signature, + &siglen, priv_rsa); + if (ret < 0) + fprintf(stderr, "error: failed to sign manifest\n"); + + /* copy public key modulus and exponent to manifest */ + BN_bn2bin(priv_rsa->n, mod); + BN_bn2bin(priv_rsa->e, (unsigned char*)man->css.exponent); + + /* modulus is reveresd */ + for (i = 0; i < MAN_RSA_KEY_MODULUS_LEN; i++) + man->css.modulus[i] = mod[MAN_RSA_KEY_MODULUS_LEN - (1 + i)]; + + /* signature is reveresd, swap it */ + bytes_swap(man->css.signature, sizeof(man->css.signature)); + + EVP_PKEY_free(privkey); + return ret; +} + +int ri_manifest_sign(struct image *image) +{ + struct fw_image_manifest *man = image->fw_image; + + pkcs_sign(image, man, (void *)man + MAN_CSS_HDR_OFFSET, + sizeof(struct css_header) - + (MAN_RSA_KEY_MODULUS_LEN + MAN_RSA_KEY_EXPONENT_LEN + + MAN_RSA_SIGNATURE_LEN), + (void *)man + MAN_SIG_PKG_OFFSET, + (man->css.size - man->css.header_len) * sizeof(uint32_t)); +} diff --git a/rimage/plat_auth.c b/rimage/plat_auth.c new file mode 100644 index 0000000..21c7138 --- /dev/null +++ b/rimage/plat_auth.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Author: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> + * Keyon Jie <yang.jie(a)linux.intel.com> + */ + +#include "rimage.h" +#include "manifest.h" +#include "plat_auth.h" + +void ri_adsp_meta_data_create(struct image *image) +{ + struct sof_man_adsp_meta_file_ext *meta = + image->fw_image + MAN_META_EXT_OFFSET; + + fprintf(stdout, " meta: completing ADSP manifest\n"); + + meta->comp_desc[0].limit_offset = MAN_DESC_OFFSET + image->image_end + - MAN_FW_DESC_OFFSET; + + fprintf(stdout, " meta: limit is 0x%x\n", + meta->comp_desc[0].limit_offset); + /* now hash the AdspFwBinaryDesc -> EOF */ +} + +void ri_plat_ext_data_create(struct image *image) +{ + struct partition_info_ext *part = image->fw_image + MAN_PART_INFO_OFFSET; + struct sof_man_adsp_meta_file_ext *meta = + image->fw_image + MAN_META_EXT_OFFSET; + struct sof_man_fw_desc *desc = image->fw_image + MAN_DESC_OFFSET; + + fprintf(stdout, " auth: completing authentication manifest\n"); + + part->length = meta->comp_desc[0].limit_offset - MAN_DESC_OFFSET; + part->length += MAN_PAGE_SIZE - (part->length % MAN_PAGE_SIZE); + + /* do this here atm */ + desc->header.preload_page_count = part->length / MAN_PAGE_SIZE; +} diff --git a/rimage/plat_auth.h b/rimage/plat_auth.h new file mode 100644 index 0000000..135f2d1 --- /dev/null +++ b/rimage/plat_auth.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2017, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PLAT_AUTH_H__ +#define __PLAT_AUTH_H__ + +#include <stdint.h> + +struct image; + +#define PLAT_AUTH_SHA256_LEN 32 +#define PLAT_AUTH_NAME_LEN 12 +#define PLAT_AUTH_PADDING 48 /* pad at end of struct */ + +#define SIGN_PKG_EXT_TYPE 15 +#define SIGN_PKG_NUM_MODULE 1 + +struct signed_pkg_info_module { + uint8_t name[PLAT_AUTH_NAME_LEN]; /* must be padded with 0 */ + uint8_t type; + uint8_t hash_algo; + uint16_t hash_size; + uint32_t meta_size; + uint8_t hash[PLAT_AUTH_SHA256_LEN]; +} __attribute__((packed)); + +struct signed_pkg_info_ext { + uint32_t ext_type; + uint32_t ext_len; + + uint8_t name[4]; + uint32_t vcn; + uint8_t bitmap[16]; + uint32_t svn; + uint8_t fw_type; + uint8_t fw_sub_type; + uint8_t reserved[14]; /* must be 0 */ + + /* variable length of modules */ + struct signed_pkg_info_module module[SIGN_PKG_NUM_MODULE]; +} __attribute__((packed)); + + +#define PART_INFO_EXT_TYPE 3 +#define PART_INFO_NUM_MODULE 1 + +struct partition_info_module { + uint8_t name[PLAT_AUTH_NAME_LEN]; /* must be padded with 0 */ + uint8_t type; + uint8_t reserved[3]; + uint32_t meta_size; + uint8_t hash[PLAT_AUTH_SHA256_LEN]; +} __attribute__((packed)); + +struct partition_info_ext { + uint32_t ext_type; + uint32_t ext_len; + + uint8_t name[4]; /* "ADSP" */ + uint32_t length; + uint8_t hash[PLAT_AUTH_SHA256_LEN]; + + uint32_t vcn; + uint32_t part_version; + uint32_t fmt_version; + uint32_t instance_id; + uint32_t part_flags; + uint8_t reserved[20]; /* must be 0 */ + + /* variable length of modules */ + struct partition_info_module module[PART_INFO_NUM_MODULE]; +} __attribute__((packed)); + + +#define PLAT_AUTH_SIZE \ + (sizeof(struct partition_info_ext) + \ + sizeof(struct signed_pkg_info_ext)) + +void ri_adsp_meta_data_create(struct image *image); +void ri_plat_ext_data_create(struct image *image); + +#endif diff --git a/rimage/rimage.c b/rimage/rimage.c index af4a7d0..f407a42 100644 --- a/rimage/rimage.c +++ b/rimage/rimage.c @@ -21,204 +21,21 @@ #include "rimage.h" #include "file_format.h" +#include "manifest.h" static const struct adsp *machine[] = { - &byt_machine, - &cht_machine, + &machine_byt, + &machine_cht, + &machine_bsw, + &machine_hsw, + &machine_bdw, + &machine_apl, + &machine_cnl, }; -static int read_elf_sections(struct image *image) -{ - size_t count; - int i, ret; - uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR); - - /* read in section header */ - ret = fseek(image->in_fd, image->hdr.e_shoff, SEEK_SET); - if (ret < 0) { - fprintf(stderr, "error: cant seek to section header %d\n", ret); - return ret; - } - - image->section = calloc(sizeof(Elf32_Shdr), image->hdr.e_shnum); - if (image->section == NULL) - return -ENOMEM; - - count = fread(image->section, sizeof(Elf32_Shdr), - image->hdr.e_shnum, image->in_fd); - if (count != image->hdr.e_shnum) { - fprintf(stderr, "error: failed to read section header %d\n", - -errno); - return -errno; - } - - for (i = 0; i < image->hdr.e_shnum; i++) { - - /* only write valid sections */ - if (!(image->section[i].sh_flags & valid)) - continue; - - switch (image->section[i].sh_type) { - case SHT_NOBITS: - /* bss */ - image->bss_size += image->section[i].sh_size; - image->num_bss++; - break; - case SHT_PROGBITS: - /* text or data */ - image->fw_size += image->section[i].sh_size; - - if (image->section[i].sh_flags & SHF_EXECINSTR) - image->text_size += image->section[i].sh_size; - else - image->data_size += image->section[i].sh_size; - break; - default: - continue; - } - - image->num_sections++; - - if (!image->verbose) - continue; - - fprintf(stdout, "section-%d: \ttype\t 0x%8.8x\n", i, - image->section[i].sh_type); - fprintf(stdout, "section-%d: \tflags\t 0x%8.8x\n", i, - image->section[i].sh_flags); - fprintf(stdout, "section-%d: \taddr\t 0x%8.8x\n", i, - image->section[i].sh_addr); - fprintf(stdout, "section-%d: \toffset\t 0x%8.8x\n", i, - image->section[i].sh_offset); - fprintf(stdout, "section-%d: \tsize\t 0x%8.8x\n", i, - image->section[i].sh_size); - fprintf(stdout, "section-%d: \tlink\t 0x%8.8x\n", i, - image->section[i].sh_link); - fprintf(stdout, "section-%d: \tinfo\t 0x%8.8x\n\n", i, - image->section[i].sh_info); - } - - return 0; -} - -static int read_elf_programs(struct image *image) -{ - size_t count; - int i, ret; - - /* read in program header */ - ret = fseek(image->in_fd, image->hdr.e_phoff, SEEK_SET); - if (ret < 0) { - fprintf(stderr, "error: cant seek to program header %d\n", ret); - return ret; - } - - image->prg = calloc(sizeof(Elf32_Phdr), image->hdr.e_phnum); - if (image->prg == NULL) - return -ENOMEM; - - count = fread(image->prg, sizeof(Elf32_Phdr), - image->hdr.e_phnum, image->in_fd); - if (count != image->hdr.e_phnum) { - fprintf(stderr, "error: failed to read program header %d\n", - -errno); - return -errno; - } - - for (i = 0; i < image->hdr.e_phnum; i++) { - - if (image->prg[i].p_filesz == 0) - continue; - - if (!image->verbose) - continue; - - fprintf(stdout, "program-%d: \ttype\t 0x%8.8x\n", i, - image->prg[i].p_type); - fprintf(stdout, "program-%d: \toffset\t 0x%8.8x\n", i, - image->prg[i].p_offset); - fprintf(stdout, "program-%d: \tvaddr\t 0x%8.8x\n", i, - image->prg[i].p_vaddr); - fprintf(stdout, "program-%d: \tpaddr\t 0x%8.8x\n", i, - image->prg[i].p_paddr); - fprintf(stdout, "program-%d: \tfsize\t 0x%8.8x\n", i, - image->prg[i].p_filesz); - fprintf(stdout, "program-%d: \tmsize\t 0x%8.8x\n", i, - image->prg[i].p_memsz); - fprintf(stdout, "program-%d: \tflags\t 0x%8.8x\n\n", i, - image->prg[i].p_flags); - } - - return 0; -} - -static int write_elf_data(struct image *image) -{ - const struct adsp *adsp = image->adsp; - int ret = 0; - size_t count; - - /* read in elf header */ - count = fread(&image->hdr, sizeof(image->hdr), 1, image->in_fd); - if (count != 1) { - fprintf(stderr, "error: failed to read elf header %d\n", - -errno); - return -errno; - } - - fprintf(stdout, "elf: \tentry point\t 0x%8.8x\n", image->hdr.e_entry); - fprintf(stdout, "elf: \tprogram offset\t 0x%8.8x\n", image->hdr.e_phoff); - fprintf(stdout, "elf: \tsection offset\t 0x%8.8x\n", image->hdr.e_shoff); - fprintf(stdout, "elf: \tprogram size\t 0x%8.8x\n", image->hdr.e_phentsize); - fprintf(stdout, "elf: \tprogram count\t 0x%8.8x\n", image->hdr.e_phnum); - fprintf(stdout, "elf: \tsection size\t 0x%8.8x\n", image->hdr.e_shentsize); - fprintf(stdout, "elf: \tsection count\t 0x%8.8x\n", image->hdr.e_shnum); - fprintf(stdout, "elf: \tstring index\t 0x%8.8x\n\n", image->hdr.e_shstrndx); - - ret = read_elf_programs(image); - if (ret < 0) { - fprintf(stderr, "error: failed to read program sections %d\n", ret); - goto out; - } - - ret = read_elf_sections(image); - if (ret < 0) { - fprintf(stderr, "error: failed to read sections %d\n", ret); - goto out; - } - - fprintf(stdout, "fw: input size %d (0x%x) bytes %d sections\n", - image->fw_size, image->fw_size, image->num_sections); - fprintf(stdout, "fw: text %d (0x%x) bytes\n" - " data %d (0x%x) bytes\n" - " bss %d (0x%x) bytes\n", - image->text_size, image->text_size, - image->data_size, image->data_size, - image->bss_size, image->bss_size); - - ret = adsp->ops.write_header(image); - if (ret < 0) { - fprintf(stderr, "error: failed to write header %d\n", ret); - goto out; - } - - ret = adsp->ops.write_modules(image); - if (ret < 0) { - fprintf(stderr, "error: failed to write modules %d\n", ret); - goto out; - } - -out: - if (image->prg) - free(image->prg); - if (image->section) - free(image->section); - return ret; -} - static void usage(char *name) { - fprintf(stdout, "%s:\t -m machine -i infile -o outfile\n", name); + fprintf(stdout, "%s:\t -m machine -o outfile -k [key] ELF files\n", name); fprintf(stdout, "\t -v enable verbose output\n"); exit(0); } @@ -227,42 +44,48 @@ int main(int argc, char *argv[]) { struct image image; const char *mach = NULL; - int opt, ret, i; + int opt, ret, i, binary = 0, elf_argc = 0; memset(&image, 0, sizeof(image)); - image.text_start = 0xffffffff; - image.data_start = 0xffffffff; - image.bss_start = 0xffffffff; - while ((opt = getopt(argc, argv, "ho:i:m:vba:sk:")) != -1) { + while ((opt = getopt(argc, argv, "ho:m:vba:sk:l:")) != -1) { switch (opt) { case 'o': image.out_file = optarg; break; - case 'i': - image.in_file = optarg; - break; case 'm': mach = optarg; break; case 'v': image.verbose = 1; break; + case 'b': + binary = 1; + break; case 's': image.dump_sections = 1; break; case 'a': image.abi = atoi(optarg); break; + case 'k': + image.key_name = optarg; + break; case 'h': - default: /* '?' */ usage(argv[0]); + break; + default: + break; } } - if (image.in_file == NULL || image.out_file == NULL || mach == NULL) + elf_argc = optind; + + /* make sure we have an outfile and machine */ + if (image.out_file == NULL || mach == NULL) usage(argv[0]); + /* find machine */ for (i = 0; i < ARRAY_SIZE(machine); i++) { if (!strcmp(mach, machine[i]->name)) { @@ -274,20 +97,26 @@ int main(int argc, char *argv[]) fprintf(stderr, "error: available machines "); for (i = 0; i < ARRAY_SIZE(machine); i++) fprintf(stderr, "%s, ", machine[i]->name); - fprintf(stderr, "/n"); + fprintf(stderr, "\n"); return -EINVAL; found: - /* open infile for reading */ - image.in_fd = fopen(image.in_file, "r"); - if (image.in_fd == NULL) { - fprintf(stderr, "error: unable to open %s for reading %d\n", - image.in_file, errno); - ret = -EINVAL; - goto out; + + /* parse input ELF files */ + image.num_modules = argc - elf_argc; + for (i = elf_argc; i < argc; i++) { + fprintf(stdout, "\nModule Reading %s\n", argv[i]); + ret = elf_parse_module(&image, i - elf_argc, argv[i]); + if (ret < 0) + goto out; } + /* validate all modules */ + ret = elf_validate_modules(&image); + if (ret < 0) + goto out; + /* open outfile for writing */ unlink(image.out_file); image.out_fd = fopen(image.out_file, "w"); @@ -298,16 +127,13 @@ found: goto out; } - /* write data */ - ret = write_elf_data(&image); - + /* process and write output */ + ret = image.adsp->write_firmware(&image); out: /* close files */ - if (image.in_fd) - fclose(image.in_fd); if (image.out_fd) fclose(image.out_fd); + return ret; } - diff --git a/rimage/rimage.h b/rimage/rimage.h index 9b8200a..84ff93f 100644 --- a/rimage/rimage.h +++ b/rimage/rimage.h @@ -1,7 +1,7 @@ /* * ELF to firmware image creator. * - * Copyright (c) 2015, Intel Corporation. + * Copyright (c) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -25,92 +25,140 @@ #include <openssl/err.h> #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#define MAX_MODULES 32 struct adsp; -struct fw_image_manifest; +struct manifest; +struct man_module; + +/* list of supported targets */ +enum machine_id { + MACHINE_BAYTRAIL = 0, + MACHINE_CHERRYTRAIL, + MACHINE_BRASWELL, + MACHINE_HASWELL, + MACHINE_BROADWELL, + MACHINE_APOLLOLAKE, + MACHINE_CANNONLAKE, + MACHINE_MAX +}; + +/* + * ELF module data + */ +struct module { + const char *elf_file; + FILE *fd; -struct image { - const char *in_file; - const char *out_file; - FILE *in_fd; - FILE *out_fd; - void *pos; Elf32_Ehdr hdr; Elf32_Shdr *section; Elf32_Phdr *prg; - const struct adsp *adsp; - int abi; - int verbose; - int num_sections; - int num_bss; - int fw_size; - int bss_size; - int text_size; - int data_size; - int file_size; - int num_modules; uint32_t text_start; uint32_t text_end; uint32_t data_start; uint32_t data_end; uint32_t bss_start; uint32_t bss_end; + uint32_t foffset; + int num_sections; + int num_bss; + int fw_size; - /* disa */ - void *in_buffer; - void *out_buffer; - int dump_sections; -}; + /* sizes do not include any gaps */ + int bss_size; + int text_size; + int data_size; -struct section { - const char *name; - uint32_t addr; - uint32_t size; + /* sizes do include gaps to nearest page */ + int bss_file_size; + int text_file_size; + int data_file_size; }; -struct adsp_ops { - /* write header or manifest */ - int (*write_header)(struct image *image); - /* write data modules */ - int (*write_modules)(struct image *image); -}; +/* + * Firmware image context. + */ +struct image { -enum machine_id { - MACHINE_BAYTRAIL = 0, - MACHINE_CHERRYTRAIL, - MACHINE_MAX + const char *out_file; + FILE *out_fd; + void *pos; + + const struct adsp *adsp; + int abi; + int verbose; + int num_modules; + struct module module[MAX_MODULES]; + uint32_t image_end;/* module end, equal to output image size */ + int dump_sections; + + /* SHA 256 */ + const char *key_name; + EVP_MD_CTX *mdctx; + const EVP_MD *md; + + /* file IO */ + void *fw_image; + void *rom_image; + FILE *out_rom_fd; + FILE *out_man_fd; + FILE *out_unsigned_fd; + char out_rom_file[256]; + char out_man_file[256]; + char out_unsigned_file[256]; }; +/* + * Audio DSP descriptor and operations. + */ struct adsp { const char *name; uint32_t iram_base; uint32_t iram_size; uint32_t dram_base; uint32_t dram_size; + uint32_t sram_base; + uint32_t sram_size; uint32_t host_iram_offset; uint32_t host_dram_offset; + uint32_t rom_base; + uint32_t rom_size; + uint32_t imr_base; + uint32_t imr_size; uint32_t image_size; uint32_t dram_offset; enum machine_id machine_id; - struct adsp_ops ops; - const struct section *sections; -}; + int (*write_firmware)(struct image *image); + struct fw_image_manifest *man; -/* headers used by multiple platforms */ -int byt_write_header(struct image *image); + /* fixups */ + uint32_t base_fw_text_size_fixup; /* added to BASEFW text size */ +}; -/* modules used by multiple platforms */ -int byt_write_modules(struct image *image); +void module_sha256_create(struct image *image); +void module_sha256_update(struct image *image, uint8_t *data, size_t bytes); +void module_sha256_complete(struct image *image, uint8_t *hash); +int ri_manifest_sign(struct image *image); +void ri_hash(struct image *image, unsigned offset, unsigned size, char *hash); -/* for disassembly */ -int write_byt_binary_image(struct image *image); +int elf_parse_module(struct image *image, int module_index, const char *name); +void elf_free_module(struct image *image, int module_index); +int elf_is_rom(struct image *image, Elf32_Shdr *section); +int elf_validate_modules(struct image *image); +int elf_find_section(struct image *image, struct module *module, + const char *name); /* supported machines */ -extern const struct adsp byt_machine; -extern const struct adsp cht_machine; +extern const struct adsp machine_byt; +extern const struct adsp machine_cht; +extern const struct adsp machine_bsw; +extern const struct adsp machine_hsw; +extern const struct adsp machine_bdw; +extern const struct adsp machine_apl; +extern const struct adsp machine_cnl; #endif -- 2.14.1

1 0

Re: [Sound-open-firmware] [PATCH] sof: add git pre- and post-commit hooks
by Liam Girdwood 23 Jan '18

23 Jan '18

On Mon, 2018-01-22 at 08:32 -0600, Pierre-Louis Bossart wrote: > Use Linux checkpatch.pl to check for style problems on each commit > rather than waste time on mailing lists. > > The hooks are installed by default with autogen.sh if there are > no pre-existing hooks, e.g. if a global template is used. > > Commits can still be forced by using git commit -n (or --no-verify) if > you absolutely need to bypass checkpatch.pl in a work branch. > > Note that both checkpatch.pl and spelling.txt are provided under > a GPL v2 license. > > Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> > --- > autogen.sh | 6 + > scripts/checkpatch.pl | 6448 ++++++++++++++++++++++++++++++++++++++ > scripts/const_structs.checkpatch | 4 + > scripts/sof-post-commit-hook.sh | 4 + > scripts/sof-pre-commit-hook.sh | 4 + > scripts/spelling.txt | 1254 ++++++++ > 6 files changed, 7720 insertions(+) > create mode 100755 scripts/checkpatch.pl > create mode 100644 scripts/const_structs.checkpatch > create mode 100755 scripts/sof-post-commit-hook.sh > create mode 100755 scripts/sof-pre-commit-hook.sh > create mode 100644 scripts/spelling.txt Applied. Thanks Liam

1 0

[Sound-open-firmware] [PATCH] platform: byt: move DW-DMA specific headers into DMA driver.
by Liam Girdwood 23 Jan '18

23 Jan '18

Lets keep all the DW-DMA register/bits in one place. Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- src/drivers/dw-dma.c | 33 ++++++++++++++++++++++++++++ src/platform/baytrail/include/platform/dma.h | 26 ---------------------- 2 files changed, 33 insertions(+), 26 deletions(-) diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index 5374f94..22e90b7 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -163,6 +163,39 @@ /* default initial setup register values */ #define DW_CFG_LOW_DEF 0x0 #define DW_CFG_HIGH_DEF 0x4 + +#elif defined (CONFIG_BAYTRAIL) || defined (CONFIG_CHERRYTRAIL) +/* baytrail specific registers */ + +/* CTL_LO */ +#define DW_CTLL_S_GATH_EN (1 << 17) +#define DW_CTLL_D_SCAT_EN (1 << 18) + +/* CTL_HI */ +#define DW_CTLH_DONE 0x00020000 +#define DW_CTLH_BLOCK_TS_MASK 0x0001ffff +#define DW_CTLH_CLASS(x) ((x) << 29) +#define DW_CTLH_WEIGHT(x) ((x) << 18) + +/* CFG_LO */ +#define DW_CFG_CH_DRAIN 0x400 + +/* CFG_HI */ +#define DW_CFGH_SRC_PER(x) ((x) << 0) +#define DW_CFGH_DST_PER(x) ((x) << 4) + +/* FIFO Partition */ +#define DW_FIFO_PARTITION +#define DW_FIFO_PART0_LO 0x0400 +#define DW_FIFO_PART0_HI 0x0404 +#define DW_FIFO_PART1_LO 0x0408 +#define DW_FIFO_PART1_HI 0x040C +#define DW_CH_SAI_ERR 0x0410 + +/* default initial setup register values */ +#define DW_CFG_LOW_DEF 0x00000003 +#define DW_CFG_HIGH_DEF 0x0 + #endif /* tracing */ diff --git a/src/platform/baytrail/include/platform/dma.h b/src/platform/baytrail/include/platform/dma.h index 37ae067..eec501a 100644 --- a/src/platform/baytrail/include/platform/dma.h +++ b/src/platform/baytrail/include/platform/dma.h @@ -38,32 +38,6 @@ #define DMA_ID_DMAC1 1 #define DMA_ID_DMAC2 2 -/* baytrail specific registers */ -/* CTL_LO */ -#define DW_CTLL_S_GATH_EN (1 << 17) -#define DW_CTLL_D_SCAT_EN (1 << 18) -/* CTL_HI */ -#define DW_CTLH_DONE 0x00020000 -#define DW_CTLH_BLOCK_TS_MASK 0x0001ffff -#define DW_CTLH_CLASS(x) ((x) << 29) -#define DW_CTLH_WEIGHT(x) ((x) << 18) -/* CFG_LO */ -#define DW_CFG_CH_DRAIN 0x400 -/* CFG_HI */ -#define DW_CFGH_SRC_PER(x) ((x) << 0) -#define DW_CFGH_DST_PER(x) ((x) << 4) -/* FIFO Partition */ -#define DW_FIFO_PARTITION -#define DW_FIFO_PART0_LO 0x0400 -#define DW_FIFO_PART0_HI 0x0404 -#define DW_FIFO_PART1_LO 0x0408 -#define DW_FIFO_PART1_HI 0x040C -#define DW_CH_SAI_ERR 0x0410 - -/* default initial setup register values */ -#define DW_CFG_LOW_DEF 0x00000003 -#define DW_CFG_HIGH_DEF 0x0 - #define DMA_HANDSHAKE_SSP0_RX 0 #define DMA_HANDSHAKE_SSP0_TX 1 #define DMA_HANDSHAKE_SSP1_RX 2 -- 2.14.1

2 27

[Sound-open-firmware] checkpatch results for last batch
by Pierre-Louis Bossart 23 Jan '18

23 Jan '18

quite a few warnings worth fixing? --------------------------------------------------------------- 0001-platform-byt-move-DW-DMA-specific-headers-into-DMA-d.patch --------------------------------------------------------------- WARNING: space prohibited between function name and open parenthesis '(' #24: FILE: src/drivers/dw-dma.c:167: +#elif defined (CONFIG_BAYTRAIL) || defined (CONFIG_CHERRYTRAIL) WARNING: space prohibited between function name and open parenthesis '(' #24: FILE: src/drivers/dw-dma.c:167: +#elif defined (CONFIG_BAYTRAIL) || defined (CONFIG_CHERRYTRAIL) ----------------------------------------------------- 0003-core-irq-Add-support-for-nested-interrupts.patch ----------------------------------------------------- WARNING: missing space after return type #76: FILE: src/include/reef/interrupt.h:64: + void(*handler)(void *arg), void *arg); ERROR: spaces required around that '=' (ctx:WxV) #238: FILE: src/lib/interrupt.c:109: + child =parent->child[REEF_IRQ_BIT(irq)]; ^ ERROR: spaces required around that '=' (ctx:WxV) #265: FILE: src/lib/interrupt.c:136: + child =parent->child[REEF_IRQ_BIT(irq)]; ^ -------------------------------------------------------------- 0005-ipc-trace-dma_trace-cant-use-page-tables-on-APL-CNL.patch -------------------------------------------------------------- WARNING: 'cant' may be misspelled - perhaps 'can't'? #4: Subject: [PATCH 05/24] ipc: trace: dma_trace cant use page tables on APL/CNL --------------------------------------------------------------- 0009-drv-dw-dma-Add-support-for-apollolake-and-cannonlake.patch --------------------------------------------------------------- WARNING: space prohibited between function name and open parenthesis '(' #23: FILE: src/drivers/dw-dma.c:199: +#elif defined (CONFIG_APOLLOLAKE) || defined (CONFIG_CANNONLAKE) WARNING: space prohibited between function name and open parenthesis '(' #23: FILE: src/drivers/dw-dma.c:199: +#elif defined (CONFIG_APOLLOLAKE) || defined (CONFIG_CANNONLAKE) ----------------------------------------------- 0010-io-Add-support-for-16bit-register-IO.patch ----------------------------------------------- WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #23: FILE: src/include/reef/io.h:53: + return *((volatile uint16_t*)reg); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #28: FILE: src/include/reef/io.h:58: + *((volatile uint16_t*)reg) = val; --------------------------------------------------------- 0014-platform-apl-Add-xtensa-headers-for-apollolake.patch --------------------------------------------------------- WARNING: please, no spaces at the start of a line #643: FILE: src/platform/apollolake/include/platform/memory.h:194: + (L2_SRAM_SIZE - L2_VECTOR_SIZE - REEF_TEXT_SIZE - REEF_DATA_SIZE - \$ WARNING: please, no spaces at the start of a line #644: FILE: src/platform/apollolake/include/platform/memory.h:195: + REEF_BSS_DATA_SIZE - HEAP_RUNTIME_SIZE - REEF_STACK_SIZE - HEAP_SYSTEM_SIZE)$ WARNING: please, no spaces at the start of a line #781: FILE: src/platform/apollolake/include/platform/memory.h:332: + (LP_SRAM_SIZE - HEAP_LP_RUNTIME_SIZE - REEF_LP_STACK_SIZE - HEAP_LP_SYSTEM_SIZE)$ WARNING: 'INTERUPT' may be misspelled - perhaps 'INTERRUPT'? #858: FILE: src/platform/apollolake/include/platform/platform.h:46: +#define PLATFORM_IPC_INTERUPT IRQ_EXT_IPC_LVL2(0) ERROR: Macros with multiple statements should be enclosed in a do - while loop #928: FILE: src/platform/apollolake/include/platform/platform.h:116: +#define platform_trace_point(__x) \ + sw_reg_write(SW_REG_STATUS, (0xace0000 | __x) & 0x3fffffff));\ + sw_reg_write(SW_REG_ERRCODE, __x) WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1119: FILE: src/platform/apollolake/include/platform/shim.h:162: + return *((volatile uint32_t*)(SHIM_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1124: FILE: src/platform/apollolake/include/platform/shim.h:167: + *((volatile uint32_t*)(SHIM_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1129: FILE: src/platform/apollolake/include/platform/shim.h:172: + return *((volatile uint64_t*)(SHIM_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1134: FILE: src/platform/apollolake/include/platform/shim.h:177: + *((volatile uint64_t*)(SHIM_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1139: FILE: src/platform/apollolake/include/platform/shim.h:182: + return *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1144: FILE: src/platform/apollolake/include/platform/shim.h:187: + *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1149: FILE: src/platform/apollolake/include/platform/shim.h:192: + return *((volatile uint32_t*)(MN_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1154: FILE: src/platform/apollolake/include/platform/shim.h:197: + *((volatile uint32_t*)(MN_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1159: FILE: src/platform/apollolake/include/platform/shim.h:202: + return *((volatile uint32_t*)(IRQ_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1164: FILE: src/platform/apollolake/include/platform/shim.h:207: + *((volatile uint32_t*)(IRQ_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1169: FILE: src/platform/apollolake/include/platform/shim.h:212: + return *((volatile uint32_t*)(IPC_HOST_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1174: FILE: src/platform/apollolake/include/platform/shim.h:217: + *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val; ----------------------------------------------------------- 0016-platform-apl-Add-platform-drivers-for-apollolake.patch ----------------------------------------------------------- WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #33: new file mode 100644 WARNING: please, no space before tabs #1014: FILE: src/platform/apollolake/dai.c:120: +^I^I^I.offset ^I= SSP_BASE(4) + SSDR,$ WARNING: please, no space before tabs #1018: FILE: src/platform/apollolake/dai.c:124: +^I^I^I.offset ^I= SSP_BASE(4) + SSDR,$ WARNING: please, no space before tabs #1031: FILE: src/platform/apollolake/dai.c:137: +^I^I^I.offset ^I= SSP_BASE(5) + SSDR,$ WARNING: please, no space before tabs #1035: FILE: src/platform/apollolake/dai.c:141: +^I^I^I.offset ^I= SSP_BASE(5) + SSDR,$ ERROR: "foo * bar" should be "foo *bar" #1290: FILE: src/platform/apollolake/interrupt.c:45: + struct irq_child * child = NULL; ERROR: "foo * bar" should be "foo *bar" #1333: FILE: src/platform/apollolake/interrupt.c:88: + struct irq_child * child = NULL; ERROR: "foo * bar" should be "foo *bar" #1376: FILE: src/platform/apollolake/interrupt.c:131: + struct irq_child * child = NULL; ERROR: "foo * bar" should be "foo *bar" #1419: FILE: src/platform/apollolake/interrupt.c:174: + struct irq_child * child = NULL; WARNING: braces {} are not necessary for single statement blocks #1546: FILE: src/platform/apollolake/interrupt.c:301: + for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) { + spinlock_init(&dsp_irq[i].lock); + } ERROR: Use of the '__DATE__' macro makes the build non-deterministic #1618: FILE: src/platform/apollolake/platform.c:63: + .date = __DATE__, ERROR: Use of the '__TIME__' macro makes the build non-deterministic #1619: FILE: src/platform/apollolake/platform.c:64: + .time = __TIME__, WARNING: 'postion' may be misspelled - perhaps 'position'? #1900: FILE: src/platform/apollolake/timer.c:87: + /* get host postion */ WARNING: 'postion' may be misspelled - perhaps 'position'? #1912: FILE: src/platform/apollolake/timer.c:99: + /* get DAI postion */ ---------------------------------------------------- 0017-ipc-apl-Add-support-for-IPC-on-apollolake.patch ---------------------------------------------------- ERROR: need consistent spacing around '|' (ctx:WxV) #133: FILE: src/ipc/apl-ipc.c:94: + ipc_write(IPC_DIPCIE, ipc_read(IPC_DIPCIE) |IPC_DIPCIE_DONE); ^ ERROR: need consistent spacing around '|' (ctx:WxV) #170: FILE: src/ipc/apl-ipc.c:131: + ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) |IPC_DIPCT_BUSY ); ^ ERROR: space prohibited before that close parenthesis ')' #170: FILE: src/ipc/apl-ipc.c:131: + ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) |IPC_DIPCT_BUSY ); WARNING: 'INTERUPT' may be misspelled - perhaps 'INTERRUPT'? #246: FILE: src/ipc/apl-ipc.c:207: + interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL); WARNING: 'INTERUPT' may be misspelled - perhaps 'INTERRUPT'? #247: FILE: src/ipc/apl-ipc.c:208: + interrupt_enable(PLATFORM_IPC_INTERUPT); 0020-platform-cnl-Add-xtensa-headers-for-cannonlake.patch has style problems, please review. ------------------------------------------------------- 0021-platform-cnl-Add-cannonlake-platform-headers.patch ------------------------------------------------------- WARNING: 'INTERUPT' may be misspelled - perhaps 'INTERRUPT'? #848: FILE: src/platform/cannonlake/include/platform/platform.h:49: +#define PLATFORM_IPC_INTERUPT IRQ_EXT_IPC_LVL2(0) WARNING: line over 80 characters #872: FILE: src/platform/cannonlake/include/platform/platform.h:73: +/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */ ERROR: Macros with multiple statements should be enclosed in a do - while loop #918: FILE: src/platform/cannonlake/include/platform/platform.h:119: +#define platform_trace_point(__x) \ + sw_reg_write(SW_REG_STATUS, (0xace0000 | __x) & 0x3fffffff));\ + sw_reg_write(SW_REG_ERRCODE, __x) WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1152: FILE: src/platform/cannonlake/include/platform/shim.h:205: + return *((volatile uint16_t*)(SHIM_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1157: FILE: src/platform/cannonlake/include/platform/shim.h:210: + *((volatile uint16_t*)(SHIM_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1162: FILE: src/platform/cannonlake/include/platform/shim.h:215: + return *((volatile uint32_t*)(SHIM_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1167: FILE: src/platform/cannonlake/include/platform/shim.h:220: + *((volatile uint32_t*)(SHIM_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1172: FILE: src/platform/cannonlake/include/platform/shim.h:225: + return *((volatile uint64_t*)(SHIM_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1177: FILE: src/platform/cannonlake/include/platform/shim.h:230: + *((volatile uint64_t*)(SHIM_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1182: FILE: src/platform/cannonlake/include/platform/shim.h:235: + return *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1187: FILE: src/platform/cannonlake/include/platform/shim.h:240: + *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1192: FILE: src/platform/cannonlake/include/platform/shim.h:245: + return *((volatile uint32_t*)(MN_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1197: FILE: src/platform/cannonlake/include/platform/shim.h:250: + *((volatile uint32_t*)(MN_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1202: FILE: src/platform/cannonlake/include/platform/shim.h:255: + return *((volatile uint32_t*)(IRQ_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1207: FILE: src/platform/cannonlake/include/platform/shim.h:260: + *((volatile uint32_t*)(IRQ_BASE + reg)) = val; WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1212: FILE: src/platform/cannonlake/include/platform/shim.h:265: + return *((volatile uint32_t*)(IPC_HOST_BASE + reg)); WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst #1217: FILE: src/platform/cannonlake/include/platform/shim.h:270: + *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val; ------------------------------------------------------- 0022-platform-Add-platform-drivers-for-cannonlake.patch ------------------------------------------------------- ERROR: "foo * bar" should be "foo *bar" #1743: FILE: src/platform/cannonlake/interrupt.c:45: + struct irq_child * child = NULL; ERROR: "foo * bar" should be "foo *bar" #1786: FILE: src/platform/cannonlake/interrupt.c:88: + struct irq_child * child = NULL; ERROR: "foo * bar" should be "foo *bar" #1829: FILE: src/platform/cannonlake/interrupt.c:131: + struct irq_child * child = NULL; ERROR: "foo * bar" should be "foo *bar" #1872: FILE: src/platform/cannonlake/interrupt.c:174: + struct irq_child * child = NULL; WARNING: braces {} are not necessary for single statement blocks #1999: FILE: src/platform/cannonlake/interrupt.c:301: + for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) { + spinlock_init(&dsp_irq[i].lock); + } ERROR: Use of the '__DATE__' macro makes the build non-deterministic #2073: FILE: src/platform/cannonlake/platform.c:65: + .date = __DATE__, ERROR: Use of the '__TIME__' macro makes the build non-deterministic #2074: FILE: src/platform/cannonlake/platform.c:66: + .time = __TIME__, ERROR: need consistent spacing around '|' (ctx:WxV) #2189: FILE: src/platform/cannonlake/platform.c:181: + IOPO_DMIC_FLAG |IOPO_I2S_FLAG); ^ ERROR: space required before the open parenthesis '(' #2272: FILE: src/platform/cannonlake/platform.c:264: + for(i = 0; i < PLATFORM_SSP_COUNT; i++) { WARNING: 'postion' may be misspelled - perhaps 'position'? #2374: FILE: src/platform/cannonlake/timer.c:88: + /* get host postion */ WARNING: 'postion' may be misspelled - perhaps 'position'? #2386: FILE: src/platform/cannonlake/timer.c:100: + /* get DAI postion */ ---------------------------------------------------- 0023-ipc-cnl-Add-support-for-IPC-on-cannonlake.patch ---------------------------------------------------- ERROR: need consistent spacing around '|' (ctx:WxV) #133: FILE: src/ipc/cnl-ipc.c:94: + ipc_write(IPC_DIPCIDA, ipc_read(IPC_DIPCIDA) |IPC_DIPCIDA_DONE); ^ WARNING: line over 80 characters #136: FILE: src/ipc/cnl-ipc.c:97: + ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCIDIE); ERROR: need consistent spacing around '|' (ctx:WxV) #170: FILE: src/ipc/cnl-ipc.c:131: + ipc_write(IPC_DIPCTDR, ipc_read(IPC_DIPCTDR) |IPC_DIPCTDR_BUSY); ^ ERROR: need consistent spacing around '|' (ctx:WxV) #171: FILE: src/ipc/cnl-ipc.c:132: + ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) |IPC_DIPCTDA_BUSY ); ^ ERROR: space prohibited before that close parenthesis ')' #171: FILE: src/ipc/cnl-ipc.c:132: + ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) |IPC_DIPCTDA_BUSY ); WARNING: 'INTERUPT' may be misspelled - perhaps 'INTERRUPT'? #244: FILE: src/ipc/cnl-ipc.c:205: + interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL); WARNING: 'INTERUPT' may be misspelled - perhaps 'INTERRUPT'? #245: FILE: src/ipc/cnl-ipc.c:206: + interrupt_enable(PLATFORM_IPC_INTERUPT);

2 1

[Sound-open-firmware] [RFC PATCH] mailbox: move multi-line macros to inline functions
by Pierre-Louis Bossart 22 Jan '18

22 Jan '18

Detected with Coverity: In do_notify: The indentation of this code suggests it is nested when it is not. (CWE-483) multi_stmt_macro: The macro on this line expands into multiple statements, only the first of which is nested within the preceding parent while the rest are not. if (msg->rx_size && msg->rx_size < SOF_IPC_MSG_MAX_SIZE) mailbox_dspbox_read(msg->rx_data, 0, msg->rx_size); Move mailbox macros to inline functions to remove the issue, keep indentation the same and add typecasts as needed FIXME: a. is type uint8_t * ok for data? b. is uint32_t ok for offset (renamed from dest since it was not a pointer) c. This code is full of integer/pointer conversions which will have to be cleaned-up for MISRA compliance Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> --- src/include/reef/mailbox.h | 44 ++++++++++++++++++++++++++-------------- src/ipc/byt-ipc.c | 2 +- src/ipc/intel-ipc.c | 23 +++++++++++---------- src/platform/baytrail/platform.c | 2 +- 4 files changed, 43 insertions(+), 28 deletions(-) diff --git a/src/include/reef/mailbox.h b/src/include/reef/mailbox.h index c0580a9..c3976a3 100644 --- a/src/include/reef/mailbox.h +++ b/src/include/reef/mailbox.h @@ -34,6 +34,7 @@ #include <platform/mailbox.h> #include <arch/cache.h> #include <stdint.h> +#include <reef/reef.h> /* 4k should be enough for everyone ..... */ #define IPC_MAX_MAILBOX_BYTES 0x1000 @@ -62,20 +63,33 @@ #define mailbox_get_debug_size() \ MAILBOX_DEBUG_SIZE -#define mailbox_dspbox_write(dest, src, bytes) \ - rmemcpy((void*)(MAILBOX_DSPBOX_BASE + dest), src, bytes); \ - dcache_writeback_region((void*)(MAILBOX_DSPBOX_BASE + dest), bytes); - -#define mailbox_dspbox_read(dest, src, bytes) \ - dcache_invalidate_region((void*)(MAILBOX_DSPBOX_BASE + src), bytes); \ - rmemcpy(dest, (void*)(MAILBOX_DSPBOX_BASE + src), bytes); - -#define mailbox_hostbox_write(dest, src, bytes) \ - rmemcpy((void*)(MAILBOX_HOSTBOX_BASE + dest), src, bytes); \ - dcache_writeback_region((void*)(MAILBOX_HOSTBOX_BASE + dest), bytes); - -#define mailbox_hostbox_read(dest, src, bytes) \ - dcache_invalidate_region((void*)(MAILBOX_HOSTBOX_BASE + src), bytes); \ - rmemcpy(dest, (void*)(MAILBOX_HOSTBOX_BASE + src), bytes); +static inline +void mailbox_dspbox_write(uint32_t offset, uint8_t *src, uint32_t bytes) +{ + rmemcpy((void *)(MAILBOX_DSPBOX_BASE + offset), src, bytes); + dcache_writeback_region((void *)(MAILBOX_DSPBOX_BASE + offset), bytes); +} + +static inline +void mailbox_dspbox_read(uint8_t *dest, uint32_t offset, uint32_t bytes) +{ + dcache_invalidate_region((void *)(MAILBOX_DSPBOX_BASE + offset), bytes); + rmemcpy(dest, (void *)(MAILBOX_DSPBOX_BASE + offset), bytes); +} + +static inline +void mailbox_hostbox_write(uint32_t offset, uint8_t *src, uint32_t bytes) +{ + rmemcpy((void *)(MAILBOX_HOSTBOX_BASE + offset), src, bytes); + dcache_writeback_region((void *)(MAILBOX_HOSTBOX_BASE + offset), bytes); +} + +static inline +void mailbox_hostbox_read(uint8_t *dest, uint32_t offset, uint32_t bytes) +{ + dcache_invalidate_region((void *)(MAILBOX_HOSTBOX_BASE + offset), + bytes); + rmemcpy(dest, (void *)(MAILBOX_HOSTBOX_BASE + offset), bytes); +} #endif diff --git a/src/ipc/byt-ipc.c b/src/ipc/byt-ipc.c index 8897bb9..029d3a6 100644 --- a/src/ipc/byt-ipc.c +++ b/src/ipc/byt-ipc.c @@ -140,7 +140,7 @@ void ipc_platform_do_cmd(struct ipc *ipc) /* send std error/ok reply */ reply.hdr.cmd = SOF_IPC_GLB_REPLY; reply.hdr.size = sizeof(reply); - mailbox_hostbox_write(0, &reply, sizeof(reply)); + mailbox_hostbox_write(0, (uint8_t *)&reply, sizeof(reply)); done: ipc->host_pending = 0; diff --git a/src/ipc/intel-ipc.c b/src/ipc/intel-ipc.c index 5a98e1f..99e0a90 100644 --- a/src/ipc/intel-ipc.c +++ b/src/ipc/intel-ipc.c @@ -69,7 +69,7 @@ static inline struct sof_ipc_hdr *mailbox_validate(void) struct sof_ipc_hdr *hdr = _ipc->comp_data; /* read component values from the inbox */ - mailbox_hostbox_read(hdr, 0, sizeof(*hdr)); + mailbox_hostbox_read((uint8_t *)hdr, 0, sizeof(*hdr)); /* validate component header */ if (hdr->size > SOF_IPC_MSG_MAX_SIZE) { @@ -78,7 +78,8 @@ static inline struct sof_ipc_hdr *mailbox_validate(void) } /* read rest of component data */ - mailbox_hostbox_read(hdr + 1, sizeof(*hdr), hdr->size - sizeof(*hdr)); + mailbox_hostbox_read((uint8_t *)(hdr + 1), sizeof(*hdr), + hdr->size - sizeof(*hdr)); return hdr; } @@ -297,7 +298,7 @@ static int ipc_stream_pcm_params(uint32_t stream) reply.rhdr.error = 0; reply.comp_id = pcm_params->comp_id; reply.posn_offset = 0; /* TODO: set this up for mmaped components */ - mailbox_hostbox_write(0, &reply, sizeof(reply)); + mailbox_hostbox_write(0, (uint8_t *)&reply, sizeof(reply)); return 1; error: @@ -360,7 +361,7 @@ static int ipc_stream_position(uint32_t header) pipeline_get_timestamp(pcm_dev->cd->pipeline, pcm_dev->cd, &posn); /* copy positions to outbox */ - mailbox_hostbox_write(0, &posn, sizeof(posn)); + mailbox_hostbox_write(0, (uint8_t *)&posn, sizeof(posn)); return 1; } @@ -521,7 +522,7 @@ static int ipc_pm_context_size(uint32_t header) /* TODO: calculate the context and size of host buffers required */ /* write the context to the host driver */ - mailbox_hostbox_write(0, &pm_ctx, sizeof(pm_ctx)); + mailbox_hostbox_write(0, (uint8_t *)&pm_ctx, sizeof(pm_ctx)); return 1; } @@ -554,7 +555,7 @@ static int ipc_pm_context_save(uint32_t header) //reply.entries_no = 0; /* write the context to the host driver */ - mailbox_hostbox_write(0, pm_ctx, sizeof(*pm_ctx)); + mailbox_hostbox_write(0, (uint8_t *)pm_ctx, sizeof(*pm_ctx)); //iipc->pm_prepare_D3 = 1; @@ -632,7 +633,7 @@ static int ipc_dma_trace_config(uint32_t header) reply.hdr.size = sizeof(reply); reply.hdr.cmd = header; reply.error = 0; - mailbox_hostbox_write(0, &reply, sizeof(reply)); + mailbox_hostbox_write(0, (uint8_t *)&reply, sizeof(reply)); return 0; error: @@ -702,7 +703,7 @@ static int ipc_comp_value(uint32_t header, uint32_t cmd) } /* write component values to the outbox */ - mailbox_hostbox_write(0, data, data->rhdr.hdr.size); + mailbox_hostbox_write(0, (uint8_t *)data, data->rhdr.hdr.size); return 1; } @@ -746,7 +747,7 @@ static int ipc_glb_tplg_comp_new(uint32_t header) reply.rhdr.hdr.cmd = header; reply.rhdr.error = 0; reply.offset = 0; /* TODO: set this up for mmaped components */ - mailbox_hostbox_write(0, &reply, sizeof(reply)); + mailbox_hostbox_write(0, (uint8_t *)&reply, sizeof(reply)); return 1; } @@ -769,7 +770,7 @@ static int ipc_glb_tplg_buffer_new(uint32_t header) reply.rhdr.hdr.cmd = header; reply.rhdr.error = 0; reply.offset = 0; /* TODO: set this up for mmaped components */ - mailbox_hostbox_write(0, &reply, sizeof(reply)); + mailbox_hostbox_write(0, (uint8_t *)&reply, sizeof(reply)); return 1; } @@ -792,7 +793,7 @@ static int ipc_glb_tplg_pipe_new(uint32_t header) reply.rhdr.hdr.cmd = header; reply.rhdr.error = 0; reply.offset = 0; /* TODO: set this up for mmaped components */ - mailbox_hostbox_write(0, &reply, sizeof(reply)); + mailbox_hostbox_write(0, (uint8_t *)&reply, sizeof(reply)); return 1; } diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c index 3114ac1..c5c9108 100644 --- a/src/platform/baytrail/platform.c +++ b/src/platform/baytrail/platform.c @@ -92,7 +92,7 @@ int platform_boot_complete(uint32_t boot_message) { uint64_t outbox = MAILBOX_HOST_OFFSET >> 3; - mailbox_dspbox_write(0, &ready, sizeof(ready)); + mailbox_dspbox_write(0, (uint8_t *)&ready, sizeof(ready)); /* now interrupt host to tell it we are done booting */ shim_write(SHIM_IPCDL, SOF_IPC_FW_READY | outbox); -- 2.14.1

3 4

[Sound-open-firmware] [PATCH] platform: hsw: Add xtensa headers for haswell and broadwell
by Liam Girdwood 22 Jan '18

22 Jan '18

Add xtensa headers for Haswell and Broadwell. Signed-off-by: Liam Girdwood <liam.r.girdwood(a)linux.intel.com> --- src/platform/haswell/include/xtensa/Makefile.am | 1 + .../haswell/include/xtensa/config/Makefile.am | 8 + .../haswell/include/xtensa/config/core-isa-bdw.h | 582 +++++++++++++++++++++ .../haswell/include/xtensa/config/core-isa-hsw.h | 582 +++++++++++++++++++++ .../haswell/include/xtensa/config/core-isa.h | 9 + .../haswell/include/xtensa/config/core-matmap.h | 314 +++++++++++ src/platform/haswell/include/xtensa/config/defs.h | 38 ++ .../haswell/include/xtensa/config/specreg.h | 107 ++++ .../haswell/include/xtensa/config/system.h | 272 ++++++++++ .../haswell/include/xtensa/config/tie-asm.h | 240 +++++++++ src/platform/haswell/include/xtensa/config/tie.h | 170 ++++++ 11 files changed, 2323 insertions(+) create mode 100644 src/platform/haswell/include/xtensa/Makefile.am create mode 100644 src/platform/haswell/include/xtensa/config/Makefile.am create mode 100644 src/platform/haswell/include/xtensa/config/core-isa-bdw.h create mode 100644 src/platform/haswell/include/xtensa/config/core-isa-hsw.h create mode 100644 src/platform/haswell/include/xtensa/config/core-isa.h create mode 100644 src/platform/haswell/include/xtensa/config/core-matmap.h create mode 100644 src/platform/haswell/include/xtensa/config/defs.h create mode 100644 src/platform/haswell/include/xtensa/config/specreg.h create mode 100644 src/platform/haswell/include/xtensa/config/system.h create mode 100644 src/platform/haswell/include/xtensa/config/tie-asm.h create mode 100644 src/platform/haswell/include/xtensa/config/tie.h diff --git a/src/platform/haswell/include/xtensa/Makefile.am b/src/platform/haswell/include/xtensa/Makefile.am new file mode 100644 index 0000000..a85a5bb --- /dev/null +++ b/src/platform/haswell/include/xtensa/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = config diff --git a/src/platform/haswell/include/xtensa/config/Makefile.am b/src/platform/haswell/include/xtensa/config/Makefile.am new file mode 100644 index 0000000..99c21a5 --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/Makefile.am @@ -0,0 +1,8 @@ +noinst_HEADERS = \ + core-isa.h \ + core-matmap.h \ + defs.h \ + specreg.h \ + system.h \ + tie.h \ + tie-asm.h diff --git a/src/platform/haswell/include/xtensa/config/core-isa-bdw.h b/src/platform/haswell/include/xtensa/config/core-isa-bdw.h new file mode 100644 index 0000000..8e562f9 --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/core-isa-bdw.h @@ -0,0 +1,582 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See <xtensa/config/core.h>, which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 0 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ + +/* TODO: we have this option but currently our assembler does not support it */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */ +#define XCHAL_HAVE_HIFI_MINI 0 + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1100002 /* sw version of this header */ + +#define XCHAL_CORE_ID "hifi2ep" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC2B3DBFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1C85483E /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260002 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_2 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 0 +#define XCHAL_DCACHE_WAYS 0 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 8 +#define XCHAL_DCACHE_ACCESS_SIZE 8 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ +#define XCHAL_CA_BITS 4 + +/* Whether MEMCTL register has anything useful */ +#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ + XCHAL_DCACHE_IS_COHERENT || \ + XCHAL_HAVE_ICACHE_DYN_WAYS || \ + XCHAL_HAVE_DCACHE_DYN_WAYS) && \ + (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x00000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x00000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 0x50000 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x00400000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x00400000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 0xA0000 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ + + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x000000FF +#define XCHAL_INTLEVEL2_MASK 0x00000100 +#define XCHAL_INTLEVEL3_MASK 0x00000e00 +#define XCHAL_INTLEVEL4_MASK 0x00001000 +#define XCHAL_INTLEVEL5_MASK 0x00002000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000000FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000001FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00003FFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00003FFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 + +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 + +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 + +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 5 +#define XCHAL_INT14_LEVEL 7 + +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133f +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +//#define XCHAL_INTLEVEL2_NUM 8 +//#define XCHAL_INTLEVEL4_NUM 12 +//#define XCHAL_INTLEVEL5_NUM 13 +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 3.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt<n> pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ +#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ +#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ +#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x00000400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x00000400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x00000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x00000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x00000000 +#define XCHAL_RESET_VECTOR1_PADDR 0x00000000 +#define XCHAL_RESET_VECTOR_VADDR 0x00000000 +#define XCHAL_RESET_VECTOR_PADDR 0x00000000 +#define XCHAL_USER_VECOFS 0x000005c0 +#define XCHAL_USER_VECTOR_VADDR 0x000005c0 +#define XCHAL_USER_VECTOR_PADDR 0x000005c0 +#define XCHAL_KERNEL_VECOFS 0x00000584 +#define XCHAL_KERNEL_VECTOR_VADDR 0x00000584 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00000584 +#define XCHAL_DOUBLEEXC_VECOFS 0x000005fc +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000005fc +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000005fc +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x00000400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00000400 +#define XCHAL_INTLEVEL2_VECOFS 0x00000640 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00000640 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000640 +#define XCHAL_INTLEVEL3_VECOFS 0x0000067c +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0000067c +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0000067c +#define XCHAL_INTLEVEL4_VECOFS 0x000006b8 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000006b8 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000006b8 +#define XCHAL_INTLEVEL5_VECOFS 0x000006f4 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x000006f4 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x000006f4 +#define XCHAL_INTLEVEL6_VECOFS 0x00000730 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00000730 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000730 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x0000076c +#define XCHAL_NMI_VECTOR_VADDR 0x0000076c +#define XCHAL_NMI_VECTOR_PADDR 0x0000076c +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/src/platform/haswell/include/xtensa/config/core-isa-hsw.h b/src/platform/haswell/include/xtensa/config/core-isa-hsw.h new file mode 100644 index 0000000..b25162d --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/core-isa-hsw.h @@ -0,0 +1,582 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See <xtensa/config/core.h>, which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 0 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ + +/* TODO: we have this option but currently our assembler does not support it */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */ +#define XCHAL_HAVE_HIFI_MINI 0 + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1100002 /* sw version of this header */ + +#define XCHAL_CORE_ID "hifi2ep" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC2B3DBFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1C85483E /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260002 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_2 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 0 +#define XCHAL_DCACHE_WAYS 0 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 8 +#define XCHAL_DCACHE_ACCESS_SIZE 8 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ +#define XCHAL_CA_BITS 4 + +/* Whether MEMCTL register has anything useful */ +#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ + XCHAL_DCACHE_IS_COHERENT || \ + XCHAL_HAVE_ICACHE_DYN_WAYS || \ + XCHAL_HAVE_DCACHE_DYN_WAYS) && \ + (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x00000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x00000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 0x50000 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x00400000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x00400000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 0x80000 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ + + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x000000FF +#define XCHAL_INTLEVEL2_MASK 0x00000100 +#define XCHAL_INTLEVEL3_MASK 0x00000e00 +#define XCHAL_INTLEVEL4_MASK 0x00001000 +#define XCHAL_INTLEVEL5_MASK 0x00002000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000000FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000001FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00003FFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00003FFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 + +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 + +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 + +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 5 +#define XCHAL_INT14_LEVEL 7 + +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133f +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +//#define XCHAL_INTLEVEL2_NUM 8 +//#define XCHAL_INTLEVEL4_NUM 12 +//#define XCHAL_INTLEVEL5_NUM 13 +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 3.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt<n> pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ +#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ +#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ +#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x00000400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x00000400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x00000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x00000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x00000000 +#define XCHAL_RESET_VECTOR1_PADDR 0x00000000 +#define XCHAL_RESET_VECTOR_VADDR 0x00000000 +#define XCHAL_RESET_VECTOR_PADDR 0x00000000 +#define XCHAL_USER_VECOFS 0x000005c0 +#define XCHAL_USER_VECTOR_VADDR 0x000005c0 +#define XCHAL_USER_VECTOR_PADDR 0x000005c0 +#define XCHAL_KERNEL_VECOFS 0x00000584 +#define XCHAL_KERNEL_VECTOR_VADDR 0x00000584 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00000584 +#define XCHAL_DOUBLEEXC_VECOFS 0x000005fc +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000005fc +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000005fc +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x00000400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00000400 +#define XCHAL_INTLEVEL2_VECOFS 0x00000640 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00000640 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000640 +#define XCHAL_INTLEVEL3_VECOFS 0x0000067c +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0000067c +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0000067c +#define XCHAL_INTLEVEL4_VECOFS 0x000006b8 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000006b8 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000006b8 +#define XCHAL_INTLEVEL5_VECOFS 0x000006f4 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x000006f4 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x000006f4 +#define XCHAL_INTLEVEL6_VECOFS 0x00000730 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00000730 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000730 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x0000076c +#define XCHAL_NMI_VECTOR_VADDR 0x0000076c +#define XCHAL_NMI_VECTOR_PADDR 0x0000076c +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/src/platform/haswell/include/xtensa/config/core-isa.h b/src/platform/haswell/include/xtensa/config/core-isa.h new file mode 100644 index 0000000..00a8b7d --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/core-isa.h @@ -0,0 +1,9 @@ +#include <config.h> + +#ifdef CONFIG_HASWELL +#include <xtensa/config/core-isa-hsw.h> +#elif CONFIG_BROADWELL +#include <xtensa/config/core-isa-bdw.h> +#else +#error "No ISA configuration selected" +#endif diff --git a/src/platform/haswell/include/xtensa/config/core-matmap.h b/src/platform/haswell/include/xtensa/config/core-matmap.h new file mode 100644 index 0000000..5c6fffe --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/core-matmap.h @@ -0,0 +1,314 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ + + +/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ +#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION +#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_ISOLATE XCHAL_SEP \ + XTHAL_LAM_EXCEPTION +#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_WRITEBACK XCHAL_SEP \ + XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_ISOLATE XCHAL_SEP \ + XTHAL_SAM_EXCEPTION + + +/* + * Specific encoded cache attribute values of general interest. + * If a specific cache mode is not available, the closest available + * one is returned instead (eg. writethru instead of writeback, + * bypass instead of writethru). + */ +#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ +#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */ +#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ +#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */ +#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */ +#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ +#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* + * General notes on MMU parameters. + * + * Terminology: + * ASID = address-space ID (acts as an "extension" of virtual addresses) + * VPN = virtual page number + * PPN = physical page number + * CA = encoded cache attribute (access modes) + * TLB = translation look-aside buffer (term is stretched somewhat here) + * I = instruction (fetch accesses) + * D = data (load and store accesses) + * way = each TLB (ITLB and DTLB) consists of a number of "ways" + * that simultaneously match the virtual address of an access; + * a TLB successfully translates a virtual address if exactly + * one way matches the vaddr; if none match, it is a miss; + * if multiple match, one gets a "multihit" exception; + * each way can be independently configured in terms of number of + * entries, page sizes, which fields are writable or constant, etc. + * set = group of contiguous ways with exactly identical parameters + * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE + * from the page table and storing it in one of the auto-refill ways; + * if this PTE load also misses, a miss exception is posted for s/w. + * min-wired = a "min-wired" way can be used to map a single (minimum-sized) + * page arbitrarily under program control; it has a single entry, + * is non-auto-refill (some other way(s) must be auto-refill), + * all its fields (VPN, PPN, ASID, CA) are all writable, and it + * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current + * restriction is that this be the only page size it supports). + * + * TLB way entries are virtually indexed. + * TLB ways that support multiple page sizes: + * - must have all writable VPN and PPN fields; + * - can only use one page size at any given time (eg. setup at startup), + * selected by the respective ITLBCFG or DTLBCFG special register, + * whose bits n*4+3 .. n*4 index the list of page sizes for way n + * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); + * this list may be sparse for auto-refill ways because auto-refill + * ways have independent lists of supported page sizes sharing a + * common encoding with PTE entries; the encoding is the index into + * this list; unsupported sizes for a given way are zero in the list; + * selecting unsupported sizes results in undefined hardware behaviour; + * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). + */ + +#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ +#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ +#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ +#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ +#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ + + +/*** Instruction TLB: ***/ + +#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_ITLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* ITLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 + + +/*** Data TLB: ***/ + +#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_DTLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* DTLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 + + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/src/platform/haswell/include/xtensa/config/defs.h b/src/platform/haswell/include/xtensa/config/defs.h new file mode 100644 index 0000000..b695e59 --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/defs.h @@ -0,0 +1,38 @@ +/* Definitions for Xtensa instructions, types, and protos. */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 2003-2004 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* NOTE: This file exists only for backward compatibility with T1050 + and earlier Xtensa releases. It includes only a subset of the + available header files. */ + +#ifndef _XTENSA_BASE_HEADER +#define _XTENSA_BASE_HEADER + +#ifdef __XTENSA__ + +#include <xtensa/tie/xt_core.h> +#include <xtensa/tie/xt_misc.h> +#include <xtensa/tie/xt_booleans.h> + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_BASE_HEADER */ diff --git a/src/platform/haswell/include/xtensa/config/specreg.h b/src/platform/haswell/include/xtensa/config/specreg.h new file mode 100644 index 0000000..89bfe16 --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/specreg.h @@ -0,0 +1,107 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include <xtensa/corebits.h> + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define SCOMPARE1 12 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define IBREAKENABLE 96 +#define ATOMCTL 99 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define EPC_7 183 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EPS_7 199 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define EXCSAVE_7 215 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ + diff --git a/src/platform/haswell/include/xtensa/config/system.h b/src/platform/haswell/include/xtensa/config/system.h new file mode 100644 index 0000000..147346a --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/system.h @@ -0,0 +1,272 @@ +/* + * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration + * + * NOTE: The location and contents of this file are highly subject to change. + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * The HAL itself has historically included this file in some instances, + * but this is not appropriate either, because the HAL is meant to be + * core-specific but system independent. + */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 2000-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_SYSTEM_H +#define XTENSA_CONFIG_SYSTEM_H + +/*#include <xtensa/hal.h>*/ + + + +/*---------------------------------------------------------------------- + CONFIGURED SOFTWARE OPTIONS + ----------------------------------------------------------------------*/ + +#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#define XSHAL_ABI XTHAL_ABI_CALL0 /* (sw-only option, selected ABI) */ +/* The above maps to one of the following constants: */ +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 +/* Alternatives: */ +/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ +/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ + +#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ +/* The above maps to one of the following constants: */ +#define XTHAL_CLIB_NEWLIB 0 +#define XTHAL_CLIB_UCLIBC 1 +#define XTHAL_CLIB_XCLIB 2 +/* Alternatives: */ +/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ +/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ +/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ + +#define XSHAL_USE_FLOATING_POINT 1 + +#define XSHAL_FLOATING_POINT_ABI 0 + +/*---------------------------------------------------------------------- + DEVICE ADDRESSES + ----------------------------------------------------------------------*/ + +/* + * Strange place to find these, but the configuration GUI + * allows moving these around to account for various core + * configurations. Specific boards (and their BSP software) + * will have specific meanings for these components. + */ + +/* I/O Block areas: */ +#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 + +#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 + +/* System ROM: */ +#define XSHAL_ROM_VADDR 0x50000000 +#define XSHAL_ROM_PADDR 0x50000000 +#define XSHAL_ROM_SIZE 0x01000000 +/* Largest available area (free of vectors): */ +#define XSHAL_ROM_AVAIL_VADDR 0x50000300 +#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00 + +/* System RAM: */ +#define XSHAL_RAM_VADDR 0x60000000 +#define XSHAL_RAM_PADDR 0x60000000 +#define XSHAL_RAM_VSIZE 0x04000000 +#define XSHAL_RAM_PSIZE 0x04000000 +#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE +/* Largest available area (free of vectors): */ +#define XSHAL_RAM_AVAIL_VADDR 0x60000400 +#define XSHAL_RAM_AVAIL_VSIZE 0x03FFFC00 + +/* + * Shadow system RAM (same device as system RAM, at different address). + * (Emulation boards need this for the SONIC Ethernet driver + * when data caches are configured for writeback mode.) + * NOTE: on full MMU configs, this points to the BYPASS virtual address + * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual + * addresses are viewed through the BYPASS static map rather than + * the CACHED static map. + */ +#define XSHAL_RAM_BYPASS_VADDR 0xA0000000 +#define XSHAL_RAM_BYPASS_PADDR 0xA0000000 +#define XSHAL_RAM_BYPASS_PSIZE 0x04000000 + +/* Alternate system RAM (different device than system RAM): */ +/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ +/*#define XSHAL_ALTRAM_SIZE ...not configured...*/ + +/* Some available location in which to place devices in a simulation (eg. XTMP): */ +#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 +#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 +#define XSHAL_SIMIO_PADDR 0xC0000000 +#define XSHAL_SIMIO_SIZE 0x20000000 + + +/*---------------------------------------------------------------------- + * For use by reference testbench exit and diagnostic routines. + */ +#define XSHAL_MAGIC_EXIT 0x0 + +/*---------------------------------------------------------------------- + * DEVICE-ADDRESS DEPENDENT... + * + * Values written to CACHEATTR special register (or its equivalent) + * to enable and disable caches in various modes. + *----------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + BACKWARD COMPATIBILITY ... + ----------------------------------------------------------------------*/ + +/* + * NOTE: the following two macros are DEPRECATED. Use the latter + * board-specific macros instead, which are specially tuned for the + * particular target environments' memory maps. + */ +#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ +#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ + +/*---------------------------------------------------------------------- + GENERIC + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains a system (PIF) RAM, + * system (PIF) ROM, local memory, or XLMI. */ + +/* These set any unused 512MB region to cache-BYPASS attribute: */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22224442 /* enable caches in write-back mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */ +#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ +#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set any unused 512MB region to ILLEGAL attribute: */ +#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF444F /* enable caches in write-back mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */ +#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */ +#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */ +#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch + * NULL-pointer dereference bugs; all other unused 512MB regions are set + * to cache-BYPASS attribute: */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222444F /* enable caches in write-back mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */ +#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ +#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/*---------------------------------------------------------------------- + ISS (Instruction Set Simulator) SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For now, ISS defaults to the TRAPNULL settings: */ +#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK +#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC +#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU +#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS +#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +#define XSHAL_ISS_PIPE_REGIONS 0 +#define XSHAL_ISS_SDRAM_REGIONS 0 + + +/*---------------------------------------------------------------------- + XT2000 BOARD SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains any system RAM, + * system ROM, local memory, XLMI, or other XT2000 board device or memory. + * Regions containing devices are forced to cache-BYPASS mode regardless + * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ + +/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ +#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22444F /* enable caches in write-back mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */ +#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */ +#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ +#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ +#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */ + + +/*---------------------------------------------------------------------- + VECTOR INFO AND SIZES + ----------------------------------------------------------------------*/ + +#define XSHAL_VECTORS_PACKED 0 +#define XSHAL_STATIC_VECTOR_SELECT 0 +#define XSHAL_RESET_VECTOR_VADDR 0x50000000 +#define XSHAL_RESET_VECTOR_PADDR 0x50000000 + +/* + * Sizes allocated to vectors by the system (memory map) configuration. + * These sizes are constrained by core configuration (eg. one vector's + * code cannot overflow into another vector) but are dependent on the + * system or board (or LSP) memory map configuration. + * + * Whether or not each vector happens to be in a system ROM is also + * a system configuration matter, sometimes useful, included here also: + */ +#define XSHAL_RESET_VECTOR_SIZE 0x00000300 +#define XSHAL_RESET_VECTOR_ISROM 1 +#define XSHAL_USER_VECTOR_SIZE 0x00000038 +#define XSHAL_USER_VECTOR_ISROM 0 +#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 +#define XSHAL_KERNEL_VECTOR_ISROM 0 +#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 +#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 +#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 +#define XSHAL_WINDOW_VECTORS_ISROM 0 +#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL5_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL6_VECTOR_ISROM 0 +#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE +#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM +#define XSHAL_NMI_VECTOR_SIZE 0x00000038 +#define XSHAL_NMI_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE + + +#endif /*XTENSA_CONFIG_SYSTEM_H*/ + diff --git a/src/platform/haswell/include/xtensa/config/tie-asm.h b/src/platform/haswell/include/xtensa/config/tie-asm.h new file mode 100644 index 0000000..d7140f8 --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/tie-asm.h @@ -0,0 +1,240 @@ +/* + * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file contains assembly-language definitions (assembly + macros, etc.) for this specific Xtensa processor's TIE extensions + and options. It is customized to this Xtensa processor configuration. + + Copyright (c) 1999-2015 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + + + /* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if <continue> is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in <select>, space for + * the corresponding registers is skipped without doing any store. + */ + .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + rsr.BR \at1 // boolean option + s32i \at1, \ptr, .Lxchal_ofs_+0 + rsr.SCOMPARE1 \at1 // conditional store option + s32i \at1, \ptr, .Lxchal_ofs_+4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + .endm // xchal_ncp_store + + /* + * Macro to load all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger load sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to load. Defaults to next available space + * (or 0 if <continue> is 0). + * select Select what category(ies) of registers to load, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in <select>, space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.BR \at1 // boolean option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.SCOMPARE1 \at1 // conditional store option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + .endm // xchal_ncp_load + + +#define XCHAL_NCP_NUM_ATMPS 1 + + /* + * Macro to store the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ +#define xchal_cp_AudioEngineLX_store xchal_cp1_store + .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + rur.AE_OVF_SAR \at1 // ureg 240 + s32i \at1, \ptr, .Lxchal_ofs_+0 + rur.AE_BITHEAD \at1 // ureg 241 + s32i \at1, \ptr, .Lxchal_ofs_+4 + rur.AE_TS_FTS_BU_BP \at1 // ureg 242 + s32i \at1, \ptr, .Lxchal_ofs_+8 + rur.AE_SD_NO \at1 // ureg 243 + s32i \at1, \ptr, .Lxchal_ofs_+12 + ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+16 + ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+24 + ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+32 + ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+40 + ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+48 + ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+0 + ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+8 + ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+16 + ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+24 + ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+32 + ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+40 + .set .Lxchal_pofs_, .Lxchal_pofs_ + 64 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 48 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 + .endif + .endm // xchal_cp1_store + + /* + * Macro to load the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ +#define xchal_cp_AudioEngineLX_load xchal_cp1_load + .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.AE_OVF_SAR \at1 // ureg 240 + l32i \at1, \ptr, .Lxchal_ofs_+4 + wur.AE_BITHEAD \at1 // ureg 241 + l32i \at1, \ptr, .Lxchal_ofs_+8 + wur.AE_TS_FTS_BU_BP \at1 // ureg 242 + l32i \at1, \ptr, .Lxchal_ofs_+12 + wur.AE_SD_NO \at1 // ureg 243 + ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+16 + ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+24 + ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+32 + ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+40 + ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+48 + ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+0 + ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+8 + addi \ptr, \ptr, 16 + ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0 + ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8 + ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16 + ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24 + .set .Lxchal_pofs_, .Lxchal_pofs_ + 80 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 + .endif + .endm // xchal_cp1_load + +#define XCHAL_CP1_NUM_ATMPS 1 +#define XCHAL_SA_NUM_ATMPS 1 + + /* Empty macros for unconfigured coprocessors: */ + .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/src/platform/haswell/include/xtensa/config/tie.h b/src/platform/haswell/include/xtensa/config/tie.h new file mode 100644 index 0000000..3c63812 --- /dev/null +++ b/src/platform/haswell/include/xtensa/config/tie.h @@ -0,0 +1,170 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file describes this specific Xtensa processor's TIE extensions + that extend basic Xtensa core functionality. It is customized to this + Xtensa processor configuration. + + Copyright (c) 1999-2015 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP1_NAME "AudioEngineLX" +#define XCHAL_CP1_IDENT AudioEngineLX +#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */ +#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ +#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 8 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 2 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 16 +#define XCHAL_CP1_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0) + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 + +#endif /*_XTENSA_CORE_TIE_H*/ + -- 2.14.1

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[Sound-open-firmware] [PATCH v3 1/2] host/dai: update pointer cast to support 64-bit library build
by Ranjani Sridharan 19 Jan '18

19 Jan '18

This patch updates the pointer cast in host/dai for library build support for 64-bit arch Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> --- src/audio/dai.c | 4 ++-- src/audio/host.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/audio/dai.c b/src/audio/dai.c index b7ad1b4..f3c73b3 100644 --- a/src/audio/dai.c +++ b/src/audio/dai.c @@ -293,7 +293,7 @@ static int dai_playback_params(struct comp_dev *dev) goto err_unwind; elem->size = dd->period_bytes; - elem->src = (uint32_t)(dma_buffer->r_ptr) + + elem->src = (uintptr_t)(dma_buffer->r_ptr) + i * dd->period_bytes; elem->dest = dai_fifo(dd->dai, SOF_IPC_STREAM_PLAYBACK); @@ -360,7 +360,7 @@ static int dai_capture_params(struct comp_dev *dev) goto err_unwind; elem->size = dd->period_bytes; - elem->dest = (uint32_t)(dma_buffer->w_ptr) + + elem->dest = (uintptr_t)(dma_buffer->w_ptr) + i * dd->period_bytes; elem->src = dai_fifo(dd->dai, SOF_IPC_STREAM_CAPTURE); list_item_append(&elem->list, &config->elem_list); diff --git a/src/audio/host.c b/src/audio/host.c index 7cb62ef..67472e1 100644 --- a/src/audio/host.c +++ b/src/audio/host.c @@ -325,10 +325,10 @@ static int create_local_elems(struct comp_dev *dev) goto unwind; if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) - e->dest = (uint32_t)(hd->dma_buffer->addr) + + e->dest = (uintptr_t)(hd->dma_buffer->addr) + i * hd->period_bytes; else - e->src = (uint32_t)(hd->dma_buffer->addr) + + e->src = (uintptr_t)(hd->dma_buffer->addr) + i * hd->period_bytes; e->size = hd->period_bytes; -- 2.11.0

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