On Oct 2, 2015, at 08:25 , Caleb Crome caleb@crome.org wrote:
Sent from my iPhone
On Oct 2, 2015, at 2:55 AM, Rick Mann rmann@latencyzero.com wrote:
It's pretty exactly 24.00 MHz, ±0.02 MHz.
Oh, it's coming back to me. Perhaps 24 MHz is all the pin can put out. So if you set your sysclk to 24 MHz, then the PLL will get set to the right thing, and give you the right clocks.
My board has its own clock, so I don't actually use the mclk from the bbb.
Well, the other Audio Cape (from Circuitco) seems to get by specifying 12 MHz. I'll try setting it to 24, but it seems weird that they can use 12 and I can't. Maybe they can only use 12 in the 3.8.x kernel, and something broke since then?
Also, you can use DSP mode for stereo just fine. I don't think you need to worry about that at all as long as both sides recognize the format.
Good to know.