[alsa-devel] [Q] ASoC: What's the real meaning of SND_SOC_DAIFMT_NB_NF?

javier Martin javier.martin at vista-silicon.com
Fri Feb 24 08:53:11 CET 2012

On 23 February 2012 17:14, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Thu, Feb 23, 2012 at 04:58:09PM +0100, javier Martin wrote:
>> So, let's see if I understood properly. If I want to configure the
>> i.MX SSI into standard, I2S format I should do:
>> snd_soc_dai_set_fmt(cpu_dai, dai_format);
> Yes.
>> While initially TFSI bit is set because of I2S flag, it is then
>> cleared because of the NB_NF.
>> Does this mean this is a bug then? If it is, I would gladly fix it but
> I've no idea what any of the register settings mean here...

If TFSI bit is 1, frame clock is active high.
If TFSI bit is 0, frame clock is active low.

In the piece of code I've shown to you, when someone configures
(SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF) he's really selecting an
active high frame clock when the standard says just the opposite
(wm8974 datasheet p50).

>> there is at least one platform relying on this misleading behavior
>> that I can't test:
>> http://lxr.linux.no/#linux+v3.2.7/sound/soc/imx/wm1133-ev1.c#L81
> That was correct at the time it was written, though the code has changed
> since then and I don't know when it was last retested.  Of course
> depending on the signal it may interoperate well even if the setup isn't
> actually correct.  I'd just fix the driver and if it works for yours
> it's probably OK for that board too.

It is not one but two boards that are affected:

If I fixed the bug in the SSI I would break both of them, since I
would be changing frame clock polarity.

Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60

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