[alsa-devel] SAIF configuration on imx28
stefan.george87 at gmail.com
Thu Aug 23 09:13:11 CEST 2012
2012/8/23 Dong Aisheng <b29396 at freescale.com>
> On Thu, Aug 23, 2012 at 02:41:30PM +0800, George Stefan wrote:
> > /*set the saif clk mux, saif0/saif1 both use saif0 clk*/
> > __raw_writel(BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(0x0), \
> Should this be 0x2 if both saif0 and saif1 are using saif0 clk?
> > IO_ADDRESS(DIGCTL_PHYS_ADDR) + HW_DIGCTL_CTRL);
> > Using this configuration i am not able to receive IRQs from DMA and i
> > think the reason
> > is that SAIF is not receiving the CLK.
> > What do you think?
> > Thanks,
> > George.
> Dong Aisheng
> Yes, it should be 0x2 if they are using saif0 clk. but it they are using
the CLK from an external device
which is master, i think that they should use an independent clock.
"In slave clocking mode, the SAIF configures the BITCLK and LRCLK pins as
the off-chip codec is responsible for driving both clocks to the
SAIF"(imx28 reference manual)
0x0 - DIRECT — SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
clock pins selected for
SAIF1 input clocks.
Am i interpreting this in the wrong way?
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