[alsa-devel] [PATCH 1/2 v2] ASoC: soc-cache: block based rbtree compression

Mark Brown broonie at opensource.wolfsonmicro.com
Tue May 3 17:55:59 CEST 2011

On Tue, May 03, 2011 at 05:54:21PM +0200, Takashi Iwai wrote:
> Mark Brown wrote:

> > We'll want to do that as well, but we still want the actual data
> > structure underneath to support that.  Since most register maps that
> > benefit from compression are also sparse rbtree is the common case for
> > getting a win from this.

> Hm, but iteration in the sorted order is pretty easy and cheap in
> rb-tree structure.  It's not necessarily to be exported in an array.

I2C and SPI controllers don't typically do gather terribly well, though,
and there is a win from reducing the number of rbtree nodes anyway.

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