[alsa-devel] [PATCH 1/2 v2] ASoC: soc-cache: block based rbtree compression

Takashi Iwai tiwai at suse.de
Tue May 3 18:06:57 CEST 2011

At Tue, 3 May 2011 16:55:59 +0100,
Mark Brown wrote:
> On Tue, May 03, 2011 at 05:54:21PM +0200, Takashi Iwai wrote:
> > Mark Brown wrote:
> > > We'll want to do that as well, but we still want the actual data
> > > structure underneath to support that.  Since most register maps that
> > > benefit from compression are also sparse rbtree is the common case for
> > > getting a win from this.
> > Hm, but iteration in the sorted order is pretty easy and cheap in
> > rb-tree structure.  It's not necessarily to be exported in an array.
> I2C and SPI controllers don't typically do gather terribly well, though,
> and there is a win from reducing the number of rbtree nodes anyway.

That's true.  But it may also result in holes.
And, this gives more code complexity.  That's my point.

That being said, I see the usefulness of this change, too.  But, also
interested in a bit more quantitative investigation about its gain,


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