[alsa-devel] [PATCH 1/2 v2] ASoC: soc-cache: block based rbtree compression

Takashi Iwai tiwai at suse.de
Tue May 3 15:18:47 CEST 2011

At Tue, 3 May 2011 14:02:59 +0100,
Mark Brown wrote:
> On Tue, May 03, 2011 at 02:25:12PM +0200, Takashi Iwai wrote:
> > So, this is the preliminary work for implementing the bulk I/O?
> > If so, it's worth to consider once whether implementing in the rb-tree
> > cache code is the right choice.  Can it be implemented in the cache
> > management core, since you'll need an API anyway for getting the bulk
> > register array via cache manager?
> The whole point of the caches is to be responsible for abstracting out
> the in-memory layout of the data.  The core already provides information
> that the caches can use about the register format and what registers are
> present.

Yes, but the core doesn't give how linearly it's stored although its
storing order influences on the bulk I/O behavior.  In other words,
the patches try to put registers partly linearly in magical blocks.
But it doesn't guarantee whether the cache block is aligned to what
hardware prefers since it's behind the scene.


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