[alsa-devel] [PATCH 10/11] ASoC: tegra: Harmony machine support

[Stephen Warren]

Mark Brown wrote:
> 
> On Wed, Dec 22, 2010 at 05:13:20PM -0800, Stephen Warren wrote:
> > As an aside, I was looking through the Tegra documentation, and in fact
> > the cdev1 pin (which feeds the codec MCLK) can be sourced from pll_a,
> > i.e. the same clock domain as the I2S bit clock. The existing kernel
> > clock driver is simply missing the code to set this up.
> 
> OK, that's a better solution anyway as it uses less power - the only
> reason to use the FLL if you can provide a good MCLK directly would be
> to allow the CODEC to clock itself with the CPU completely off for jack
> or button detection but that is fairly unusual (usually jack detection
> wouldn't be a wake event).
> 
> > Again unfortunately, implementing and doing that doesn't solve the noise
> > issue. I suppose I need to start probing the pins with a 'scope/analyzer
> > to make sure of what's really coming out of Tegra. Pity they're so small
> > and have no test points:-(
> 
> Does providing a good MCLK have any impact at all on the noise levels?
> It might be interesting to try having the CODEC master the I2S bus - it
> might not change anything, but it sometimes shows up if one of the clock
> lines is misconfigured.

Having the codec be master of the bit and frame clocks appears to completely
solve the noise issues. I do notice that different sample rates play the same
audio at different pitches though, so something is still wrong, but it's most
likely to be incorrect codec MCLK input right now; I'll keep investigating...

Thanks.

-- 
nvpublic