[alsa-devel] USB asynchronous mode feedback format

Alex Lee lee188 at singnet.com.sg
Thu Oct 14 17:33:40 CEST 2010

> Would you agree that the data (this time blue channel) is delayed too much? 
> Looks like it's at least 2 cycles behind the LRCK toggle.
> Would it be possible that this is the reason for the DAC not understanding the 
> data?

Yes it is delayed 2-3 cycles (should be only 1 cycle).  Also, as I
pointed out earlier, data is valid on falling edge of clock.  Should be
rising edge according to i2S.


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